| 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
|---|---|
| 2 | |* *| |
| 3 | |* Target Instruction Enum Values and Descriptors *| |
| 4 | |* *| |
| 5 | |* Automatically generated file, do not edit! *| |
| 6 | |* *| |
| 7 | \*===----------------------------------------------------------------------===*/ |
| 8 | |
| 9 | #ifdef GET_INSTRINFO_ENUM |
| 10 | #undef GET_INSTRINFO_ENUM |
| 11 | |
| 12 | namespace llvm::WebAssembly { |
| 13 | |
| 14 | enum { |
| 15 | PHI = 0, // Target.td:1206 |
| 16 | INLINEASM = 1, // Target.td:1212 |
| 17 | INLINEASM_BR = 2, // Target.td:1218 |
| 18 | CFI_INSTRUCTION = 3, // Target.td:1227 |
| 19 | EH_LABEL = 4, // Target.td:1236 |
| 20 | GC_LABEL = 5, // Target.td:1245 |
| 21 | ANNOTATION_LABEL = 6, // Target.td:1254 |
| 22 | KILL = 7, // Target.td:1262 |
| 23 | EXTRACT_SUBREG = 8, // Target.td:1269 |
| 24 | INSERT_SUBREG = 9, // Target.td:1275 |
| 25 | IMPLICIT_DEF = 10, // Target.td:1282 |
| 26 | INIT_UNDEF = 11, // Target.td:1291 |
| 27 | SUBREG_TO_REG = 12, // Target.td:1298 |
| 28 | COPY_TO_REGCLASS = 13, // Target.td:1304 |
| 29 | DBG_VALUE = 14, // Target.td:1311 |
| 30 | DBG_VALUE_LIST = 15, // Target.td:1318 |
| 31 | DBG_INSTR_REF = 16, // Target.td:1325 |
| 32 | DBG_PHI = 17, // Target.td:1332 |
| 33 | DBG_LABEL = 18, // Target.td:1339 |
| 34 | REG_SEQUENCE = 19, // Target.td:1346 |
| 35 | COPY = 20, // Target.td:1353 |
| 36 | COPY_LANEMASK = 21, // Target.td:1361 |
| 37 | BUNDLE = 22, // Target.td:1368 |
| 38 | LIFETIME_START = 23, // Target.td:1374 |
| 39 | LIFETIME_END = 24, // Target.td:1381 |
| 40 | PSEUDO_PROBE = 25, // Target.td:1388 |
| 41 | ARITH_FENCE = 26, // Target.td:1395 |
| 42 | STACKMAP = 27, // Target.td:1404 |
| 43 | FENTRY_CALL = 28, // Target.td:1539 |
| 44 | PATCHPOINT = 29, // Target.td:1412 |
| 45 | LOAD_STACK_GUARD = 30, // Target.td:1430 |
| 46 | PREALLOCATED_SETUP = 31, // Target.td:1438 |
| 47 | PREALLOCATED_ARG = 32, // Target.td:1444 |
| 48 | STATEPOINT = 33, // Target.td:1421 |
| 49 | LOCAL_ESCAPE = 34, // Target.td:1450 |
| 50 | FAULTING_OP = 35, // Target.td:1459 |
| 51 | PATCHABLE_OP = 36, // Target.td:1479 |
| 52 | PATCHABLE_FUNCTION_ENTER = 37, // Target.td:1487 |
| 53 | PATCHABLE_RET = 38, // Target.td:1494 |
| 54 | PATCHABLE_FUNCTION_EXIT = 39, // Target.td:1503 |
| 55 | PATCHABLE_TAIL_CALL = 40, // Target.td:1511 |
| 56 | PATCHABLE_EVENT_CALL = 41, // Target.td:1519 |
| 57 | PATCHABLE_TYPED_EVENT_CALL = 42, // Target.td:1529 |
| 58 | ICALL_BRANCH_FUNNEL = 43, // Target.td:1549 |
| 59 | FAKE_USE = 44, // Target.td:1469 |
| 60 | MEMBARRIER = 45, // Target.td:1555 |
| 61 | JUMP_TABLE_DEBUG_INFO = 46, // Target.td:1563 |
| 62 | RELOC_NONE = 47, // Target.td:1571 |
| 63 | CONVERGENCECTRL_ENTRY = 48, // Target.td:1583 |
| 64 | CONVERGENCECTRL_ANCHOR = 49, // Target.td:1579 |
| 65 | CONVERGENCECTRL_LOOP = 50, // Target.td:1587 |
| 66 | CONVERGENCECTRL_GLUE = 51, // Target.td:1591 |
| 67 | G_ASSERT_SEXT = 52, // GenericOpcodes.td:1955 |
| 68 | G_ASSERT_ZEXT = 53, // GenericOpcodes.td:1947 |
| 69 | G_ASSERT_ALIGN = 54, // GenericOpcodes.td:1962 |
| 70 | G_ADD = 55, // GenericOpcodes.td:308 |
| 71 | G_SUB = 56, // GenericOpcodes.td:316 |
| 72 | G_MUL = 57, // GenericOpcodes.td:324 |
| 73 | G_SDIV = 58, // GenericOpcodes.td:332 |
| 74 | G_UDIV = 59, // GenericOpcodes.td:340 |
| 75 | G_SREM = 60, // GenericOpcodes.td:348 |
| 76 | G_UREM = 61, // GenericOpcodes.td:356 |
| 77 | G_SDIVREM = 62, // GenericOpcodes.td:364 |
| 78 | G_UDIVREM = 63, // GenericOpcodes.td:372 |
| 79 | G_AND = 64, // GenericOpcodes.td:380 |
| 80 | G_OR = 65, // GenericOpcodes.td:388 |
| 81 | G_XOR = 66, // GenericOpcodes.td:396 |
| 82 | G_ABDS = 67, // GenericOpcodes.td:425 |
| 83 | G_ABDU = 68, // GenericOpcodes.td:433 |
| 84 | G_UAVGFLOOR = 69, // GenericOpcodes.td:441 |
| 85 | G_UAVGCEIL = 70, // GenericOpcodes.td:448 |
| 86 | G_SAVGFLOOR = 71, // GenericOpcodes.td:455 |
| 87 | G_SAVGCEIL = 72, // GenericOpcodes.td:462 |
| 88 | G_IMPLICIT_DEF = 73, // GenericOpcodes.td:111 |
| 89 | G_PHI = 74, // GenericOpcodes.td:118 |
| 90 | G_FRAME_INDEX = 75, // GenericOpcodes.td:125 |
| 91 | G_GLOBAL_VALUE = 76, // GenericOpcodes.td:131 |
| 92 | G_PTRAUTH_GLOBAL_VALUE = 77, // GenericOpcodes.td:137 |
| 93 | G_CONSTANT_POOL = 78, // GenericOpcodes.td:143 |
| 94 | G_EXTRACT = 79, // GenericOpcodes.td:1540 |
| 95 | G_UNMERGE_VALUES = 80, // GenericOpcodes.td:1553 |
| 96 | G_INSERT = 81, // GenericOpcodes.td:1562 |
| 97 | G_MERGE_VALUES = 82, // GenericOpcodes.td:1572 |
| 98 | G_BUILD_VECTOR = 83, // GenericOpcodes.td:1592 |
| 99 | G_BUILD_VECTOR_TRUNC = 84, // GenericOpcodes.td:1602 |
| 100 | G_CONCAT_VECTORS = 85, // GenericOpcodes.td:1609 |
| 101 | G_PTRTOINT = 86, // GenericOpcodes.td:155 |
| 102 | G_INTTOPTR = 87, // GenericOpcodes.td:149 |
| 103 | G_BITCAST = 88, // GenericOpcodes.td:161 |
| 104 | G_FREEZE = 89, // GenericOpcodes.td:284 |
| 105 | G_CONSTANT_FOLD_BARRIER = 90, // GenericOpcodes.td:1969 |
| 106 | G_INTRINSIC_FPTRUNC_ROUND = 91, // GenericOpcodes.td:1298 |
| 107 | G_INTRINSIC_TRUNC = 92, // GenericOpcodes.td:1304 |
| 108 | G_INTRINSIC_ROUND = 93, // GenericOpcodes.td:1310 |
| 109 | G_INTRINSIC_LRINT = 94, // GenericOpcodes.td:1316 |
| 110 | G_INTRINSIC_LLRINT = 95, // GenericOpcodes.td:1322 |
| 111 | G_INTRINSIC_ROUNDEVEN = 96, // GenericOpcodes.td:1328 |
| 112 | G_READCYCLECOUNTER = 97, // GenericOpcodes.td:1334 |
| 113 | G_READSTEADYCOUNTER = 98, // GenericOpcodes.td:1340 |
| 114 | G_LOAD = 99, // GenericOpcodes.td:1367 |
| 115 | G_SEXTLOAD = 100, // GenericOpcodes.td:1376 |
| 116 | G_ZEXTLOAD = 101, // GenericOpcodes.td:1384 |
| 117 | G_FPEXTLOAD = 102, // GenericOpcodes.td:1393 |
| 118 | G_INDEXED_LOAD = 103, // GenericOpcodes.td:1403 |
| 119 | G_INDEXED_SEXTLOAD = 104, // GenericOpcodes.td:1412 |
| 120 | G_INDEXED_ZEXTLOAD = 105, // GenericOpcodes.td:1420 |
| 121 | G_STORE = 106, // GenericOpcodes.td:1428 |
| 122 | G_FPTRUNCSTORE = 107, // GenericOpcodes.td:1438 |
| 123 | G_INDEXED_STORE = 108, // GenericOpcodes.td:1446 |
| 124 | G_ATOMIC_CMPXCHG_WITH_SUCCESS = 109, // GenericOpcodes.td:1457 |
| 125 | G_ATOMIC_CMPXCHG = 110, // GenericOpcodes.td:1468 |
| 126 | G_ATOMICRMW_XCHG = 111, // GenericOpcodes.td:1488 |
| 127 | G_ATOMICRMW_ADD = 112, // GenericOpcodes.td:1489 |
| 128 | G_ATOMICRMW_SUB = 113, // GenericOpcodes.td:1490 |
| 129 | G_ATOMICRMW_AND = 114, // GenericOpcodes.td:1491 |
| 130 | G_ATOMICRMW_NAND = 115, // GenericOpcodes.td:1492 |
| 131 | G_ATOMICRMW_OR = 116, // GenericOpcodes.td:1493 |
| 132 | G_ATOMICRMW_XOR = 117, // GenericOpcodes.td:1494 |
| 133 | G_ATOMICRMW_MAX = 118, // GenericOpcodes.td:1495 |
| 134 | G_ATOMICRMW_MIN = 119, // GenericOpcodes.td:1496 |
| 135 | G_ATOMICRMW_UMAX = 120, // GenericOpcodes.td:1497 |
| 136 | G_ATOMICRMW_UMIN = 121, // GenericOpcodes.td:1498 |
| 137 | G_ATOMICRMW_FADD = 122, // GenericOpcodes.td:1509 |
| 138 | G_ATOMICRMW_FSUB = 123, // GenericOpcodes.td:1510 |
| 139 | G_ATOMICRMW_FMAX = 124, // GenericOpcodes.td:1511 |
| 140 | G_ATOMICRMW_FMIN = 125, // GenericOpcodes.td:1512 |
| 141 | G_ATOMICRMW_FMAXIMUM = 126, // GenericOpcodes.td:1513 |
| 142 | G_ATOMICRMW_FMINIMUM = 127, // GenericOpcodes.td:1514 |
| 143 | G_ATOMICRMW_FMAXIMUMNUM = 128, // GenericOpcodes.td:1515 |
| 144 | G_ATOMICRMW_FMINIMUMNUM = 129, // GenericOpcodes.td:1516 |
| 145 | G_ATOMICRMW_UINC_WRAP = 130, // GenericOpcodes.td:1499 |
| 146 | G_ATOMICRMW_UDEC_WRAP = 131, // GenericOpcodes.td:1500 |
| 147 | G_ATOMICRMW_USUB_COND = 132, // GenericOpcodes.td:1501 |
| 148 | G_ATOMICRMW_USUB_SAT = 133, // GenericOpcodes.td:1502 |
| 149 | G_FENCE = 134, // GenericOpcodes.td:1518 |
| 150 | G_PREFETCH = 135, // GenericOpcodes.td:1525 |
| 151 | G_BRCOND = 136, // GenericOpcodes.td:1665 |
| 152 | G_BRINDIRECT = 137, // GenericOpcodes.td:1674 |
| 153 | G_INVOKE_REGION_START = 138, // GenericOpcodes.td:1697 |
| 154 | G_INTRINSIC = 139, // GenericOpcodes.td:1617 |
| 155 | G_INTRINSIC_W_SIDE_EFFECTS = 140, // GenericOpcodes.td:1624 |
| 156 | G_INTRINSIC_CONVERGENT = 141, // GenericOpcodes.td:1633 |
| 157 | G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 142, // GenericOpcodes.td:1641 |
| 158 | G_ANYEXT = 143, // GenericOpcodes.td:44 |
| 159 | G_TRUNC = 144, // GenericOpcodes.td:83 |
| 160 | G_TRUNC_SSAT_S = 145, // GenericOpcodes.td:91 |
| 161 | G_TRUNC_SSAT_U = 146, // GenericOpcodes.td:98 |
| 162 | G_TRUNC_USAT_U = 147, // GenericOpcodes.td:105 |
| 163 | G_CONSTANT = 148, // GenericOpcodes.td:169 |
| 164 | G_FCONSTANT = 149, // GenericOpcodes.td:177 |
| 165 | G_VASTART = 150, // GenericOpcodes.td:184 |
| 166 | G_VAARG = 151, // GenericOpcodes.td:191 |
| 167 | G_SEXT = 152, // GenericOpcodes.td:52 |
| 168 | G_SEXT_INREG = 153, // GenericOpcodes.td:66 |
| 169 | G_ZEXT = 154, // GenericOpcodes.td:74 |
| 170 | G_SHL = 155, // GenericOpcodes.td:404 |
| 171 | G_LSHR = 156, // GenericOpcodes.td:411 |
| 172 | G_ASHR = 157, // GenericOpcodes.td:418 |
| 173 | G_FSHL = 158, // GenericOpcodes.td:470 |
| 174 | G_FSHR = 159, // GenericOpcodes.td:478 |
| 175 | G_ROTR = 160, // GenericOpcodes.td:485 |
| 176 | G_ROTL = 161, // GenericOpcodes.td:492 |
| 177 | G_ICMP = 162, // GenericOpcodes.td:499 |
| 178 | G_FCMP = 163, // GenericOpcodes.td:506 |
| 179 | G_SCMP = 164, // GenericOpcodes.td:513 |
| 180 | G_UCMP = 165, // GenericOpcodes.td:520 |
| 181 | G_SELECT = 166, // GenericOpcodes.td:527 |
| 182 | G_UADDO = 167, // GenericOpcodes.td:619 |
| 183 | G_UADDE = 168, // GenericOpcodes.td:627 |
| 184 | G_USUBO = 169, // GenericOpcodes.td:649 |
| 185 | G_USUBE = 170, // GenericOpcodes.td:655 |
| 186 | G_SADDO = 171, // GenericOpcodes.td:634 |
| 187 | G_SADDE = 172, // GenericOpcodes.td:642 |
| 188 | G_SSUBO = 173, // GenericOpcodes.td:662 |
| 189 | G_SSUBE = 174, // GenericOpcodes.td:669 |
| 190 | G_UMULO = 175, // GenericOpcodes.td:676 |
| 191 | G_SMULO = 176, // GenericOpcodes.td:684 |
| 192 | G_UMULH = 177, // GenericOpcodes.td:693 |
| 193 | G_SMULH = 178, // GenericOpcodes.td:702 |
| 194 | G_UADDSAT = 179, // GenericOpcodes.td:714 |
| 195 | G_SADDSAT = 180, // GenericOpcodes.td:722 |
| 196 | G_USUBSAT = 181, // GenericOpcodes.td:730 |
| 197 | G_SSUBSAT = 182, // GenericOpcodes.td:738 |
| 198 | G_USHLSAT = 183, // GenericOpcodes.td:746 |
| 199 | G_SSHLSAT = 184, // GenericOpcodes.td:754 |
| 200 | G_SMULFIX = 185, // GenericOpcodes.td:766 |
| 201 | G_UMULFIX = 186, // GenericOpcodes.td:773 |
| 202 | G_SMULFIXSAT = 187, // GenericOpcodes.td:783 |
| 203 | G_UMULFIXSAT = 188, // GenericOpcodes.td:790 |
| 204 | G_SDIVFIX = 189, // GenericOpcodes.td:801 |
| 205 | G_UDIVFIX = 190, // GenericOpcodes.td:808 |
| 206 | G_SDIVFIXSAT = 191, // GenericOpcodes.td:818 |
| 207 | G_UDIVFIXSAT = 192, // GenericOpcodes.td:825 |
| 208 | G_FADD = 193, // GenericOpcodes.td:998 |
| 209 | G_FSUB = 194, // GenericOpcodes.td:1006 |
| 210 | G_FMUL = 195, // GenericOpcodes.td:1014 |
| 211 | G_FMA = 196, // GenericOpcodes.td:1023 |
| 212 | G_FMAD = 197, // GenericOpcodes.td:1032 |
| 213 | G_FDIV = 198, // GenericOpcodes.td:1040 |
| 214 | G_FREM = 199, // GenericOpcodes.td:1047 |
| 215 | G_FMODF = 200, // GenericOpcodes.td:1054 |
| 216 | G_FPOW = 201, // GenericOpcodes.td:1061 |
| 217 | G_FPOWI = 202, // GenericOpcodes.td:1068 |
| 218 | G_FEXP = 203, // GenericOpcodes.td:1075 |
| 219 | G_FEXP2 = 204, // GenericOpcodes.td:1082 |
| 220 | G_FEXP10 = 205, // GenericOpcodes.td:1089 |
| 221 | G_FLOG = 206, // GenericOpcodes.td:1096 |
| 222 | G_FLOG2 = 207, // GenericOpcodes.td:1103 |
| 223 | G_FLOG10 = 208, // GenericOpcodes.td:1110 |
| 224 | G_FLDEXP = 209, // GenericOpcodes.td:1117 |
| 225 | G_FFREXP = 210, // GenericOpcodes.td:1124 |
| 226 | G_FNEG = 211, // GenericOpcodes.td:836 |
| 227 | G_FPEXT = 212, // GenericOpcodes.td:842 |
| 228 | G_FPTRUNC = 213, // GenericOpcodes.td:848 |
| 229 | G_FPTOSI = 214, // GenericOpcodes.td:854 |
| 230 | G_FPTOUI = 215, // GenericOpcodes.td:860 |
| 231 | G_SITOFP = 216, // GenericOpcodes.td:866 |
| 232 | G_UITOFP = 217, // GenericOpcodes.td:872 |
| 233 | G_FPTOSI_SAT = 218, // GenericOpcodes.td:878 |
| 234 | G_FPTOUI_SAT = 219, // GenericOpcodes.td:884 |
| 235 | G_FABS = 220, // GenericOpcodes.td:890 |
| 236 | G_FCOPYSIGN = 221, // GenericOpcodes.td:896 |
| 237 | G_IS_FPCLASS = 222, // GenericOpcodes.td:909 |
| 238 | G_FCANONICALIZE = 223, // GenericOpcodes.td:902 |
| 239 | G_FMINNUM = 224, // GenericOpcodes.td:922 |
| 240 | G_FMAXNUM = 225, // GenericOpcodes.td:929 |
| 241 | G_FMINNUM_IEEE = 226, // GenericOpcodes.td:947 |
| 242 | G_FMAXNUM_IEEE = 227, // GenericOpcodes.td:954 |
| 243 | G_FMINIMUM = 228, // GenericOpcodes.td:964 |
| 244 | G_FMAXIMUM = 229, // GenericOpcodes.td:971 |
| 245 | G_FMINIMUMNUM = 230, // GenericOpcodes.td:979 |
| 246 | G_FMAXIMUMNUM = 231, // GenericOpcodes.td:986 |
| 247 | G_GET_FPENV = 232, // GenericOpcodes.td:1254 |
| 248 | G_SET_FPENV = 233, // GenericOpcodes.td:1261 |
| 249 | G_RESET_FPENV = 234, // GenericOpcodes.td:1268 |
| 250 | G_GET_FPMODE = 235, // GenericOpcodes.td:1275 |
| 251 | G_SET_FPMODE = 236, // GenericOpcodes.td:1282 |
| 252 | G_RESET_FPMODE = 237, // GenericOpcodes.td:1289 |
| 253 | G_GET_ROUNDING = 238, // GenericOpcodes.td:1346 |
| 254 | G_SET_ROUNDING = 239, // GenericOpcodes.td:1352 |
| 255 | G_PTR_ADD = 240, // GenericOpcodes.td:534 |
| 256 | G_PTRMASK = 241, // GenericOpcodes.td:542 |
| 257 | G_SMIN = 242, // GenericOpcodes.td:549 |
| 258 | G_SMAX = 243, // GenericOpcodes.td:557 |
| 259 | G_UMIN = 244, // GenericOpcodes.td:565 |
| 260 | G_UMAX = 245, // GenericOpcodes.td:573 |
| 261 | G_ABS = 246, // GenericOpcodes.td:581 |
| 262 | G_LROUND = 247, // GenericOpcodes.td:291 |
| 263 | G_LLROUND = 248, // GenericOpcodes.td:297 |
| 264 | G_BR = 249, // GenericOpcodes.td:1655 |
| 265 | G_BRJT = 250, // GenericOpcodes.td:1685 |
| 266 | G_VSCALE = 251, // GenericOpcodes.td:1583 |
| 267 | G_INSERT_SUBVECTOR = 252, // GenericOpcodes.td:1729 |
| 268 | G_EXTRACT_SUBVECTOR = 253, // GenericOpcodes.td:1737 |
| 269 | G_INSERT_VECTOR_ELT = 254, // GenericOpcodes.td:1745 |
| 270 | G_EXTRACT_VECTOR_ELT = 255, // GenericOpcodes.td:1753 |
| 271 | G_SHUFFLE_VECTOR = 256, // GenericOpcodes.td:1764 |
| 272 | G_SPLAT_VECTOR = 257, // GenericOpcodes.td:1772 |
| 273 | G_STEP_VECTOR = 258, // GenericOpcodes.td:1780 |
| 274 | G_VECTOR_COMPRESS = 259, // GenericOpcodes.td:1787 |
| 275 | G_CTTZ = 260, // GenericOpcodes.td:211 |
| 276 | G_CTTZ_ZERO_POISON = 261, // GenericOpcodes.td:217 |
| 277 | G_CTLZ = 262, // GenericOpcodes.td:199 |
| 278 | G_CTLZ_ZERO_POISON = 263, // GenericOpcodes.td:205 |
| 279 | G_CTLS = 264, // GenericOpcodes.td:223 |
| 280 | G_CTPOP = 265, // GenericOpcodes.td:229 |
| 281 | G_BSWAP = 266, // GenericOpcodes.td:235 |
| 282 | G_BITREVERSE = 267, // GenericOpcodes.td:242 |
| 283 | G_CLMUL = 268, // GenericOpcodes.td:588 |
| 284 | G_CLMULH = 269, // GenericOpcodes.td:596 |
| 285 | G_CLMULR = 270, // GenericOpcodes.td:606 |
| 286 | G_FCEIL = 271, // GenericOpcodes.td:1131 |
| 287 | G_FCOS = 272, // GenericOpcodes.td:1138 |
| 288 | G_FSIN = 273, // GenericOpcodes.td:1145 |
| 289 | G_FSINCOS = 274, // GenericOpcodes.td:1152 |
| 290 | G_FTAN = 275, // GenericOpcodes.td:1159 |
| 291 | G_FACOS = 276, // GenericOpcodes.td:1166 |
| 292 | G_FASIN = 277, // GenericOpcodes.td:1173 |
| 293 | G_FATAN = 278, // GenericOpcodes.td:1180 |
| 294 | G_FATAN2 = 279, // GenericOpcodes.td:1187 |
| 295 | G_FCOSH = 280, // GenericOpcodes.td:1194 |
| 296 | G_FSINH = 281, // GenericOpcodes.td:1201 |
| 297 | G_FTANH = 282, // GenericOpcodes.td:1208 |
| 298 | G_FSQRT = 283, // GenericOpcodes.td:1218 |
| 299 | G_FFLOOR = 284, // GenericOpcodes.td:1225 |
| 300 | G_FRINT = 285, // GenericOpcodes.td:1232 |
| 301 | G_FNEARBYINT = 286, // GenericOpcodes.td:1239 |
| 302 | G_ADDRSPACE_CAST = 287, // GenericOpcodes.td:248 |
| 303 | G_BLOCK_ADDR = 288, // GenericOpcodes.td:254 |
| 304 | G_JUMP_TABLE = 289, // GenericOpcodes.td:260 |
| 305 | G_DYN_STACKALLOC = 290, // GenericOpcodes.td:266 |
| 306 | G_STACKSAVE = 291, // GenericOpcodes.td:272 |
| 307 | G_STACKRESTORE = 292, // GenericOpcodes.td:278 |
| 308 | G_STRICT_FADD = 293, // GenericOpcodes.td:1839 |
| 309 | G_STRICT_FSUB = 294, // GenericOpcodes.td:1840 |
| 310 | G_STRICT_FMUL = 295, // GenericOpcodes.td:1841 |
| 311 | G_STRICT_FDIV = 296, // GenericOpcodes.td:1842 |
| 312 | G_STRICT_FREM = 297, // GenericOpcodes.td:1843 |
| 313 | G_STRICT_FMA = 298, // GenericOpcodes.td:1844 |
| 314 | G_STRICT_FSQRT = 299, // GenericOpcodes.td:1845 |
| 315 | G_STRICT_FLDEXP = 300, // GenericOpcodes.td:1846 |
| 316 | G_STRICT_FCMP = 301, // GenericOpcodes.td:1847 |
| 317 | G_STRICT_FCMPS = 302, // GenericOpcodes.td:1848 |
| 318 | G_READ_REGISTER = 303, // GenericOpcodes.td:1704 |
| 319 | G_WRITE_REGISTER = 304, // GenericOpcodes.td:1714 |
| 320 | G_MEMCPY = 305, // GenericOpcodes.td:1854 |
| 321 | G_MEMCPY_INLINE = 306, // GenericOpcodes.td:1862 |
| 322 | G_MEMMOVE = 307, // GenericOpcodes.td:1870 |
| 323 | G_MEMSET = 308, // GenericOpcodes.td:1878 |
| 324 | G_BZERO = 309, // GenericOpcodes.td:1885 |
| 325 | G_MEMSET_INLINE = 310, // GenericOpcodes.td:1892 |
| 326 | G_TRAP = 311, // GenericOpcodes.td:1902 |
| 327 | G_DEBUGTRAP = 312, // GenericOpcodes.td:1909 |
| 328 | G_UBSANTRAP = 313, // GenericOpcodes.td:1915 |
| 329 | G_VECREDUCE_SEQ_FADD = 314, // GenericOpcodes.td:1803 |
| 330 | G_VECREDUCE_SEQ_FMUL = 315, // GenericOpcodes.td:1809 |
| 331 | G_VECREDUCE_FADD = 316, // GenericOpcodes.td:1815 |
| 332 | G_VECREDUCE_FMUL = 317, // GenericOpcodes.td:1816 |
| 333 | G_VECREDUCE_FMAX = 318, // GenericOpcodes.td:1818 |
| 334 | G_VECREDUCE_FMIN = 319, // GenericOpcodes.td:1819 |
| 335 | G_VECREDUCE_FMAXIMUM = 320, // GenericOpcodes.td:1820 |
| 336 | G_VECREDUCE_FMINIMUM = 321, // GenericOpcodes.td:1821 |
| 337 | G_VECREDUCE_FMAXIMUMNUM = 322, // GenericOpcodes.td:1822 |
| 338 | G_VECREDUCE_FMINIMUMNUM = 323, // GenericOpcodes.td:1823 |
| 339 | G_VECREDUCE_ADD = 324, // GenericOpcodes.td:1825 |
| 340 | G_VECREDUCE_MUL = 325, // GenericOpcodes.td:1826 |
| 341 | G_VECREDUCE_AND = 326, // GenericOpcodes.td:1827 |
| 342 | G_VECREDUCE_OR = 327, // GenericOpcodes.td:1828 |
| 343 | G_VECREDUCE_XOR = 328, // GenericOpcodes.td:1829 |
| 344 | G_VECREDUCE_SMAX = 329, // GenericOpcodes.td:1830 |
| 345 | G_VECREDUCE_SMIN = 330, // GenericOpcodes.td:1831 |
| 346 | G_VECREDUCE_UMAX = 331, // GenericOpcodes.td:1832 |
| 347 | G_VECREDUCE_UMIN = 332, // GenericOpcodes.td:1833 |
| 348 | G_SBFX = 333, // GenericOpcodes.td:1927 |
| 349 | G_UBFX = 334, // GenericOpcodes.td:1935 |
| 350 | CALL_PARAMS = 335, // WebAssemblyInstrFormats.td:59 |
| 351 | CALL_PARAMS_S = 336, // WebAssemblyInstrFormats.td:61 |
| 352 | CALL_RESULTS = 337, // WebAssemblyInstrFormats.td:59 |
| 353 | CALL_RESULTS_S = 338, // WebAssemblyInstrFormats.td:61 |
| 354 | CATCHRET = 339, // WebAssemblyInstrFormats.td:59 |
| 355 | CATCHRET_S = 340, // WebAssemblyInstrFormats.td:61 |
| 356 | CLEANUPRET = 341, // WebAssemblyInstrFormats.td:59 |
| 357 | CLEANUPRET_S = 342, // WebAssemblyInstrFormats.td:61 |
| 358 | COMPILER_FENCE = 343, // WebAssemblyInstrFormats.td:59 |
| 359 | COMPILER_FENCE_S = 344, // WebAssemblyInstrFormats.td:61 |
| 360 | RET_CALL_PARAMS = 345, // WebAssemblyInstrFormats.td:59 |
| 361 | RET_CALL_PARAMS_S = 346, // WebAssemblyInstrFormats.td:61 |
| 362 | RET_CALL_RESULTS = 347, // WebAssemblyInstrFormats.td:59 |
| 363 | RET_CALL_RESULTS_S = 348, // WebAssemblyInstrFormats.td:61 |
| 364 | ABS_F16x8 = 349, // WebAssemblyInstrFormats.td:59 |
| 365 | ABS_F16x8_S = 350, // WebAssemblyInstrFormats.td:61 |
| 366 | ABS_F32 = 351, // WebAssemblyInstrFormats.td:59 |
| 367 | ABS_F32_S = 352, // WebAssemblyInstrFormats.td:61 |
| 368 | ABS_F32x4 = 353, // WebAssemblyInstrFormats.td:59 |
| 369 | ABS_F32x4_S = 354, // WebAssemblyInstrFormats.td:61 |
| 370 | ABS_F64 = 355, // WebAssemblyInstrFormats.td:59 |
| 371 | ABS_F64_S = 356, // WebAssemblyInstrFormats.td:61 |
| 372 | ABS_F64x2 = 357, // WebAssemblyInstrFormats.td:59 |
| 373 | ABS_F64x2_S = 358, // WebAssemblyInstrFormats.td:61 |
| 374 | ABS_I16x8 = 359, // WebAssemblyInstrFormats.td:59 |
| 375 | ABS_I16x8_S = 360, // WebAssemblyInstrFormats.td:61 |
| 376 | ABS_I32x4 = 361, // WebAssemblyInstrFormats.td:59 |
| 377 | ABS_I32x4_S = 362, // WebAssemblyInstrFormats.td:61 |
| 378 | ABS_I64x2 = 363, // WebAssemblyInstrFormats.td:59 |
| 379 | ABS_I64x2_S = 364, // WebAssemblyInstrFormats.td:61 |
| 380 | ABS_I8x16 = 365, // WebAssemblyInstrFormats.td:59 |
| 381 | ABS_I8x16_S = 366, // WebAssemblyInstrFormats.td:61 |
| 382 | ADD_F16x8 = 367, // WebAssemblyInstrFormats.td:59 |
| 383 | ADD_F16x8_S = 368, // WebAssemblyInstrFormats.td:61 |
| 384 | ADD_F32 = 369, // WebAssemblyInstrFormats.td:59 |
| 385 | ADD_F32_S = 370, // WebAssemblyInstrFormats.td:61 |
| 386 | ADD_F32x4 = 371, // WebAssemblyInstrFormats.td:59 |
| 387 | ADD_F32x4_S = 372, // WebAssemblyInstrFormats.td:61 |
| 388 | ADD_F64 = 373, // WebAssemblyInstrFormats.td:59 |
| 389 | ADD_F64_S = 374, // WebAssemblyInstrFormats.td:61 |
| 390 | ADD_F64x2 = 375, // WebAssemblyInstrFormats.td:59 |
| 391 | ADD_F64x2_S = 376, // WebAssemblyInstrFormats.td:61 |
| 392 | ADD_I16x8 = 377, // WebAssemblyInstrFormats.td:59 |
| 393 | ADD_I16x8_S = 378, // WebAssemblyInstrFormats.td:61 |
| 394 | ADD_I32 = 379, // WebAssemblyInstrFormats.td:59 |
| 395 | ADD_I32_S = 380, // WebAssemblyInstrFormats.td:61 |
| 396 | ADD_I32x4 = 381, // WebAssemblyInstrFormats.td:59 |
| 397 | ADD_I32x4_S = 382, // WebAssemblyInstrFormats.td:61 |
| 398 | ADD_I64 = 383, // WebAssemblyInstrFormats.td:59 |
| 399 | ADD_I64_S = 384, // WebAssemblyInstrFormats.td:61 |
| 400 | ADD_I64x2 = 385, // WebAssemblyInstrFormats.td:59 |
| 401 | ADD_I64x2_S = 386, // WebAssemblyInstrFormats.td:61 |
| 402 | ADD_I8x16 = 387, // WebAssemblyInstrFormats.td:59 |
| 403 | ADD_I8x16_S = 388, // WebAssemblyInstrFormats.td:61 |
| 404 | ADD_SAT_S_I16x8 = 389, // WebAssemblyInstrFormats.td:59 |
| 405 | ADD_SAT_S_I16x8_S = 390, // WebAssemblyInstrFormats.td:61 |
| 406 | ADD_SAT_S_I8x16 = 391, // WebAssemblyInstrFormats.td:59 |
| 407 | ADD_SAT_S_I8x16_S = 392, // WebAssemblyInstrFormats.td:61 |
| 408 | ADD_SAT_U_I16x8 = 393, // WebAssemblyInstrFormats.td:59 |
| 409 | ADD_SAT_U_I16x8_S = 394, // WebAssemblyInstrFormats.td:61 |
| 410 | ADD_SAT_U_I8x16 = 395, // WebAssemblyInstrFormats.td:59 |
| 411 | ADD_SAT_U_I8x16_S = 396, // WebAssemblyInstrFormats.td:61 |
| 412 | ADJCALLSTACKDOWN = 397, // WebAssemblyInstrFormats.td:59 |
| 413 | ADJCALLSTACKDOWN_S = 398, // WebAssemblyInstrFormats.td:61 |
| 414 | ADJCALLSTACKUP = 399, // WebAssemblyInstrFormats.td:59 |
| 415 | ADJCALLSTACKUP_S = 400, // WebAssemblyInstrFormats.td:61 |
| 416 | ALLTRUE_I16x8 = 401, // WebAssemblyInstrFormats.td:59 |
| 417 | ALLTRUE_I16x8_S = 402, // WebAssemblyInstrFormats.td:61 |
| 418 | ALLTRUE_I32x4 = 403, // WebAssemblyInstrFormats.td:59 |
| 419 | ALLTRUE_I32x4_S = 404, // WebAssemblyInstrFormats.td:61 |
| 420 | ALLTRUE_I64x2 = 405, // WebAssemblyInstrFormats.td:59 |
| 421 | ALLTRUE_I64x2_S = 406, // WebAssemblyInstrFormats.td:61 |
| 422 | ALLTRUE_I8x16 = 407, // WebAssemblyInstrFormats.td:59 |
| 423 | ALLTRUE_I8x16_S = 408, // WebAssemblyInstrFormats.td:61 |
| 424 | AND = 409, // WebAssemblyInstrFormats.td:59 |
| 425 | ANDNOT = 410, // WebAssemblyInstrFormats.td:59 |
| 426 | ANDNOT_S = 411, // WebAssemblyInstrFormats.td:61 |
| 427 | AND_I32 = 412, // WebAssemblyInstrFormats.td:59 |
| 428 | AND_I32_S = 413, // WebAssemblyInstrFormats.td:61 |
| 429 | AND_I64 = 414, // WebAssemblyInstrFormats.td:59 |
| 430 | AND_I64_S = 415, // WebAssemblyInstrFormats.td:61 |
| 431 | AND_S = 416, // WebAssemblyInstrFormats.td:61 |
| 432 | ANYTRUE = 417, // WebAssemblyInstrFormats.td:59 |
| 433 | ANYTRUE_S = 418, // WebAssemblyInstrFormats.td:61 |
| 434 | ARGUMENT_exnref = 419, // WebAssemblyInstrFormats.td:59 |
| 435 | ARGUMENT_exnref_S = 420, // WebAssemblyInstrFormats.td:61 |
| 436 | ARGUMENT_externref = 421, // WebAssemblyInstrFormats.td:59 |
| 437 | ARGUMENT_externref_S = 422, // WebAssemblyInstrFormats.td:61 |
| 438 | ARGUMENT_f32 = 423, // WebAssemblyInstrFormats.td:59 |
| 439 | ARGUMENT_f32_S = 424, // WebAssemblyInstrFormats.td:61 |
| 440 | ARGUMENT_f64 = 425, // WebAssemblyInstrFormats.td:59 |
| 441 | ARGUMENT_f64_S = 426, // WebAssemblyInstrFormats.td:61 |
| 442 | ARGUMENT_funcref = 427, // WebAssemblyInstrFormats.td:59 |
| 443 | ARGUMENT_funcref_S = 428, // WebAssemblyInstrFormats.td:61 |
| 444 | ARGUMENT_i32 = 429, // WebAssemblyInstrFormats.td:59 |
| 445 | ARGUMENT_i32_S = 430, // WebAssemblyInstrFormats.td:61 |
| 446 | ARGUMENT_i64 = 431, // WebAssemblyInstrFormats.td:59 |
| 447 | ARGUMENT_i64_S = 432, // WebAssemblyInstrFormats.td:61 |
| 448 | ARGUMENT_v16i8 = 433, // WebAssemblyInstrFormats.td:59 |
| 449 | ARGUMENT_v16i8_S = 434, // WebAssemblyInstrFormats.td:61 |
| 450 | ARGUMENT_v2f64 = 435, // WebAssemblyInstrFormats.td:59 |
| 451 | ARGUMENT_v2f64_S = 436, // WebAssemblyInstrFormats.td:61 |
| 452 | ARGUMENT_v2i64 = 437, // WebAssemblyInstrFormats.td:59 |
| 453 | ARGUMENT_v2i64_S = 438, // WebAssemblyInstrFormats.td:61 |
| 454 | ARGUMENT_v4f32 = 439, // WebAssemblyInstrFormats.td:59 |
| 455 | ARGUMENT_v4f32_S = 440, // WebAssemblyInstrFormats.td:61 |
| 456 | ARGUMENT_v4i32 = 441, // WebAssemblyInstrFormats.td:59 |
| 457 | ARGUMENT_v4i32_S = 442, // WebAssemblyInstrFormats.td:61 |
| 458 | ARGUMENT_v8f16 = 443, // WebAssemblyInstrFormats.td:59 |
| 459 | ARGUMENT_v8f16_S = 444, // WebAssemblyInstrFormats.td:61 |
| 460 | ARGUMENT_v8i16 = 445, // WebAssemblyInstrFormats.td:59 |
| 461 | ARGUMENT_v8i16_S = 446, // WebAssemblyInstrFormats.td:61 |
| 462 | ATOMIC_FENCE = 447, // WebAssemblyInstrFormats.td:59 |
| 463 | ATOMIC_FENCE_S = 448, // WebAssemblyInstrFormats.td:61 |
| 464 | ATOMIC_LOAD16_U_I32_A32 = 449, // WebAssemblyInstrFormats.td:59 |
| 465 | ATOMIC_LOAD16_U_I32_A32_S = 450, // WebAssemblyInstrFormats.td:61 |
| 466 | ATOMIC_LOAD16_U_I32_A64 = 451, // WebAssemblyInstrFormats.td:59 |
| 467 | ATOMIC_LOAD16_U_I32_A64_S = 452, // WebAssemblyInstrFormats.td:61 |
| 468 | ATOMIC_LOAD16_U_I64_A32 = 453, // WebAssemblyInstrFormats.td:59 |
| 469 | ATOMIC_LOAD16_U_I64_A32_S = 454, // WebAssemblyInstrFormats.td:61 |
| 470 | ATOMIC_LOAD16_U_I64_A64 = 455, // WebAssemblyInstrFormats.td:59 |
| 471 | ATOMIC_LOAD16_U_I64_A64_S = 456, // WebAssemblyInstrFormats.td:61 |
| 472 | ATOMIC_LOAD32_U_I64_A32 = 457, // WebAssemblyInstrFormats.td:59 |
| 473 | ATOMIC_LOAD32_U_I64_A32_S = 458, // WebAssemblyInstrFormats.td:61 |
| 474 | ATOMIC_LOAD32_U_I64_A64 = 459, // WebAssemblyInstrFormats.td:59 |
| 475 | ATOMIC_LOAD32_U_I64_A64_S = 460, // WebAssemblyInstrFormats.td:61 |
| 476 | ATOMIC_LOAD8_U_I32_A32 = 461, // WebAssemblyInstrFormats.td:59 |
| 477 | ATOMIC_LOAD8_U_I32_A32_S = 462, // WebAssemblyInstrFormats.td:61 |
| 478 | ATOMIC_LOAD8_U_I32_A64 = 463, // WebAssemblyInstrFormats.td:59 |
| 479 | ATOMIC_LOAD8_U_I32_A64_S = 464, // WebAssemblyInstrFormats.td:61 |
| 480 | ATOMIC_LOAD8_U_I64_A32 = 465, // WebAssemblyInstrFormats.td:59 |
| 481 | ATOMIC_LOAD8_U_I64_A32_S = 466, // WebAssemblyInstrFormats.td:61 |
| 482 | ATOMIC_LOAD8_U_I64_A64 = 467, // WebAssemblyInstrFormats.td:59 |
| 483 | ATOMIC_LOAD8_U_I64_A64_S = 468, // WebAssemblyInstrFormats.td:61 |
| 484 | ATOMIC_LOAD_I32_A32 = 469, // WebAssemblyInstrFormats.td:59 |
| 485 | ATOMIC_LOAD_I32_A32_S = 470, // WebAssemblyInstrFormats.td:61 |
| 486 | ATOMIC_LOAD_I32_A64 = 471, // WebAssemblyInstrFormats.td:59 |
| 487 | ATOMIC_LOAD_I32_A64_S = 472, // WebAssemblyInstrFormats.td:61 |
| 488 | ATOMIC_LOAD_I64_A32 = 473, // WebAssemblyInstrFormats.td:59 |
| 489 | ATOMIC_LOAD_I64_A32_S = 474, // WebAssemblyInstrFormats.td:61 |
| 490 | ATOMIC_LOAD_I64_A64 = 475, // WebAssemblyInstrFormats.td:59 |
| 491 | ATOMIC_LOAD_I64_A64_S = 476, // WebAssemblyInstrFormats.td:61 |
| 492 | ATOMIC_RMW16_U_ADD_I32_A32 = 477, // WebAssemblyInstrFormats.td:59 |
| 493 | ATOMIC_RMW16_U_ADD_I32_A32_S = 478, // WebAssemblyInstrFormats.td:61 |
| 494 | ATOMIC_RMW16_U_ADD_I32_A64 = 479, // WebAssemblyInstrFormats.td:59 |
| 495 | ATOMIC_RMW16_U_ADD_I32_A64_S = 480, // WebAssemblyInstrFormats.td:61 |
| 496 | ATOMIC_RMW16_U_ADD_I64_A32 = 481, // WebAssemblyInstrFormats.td:59 |
| 497 | ATOMIC_RMW16_U_ADD_I64_A32_S = 482, // WebAssemblyInstrFormats.td:61 |
| 498 | ATOMIC_RMW16_U_ADD_I64_A64 = 483, // WebAssemblyInstrFormats.td:59 |
| 499 | ATOMIC_RMW16_U_ADD_I64_A64_S = 484, // WebAssemblyInstrFormats.td:61 |
| 500 | ATOMIC_RMW16_U_AND_I32_A32 = 485, // WebAssemblyInstrFormats.td:59 |
| 501 | ATOMIC_RMW16_U_AND_I32_A32_S = 486, // WebAssemblyInstrFormats.td:61 |
| 502 | ATOMIC_RMW16_U_AND_I32_A64 = 487, // WebAssemblyInstrFormats.td:59 |
| 503 | ATOMIC_RMW16_U_AND_I32_A64_S = 488, // WebAssemblyInstrFormats.td:61 |
| 504 | ATOMIC_RMW16_U_AND_I64_A32 = 489, // WebAssemblyInstrFormats.td:59 |
| 505 | ATOMIC_RMW16_U_AND_I64_A32_S = 490, // WebAssemblyInstrFormats.td:61 |
| 506 | ATOMIC_RMW16_U_AND_I64_A64 = 491, // WebAssemblyInstrFormats.td:59 |
| 507 | ATOMIC_RMW16_U_AND_I64_A64_S = 492, // WebAssemblyInstrFormats.td:61 |
| 508 | ATOMIC_RMW16_U_CMPXCHG_I32_A32 = 493, // WebAssemblyInstrFormats.td:59 |
| 509 | ATOMIC_RMW16_U_CMPXCHG_I32_A32_S = 494, // WebAssemblyInstrFormats.td:61 |
| 510 | ATOMIC_RMW16_U_CMPXCHG_I32_A64 = 495, // WebAssemblyInstrFormats.td:59 |
| 511 | ATOMIC_RMW16_U_CMPXCHG_I32_A64_S = 496, // WebAssemblyInstrFormats.td:61 |
| 512 | ATOMIC_RMW16_U_CMPXCHG_I64_A32 = 497, // WebAssemblyInstrFormats.td:59 |
| 513 | ATOMIC_RMW16_U_CMPXCHG_I64_A32_S = 498, // WebAssemblyInstrFormats.td:61 |
| 514 | ATOMIC_RMW16_U_CMPXCHG_I64_A64 = 499, // WebAssemblyInstrFormats.td:59 |
| 515 | ATOMIC_RMW16_U_CMPXCHG_I64_A64_S = 500, // WebAssemblyInstrFormats.td:61 |
| 516 | ATOMIC_RMW16_U_OR_I32_A32 = 501, // WebAssemblyInstrFormats.td:59 |
| 517 | ATOMIC_RMW16_U_OR_I32_A32_S = 502, // WebAssemblyInstrFormats.td:61 |
| 518 | ATOMIC_RMW16_U_OR_I32_A64 = 503, // WebAssemblyInstrFormats.td:59 |
| 519 | ATOMIC_RMW16_U_OR_I32_A64_S = 504, // WebAssemblyInstrFormats.td:61 |
| 520 | ATOMIC_RMW16_U_OR_I64_A32 = 505, // WebAssemblyInstrFormats.td:59 |
| 521 | ATOMIC_RMW16_U_OR_I64_A32_S = 506, // WebAssemblyInstrFormats.td:61 |
| 522 | ATOMIC_RMW16_U_OR_I64_A64 = 507, // WebAssemblyInstrFormats.td:59 |
| 523 | ATOMIC_RMW16_U_OR_I64_A64_S = 508, // WebAssemblyInstrFormats.td:61 |
| 524 | ATOMIC_RMW16_U_SUB_I32_A32 = 509, // WebAssemblyInstrFormats.td:59 |
| 525 | ATOMIC_RMW16_U_SUB_I32_A32_S = 510, // WebAssemblyInstrFormats.td:61 |
| 526 | ATOMIC_RMW16_U_SUB_I32_A64 = 511, // WebAssemblyInstrFormats.td:59 |
| 527 | ATOMIC_RMW16_U_SUB_I32_A64_S = 512, // WebAssemblyInstrFormats.td:61 |
| 528 | ATOMIC_RMW16_U_SUB_I64_A32 = 513, // WebAssemblyInstrFormats.td:59 |
| 529 | ATOMIC_RMW16_U_SUB_I64_A32_S = 514, // WebAssemblyInstrFormats.td:61 |
| 530 | ATOMIC_RMW16_U_SUB_I64_A64 = 515, // WebAssemblyInstrFormats.td:59 |
| 531 | ATOMIC_RMW16_U_SUB_I64_A64_S = 516, // WebAssemblyInstrFormats.td:61 |
| 532 | ATOMIC_RMW16_U_XCHG_I32_A32 = 517, // WebAssemblyInstrFormats.td:59 |
| 533 | ATOMIC_RMW16_U_XCHG_I32_A32_S = 518, // WebAssemblyInstrFormats.td:61 |
| 534 | ATOMIC_RMW16_U_XCHG_I32_A64 = 519, // WebAssemblyInstrFormats.td:59 |
| 535 | ATOMIC_RMW16_U_XCHG_I32_A64_S = 520, // WebAssemblyInstrFormats.td:61 |
| 536 | ATOMIC_RMW16_U_XCHG_I64_A32 = 521, // WebAssemblyInstrFormats.td:59 |
| 537 | ATOMIC_RMW16_U_XCHG_I64_A32_S = 522, // WebAssemblyInstrFormats.td:61 |
| 538 | ATOMIC_RMW16_U_XCHG_I64_A64 = 523, // WebAssemblyInstrFormats.td:59 |
| 539 | ATOMIC_RMW16_U_XCHG_I64_A64_S = 524, // WebAssemblyInstrFormats.td:61 |
| 540 | ATOMIC_RMW16_U_XOR_I32_A32 = 525, // WebAssemblyInstrFormats.td:59 |
| 541 | ATOMIC_RMW16_U_XOR_I32_A32_S = 526, // WebAssemblyInstrFormats.td:61 |
| 542 | ATOMIC_RMW16_U_XOR_I32_A64 = 527, // WebAssemblyInstrFormats.td:59 |
| 543 | ATOMIC_RMW16_U_XOR_I32_A64_S = 528, // WebAssemblyInstrFormats.td:61 |
| 544 | ATOMIC_RMW16_U_XOR_I64_A32 = 529, // WebAssemblyInstrFormats.td:59 |
| 545 | ATOMIC_RMW16_U_XOR_I64_A32_S = 530, // WebAssemblyInstrFormats.td:61 |
| 546 | ATOMIC_RMW16_U_XOR_I64_A64 = 531, // WebAssemblyInstrFormats.td:59 |
| 547 | ATOMIC_RMW16_U_XOR_I64_A64_S = 532, // WebAssemblyInstrFormats.td:61 |
| 548 | ATOMIC_RMW32_U_ADD_I64_A32 = 533, // WebAssemblyInstrFormats.td:59 |
| 549 | ATOMIC_RMW32_U_ADD_I64_A32_S = 534, // WebAssemblyInstrFormats.td:61 |
| 550 | ATOMIC_RMW32_U_ADD_I64_A64 = 535, // WebAssemblyInstrFormats.td:59 |
| 551 | ATOMIC_RMW32_U_ADD_I64_A64_S = 536, // WebAssemblyInstrFormats.td:61 |
| 552 | ATOMIC_RMW32_U_AND_I64_A32 = 537, // WebAssemblyInstrFormats.td:59 |
| 553 | ATOMIC_RMW32_U_AND_I64_A32_S = 538, // WebAssemblyInstrFormats.td:61 |
| 554 | ATOMIC_RMW32_U_AND_I64_A64 = 539, // WebAssemblyInstrFormats.td:59 |
| 555 | ATOMIC_RMW32_U_AND_I64_A64_S = 540, // WebAssemblyInstrFormats.td:61 |
| 556 | ATOMIC_RMW32_U_CMPXCHG_I64_A32 = 541, // WebAssemblyInstrFormats.td:59 |
| 557 | ATOMIC_RMW32_U_CMPXCHG_I64_A32_S = 542, // WebAssemblyInstrFormats.td:61 |
| 558 | ATOMIC_RMW32_U_CMPXCHG_I64_A64 = 543, // WebAssemblyInstrFormats.td:59 |
| 559 | ATOMIC_RMW32_U_CMPXCHG_I64_A64_S = 544, // WebAssemblyInstrFormats.td:61 |
| 560 | ATOMIC_RMW32_U_OR_I64_A32 = 545, // WebAssemblyInstrFormats.td:59 |
| 561 | ATOMIC_RMW32_U_OR_I64_A32_S = 546, // WebAssemblyInstrFormats.td:61 |
| 562 | ATOMIC_RMW32_U_OR_I64_A64 = 547, // WebAssemblyInstrFormats.td:59 |
| 563 | ATOMIC_RMW32_U_OR_I64_A64_S = 548, // WebAssemblyInstrFormats.td:61 |
| 564 | ATOMIC_RMW32_U_SUB_I64_A32 = 549, // WebAssemblyInstrFormats.td:59 |
| 565 | ATOMIC_RMW32_U_SUB_I64_A32_S = 550, // WebAssemblyInstrFormats.td:61 |
| 566 | ATOMIC_RMW32_U_SUB_I64_A64 = 551, // WebAssemblyInstrFormats.td:59 |
| 567 | ATOMIC_RMW32_U_SUB_I64_A64_S = 552, // WebAssemblyInstrFormats.td:61 |
| 568 | ATOMIC_RMW32_U_XCHG_I64_A32 = 553, // WebAssemblyInstrFormats.td:59 |
| 569 | ATOMIC_RMW32_U_XCHG_I64_A32_S = 554, // WebAssemblyInstrFormats.td:61 |
| 570 | ATOMIC_RMW32_U_XCHG_I64_A64 = 555, // WebAssemblyInstrFormats.td:59 |
| 571 | ATOMIC_RMW32_U_XCHG_I64_A64_S = 556, // WebAssemblyInstrFormats.td:61 |
| 572 | ATOMIC_RMW32_U_XOR_I64_A32 = 557, // WebAssemblyInstrFormats.td:59 |
| 573 | ATOMIC_RMW32_U_XOR_I64_A32_S = 558, // WebAssemblyInstrFormats.td:61 |
| 574 | ATOMIC_RMW32_U_XOR_I64_A64 = 559, // WebAssemblyInstrFormats.td:59 |
| 575 | ATOMIC_RMW32_U_XOR_I64_A64_S = 560, // WebAssemblyInstrFormats.td:61 |
| 576 | ATOMIC_RMW8_U_ADD_I32_A32 = 561, // WebAssemblyInstrFormats.td:59 |
| 577 | ATOMIC_RMW8_U_ADD_I32_A32_S = 562, // WebAssemblyInstrFormats.td:61 |
| 578 | ATOMIC_RMW8_U_ADD_I32_A64 = 563, // WebAssemblyInstrFormats.td:59 |
| 579 | ATOMIC_RMW8_U_ADD_I32_A64_S = 564, // WebAssemblyInstrFormats.td:61 |
| 580 | ATOMIC_RMW8_U_ADD_I64_A32 = 565, // WebAssemblyInstrFormats.td:59 |
| 581 | ATOMIC_RMW8_U_ADD_I64_A32_S = 566, // WebAssemblyInstrFormats.td:61 |
| 582 | ATOMIC_RMW8_U_ADD_I64_A64 = 567, // WebAssemblyInstrFormats.td:59 |
| 583 | ATOMIC_RMW8_U_ADD_I64_A64_S = 568, // WebAssemblyInstrFormats.td:61 |
| 584 | ATOMIC_RMW8_U_AND_I32_A32 = 569, // WebAssemblyInstrFormats.td:59 |
| 585 | ATOMIC_RMW8_U_AND_I32_A32_S = 570, // WebAssemblyInstrFormats.td:61 |
| 586 | ATOMIC_RMW8_U_AND_I32_A64 = 571, // WebAssemblyInstrFormats.td:59 |
| 587 | ATOMIC_RMW8_U_AND_I32_A64_S = 572, // WebAssemblyInstrFormats.td:61 |
| 588 | ATOMIC_RMW8_U_AND_I64_A32 = 573, // WebAssemblyInstrFormats.td:59 |
| 589 | ATOMIC_RMW8_U_AND_I64_A32_S = 574, // WebAssemblyInstrFormats.td:61 |
| 590 | ATOMIC_RMW8_U_AND_I64_A64 = 575, // WebAssemblyInstrFormats.td:59 |
| 591 | ATOMIC_RMW8_U_AND_I64_A64_S = 576, // WebAssemblyInstrFormats.td:61 |
| 592 | ATOMIC_RMW8_U_CMPXCHG_I32_A32 = 577, // WebAssemblyInstrFormats.td:59 |
| 593 | ATOMIC_RMW8_U_CMPXCHG_I32_A32_S = 578, // WebAssemblyInstrFormats.td:61 |
| 594 | ATOMIC_RMW8_U_CMPXCHG_I32_A64 = 579, // WebAssemblyInstrFormats.td:59 |
| 595 | ATOMIC_RMW8_U_CMPXCHG_I32_A64_S = 580, // WebAssemblyInstrFormats.td:61 |
| 596 | ATOMIC_RMW8_U_CMPXCHG_I64_A32 = 581, // WebAssemblyInstrFormats.td:59 |
| 597 | ATOMIC_RMW8_U_CMPXCHG_I64_A32_S = 582, // WebAssemblyInstrFormats.td:61 |
| 598 | ATOMIC_RMW8_U_CMPXCHG_I64_A64 = 583, // WebAssemblyInstrFormats.td:59 |
| 599 | ATOMIC_RMW8_U_CMPXCHG_I64_A64_S = 584, // WebAssemblyInstrFormats.td:61 |
| 600 | ATOMIC_RMW8_U_OR_I32_A32 = 585, // WebAssemblyInstrFormats.td:59 |
| 601 | ATOMIC_RMW8_U_OR_I32_A32_S = 586, // WebAssemblyInstrFormats.td:61 |
| 602 | ATOMIC_RMW8_U_OR_I32_A64 = 587, // WebAssemblyInstrFormats.td:59 |
| 603 | ATOMIC_RMW8_U_OR_I32_A64_S = 588, // WebAssemblyInstrFormats.td:61 |
| 604 | ATOMIC_RMW8_U_OR_I64_A32 = 589, // WebAssemblyInstrFormats.td:59 |
| 605 | ATOMIC_RMW8_U_OR_I64_A32_S = 590, // WebAssemblyInstrFormats.td:61 |
| 606 | ATOMIC_RMW8_U_OR_I64_A64 = 591, // WebAssemblyInstrFormats.td:59 |
| 607 | ATOMIC_RMW8_U_OR_I64_A64_S = 592, // WebAssemblyInstrFormats.td:61 |
| 608 | ATOMIC_RMW8_U_SUB_I32_A32 = 593, // WebAssemblyInstrFormats.td:59 |
| 609 | ATOMIC_RMW8_U_SUB_I32_A32_S = 594, // WebAssemblyInstrFormats.td:61 |
| 610 | ATOMIC_RMW8_U_SUB_I32_A64 = 595, // WebAssemblyInstrFormats.td:59 |
| 611 | ATOMIC_RMW8_U_SUB_I32_A64_S = 596, // WebAssemblyInstrFormats.td:61 |
| 612 | ATOMIC_RMW8_U_SUB_I64_A32 = 597, // WebAssemblyInstrFormats.td:59 |
| 613 | ATOMIC_RMW8_U_SUB_I64_A32_S = 598, // WebAssemblyInstrFormats.td:61 |
| 614 | ATOMIC_RMW8_U_SUB_I64_A64 = 599, // WebAssemblyInstrFormats.td:59 |
| 615 | ATOMIC_RMW8_U_SUB_I64_A64_S = 600, // WebAssemblyInstrFormats.td:61 |
| 616 | ATOMIC_RMW8_U_XCHG_I32_A32 = 601, // WebAssemblyInstrFormats.td:59 |
| 617 | ATOMIC_RMW8_U_XCHG_I32_A32_S = 602, // WebAssemblyInstrFormats.td:61 |
| 618 | ATOMIC_RMW8_U_XCHG_I32_A64 = 603, // WebAssemblyInstrFormats.td:59 |
| 619 | ATOMIC_RMW8_U_XCHG_I32_A64_S = 604, // WebAssemblyInstrFormats.td:61 |
| 620 | ATOMIC_RMW8_U_XCHG_I64_A32 = 605, // WebAssemblyInstrFormats.td:59 |
| 621 | ATOMIC_RMW8_U_XCHG_I64_A32_S = 606, // WebAssemblyInstrFormats.td:61 |
| 622 | ATOMIC_RMW8_U_XCHG_I64_A64 = 607, // WebAssemblyInstrFormats.td:59 |
| 623 | ATOMIC_RMW8_U_XCHG_I64_A64_S = 608, // WebAssemblyInstrFormats.td:61 |
| 624 | ATOMIC_RMW8_U_XOR_I32_A32 = 609, // WebAssemblyInstrFormats.td:59 |
| 625 | ATOMIC_RMW8_U_XOR_I32_A32_S = 610, // WebAssemblyInstrFormats.td:61 |
| 626 | ATOMIC_RMW8_U_XOR_I32_A64 = 611, // WebAssemblyInstrFormats.td:59 |
| 627 | ATOMIC_RMW8_U_XOR_I32_A64_S = 612, // WebAssemblyInstrFormats.td:61 |
| 628 | ATOMIC_RMW8_U_XOR_I64_A32 = 613, // WebAssemblyInstrFormats.td:59 |
| 629 | ATOMIC_RMW8_U_XOR_I64_A32_S = 614, // WebAssemblyInstrFormats.td:61 |
| 630 | ATOMIC_RMW8_U_XOR_I64_A64 = 615, // WebAssemblyInstrFormats.td:59 |
| 631 | ATOMIC_RMW8_U_XOR_I64_A64_S = 616, // WebAssemblyInstrFormats.td:61 |
| 632 | ATOMIC_RMW_ADD_I32_A32 = 617, // WebAssemblyInstrFormats.td:59 |
| 633 | ATOMIC_RMW_ADD_I32_A32_S = 618, // WebAssemblyInstrFormats.td:61 |
| 634 | ATOMIC_RMW_ADD_I32_A64 = 619, // WebAssemblyInstrFormats.td:59 |
| 635 | ATOMIC_RMW_ADD_I32_A64_S = 620, // WebAssemblyInstrFormats.td:61 |
| 636 | ATOMIC_RMW_ADD_I64_A32 = 621, // WebAssemblyInstrFormats.td:59 |
| 637 | ATOMIC_RMW_ADD_I64_A32_S = 622, // WebAssemblyInstrFormats.td:61 |
| 638 | ATOMIC_RMW_ADD_I64_A64 = 623, // WebAssemblyInstrFormats.td:59 |
| 639 | ATOMIC_RMW_ADD_I64_A64_S = 624, // WebAssemblyInstrFormats.td:61 |
| 640 | ATOMIC_RMW_AND_I32_A32 = 625, // WebAssemblyInstrFormats.td:59 |
| 641 | ATOMIC_RMW_AND_I32_A32_S = 626, // WebAssemblyInstrFormats.td:61 |
| 642 | ATOMIC_RMW_AND_I32_A64 = 627, // WebAssemblyInstrFormats.td:59 |
| 643 | ATOMIC_RMW_AND_I32_A64_S = 628, // WebAssemblyInstrFormats.td:61 |
| 644 | ATOMIC_RMW_AND_I64_A32 = 629, // WebAssemblyInstrFormats.td:59 |
| 645 | ATOMIC_RMW_AND_I64_A32_S = 630, // WebAssemblyInstrFormats.td:61 |
| 646 | ATOMIC_RMW_AND_I64_A64 = 631, // WebAssemblyInstrFormats.td:59 |
| 647 | ATOMIC_RMW_AND_I64_A64_S = 632, // WebAssemblyInstrFormats.td:61 |
| 648 | ATOMIC_RMW_CMPXCHG_I32_A32 = 633, // WebAssemblyInstrFormats.td:59 |
| 649 | ATOMIC_RMW_CMPXCHG_I32_A32_S = 634, // WebAssemblyInstrFormats.td:61 |
| 650 | ATOMIC_RMW_CMPXCHG_I32_A64 = 635, // WebAssemblyInstrFormats.td:59 |
| 651 | ATOMIC_RMW_CMPXCHG_I32_A64_S = 636, // WebAssemblyInstrFormats.td:61 |
| 652 | ATOMIC_RMW_CMPXCHG_I64_A32 = 637, // WebAssemblyInstrFormats.td:59 |
| 653 | ATOMIC_RMW_CMPXCHG_I64_A32_S = 638, // WebAssemblyInstrFormats.td:61 |
| 654 | ATOMIC_RMW_CMPXCHG_I64_A64 = 639, // WebAssemblyInstrFormats.td:59 |
| 655 | ATOMIC_RMW_CMPXCHG_I64_A64_S = 640, // WebAssemblyInstrFormats.td:61 |
| 656 | ATOMIC_RMW_OR_I32_A32 = 641, // WebAssemblyInstrFormats.td:59 |
| 657 | ATOMIC_RMW_OR_I32_A32_S = 642, // WebAssemblyInstrFormats.td:61 |
| 658 | ATOMIC_RMW_OR_I32_A64 = 643, // WebAssemblyInstrFormats.td:59 |
| 659 | ATOMIC_RMW_OR_I32_A64_S = 644, // WebAssemblyInstrFormats.td:61 |
| 660 | ATOMIC_RMW_OR_I64_A32 = 645, // WebAssemblyInstrFormats.td:59 |
| 661 | ATOMIC_RMW_OR_I64_A32_S = 646, // WebAssemblyInstrFormats.td:61 |
| 662 | ATOMIC_RMW_OR_I64_A64 = 647, // WebAssemblyInstrFormats.td:59 |
| 663 | ATOMIC_RMW_OR_I64_A64_S = 648, // WebAssemblyInstrFormats.td:61 |
| 664 | ATOMIC_RMW_SUB_I32_A32 = 649, // WebAssemblyInstrFormats.td:59 |
| 665 | ATOMIC_RMW_SUB_I32_A32_S = 650, // WebAssemblyInstrFormats.td:61 |
| 666 | ATOMIC_RMW_SUB_I32_A64 = 651, // WebAssemblyInstrFormats.td:59 |
| 667 | ATOMIC_RMW_SUB_I32_A64_S = 652, // WebAssemblyInstrFormats.td:61 |
| 668 | ATOMIC_RMW_SUB_I64_A32 = 653, // WebAssemblyInstrFormats.td:59 |
| 669 | ATOMIC_RMW_SUB_I64_A32_S = 654, // WebAssemblyInstrFormats.td:61 |
| 670 | ATOMIC_RMW_SUB_I64_A64 = 655, // WebAssemblyInstrFormats.td:59 |
| 671 | ATOMIC_RMW_SUB_I64_A64_S = 656, // WebAssemblyInstrFormats.td:61 |
| 672 | ATOMIC_RMW_XCHG_I32_A32 = 657, // WebAssemblyInstrFormats.td:59 |
| 673 | ATOMIC_RMW_XCHG_I32_A32_S = 658, // WebAssemblyInstrFormats.td:61 |
| 674 | ATOMIC_RMW_XCHG_I32_A64 = 659, // WebAssemblyInstrFormats.td:59 |
| 675 | ATOMIC_RMW_XCHG_I32_A64_S = 660, // WebAssemblyInstrFormats.td:61 |
| 676 | ATOMIC_RMW_XCHG_I64_A32 = 661, // WebAssemblyInstrFormats.td:59 |
| 677 | ATOMIC_RMW_XCHG_I64_A32_S = 662, // WebAssemblyInstrFormats.td:61 |
| 678 | ATOMIC_RMW_XCHG_I64_A64 = 663, // WebAssemblyInstrFormats.td:59 |
| 679 | ATOMIC_RMW_XCHG_I64_A64_S = 664, // WebAssemblyInstrFormats.td:61 |
| 680 | ATOMIC_RMW_XOR_I32_A32 = 665, // WebAssemblyInstrFormats.td:59 |
| 681 | ATOMIC_RMW_XOR_I32_A32_S = 666, // WebAssemblyInstrFormats.td:61 |
| 682 | ATOMIC_RMW_XOR_I32_A64 = 667, // WebAssemblyInstrFormats.td:59 |
| 683 | ATOMIC_RMW_XOR_I32_A64_S = 668, // WebAssemblyInstrFormats.td:61 |
| 684 | ATOMIC_RMW_XOR_I64_A32 = 669, // WebAssemblyInstrFormats.td:59 |
| 685 | ATOMIC_RMW_XOR_I64_A32_S = 670, // WebAssemblyInstrFormats.td:61 |
| 686 | ATOMIC_RMW_XOR_I64_A64 = 671, // WebAssemblyInstrFormats.td:59 |
| 687 | ATOMIC_RMW_XOR_I64_A64_S = 672, // WebAssemblyInstrFormats.td:61 |
| 688 | ATOMIC_STORE16_I32_A32 = 673, // WebAssemblyInstrFormats.td:59 |
| 689 | ATOMIC_STORE16_I32_A32_S = 674, // WebAssemblyInstrFormats.td:61 |
| 690 | ATOMIC_STORE16_I32_A64 = 675, // WebAssemblyInstrFormats.td:59 |
| 691 | ATOMIC_STORE16_I32_A64_S = 676, // WebAssemblyInstrFormats.td:61 |
| 692 | ATOMIC_STORE16_I64_A32 = 677, // WebAssemblyInstrFormats.td:59 |
| 693 | ATOMIC_STORE16_I64_A32_S = 678, // WebAssemblyInstrFormats.td:61 |
| 694 | ATOMIC_STORE16_I64_A64 = 679, // WebAssemblyInstrFormats.td:59 |
| 695 | ATOMIC_STORE16_I64_A64_S = 680, // WebAssemblyInstrFormats.td:61 |
| 696 | ATOMIC_STORE32_I64_A32 = 681, // WebAssemblyInstrFormats.td:59 |
| 697 | ATOMIC_STORE32_I64_A32_S = 682, // WebAssemblyInstrFormats.td:61 |
| 698 | ATOMIC_STORE32_I64_A64 = 683, // WebAssemblyInstrFormats.td:59 |
| 699 | ATOMIC_STORE32_I64_A64_S = 684, // WebAssemblyInstrFormats.td:61 |
| 700 | ATOMIC_STORE8_I32_A32 = 685, // WebAssemblyInstrFormats.td:59 |
| 701 | ATOMIC_STORE8_I32_A32_S = 686, // WebAssemblyInstrFormats.td:61 |
| 702 | ATOMIC_STORE8_I32_A64 = 687, // WebAssemblyInstrFormats.td:59 |
| 703 | ATOMIC_STORE8_I32_A64_S = 688, // WebAssemblyInstrFormats.td:61 |
| 704 | ATOMIC_STORE8_I64_A32 = 689, // WebAssemblyInstrFormats.td:59 |
| 705 | ATOMIC_STORE8_I64_A32_S = 690, // WebAssemblyInstrFormats.td:61 |
| 706 | ATOMIC_STORE8_I64_A64 = 691, // WebAssemblyInstrFormats.td:59 |
| 707 | ATOMIC_STORE8_I64_A64_S = 692, // WebAssemblyInstrFormats.td:61 |
| 708 | ATOMIC_STORE_I32_A32 = 693, // WebAssemblyInstrFormats.td:59 |
| 709 | ATOMIC_STORE_I32_A32_S = 694, // WebAssemblyInstrFormats.td:61 |
| 710 | ATOMIC_STORE_I32_A64 = 695, // WebAssemblyInstrFormats.td:59 |
| 711 | ATOMIC_STORE_I32_A64_S = 696, // WebAssemblyInstrFormats.td:61 |
| 712 | ATOMIC_STORE_I64_A32 = 697, // WebAssemblyInstrFormats.td:59 |
| 713 | ATOMIC_STORE_I64_A32_S = 698, // WebAssemblyInstrFormats.td:61 |
| 714 | ATOMIC_STORE_I64_A64 = 699, // WebAssemblyInstrFormats.td:59 |
| 715 | ATOMIC_STORE_I64_A64_S = 700, // WebAssemblyInstrFormats.td:61 |
| 716 | AVGR_U_I16x8 = 701, // WebAssemblyInstrFormats.td:59 |
| 717 | AVGR_U_I16x8_S = 702, // WebAssemblyInstrFormats.td:61 |
| 718 | AVGR_U_I8x16 = 703, // WebAssemblyInstrFormats.td:59 |
| 719 | AVGR_U_I8x16_S = 704, // WebAssemblyInstrFormats.td:61 |
| 720 | BITMASK_I16x8 = 705, // WebAssemblyInstrFormats.td:59 |
| 721 | BITMASK_I16x8_S = 706, // WebAssemblyInstrFormats.td:61 |
| 722 | BITMASK_I32x4 = 707, // WebAssemblyInstrFormats.td:59 |
| 723 | BITMASK_I32x4_S = 708, // WebAssemblyInstrFormats.td:61 |
| 724 | BITMASK_I64x2 = 709, // WebAssemblyInstrFormats.td:59 |
| 725 | BITMASK_I64x2_S = 710, // WebAssemblyInstrFormats.td:61 |
| 726 | BITMASK_I8x16 = 711, // WebAssemblyInstrFormats.td:59 |
| 727 | BITMASK_I8x16_S = 712, // WebAssemblyInstrFormats.td:61 |
| 728 | BITSELECT = 713, // WebAssemblyInstrFormats.td:59 |
| 729 | BITSELECT_S = 714, // WebAssemblyInstrFormats.td:61 |
| 730 | BLOCK = 715, // WebAssemblyInstrFormats.td:59 |
| 731 | BLOCK_S = 716, // WebAssemblyInstrFormats.td:61 |
| 732 | BR = 717, // WebAssemblyInstrFormats.td:59 |
| 733 | BR_IF = 718, // WebAssemblyInstrFormats.td:59 |
| 734 | BR_IF_S = 719, // WebAssemblyInstrFormats.td:61 |
| 735 | BR_S = 720, // WebAssemblyInstrFormats.td:61 |
| 736 | BR_TABLE_I32 = 721, // WebAssemblyInstrFormats.td:59 |
| 737 | BR_TABLE_I32_S = 722, // WebAssemblyInstrFormats.td:61 |
| 738 | BR_TABLE_I64 = 723, // WebAssemblyInstrFormats.td:59 |
| 739 | BR_TABLE_I64_S = 724, // WebAssemblyInstrFormats.td:61 |
| 740 | BR_UNLESS = 725, // WebAssemblyInstrFormats.td:59 |
| 741 | BR_UNLESS_S = 726, // WebAssemblyInstrFormats.td:61 |
| 742 | CALL = 727, // WebAssemblyInstrFormats.td:59 |
| 743 | CALL_INDIRECT = 728, // WebAssemblyInstrFormats.td:59 |
| 744 | CALL_INDIRECT_S = 729, // WebAssemblyInstrFormats.td:61 |
| 745 | CALL_REF = 730, // WebAssemblyInstrFormats.td:59 |
| 746 | CALL_REF_S = 731, // WebAssemblyInstrFormats.td:61 |
| 747 | CALL_S = 732, // WebAssemblyInstrFormats.td:61 |
| 748 | CATCH = 733, // WebAssemblyInstrFormats.td:59 |
| 749 | CATCH_ALL = 734, // WebAssemblyInstrFormats.td:59 |
| 750 | CATCH_ALL_LEGACY = 735, // WebAssemblyInstrFormats.td:59 |
| 751 | CATCH_ALL_LEGACY_S = 736, // WebAssemblyInstrFormats.td:61 |
| 752 | CATCH_ALL_REF = 737, // WebAssemblyInstrFormats.td:59 |
| 753 | CATCH_ALL_REF_S = 738, // WebAssemblyInstrFormats.td:61 |
| 754 | CATCH_ALL_S = 739, // WebAssemblyInstrFormats.td:61 |
| 755 | CATCH_LEGACY = 740, // WebAssemblyInstrFormats.td:59 |
| 756 | CATCH_LEGACY_S = 741, // WebAssemblyInstrFormats.td:61 |
| 757 | CATCH_REF = 742, // WebAssemblyInstrFormats.td:59 |
| 758 | CATCH_REF_S = 743, // WebAssemblyInstrFormats.td:61 |
| 759 | CATCH_S = 744, // WebAssemblyInstrFormats.td:61 |
| 760 | CEIL_F16x8 = 745, // WebAssemblyInstrFormats.td:59 |
| 761 | CEIL_F16x8_S = 746, // WebAssemblyInstrFormats.td:61 |
| 762 | CEIL_F32 = 747, // WebAssemblyInstrFormats.td:59 |
| 763 | CEIL_F32_S = 748, // WebAssemblyInstrFormats.td:61 |
| 764 | CEIL_F32x4 = 749, // WebAssemblyInstrFormats.td:59 |
| 765 | CEIL_F32x4_S = 750, // WebAssemblyInstrFormats.td:61 |
| 766 | CEIL_F64 = 751, // WebAssemblyInstrFormats.td:59 |
| 767 | CEIL_F64_S = 752, // WebAssemblyInstrFormats.td:61 |
| 768 | CEIL_F64x2 = 753, // WebAssemblyInstrFormats.td:59 |
| 769 | CEIL_F64x2_S = 754, // WebAssemblyInstrFormats.td:61 |
| 770 | CLZ_I32 = 755, // WebAssemblyInstrFormats.td:59 |
| 771 | CLZ_I32_S = 756, // WebAssemblyInstrFormats.td:61 |
| 772 | CLZ_I64 = 757, // WebAssemblyInstrFormats.td:59 |
| 773 | CLZ_I64_S = 758, // WebAssemblyInstrFormats.td:61 |
| 774 | CONST_F32 = 759, // WebAssemblyInstrFormats.td:59 |
| 775 | CONST_F32_S = 760, // WebAssemblyInstrFormats.td:61 |
| 776 | CONST_F64 = 761, // WebAssemblyInstrFormats.td:59 |
| 777 | CONST_F64_S = 762, // WebAssemblyInstrFormats.td:61 |
| 778 | CONST_I32 = 763, // WebAssemblyInstrFormats.td:59 |
| 779 | CONST_I32_S = 764, // WebAssemblyInstrFormats.td:61 |
| 780 | CONST_I64 = 765, // WebAssemblyInstrFormats.td:59 |
| 781 | CONST_I64_S = 766, // WebAssemblyInstrFormats.td:61 |
| 782 | CONST_V128_F32x4 = 767, // WebAssemblyInstrFormats.td:59 |
| 783 | CONST_V128_F32x4_S = 768, // WebAssemblyInstrFormats.td:61 |
| 784 | CONST_V128_F64x2 = 769, // WebAssemblyInstrFormats.td:59 |
| 785 | CONST_V128_F64x2_S = 770, // WebAssemblyInstrFormats.td:61 |
| 786 | CONST_V128_I16x8 = 771, // WebAssemblyInstrFormats.td:59 |
| 787 | CONST_V128_I16x8_S = 772, // WebAssemblyInstrFormats.td:61 |
| 788 | CONST_V128_I32x4 = 773, // WebAssemblyInstrFormats.td:59 |
| 789 | CONST_V128_I32x4_S = 774, // WebAssemblyInstrFormats.td:61 |
| 790 | CONST_V128_I64x2 = 775, // WebAssemblyInstrFormats.td:59 |
| 791 | CONST_V128_I64x2_S = 776, // WebAssemblyInstrFormats.td:61 |
| 792 | CONST_V128_I8x16 = 777, // WebAssemblyInstrFormats.td:59 |
| 793 | CONST_V128_I8x16_S = 778, // WebAssemblyInstrFormats.td:61 |
| 794 | COPYSIGN_F32 = 779, // WebAssemblyInstrFormats.td:59 |
| 795 | COPYSIGN_F32_S = 780, // WebAssemblyInstrFormats.td:61 |
| 796 | COPYSIGN_F64 = 781, // WebAssemblyInstrFormats.td:59 |
| 797 | COPYSIGN_F64_S = 782, // WebAssemblyInstrFormats.td:61 |
| 798 | COPY_EXNREF = 783, // WebAssemblyInstrFormats.td:59 |
| 799 | COPY_EXNREF_S = 784, // WebAssemblyInstrFormats.td:61 |
| 800 | COPY_EXTERNREF = 785, // WebAssemblyInstrFormats.td:59 |
| 801 | COPY_EXTERNREF_S = 786, // WebAssemblyInstrFormats.td:61 |
| 802 | COPY_F32 = 787, // WebAssemblyInstrFormats.td:59 |
| 803 | COPY_F32_S = 788, // WebAssemblyInstrFormats.td:61 |
| 804 | COPY_F64 = 789, // WebAssemblyInstrFormats.td:59 |
| 805 | COPY_F64_S = 790, // WebAssemblyInstrFormats.td:61 |
| 806 | COPY_FUNCREF = 791, // WebAssemblyInstrFormats.td:59 |
| 807 | COPY_FUNCREF_S = 792, // WebAssemblyInstrFormats.td:61 |
| 808 | COPY_I32 = 793, // WebAssemblyInstrFormats.td:59 |
| 809 | COPY_I32_S = 794, // WebAssemblyInstrFormats.td:61 |
| 810 | COPY_I64 = 795, // WebAssemblyInstrFormats.td:59 |
| 811 | COPY_I64_S = 796, // WebAssemblyInstrFormats.td:61 |
| 812 | COPY_V128 = 797, // WebAssemblyInstrFormats.td:59 |
| 813 | COPY_V128_S = 798, // WebAssemblyInstrFormats.td:61 |
| 814 | CTZ_I32 = 799, // WebAssemblyInstrFormats.td:59 |
| 815 | CTZ_I32_S = 800, // WebAssemblyInstrFormats.td:61 |
| 816 | CTZ_I64 = 801, // WebAssemblyInstrFormats.td:59 |
| 817 | CTZ_I64_S = 802, // WebAssemblyInstrFormats.td:61 |
| 818 | DATA_DROP = 803, // WebAssemblyInstrFormats.td:59 |
| 819 | DATA_DROP_S = 804, // WebAssemblyInstrFormats.td:61 |
| 820 | DEBUG_UNREACHABLE = 805, // WebAssemblyInstrFormats.td:59 |
| 821 | DEBUG_UNREACHABLE_S = 806, // WebAssemblyInstrFormats.td:61 |
| 822 | DELEGATE = 807, // WebAssemblyInstrFormats.td:59 |
| 823 | DELEGATE_S = 808, // WebAssemblyInstrFormats.td:61 |
| 824 | DIV_F16x8 = 809, // WebAssemblyInstrFormats.td:59 |
| 825 | DIV_F16x8_S = 810, // WebAssemblyInstrFormats.td:61 |
| 826 | DIV_F32 = 811, // WebAssemblyInstrFormats.td:59 |
| 827 | DIV_F32_S = 812, // WebAssemblyInstrFormats.td:61 |
| 828 | DIV_F32x4 = 813, // WebAssemblyInstrFormats.td:59 |
| 829 | DIV_F32x4_S = 814, // WebAssemblyInstrFormats.td:61 |
| 830 | DIV_F64 = 815, // WebAssemblyInstrFormats.td:59 |
| 831 | DIV_F64_S = 816, // WebAssemblyInstrFormats.td:61 |
| 832 | DIV_F64x2 = 817, // WebAssemblyInstrFormats.td:59 |
| 833 | DIV_F64x2_S = 818, // WebAssemblyInstrFormats.td:61 |
| 834 | DIV_S_I32 = 819, // WebAssemblyInstrFormats.td:59 |
| 835 | DIV_S_I32_S = 820, // WebAssemblyInstrFormats.td:61 |
| 836 | DIV_S_I64 = 821, // WebAssemblyInstrFormats.td:59 |
| 837 | DIV_S_I64_S = 822, // WebAssemblyInstrFormats.td:61 |
| 838 | DIV_U_I32 = 823, // WebAssemblyInstrFormats.td:59 |
| 839 | DIV_U_I32_S = 824, // WebAssemblyInstrFormats.td:61 |
| 840 | DIV_U_I64 = 825, // WebAssemblyInstrFormats.td:59 |
| 841 | DIV_U_I64_S = 826, // WebAssemblyInstrFormats.td:61 |
| 842 | DOT = 827, // WebAssemblyInstrFormats.td:59 |
| 843 | DOT_S = 828, // WebAssemblyInstrFormats.td:61 |
| 844 | DROP_EXNREF = 829, // WebAssemblyInstrFormats.td:59 |
| 845 | DROP_EXNREF_S = 830, // WebAssemblyInstrFormats.td:61 |
| 846 | DROP_EXTERNREF = 831, // WebAssemblyInstrFormats.td:59 |
| 847 | DROP_EXTERNREF_S = 832, // WebAssemblyInstrFormats.td:61 |
| 848 | DROP_F32 = 833, // WebAssemblyInstrFormats.td:59 |
| 849 | DROP_F32_S = 834, // WebAssemblyInstrFormats.td:61 |
| 850 | DROP_F64 = 835, // WebAssemblyInstrFormats.td:59 |
| 851 | DROP_F64_S = 836, // WebAssemblyInstrFormats.td:61 |
| 852 | DROP_FUNCREF = 837, // WebAssemblyInstrFormats.td:59 |
| 853 | DROP_FUNCREF_S = 838, // WebAssemblyInstrFormats.td:61 |
| 854 | DROP_I32 = 839, // WebAssemblyInstrFormats.td:59 |
| 855 | DROP_I32_S = 840, // WebAssemblyInstrFormats.td:61 |
| 856 | DROP_I64 = 841, // WebAssemblyInstrFormats.td:59 |
| 857 | DROP_I64_S = 842, // WebAssemblyInstrFormats.td:61 |
| 858 | DROP_V128 = 843, // WebAssemblyInstrFormats.td:59 |
| 859 | DROP_V128_S = 844, // WebAssemblyInstrFormats.td:61 |
| 860 | ELSE = 845, // WebAssemblyInstrFormats.td:59 |
| 861 | ELSE_S = 846, // WebAssemblyInstrFormats.td:61 |
| 862 | END = 847, // WebAssemblyInstrFormats.td:59 |
| 863 | END_BLOCK = 848, // WebAssemblyInstrFormats.td:59 |
| 864 | END_BLOCK_S = 849, // WebAssemblyInstrFormats.td:61 |
| 865 | END_FUNCTION = 850, // WebAssemblyInstrFormats.td:59 |
| 866 | END_FUNCTION_S = 851, // WebAssemblyInstrFormats.td:61 |
| 867 | END_IF = 852, // WebAssemblyInstrFormats.td:59 |
| 868 | END_IF_S = 853, // WebAssemblyInstrFormats.td:61 |
| 869 | END_LOOP = 854, // WebAssemblyInstrFormats.td:59 |
| 870 | END_LOOP_S = 855, // WebAssemblyInstrFormats.td:61 |
| 871 | END_S = 856, // WebAssemblyInstrFormats.td:61 |
| 872 | END_TRY = 857, // WebAssemblyInstrFormats.td:59 |
| 873 | END_TRY_S = 858, // WebAssemblyInstrFormats.td:61 |
| 874 | END_TRY_TABLE = 859, // WebAssemblyInstrFormats.td:59 |
| 875 | END_TRY_TABLE_S = 860, // WebAssemblyInstrFormats.td:61 |
| 876 | EQZ_I32 = 861, // WebAssemblyInstrFormats.td:59 |
| 877 | EQZ_I32_S = 862, // WebAssemblyInstrFormats.td:61 |
| 878 | EQZ_I64 = 863, // WebAssemblyInstrFormats.td:59 |
| 879 | EQZ_I64_S = 864, // WebAssemblyInstrFormats.td:61 |
| 880 | EQ_F16x8 = 865, // WebAssemblyInstrFormats.td:59 |
| 881 | EQ_F16x8_S = 866, // WebAssemblyInstrFormats.td:61 |
| 882 | EQ_F32 = 867, // WebAssemblyInstrFormats.td:59 |
| 883 | EQ_F32_S = 868, // WebAssemblyInstrFormats.td:61 |
| 884 | EQ_F32x4 = 869, // WebAssemblyInstrFormats.td:59 |
| 885 | EQ_F32x4_S = 870, // WebAssemblyInstrFormats.td:61 |
| 886 | EQ_F64 = 871, // WebAssemblyInstrFormats.td:59 |
| 887 | EQ_F64_S = 872, // WebAssemblyInstrFormats.td:61 |
| 888 | EQ_F64x2 = 873, // WebAssemblyInstrFormats.td:59 |
| 889 | EQ_F64x2_S = 874, // WebAssemblyInstrFormats.td:61 |
| 890 | EQ_I16x8 = 875, // WebAssemblyInstrFormats.td:59 |
| 891 | EQ_I16x8_S = 876, // WebAssemblyInstrFormats.td:61 |
| 892 | EQ_I32 = 877, // WebAssemblyInstrFormats.td:59 |
| 893 | EQ_I32_S = 878, // WebAssemblyInstrFormats.td:61 |
| 894 | EQ_I32x4 = 879, // WebAssemblyInstrFormats.td:59 |
| 895 | EQ_I32x4_S = 880, // WebAssemblyInstrFormats.td:61 |
| 896 | EQ_I64 = 881, // WebAssemblyInstrFormats.td:59 |
| 897 | EQ_I64_S = 882, // WebAssemblyInstrFormats.td:61 |
| 898 | EQ_I64x2 = 883, // WebAssemblyInstrFormats.td:59 |
| 899 | EQ_I64x2_S = 884, // WebAssemblyInstrFormats.td:61 |
| 900 | EQ_I8x16 = 885, // WebAssemblyInstrFormats.td:59 |
| 901 | EQ_I8x16_S = 886, // WebAssemblyInstrFormats.td:61 |
| 902 | EXTMUL_HIGH_S_I16x8 = 887, // WebAssemblyInstrFormats.td:59 |
| 903 | EXTMUL_HIGH_S_I16x8_S = 888, // WebAssemblyInstrFormats.td:61 |
| 904 | EXTMUL_HIGH_S_I32x4 = 889, // WebAssemblyInstrFormats.td:59 |
| 905 | EXTMUL_HIGH_S_I32x4_S = 890, // WebAssemblyInstrFormats.td:61 |
| 906 | EXTMUL_HIGH_S_I64x2 = 891, // WebAssemblyInstrFormats.td:59 |
| 907 | EXTMUL_HIGH_S_I64x2_S = 892, // WebAssemblyInstrFormats.td:61 |
| 908 | EXTMUL_HIGH_U_I16x8 = 893, // WebAssemblyInstrFormats.td:59 |
| 909 | EXTMUL_HIGH_U_I16x8_S = 894, // WebAssemblyInstrFormats.td:61 |
| 910 | EXTMUL_HIGH_U_I32x4 = 895, // WebAssemblyInstrFormats.td:59 |
| 911 | EXTMUL_HIGH_U_I32x4_S = 896, // WebAssemblyInstrFormats.td:61 |
| 912 | EXTMUL_HIGH_U_I64x2 = 897, // WebAssemblyInstrFormats.td:59 |
| 913 | EXTMUL_HIGH_U_I64x2_S = 898, // WebAssemblyInstrFormats.td:61 |
| 914 | EXTMUL_LOW_S_I16x8 = 899, // WebAssemblyInstrFormats.td:59 |
| 915 | EXTMUL_LOW_S_I16x8_S = 900, // WebAssemblyInstrFormats.td:61 |
| 916 | EXTMUL_LOW_S_I32x4 = 901, // WebAssemblyInstrFormats.td:59 |
| 917 | EXTMUL_LOW_S_I32x4_S = 902, // WebAssemblyInstrFormats.td:61 |
| 918 | EXTMUL_LOW_S_I64x2 = 903, // WebAssemblyInstrFormats.td:59 |
| 919 | EXTMUL_LOW_S_I64x2_S = 904, // WebAssemblyInstrFormats.td:61 |
| 920 | EXTMUL_LOW_U_I16x8 = 905, // WebAssemblyInstrFormats.td:59 |
| 921 | EXTMUL_LOW_U_I16x8_S = 906, // WebAssemblyInstrFormats.td:61 |
| 922 | EXTMUL_LOW_U_I32x4 = 907, // WebAssemblyInstrFormats.td:59 |
| 923 | EXTMUL_LOW_U_I32x4_S = 908, // WebAssemblyInstrFormats.td:61 |
| 924 | EXTMUL_LOW_U_I64x2 = 909, // WebAssemblyInstrFormats.td:59 |
| 925 | EXTMUL_LOW_U_I64x2_S = 910, // WebAssemblyInstrFormats.td:61 |
| 926 | EXTRACT_LANE_F16x8 = 911, // WebAssemblyInstrFormats.td:59 |
| 927 | EXTRACT_LANE_F16x8_S = 912, // WebAssemblyInstrFormats.td:61 |
| 928 | EXTRACT_LANE_F32x4 = 913, // WebAssemblyInstrFormats.td:59 |
| 929 | EXTRACT_LANE_F32x4_S = 914, // WebAssemblyInstrFormats.td:61 |
| 930 | EXTRACT_LANE_F64x2 = 915, // WebAssemblyInstrFormats.td:59 |
| 931 | EXTRACT_LANE_F64x2_S = 916, // WebAssemblyInstrFormats.td:61 |
| 932 | EXTRACT_LANE_I16x8_s = 917, // WebAssemblyInstrFormats.td:59 |
| 933 | EXTRACT_LANE_I16x8_s_S = 918, // WebAssemblyInstrFormats.td:61 |
| 934 | EXTRACT_LANE_I16x8_u = 919, // WebAssemblyInstrFormats.td:59 |
| 935 | EXTRACT_LANE_I16x8_u_S = 920, // WebAssemblyInstrFormats.td:61 |
| 936 | EXTRACT_LANE_I32x4 = 921, // WebAssemblyInstrFormats.td:59 |
| 937 | EXTRACT_LANE_I32x4_S = 922, // WebAssemblyInstrFormats.td:61 |
| 938 | EXTRACT_LANE_I64x2 = 923, // WebAssemblyInstrFormats.td:59 |
| 939 | EXTRACT_LANE_I64x2_S = 924, // WebAssemblyInstrFormats.td:61 |
| 940 | EXTRACT_LANE_I8x16_s = 925, // WebAssemblyInstrFormats.td:59 |
| 941 | EXTRACT_LANE_I8x16_s_S = 926, // WebAssemblyInstrFormats.td:61 |
| 942 | EXTRACT_LANE_I8x16_u = 927, // WebAssemblyInstrFormats.td:59 |
| 943 | EXTRACT_LANE_I8x16_u_S = 928, // WebAssemblyInstrFormats.td:61 |
| 944 | F32_CONVERT_S_I32 = 929, // WebAssemblyInstrFormats.td:59 |
| 945 | F32_CONVERT_S_I32_S = 930, // WebAssemblyInstrFormats.td:61 |
| 946 | F32_CONVERT_S_I64 = 931, // WebAssemblyInstrFormats.td:59 |
| 947 | F32_CONVERT_S_I64_S = 932, // WebAssemblyInstrFormats.td:61 |
| 948 | F32_CONVERT_U_I32 = 933, // WebAssemblyInstrFormats.td:59 |
| 949 | F32_CONVERT_U_I32_S = 934, // WebAssemblyInstrFormats.td:61 |
| 950 | F32_CONVERT_U_I64 = 935, // WebAssemblyInstrFormats.td:59 |
| 951 | F32_CONVERT_U_I64_S = 936, // WebAssemblyInstrFormats.td:61 |
| 952 | F32_DEMOTE_F64 = 937, // WebAssemblyInstrFormats.td:59 |
| 953 | F32_DEMOTE_F64_S = 938, // WebAssemblyInstrFormats.td:61 |
| 954 | F32_REINTERPRET_I32 = 939, // WebAssemblyInstrFormats.td:59 |
| 955 | F32_REINTERPRET_I32_S = 940, // WebAssemblyInstrFormats.td:61 |
| 956 | F64_CONVERT_S_I32 = 941, // WebAssemblyInstrFormats.td:59 |
| 957 | F64_CONVERT_S_I32_S = 942, // WebAssemblyInstrFormats.td:61 |
| 958 | F64_CONVERT_S_I64 = 943, // WebAssemblyInstrFormats.td:59 |
| 959 | F64_CONVERT_S_I64_S = 944, // WebAssemblyInstrFormats.td:61 |
| 960 | F64_CONVERT_U_I32 = 945, // WebAssemblyInstrFormats.td:59 |
| 961 | F64_CONVERT_U_I32_S = 946, // WebAssemblyInstrFormats.td:61 |
| 962 | F64_CONVERT_U_I64 = 947, // WebAssemblyInstrFormats.td:59 |
| 963 | F64_CONVERT_U_I64_S = 948, // WebAssemblyInstrFormats.td:61 |
| 964 | F64_PROMOTE_F32 = 949, // WebAssemblyInstrFormats.td:59 |
| 965 | F64_PROMOTE_F32_S = 950, // WebAssemblyInstrFormats.td:61 |
| 966 | F64_REINTERPRET_I64 = 951, // WebAssemblyInstrFormats.td:59 |
| 967 | F64_REINTERPRET_I64_S = 952, // WebAssemblyInstrFormats.td:61 |
| 968 | FALLTHROUGH_RETURN = 953, // WebAssemblyInstrFormats.td:59 |
| 969 | FALLTHROUGH_RETURN_S = 954, // WebAssemblyInstrFormats.td:61 |
| 970 | FLOOR_F16x8 = 955, // WebAssemblyInstrFormats.td:59 |
| 971 | FLOOR_F16x8_S = 956, // WebAssemblyInstrFormats.td:61 |
| 972 | FLOOR_F32 = 957, // WebAssemblyInstrFormats.td:59 |
| 973 | FLOOR_F32_S = 958, // WebAssemblyInstrFormats.td:61 |
| 974 | FLOOR_F32x4 = 959, // WebAssemblyInstrFormats.td:59 |
| 975 | FLOOR_F32x4_S = 960, // WebAssemblyInstrFormats.td:61 |
| 976 | FLOOR_F64 = 961, // WebAssemblyInstrFormats.td:59 |
| 977 | FLOOR_F64_S = 962, // WebAssemblyInstrFormats.td:61 |
| 978 | FLOOR_F64x2 = 963, // WebAssemblyInstrFormats.td:59 |
| 979 | FLOOR_F64x2_S = 964, // WebAssemblyInstrFormats.td:61 |
| 980 | FP_TO_SINT_I32_F32 = 965, // WebAssemblyInstrFormats.td:59 |
| 981 | FP_TO_SINT_I32_F32_S = 966, // WebAssemblyInstrFormats.td:61 |
| 982 | FP_TO_SINT_I32_F64 = 967, // WebAssemblyInstrFormats.td:59 |
| 983 | FP_TO_SINT_I32_F64_S = 968, // WebAssemblyInstrFormats.td:61 |
| 984 | FP_TO_SINT_I64_F32 = 969, // WebAssemblyInstrFormats.td:59 |
| 985 | FP_TO_SINT_I64_F32_S = 970, // WebAssemblyInstrFormats.td:61 |
| 986 | FP_TO_SINT_I64_F64 = 971, // WebAssemblyInstrFormats.td:59 |
| 987 | FP_TO_SINT_I64_F64_S = 972, // WebAssemblyInstrFormats.td:61 |
| 988 | FP_TO_UINT_I32_F32 = 973, // WebAssemblyInstrFormats.td:59 |
| 989 | FP_TO_UINT_I32_F32_S = 974, // WebAssemblyInstrFormats.td:61 |
| 990 | FP_TO_UINT_I32_F64 = 975, // WebAssemblyInstrFormats.td:59 |
| 991 | FP_TO_UINT_I32_F64_S = 976, // WebAssemblyInstrFormats.td:61 |
| 992 | FP_TO_UINT_I64_F32 = 977, // WebAssemblyInstrFormats.td:59 |
| 993 | FP_TO_UINT_I64_F32_S = 978, // WebAssemblyInstrFormats.td:61 |
| 994 | FP_TO_UINT_I64_F64 = 979, // WebAssemblyInstrFormats.td:59 |
| 995 | FP_TO_UINT_I64_F64_S = 980, // WebAssemblyInstrFormats.td:61 |
| 996 | GE_F16x8 = 981, // WebAssemblyInstrFormats.td:59 |
| 997 | GE_F16x8_S = 982, // WebAssemblyInstrFormats.td:61 |
| 998 | GE_F32 = 983, // WebAssemblyInstrFormats.td:59 |
| 999 | GE_F32_S = 984, // WebAssemblyInstrFormats.td:61 |
| 1000 | GE_F32x4 = 985, // WebAssemblyInstrFormats.td:59 |
| 1001 | GE_F32x4_S = 986, // WebAssemblyInstrFormats.td:61 |
| 1002 | GE_F64 = 987, // WebAssemblyInstrFormats.td:59 |
| 1003 | GE_F64_S = 988, // WebAssemblyInstrFormats.td:61 |
| 1004 | GE_F64x2 = 989, // WebAssemblyInstrFormats.td:59 |
| 1005 | GE_F64x2_S = 990, // WebAssemblyInstrFormats.td:61 |
| 1006 | GE_S_I16x8 = 991, // WebAssemblyInstrFormats.td:59 |
| 1007 | GE_S_I16x8_S = 992, // WebAssemblyInstrFormats.td:61 |
| 1008 | GE_S_I32 = 993, // WebAssemblyInstrFormats.td:59 |
| 1009 | GE_S_I32_S = 994, // WebAssemblyInstrFormats.td:61 |
| 1010 | GE_S_I32x4 = 995, // WebAssemblyInstrFormats.td:59 |
| 1011 | GE_S_I32x4_S = 996, // WebAssemblyInstrFormats.td:61 |
| 1012 | GE_S_I64 = 997, // WebAssemblyInstrFormats.td:59 |
| 1013 | GE_S_I64_S = 998, // WebAssemblyInstrFormats.td:61 |
| 1014 | GE_S_I64x2 = 999, // WebAssemblyInstrFormats.td:59 |
| 1015 | GE_S_I64x2_S = 1000, // WebAssemblyInstrFormats.td:61 |
| 1016 | GE_S_I8x16 = 1001, // WebAssemblyInstrFormats.td:59 |
| 1017 | GE_S_I8x16_S = 1002, // WebAssemblyInstrFormats.td:61 |
| 1018 | GE_U_I16x8 = 1003, // WebAssemblyInstrFormats.td:59 |
| 1019 | GE_U_I16x8_S = 1004, // WebAssemblyInstrFormats.td:61 |
| 1020 | GE_U_I32 = 1005, // WebAssemblyInstrFormats.td:59 |
| 1021 | GE_U_I32_S = 1006, // WebAssemblyInstrFormats.td:61 |
| 1022 | GE_U_I32x4 = 1007, // WebAssemblyInstrFormats.td:59 |
| 1023 | GE_U_I32x4_S = 1008, // WebAssemblyInstrFormats.td:61 |
| 1024 | GE_U_I64 = 1009, // WebAssemblyInstrFormats.td:59 |
| 1025 | GE_U_I64_S = 1010, // WebAssemblyInstrFormats.td:61 |
| 1026 | GE_U_I8x16 = 1011, // WebAssemblyInstrFormats.td:59 |
| 1027 | GE_U_I8x16_S = 1012, // WebAssemblyInstrFormats.td:61 |
| 1028 | GLOBAL_GET_EXNREF = 1013, // WebAssemblyInstrFormats.td:59 |
| 1029 | GLOBAL_GET_EXNREF_S = 1014, // WebAssemblyInstrFormats.td:61 |
| 1030 | GLOBAL_GET_EXTERNREF = 1015, // WebAssemblyInstrFormats.td:59 |
| 1031 | GLOBAL_GET_EXTERNREF_S = 1016, // WebAssemblyInstrFormats.td:61 |
| 1032 | GLOBAL_GET_F32 = 1017, // WebAssemblyInstrFormats.td:59 |
| 1033 | GLOBAL_GET_F32_S = 1018, // WebAssemblyInstrFormats.td:61 |
| 1034 | GLOBAL_GET_F64 = 1019, // WebAssemblyInstrFormats.td:59 |
| 1035 | GLOBAL_GET_F64_S = 1020, // WebAssemblyInstrFormats.td:61 |
| 1036 | GLOBAL_GET_FUNCREF = 1021, // WebAssemblyInstrFormats.td:59 |
| 1037 | GLOBAL_GET_FUNCREF_S = 1022, // WebAssemblyInstrFormats.td:61 |
| 1038 | GLOBAL_GET_I32 = 1023, // WebAssemblyInstrFormats.td:59 |
| 1039 | GLOBAL_GET_I32_S = 1024, // WebAssemblyInstrFormats.td:61 |
| 1040 | GLOBAL_GET_I64 = 1025, // WebAssemblyInstrFormats.td:59 |
| 1041 | GLOBAL_GET_I64_S = 1026, // WebAssemblyInstrFormats.td:61 |
| 1042 | GLOBAL_GET_V128 = 1027, // WebAssemblyInstrFormats.td:59 |
| 1043 | GLOBAL_GET_V128_S = 1028, // WebAssemblyInstrFormats.td:61 |
| 1044 | GLOBAL_SET_EXNREF = 1029, // WebAssemblyInstrFormats.td:59 |
| 1045 | GLOBAL_SET_EXNREF_S = 1030, // WebAssemblyInstrFormats.td:61 |
| 1046 | GLOBAL_SET_EXTERNREF = 1031, // WebAssemblyInstrFormats.td:59 |
| 1047 | GLOBAL_SET_EXTERNREF_S = 1032, // WebAssemblyInstrFormats.td:61 |
| 1048 | GLOBAL_SET_F32 = 1033, // WebAssemblyInstrFormats.td:59 |
| 1049 | GLOBAL_SET_F32_S = 1034, // WebAssemblyInstrFormats.td:61 |
| 1050 | GLOBAL_SET_F64 = 1035, // WebAssemblyInstrFormats.td:59 |
| 1051 | GLOBAL_SET_F64_S = 1036, // WebAssemblyInstrFormats.td:61 |
| 1052 | GLOBAL_SET_FUNCREF = 1037, // WebAssemblyInstrFormats.td:59 |
| 1053 | GLOBAL_SET_FUNCREF_S = 1038, // WebAssemblyInstrFormats.td:61 |
| 1054 | GLOBAL_SET_I32 = 1039, // WebAssemblyInstrFormats.td:59 |
| 1055 | GLOBAL_SET_I32_S = 1040, // WebAssemblyInstrFormats.td:61 |
| 1056 | GLOBAL_SET_I64 = 1041, // WebAssemblyInstrFormats.td:59 |
| 1057 | GLOBAL_SET_I64_S = 1042, // WebAssemblyInstrFormats.td:61 |
| 1058 | GLOBAL_SET_V128 = 1043, // WebAssemblyInstrFormats.td:59 |
| 1059 | GLOBAL_SET_V128_S = 1044, // WebAssemblyInstrFormats.td:61 |
| 1060 | GT_F16x8 = 1045, // WebAssemblyInstrFormats.td:59 |
| 1061 | GT_F16x8_S = 1046, // WebAssemblyInstrFormats.td:61 |
| 1062 | GT_F32 = 1047, // WebAssemblyInstrFormats.td:59 |
| 1063 | GT_F32_S = 1048, // WebAssemblyInstrFormats.td:61 |
| 1064 | GT_F32x4 = 1049, // WebAssemblyInstrFormats.td:59 |
| 1065 | GT_F32x4_S = 1050, // WebAssemblyInstrFormats.td:61 |
| 1066 | GT_F64 = 1051, // WebAssemblyInstrFormats.td:59 |
| 1067 | GT_F64_S = 1052, // WebAssemblyInstrFormats.td:61 |
| 1068 | GT_F64x2 = 1053, // WebAssemblyInstrFormats.td:59 |
| 1069 | GT_F64x2_S = 1054, // WebAssemblyInstrFormats.td:61 |
| 1070 | GT_S_I16x8 = 1055, // WebAssemblyInstrFormats.td:59 |
| 1071 | GT_S_I16x8_S = 1056, // WebAssemblyInstrFormats.td:61 |
| 1072 | GT_S_I32 = 1057, // WebAssemblyInstrFormats.td:59 |
| 1073 | GT_S_I32_S = 1058, // WebAssemblyInstrFormats.td:61 |
| 1074 | GT_S_I32x4 = 1059, // WebAssemblyInstrFormats.td:59 |
| 1075 | GT_S_I32x4_S = 1060, // WebAssemblyInstrFormats.td:61 |
| 1076 | GT_S_I64 = 1061, // WebAssemblyInstrFormats.td:59 |
| 1077 | GT_S_I64_S = 1062, // WebAssemblyInstrFormats.td:61 |
| 1078 | GT_S_I64x2 = 1063, // WebAssemblyInstrFormats.td:59 |
| 1079 | GT_S_I64x2_S = 1064, // WebAssemblyInstrFormats.td:61 |
| 1080 | GT_S_I8x16 = 1065, // WebAssemblyInstrFormats.td:59 |
| 1081 | GT_S_I8x16_S = 1066, // WebAssemblyInstrFormats.td:61 |
| 1082 | GT_U_I16x8 = 1067, // WebAssemblyInstrFormats.td:59 |
| 1083 | GT_U_I16x8_S = 1068, // WebAssemblyInstrFormats.td:61 |
| 1084 | GT_U_I32 = 1069, // WebAssemblyInstrFormats.td:59 |
| 1085 | GT_U_I32_S = 1070, // WebAssemblyInstrFormats.td:61 |
| 1086 | GT_U_I32x4 = 1071, // WebAssemblyInstrFormats.td:59 |
| 1087 | GT_U_I32x4_S = 1072, // WebAssemblyInstrFormats.td:61 |
| 1088 | GT_U_I64 = 1073, // WebAssemblyInstrFormats.td:59 |
| 1089 | GT_U_I64_S = 1074, // WebAssemblyInstrFormats.td:61 |
| 1090 | GT_U_I8x16 = 1075, // WebAssemblyInstrFormats.td:59 |
| 1091 | GT_U_I8x16_S = 1076, // WebAssemblyInstrFormats.td:61 |
| 1092 | I32_EXTEND16_S_I32 = 1077, // WebAssemblyInstrFormats.td:59 |
| 1093 | I32_EXTEND16_S_I32_S = 1078, // WebAssemblyInstrFormats.td:61 |
| 1094 | I32_EXTEND8_S_I32 = 1079, // WebAssemblyInstrFormats.td:59 |
| 1095 | I32_EXTEND8_S_I32_S = 1080, // WebAssemblyInstrFormats.td:61 |
| 1096 | I32_REINTERPRET_F32 = 1081, // WebAssemblyInstrFormats.td:59 |
| 1097 | I32_REINTERPRET_F32_S = 1082, // WebAssemblyInstrFormats.td:61 |
| 1098 | I32_TRUNC_S_F32 = 1083, // WebAssemblyInstrFormats.td:59 |
| 1099 | I32_TRUNC_S_F32_S = 1084, // WebAssemblyInstrFormats.td:61 |
| 1100 | I32_TRUNC_S_F64 = 1085, // WebAssemblyInstrFormats.td:59 |
| 1101 | I32_TRUNC_S_F64_S = 1086, // WebAssemblyInstrFormats.td:61 |
| 1102 | I32_TRUNC_S_SAT_F32 = 1087, // WebAssemblyInstrFormats.td:59 |
| 1103 | I32_TRUNC_S_SAT_F32_S = 1088, // WebAssemblyInstrFormats.td:61 |
| 1104 | I32_TRUNC_S_SAT_F64 = 1089, // WebAssemblyInstrFormats.td:59 |
| 1105 | I32_TRUNC_S_SAT_F64_S = 1090, // WebAssemblyInstrFormats.td:61 |
| 1106 | I32_TRUNC_U_F32 = 1091, // WebAssemblyInstrFormats.td:59 |
| 1107 | I32_TRUNC_U_F32_S = 1092, // WebAssemblyInstrFormats.td:61 |
| 1108 | I32_TRUNC_U_F64 = 1093, // WebAssemblyInstrFormats.td:59 |
| 1109 | I32_TRUNC_U_F64_S = 1094, // WebAssemblyInstrFormats.td:61 |
| 1110 | I32_TRUNC_U_SAT_F32 = 1095, // WebAssemblyInstrFormats.td:59 |
| 1111 | I32_TRUNC_U_SAT_F32_S = 1096, // WebAssemblyInstrFormats.td:61 |
| 1112 | I32_TRUNC_U_SAT_F64 = 1097, // WebAssemblyInstrFormats.td:59 |
| 1113 | I32_TRUNC_U_SAT_F64_S = 1098, // WebAssemblyInstrFormats.td:61 |
| 1114 | I32_WRAP_I64 = 1099, // WebAssemblyInstrFormats.td:59 |
| 1115 | I32_WRAP_I64_S = 1100, // WebAssemblyInstrFormats.td:61 |
| 1116 | I64_ADD128 = 1101, // WebAssemblyInstrFormats.td:59 |
| 1117 | I64_ADD128_S = 1102, // WebAssemblyInstrFormats.td:61 |
| 1118 | I64_EXTEND16_S_I64 = 1103, // WebAssemblyInstrFormats.td:59 |
| 1119 | I64_EXTEND16_S_I64_S = 1104, // WebAssemblyInstrFormats.td:61 |
| 1120 | I64_EXTEND32_S_I64 = 1105, // WebAssemblyInstrFormats.td:59 |
| 1121 | I64_EXTEND32_S_I64_S = 1106, // WebAssemblyInstrFormats.td:61 |
| 1122 | I64_EXTEND8_S_I64 = 1107, // WebAssemblyInstrFormats.td:59 |
| 1123 | I64_EXTEND8_S_I64_S = 1108, // WebAssemblyInstrFormats.td:61 |
| 1124 | I64_EXTEND_S_I32 = 1109, // WebAssemblyInstrFormats.td:59 |
| 1125 | I64_EXTEND_S_I32_S = 1110, // WebAssemblyInstrFormats.td:61 |
| 1126 | I64_EXTEND_U_I32 = 1111, // WebAssemblyInstrFormats.td:59 |
| 1127 | I64_EXTEND_U_I32_S = 1112, // WebAssemblyInstrFormats.td:61 |
| 1128 | I64_MUL_WIDE_S = 1113, // WebAssemblyInstrFormats.td:59 |
| 1129 | I64_MUL_WIDE_S_S = 1114, // WebAssemblyInstrFormats.td:61 |
| 1130 | I64_MUL_WIDE_U = 1115, // WebAssemblyInstrFormats.td:59 |
| 1131 | I64_MUL_WIDE_U_S = 1116, // WebAssemblyInstrFormats.td:61 |
| 1132 | I64_REINTERPRET_F64 = 1117, // WebAssemblyInstrFormats.td:59 |
| 1133 | I64_REINTERPRET_F64_S = 1118, // WebAssemblyInstrFormats.td:61 |
| 1134 | I64_SUB128 = 1119, // WebAssemblyInstrFormats.td:59 |
| 1135 | I64_SUB128_S = 1120, // WebAssemblyInstrFormats.td:61 |
| 1136 | I64_TRUNC_S_F32 = 1121, // WebAssemblyInstrFormats.td:59 |
| 1137 | I64_TRUNC_S_F32_S = 1122, // WebAssemblyInstrFormats.td:61 |
| 1138 | I64_TRUNC_S_F64 = 1123, // WebAssemblyInstrFormats.td:59 |
| 1139 | I64_TRUNC_S_F64_S = 1124, // WebAssemblyInstrFormats.td:61 |
| 1140 | I64_TRUNC_S_SAT_F32 = 1125, // WebAssemblyInstrFormats.td:59 |
| 1141 | I64_TRUNC_S_SAT_F32_S = 1126, // WebAssemblyInstrFormats.td:61 |
| 1142 | I64_TRUNC_S_SAT_F64 = 1127, // WebAssemblyInstrFormats.td:59 |
| 1143 | I64_TRUNC_S_SAT_F64_S = 1128, // WebAssemblyInstrFormats.td:61 |
| 1144 | I64_TRUNC_U_F32 = 1129, // WebAssemblyInstrFormats.td:59 |
| 1145 | I64_TRUNC_U_F32_S = 1130, // WebAssemblyInstrFormats.td:61 |
| 1146 | I64_TRUNC_U_F64 = 1131, // WebAssemblyInstrFormats.td:59 |
| 1147 | I64_TRUNC_U_F64_S = 1132, // WebAssemblyInstrFormats.td:61 |
| 1148 | I64_TRUNC_U_SAT_F32 = 1133, // WebAssemblyInstrFormats.td:59 |
| 1149 | I64_TRUNC_U_SAT_F32_S = 1134, // WebAssemblyInstrFormats.td:61 |
| 1150 | I64_TRUNC_U_SAT_F64 = 1135, // WebAssemblyInstrFormats.td:59 |
| 1151 | I64_TRUNC_U_SAT_F64_S = 1136, // WebAssemblyInstrFormats.td:61 |
| 1152 | IF = 1137, // WebAssemblyInstrFormats.td:59 |
| 1153 | IF_S = 1138, // WebAssemblyInstrFormats.td:61 |
| 1154 | LANESELECT_I16x8 = 1139, // WebAssemblyInstrFormats.td:59 |
| 1155 | LANESELECT_I16x8_S = 1140, // WebAssemblyInstrFormats.td:61 |
| 1156 | LANESELECT_I32x4 = 1141, // WebAssemblyInstrFormats.td:59 |
| 1157 | LANESELECT_I32x4_S = 1142, // WebAssemblyInstrFormats.td:61 |
| 1158 | LANESELECT_I64x2 = 1143, // WebAssemblyInstrFormats.td:59 |
| 1159 | LANESELECT_I64x2_S = 1144, // WebAssemblyInstrFormats.td:61 |
| 1160 | LANESELECT_I8x16 = 1145, // WebAssemblyInstrFormats.td:59 |
| 1161 | LANESELECT_I8x16_S = 1146, // WebAssemblyInstrFormats.td:61 |
| 1162 | LE_F16x8 = 1147, // WebAssemblyInstrFormats.td:59 |
| 1163 | LE_F16x8_S = 1148, // WebAssemblyInstrFormats.td:61 |
| 1164 | LE_F32 = 1149, // WebAssemblyInstrFormats.td:59 |
| 1165 | LE_F32_S = 1150, // WebAssemblyInstrFormats.td:61 |
| 1166 | LE_F32x4 = 1151, // WebAssemblyInstrFormats.td:59 |
| 1167 | LE_F32x4_S = 1152, // WebAssemblyInstrFormats.td:61 |
| 1168 | LE_F64 = 1153, // WebAssemblyInstrFormats.td:59 |
| 1169 | LE_F64_S = 1154, // WebAssemblyInstrFormats.td:61 |
| 1170 | LE_F64x2 = 1155, // WebAssemblyInstrFormats.td:59 |
| 1171 | LE_F64x2_S = 1156, // WebAssemblyInstrFormats.td:61 |
| 1172 | LE_S_I16x8 = 1157, // WebAssemblyInstrFormats.td:59 |
| 1173 | LE_S_I16x8_S = 1158, // WebAssemblyInstrFormats.td:61 |
| 1174 | LE_S_I32 = 1159, // WebAssemblyInstrFormats.td:59 |
| 1175 | LE_S_I32_S = 1160, // WebAssemblyInstrFormats.td:61 |
| 1176 | LE_S_I32x4 = 1161, // WebAssemblyInstrFormats.td:59 |
| 1177 | LE_S_I32x4_S = 1162, // WebAssemblyInstrFormats.td:61 |
| 1178 | LE_S_I64 = 1163, // WebAssemblyInstrFormats.td:59 |
| 1179 | LE_S_I64_S = 1164, // WebAssemblyInstrFormats.td:61 |
| 1180 | LE_S_I64x2 = 1165, // WebAssemblyInstrFormats.td:59 |
| 1181 | LE_S_I64x2_S = 1166, // WebAssemblyInstrFormats.td:61 |
| 1182 | LE_S_I8x16 = 1167, // WebAssemblyInstrFormats.td:59 |
| 1183 | LE_S_I8x16_S = 1168, // WebAssemblyInstrFormats.td:61 |
| 1184 | LE_U_I16x8 = 1169, // WebAssemblyInstrFormats.td:59 |
| 1185 | LE_U_I16x8_S = 1170, // WebAssemblyInstrFormats.td:61 |
| 1186 | LE_U_I32 = 1171, // WebAssemblyInstrFormats.td:59 |
| 1187 | LE_U_I32_S = 1172, // WebAssemblyInstrFormats.td:61 |
| 1188 | LE_U_I32x4 = 1173, // WebAssemblyInstrFormats.td:59 |
| 1189 | LE_U_I32x4_S = 1174, // WebAssemblyInstrFormats.td:61 |
| 1190 | LE_U_I64 = 1175, // WebAssemblyInstrFormats.td:59 |
| 1191 | LE_U_I64_S = 1176, // WebAssemblyInstrFormats.td:61 |
| 1192 | LE_U_I8x16 = 1177, // WebAssemblyInstrFormats.td:59 |
| 1193 | LE_U_I8x16_S = 1178, // WebAssemblyInstrFormats.td:61 |
| 1194 | LOAD16_SPLAT_A32 = 1179, // WebAssemblyInstrFormats.td:59 |
| 1195 | LOAD16_SPLAT_A32_S = 1180, // WebAssemblyInstrFormats.td:61 |
| 1196 | LOAD16_SPLAT_A64 = 1181, // WebAssemblyInstrFormats.td:59 |
| 1197 | LOAD16_SPLAT_A64_S = 1182, // WebAssemblyInstrFormats.td:61 |
| 1198 | LOAD16_S_I32_A32 = 1183, // WebAssemblyInstrFormats.td:59 |
| 1199 | LOAD16_S_I32_A32_S = 1184, // WebAssemblyInstrFormats.td:61 |
| 1200 | LOAD16_S_I32_A64 = 1185, // WebAssemblyInstrFormats.td:59 |
| 1201 | LOAD16_S_I32_A64_S = 1186, // WebAssemblyInstrFormats.td:61 |
| 1202 | LOAD16_S_I64_A32 = 1187, // WebAssemblyInstrFormats.td:59 |
| 1203 | LOAD16_S_I64_A32_S = 1188, // WebAssemblyInstrFormats.td:61 |
| 1204 | LOAD16_S_I64_A64 = 1189, // WebAssemblyInstrFormats.td:59 |
| 1205 | LOAD16_S_I64_A64_S = 1190, // WebAssemblyInstrFormats.td:61 |
| 1206 | LOAD16_U_I32_A32 = 1191, // WebAssemblyInstrFormats.td:59 |
| 1207 | LOAD16_U_I32_A32_S = 1192, // WebAssemblyInstrFormats.td:61 |
| 1208 | LOAD16_U_I32_A64 = 1193, // WebAssemblyInstrFormats.td:59 |
| 1209 | LOAD16_U_I32_A64_S = 1194, // WebAssemblyInstrFormats.td:61 |
| 1210 | LOAD16_U_I64_A32 = 1195, // WebAssemblyInstrFormats.td:59 |
| 1211 | LOAD16_U_I64_A32_S = 1196, // WebAssemblyInstrFormats.td:61 |
| 1212 | LOAD16_U_I64_A64 = 1197, // WebAssemblyInstrFormats.td:59 |
| 1213 | LOAD16_U_I64_A64_S = 1198, // WebAssemblyInstrFormats.td:61 |
| 1214 | LOAD32_SPLAT_A32 = 1199, // WebAssemblyInstrFormats.td:59 |
| 1215 | LOAD32_SPLAT_A32_S = 1200, // WebAssemblyInstrFormats.td:61 |
| 1216 | LOAD32_SPLAT_A64 = 1201, // WebAssemblyInstrFormats.td:59 |
| 1217 | LOAD32_SPLAT_A64_S = 1202, // WebAssemblyInstrFormats.td:61 |
| 1218 | LOAD32_S_I64_A32 = 1203, // WebAssemblyInstrFormats.td:59 |
| 1219 | LOAD32_S_I64_A32_S = 1204, // WebAssemblyInstrFormats.td:61 |
| 1220 | LOAD32_S_I64_A64 = 1205, // WebAssemblyInstrFormats.td:59 |
| 1221 | LOAD32_S_I64_A64_S = 1206, // WebAssemblyInstrFormats.td:61 |
| 1222 | LOAD32_U_I64_A32 = 1207, // WebAssemblyInstrFormats.td:59 |
| 1223 | LOAD32_U_I64_A32_S = 1208, // WebAssemblyInstrFormats.td:61 |
| 1224 | LOAD32_U_I64_A64 = 1209, // WebAssemblyInstrFormats.td:59 |
| 1225 | LOAD32_U_I64_A64_S = 1210, // WebAssemblyInstrFormats.td:61 |
| 1226 | LOAD64_SPLAT_A32 = 1211, // WebAssemblyInstrFormats.td:59 |
| 1227 | LOAD64_SPLAT_A32_S = 1212, // WebAssemblyInstrFormats.td:61 |
| 1228 | LOAD64_SPLAT_A64 = 1213, // WebAssemblyInstrFormats.td:59 |
| 1229 | LOAD64_SPLAT_A64_S = 1214, // WebAssemblyInstrFormats.td:61 |
| 1230 | LOAD8_SPLAT_A32 = 1215, // WebAssemblyInstrFormats.td:59 |
| 1231 | LOAD8_SPLAT_A32_S = 1216, // WebAssemblyInstrFormats.td:61 |
| 1232 | LOAD8_SPLAT_A64 = 1217, // WebAssemblyInstrFormats.td:59 |
| 1233 | LOAD8_SPLAT_A64_S = 1218, // WebAssemblyInstrFormats.td:61 |
| 1234 | LOAD8_S_I32_A32 = 1219, // WebAssemblyInstrFormats.td:59 |
| 1235 | LOAD8_S_I32_A32_S = 1220, // WebAssemblyInstrFormats.td:61 |
| 1236 | LOAD8_S_I32_A64 = 1221, // WebAssemblyInstrFormats.td:59 |
| 1237 | LOAD8_S_I32_A64_S = 1222, // WebAssemblyInstrFormats.td:61 |
| 1238 | LOAD8_S_I64_A32 = 1223, // WebAssemblyInstrFormats.td:59 |
| 1239 | LOAD8_S_I64_A32_S = 1224, // WebAssemblyInstrFormats.td:61 |
| 1240 | LOAD8_S_I64_A64 = 1225, // WebAssemblyInstrFormats.td:59 |
| 1241 | LOAD8_S_I64_A64_S = 1226, // WebAssemblyInstrFormats.td:61 |
| 1242 | LOAD8_U_I32_A32 = 1227, // WebAssemblyInstrFormats.td:59 |
| 1243 | LOAD8_U_I32_A32_S = 1228, // WebAssemblyInstrFormats.td:61 |
| 1244 | LOAD8_U_I32_A64 = 1229, // WebAssemblyInstrFormats.td:59 |
| 1245 | LOAD8_U_I32_A64_S = 1230, // WebAssemblyInstrFormats.td:61 |
| 1246 | LOAD8_U_I64_A32 = 1231, // WebAssemblyInstrFormats.td:59 |
| 1247 | LOAD8_U_I64_A32_S = 1232, // WebAssemblyInstrFormats.td:61 |
| 1248 | LOAD8_U_I64_A64 = 1233, // WebAssemblyInstrFormats.td:59 |
| 1249 | LOAD8_U_I64_A64_S = 1234, // WebAssemblyInstrFormats.td:61 |
| 1250 | LOAD_EXTEND_S_I16x8_A32 = 1235, // WebAssemblyInstrFormats.td:59 |
| 1251 | LOAD_EXTEND_S_I16x8_A32_S = 1236, // WebAssemblyInstrFormats.td:61 |
| 1252 | LOAD_EXTEND_S_I16x8_A64 = 1237, // WebAssemblyInstrFormats.td:59 |
| 1253 | LOAD_EXTEND_S_I16x8_A64_S = 1238, // WebAssemblyInstrFormats.td:61 |
| 1254 | LOAD_EXTEND_S_I32x4_A32 = 1239, // WebAssemblyInstrFormats.td:59 |
| 1255 | LOAD_EXTEND_S_I32x4_A32_S = 1240, // WebAssemblyInstrFormats.td:61 |
| 1256 | LOAD_EXTEND_S_I32x4_A64 = 1241, // WebAssemblyInstrFormats.td:59 |
| 1257 | LOAD_EXTEND_S_I32x4_A64_S = 1242, // WebAssemblyInstrFormats.td:61 |
| 1258 | LOAD_EXTEND_S_I64x2_A32 = 1243, // WebAssemblyInstrFormats.td:59 |
| 1259 | LOAD_EXTEND_S_I64x2_A32_S = 1244, // WebAssemblyInstrFormats.td:61 |
| 1260 | LOAD_EXTEND_S_I64x2_A64 = 1245, // WebAssemblyInstrFormats.td:59 |
| 1261 | LOAD_EXTEND_S_I64x2_A64_S = 1246, // WebAssemblyInstrFormats.td:61 |
| 1262 | LOAD_EXTEND_U_I16x8_A32 = 1247, // WebAssemblyInstrFormats.td:59 |
| 1263 | LOAD_EXTEND_U_I16x8_A32_S = 1248, // WebAssemblyInstrFormats.td:61 |
| 1264 | LOAD_EXTEND_U_I16x8_A64 = 1249, // WebAssemblyInstrFormats.td:59 |
| 1265 | LOAD_EXTEND_U_I16x8_A64_S = 1250, // WebAssemblyInstrFormats.td:61 |
| 1266 | LOAD_EXTEND_U_I32x4_A32 = 1251, // WebAssemblyInstrFormats.td:59 |
| 1267 | LOAD_EXTEND_U_I32x4_A32_S = 1252, // WebAssemblyInstrFormats.td:61 |
| 1268 | LOAD_EXTEND_U_I32x4_A64 = 1253, // WebAssemblyInstrFormats.td:59 |
| 1269 | LOAD_EXTEND_U_I32x4_A64_S = 1254, // WebAssemblyInstrFormats.td:61 |
| 1270 | LOAD_EXTEND_U_I64x2_A32 = 1255, // WebAssemblyInstrFormats.td:59 |
| 1271 | LOAD_EXTEND_U_I64x2_A32_S = 1256, // WebAssemblyInstrFormats.td:61 |
| 1272 | LOAD_EXTEND_U_I64x2_A64 = 1257, // WebAssemblyInstrFormats.td:59 |
| 1273 | LOAD_EXTEND_U_I64x2_A64_S = 1258, // WebAssemblyInstrFormats.td:61 |
| 1274 | LOAD_F16_F32_A32 = 1259, // WebAssemblyInstrFormats.td:59 |
| 1275 | LOAD_F16_F32_A32_S = 1260, // WebAssemblyInstrFormats.td:61 |
| 1276 | LOAD_F16_F32_A64 = 1261, // WebAssemblyInstrFormats.td:59 |
| 1277 | LOAD_F16_F32_A64_S = 1262, // WebAssemblyInstrFormats.td:61 |
| 1278 | LOAD_F32_A32 = 1263, // WebAssemblyInstrFormats.td:59 |
| 1279 | LOAD_F32_A32_S = 1264, // WebAssemblyInstrFormats.td:61 |
| 1280 | LOAD_F32_A64 = 1265, // WebAssemblyInstrFormats.td:59 |
| 1281 | LOAD_F32_A64_S = 1266, // WebAssemblyInstrFormats.td:61 |
| 1282 | LOAD_F64_A32 = 1267, // WebAssemblyInstrFormats.td:59 |
| 1283 | LOAD_F64_A32_S = 1268, // WebAssemblyInstrFormats.td:61 |
| 1284 | LOAD_F64_A64 = 1269, // WebAssemblyInstrFormats.td:59 |
| 1285 | LOAD_F64_A64_S = 1270, // WebAssemblyInstrFormats.td:61 |
| 1286 | LOAD_I32_A32 = 1271, // WebAssemblyInstrFormats.td:59 |
| 1287 | LOAD_I32_A32_S = 1272, // WebAssemblyInstrFormats.td:61 |
| 1288 | LOAD_I32_A64 = 1273, // WebAssemblyInstrFormats.td:59 |
| 1289 | LOAD_I32_A64_S = 1274, // WebAssemblyInstrFormats.td:61 |
| 1290 | LOAD_I64_A32 = 1275, // WebAssemblyInstrFormats.td:59 |
| 1291 | LOAD_I64_A32_S = 1276, // WebAssemblyInstrFormats.td:61 |
| 1292 | LOAD_I64_A64 = 1277, // WebAssemblyInstrFormats.td:59 |
| 1293 | LOAD_I64_A64_S = 1278, // WebAssemblyInstrFormats.td:61 |
| 1294 | LOAD_LANE_16_A32 = 1279, // WebAssemblyInstrFormats.td:59 |
| 1295 | LOAD_LANE_16_A32_S = 1280, // WebAssemblyInstrFormats.td:61 |
| 1296 | LOAD_LANE_16_A64 = 1281, // WebAssemblyInstrFormats.td:59 |
| 1297 | LOAD_LANE_16_A64_S = 1282, // WebAssemblyInstrFormats.td:61 |
| 1298 | LOAD_LANE_32_A32 = 1283, // WebAssemblyInstrFormats.td:59 |
| 1299 | LOAD_LANE_32_A32_S = 1284, // WebAssemblyInstrFormats.td:61 |
| 1300 | LOAD_LANE_32_A64 = 1285, // WebAssemblyInstrFormats.td:59 |
| 1301 | LOAD_LANE_32_A64_S = 1286, // WebAssemblyInstrFormats.td:61 |
| 1302 | LOAD_LANE_64_A32 = 1287, // WebAssemblyInstrFormats.td:59 |
| 1303 | LOAD_LANE_64_A32_S = 1288, // WebAssemblyInstrFormats.td:61 |
| 1304 | LOAD_LANE_64_A64 = 1289, // WebAssemblyInstrFormats.td:59 |
| 1305 | LOAD_LANE_64_A64_S = 1290, // WebAssemblyInstrFormats.td:61 |
| 1306 | LOAD_LANE_8_A32 = 1291, // WebAssemblyInstrFormats.td:59 |
| 1307 | LOAD_LANE_8_A32_S = 1292, // WebAssemblyInstrFormats.td:61 |
| 1308 | LOAD_LANE_8_A64 = 1293, // WebAssemblyInstrFormats.td:59 |
| 1309 | LOAD_LANE_8_A64_S = 1294, // WebAssemblyInstrFormats.td:61 |
| 1310 | LOAD_V128_A32 = 1295, // WebAssemblyInstrFormats.td:59 |
| 1311 | LOAD_V128_A32_S = 1296, // WebAssemblyInstrFormats.td:61 |
| 1312 | LOAD_V128_A64 = 1297, // WebAssemblyInstrFormats.td:59 |
| 1313 | LOAD_V128_A64_S = 1298, // WebAssemblyInstrFormats.td:61 |
| 1314 | LOAD_ZERO_32_A32 = 1299, // WebAssemblyInstrFormats.td:59 |
| 1315 | LOAD_ZERO_32_A32_S = 1300, // WebAssemblyInstrFormats.td:61 |
| 1316 | LOAD_ZERO_32_A64 = 1301, // WebAssemblyInstrFormats.td:59 |
| 1317 | LOAD_ZERO_32_A64_S = 1302, // WebAssemblyInstrFormats.td:61 |
| 1318 | LOAD_ZERO_64_A32 = 1303, // WebAssemblyInstrFormats.td:59 |
| 1319 | LOAD_ZERO_64_A32_S = 1304, // WebAssemblyInstrFormats.td:61 |
| 1320 | LOAD_ZERO_64_A64 = 1305, // WebAssemblyInstrFormats.td:59 |
| 1321 | LOAD_ZERO_64_A64_S = 1306, // WebAssemblyInstrFormats.td:61 |
| 1322 | LOCAL_GET_EXNREF = 1307, // WebAssemblyInstrFormats.td:59 |
| 1323 | LOCAL_GET_EXNREF_S = 1308, // WebAssemblyInstrFormats.td:61 |
| 1324 | LOCAL_GET_EXTERNREF = 1309, // WebAssemblyInstrFormats.td:59 |
| 1325 | LOCAL_GET_EXTERNREF_S = 1310, // WebAssemblyInstrFormats.td:61 |
| 1326 | LOCAL_GET_F32 = 1311, // WebAssemblyInstrFormats.td:59 |
| 1327 | LOCAL_GET_F32_S = 1312, // WebAssemblyInstrFormats.td:61 |
| 1328 | LOCAL_GET_F64 = 1313, // WebAssemblyInstrFormats.td:59 |
| 1329 | LOCAL_GET_F64_S = 1314, // WebAssemblyInstrFormats.td:61 |
| 1330 | LOCAL_GET_FUNCREF = 1315, // WebAssemblyInstrFormats.td:59 |
| 1331 | LOCAL_GET_FUNCREF_S = 1316, // WebAssemblyInstrFormats.td:61 |
| 1332 | LOCAL_GET_I32 = 1317, // WebAssemblyInstrFormats.td:59 |
| 1333 | LOCAL_GET_I32_S = 1318, // WebAssemblyInstrFormats.td:61 |
| 1334 | LOCAL_GET_I64 = 1319, // WebAssemblyInstrFormats.td:59 |
| 1335 | LOCAL_GET_I64_S = 1320, // WebAssemblyInstrFormats.td:61 |
| 1336 | LOCAL_GET_V128 = 1321, // WebAssemblyInstrFormats.td:59 |
| 1337 | LOCAL_GET_V128_S = 1322, // WebAssemblyInstrFormats.td:61 |
| 1338 | LOCAL_SET_EXNREF = 1323, // WebAssemblyInstrFormats.td:59 |
| 1339 | LOCAL_SET_EXNREF_S = 1324, // WebAssemblyInstrFormats.td:61 |
| 1340 | LOCAL_SET_EXTERNREF = 1325, // WebAssemblyInstrFormats.td:59 |
| 1341 | LOCAL_SET_EXTERNREF_S = 1326, // WebAssemblyInstrFormats.td:61 |
| 1342 | LOCAL_SET_F32 = 1327, // WebAssemblyInstrFormats.td:59 |
| 1343 | LOCAL_SET_F32_S = 1328, // WebAssemblyInstrFormats.td:61 |
| 1344 | LOCAL_SET_F64 = 1329, // WebAssemblyInstrFormats.td:59 |
| 1345 | LOCAL_SET_F64_S = 1330, // WebAssemblyInstrFormats.td:61 |
| 1346 | LOCAL_SET_FUNCREF = 1331, // WebAssemblyInstrFormats.td:59 |
| 1347 | LOCAL_SET_FUNCREF_S = 1332, // WebAssemblyInstrFormats.td:61 |
| 1348 | LOCAL_SET_I32 = 1333, // WebAssemblyInstrFormats.td:59 |
| 1349 | LOCAL_SET_I32_S = 1334, // WebAssemblyInstrFormats.td:61 |
| 1350 | LOCAL_SET_I64 = 1335, // WebAssemblyInstrFormats.td:59 |
| 1351 | LOCAL_SET_I64_S = 1336, // WebAssemblyInstrFormats.td:61 |
| 1352 | LOCAL_SET_V128 = 1337, // WebAssemblyInstrFormats.td:59 |
| 1353 | LOCAL_SET_V128_S = 1338, // WebAssemblyInstrFormats.td:61 |
| 1354 | LOCAL_TEE_EXNREF = 1339, // WebAssemblyInstrFormats.td:59 |
| 1355 | LOCAL_TEE_EXNREF_S = 1340, // WebAssemblyInstrFormats.td:61 |
| 1356 | LOCAL_TEE_EXTERNREF = 1341, // WebAssemblyInstrFormats.td:59 |
| 1357 | LOCAL_TEE_EXTERNREF_S = 1342, // WebAssemblyInstrFormats.td:61 |
| 1358 | LOCAL_TEE_F32 = 1343, // WebAssemblyInstrFormats.td:59 |
| 1359 | LOCAL_TEE_F32_S = 1344, // WebAssemblyInstrFormats.td:61 |
| 1360 | LOCAL_TEE_F64 = 1345, // WebAssemblyInstrFormats.td:59 |
| 1361 | LOCAL_TEE_F64_S = 1346, // WebAssemblyInstrFormats.td:61 |
| 1362 | LOCAL_TEE_FUNCREF = 1347, // WebAssemblyInstrFormats.td:59 |
| 1363 | LOCAL_TEE_FUNCREF_S = 1348, // WebAssemblyInstrFormats.td:61 |
| 1364 | LOCAL_TEE_I32 = 1349, // WebAssemblyInstrFormats.td:59 |
| 1365 | LOCAL_TEE_I32_S = 1350, // WebAssemblyInstrFormats.td:61 |
| 1366 | LOCAL_TEE_I64 = 1351, // WebAssemblyInstrFormats.td:59 |
| 1367 | LOCAL_TEE_I64_S = 1352, // WebAssemblyInstrFormats.td:61 |
| 1368 | LOCAL_TEE_V128 = 1353, // WebAssemblyInstrFormats.td:59 |
| 1369 | LOCAL_TEE_V128_S = 1354, // WebAssemblyInstrFormats.td:61 |
| 1370 | LOOP = 1355, // WebAssemblyInstrFormats.td:59 |
| 1371 | LOOP_S = 1356, // WebAssemblyInstrFormats.td:61 |
| 1372 | LT_F16x8 = 1357, // WebAssemblyInstrFormats.td:59 |
| 1373 | LT_F16x8_S = 1358, // WebAssemblyInstrFormats.td:61 |
| 1374 | LT_F32 = 1359, // WebAssemblyInstrFormats.td:59 |
| 1375 | LT_F32_S = 1360, // WebAssemblyInstrFormats.td:61 |
| 1376 | LT_F32x4 = 1361, // WebAssemblyInstrFormats.td:59 |
| 1377 | LT_F32x4_S = 1362, // WebAssemblyInstrFormats.td:61 |
| 1378 | LT_F64 = 1363, // WebAssemblyInstrFormats.td:59 |
| 1379 | LT_F64_S = 1364, // WebAssemblyInstrFormats.td:61 |
| 1380 | LT_F64x2 = 1365, // WebAssemblyInstrFormats.td:59 |
| 1381 | LT_F64x2_S = 1366, // WebAssemblyInstrFormats.td:61 |
| 1382 | LT_S_I16x8 = 1367, // WebAssemblyInstrFormats.td:59 |
| 1383 | LT_S_I16x8_S = 1368, // WebAssemblyInstrFormats.td:61 |
| 1384 | LT_S_I32 = 1369, // WebAssemblyInstrFormats.td:59 |
| 1385 | LT_S_I32_S = 1370, // WebAssemblyInstrFormats.td:61 |
| 1386 | LT_S_I32x4 = 1371, // WebAssemblyInstrFormats.td:59 |
| 1387 | LT_S_I32x4_S = 1372, // WebAssemblyInstrFormats.td:61 |
| 1388 | LT_S_I64 = 1373, // WebAssemblyInstrFormats.td:59 |
| 1389 | LT_S_I64_S = 1374, // WebAssemblyInstrFormats.td:61 |
| 1390 | LT_S_I64x2 = 1375, // WebAssemblyInstrFormats.td:59 |
| 1391 | LT_S_I64x2_S = 1376, // WebAssemblyInstrFormats.td:61 |
| 1392 | LT_S_I8x16 = 1377, // WebAssemblyInstrFormats.td:59 |
| 1393 | LT_S_I8x16_S = 1378, // WebAssemblyInstrFormats.td:61 |
| 1394 | LT_U_I16x8 = 1379, // WebAssemblyInstrFormats.td:59 |
| 1395 | LT_U_I16x8_S = 1380, // WebAssemblyInstrFormats.td:61 |
| 1396 | LT_U_I32 = 1381, // WebAssemblyInstrFormats.td:59 |
| 1397 | LT_U_I32_S = 1382, // WebAssemblyInstrFormats.td:61 |
| 1398 | LT_U_I32x4 = 1383, // WebAssemblyInstrFormats.td:59 |
| 1399 | LT_U_I32x4_S = 1384, // WebAssemblyInstrFormats.td:61 |
| 1400 | LT_U_I64 = 1385, // WebAssemblyInstrFormats.td:59 |
| 1401 | LT_U_I64_S = 1386, // WebAssemblyInstrFormats.td:61 |
| 1402 | LT_U_I8x16 = 1387, // WebAssemblyInstrFormats.td:59 |
| 1403 | LT_U_I8x16_S = 1388, // WebAssemblyInstrFormats.td:61 |
| 1404 | MADD_F16x8 = 1389, // WebAssemblyInstrFormats.td:59 |
| 1405 | MADD_F16x8_S = 1390, // WebAssemblyInstrFormats.td:61 |
| 1406 | MADD_F32x4 = 1391, // WebAssemblyInstrFormats.td:59 |
| 1407 | MADD_F32x4_S = 1392, // WebAssemblyInstrFormats.td:61 |
| 1408 | MADD_F64x2 = 1393, // WebAssemblyInstrFormats.td:59 |
| 1409 | MADD_F64x2_S = 1394, // WebAssemblyInstrFormats.td:61 |
| 1410 | MAX_F16x8 = 1395, // WebAssemblyInstrFormats.td:59 |
| 1411 | MAX_F16x8_S = 1396, // WebAssemblyInstrFormats.td:61 |
| 1412 | MAX_F32 = 1397, // WebAssemblyInstrFormats.td:59 |
| 1413 | MAX_F32_S = 1398, // WebAssemblyInstrFormats.td:61 |
| 1414 | MAX_F32x4 = 1399, // WebAssemblyInstrFormats.td:59 |
| 1415 | MAX_F32x4_S = 1400, // WebAssemblyInstrFormats.td:61 |
| 1416 | MAX_F64 = 1401, // WebAssemblyInstrFormats.td:59 |
| 1417 | MAX_F64_S = 1402, // WebAssemblyInstrFormats.td:61 |
| 1418 | MAX_F64x2 = 1403, // WebAssemblyInstrFormats.td:59 |
| 1419 | MAX_F64x2_S = 1404, // WebAssemblyInstrFormats.td:61 |
| 1420 | MAX_S_I16x8 = 1405, // WebAssemblyInstrFormats.td:59 |
| 1421 | MAX_S_I16x8_S = 1406, // WebAssemblyInstrFormats.td:61 |
| 1422 | MAX_S_I32x4 = 1407, // WebAssemblyInstrFormats.td:59 |
| 1423 | MAX_S_I32x4_S = 1408, // WebAssemblyInstrFormats.td:61 |
| 1424 | MAX_S_I8x16 = 1409, // WebAssemblyInstrFormats.td:59 |
| 1425 | MAX_S_I8x16_S = 1410, // WebAssemblyInstrFormats.td:61 |
| 1426 | MAX_U_I16x8 = 1411, // WebAssemblyInstrFormats.td:59 |
| 1427 | MAX_U_I16x8_S = 1412, // WebAssemblyInstrFormats.td:61 |
| 1428 | MAX_U_I32x4 = 1413, // WebAssemblyInstrFormats.td:59 |
| 1429 | MAX_U_I32x4_S = 1414, // WebAssemblyInstrFormats.td:61 |
| 1430 | MAX_U_I8x16 = 1415, // WebAssemblyInstrFormats.td:59 |
| 1431 | MAX_U_I8x16_S = 1416, // WebAssemblyInstrFormats.td:61 |
| 1432 | MEMCPY_A32 = 1417, // WebAssemblyInstrFormats.td:59 |
| 1433 | MEMCPY_A32_S = 1418, // WebAssemblyInstrFormats.td:61 |
| 1434 | MEMCPY_A64 = 1419, // WebAssemblyInstrFormats.td:59 |
| 1435 | MEMCPY_A64_S = 1420, // WebAssemblyInstrFormats.td:61 |
| 1436 | MEMORY_ATOMIC_NOTIFY_A32 = 1421, // WebAssemblyInstrFormats.td:59 |
| 1437 | MEMORY_ATOMIC_NOTIFY_A32_S = 1422, // WebAssemblyInstrFormats.td:61 |
| 1438 | MEMORY_ATOMIC_NOTIFY_A64 = 1423, // WebAssemblyInstrFormats.td:59 |
| 1439 | MEMORY_ATOMIC_NOTIFY_A64_S = 1424, // WebAssemblyInstrFormats.td:61 |
| 1440 | MEMORY_ATOMIC_WAIT32_A32 = 1425, // WebAssemblyInstrFormats.td:59 |
| 1441 | MEMORY_ATOMIC_WAIT32_A32_S = 1426, // WebAssemblyInstrFormats.td:61 |
| 1442 | MEMORY_ATOMIC_WAIT32_A64 = 1427, // WebAssemblyInstrFormats.td:59 |
| 1443 | MEMORY_ATOMIC_WAIT32_A64_S = 1428, // WebAssemblyInstrFormats.td:61 |
| 1444 | MEMORY_ATOMIC_WAIT64_A32 = 1429, // WebAssemblyInstrFormats.td:59 |
| 1445 | MEMORY_ATOMIC_WAIT64_A32_S = 1430, // WebAssemblyInstrFormats.td:61 |
| 1446 | MEMORY_ATOMIC_WAIT64_A64 = 1431, // WebAssemblyInstrFormats.td:59 |
| 1447 | MEMORY_ATOMIC_WAIT64_A64_S = 1432, // WebAssemblyInstrFormats.td:61 |
| 1448 | MEMORY_COPY_A32 = 1433, // WebAssemblyInstrFormats.td:59 |
| 1449 | MEMORY_COPY_A32_S = 1434, // WebAssemblyInstrFormats.td:61 |
| 1450 | MEMORY_COPY_A64 = 1435, // WebAssemblyInstrFormats.td:59 |
| 1451 | MEMORY_COPY_A64_S = 1436, // WebAssemblyInstrFormats.td:61 |
| 1452 | MEMORY_FILL_A32 = 1437, // WebAssemblyInstrFormats.td:59 |
| 1453 | MEMORY_FILL_A32_S = 1438, // WebAssemblyInstrFormats.td:61 |
| 1454 | MEMORY_FILL_A64 = 1439, // WebAssemblyInstrFormats.td:59 |
| 1455 | MEMORY_FILL_A64_S = 1440, // WebAssemblyInstrFormats.td:61 |
| 1456 | MEMORY_INIT_A32 = 1441, // WebAssemblyInstrFormats.td:59 |
| 1457 | MEMORY_INIT_A32_S = 1442, // WebAssemblyInstrFormats.td:61 |
| 1458 | MEMORY_INIT_A64 = 1443, // WebAssemblyInstrFormats.td:59 |
| 1459 | MEMORY_INIT_A64_S = 1444, // WebAssemblyInstrFormats.td:61 |
| 1460 | MEMSET_A32 = 1445, // WebAssemblyInstrFormats.td:59 |
| 1461 | MEMSET_A32_S = 1446, // WebAssemblyInstrFormats.td:61 |
| 1462 | MEMSET_A64 = 1447, // WebAssemblyInstrFormats.td:59 |
| 1463 | MEMSET_A64_S = 1448, // WebAssemblyInstrFormats.td:61 |
| 1464 | MIN_F16x8 = 1449, // WebAssemblyInstrFormats.td:59 |
| 1465 | MIN_F16x8_S = 1450, // WebAssemblyInstrFormats.td:61 |
| 1466 | MIN_F32 = 1451, // WebAssemblyInstrFormats.td:59 |
| 1467 | MIN_F32_S = 1452, // WebAssemblyInstrFormats.td:61 |
| 1468 | MIN_F32x4 = 1453, // WebAssemblyInstrFormats.td:59 |
| 1469 | MIN_F32x4_S = 1454, // WebAssemblyInstrFormats.td:61 |
| 1470 | MIN_F64 = 1455, // WebAssemblyInstrFormats.td:59 |
| 1471 | MIN_F64_S = 1456, // WebAssemblyInstrFormats.td:61 |
| 1472 | MIN_F64x2 = 1457, // WebAssemblyInstrFormats.td:59 |
| 1473 | MIN_F64x2_S = 1458, // WebAssemblyInstrFormats.td:61 |
| 1474 | MIN_S_I16x8 = 1459, // WebAssemblyInstrFormats.td:59 |
| 1475 | MIN_S_I16x8_S = 1460, // WebAssemblyInstrFormats.td:61 |
| 1476 | MIN_S_I32x4 = 1461, // WebAssemblyInstrFormats.td:59 |
| 1477 | MIN_S_I32x4_S = 1462, // WebAssemblyInstrFormats.td:61 |
| 1478 | MIN_S_I8x16 = 1463, // WebAssemblyInstrFormats.td:59 |
| 1479 | MIN_S_I8x16_S = 1464, // WebAssemblyInstrFormats.td:61 |
| 1480 | MIN_U_I16x8 = 1465, // WebAssemblyInstrFormats.td:59 |
| 1481 | MIN_U_I16x8_S = 1466, // WebAssemblyInstrFormats.td:61 |
| 1482 | MIN_U_I32x4 = 1467, // WebAssemblyInstrFormats.td:59 |
| 1483 | MIN_U_I32x4_S = 1468, // WebAssemblyInstrFormats.td:61 |
| 1484 | MIN_U_I8x16 = 1469, // WebAssemblyInstrFormats.td:59 |
| 1485 | MIN_U_I8x16_S = 1470, // WebAssemblyInstrFormats.td:61 |
| 1486 | MUL_F16x8 = 1471, // WebAssemblyInstrFormats.td:59 |
| 1487 | MUL_F16x8_S = 1472, // WebAssemblyInstrFormats.td:61 |
| 1488 | MUL_F32 = 1473, // WebAssemblyInstrFormats.td:59 |
| 1489 | MUL_F32_S = 1474, // WebAssemblyInstrFormats.td:61 |
| 1490 | MUL_F32x4 = 1475, // WebAssemblyInstrFormats.td:59 |
| 1491 | MUL_F32x4_S = 1476, // WebAssemblyInstrFormats.td:61 |
| 1492 | MUL_F64 = 1477, // WebAssemblyInstrFormats.td:59 |
| 1493 | MUL_F64_S = 1478, // WebAssemblyInstrFormats.td:61 |
| 1494 | MUL_F64x2 = 1479, // WebAssemblyInstrFormats.td:59 |
| 1495 | MUL_F64x2_S = 1480, // WebAssemblyInstrFormats.td:61 |
| 1496 | MUL_I16x8 = 1481, // WebAssemblyInstrFormats.td:59 |
| 1497 | MUL_I16x8_S = 1482, // WebAssemblyInstrFormats.td:61 |
| 1498 | MUL_I32 = 1483, // WebAssemblyInstrFormats.td:59 |
| 1499 | MUL_I32_S = 1484, // WebAssemblyInstrFormats.td:61 |
| 1500 | MUL_I32x4 = 1485, // WebAssemblyInstrFormats.td:59 |
| 1501 | MUL_I32x4_S = 1486, // WebAssemblyInstrFormats.td:61 |
| 1502 | MUL_I64 = 1487, // WebAssemblyInstrFormats.td:59 |
| 1503 | MUL_I64_S = 1488, // WebAssemblyInstrFormats.td:61 |
| 1504 | MUL_I64x2 = 1489, // WebAssemblyInstrFormats.td:59 |
| 1505 | MUL_I64x2_S = 1490, // WebAssemblyInstrFormats.td:61 |
| 1506 | NARROW_S_I16x8 = 1491, // WebAssemblyInstrFormats.td:59 |
| 1507 | NARROW_S_I16x8_S = 1492, // WebAssemblyInstrFormats.td:61 |
| 1508 | NARROW_S_I8x16 = 1493, // WebAssemblyInstrFormats.td:59 |
| 1509 | NARROW_S_I8x16_S = 1494, // WebAssemblyInstrFormats.td:61 |
| 1510 | NARROW_U_I16x8 = 1495, // WebAssemblyInstrFormats.td:59 |
| 1511 | NARROW_U_I16x8_S = 1496, // WebAssemblyInstrFormats.td:61 |
| 1512 | NARROW_U_I8x16 = 1497, // WebAssemblyInstrFormats.td:59 |
| 1513 | NARROW_U_I8x16_S = 1498, // WebAssemblyInstrFormats.td:61 |
| 1514 | NEAREST_F16x8 = 1499, // WebAssemblyInstrFormats.td:59 |
| 1515 | NEAREST_F16x8_S = 1500, // WebAssemblyInstrFormats.td:61 |
| 1516 | NEAREST_F32 = 1501, // WebAssemblyInstrFormats.td:59 |
| 1517 | NEAREST_F32_S = 1502, // WebAssemblyInstrFormats.td:61 |
| 1518 | NEAREST_F32x4 = 1503, // WebAssemblyInstrFormats.td:59 |
| 1519 | NEAREST_F32x4_S = 1504, // WebAssemblyInstrFormats.td:61 |
| 1520 | NEAREST_F64 = 1505, // WebAssemblyInstrFormats.td:59 |
| 1521 | NEAREST_F64_S = 1506, // WebAssemblyInstrFormats.td:61 |
| 1522 | NEAREST_F64x2 = 1507, // WebAssemblyInstrFormats.td:59 |
| 1523 | NEAREST_F64x2_S = 1508, // WebAssemblyInstrFormats.td:61 |
| 1524 | NEG_F16x8 = 1509, // WebAssemblyInstrFormats.td:59 |
| 1525 | NEG_F16x8_S = 1510, // WebAssemblyInstrFormats.td:61 |
| 1526 | NEG_F32 = 1511, // WebAssemblyInstrFormats.td:59 |
| 1527 | NEG_F32_S = 1512, // WebAssemblyInstrFormats.td:61 |
| 1528 | NEG_F32x4 = 1513, // WebAssemblyInstrFormats.td:59 |
| 1529 | NEG_F32x4_S = 1514, // WebAssemblyInstrFormats.td:61 |
| 1530 | NEG_F64 = 1515, // WebAssemblyInstrFormats.td:59 |
| 1531 | NEG_F64_S = 1516, // WebAssemblyInstrFormats.td:61 |
| 1532 | NEG_F64x2 = 1517, // WebAssemblyInstrFormats.td:59 |
| 1533 | NEG_F64x2_S = 1518, // WebAssemblyInstrFormats.td:61 |
| 1534 | NEG_I16x8 = 1519, // WebAssemblyInstrFormats.td:59 |
| 1535 | NEG_I16x8_S = 1520, // WebAssemblyInstrFormats.td:61 |
| 1536 | NEG_I32x4 = 1521, // WebAssemblyInstrFormats.td:59 |
| 1537 | NEG_I32x4_S = 1522, // WebAssemblyInstrFormats.td:61 |
| 1538 | NEG_I64x2 = 1523, // WebAssemblyInstrFormats.td:59 |
| 1539 | NEG_I64x2_S = 1524, // WebAssemblyInstrFormats.td:61 |
| 1540 | NEG_I8x16 = 1525, // WebAssemblyInstrFormats.td:59 |
| 1541 | NEG_I8x16_S = 1526, // WebAssemblyInstrFormats.td:61 |
| 1542 | NE_F16x8 = 1527, // WebAssemblyInstrFormats.td:59 |
| 1543 | NE_F16x8_S = 1528, // WebAssemblyInstrFormats.td:61 |
| 1544 | NE_F32 = 1529, // WebAssemblyInstrFormats.td:59 |
| 1545 | NE_F32_S = 1530, // WebAssemblyInstrFormats.td:61 |
| 1546 | NE_F32x4 = 1531, // WebAssemblyInstrFormats.td:59 |
| 1547 | NE_F32x4_S = 1532, // WebAssemblyInstrFormats.td:61 |
| 1548 | NE_F64 = 1533, // WebAssemblyInstrFormats.td:59 |
| 1549 | NE_F64_S = 1534, // WebAssemblyInstrFormats.td:61 |
| 1550 | NE_F64x2 = 1535, // WebAssemblyInstrFormats.td:59 |
| 1551 | NE_F64x2_S = 1536, // WebAssemblyInstrFormats.td:61 |
| 1552 | NE_I16x8 = 1537, // WebAssemblyInstrFormats.td:59 |
| 1553 | NE_I16x8_S = 1538, // WebAssemblyInstrFormats.td:61 |
| 1554 | NE_I32 = 1539, // WebAssemblyInstrFormats.td:59 |
| 1555 | NE_I32_S = 1540, // WebAssemblyInstrFormats.td:61 |
| 1556 | NE_I32x4 = 1541, // WebAssemblyInstrFormats.td:59 |
| 1557 | NE_I32x4_S = 1542, // WebAssemblyInstrFormats.td:61 |
| 1558 | NE_I64 = 1543, // WebAssemblyInstrFormats.td:59 |
| 1559 | NE_I64_S = 1544, // WebAssemblyInstrFormats.td:61 |
| 1560 | NE_I64x2 = 1545, // WebAssemblyInstrFormats.td:59 |
| 1561 | NE_I64x2_S = 1546, // WebAssemblyInstrFormats.td:61 |
| 1562 | NE_I8x16 = 1547, // WebAssemblyInstrFormats.td:59 |
| 1563 | NE_I8x16_S = 1548, // WebAssemblyInstrFormats.td:61 |
| 1564 | NMADD_F16x8 = 1549, // WebAssemblyInstrFormats.td:59 |
| 1565 | NMADD_F16x8_S = 1550, // WebAssemblyInstrFormats.td:61 |
| 1566 | NMADD_F32x4 = 1551, // WebAssemblyInstrFormats.td:59 |
| 1567 | NMADD_F32x4_S = 1552, // WebAssemblyInstrFormats.td:61 |
| 1568 | NMADD_F64x2 = 1553, // WebAssemblyInstrFormats.td:59 |
| 1569 | NMADD_F64x2_S = 1554, // WebAssemblyInstrFormats.td:61 |
| 1570 | NOP = 1555, // WebAssemblyInstrFormats.td:59 |
| 1571 | NOP_S = 1556, // WebAssemblyInstrFormats.td:61 |
| 1572 | NOT = 1557, // WebAssemblyInstrFormats.td:59 |
| 1573 | NOT_S = 1558, // WebAssemblyInstrFormats.td:61 |
| 1574 | OR = 1559, // WebAssemblyInstrFormats.td:59 |
| 1575 | OR_I32 = 1560, // WebAssemblyInstrFormats.td:59 |
| 1576 | OR_I32_S = 1561, // WebAssemblyInstrFormats.td:61 |
| 1577 | OR_I64 = 1562, // WebAssemblyInstrFormats.td:59 |
| 1578 | OR_I64_S = 1563, // WebAssemblyInstrFormats.td:61 |
| 1579 | OR_S = 1564, // WebAssemblyInstrFormats.td:61 |
| 1580 | PMAX_F16x8 = 1565, // WebAssemblyInstrFormats.td:59 |
| 1581 | PMAX_F16x8_S = 1566, // WebAssemblyInstrFormats.td:61 |
| 1582 | PMAX_F32x4 = 1567, // WebAssemblyInstrFormats.td:59 |
| 1583 | PMAX_F32x4_S = 1568, // WebAssemblyInstrFormats.td:61 |
| 1584 | PMAX_F64x2 = 1569, // WebAssemblyInstrFormats.td:59 |
| 1585 | PMAX_F64x2_S = 1570, // WebAssemblyInstrFormats.td:61 |
| 1586 | PMIN_F16x8 = 1571, // WebAssemblyInstrFormats.td:59 |
| 1587 | PMIN_F16x8_S = 1572, // WebAssemblyInstrFormats.td:61 |
| 1588 | PMIN_F32x4 = 1573, // WebAssemblyInstrFormats.td:59 |
| 1589 | PMIN_F32x4_S = 1574, // WebAssemblyInstrFormats.td:61 |
| 1590 | PMIN_F64x2 = 1575, // WebAssemblyInstrFormats.td:59 |
| 1591 | PMIN_F64x2_S = 1576, // WebAssemblyInstrFormats.td:61 |
| 1592 | POPCNT_I32 = 1577, // WebAssemblyInstrFormats.td:59 |
| 1593 | POPCNT_I32_S = 1578, // WebAssemblyInstrFormats.td:61 |
| 1594 | POPCNT_I64 = 1579, // WebAssemblyInstrFormats.td:59 |
| 1595 | POPCNT_I64_S = 1580, // WebAssemblyInstrFormats.td:61 |
| 1596 | POPCNT_I8x16 = 1581, // WebAssemblyInstrFormats.td:59 |
| 1597 | POPCNT_I8x16_S = 1582, // WebAssemblyInstrFormats.td:61 |
| 1598 | Q15MULR_SAT_S_I16x8 = 1583, // WebAssemblyInstrFormats.td:59 |
| 1599 | Q15MULR_SAT_S_I16x8_S = 1584, // WebAssemblyInstrFormats.td:61 |
| 1600 | REF_CAST_FUNCREF = 1585, // WebAssemblyInstrFormats.td:59 |
| 1601 | REF_CAST_FUNCREF_S = 1586, // WebAssemblyInstrFormats.td:61 |
| 1602 | REF_FUNC = 1587, // WebAssemblyInstrFormats.td:59 |
| 1603 | REF_FUNC_S = 1588, // WebAssemblyInstrFormats.td:61 |
| 1604 | REF_IS_NULL_EXNREF = 1589, // WebAssemblyInstrFormats.td:59 |
| 1605 | REF_IS_NULL_EXNREF_S = 1590, // WebAssemblyInstrFormats.td:61 |
| 1606 | REF_IS_NULL_EXTERNREF = 1591, // WebAssemblyInstrFormats.td:59 |
| 1607 | REF_IS_NULL_EXTERNREF_S = 1592, // WebAssemblyInstrFormats.td:61 |
| 1608 | REF_IS_NULL_FUNCREF = 1593, // WebAssemblyInstrFormats.td:59 |
| 1609 | REF_IS_NULL_FUNCREF_S = 1594, // WebAssemblyInstrFormats.td:61 |
| 1610 | REF_NULL_EXNREF = 1595, // WebAssemblyInstrFormats.td:59 |
| 1611 | REF_NULL_EXNREF_S = 1596, // WebAssemblyInstrFormats.td:61 |
| 1612 | REF_NULL_EXTERNREF = 1597, // WebAssemblyInstrFormats.td:59 |
| 1613 | REF_NULL_EXTERNREF_S = 1598, // WebAssemblyInstrFormats.td:61 |
| 1614 | REF_NULL_FUNCREF = 1599, // WebAssemblyInstrFormats.td:59 |
| 1615 | REF_NULL_FUNCREF_S = 1600, // WebAssemblyInstrFormats.td:61 |
| 1616 | REF_TEST_FUNCREF = 1601, // WebAssemblyInstrFormats.td:59 |
| 1617 | REF_TEST_FUNCREF_S = 1602, // WebAssemblyInstrFormats.td:61 |
| 1618 | RELAXED_DOT = 1603, // WebAssemblyInstrFormats.td:59 |
| 1619 | RELAXED_DOT_ADD = 1604, // WebAssemblyInstrFormats.td:59 |
| 1620 | RELAXED_DOT_ADD_S = 1605, // WebAssemblyInstrFormats.td:61 |
| 1621 | RELAXED_DOT_BFLOAT = 1606, // WebAssemblyInstrFormats.td:59 |
| 1622 | RELAXED_DOT_BFLOAT_S = 1607, // WebAssemblyInstrFormats.td:61 |
| 1623 | RELAXED_DOT_S = 1608, // WebAssemblyInstrFormats.td:61 |
| 1624 | RELAXED_Q15MULR_S_I16x8 = 1609, // WebAssemblyInstrFormats.td:59 |
| 1625 | RELAXED_Q15MULR_S_I16x8_S = 1610, // WebAssemblyInstrFormats.td:61 |
| 1626 | RELAXED_SWIZZLE = 1611, // WebAssemblyInstrFormats.td:59 |
| 1627 | RELAXED_SWIZZLE_S = 1612, // WebAssemblyInstrFormats.td:61 |
| 1628 | REM_S_I32 = 1613, // WebAssemblyInstrFormats.td:59 |
| 1629 | REM_S_I32_S = 1614, // WebAssemblyInstrFormats.td:61 |
| 1630 | REM_S_I64 = 1615, // WebAssemblyInstrFormats.td:59 |
| 1631 | REM_S_I64_S = 1616, // WebAssemblyInstrFormats.td:61 |
| 1632 | REM_U_I32 = 1617, // WebAssemblyInstrFormats.td:59 |
| 1633 | REM_U_I32_S = 1618, // WebAssemblyInstrFormats.td:61 |
| 1634 | REM_U_I64 = 1619, // WebAssemblyInstrFormats.td:59 |
| 1635 | REM_U_I64_S = 1620, // WebAssemblyInstrFormats.td:61 |
| 1636 | REPLACE_LANE_F16x8 = 1621, // WebAssemblyInstrFormats.td:59 |
| 1637 | REPLACE_LANE_F16x8_S = 1622, // WebAssemblyInstrFormats.td:61 |
| 1638 | REPLACE_LANE_F32x4 = 1623, // WebAssemblyInstrFormats.td:59 |
| 1639 | REPLACE_LANE_F32x4_S = 1624, // WebAssemblyInstrFormats.td:61 |
| 1640 | REPLACE_LANE_F64x2 = 1625, // WebAssemblyInstrFormats.td:59 |
| 1641 | REPLACE_LANE_F64x2_S = 1626, // WebAssemblyInstrFormats.td:61 |
| 1642 | REPLACE_LANE_I16x8 = 1627, // WebAssemblyInstrFormats.td:59 |
| 1643 | REPLACE_LANE_I16x8_S = 1628, // WebAssemblyInstrFormats.td:61 |
| 1644 | REPLACE_LANE_I32x4 = 1629, // WebAssemblyInstrFormats.td:59 |
| 1645 | REPLACE_LANE_I32x4_S = 1630, // WebAssemblyInstrFormats.td:61 |
| 1646 | REPLACE_LANE_I64x2 = 1631, // WebAssemblyInstrFormats.td:59 |
| 1647 | REPLACE_LANE_I64x2_S = 1632, // WebAssemblyInstrFormats.td:61 |
| 1648 | REPLACE_LANE_I8x16 = 1633, // WebAssemblyInstrFormats.td:59 |
| 1649 | REPLACE_LANE_I8x16_S = 1634, // WebAssemblyInstrFormats.td:61 |
| 1650 | RETHROW = 1635, // WebAssemblyInstrFormats.td:59 |
| 1651 | RETHROW_S = 1636, // WebAssemblyInstrFormats.td:61 |
| 1652 | RETURN = 1637, // WebAssemblyInstrFormats.td:59 |
| 1653 | RETURN_S = 1638, // WebAssemblyInstrFormats.td:61 |
| 1654 | RET_CALL = 1639, // WebAssemblyInstrFormats.td:59 |
| 1655 | RET_CALL_INDIRECT = 1640, // WebAssemblyInstrFormats.td:59 |
| 1656 | RET_CALL_INDIRECT_S = 1641, // WebAssemblyInstrFormats.td:61 |
| 1657 | RET_CALL_REF = 1642, // WebAssemblyInstrFormats.td:59 |
| 1658 | RET_CALL_REF_S = 1643, // WebAssemblyInstrFormats.td:61 |
| 1659 | RET_CALL_S = 1644, // WebAssemblyInstrFormats.td:61 |
| 1660 | ROTL_I32 = 1645, // WebAssemblyInstrFormats.td:59 |
| 1661 | ROTL_I32_S = 1646, // WebAssemblyInstrFormats.td:61 |
| 1662 | ROTL_I64 = 1647, // WebAssemblyInstrFormats.td:59 |
| 1663 | ROTL_I64_S = 1648, // WebAssemblyInstrFormats.td:61 |
| 1664 | ROTR_I32 = 1649, // WebAssemblyInstrFormats.td:59 |
| 1665 | ROTR_I32_S = 1650, // WebAssemblyInstrFormats.td:61 |
| 1666 | ROTR_I64 = 1651, // WebAssemblyInstrFormats.td:59 |
| 1667 | ROTR_I64_S = 1652, // WebAssemblyInstrFormats.td:61 |
| 1668 | SELECT_EXNREF = 1653, // WebAssemblyInstrFormats.td:59 |
| 1669 | SELECT_EXNREF_S = 1654, // WebAssemblyInstrFormats.td:61 |
| 1670 | SELECT_EXTERNREF = 1655, // WebAssemblyInstrFormats.td:59 |
| 1671 | SELECT_EXTERNREF_S = 1656, // WebAssemblyInstrFormats.td:61 |
| 1672 | SELECT_F32 = 1657, // WebAssemblyInstrFormats.td:59 |
| 1673 | SELECT_F32_S = 1658, // WebAssemblyInstrFormats.td:61 |
| 1674 | SELECT_F64 = 1659, // WebAssemblyInstrFormats.td:59 |
| 1675 | SELECT_F64_S = 1660, // WebAssemblyInstrFormats.td:61 |
| 1676 | SELECT_FUNCREF = 1661, // WebAssemblyInstrFormats.td:59 |
| 1677 | SELECT_FUNCREF_S = 1662, // WebAssemblyInstrFormats.td:61 |
| 1678 | SELECT_I32 = 1663, // WebAssemblyInstrFormats.td:59 |
| 1679 | SELECT_I32_S = 1664, // WebAssemblyInstrFormats.td:61 |
| 1680 | SELECT_I64 = 1665, // WebAssemblyInstrFormats.td:59 |
| 1681 | SELECT_I64_S = 1666, // WebAssemblyInstrFormats.td:61 |
| 1682 | SELECT_T = 1667, // WebAssemblyInstrFormats.td:59 |
| 1683 | SELECT_T_S = 1668, // WebAssemblyInstrFormats.td:61 |
| 1684 | SELECT_V128 = 1669, // WebAssemblyInstrFormats.td:59 |
| 1685 | SELECT_V128_S = 1670, // WebAssemblyInstrFormats.td:61 |
| 1686 | SHL_I16x8 = 1671, // WebAssemblyInstrFormats.td:59 |
| 1687 | SHL_I16x8_S = 1672, // WebAssemblyInstrFormats.td:61 |
| 1688 | SHL_I32 = 1673, // WebAssemblyInstrFormats.td:59 |
| 1689 | SHL_I32_S = 1674, // WebAssemblyInstrFormats.td:61 |
| 1690 | SHL_I32x4 = 1675, // WebAssemblyInstrFormats.td:59 |
| 1691 | SHL_I32x4_S = 1676, // WebAssemblyInstrFormats.td:61 |
| 1692 | SHL_I64 = 1677, // WebAssemblyInstrFormats.td:59 |
| 1693 | SHL_I64_S = 1678, // WebAssemblyInstrFormats.td:61 |
| 1694 | SHL_I64x2 = 1679, // WebAssemblyInstrFormats.td:59 |
| 1695 | SHL_I64x2_S = 1680, // WebAssemblyInstrFormats.td:61 |
| 1696 | SHL_I8x16 = 1681, // WebAssemblyInstrFormats.td:59 |
| 1697 | SHL_I8x16_S = 1682, // WebAssemblyInstrFormats.td:61 |
| 1698 | SHR_S_I16x8 = 1683, // WebAssemblyInstrFormats.td:59 |
| 1699 | SHR_S_I16x8_S = 1684, // WebAssemblyInstrFormats.td:61 |
| 1700 | SHR_S_I32 = 1685, // WebAssemblyInstrFormats.td:59 |
| 1701 | SHR_S_I32_S = 1686, // WebAssemblyInstrFormats.td:61 |
| 1702 | SHR_S_I32x4 = 1687, // WebAssemblyInstrFormats.td:59 |
| 1703 | SHR_S_I32x4_S = 1688, // WebAssemblyInstrFormats.td:61 |
| 1704 | SHR_S_I64 = 1689, // WebAssemblyInstrFormats.td:59 |
| 1705 | SHR_S_I64_S = 1690, // WebAssemblyInstrFormats.td:61 |
| 1706 | SHR_S_I64x2 = 1691, // WebAssemblyInstrFormats.td:59 |
| 1707 | SHR_S_I64x2_S = 1692, // WebAssemblyInstrFormats.td:61 |
| 1708 | SHR_S_I8x16 = 1693, // WebAssemblyInstrFormats.td:59 |
| 1709 | SHR_S_I8x16_S = 1694, // WebAssemblyInstrFormats.td:61 |
| 1710 | SHR_U_I16x8 = 1695, // WebAssemblyInstrFormats.td:59 |
| 1711 | SHR_U_I16x8_S = 1696, // WebAssemblyInstrFormats.td:61 |
| 1712 | SHR_U_I32 = 1697, // WebAssemblyInstrFormats.td:59 |
| 1713 | SHR_U_I32_S = 1698, // WebAssemblyInstrFormats.td:61 |
| 1714 | SHR_U_I32x4 = 1699, // WebAssemblyInstrFormats.td:59 |
| 1715 | SHR_U_I32x4_S = 1700, // WebAssemblyInstrFormats.td:61 |
| 1716 | SHR_U_I64 = 1701, // WebAssemblyInstrFormats.td:59 |
| 1717 | SHR_U_I64_S = 1702, // WebAssemblyInstrFormats.td:61 |
| 1718 | SHR_U_I64x2 = 1703, // WebAssemblyInstrFormats.td:59 |
| 1719 | SHR_U_I64x2_S = 1704, // WebAssemblyInstrFormats.td:61 |
| 1720 | SHR_U_I8x16 = 1705, // WebAssemblyInstrFormats.td:59 |
| 1721 | SHR_U_I8x16_S = 1706, // WebAssemblyInstrFormats.td:61 |
| 1722 | SHUFFLE = 1707, // WebAssemblyInstrFormats.td:59 |
| 1723 | SHUFFLE_S = 1708, // WebAssemblyInstrFormats.td:61 |
| 1724 | SIMD_RELAXED_FMAX_F32x4 = 1709, // WebAssemblyInstrFormats.td:59 |
| 1725 | SIMD_RELAXED_FMAX_F32x4_S = 1710, // WebAssemblyInstrFormats.td:61 |
| 1726 | SIMD_RELAXED_FMAX_F64x2 = 1711, // WebAssemblyInstrFormats.td:59 |
| 1727 | SIMD_RELAXED_FMAX_F64x2_S = 1712, // WebAssemblyInstrFormats.td:61 |
| 1728 | SIMD_RELAXED_FMIN_F32x4 = 1713, // WebAssemblyInstrFormats.td:59 |
| 1729 | SIMD_RELAXED_FMIN_F32x4_S = 1714, // WebAssemblyInstrFormats.td:61 |
| 1730 | SIMD_RELAXED_FMIN_F64x2 = 1715, // WebAssemblyInstrFormats.td:59 |
| 1731 | SIMD_RELAXED_FMIN_F64x2_S = 1716, // WebAssemblyInstrFormats.td:61 |
| 1732 | SPLAT_F16x8 = 1717, // WebAssemblyInstrFormats.td:59 |
| 1733 | SPLAT_F16x8_S = 1718, // WebAssemblyInstrFormats.td:61 |
| 1734 | SPLAT_F32x4 = 1719, // WebAssemblyInstrFormats.td:59 |
| 1735 | SPLAT_F32x4_S = 1720, // WebAssemblyInstrFormats.td:61 |
| 1736 | SPLAT_F64x2 = 1721, // WebAssemblyInstrFormats.td:59 |
| 1737 | SPLAT_F64x2_S = 1722, // WebAssemblyInstrFormats.td:61 |
| 1738 | SPLAT_I16x8 = 1723, // WebAssemblyInstrFormats.td:59 |
| 1739 | SPLAT_I16x8_S = 1724, // WebAssemblyInstrFormats.td:61 |
| 1740 | SPLAT_I32x4 = 1725, // WebAssemblyInstrFormats.td:59 |
| 1741 | SPLAT_I32x4_S = 1726, // WebAssemblyInstrFormats.td:61 |
| 1742 | SPLAT_I64x2 = 1727, // WebAssemblyInstrFormats.td:59 |
| 1743 | SPLAT_I64x2_S = 1728, // WebAssemblyInstrFormats.td:61 |
| 1744 | SPLAT_I8x16 = 1729, // WebAssemblyInstrFormats.td:59 |
| 1745 | SPLAT_I8x16_S = 1730, // WebAssemblyInstrFormats.td:61 |
| 1746 | SQRT_F16x8 = 1731, // WebAssemblyInstrFormats.td:59 |
| 1747 | SQRT_F16x8_S = 1732, // WebAssemblyInstrFormats.td:61 |
| 1748 | SQRT_F32 = 1733, // WebAssemblyInstrFormats.td:59 |
| 1749 | SQRT_F32_S = 1734, // WebAssemblyInstrFormats.td:61 |
| 1750 | SQRT_F32x4 = 1735, // WebAssemblyInstrFormats.td:59 |
| 1751 | SQRT_F32x4_S = 1736, // WebAssemblyInstrFormats.td:61 |
| 1752 | SQRT_F64 = 1737, // WebAssemblyInstrFormats.td:59 |
| 1753 | SQRT_F64_S = 1738, // WebAssemblyInstrFormats.td:61 |
| 1754 | SQRT_F64x2 = 1739, // WebAssemblyInstrFormats.td:59 |
| 1755 | SQRT_F64x2_S = 1740, // WebAssemblyInstrFormats.td:61 |
| 1756 | STORE16_I32_A32 = 1741, // WebAssemblyInstrFormats.td:59 |
| 1757 | STORE16_I32_A32_S = 1742, // WebAssemblyInstrFormats.td:61 |
| 1758 | STORE16_I32_A64 = 1743, // WebAssemblyInstrFormats.td:59 |
| 1759 | STORE16_I32_A64_S = 1744, // WebAssemblyInstrFormats.td:61 |
| 1760 | STORE16_I64_A32 = 1745, // WebAssemblyInstrFormats.td:59 |
| 1761 | STORE16_I64_A32_S = 1746, // WebAssemblyInstrFormats.td:61 |
| 1762 | STORE16_I64_A64 = 1747, // WebAssemblyInstrFormats.td:59 |
| 1763 | STORE16_I64_A64_S = 1748, // WebAssemblyInstrFormats.td:61 |
| 1764 | STORE32_I64_A32 = 1749, // WebAssemblyInstrFormats.td:59 |
| 1765 | STORE32_I64_A32_S = 1750, // WebAssemblyInstrFormats.td:61 |
| 1766 | STORE32_I64_A64 = 1751, // WebAssemblyInstrFormats.td:59 |
| 1767 | STORE32_I64_A64_S = 1752, // WebAssemblyInstrFormats.td:61 |
| 1768 | STORE8_I32_A32 = 1753, // WebAssemblyInstrFormats.td:59 |
| 1769 | STORE8_I32_A32_S = 1754, // WebAssemblyInstrFormats.td:61 |
| 1770 | STORE8_I32_A64 = 1755, // WebAssemblyInstrFormats.td:59 |
| 1771 | STORE8_I32_A64_S = 1756, // WebAssemblyInstrFormats.td:61 |
| 1772 | STORE8_I64_A32 = 1757, // WebAssemblyInstrFormats.td:59 |
| 1773 | STORE8_I64_A32_S = 1758, // WebAssemblyInstrFormats.td:61 |
| 1774 | STORE8_I64_A64 = 1759, // WebAssemblyInstrFormats.td:59 |
| 1775 | STORE8_I64_A64_S = 1760, // WebAssemblyInstrFormats.td:61 |
| 1776 | STORE_F16_F32_A32 = 1761, // WebAssemblyInstrFormats.td:59 |
| 1777 | STORE_F16_F32_A32_S = 1762, // WebAssemblyInstrFormats.td:61 |
| 1778 | STORE_F16_F32_A64 = 1763, // WebAssemblyInstrFormats.td:59 |
| 1779 | STORE_F16_F32_A64_S = 1764, // WebAssemblyInstrFormats.td:61 |
| 1780 | STORE_F32_A32 = 1765, // WebAssemblyInstrFormats.td:59 |
| 1781 | STORE_F32_A32_S = 1766, // WebAssemblyInstrFormats.td:61 |
| 1782 | STORE_F32_A64 = 1767, // WebAssemblyInstrFormats.td:59 |
| 1783 | STORE_F32_A64_S = 1768, // WebAssemblyInstrFormats.td:61 |
| 1784 | STORE_F64_A32 = 1769, // WebAssemblyInstrFormats.td:59 |
| 1785 | STORE_F64_A32_S = 1770, // WebAssemblyInstrFormats.td:61 |
| 1786 | STORE_F64_A64 = 1771, // WebAssemblyInstrFormats.td:59 |
| 1787 | STORE_F64_A64_S = 1772, // WebAssemblyInstrFormats.td:61 |
| 1788 | STORE_I32_A32 = 1773, // WebAssemblyInstrFormats.td:59 |
| 1789 | STORE_I32_A32_S = 1774, // WebAssemblyInstrFormats.td:61 |
| 1790 | STORE_I32_A64 = 1775, // WebAssemblyInstrFormats.td:59 |
| 1791 | STORE_I32_A64_S = 1776, // WebAssemblyInstrFormats.td:61 |
| 1792 | STORE_I64_A32 = 1777, // WebAssemblyInstrFormats.td:59 |
| 1793 | STORE_I64_A32_S = 1778, // WebAssemblyInstrFormats.td:61 |
| 1794 | STORE_I64_A64 = 1779, // WebAssemblyInstrFormats.td:59 |
| 1795 | STORE_I64_A64_S = 1780, // WebAssemblyInstrFormats.td:61 |
| 1796 | STORE_LANE_I16x8_A32 = 1781, // WebAssemblyInstrFormats.td:59 |
| 1797 | STORE_LANE_I16x8_A32_S = 1782, // WebAssemblyInstrFormats.td:61 |
| 1798 | STORE_LANE_I16x8_A64 = 1783, // WebAssemblyInstrFormats.td:59 |
| 1799 | STORE_LANE_I16x8_A64_S = 1784, // WebAssemblyInstrFormats.td:61 |
| 1800 | STORE_LANE_I32x4_A32 = 1785, // WebAssemblyInstrFormats.td:59 |
| 1801 | STORE_LANE_I32x4_A32_S = 1786, // WebAssemblyInstrFormats.td:61 |
| 1802 | STORE_LANE_I32x4_A64 = 1787, // WebAssemblyInstrFormats.td:59 |
| 1803 | STORE_LANE_I32x4_A64_S = 1788, // WebAssemblyInstrFormats.td:61 |
| 1804 | STORE_LANE_I64x2_A32 = 1789, // WebAssemblyInstrFormats.td:59 |
| 1805 | STORE_LANE_I64x2_A32_S = 1790, // WebAssemblyInstrFormats.td:61 |
| 1806 | STORE_LANE_I64x2_A64 = 1791, // WebAssemblyInstrFormats.td:59 |
| 1807 | STORE_LANE_I64x2_A64_S = 1792, // WebAssemblyInstrFormats.td:61 |
| 1808 | STORE_LANE_I8x16_A32 = 1793, // WebAssemblyInstrFormats.td:59 |
| 1809 | STORE_LANE_I8x16_A32_S = 1794, // WebAssemblyInstrFormats.td:61 |
| 1810 | STORE_LANE_I8x16_A64 = 1795, // WebAssemblyInstrFormats.td:59 |
| 1811 | STORE_LANE_I8x16_A64_S = 1796, // WebAssemblyInstrFormats.td:61 |
| 1812 | STORE_V128_A32 = 1797, // WebAssemblyInstrFormats.td:59 |
| 1813 | STORE_V128_A32_S = 1798, // WebAssemblyInstrFormats.td:61 |
| 1814 | STORE_V128_A64 = 1799, // WebAssemblyInstrFormats.td:59 |
| 1815 | STORE_V128_A64_S = 1800, // WebAssemblyInstrFormats.td:61 |
| 1816 | SUB_F16x8 = 1801, // WebAssemblyInstrFormats.td:59 |
| 1817 | SUB_F16x8_S = 1802, // WebAssemblyInstrFormats.td:61 |
| 1818 | SUB_F32 = 1803, // WebAssemblyInstrFormats.td:59 |
| 1819 | SUB_F32_S = 1804, // WebAssemblyInstrFormats.td:61 |
| 1820 | SUB_F32x4 = 1805, // WebAssemblyInstrFormats.td:59 |
| 1821 | SUB_F32x4_S = 1806, // WebAssemblyInstrFormats.td:61 |
| 1822 | SUB_F64 = 1807, // WebAssemblyInstrFormats.td:59 |
| 1823 | SUB_F64_S = 1808, // WebAssemblyInstrFormats.td:61 |
| 1824 | SUB_F64x2 = 1809, // WebAssemblyInstrFormats.td:59 |
| 1825 | SUB_F64x2_S = 1810, // WebAssemblyInstrFormats.td:61 |
| 1826 | SUB_I16x8 = 1811, // WebAssemblyInstrFormats.td:59 |
| 1827 | SUB_I16x8_S = 1812, // WebAssemblyInstrFormats.td:61 |
| 1828 | SUB_I32 = 1813, // WebAssemblyInstrFormats.td:59 |
| 1829 | SUB_I32_S = 1814, // WebAssemblyInstrFormats.td:61 |
| 1830 | SUB_I32x4 = 1815, // WebAssemblyInstrFormats.td:59 |
| 1831 | SUB_I32x4_S = 1816, // WebAssemblyInstrFormats.td:61 |
| 1832 | SUB_I64 = 1817, // WebAssemblyInstrFormats.td:59 |
| 1833 | SUB_I64_S = 1818, // WebAssemblyInstrFormats.td:61 |
| 1834 | SUB_I64x2 = 1819, // WebAssemblyInstrFormats.td:59 |
| 1835 | SUB_I64x2_S = 1820, // WebAssemblyInstrFormats.td:61 |
| 1836 | SUB_I8x16 = 1821, // WebAssemblyInstrFormats.td:59 |
| 1837 | SUB_I8x16_S = 1822, // WebAssemblyInstrFormats.td:61 |
| 1838 | SUB_SAT_S_I16x8 = 1823, // WebAssemblyInstrFormats.td:59 |
| 1839 | SUB_SAT_S_I16x8_S = 1824, // WebAssemblyInstrFormats.td:61 |
| 1840 | SUB_SAT_S_I8x16 = 1825, // WebAssemblyInstrFormats.td:59 |
| 1841 | SUB_SAT_S_I8x16_S = 1826, // WebAssemblyInstrFormats.td:61 |
| 1842 | SUB_SAT_U_I16x8 = 1827, // WebAssemblyInstrFormats.td:59 |
| 1843 | SUB_SAT_U_I16x8_S = 1828, // WebAssemblyInstrFormats.td:61 |
| 1844 | SUB_SAT_U_I8x16 = 1829, // WebAssemblyInstrFormats.td:59 |
| 1845 | SUB_SAT_U_I8x16_S = 1830, // WebAssemblyInstrFormats.td:61 |
| 1846 | SWIZZLE = 1831, // WebAssemblyInstrFormats.td:59 |
| 1847 | SWIZZLE_S = 1832, // WebAssemblyInstrFormats.td:61 |
| 1848 | TABLE_COPY = 1833, // WebAssemblyInstrFormats.td:59 |
| 1849 | TABLE_COPY_S = 1834, // WebAssemblyInstrFormats.td:61 |
| 1850 | TABLE_FILL_EXNREF = 1835, // WebAssemblyInstrFormats.td:59 |
| 1851 | TABLE_FILL_EXNREF_S = 1836, // WebAssemblyInstrFormats.td:61 |
| 1852 | TABLE_FILL_EXTERNREF = 1837, // WebAssemblyInstrFormats.td:59 |
| 1853 | TABLE_FILL_EXTERNREF_S = 1838, // WebAssemblyInstrFormats.td:61 |
| 1854 | TABLE_FILL_FUNCREF = 1839, // WebAssemblyInstrFormats.td:59 |
| 1855 | TABLE_FILL_FUNCREF_S = 1840, // WebAssemblyInstrFormats.td:61 |
| 1856 | TABLE_GET_EXNREF = 1841, // WebAssemblyInstrFormats.td:59 |
| 1857 | TABLE_GET_EXNREF_S = 1842, // WebAssemblyInstrFormats.td:61 |
| 1858 | TABLE_GET_EXTERNREF = 1843, // WebAssemblyInstrFormats.td:59 |
| 1859 | TABLE_GET_EXTERNREF_S = 1844, // WebAssemblyInstrFormats.td:61 |
| 1860 | TABLE_GET_FUNCREF = 1845, // WebAssemblyInstrFormats.td:59 |
| 1861 | TABLE_GET_FUNCREF_S = 1846, // WebAssemblyInstrFormats.td:61 |
| 1862 | TABLE_GROW_EXNREF = 1847, // WebAssemblyInstrFormats.td:59 |
| 1863 | TABLE_GROW_EXNREF_S = 1848, // WebAssemblyInstrFormats.td:61 |
| 1864 | TABLE_GROW_EXTERNREF = 1849, // WebAssemblyInstrFormats.td:59 |
| 1865 | TABLE_GROW_EXTERNREF_S = 1850, // WebAssemblyInstrFormats.td:61 |
| 1866 | TABLE_GROW_FUNCREF = 1851, // WebAssemblyInstrFormats.td:59 |
| 1867 | TABLE_GROW_FUNCREF_S = 1852, // WebAssemblyInstrFormats.td:61 |
| 1868 | TABLE_SET_EXNREF = 1853, // WebAssemblyInstrFormats.td:59 |
| 1869 | TABLE_SET_EXNREF_S = 1854, // WebAssemblyInstrFormats.td:61 |
| 1870 | TABLE_SET_EXTERNREF = 1855, // WebAssemblyInstrFormats.td:59 |
| 1871 | TABLE_SET_EXTERNREF_S = 1856, // WebAssemblyInstrFormats.td:61 |
| 1872 | TABLE_SET_FUNCREF = 1857, // WebAssemblyInstrFormats.td:59 |
| 1873 | TABLE_SET_FUNCREF_S = 1858, // WebAssemblyInstrFormats.td:61 |
| 1874 | TABLE_SIZE = 1859, // WebAssemblyInstrFormats.td:59 |
| 1875 | TABLE_SIZE_S = 1860, // WebAssemblyInstrFormats.td:61 |
| 1876 | TEE_EXNREF = 1861, // WebAssemblyInstrFormats.td:59 |
| 1877 | TEE_EXNREF_S = 1862, // WebAssemblyInstrFormats.td:61 |
| 1878 | TEE_EXTERNREF = 1863, // WebAssemblyInstrFormats.td:59 |
| 1879 | TEE_EXTERNREF_S = 1864, // WebAssemblyInstrFormats.td:61 |
| 1880 | TEE_F32 = 1865, // WebAssemblyInstrFormats.td:59 |
| 1881 | TEE_F32_S = 1866, // WebAssemblyInstrFormats.td:61 |
| 1882 | TEE_F64 = 1867, // WebAssemblyInstrFormats.td:59 |
| 1883 | TEE_F64_S = 1868, // WebAssemblyInstrFormats.td:61 |
| 1884 | TEE_FUNCREF = 1869, // WebAssemblyInstrFormats.td:59 |
| 1885 | TEE_FUNCREF_S = 1870, // WebAssemblyInstrFormats.td:61 |
| 1886 | TEE_I32 = 1871, // WebAssemblyInstrFormats.td:59 |
| 1887 | TEE_I32_S = 1872, // WebAssemblyInstrFormats.td:61 |
| 1888 | TEE_I64 = 1873, // WebAssemblyInstrFormats.td:59 |
| 1889 | TEE_I64_S = 1874, // WebAssemblyInstrFormats.td:61 |
| 1890 | TEE_V128 = 1875, // WebAssemblyInstrFormats.td:59 |
| 1891 | TEE_V128_S = 1876, // WebAssemblyInstrFormats.td:61 |
| 1892 | THROW = 1877, // WebAssemblyInstrFormats.td:59 |
| 1893 | THROW_REF = 1878, // WebAssemblyInstrFormats.td:59 |
| 1894 | THROW_REF_S = 1879, // WebAssemblyInstrFormats.td:61 |
| 1895 | THROW_S = 1880, // WebAssemblyInstrFormats.td:61 |
| 1896 | TRUNC_F16x8 = 1881, // WebAssemblyInstrFormats.td:59 |
| 1897 | TRUNC_F16x8_S = 1882, // WebAssemblyInstrFormats.td:61 |
| 1898 | TRUNC_F32 = 1883, // WebAssemblyInstrFormats.td:59 |
| 1899 | TRUNC_F32_S = 1884, // WebAssemblyInstrFormats.td:61 |
| 1900 | TRUNC_F32x4 = 1885, // WebAssemblyInstrFormats.td:59 |
| 1901 | TRUNC_F32x4_S = 1886, // WebAssemblyInstrFormats.td:61 |
| 1902 | TRUNC_F64 = 1887, // WebAssemblyInstrFormats.td:59 |
| 1903 | TRUNC_F64_S = 1888, // WebAssemblyInstrFormats.td:61 |
| 1904 | TRUNC_F64x2 = 1889, // WebAssemblyInstrFormats.td:59 |
| 1905 | TRUNC_F64x2_S = 1890, // WebAssemblyInstrFormats.td:61 |
| 1906 | TRY = 1891, // WebAssemblyInstrFormats.td:59 |
| 1907 | TRY_S = 1892, // WebAssemblyInstrFormats.td:61 |
| 1908 | TRY_TABLE = 1893, // WebAssemblyInstrFormats.td:59 |
| 1909 | TRY_TABLE_S = 1894, // WebAssemblyInstrFormats.td:61 |
| 1910 | UNREACHABLE = 1895, // WebAssemblyInstrFormats.td:59 |
| 1911 | UNREACHABLE_S = 1896, // WebAssemblyInstrFormats.td:61 |
| 1912 | XOR = 1897, // WebAssemblyInstrFormats.td:59 |
| 1913 | XOR_I32 = 1898, // WebAssemblyInstrFormats.td:59 |
| 1914 | XOR_I32_S = 1899, // WebAssemblyInstrFormats.td:61 |
| 1915 | XOR_I64 = 1900, // WebAssemblyInstrFormats.td:59 |
| 1916 | XOR_I64_S = 1901, // WebAssemblyInstrFormats.td:61 |
| 1917 | XOR_S = 1902, // WebAssemblyInstrFormats.td:61 |
| 1918 | anonymous_14864MEMORY_GROW_A32 = 1903, // WebAssemblyInstrFormats.td:59 |
| 1919 | anonymous_14864MEMORY_GROW_A32_S = 1904, // WebAssemblyInstrFormats.td:61 |
| 1920 | anonymous_14864MEMORY_SIZE_A32 = 1905, // WebAssemblyInstrFormats.td:59 |
| 1921 | anonymous_14864MEMORY_SIZE_A32_S = 1906, // WebAssemblyInstrFormats.td:61 |
| 1922 | anonymous_14865MEMORY_GROW_A64 = 1907, // WebAssemblyInstrFormats.td:59 |
| 1923 | anonymous_14865MEMORY_GROW_A64_S = 1908, // WebAssemblyInstrFormats.td:61 |
| 1924 | anonymous_14865MEMORY_SIZE_A64 = 1909, // WebAssemblyInstrFormats.td:59 |
| 1925 | anonymous_14865MEMORY_SIZE_A64_S = 1910, // WebAssemblyInstrFormats.td:61 |
| 1926 | convert_low_s_F64x2 = 1911, // WebAssemblyInstrFormats.td:59 |
| 1927 | convert_low_s_F64x2_S = 1912, // WebAssemblyInstrFormats.td:61 |
| 1928 | convert_low_u_F64x2 = 1913, // WebAssemblyInstrFormats.td:59 |
| 1929 | convert_low_u_F64x2_S = 1914, // WebAssemblyInstrFormats.td:61 |
| 1930 | demote_zero_F16x8 = 1915, // WebAssemblyInstrFormats.td:59 |
| 1931 | demote_zero_F16x8_S = 1916, // WebAssemblyInstrFormats.td:61 |
| 1932 | demote_zero_F32x4 = 1917, // WebAssemblyInstrFormats.td:59 |
| 1933 | demote_zero_F32x4_S = 1918, // WebAssemblyInstrFormats.td:61 |
| 1934 | extadd_pairwise_s_I16x8 = 1919, // WebAssemblyInstrFormats.td:59 |
| 1935 | extadd_pairwise_s_I16x8_S = 1920, // WebAssemblyInstrFormats.td:61 |
| 1936 | extadd_pairwise_s_I32x4 = 1921, // WebAssemblyInstrFormats.td:59 |
| 1937 | extadd_pairwise_s_I32x4_S = 1922, // WebAssemblyInstrFormats.td:61 |
| 1938 | extadd_pairwise_u_I16x8 = 1923, // WebAssemblyInstrFormats.td:59 |
| 1939 | extadd_pairwise_u_I16x8_S = 1924, // WebAssemblyInstrFormats.td:61 |
| 1940 | extadd_pairwise_u_I32x4 = 1925, // WebAssemblyInstrFormats.td:59 |
| 1941 | extadd_pairwise_u_I32x4_S = 1926, // WebAssemblyInstrFormats.td:61 |
| 1942 | extend_high_s_I16x8 = 1927, // WebAssemblyInstrFormats.td:59 |
| 1943 | extend_high_s_I16x8_S = 1928, // WebAssemblyInstrFormats.td:61 |
| 1944 | extend_high_s_I32x4 = 1929, // WebAssemblyInstrFormats.td:59 |
| 1945 | extend_high_s_I32x4_S = 1930, // WebAssemblyInstrFormats.td:61 |
| 1946 | extend_high_s_I64x2 = 1931, // WebAssemblyInstrFormats.td:59 |
| 1947 | extend_high_s_I64x2_S = 1932, // WebAssemblyInstrFormats.td:61 |
| 1948 | extend_high_u_I16x8 = 1933, // WebAssemblyInstrFormats.td:59 |
| 1949 | extend_high_u_I16x8_S = 1934, // WebAssemblyInstrFormats.td:61 |
| 1950 | extend_high_u_I32x4 = 1935, // WebAssemblyInstrFormats.td:59 |
| 1951 | extend_high_u_I32x4_S = 1936, // WebAssemblyInstrFormats.td:61 |
| 1952 | extend_high_u_I64x2 = 1937, // WebAssemblyInstrFormats.td:59 |
| 1953 | extend_high_u_I64x2_S = 1938, // WebAssemblyInstrFormats.td:61 |
| 1954 | extend_low_s_I16x8 = 1939, // WebAssemblyInstrFormats.td:59 |
| 1955 | extend_low_s_I16x8_S = 1940, // WebAssemblyInstrFormats.td:61 |
| 1956 | extend_low_s_I32x4 = 1941, // WebAssemblyInstrFormats.td:59 |
| 1957 | extend_low_s_I32x4_S = 1942, // WebAssemblyInstrFormats.td:61 |
| 1958 | extend_low_s_I64x2 = 1943, // WebAssemblyInstrFormats.td:59 |
| 1959 | extend_low_s_I64x2_S = 1944, // WebAssemblyInstrFormats.td:61 |
| 1960 | extend_low_u_I16x8 = 1945, // WebAssemblyInstrFormats.td:59 |
| 1961 | extend_low_u_I16x8_S = 1946, // WebAssemblyInstrFormats.td:61 |
| 1962 | extend_low_u_I32x4 = 1947, // WebAssemblyInstrFormats.td:59 |
| 1963 | extend_low_u_I32x4_S = 1948, // WebAssemblyInstrFormats.td:61 |
| 1964 | extend_low_u_I64x2 = 1949, // WebAssemblyInstrFormats.td:59 |
| 1965 | extend_low_u_I64x2_S = 1950, // WebAssemblyInstrFormats.td:61 |
| 1966 | fp_to_sint_I16x8 = 1951, // WebAssemblyInstrFormats.td:59 |
| 1967 | fp_to_sint_I16x8_S = 1952, // WebAssemblyInstrFormats.td:61 |
| 1968 | fp_to_sint_I32x4 = 1953, // WebAssemblyInstrFormats.td:59 |
| 1969 | fp_to_sint_I32x4_S = 1954, // WebAssemblyInstrFormats.td:61 |
| 1970 | fp_to_uint_I16x8 = 1955, // WebAssemblyInstrFormats.td:59 |
| 1971 | fp_to_uint_I16x8_S = 1956, // WebAssemblyInstrFormats.td:61 |
| 1972 | fp_to_uint_I32x4 = 1957, // WebAssemblyInstrFormats.td:59 |
| 1973 | fp_to_uint_I32x4_S = 1958, // WebAssemblyInstrFormats.td:61 |
| 1974 | int_wasm_relaxed_trunc_signed_I32x4 = 1959, // WebAssemblyInstrFormats.td:59 |
| 1975 | int_wasm_relaxed_trunc_signed_I32x4_S = 1960, // WebAssemblyInstrFormats.td:61 |
| 1976 | int_wasm_relaxed_trunc_signed_zero_I32x4 = 1961, // WebAssemblyInstrFormats.td:59 |
| 1977 | int_wasm_relaxed_trunc_signed_zero_I32x4_S = 1962, // WebAssemblyInstrFormats.td:61 |
| 1978 | int_wasm_relaxed_trunc_unsigned_I32x4 = 1963, // WebAssemblyInstrFormats.td:59 |
| 1979 | int_wasm_relaxed_trunc_unsigned_I32x4_S = 1964, // WebAssemblyInstrFormats.td:61 |
| 1980 | int_wasm_relaxed_trunc_unsigned_zero_I32x4 = 1965, // WebAssemblyInstrFormats.td:59 |
| 1981 | int_wasm_relaxed_trunc_unsigned_zero_I32x4_S = 1966, // WebAssemblyInstrFormats.td:61 |
| 1982 | promote_low_F32x4 = 1967, // WebAssemblyInstrFormats.td:59 |
| 1983 | promote_low_F32x4_S = 1968, // WebAssemblyInstrFormats.td:61 |
| 1984 | promote_low_F64x2 = 1969, // WebAssemblyInstrFormats.td:59 |
| 1985 | promote_low_F64x2_S = 1970, // WebAssemblyInstrFormats.td:61 |
| 1986 | sint_to_fp_F16x8 = 1971, // WebAssemblyInstrFormats.td:59 |
| 1987 | sint_to_fp_F16x8_S = 1972, // WebAssemblyInstrFormats.td:61 |
| 1988 | sint_to_fp_F32x4 = 1973, // WebAssemblyInstrFormats.td:59 |
| 1989 | sint_to_fp_F32x4_S = 1974, // WebAssemblyInstrFormats.td:61 |
| 1990 | trunc_sat_zero_s_I32x4 = 1975, // WebAssemblyInstrFormats.td:59 |
| 1991 | trunc_sat_zero_s_I32x4_S = 1976, // WebAssemblyInstrFormats.td:61 |
| 1992 | trunc_sat_zero_u_I32x4 = 1977, // WebAssemblyInstrFormats.td:59 |
| 1993 | trunc_sat_zero_u_I32x4_S = 1978, // WebAssemblyInstrFormats.td:61 |
| 1994 | uint_to_fp_F16x8 = 1979, // WebAssemblyInstrFormats.td:59 |
| 1995 | uint_to_fp_F16x8_S = 1980, // WebAssemblyInstrFormats.td:61 |
| 1996 | uint_to_fp_F32x4 = 1981, // WebAssemblyInstrFormats.td:59 |
| 1997 | uint_to_fp_F32x4_S = 1982, // WebAssemblyInstrFormats.td:61 |
| 1998 | INSTRUCTION_LIST_END = 1983 |
| 1999 | }; |
| 2000 | enum RegClassByHwModeUses : uint16_t { |
| 2001 | wasm_ptr_rc, |
| 2002 | }; |
| 2003 | |
| 2004 | } // namespace llvm::WebAssembly |
| 2005 | |
| 2006 | #endif // GET_INSTRINFO_ENUM |
| 2007 | |
| 2008 | #ifdef GET_INSTRINFO_SCHED_ENUM |
| 2009 | #undef GET_INSTRINFO_SCHED_ENUM |
| 2010 | |
| 2011 | namespace llvm::WebAssembly::Sched { |
| 2012 | |
| 2013 | enum { |
| 2014 | NoInstrModel = 0, |
| 2015 | SCHED_LIST_END = 1 |
| 2016 | }; |
| 2017 | |
| 2018 | } // namespace llvm::WebAssembly::Sched |
| 2019 | |
| 2020 | #endif // GET_INSTRINFO_SCHED_ENUM |
| 2021 | |
| 2022 | #if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR) |
| 2023 | |
| 2024 | namespace llvm { |
| 2025 | |
| 2026 | struct WebAssemblyInstrTable { |
| 2027 | MCInstrDesc Insts[1983]; |
| 2028 | static_assert(alignof(MCInstrDesc) >= alignof(MCPhysReg), "Unwanted padding between Insts and ImplicitOps"); |
| 2029 | MCPhysReg ImplicitOps[10]; |
| 2030 | char Padding[sizeof(MCOperandInfo) - sizeof ImplicitOps % sizeof(MCOperandInfo)]; |
| 2031 | static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo"); |
| 2032 | MCOperandInfo OperandInfo[890]; |
| 2033 | }; |
| 2034 | } // namespace llvm |
| 2035 | |
| 2036 | #endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR) |
| 2037 | |
| 2038 | #ifdef GET_INSTRINFO_MC_DESC |
| 2039 | #undef GET_INSTRINFO_MC_DESC |
| 2040 | |
| 2041 | namespace llvm { |
| 2042 | |
| 2043 | static_assert((sizeof WebAssemblyInstrTable::ImplicitOps + sizeof WebAssemblyInstrTable::Padding) % sizeof(MCOperandInfo) == 0); |
| 2044 | static constexpr unsigned WebAssemblyOpInfoBase = (sizeof WebAssemblyInstrTable::ImplicitOps + sizeof WebAssemblyInstrTable::Padding) / sizeof(MCOperandInfo); |
| 2045 | |
| 2046 | extern const WebAssemblyInstrTable WebAssemblyDescs = { |
| 2047 | { |
| 2048 | { 1982, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // uint_to_fp_F32x4_S |
| 2049 | { 1981, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // uint_to_fp_F32x4 |
| 2050 | { 1980, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // uint_to_fp_F16x8_S |
| 2051 | { 1979, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // uint_to_fp_F16x8 |
| 2052 | { 1978, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // trunc_sat_zero_u_I32x4_S |
| 2053 | { 1977, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // trunc_sat_zero_u_I32x4 |
| 2054 | { 1976, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // trunc_sat_zero_s_I32x4_S |
| 2055 | { 1975, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // trunc_sat_zero_s_I32x4 |
| 2056 | { 1974, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // sint_to_fp_F32x4_S |
| 2057 | { 1973, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // sint_to_fp_F32x4 |
| 2058 | { 1972, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // sint_to_fp_F16x8_S |
| 2059 | { 1971, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // sint_to_fp_F16x8 |
| 2060 | { 1970, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // promote_low_F64x2_S |
| 2061 | { 1969, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // promote_low_F64x2 |
| 2062 | { 1968, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // promote_low_F32x4_S |
| 2063 | { 1967, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // promote_low_F32x4 |
| 2064 | { 1966, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // int_wasm_relaxed_trunc_unsigned_zero_I32x4_S |
| 2065 | { 1965, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // int_wasm_relaxed_trunc_unsigned_zero_I32x4 |
| 2066 | { 1964, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // int_wasm_relaxed_trunc_unsigned_I32x4_S |
| 2067 | { 1963, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // int_wasm_relaxed_trunc_unsigned_I32x4 |
| 2068 | { 1962, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // int_wasm_relaxed_trunc_signed_zero_I32x4_S |
| 2069 | { 1961, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // int_wasm_relaxed_trunc_signed_zero_I32x4 |
| 2070 | { 1960, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // int_wasm_relaxed_trunc_signed_I32x4_S |
| 2071 | { 1959, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // int_wasm_relaxed_trunc_signed_I32x4 |
| 2072 | { 1958, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // fp_to_uint_I32x4_S |
| 2073 | { 1957, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // fp_to_uint_I32x4 |
| 2074 | { 1956, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // fp_to_uint_I16x8_S |
| 2075 | { 1955, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // fp_to_uint_I16x8 |
| 2076 | { 1954, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // fp_to_sint_I32x4_S |
| 2077 | { 1953, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // fp_to_sint_I32x4 |
| 2078 | { 1952, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // fp_to_sint_I16x8_S |
| 2079 | { 1951, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // fp_to_sint_I16x8 |
| 2080 | { 1950, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_low_u_I64x2_S |
| 2081 | { 1949, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_low_u_I64x2 |
| 2082 | { 1948, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_low_u_I32x4_S |
| 2083 | { 1947, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_low_u_I32x4 |
| 2084 | { 1946, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_low_u_I16x8_S |
| 2085 | { 1945, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_low_u_I16x8 |
| 2086 | { 1944, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_low_s_I64x2_S |
| 2087 | { 1943, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_low_s_I64x2 |
| 2088 | { 1942, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_low_s_I32x4_S |
| 2089 | { 1941, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_low_s_I32x4 |
| 2090 | { 1940, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_low_s_I16x8_S |
| 2091 | { 1939, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_low_s_I16x8 |
| 2092 | { 1938, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_high_u_I64x2_S |
| 2093 | { 1937, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_high_u_I64x2 |
| 2094 | { 1936, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_high_u_I32x4_S |
| 2095 | { 1935, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_high_u_I32x4 |
| 2096 | { 1934, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_high_u_I16x8_S |
| 2097 | { 1933, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_high_u_I16x8 |
| 2098 | { 1932, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_high_s_I64x2_S |
| 2099 | { 1931, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_high_s_I64x2 |
| 2100 | { 1930, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_high_s_I32x4_S |
| 2101 | { 1929, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_high_s_I32x4 |
| 2102 | { 1928, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_high_s_I16x8_S |
| 2103 | { 1927, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_high_s_I16x8 |
| 2104 | { 1926, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extadd_pairwise_u_I32x4_S |
| 2105 | { 1925, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extadd_pairwise_u_I32x4 |
| 2106 | { 1924, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extadd_pairwise_u_I16x8_S |
| 2107 | { 1923, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extadd_pairwise_u_I16x8 |
| 2108 | { 1922, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extadd_pairwise_s_I32x4_S |
| 2109 | { 1921, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extadd_pairwise_s_I32x4 |
| 2110 | { 1920, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extadd_pairwise_s_I16x8_S |
| 2111 | { 1919, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extadd_pairwise_s_I16x8 |
| 2112 | { 1918, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // demote_zero_F32x4_S |
| 2113 | { 1917, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // demote_zero_F32x4 |
| 2114 | { 1916, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // demote_zero_F16x8_S |
| 2115 | { 1915, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // demote_zero_F16x8 |
| 2116 | { 1914, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // convert_low_u_F64x2_S |
| 2117 | { 1913, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // convert_low_u_F64x2 |
| 2118 | { 1912, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // convert_low_s_F64x2_S |
| 2119 | { 1911, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // convert_low_s_F64x2 |
| 2120 | { 1910, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14865MEMORY_SIZE_A64_S |
| 2121 | { 1909, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 190, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14865MEMORY_SIZE_A64 |
| 2122 | { 1908, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14865MEMORY_GROW_A64_S |
| 2123 | { 1907, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 887, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14865MEMORY_GROW_A64 |
| 2124 | { 1906, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14864MEMORY_SIZE_A32_S |
| 2125 | { 1905, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 188, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14864MEMORY_SIZE_A32 |
| 2126 | { 1904, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14864MEMORY_GROW_A32_S |
| 2127 | { 1903, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 884, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14864MEMORY_GROW_A32 |
| 2128 | { 1902, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_S |
| 2129 | { 1901, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_I64_S |
| 2130 | { 1900, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_I64 |
| 2131 | { 1899, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_I32_S |
| 2132 | { 1898, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_I32 |
| 2133 | { 1897, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR |
| 2134 | { 1896, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Trap)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // UNREACHABLE_S |
| 2135 | { 1895, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Trap)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // UNREACHABLE |
| 2136 | { 1894, 2, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 882, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRY_TABLE_S |
| 2137 | { 1893, 1, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 297, 8, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRY_TABLE |
| 2138 | { 1892, 1, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 297, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRY_S |
| 2139 | { 1891, 1, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 297, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRY |
| 2140 | { 1890, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRUNC_F64x2_S |
| 2141 | { 1889, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRUNC_F64x2 |
| 2142 | { 1888, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRUNC_F64_S |
| 2143 | { 1887, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRUNC_F64 |
| 2144 | { 1886, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRUNC_F32x4_S |
| 2145 | { 1885, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRUNC_F32x4 |
| 2146 | { 1884, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRUNC_F32_S |
| 2147 | { 1883, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 157, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRUNC_F32 |
| 2148 | { 1882, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRUNC_F16x8_S |
| 2149 | { 1881, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRUNC_F16x8 |
| 2150 | { 1880, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 308, 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // THROW_S |
| 2151 | { 1879, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // THROW_REF_S |
| 2152 | { 1878, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 309, 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // THROW_REF |
| 2153 | { 1877, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 308, 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // THROW |
| 2154 | { 1876, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_V128_S |
| 2155 | { 1875, 3, 2, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_V128 |
| 2156 | { 1874, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_I64_S |
| 2157 | { 1873, 3, 2, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_I64 |
| 2158 | { 1872, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_I32_S |
| 2159 | { 1871, 3, 2, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_I32 |
| 2160 | { 1870, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_FUNCREF_S |
| 2161 | { 1869, 3, 2, 0, 0, 0, 1, WebAssemblyOpInfoBase + 879, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_FUNCREF |
| 2162 | { 1868, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_F64_S |
| 2163 | { 1867, 3, 2, 0, 0, 0, 1, WebAssemblyOpInfoBase + 167, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_F64 |
| 2164 | { 1866, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_F32_S |
| 2165 | { 1865, 3, 2, 0, 0, 0, 1, WebAssemblyOpInfoBase + 164, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_F32 |
| 2166 | { 1864, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_EXTERNREF_S |
| 2167 | { 1863, 3, 2, 0, 0, 0, 1, WebAssemblyOpInfoBase + 876, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_EXTERNREF |
| 2168 | { 1862, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_EXNREF_S |
| 2169 | { 1861, 3, 2, 0, 0, 0, 1, WebAssemblyOpInfoBase + 873, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_EXNREF |
| 2170 | { 1860, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 832, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_SIZE_S |
| 2171 | { 1859, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 871, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_SIZE |
| 2172 | { 1858, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 832, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_SET_FUNCREF_S |
| 2173 | { 1857, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 868, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_SET_FUNCREF |
| 2174 | { 1856, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 832, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_SET_EXTERNREF_S |
| 2175 | { 1855, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 865, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_SET_EXTERNREF |
| 2176 | { 1854, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 832, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_SET_EXNREF_S |
| 2177 | { 1853, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 862, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_SET_EXNREF |
| 2178 | { 1852, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 832, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_GROW_FUNCREF_S |
| 2179 | { 1851, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 858, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_GROW_FUNCREF |
| 2180 | { 1850, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 832, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_GROW_EXTERNREF_S |
| 2181 | { 1849, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 854, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_GROW_EXTERNREF |
| 2182 | { 1848, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 832, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_GROW_EXNREF_S |
| 2183 | { 1847, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 850, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_GROW_EXNREF |
| 2184 | { 1846, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 832, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_GET_FUNCREF_S |
| 2185 | { 1845, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 847, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_GET_FUNCREF |
| 2186 | { 1844, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 832, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_GET_EXTERNREF_S |
| 2187 | { 1843, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 844, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_GET_EXTERNREF |
| 2188 | { 1842, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 832, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_GET_EXNREF_S |
| 2189 | { 1841, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 841, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_GET_EXNREF |
| 2190 | { 1840, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 832, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_FILL_FUNCREF_S |
| 2191 | { 1839, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 837, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_FILL_FUNCREF |
| 2192 | { 1838, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 832, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_FILL_EXTERNREF_S |
| 2193 | { 1837, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 833, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_FILL_EXTERNREF |
| 2194 | { 1836, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 832, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_FILL_EXNREF_S |
| 2195 | { 1835, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 828, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_FILL_EXNREF |
| 2196 | { 1834, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 826, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_COPY_S |
| 2197 | { 1833, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 821, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_COPY |
| 2198 | { 1832, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SWIZZLE_S |
| 2199 | { 1831, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SWIZZLE |
| 2200 | { 1830, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_SAT_U_I8x16_S |
| 2201 | { 1829, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_SAT_U_I8x16 |
| 2202 | { 1828, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_SAT_U_I16x8_S |
| 2203 | { 1827, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_SAT_U_I16x8 |
| 2204 | { 1826, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_SAT_S_I8x16_S |
| 2205 | { 1825, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_SAT_S_I8x16 |
| 2206 | { 1824, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_SAT_S_I16x8_S |
| 2207 | { 1823, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_SAT_S_I16x8 |
| 2208 | { 1822, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I8x16_S |
| 2209 | { 1821, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I8x16 |
| 2210 | { 1820, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I64x2_S |
| 2211 | { 1819, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I64x2 |
| 2212 | { 1818, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I64_S |
| 2213 | { 1817, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I64 |
| 2214 | { 1816, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I32x4_S |
| 2215 | { 1815, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I32x4 |
| 2216 | { 1814, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I32_S |
| 2217 | { 1813, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I32 |
| 2218 | { 1812, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I16x8_S |
| 2219 | { 1811, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I16x8 |
| 2220 | { 1810, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F64x2_S |
| 2221 | { 1809, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F64x2 |
| 2222 | { 1808, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F64_S |
| 2223 | { 1807, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 167, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F64 |
| 2224 | { 1806, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F32x4_S |
| 2225 | { 1805, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F32x4 |
| 2226 | { 1804, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F32_S |
| 2227 | { 1803, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 164, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F32 |
| 2228 | { 1802, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F16x8_S |
| 2229 | { 1801, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F16x8 |
| 2230 | { 1800, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_V128_A64_S |
| 2231 | { 1799, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 817, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_V128_A64 |
| 2232 | { 1798, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_V128_A32_S |
| 2233 | { 1797, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 813, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_V128_A32 |
| 2234 | { 1796, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 565, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I8x16_A64_S |
| 2235 | { 1795, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 808, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I8x16_A64 |
| 2236 | { 1794, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 556, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I8x16_A32_S |
| 2237 | { 1793, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 803, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I8x16_A32 |
| 2238 | { 1792, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 565, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I64x2_A64_S |
| 2239 | { 1791, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 808, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I64x2_A64 |
| 2240 | { 1790, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 556, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I64x2_A32_S |
| 2241 | { 1789, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 803, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I64x2_A32 |
| 2242 | { 1788, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 565, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I32x4_A64_S |
| 2243 | { 1787, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 808, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I32x4_A64 |
| 2244 | { 1786, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 556, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I32x4_A32_S |
| 2245 | { 1785, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 803, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I32x4_A32 |
| 2246 | { 1784, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 565, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I16x8_A64_S |
| 2247 | { 1783, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 808, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I16x8_A64 |
| 2248 | { 1782, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 556, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I16x8_A32_S |
| 2249 | { 1781, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 803, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I16x8_A32 |
| 2250 | { 1780, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_I64_A64_S |
| 2251 | { 1779, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 783, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_I64_A64 |
| 2252 | { 1778, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_I64_A32_S |
| 2253 | { 1777, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 779, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_I64_A32 |
| 2254 | { 1776, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_I32_A64_S |
| 2255 | { 1775, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 775, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_I32_A64 |
| 2256 | { 1774, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_I32_A32_S |
| 2257 | { 1773, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 771, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_I32_A32 |
| 2258 | { 1772, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_F64_A64_S |
| 2259 | { 1771, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 799, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_F64_A64 |
| 2260 | { 1770, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_F64_A32_S |
| 2261 | { 1769, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 795, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_F64_A32 |
| 2262 | { 1768, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_F32_A64_S |
| 2263 | { 1767, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 791, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_F32_A64 |
| 2264 | { 1766, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_F32_A32_S |
| 2265 | { 1765, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 787, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_F32_A32 |
| 2266 | { 1764, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_F16_F32_A64_S |
| 2267 | { 1763, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 791, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_F16_F32_A64 |
| 2268 | { 1762, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_F16_F32_A32_S |
| 2269 | { 1761, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 787, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_F16_F32_A32 |
| 2270 | { 1760, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE8_I64_A64_S |
| 2271 | { 1759, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 783, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE8_I64_A64 |
| 2272 | { 1758, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE8_I64_A32_S |
| 2273 | { 1757, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 779, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE8_I64_A32 |
| 2274 | { 1756, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE8_I32_A64_S |
| 2275 | { 1755, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 775, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE8_I32_A64 |
| 2276 | { 1754, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE8_I32_A32_S |
| 2277 | { 1753, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 771, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE8_I32_A32 |
| 2278 | { 1752, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE32_I64_A64_S |
| 2279 | { 1751, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 783, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE32_I64_A64 |
| 2280 | { 1750, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE32_I64_A32_S |
| 2281 | { 1749, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 779, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE32_I64_A32 |
| 2282 | { 1748, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE16_I64_A64_S |
| 2283 | { 1747, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 783, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE16_I64_A64 |
| 2284 | { 1746, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE16_I64_A32_S |
| 2285 | { 1745, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 779, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE16_I64_A32 |
| 2286 | { 1744, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE16_I32_A64_S |
| 2287 | { 1743, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 775, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE16_I32_A64 |
| 2288 | { 1742, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE16_I32_A32_S |
| 2289 | { 1741, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 771, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE16_I32_A32 |
| 2290 | { 1740, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SQRT_F64x2_S |
| 2291 | { 1739, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SQRT_F64x2 |
| 2292 | { 1738, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SQRT_F64_S |
| 2293 | { 1737, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SQRT_F64 |
| 2294 | { 1736, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SQRT_F32x4_S |
| 2295 | { 1735, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SQRT_F32x4 |
| 2296 | { 1734, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SQRT_F32_S |
| 2297 | { 1733, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 157, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SQRT_F32 |
| 2298 | { 1732, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SQRT_F16x8_S |
| 2299 | { 1731, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SQRT_F16x8 |
| 2300 | { 1730, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_I8x16_S |
| 2301 | { 1729, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 767, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_I8x16 |
| 2302 | { 1728, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_I64x2_S |
| 2303 | { 1727, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 769, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_I64x2 |
| 2304 | { 1726, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_I32x4_S |
| 2305 | { 1725, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 767, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_I32x4 |
| 2306 | { 1724, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_I16x8_S |
| 2307 | { 1723, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 767, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_I16x8 |
| 2308 | { 1722, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_F64x2_S |
| 2309 | { 1721, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 765, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_F64x2 |
| 2310 | { 1720, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_F32x4_S |
| 2311 | { 1719, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 763, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_F32x4 |
| 2312 | { 1718, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_F16x8_S |
| 2313 | { 1717, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 763, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_F16x8 |
| 2314 | { 1716, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SIMD_RELAXED_FMIN_F64x2_S |
| 2315 | { 1715, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SIMD_RELAXED_FMIN_F64x2 |
| 2316 | { 1714, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SIMD_RELAXED_FMIN_F32x4_S |
| 2317 | { 1713, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SIMD_RELAXED_FMIN_F32x4 |
| 2318 | { 1712, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SIMD_RELAXED_FMAX_F64x2_S |
| 2319 | { 1711, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SIMD_RELAXED_FMAX_F64x2 |
| 2320 | { 1710, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SIMD_RELAXED_FMAX_F32x4_S |
| 2321 | { 1709, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SIMD_RELAXED_FMAX_F32x4 |
| 2322 | { 1708, 16, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 388, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHUFFLE_S |
| 2323 | { 1707, 19, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 744, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHUFFLE |
| 2324 | { 1706, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_U_I8x16_S |
| 2325 | { 1705, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 741, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_U_I8x16 |
| 2326 | { 1704, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_U_I64x2_S |
| 2327 | { 1703, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 741, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_U_I64x2 |
| 2328 | { 1702, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_U_I64_S |
| 2329 | { 1701, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_U_I64 |
| 2330 | { 1700, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_U_I32x4_S |
| 2331 | { 1699, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 741, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_U_I32x4 |
| 2332 | { 1698, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_U_I32_S |
| 2333 | { 1697, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_U_I32 |
| 2334 | { 1696, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_U_I16x8_S |
| 2335 | { 1695, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 741, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_U_I16x8 |
| 2336 | { 1694, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_S_I8x16_S |
| 2337 | { 1693, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 741, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_S_I8x16 |
| 2338 | { 1692, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_S_I64x2_S |
| 2339 | { 1691, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 741, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_S_I64x2 |
| 2340 | { 1690, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_S_I64_S |
| 2341 | { 1689, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_S_I64 |
| 2342 | { 1688, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_S_I32x4_S |
| 2343 | { 1687, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 741, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_S_I32x4 |
| 2344 | { 1686, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_S_I32_S |
| 2345 | { 1685, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_S_I32 |
| 2346 | { 1684, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_S_I16x8_S |
| 2347 | { 1683, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 741, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_S_I16x8 |
| 2348 | { 1682, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_I8x16_S |
| 2349 | { 1681, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 741, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_I8x16 |
| 2350 | { 1680, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_I64x2_S |
| 2351 | { 1679, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 741, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_I64x2 |
| 2352 | { 1678, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_I64_S |
| 2353 | { 1677, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_I64 |
| 2354 | { 1676, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_I32x4_S |
| 2355 | { 1675, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 741, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_I32x4 |
| 2356 | { 1674, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_I32_S |
| 2357 | { 1673, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_I32 |
| 2358 | { 1672, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_I16x8_S |
| 2359 | { 1671, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 741, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_I16x8 |
| 2360 | { 1670, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_V128_S |
| 2361 | { 1669, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 737, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_V128 |
| 2362 | { 1668, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 736, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_T_S |
| 2363 | { 1667, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 736, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_T |
| 2364 | { 1666, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_I64_S |
| 2365 | { 1665, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 732, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_I64 |
| 2366 | { 1664, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_I32_S |
| 2367 | { 1663, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 728, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_I32 |
| 2368 | { 1662, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_FUNCREF_S |
| 2369 | { 1661, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 724, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_FUNCREF |
| 2370 | { 1660, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_F64_S |
| 2371 | { 1659, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 720, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_F64 |
| 2372 | { 1658, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_F32_S |
| 2373 | { 1657, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 716, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_F32 |
| 2374 | { 1656, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_EXTERNREF_S |
| 2375 | { 1655, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 712, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_EXTERNREF |
| 2376 | { 1654, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_EXNREF_S |
| 2377 | { 1653, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 708, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_EXNREF |
| 2378 | { 1652, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ROTR_I64_S |
| 2379 | { 1651, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ROTR_I64 |
| 2380 | { 1650, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ROTR_I32_S |
| 2381 | { 1649, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ROTR_I32 |
| 2382 | { 1648, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ROTL_I64_S |
| 2383 | { 1647, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ROTL_I64 |
| 2384 | { 1646, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ROTL_I32_S |
| 2385 | { 1645, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ROTL_I32 |
| 2386 | { 1644, 1, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 151, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RET_CALL_S |
| 2387 | { 1643, 1, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 307, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RET_CALL_REF_S |
| 2388 | { 1642, 2, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 305, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RET_CALL_REF |
| 2389 | { 1641, 2, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 303, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RET_CALL_INDIRECT_S |
| 2390 | { 1640, 2, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 303, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RET_CALL_INDIRECT |
| 2391 | { 1639, 1, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 151, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RET_CALL |
| 2392 | { 1638, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RETURN_S |
| 2393 | { 1637, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RETURN |
| 2394 | { 1636, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 154, 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RETHROW_S |
| 2395 | { 1635, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 154, 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RETHROW |
| 2396 | { 1634, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 429, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_I8x16_S |
| 2397 | { 1633, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 700, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_I8x16 |
| 2398 | { 1632, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 429, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_I64x2_S |
| 2399 | { 1631, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 704, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_I64x2 |
| 2400 | { 1630, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 429, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_I32x4_S |
| 2401 | { 1629, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 700, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_I32x4 |
| 2402 | { 1628, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 429, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_I16x8_S |
| 2403 | { 1627, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 700, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_I16x8 |
| 2404 | { 1626, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 429, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_F64x2_S |
| 2405 | { 1625, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 696, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_F64x2 |
| 2406 | { 1624, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 429, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_F32x4_S |
| 2407 | { 1623, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 692, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_F32x4 |
| 2408 | { 1622, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 429, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_F16x8_S |
| 2409 | { 1621, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 692, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_F16x8 |
| 2410 | { 1620, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REM_U_I64_S |
| 2411 | { 1619, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REM_U_I64 |
| 2412 | { 1618, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REM_U_I32_S |
| 2413 | { 1617, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REM_U_I32 |
| 2414 | { 1616, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REM_S_I64_S |
| 2415 | { 1615, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REM_S_I64 |
| 2416 | { 1614, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REM_S_I32_S |
| 2417 | { 1613, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REM_S_I32 |
| 2418 | { 1612, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELAXED_SWIZZLE_S |
| 2419 | { 1611, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELAXED_SWIZZLE |
| 2420 | { 1610, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELAXED_Q15MULR_S_I16x8_S |
| 2421 | { 1609, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELAXED_Q15MULR_S_I16x8 |
| 2422 | { 1608, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELAXED_DOT_S |
| 2423 | { 1607, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELAXED_DOT_BFLOAT_S |
| 2424 | { 1606, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 293, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELAXED_DOT_BFLOAT |
| 2425 | { 1605, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELAXED_DOT_ADD_S |
| 2426 | { 1604, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 293, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELAXED_DOT_ADD |
| 2427 | { 1603, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELAXED_DOT |
| 2428 | { 1602, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 307, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_TEST_FUNCREF_S |
| 2429 | { 1601, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 689, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_TEST_FUNCREF |
| 2430 | { 1600, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_NULL_FUNCREF_S |
| 2431 | { 1599, 1, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 413, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_NULL_FUNCREF |
| 2432 | { 1598, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_NULL_EXTERNREF_S |
| 2433 | { 1597, 1, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 410, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_NULL_EXTERNREF |
| 2434 | { 1596, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_NULL_EXNREF_S |
| 2435 | { 1595, 1, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 309, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_NULL_EXNREF |
| 2436 | { 1594, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_IS_NULL_FUNCREF_S |
| 2437 | { 1593, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 687, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_IS_NULL_FUNCREF |
| 2438 | { 1592, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_IS_NULL_EXTERNREF_S |
| 2439 | { 1591, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 685, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_IS_NULL_EXTERNREF |
| 2440 | { 1590, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_IS_NULL_EXNREF_S |
| 2441 | { 1589, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 683, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_IS_NULL_EXNREF |
| 2442 | { 1588, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 151, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_FUNC_S |
| 2443 | { 1587, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 681, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_FUNC |
| 2444 | { 1586, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 307, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_CAST_FUNCREF_S |
| 2445 | { 1585, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 678, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_CAST_FUNCREF |
| 2446 | { 1584, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Q15MULR_SAT_S_I16x8_S |
| 2447 | { 1583, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Q15MULR_SAT_S_I16x8 |
| 2448 | { 1582, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // POPCNT_I8x16_S |
| 2449 | { 1581, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // POPCNT_I8x16 |
| 2450 | { 1580, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // POPCNT_I64_S |
| 2451 | { 1579, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 312, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // POPCNT_I64 |
| 2452 | { 1578, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // POPCNT_I32_S |
| 2453 | { 1577, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 310, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // POPCNT_I32 |
| 2454 | { 1576, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PMIN_F64x2_S |
| 2455 | { 1575, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PMIN_F64x2 |
| 2456 | { 1574, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PMIN_F32x4_S |
| 2457 | { 1573, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PMIN_F32x4 |
| 2458 | { 1572, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PMIN_F16x8_S |
| 2459 | { 1571, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PMIN_F16x8 |
| 2460 | { 1570, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PMAX_F64x2_S |
| 2461 | { 1569, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PMAX_F64x2 |
| 2462 | { 1568, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PMAX_F32x4_S |
| 2463 | { 1567, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PMAX_F32x4 |
| 2464 | { 1566, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PMAX_F16x8_S |
| 2465 | { 1565, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PMAX_F16x8 |
| 2466 | { 1564, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_S |
| 2467 | { 1563, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_I64_S |
| 2468 | { 1562, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_I64 |
| 2469 | { 1561, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_I32_S |
| 2470 | { 1560, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_I32 |
| 2471 | { 1559, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR |
| 2472 | { 1558, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NOT_S |
| 2473 | { 1557, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NOT |
| 2474 | { 1556, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NOP_S |
| 2475 | { 1555, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NOP |
| 2476 | { 1554, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NMADD_F64x2_S |
| 2477 | { 1553, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 293, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NMADD_F64x2 |
| 2478 | { 1552, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NMADD_F32x4_S |
| 2479 | { 1551, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 293, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NMADD_F32x4 |
| 2480 | { 1550, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NMADD_F16x8_S |
| 2481 | { 1549, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 293, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NMADD_F16x8 |
| 2482 | { 1548, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_I8x16_S |
| 2483 | { 1547, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_I8x16 |
| 2484 | { 1546, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_I64x2_S |
| 2485 | { 1545, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_I64x2 |
| 2486 | { 1544, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_I64_S |
| 2487 | { 1543, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 423, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_I64 |
| 2488 | { 1542, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_I32x4_S |
| 2489 | { 1541, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_I32x4 |
| 2490 | { 1540, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_I32_S |
| 2491 | { 1539, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_I32 |
| 2492 | { 1538, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_I16x8_S |
| 2493 | { 1537, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_I16x8 |
| 2494 | { 1536, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_F64x2_S |
| 2495 | { 1535, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_F64x2 |
| 2496 | { 1534, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_F64_S |
| 2497 | { 1533, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 420, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_F64 |
| 2498 | { 1532, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_F32x4_S |
| 2499 | { 1531, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_F32x4 |
| 2500 | { 1530, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_F32_S |
| 2501 | { 1529, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 417, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_F32 |
| 2502 | { 1528, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_F16x8_S |
| 2503 | { 1527, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_F16x8 |
| 2504 | { 1526, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_I8x16_S |
| 2505 | { 1525, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_I8x16 |
| 2506 | { 1524, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_I64x2_S |
| 2507 | { 1523, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_I64x2 |
| 2508 | { 1522, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_I32x4_S |
| 2509 | { 1521, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_I32x4 |
| 2510 | { 1520, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_I16x8_S |
| 2511 | { 1519, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_I16x8 |
| 2512 | { 1518, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_F64x2_S |
| 2513 | { 1517, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_F64x2 |
| 2514 | { 1516, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_F64_S |
| 2515 | { 1515, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_F64 |
| 2516 | { 1514, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_F32x4_S |
| 2517 | { 1513, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_F32x4 |
| 2518 | { 1512, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_F32_S |
| 2519 | { 1511, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 157, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_F32 |
| 2520 | { 1510, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_F16x8_S |
| 2521 | { 1509, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_F16x8 |
| 2522 | { 1508, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEAREST_F64x2_S |
| 2523 | { 1507, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEAREST_F64x2 |
| 2524 | { 1506, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEAREST_F64_S |
| 2525 | { 1505, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEAREST_F64 |
| 2526 | { 1504, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEAREST_F32x4_S |
| 2527 | { 1503, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEAREST_F32x4 |
| 2528 | { 1502, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEAREST_F32_S |
| 2529 | { 1501, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 157, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEAREST_F32 |
| 2530 | { 1500, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEAREST_F16x8_S |
| 2531 | { 1499, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEAREST_F16x8 |
| 2532 | { 1498, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NARROW_U_I8x16_S |
| 2533 | { 1497, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NARROW_U_I8x16 |
| 2534 | { 1496, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NARROW_U_I16x8_S |
| 2535 | { 1495, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NARROW_U_I16x8 |
| 2536 | { 1494, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NARROW_S_I8x16_S |
| 2537 | { 1493, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NARROW_S_I8x16 |
| 2538 | { 1492, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NARROW_S_I16x8_S |
| 2539 | { 1491, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NARROW_S_I16x8 |
| 2540 | { 1490, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_I64x2_S |
| 2541 | { 1489, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_I64x2 |
| 2542 | { 1488, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_I64_S |
| 2543 | { 1487, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_I64 |
| 2544 | { 1486, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_I32x4_S |
| 2545 | { 1485, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_I32x4 |
| 2546 | { 1484, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_I32_S |
| 2547 | { 1483, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_I32 |
| 2548 | { 1482, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_I16x8_S |
| 2549 | { 1481, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_I16x8 |
| 2550 | { 1480, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_F64x2_S |
| 2551 | { 1479, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_F64x2 |
| 2552 | { 1478, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_F64_S |
| 2553 | { 1477, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 167, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_F64 |
| 2554 | { 1476, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_F32x4_S |
| 2555 | { 1475, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_F32x4 |
| 2556 | { 1474, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_F32_S |
| 2557 | { 1473, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 164, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_F32 |
| 2558 | { 1472, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_F16x8_S |
| 2559 | { 1471, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_F16x8 |
| 2560 | { 1470, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_U_I8x16_S |
| 2561 | { 1469, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_U_I8x16 |
| 2562 | { 1468, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_U_I32x4_S |
| 2563 | { 1467, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_U_I32x4 |
| 2564 | { 1466, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_U_I16x8_S |
| 2565 | { 1465, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_U_I16x8 |
| 2566 | { 1464, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_S_I8x16_S |
| 2567 | { 1463, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_S_I8x16 |
| 2568 | { 1462, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_S_I32x4_S |
| 2569 | { 1461, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_S_I32x4 |
| 2570 | { 1460, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_S_I16x8_S |
| 2571 | { 1459, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_S_I16x8 |
| 2572 | { 1458, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_F64x2_S |
| 2573 | { 1457, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_F64x2 |
| 2574 | { 1456, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_F64_S |
| 2575 | { 1455, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 167, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_F64 |
| 2576 | { 1454, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_F32x4_S |
| 2577 | { 1453, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_F32x4 |
| 2578 | { 1452, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_F32_S |
| 2579 | { 1451, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 164, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_F32 |
| 2580 | { 1450, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_F16x8_S |
| 2581 | { 1449, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_F16x8 |
| 2582 | { 1448, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 322, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMSET_A64_S |
| 2583 | { 1447, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 669, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMSET_A64 |
| 2584 | { 1446, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 322, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMSET_A32_S |
| 2585 | { 1445, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 665, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMSET_A32 |
| 2586 | { 1444, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 630, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_INIT_A64_S |
| 2587 | { 1443, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 673, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_INIT_A64 |
| 2588 | { 1442, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 630, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_INIT_A32_S |
| 2589 | { 1441, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 625, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_INIT_A32 |
| 2590 | { 1440, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 322, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_FILL_A64_S |
| 2591 | { 1439, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 669, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_FILL_A64 |
| 2592 | { 1438, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 322, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_FILL_A32_S |
| 2593 | { 1437, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 665, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_FILL_A32 |
| 2594 | { 1436, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 630, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_COPY_A64_S |
| 2595 | { 1435, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 632, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_COPY_A64 |
| 2596 | { 1434, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 630, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_COPY_A32_S |
| 2597 | { 1433, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 625, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_COPY_A32 |
| 2598 | { 1432, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_ATOMIC_WAIT64_A64_S |
| 2599 | { 1431, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 658, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_ATOMIC_WAIT64_A64 |
| 2600 | { 1430, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_ATOMIC_WAIT64_A32_S |
| 2601 | { 1429, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 651, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_ATOMIC_WAIT64_A32 |
| 2602 | { 1428, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_ATOMIC_WAIT32_A64_S |
| 2603 | { 1427, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 644, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_ATOMIC_WAIT32_A64 |
| 2604 | { 1426, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_ATOMIC_WAIT32_A32_S |
| 2605 | { 1425, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 637, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_ATOMIC_WAIT32_A32 |
| 2606 | { 1424, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_ATOMIC_NOTIFY_A64_S |
| 2607 | { 1423, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_ATOMIC_NOTIFY_A64 |
| 2608 | { 1422, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_ATOMIC_NOTIFY_A32_S |
| 2609 | { 1421, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_ATOMIC_NOTIFY_A32 |
| 2610 | { 1420, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 630, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMCPY_A64_S |
| 2611 | { 1419, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 632, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMCPY_A64 |
| 2612 | { 1418, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 630, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMCPY_A32_S |
| 2613 | { 1417, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 625, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMCPY_A32 |
| 2614 | { 1416, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_U_I8x16_S |
| 2615 | { 1415, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_U_I8x16 |
| 2616 | { 1414, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_U_I32x4_S |
| 2617 | { 1413, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_U_I32x4 |
| 2618 | { 1412, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_U_I16x8_S |
| 2619 | { 1411, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_U_I16x8 |
| 2620 | { 1410, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_S_I8x16_S |
| 2621 | { 1409, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_S_I8x16 |
| 2622 | { 1408, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_S_I32x4_S |
| 2623 | { 1407, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_S_I32x4 |
| 2624 | { 1406, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_S_I16x8_S |
| 2625 | { 1405, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_S_I16x8 |
| 2626 | { 1404, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_F64x2_S |
| 2627 | { 1403, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_F64x2 |
| 2628 | { 1402, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_F64_S |
| 2629 | { 1401, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 167, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_F64 |
| 2630 | { 1400, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_F32x4_S |
| 2631 | { 1399, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_F32x4 |
| 2632 | { 1398, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_F32_S |
| 2633 | { 1397, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 164, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_F32 |
| 2634 | { 1396, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_F16x8_S |
| 2635 | { 1395, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_F16x8 |
| 2636 | { 1394, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MADD_F64x2_S |
| 2637 | { 1393, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 293, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MADD_F64x2 |
| 2638 | { 1392, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MADD_F32x4_S |
| 2639 | { 1391, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 293, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MADD_F32x4 |
| 2640 | { 1390, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MADD_F16x8_S |
| 2641 | { 1389, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 293, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MADD_F16x8 |
| 2642 | { 1388, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_U_I8x16_S |
| 2643 | { 1387, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_U_I8x16 |
| 2644 | { 1386, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_U_I64_S |
| 2645 | { 1385, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 423, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_U_I64 |
| 2646 | { 1384, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_U_I32x4_S |
| 2647 | { 1383, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_U_I32x4 |
| 2648 | { 1382, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_U_I32_S |
| 2649 | { 1381, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_U_I32 |
| 2650 | { 1380, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_U_I16x8_S |
| 2651 | { 1379, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_U_I16x8 |
| 2652 | { 1378, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_S_I8x16_S |
| 2653 | { 1377, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_S_I8x16 |
| 2654 | { 1376, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_S_I64x2_S |
| 2655 | { 1375, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_S_I64x2 |
| 2656 | { 1374, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_S_I64_S |
| 2657 | { 1373, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 423, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_S_I64 |
| 2658 | { 1372, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_S_I32x4_S |
| 2659 | { 1371, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_S_I32x4 |
| 2660 | { 1370, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_S_I32_S |
| 2661 | { 1369, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_S_I32 |
| 2662 | { 1368, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_S_I16x8_S |
| 2663 | { 1367, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_S_I16x8 |
| 2664 | { 1366, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_F64x2_S |
| 2665 | { 1365, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_F64x2 |
| 2666 | { 1364, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_F64_S |
| 2667 | { 1363, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 420, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_F64 |
| 2668 | { 1362, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_F32x4_S |
| 2669 | { 1361, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_F32x4 |
| 2670 | { 1360, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_F32_S |
| 2671 | { 1359, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 417, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_F32 |
| 2672 | { 1358, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_F16x8_S |
| 2673 | { 1357, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_F16x8 |
| 2674 | { 1356, 1, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 297, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOOP_S |
| 2675 | { 1355, 1, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 297, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOOP |
| 2676 | { 1354, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_V128_S |
| 2677 | { 1353, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 622, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_V128 |
| 2678 | { 1352, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_I64_S |
| 2679 | { 1351, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 619, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_I64 |
| 2680 | { 1350, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_I32_S |
| 2681 | { 1349, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 616, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_I32 |
| 2682 | { 1348, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_FUNCREF_S |
| 2683 | { 1347, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 613, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_FUNCREF |
| 2684 | { 1346, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_F64_S |
| 2685 | { 1345, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 610, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_F64 |
| 2686 | { 1344, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_F32_S |
| 2687 | { 1343, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 607, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_F32 |
| 2688 | { 1342, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_EXTERNREF_S |
| 2689 | { 1341, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 604, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_EXTERNREF |
| 2690 | { 1340, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_EXNREF_S |
| 2691 | { 1339, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 601, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_EXNREF |
| 2692 | { 1338, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_V128_S |
| 2693 | { 1337, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 599, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_V128 |
| 2694 | { 1336, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_I64_S |
| 2695 | { 1335, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 597, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_I64 |
| 2696 | { 1334, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_I32_S |
| 2697 | { 1333, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 595, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_I32 |
| 2698 | { 1332, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_FUNCREF_S |
| 2699 | { 1331, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 593, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_FUNCREF |
| 2700 | { 1330, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_F64_S |
| 2701 | { 1329, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 591, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_F64 |
| 2702 | { 1328, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_F32_S |
| 2703 | { 1327, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 589, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_F32 |
| 2704 | { 1326, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_EXTERNREF_S |
| 2705 | { 1325, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 587, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_EXTERNREF |
| 2706 | { 1324, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_EXNREF_S |
| 2707 | { 1323, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 585, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_EXNREF |
| 2708 | { 1322, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_V128_S |
| 2709 | { 1321, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 583, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_V128 |
| 2710 | { 1320, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_I64_S |
| 2711 | { 1319, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 581, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_I64 |
| 2712 | { 1318, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_I32_S |
| 2713 | { 1317, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 579, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_I32 |
| 2714 | { 1316, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_FUNCREF_S |
| 2715 | { 1315, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 577, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_FUNCREF |
| 2716 | { 1314, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_F64_S |
| 2717 | { 1313, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 575, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_F64 |
| 2718 | { 1312, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_F32_S |
| 2719 | { 1311, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 573, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_F32 |
| 2720 | { 1310, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_EXTERNREF_S |
| 2721 | { 1309, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 571, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_EXTERNREF |
| 2722 | { 1308, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_EXNREF_S |
| 2723 | { 1307, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 568, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_EXNREF |
| 2724 | { 1306, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_ZERO_64_A64_S |
| 2725 | { 1305, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 512, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_ZERO_64_A64 |
| 2726 | { 1304, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_ZERO_64_A32_S |
| 2727 | { 1303, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 506, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_ZERO_64_A32 |
| 2728 | { 1302, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_ZERO_32_A64_S |
| 2729 | { 1301, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 512, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_ZERO_32_A64 |
| 2730 | { 1300, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_ZERO_32_A32_S |
| 2731 | { 1299, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 506, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_ZERO_32_A32 |
| 2732 | { 1298, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_V128_A64_S |
| 2733 | { 1297, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 512, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_V128_A64 |
| 2734 | { 1296, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_V128_A32_S |
| 2735 | { 1295, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 506, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_V128_A32 |
| 2736 | { 1294, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 565, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_8_A64_S |
| 2737 | { 1293, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 559, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_8_A64 |
| 2738 | { 1292, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 556, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_8_A32_S |
| 2739 | { 1291, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 550, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_8_A32 |
| 2740 | { 1290, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 565, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_64_A64_S |
| 2741 | { 1289, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 559, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_64_A64 |
| 2742 | { 1288, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 556, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_64_A32_S |
| 2743 | { 1287, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 550, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_64_A32 |
| 2744 | { 1286, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 565, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_32_A64_S |
| 2745 | { 1285, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 559, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_32_A64 |
| 2746 | { 1284, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 556, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_32_A32_S |
| 2747 | { 1283, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 550, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_32_A32 |
| 2748 | { 1282, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 565, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_16_A64_S |
| 2749 | { 1281, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 559, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_16_A64 |
| 2750 | { 1280, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 556, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_16_A32_S |
| 2751 | { 1279, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 550, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_16_A32 |
| 2752 | { 1278, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_I64_A64_S |
| 2753 | { 1277, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 530, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_I64_A64 |
| 2754 | { 1276, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_I64_A32_S |
| 2755 | { 1275, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 526, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_I64_A32 |
| 2756 | { 1274, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_I32_A64_S |
| 2757 | { 1273, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 522, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_I32_A64 |
| 2758 | { 1272, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_I32_A32_S |
| 2759 | { 1271, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 518, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_I32_A32 |
| 2760 | { 1270, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_F64_A64_S |
| 2761 | { 1269, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 546, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_F64_A64 |
| 2762 | { 1268, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_F64_A32_S |
| 2763 | { 1267, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 542, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_F64_A32 |
| 2764 | { 1266, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_F32_A64_S |
| 2765 | { 1265, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 538, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_F32_A64 |
| 2766 | { 1264, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_F32_A32_S |
| 2767 | { 1263, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 534, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_F32_A32 |
| 2768 | { 1262, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_F16_F32_A64_S |
| 2769 | { 1261, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 538, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_F16_F32_A64 |
| 2770 | { 1260, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_F16_F32_A32_S |
| 2771 | { 1259, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 534, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_F16_F32_A32 |
| 2772 | { 1258, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_U_I64x2_A64_S |
| 2773 | { 1257, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 512, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_U_I64x2_A64 |
| 2774 | { 1256, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_U_I64x2_A32_S |
| 2775 | { 1255, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 506, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_U_I64x2_A32 |
| 2776 | { 1254, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_U_I32x4_A64_S |
| 2777 | { 1253, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 512, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_U_I32x4_A64 |
| 2778 | { 1252, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_U_I32x4_A32_S |
| 2779 | { 1251, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 506, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_U_I32x4_A32 |
| 2780 | { 1250, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_U_I16x8_A64_S |
| 2781 | { 1249, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 512, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_U_I16x8_A64 |
| 2782 | { 1248, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_U_I16x8_A32_S |
| 2783 | { 1247, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 506, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_U_I16x8_A32 |
| 2784 | { 1246, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_S_I64x2_A64_S |
| 2785 | { 1245, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 512, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_S_I64x2_A64 |
| 2786 | { 1244, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_S_I64x2_A32_S |
| 2787 | { 1243, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 506, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_S_I64x2_A32 |
| 2788 | { 1242, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_S_I32x4_A64_S |
| 2789 | { 1241, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 512, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_S_I32x4_A64 |
| 2790 | { 1240, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_S_I32x4_A32_S |
| 2791 | { 1239, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 506, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_S_I32x4_A32 |
| 2792 | { 1238, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_S_I16x8_A64_S |
| 2793 | { 1237, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 512, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_S_I16x8_A64 |
| 2794 | { 1236, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_S_I16x8_A32_S |
| 2795 | { 1235, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 506, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_S_I16x8_A32 |
| 2796 | { 1234, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_U_I64_A64_S |
| 2797 | { 1233, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 530, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_U_I64_A64 |
| 2798 | { 1232, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_U_I64_A32_S |
| 2799 | { 1231, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 526, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_U_I64_A32 |
| 2800 | { 1230, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_U_I32_A64_S |
| 2801 | { 1229, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 522, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_U_I32_A64 |
| 2802 | { 1228, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_U_I32_A32_S |
| 2803 | { 1227, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 518, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_U_I32_A32 |
| 2804 | { 1226, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_S_I64_A64_S |
| 2805 | { 1225, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 530, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_S_I64_A64 |
| 2806 | { 1224, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_S_I64_A32_S |
| 2807 | { 1223, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 526, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_S_I64_A32 |
| 2808 | { 1222, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_S_I32_A64_S |
| 2809 | { 1221, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 522, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_S_I32_A64 |
| 2810 | { 1220, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_S_I32_A32_S |
| 2811 | { 1219, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 518, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_S_I32_A32 |
| 2812 | { 1218, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_SPLAT_A64_S |
| 2813 | { 1217, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 512, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_SPLAT_A64 |
| 2814 | { 1216, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_SPLAT_A32_S |
| 2815 | { 1215, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 506, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_SPLAT_A32 |
| 2816 | { 1214, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD64_SPLAT_A64_S |
| 2817 | { 1213, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 512, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD64_SPLAT_A64 |
| 2818 | { 1212, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD64_SPLAT_A32_S |
| 2819 | { 1211, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 506, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD64_SPLAT_A32 |
| 2820 | { 1210, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD32_U_I64_A64_S |
| 2821 | { 1209, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 530, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD32_U_I64_A64 |
| 2822 | { 1208, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD32_U_I64_A32_S |
| 2823 | { 1207, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 526, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD32_U_I64_A32 |
| 2824 | { 1206, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD32_S_I64_A64_S |
| 2825 | { 1205, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 530, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD32_S_I64_A64 |
| 2826 | { 1204, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD32_S_I64_A32_S |
| 2827 | { 1203, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 526, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD32_S_I64_A32 |
| 2828 | { 1202, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD32_SPLAT_A64_S |
| 2829 | { 1201, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 512, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD32_SPLAT_A64 |
| 2830 | { 1200, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD32_SPLAT_A32_S |
| 2831 | { 1199, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 506, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD32_SPLAT_A32 |
| 2832 | { 1198, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_U_I64_A64_S |
| 2833 | { 1197, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 530, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_U_I64_A64 |
| 2834 | { 1196, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_U_I64_A32_S |
| 2835 | { 1195, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 526, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_U_I64_A32 |
| 2836 | { 1194, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_U_I32_A64_S |
| 2837 | { 1193, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 522, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_U_I32_A64 |
| 2838 | { 1192, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_U_I32_A32_S |
| 2839 | { 1191, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 518, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_U_I32_A32 |
| 2840 | { 1190, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_S_I64_A64_S |
| 2841 | { 1189, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 530, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_S_I64_A64 |
| 2842 | { 1188, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_S_I64_A32_S |
| 2843 | { 1187, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 526, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_S_I64_A32 |
| 2844 | { 1186, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_S_I32_A64_S |
| 2845 | { 1185, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 522, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_S_I32_A64 |
| 2846 | { 1184, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_S_I32_A32_S |
| 2847 | { 1183, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 518, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_S_I32_A32 |
| 2848 | { 1182, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_SPLAT_A64_S |
| 2849 | { 1181, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 512, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_SPLAT_A64 |
| 2850 | { 1180, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_SPLAT_A32_S |
| 2851 | { 1179, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 506, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_SPLAT_A32 |
| 2852 | { 1178, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_U_I8x16_S |
| 2853 | { 1177, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_U_I8x16 |
| 2854 | { 1176, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_U_I64_S |
| 2855 | { 1175, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 423, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_U_I64 |
| 2856 | { 1174, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_U_I32x4_S |
| 2857 | { 1173, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_U_I32x4 |
| 2858 | { 1172, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_U_I32_S |
| 2859 | { 1171, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_U_I32 |
| 2860 | { 1170, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_U_I16x8_S |
| 2861 | { 1169, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_U_I16x8 |
| 2862 | { 1168, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_S_I8x16_S |
| 2863 | { 1167, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_S_I8x16 |
| 2864 | { 1166, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_S_I64x2_S |
| 2865 | { 1165, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_S_I64x2 |
| 2866 | { 1164, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_S_I64_S |
| 2867 | { 1163, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 423, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_S_I64 |
| 2868 | { 1162, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_S_I32x4_S |
| 2869 | { 1161, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_S_I32x4 |
| 2870 | { 1160, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_S_I32_S |
| 2871 | { 1159, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_S_I32 |
| 2872 | { 1158, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_S_I16x8_S |
| 2873 | { 1157, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_S_I16x8 |
| 2874 | { 1156, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_F64x2_S |
| 2875 | { 1155, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_F64x2 |
| 2876 | { 1154, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_F64_S |
| 2877 | { 1153, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 420, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_F64 |
| 2878 | { 1152, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_F32x4_S |
| 2879 | { 1151, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_F32x4 |
| 2880 | { 1150, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_F32_S |
| 2881 | { 1149, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 417, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_F32 |
| 2882 | { 1148, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_F16x8_S |
| 2883 | { 1147, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_F16x8 |
| 2884 | { 1146, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LANESELECT_I8x16_S |
| 2885 | { 1145, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 293, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LANESELECT_I8x16 |
| 2886 | { 1144, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LANESELECT_I64x2_S |
| 2887 | { 1143, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 293, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LANESELECT_I64x2 |
| 2888 | { 1142, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LANESELECT_I32x4_S |
| 2889 | { 1141, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 293, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LANESELECT_I32x4 |
| 2890 | { 1140, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LANESELECT_I16x8_S |
| 2891 | { 1139, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 293, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LANESELECT_I16x8 |
| 2892 | { 1138, 1, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 297, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // IF_S |
| 2893 | { 1137, 2, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 504, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // IF |
| 2894 | { 1136, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_U_SAT_F64_S |
| 2895 | { 1135, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 457, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_U_SAT_F64 |
| 2896 | { 1134, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_U_SAT_F32_S |
| 2897 | { 1133, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 455, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_U_SAT_F32 |
| 2898 | { 1132, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_U_F64_S |
| 2899 | { 1131, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 457, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_U_F64 |
| 2900 | { 1130, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_U_F32_S |
| 2901 | { 1129, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 455, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_U_F32 |
| 2902 | { 1128, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_S_SAT_F64_S |
| 2903 | { 1127, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 457, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_S_SAT_F64 |
| 2904 | { 1126, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_S_SAT_F32_S |
| 2905 | { 1125, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 455, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_S_SAT_F32 |
| 2906 | { 1124, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_S_F64_S |
| 2907 | { 1123, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 457, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_S_F64 |
| 2908 | { 1122, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_S_F32_S |
| 2909 | { 1121, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 455, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_S_F32 |
| 2910 | { 1120, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_SUB128_S |
| 2911 | { 1119, 6, 2, 0, 0, 0, 1, WebAssemblyOpInfoBase + 492, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_SUB128 |
| 2912 | { 1118, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_REINTERPRET_F64_S |
| 2913 | { 1117, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 457, 3, 0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_REINTERPRET_F64 |
| 2914 | { 1116, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_MUL_WIDE_U_S |
| 2915 | { 1115, 4, 2, 0, 0, 0, 1, WebAssemblyOpInfoBase + 500, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_MUL_WIDE_U |
| 2916 | { 1114, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_MUL_WIDE_S_S |
| 2917 | { 1113, 4, 2, 0, 0, 0, 1, WebAssemblyOpInfoBase + 500, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_MUL_WIDE_S |
| 2918 | { 1112, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_EXTEND_U_I32_S |
| 2919 | { 1111, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 498, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_EXTEND_U_I32 |
| 2920 | { 1110, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_EXTEND_S_I32_S |
| 2921 | { 1109, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 498, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_EXTEND_S_I32 |
| 2922 | { 1108, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_EXTEND8_S_I64_S |
| 2923 | { 1107, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 312, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_EXTEND8_S_I64 |
| 2924 | { 1106, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_EXTEND32_S_I64_S |
| 2925 | { 1105, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 312, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_EXTEND32_S_I64 |
| 2926 | { 1104, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_EXTEND16_S_I64_S |
| 2927 | { 1103, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 312, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_EXTEND16_S_I64 |
| 2928 | { 1102, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_ADD128_S |
| 2929 | { 1101, 6, 2, 0, 0, 0, 1, WebAssemblyOpInfoBase + 492, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_ADD128 |
| 2930 | { 1100, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_WRAP_I64_S |
| 2931 | { 1099, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 415, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_WRAP_I64 |
| 2932 | { 1098, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_U_SAT_F64_S |
| 2933 | { 1097, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 453, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_U_SAT_F64 |
| 2934 | { 1096, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_U_SAT_F32_S |
| 2935 | { 1095, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 451, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_U_SAT_F32 |
| 2936 | { 1094, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_U_F64_S |
| 2937 | { 1093, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 453, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_U_F64 |
| 2938 | { 1092, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_U_F32_S |
| 2939 | { 1091, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 451, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_U_F32 |
| 2940 | { 1090, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_S_SAT_F64_S |
| 2941 | { 1089, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 453, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_S_SAT_F64 |
| 2942 | { 1088, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_S_SAT_F32_S |
| 2943 | { 1087, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 451, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_S_SAT_F32 |
| 2944 | { 1086, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_S_F64_S |
| 2945 | { 1085, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 453, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_S_F64 |
| 2946 | { 1084, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_S_F32_S |
| 2947 | { 1083, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 451, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_S_F32 |
| 2948 | { 1082, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_REINTERPRET_F32_S |
| 2949 | { 1081, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 451, 3, 0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_REINTERPRET_F32 |
| 2950 | { 1080, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_EXTEND8_S_I32_S |
| 2951 | { 1079, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 310, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_EXTEND8_S_I32 |
| 2952 | { 1078, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_EXTEND16_S_I32_S |
| 2953 | { 1077, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 310, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_EXTEND16_S_I32 |
| 2954 | { 1076, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_U_I8x16_S |
| 2955 | { 1075, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_U_I8x16 |
| 2956 | { 1074, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_U_I64_S |
| 2957 | { 1073, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 423, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_U_I64 |
| 2958 | { 1072, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_U_I32x4_S |
| 2959 | { 1071, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_U_I32x4 |
| 2960 | { 1070, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_U_I32_S |
| 2961 | { 1069, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_U_I32 |
| 2962 | { 1068, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_U_I16x8_S |
| 2963 | { 1067, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_U_I16x8 |
| 2964 | { 1066, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_S_I8x16_S |
| 2965 | { 1065, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_S_I8x16 |
| 2966 | { 1064, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_S_I64x2_S |
| 2967 | { 1063, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_S_I64x2 |
| 2968 | { 1062, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_S_I64_S |
| 2969 | { 1061, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 423, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_S_I64 |
| 2970 | { 1060, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_S_I32x4_S |
| 2971 | { 1059, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_S_I32x4 |
| 2972 | { 1058, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_S_I32_S |
| 2973 | { 1057, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_S_I32 |
| 2974 | { 1056, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_S_I16x8_S |
| 2975 | { 1055, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_S_I16x8 |
| 2976 | { 1054, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_F64x2_S |
| 2977 | { 1053, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_F64x2 |
| 2978 | { 1052, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_F64_S |
| 2979 | { 1051, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 420, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_F64 |
| 2980 | { 1050, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_F32x4_S |
| 2981 | { 1049, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_F32x4 |
| 2982 | { 1048, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_F32_S |
| 2983 | { 1047, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 417, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_F32 |
| 2984 | { 1046, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_F16x8_S |
| 2985 | { 1045, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_F16x8 |
| 2986 | { 1044, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 461, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_V128_S |
| 2987 | { 1043, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 490, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_V128 |
| 2988 | { 1042, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 461, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_I64_S |
| 2989 | { 1041, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 488, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_I64 |
| 2990 | { 1040, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 461, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_I32_S |
| 2991 | { 1039, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 486, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_I32 |
| 2992 | { 1038, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 461, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_FUNCREF_S |
| 2993 | { 1037, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 484, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_FUNCREF |
| 2994 | { 1036, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 461, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_F64_S |
| 2995 | { 1035, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 482, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_F64 |
| 2996 | { 1034, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 461, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_F32_S |
| 2997 | { 1033, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 480, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_F32 |
| 2998 | { 1032, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 461, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_EXTERNREF_S |
| 2999 | { 1031, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 478, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_EXTERNREF |
| 3000 | { 1030, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 461, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_EXNREF_S |
| 3001 | { 1029, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 476, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_EXNREF |
| 3002 | { 1028, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 461, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_V128_S |
| 3003 | { 1027, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 474, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_V128 |
| 3004 | { 1026, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 461, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_I64_S |
| 3005 | { 1025, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 472, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_I64 |
| 3006 | { 1024, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 461, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_I32_S |
| 3007 | { 1023, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 470, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_I32 |
| 3008 | { 1022, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 461, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_FUNCREF_S |
| 3009 | { 1021, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 468, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_FUNCREF |
| 3010 | { 1020, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 461, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_F64_S |
| 3011 | { 1019, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 466, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_F64 |
| 3012 | { 1018, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 461, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_F32_S |
| 3013 | { 1017, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 464, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_F32 |
| 3014 | { 1016, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 461, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_EXTERNREF_S |
| 3015 | { 1015, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 462, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_EXTERNREF |
| 3016 | { 1014, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 461, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_EXNREF_S |
| 3017 | { 1013, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 459, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_EXNREF |
| 3018 | { 1012, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_U_I8x16_S |
| 3019 | { 1011, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_U_I8x16 |
| 3020 | { 1010, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_U_I64_S |
| 3021 | { 1009, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 423, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_U_I64 |
| 3022 | { 1008, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_U_I32x4_S |
| 3023 | { 1007, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_U_I32x4 |
| 3024 | { 1006, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_U_I32_S |
| 3025 | { 1005, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_U_I32 |
| 3026 | { 1004, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_U_I16x8_S |
| 3027 | { 1003, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_U_I16x8 |
| 3028 | { 1002, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_S_I8x16_S |
| 3029 | { 1001, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_S_I8x16 |
| 3030 | { 1000, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_S_I64x2_S |
| 3031 | { 999, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_S_I64x2 |
| 3032 | { 998, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_S_I64_S |
| 3033 | { 997, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 423, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_S_I64 |
| 3034 | { 996, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_S_I32x4_S |
| 3035 | { 995, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_S_I32x4 |
| 3036 | { 994, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_S_I32_S |
| 3037 | { 993, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_S_I32 |
| 3038 | { 992, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_S_I16x8_S |
| 3039 | { 991, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_S_I16x8 |
| 3040 | { 990, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_F64x2_S |
| 3041 | { 989, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_F64x2 |
| 3042 | { 988, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_F64_S |
| 3043 | { 987, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 420, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_F64 |
| 3044 | { 986, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_F32x4_S |
| 3045 | { 985, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_F32x4 |
| 3046 | { 984, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_F32_S |
| 3047 | { 983, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 417, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_F32 |
| 3048 | { 982, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_F16x8_S |
| 3049 | { 981, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_F16x8 |
| 3050 | { 980, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_UINT_I64_F64_S |
| 3051 | { 979, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 457, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_UINT_I64_F64 |
| 3052 | { 978, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_UINT_I64_F32_S |
| 3053 | { 977, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 455, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_UINT_I64_F32 |
| 3054 | { 976, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_UINT_I32_F64_S |
| 3055 | { 975, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 453, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_UINT_I32_F64 |
| 3056 | { 974, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_UINT_I32_F32_S |
| 3057 | { 973, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 451, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_UINT_I32_F32 |
| 3058 | { 972, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_SINT_I64_F64_S |
| 3059 | { 971, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 457, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_SINT_I64_F64 |
| 3060 | { 970, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_SINT_I64_F32_S |
| 3061 | { 969, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 455, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_SINT_I64_F32 |
| 3062 | { 968, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_SINT_I32_F64_S |
| 3063 | { 967, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 453, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_SINT_I32_F64 |
| 3064 | { 966, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_SINT_I32_F32_S |
| 3065 | { 965, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 451, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_SINT_I32_F32 |
| 3066 | { 964, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FLOOR_F64x2_S |
| 3067 | { 963, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FLOOR_F64x2 |
| 3068 | { 962, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FLOOR_F64_S |
| 3069 | { 961, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FLOOR_F64 |
| 3070 | { 960, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FLOOR_F32x4_S |
| 3071 | { 959, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FLOOR_F32x4 |
| 3072 | { 958, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FLOOR_F32_S |
| 3073 | { 957, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 157, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FLOOR_F32 |
| 3074 | { 956, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FLOOR_F16x8_S |
| 3075 | { 955, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FLOOR_F16x8 |
| 3076 | { 954, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FALLTHROUGH_RETURN_S |
| 3077 | { 953, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FALLTHROUGH_RETURN |
| 3078 | { 952, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F64_REINTERPRET_I64_S |
| 3079 | { 951, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 447, 3, 0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F64_REINTERPRET_I64 |
| 3080 | { 950, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F64_PROMOTE_F32_S |
| 3081 | { 949, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 449, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F64_PROMOTE_F32 |
| 3082 | { 948, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F64_CONVERT_U_I64_S |
| 3083 | { 947, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 447, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F64_CONVERT_U_I64 |
| 3084 | { 946, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F64_CONVERT_U_I32_S |
| 3085 | { 945, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 445, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F64_CONVERT_U_I32 |
| 3086 | { 944, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F64_CONVERT_S_I64_S |
| 3087 | { 943, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 447, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F64_CONVERT_S_I64 |
| 3088 | { 942, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F64_CONVERT_S_I32_S |
| 3089 | { 941, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 445, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F64_CONVERT_S_I32 |
| 3090 | { 940, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F32_REINTERPRET_I32_S |
| 3091 | { 939, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 439, 3, 0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F32_REINTERPRET_I32 |
| 3092 | { 938, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F32_DEMOTE_F64_S |
| 3093 | { 937, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 443, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F32_DEMOTE_F64 |
| 3094 | { 936, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F32_CONVERT_U_I64_S |
| 3095 | { 935, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 441, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F32_CONVERT_U_I64 |
| 3096 | { 934, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F32_CONVERT_U_I32_S |
| 3097 | { 933, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 439, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F32_CONVERT_U_I32 |
| 3098 | { 932, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F32_CONVERT_S_I64_S |
| 3099 | { 931, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 441, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F32_CONVERT_S_I64 |
| 3100 | { 930, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F32_CONVERT_S_I32_S |
| 3101 | { 929, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 439, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F32_CONVERT_S_I32 |
| 3102 | { 928, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 429, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_I8x16_u_S |
| 3103 | { 927, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 433, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_I8x16_u |
| 3104 | { 926, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 429, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_I8x16_s_S |
| 3105 | { 925, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 433, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_I8x16_s |
| 3106 | { 924, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 429, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_I64x2_S |
| 3107 | { 923, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 436, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_I64x2 |
| 3108 | { 922, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 429, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_I32x4_S |
| 3109 | { 921, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 433, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_I32x4 |
| 3110 | { 920, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 429, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_I16x8_u_S |
| 3111 | { 919, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 433, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_I16x8_u |
| 3112 | { 918, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 429, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_I16x8_s_S |
| 3113 | { 917, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 433, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_I16x8_s |
| 3114 | { 916, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 429, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_F64x2_S |
| 3115 | { 915, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 430, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_F64x2 |
| 3116 | { 914, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 429, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_F32x4_S |
| 3117 | { 913, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 426, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_F32x4 |
| 3118 | { 912, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 429, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_F16x8_S |
| 3119 | { 911, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 426, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_F16x8 |
| 3120 | { 910, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_LOW_U_I64x2_S |
| 3121 | { 909, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_LOW_U_I64x2 |
| 3122 | { 908, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_LOW_U_I32x4_S |
| 3123 | { 907, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_LOW_U_I32x4 |
| 3124 | { 906, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_LOW_U_I16x8_S |
| 3125 | { 905, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_LOW_U_I16x8 |
| 3126 | { 904, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_LOW_S_I64x2_S |
| 3127 | { 903, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_LOW_S_I64x2 |
| 3128 | { 902, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_LOW_S_I32x4_S |
| 3129 | { 901, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_LOW_S_I32x4 |
| 3130 | { 900, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_LOW_S_I16x8_S |
| 3131 | { 899, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_LOW_S_I16x8 |
| 3132 | { 898, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_HIGH_U_I64x2_S |
| 3133 | { 897, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_HIGH_U_I64x2 |
| 3134 | { 896, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_HIGH_U_I32x4_S |
| 3135 | { 895, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_HIGH_U_I32x4 |
| 3136 | { 894, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_HIGH_U_I16x8_S |
| 3137 | { 893, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_HIGH_U_I16x8 |
| 3138 | { 892, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_HIGH_S_I64x2_S |
| 3139 | { 891, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_HIGH_S_I64x2 |
| 3140 | { 890, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_HIGH_S_I32x4_S |
| 3141 | { 889, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_HIGH_S_I32x4 |
| 3142 | { 888, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_HIGH_S_I16x8_S |
| 3143 | { 887, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_HIGH_S_I16x8 |
| 3144 | { 886, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_I8x16_S |
| 3145 | { 885, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_I8x16 |
| 3146 | { 884, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_I64x2_S |
| 3147 | { 883, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_I64x2 |
| 3148 | { 882, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_I64_S |
| 3149 | { 881, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 423, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_I64 |
| 3150 | { 880, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_I32x4_S |
| 3151 | { 879, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_I32x4 |
| 3152 | { 878, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_I32_S |
| 3153 | { 877, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_I32 |
| 3154 | { 876, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_I16x8_S |
| 3155 | { 875, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_I16x8 |
| 3156 | { 874, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_F64x2_S |
| 3157 | { 873, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_F64x2 |
| 3158 | { 872, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_F64_S |
| 3159 | { 871, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 420, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_F64 |
| 3160 | { 870, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_F32x4_S |
| 3161 | { 869, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_F32x4 |
| 3162 | { 868, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_F32_S |
| 3163 | { 867, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 417, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_F32 |
| 3164 | { 866, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_F16x8_S |
| 3165 | { 865, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_F16x8 |
| 3166 | { 864, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQZ_I64_S |
| 3167 | { 863, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 415, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQZ_I64 |
| 3168 | { 862, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQZ_I32_S |
| 3169 | { 861, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 310, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQZ_I32 |
| 3170 | { 860, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_TRY_TABLE_S |
| 3171 | { 859, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_TRY_TABLE |
| 3172 | { 858, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_TRY_S |
| 3173 | { 857, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_TRY |
| 3174 | { 856, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_S |
| 3175 | { 855, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_LOOP_S |
| 3176 | { 854, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_LOOP |
| 3177 | { 853, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_IF_S |
| 3178 | { 852, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_IF |
| 3179 | { 851, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_FUNCTION_S |
| 3180 | { 850, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_FUNCTION |
| 3181 | { 849, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_BLOCK_S |
| 3182 | { 848, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_BLOCK |
| 3183 | { 847, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END |
| 3184 | { 846, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ELSE_S |
| 3185 | { 845, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ELSE |
| 3186 | { 844, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_V128_S |
| 3187 | { 843, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 414, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_V128 |
| 3188 | { 842, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_I64_S |
| 3189 | { 841, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 302, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_I64 |
| 3190 | { 840, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_I32_S |
| 3191 | { 839, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 300, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_I32 |
| 3192 | { 838, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_FUNCREF_S |
| 3193 | { 837, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 413, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_FUNCREF |
| 3194 | { 836, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_F64_S |
| 3195 | { 835, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 412, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_F64 |
| 3196 | { 834, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_F32_S |
| 3197 | { 833, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 411, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_F32 |
| 3198 | { 832, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_EXTERNREF_S |
| 3199 | { 831, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 410, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_EXTERNREF |
| 3200 | { 830, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_EXNREF_S |
| 3201 | { 829, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 309, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_EXNREF |
| 3202 | { 828, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DOT_S |
| 3203 | { 827, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DOT |
| 3204 | { 826, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_U_I64_S |
| 3205 | { 825, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_U_I64 |
| 3206 | { 824, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_U_I32_S |
| 3207 | { 823, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_U_I32 |
| 3208 | { 822, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_S_I64_S |
| 3209 | { 821, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_S_I64 |
| 3210 | { 820, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_S_I32_S |
| 3211 | { 819, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_S_I32 |
| 3212 | { 818, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_F64x2_S |
| 3213 | { 817, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_F64x2 |
| 3214 | { 816, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_F64_S |
| 3215 | { 815, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 167, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_F64 |
| 3216 | { 814, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_F32x4_S |
| 3217 | { 813, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_F32x4 |
| 3218 | { 812, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_F32_S |
| 3219 | { 811, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 164, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_F32 |
| 3220 | { 810, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_F16x8_S |
| 3221 | { 809, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_F16x8 |
| 3222 | { 808, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 154, 3, 0|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DELEGATE_S |
| 3223 | { 807, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 154, 3, 0|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DELEGATE |
| 3224 | { 806, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Trap)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DEBUG_UNREACHABLE_S |
| 3225 | { 805, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Trap)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DEBUG_UNREACHABLE |
| 3226 | { 804, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 322, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DATA_DROP_S |
| 3227 | { 803, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 322, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DATA_DROP |
| 3228 | { 802, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CTZ_I64_S |
| 3229 | { 801, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 312, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CTZ_I64 |
| 3230 | { 800, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CTZ_I32_S |
| 3231 | { 799, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 310, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CTZ_I32 |
| 3232 | { 798, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_V128_S |
| 3233 | { 797, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_V128 |
| 3234 | { 796, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_I64_S |
| 3235 | { 795, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 312, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_I64 |
| 3236 | { 794, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_I32_S |
| 3237 | { 793, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 310, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_I32 |
| 3238 | { 792, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_FUNCREF_S |
| 3239 | { 791, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 408, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_FUNCREF |
| 3240 | { 790, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_F64_S |
| 3241 | { 789, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_F64 |
| 3242 | { 788, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_F32_S |
| 3243 | { 787, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 157, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_F32 |
| 3244 | { 786, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_EXTERNREF_S |
| 3245 | { 785, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 406, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_EXTERNREF |
| 3246 | { 784, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_EXNREF_S |
| 3247 | { 783, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 404, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_EXNREF |
| 3248 | { 782, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPYSIGN_F64_S |
| 3249 | { 781, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 167, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPYSIGN_F64 |
| 3250 | { 780, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPYSIGN_F32_S |
| 3251 | { 779, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 164, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPYSIGN_F32 |
| 3252 | { 778, 16, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 388, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_V128_I8x16_S |
| 3253 | { 777, 17, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 371, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_V128_I8x16 |
| 3254 | { 776, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 369, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_V128_I64x2_S |
| 3255 | { 775, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 366, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_V128_I64x2 |
| 3256 | { 774, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 362, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_V128_I32x4_S |
| 3257 | { 773, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 357, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_V128_I32x4 |
| 3258 | { 772, 8, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 349, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_V128_I16x8_S |
| 3259 | { 771, 9, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 340, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_V128_I16x8 |
| 3260 | { 770, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 338, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_V128_F64x2_S |
| 3261 | { 769, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 335, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_V128_F64x2 |
| 3262 | { 768, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 331, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_V128_F32x4_S |
| 3263 | { 767, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 326, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_V128_F32x4 |
| 3264 | { 766, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 325, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_I64_S |
| 3265 | { 765, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 323, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_I64 |
| 3266 | { 764, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 322, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_I32_S |
| 3267 | { 763, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 320, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_I32 |
| 3268 | { 762, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 319, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_F64_S |
| 3269 | { 761, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 317, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_F64 |
| 3270 | { 760, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 316, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_F32_S |
| 3271 | { 759, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 314, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_F32 |
| 3272 | { 758, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLZ_I64_S |
| 3273 | { 757, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 312, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLZ_I64 |
| 3274 | { 756, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLZ_I32_S |
| 3275 | { 755, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 310, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLZ_I32 |
| 3276 | { 754, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CEIL_F64x2_S |
| 3277 | { 753, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CEIL_F64x2 |
| 3278 | { 752, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CEIL_F64_S |
| 3279 | { 751, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CEIL_F64 |
| 3280 | { 750, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CEIL_F32x4_S |
| 3281 | { 749, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CEIL_F32x4 |
| 3282 | { 748, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CEIL_F32_S |
| 3283 | { 747, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 157, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CEIL_F32 |
| 3284 | { 746, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CEIL_F16x8_S |
| 3285 | { 745, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CEIL_F16x8 |
| 3286 | { 744, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 308, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CATCH_S |
| 3287 | { 743, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 308, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CATCH_REF_S |
| 3288 | { 742, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 308, 3, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CATCH_REF |
| 3289 | { 741, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 308, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CATCH_LEGACY_S |
| 3290 | { 740, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 308, 3, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CATCH_LEGACY |
| 3291 | { 739, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CATCH_ALL_S |
| 3292 | { 738, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CATCH_ALL_REF_S |
| 3293 | { 737, 1, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 309, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CATCH_ALL_REF |
| 3294 | { 736, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CATCH_ALL_LEGACY_S |
| 3295 | { 735, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CATCH_ALL_LEGACY |
| 3296 | { 734, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CATCH_ALL |
| 3297 | { 733, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 308, 3, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CATCH |
| 3298 | { 732, 1, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 151, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CALL_S |
| 3299 | { 731, 1, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 307, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CALL_REF_S |
| 3300 | { 730, 2, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 305, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CALL_REF |
| 3301 | { 729, 2, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 303, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CALL_INDIRECT_S |
| 3302 | { 728, 2, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 303, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CALL_INDIRECT |
| 3303 | { 727, 1, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 151, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CALL |
| 3304 | { 726, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 154, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BR_UNLESS_S |
| 3305 | { 725, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 298, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BR_UNLESS |
| 3306 | { 724, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 301, 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BR_TABLE_I64_S |
| 3307 | { 723, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 302, 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BR_TABLE_I64 |
| 3308 | { 722, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 301, 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BR_TABLE_I32_S |
| 3309 | { 721, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 300, 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BR_TABLE_I32 |
| 3310 | { 720, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 154, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BR_S |
| 3311 | { 719, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 154, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BR_IF_S |
| 3312 | { 718, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 298, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BR_IF |
| 3313 | { 717, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 154, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BR |
| 3314 | { 716, 1, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 297, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLOCK_S |
| 3315 | { 715, 1, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 297, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLOCK |
| 3316 | { 714, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BITSELECT_S |
| 3317 | { 713, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 293, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BITSELECT |
| 3318 | { 712, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BITMASK_I8x16_S |
| 3319 | { 711, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 176, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BITMASK_I8x16 |
| 3320 | { 710, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BITMASK_I64x2_S |
| 3321 | { 709, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 176, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BITMASK_I64x2 |
| 3322 | { 708, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BITMASK_I32x4_S |
| 3323 | { 707, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 176, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BITMASK_I32x4 |
| 3324 | { 706, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BITMASK_I16x8_S |
| 3325 | { 705, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 176, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BITMASK_I16x8 |
| 3326 | { 704, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AVGR_U_I8x16_S |
| 3327 | { 703, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AVGR_U_I8x16 |
| 3328 | { 702, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AVGR_U_I16x8_S |
| 3329 | { 701, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AVGR_U_I16x8 |
| 3330 | { 700, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE_I64_A64_S |
| 3331 | { 699, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 288, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE_I64_A64 |
| 3332 | { 698, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE_I64_A32_S |
| 3333 | { 697, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 283, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE_I64_A32 |
| 3334 | { 696, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE_I32_A64_S |
| 3335 | { 695, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 278, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE_I32_A64 |
| 3336 | { 694, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE_I32_A32_S |
| 3337 | { 693, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 273, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE_I32_A32 |
| 3338 | { 692, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE8_I64_A64_S |
| 3339 | { 691, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 288, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE8_I64_A64 |
| 3340 | { 690, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE8_I64_A32_S |
| 3341 | { 689, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 283, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE8_I64_A32 |
| 3342 | { 688, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE8_I32_A64_S |
| 3343 | { 687, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 278, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE8_I32_A64 |
| 3344 | { 686, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE8_I32_A32_S |
| 3345 | { 685, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 273, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE8_I32_A32 |
| 3346 | { 684, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE32_I64_A64_S |
| 3347 | { 683, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 288, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE32_I64_A64 |
| 3348 | { 682, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE32_I64_A32_S |
| 3349 | { 681, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 283, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE32_I64_A32 |
| 3350 | { 680, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE16_I64_A64_S |
| 3351 | { 679, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 288, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE16_I64_A64 |
| 3352 | { 678, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE16_I64_A32_S |
| 3353 | { 677, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 283, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE16_I64_A32 |
| 3354 | { 676, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE16_I32_A64_S |
| 3355 | { 675, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 278, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE16_I32_A64 |
| 3356 | { 674, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE16_I32_A32_S |
| 3357 | { 673, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 273, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE16_I32_A32 |
| 3358 | { 672, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XOR_I64_A64_S |
| 3359 | { 671, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XOR_I64_A64 |
| 3360 | { 670, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XOR_I64_A32_S |
| 3361 | { 669, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XOR_I64_A32 |
| 3362 | { 668, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XOR_I32_A64_S |
| 3363 | { 667, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XOR_I32_A64 |
| 3364 | { 666, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XOR_I32_A32_S |
| 3365 | { 665, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XOR_I32_A32 |
| 3366 | { 664, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XCHG_I64_A64_S |
| 3367 | { 663, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XCHG_I64_A64 |
| 3368 | { 662, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XCHG_I64_A32_S |
| 3369 | { 661, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XCHG_I64_A32 |
| 3370 | { 660, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XCHG_I32_A64_S |
| 3371 | { 659, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XCHG_I32_A64 |
| 3372 | { 658, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XCHG_I32_A32_S |
| 3373 | { 657, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XCHG_I32_A32 |
| 3374 | { 656, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_SUB_I64_A64_S |
| 3375 | { 655, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_SUB_I64_A64 |
| 3376 | { 654, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_SUB_I64_A32_S |
| 3377 | { 653, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_SUB_I64_A32 |
| 3378 | { 652, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_SUB_I32_A64_S |
| 3379 | { 651, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_SUB_I32_A64 |
| 3380 | { 650, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_SUB_I32_A32_S |
| 3381 | { 649, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_SUB_I32_A32 |
| 3382 | { 648, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_OR_I64_A64_S |
| 3383 | { 647, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_OR_I64_A64 |
| 3384 | { 646, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_OR_I64_A32_S |
| 3385 | { 645, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_OR_I64_A32 |
| 3386 | { 644, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_OR_I32_A64_S |
| 3387 | { 643, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_OR_I32_A64 |
| 3388 | { 642, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_OR_I32_A32_S |
| 3389 | { 641, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_OR_I32_A32 |
| 3390 | { 640, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_CMPXCHG_I64_A64_S |
| 3391 | { 639, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 266, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_CMPXCHG_I64_A64 |
| 3392 | { 638, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_CMPXCHG_I64_A32_S |
| 3393 | { 637, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 259, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_CMPXCHG_I64_A32 |
| 3394 | { 636, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_CMPXCHG_I32_A64_S |
| 3395 | { 635, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 252, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_CMPXCHG_I32_A64 |
| 3396 | { 634, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_CMPXCHG_I32_A32_S |
| 3397 | { 633, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 245, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_CMPXCHG_I32_A32 |
| 3398 | { 632, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_AND_I64_A64_S |
| 3399 | { 631, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_AND_I64_A64 |
| 3400 | { 630, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_AND_I64_A32_S |
| 3401 | { 629, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_AND_I64_A32 |
| 3402 | { 628, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_AND_I32_A64_S |
| 3403 | { 627, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_AND_I32_A64 |
| 3404 | { 626, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_AND_I32_A32_S |
| 3405 | { 625, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_AND_I32_A32 |
| 3406 | { 624, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_ADD_I64_A64_S |
| 3407 | { 623, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_ADD_I64_A64 |
| 3408 | { 622, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_ADD_I64_A32_S |
| 3409 | { 621, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_ADD_I64_A32 |
| 3410 | { 620, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_ADD_I32_A64_S |
| 3411 | { 619, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_ADD_I32_A64 |
| 3412 | { 618, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_ADD_I32_A32_S |
| 3413 | { 617, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_ADD_I32_A32 |
| 3414 | { 616, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XOR_I64_A64_S |
| 3415 | { 615, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XOR_I64_A64 |
| 3416 | { 614, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XOR_I64_A32_S |
| 3417 | { 613, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XOR_I64_A32 |
| 3418 | { 612, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XOR_I32_A64_S |
| 3419 | { 611, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XOR_I32_A64 |
| 3420 | { 610, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XOR_I32_A32_S |
| 3421 | { 609, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XOR_I32_A32 |
| 3422 | { 608, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XCHG_I64_A64_S |
| 3423 | { 607, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XCHG_I64_A64 |
| 3424 | { 606, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XCHG_I64_A32_S |
| 3425 | { 605, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XCHG_I64_A32 |
| 3426 | { 604, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XCHG_I32_A64_S |
| 3427 | { 603, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XCHG_I32_A64 |
| 3428 | { 602, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XCHG_I32_A32_S |
| 3429 | { 601, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XCHG_I32_A32 |
| 3430 | { 600, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_SUB_I64_A64_S |
| 3431 | { 599, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_SUB_I64_A64 |
| 3432 | { 598, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_SUB_I64_A32_S |
| 3433 | { 597, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_SUB_I64_A32 |
| 3434 | { 596, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_SUB_I32_A64_S |
| 3435 | { 595, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_SUB_I32_A64 |
| 3436 | { 594, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_SUB_I32_A32_S |
| 3437 | { 593, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_SUB_I32_A32 |
| 3438 | { 592, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_OR_I64_A64_S |
| 3439 | { 591, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_OR_I64_A64 |
| 3440 | { 590, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_OR_I64_A32_S |
| 3441 | { 589, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_OR_I64_A32 |
| 3442 | { 588, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_OR_I32_A64_S |
| 3443 | { 587, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_OR_I32_A64 |
| 3444 | { 586, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_OR_I32_A32_S |
| 3445 | { 585, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_OR_I32_A32 |
| 3446 | { 584, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_CMPXCHG_I64_A64_S |
| 3447 | { 583, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 266, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_CMPXCHG_I64_A64 |
| 3448 | { 582, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_CMPXCHG_I64_A32_S |
| 3449 | { 581, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 259, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_CMPXCHG_I64_A32 |
| 3450 | { 580, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_CMPXCHG_I32_A64_S |
| 3451 | { 579, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 252, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_CMPXCHG_I32_A64 |
| 3452 | { 578, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_CMPXCHG_I32_A32_S |
| 3453 | { 577, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 245, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_CMPXCHG_I32_A32 |
| 3454 | { 576, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_AND_I64_A64_S |
| 3455 | { 575, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_AND_I64_A64 |
| 3456 | { 574, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_AND_I64_A32_S |
| 3457 | { 573, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_AND_I64_A32 |
| 3458 | { 572, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_AND_I32_A64_S |
| 3459 | { 571, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_AND_I32_A64 |
| 3460 | { 570, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_AND_I32_A32_S |
| 3461 | { 569, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_AND_I32_A32 |
| 3462 | { 568, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_ADD_I64_A64_S |
| 3463 | { 567, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_ADD_I64_A64 |
| 3464 | { 566, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_ADD_I64_A32_S |
| 3465 | { 565, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_ADD_I64_A32 |
| 3466 | { 564, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_ADD_I32_A64_S |
| 3467 | { 563, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_ADD_I32_A64 |
| 3468 | { 562, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_ADD_I32_A32_S |
| 3469 | { 561, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_ADD_I32_A32 |
| 3470 | { 560, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_XOR_I64_A64_S |
| 3471 | { 559, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_XOR_I64_A64 |
| 3472 | { 558, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_XOR_I64_A32_S |
| 3473 | { 557, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_XOR_I64_A32 |
| 3474 | { 556, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_XCHG_I64_A64_S |
| 3475 | { 555, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_XCHG_I64_A64 |
| 3476 | { 554, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_XCHG_I64_A32_S |
| 3477 | { 553, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_XCHG_I64_A32 |
| 3478 | { 552, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_SUB_I64_A64_S |
| 3479 | { 551, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_SUB_I64_A64 |
| 3480 | { 550, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_SUB_I64_A32_S |
| 3481 | { 549, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_SUB_I64_A32 |
| 3482 | { 548, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_OR_I64_A64_S |
| 3483 | { 547, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_OR_I64_A64 |
| 3484 | { 546, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_OR_I64_A32_S |
| 3485 | { 545, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_OR_I64_A32 |
| 3486 | { 544, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_CMPXCHG_I64_A64_S |
| 3487 | { 543, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 266, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_CMPXCHG_I64_A64 |
| 3488 | { 542, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_CMPXCHG_I64_A32_S |
| 3489 | { 541, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 259, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_CMPXCHG_I64_A32 |
| 3490 | { 540, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_AND_I64_A64_S |
| 3491 | { 539, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_AND_I64_A64 |
| 3492 | { 538, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_AND_I64_A32_S |
| 3493 | { 537, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_AND_I64_A32 |
| 3494 | { 536, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_ADD_I64_A64_S |
| 3495 | { 535, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_ADD_I64_A64 |
| 3496 | { 534, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_ADD_I64_A32_S |
| 3497 | { 533, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_ADD_I64_A32 |
| 3498 | { 532, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XOR_I64_A64_S |
| 3499 | { 531, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XOR_I64_A64 |
| 3500 | { 530, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XOR_I64_A32_S |
| 3501 | { 529, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XOR_I64_A32 |
| 3502 | { 528, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XOR_I32_A64_S |
| 3503 | { 527, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XOR_I32_A64 |
| 3504 | { 526, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XOR_I32_A32_S |
| 3505 | { 525, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XOR_I32_A32 |
| 3506 | { 524, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XCHG_I64_A64_S |
| 3507 | { 523, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XCHG_I64_A64 |
| 3508 | { 522, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XCHG_I64_A32_S |
| 3509 | { 521, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XCHG_I64_A32 |
| 3510 | { 520, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XCHG_I32_A64_S |
| 3511 | { 519, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XCHG_I32_A64 |
| 3512 | { 518, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XCHG_I32_A32_S |
| 3513 | { 517, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XCHG_I32_A32 |
| 3514 | { 516, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_SUB_I64_A64_S |
| 3515 | { 515, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_SUB_I64_A64 |
| 3516 | { 514, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_SUB_I64_A32_S |
| 3517 | { 513, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_SUB_I64_A32 |
| 3518 | { 512, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_SUB_I32_A64_S |
| 3519 | { 511, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_SUB_I32_A64 |
| 3520 | { 510, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_SUB_I32_A32_S |
| 3521 | { 509, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_SUB_I32_A32 |
| 3522 | { 508, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_OR_I64_A64_S |
| 3523 | { 507, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_OR_I64_A64 |
| 3524 | { 506, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_OR_I64_A32_S |
| 3525 | { 505, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_OR_I64_A32 |
| 3526 | { 504, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_OR_I32_A64_S |
| 3527 | { 503, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_OR_I32_A64 |
| 3528 | { 502, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_OR_I32_A32_S |
| 3529 | { 501, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_OR_I32_A32 |
| 3530 | { 500, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_CMPXCHG_I64_A64_S |
| 3531 | { 499, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 266, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_CMPXCHG_I64_A64 |
| 3532 | { 498, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_CMPXCHG_I64_A32_S |
| 3533 | { 497, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 259, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_CMPXCHG_I64_A32 |
| 3534 | { 496, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_CMPXCHG_I32_A64_S |
| 3535 | { 495, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 252, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_CMPXCHG_I32_A64 |
| 3536 | { 494, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_CMPXCHG_I32_A32_S |
| 3537 | { 493, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 245, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_CMPXCHG_I32_A32 |
| 3538 | { 492, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_AND_I64_A64_S |
| 3539 | { 491, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_AND_I64_A64 |
| 3540 | { 490, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_AND_I64_A32_S |
| 3541 | { 489, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_AND_I64_A32 |
| 3542 | { 488, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_AND_I32_A64_S |
| 3543 | { 487, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_AND_I32_A64 |
| 3544 | { 486, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_AND_I32_A32_S |
| 3545 | { 485, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_AND_I32_A32 |
| 3546 | { 484, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_ADD_I64_A64_S |
| 3547 | { 483, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_ADD_I64_A64 |
| 3548 | { 482, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_ADD_I64_A32_S |
| 3549 | { 481, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_ADD_I64_A32 |
| 3550 | { 480, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_ADD_I32_A64_S |
| 3551 | { 479, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_ADD_I32_A64 |
| 3552 | { 478, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_ADD_I32_A32_S |
| 3553 | { 477, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_ADD_I32_A32 |
| 3554 | { 476, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD_I64_A64_S |
| 3555 | { 475, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 216, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD_I64_A64 |
| 3556 | { 474, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD_I64_A32_S |
| 3557 | { 473, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 211, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD_I64_A32 |
| 3558 | { 472, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD_I32_A64_S |
| 3559 | { 471, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 203, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD_I32_A64 |
| 3560 | { 470, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD_I32_A32_S |
| 3561 | { 469, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 195, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD_I32_A32 |
| 3562 | { 468, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD8_U_I64_A64_S |
| 3563 | { 467, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 216, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD8_U_I64_A64 |
| 3564 | { 466, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD8_U_I64_A32_S |
| 3565 | { 465, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 211, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD8_U_I64_A32 |
| 3566 | { 464, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD8_U_I32_A64_S |
| 3567 | { 463, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 203, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD8_U_I32_A64 |
| 3568 | { 462, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD8_U_I32_A32_S |
| 3569 | { 461, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 195, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD8_U_I32_A32 |
| 3570 | { 460, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD32_U_I64_A64_S |
| 3571 | { 459, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 216, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD32_U_I64_A64 |
| 3572 | { 458, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD32_U_I64_A32_S |
| 3573 | { 457, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 211, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD32_U_I64_A32 |
| 3574 | { 456, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD16_U_I64_A64_S |
| 3575 | { 455, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 216, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD16_U_I64_A64 |
| 3576 | { 454, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD16_U_I64_A32_S |
| 3577 | { 453, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 211, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD16_U_I64_A32 |
| 3578 | { 452, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD16_U_I32_A64_S |
| 3579 | { 451, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 203, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD16_U_I32_A64 |
| 3580 | { 450, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD16_U_I32_A32_S |
| 3581 | { 449, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 195, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD16_U_I32_A32 |
| 3582 | { 448, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 194, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_FENCE_S |
| 3583 | { 447, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 194, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_FENCE |
| 3584 | { 446, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v8i16_S |
| 3585 | { 445, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 192, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v8i16 |
| 3586 | { 444, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v8f16_S |
| 3587 | { 443, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 192, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v8f16 |
| 3588 | { 442, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v4i32_S |
| 3589 | { 441, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 192, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v4i32 |
| 3590 | { 440, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v4f32_S |
| 3591 | { 439, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 192, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v4f32 |
| 3592 | { 438, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v2i64_S |
| 3593 | { 437, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 192, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v2i64 |
| 3594 | { 436, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v2f64_S |
| 3595 | { 435, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 192, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v2f64 |
| 3596 | { 434, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v16i8_S |
| 3597 | { 433, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 192, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v16i8 |
| 3598 | { 432, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_i64_S |
| 3599 | { 431, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 190, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_i64 |
| 3600 | { 430, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_i32_S |
| 3601 | { 429, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 188, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_i32 |
| 3602 | { 428, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_funcref_S |
| 3603 | { 427, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 186, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_funcref |
| 3604 | { 426, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_f64_S |
| 3605 | { 425, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 184, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_f64 |
| 3606 | { 424, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_f32_S |
| 3607 | { 423, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 182, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_f32 |
| 3608 | { 422, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_externref_S |
| 3609 | { 421, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 180, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_externref |
| 3610 | { 420, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_exnref_S |
| 3611 | { 419, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 178, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_exnref |
| 3612 | { 418, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANYTRUE_S |
| 3613 | { 417, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 176, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANYTRUE |
| 3614 | { 416, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_S |
| 3615 | { 415, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_I64_S |
| 3616 | { 414, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_I64 |
| 3617 | { 413, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_I32_S |
| 3618 | { 412, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_I32 |
| 3619 | { 411, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANDNOT_S |
| 3620 | { 410, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANDNOT |
| 3621 | { 409, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND |
| 3622 | { 408, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ALLTRUE_I8x16_S |
| 3623 | { 407, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 176, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ALLTRUE_I8x16 |
| 3624 | { 406, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ALLTRUE_I64x2_S |
| 3625 | { 405, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 176, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ALLTRUE_I64x2 |
| 3626 | { 404, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ALLTRUE_I32x4_S |
| 3627 | { 403, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 176, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ALLTRUE_I32x4 |
| 3628 | { 402, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ALLTRUE_I16x8_S |
| 3629 | { 401, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 176, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ALLTRUE_I16x8 |
| 3630 | { 400, 2, 0, 0, 0, 2, 2, WebAssemblyOpInfoBase + 20, 4, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKUP_S |
| 3631 | { 399, 2, 0, 0, 0, 2, 2, WebAssemblyOpInfoBase + 20, 4, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKUP |
| 3632 | { 398, 2, 0, 0, 0, 2, 2, WebAssemblyOpInfoBase + 20, 4, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKDOWN_S |
| 3633 | { 397, 2, 0, 0, 0, 2, 2, WebAssemblyOpInfoBase + 20, 4, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKDOWN |
| 3634 | { 396, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_SAT_U_I8x16_S |
| 3635 | { 395, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_SAT_U_I8x16 |
| 3636 | { 394, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_SAT_U_I16x8_S |
| 3637 | { 393, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_SAT_U_I16x8 |
| 3638 | { 392, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_SAT_S_I8x16_S |
| 3639 | { 391, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_SAT_S_I8x16 |
| 3640 | { 390, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_SAT_S_I16x8_S |
| 3641 | { 389, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_SAT_S_I16x8 |
| 3642 | { 388, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I8x16_S |
| 3643 | { 387, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I8x16 |
| 3644 | { 386, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I64x2_S |
| 3645 | { 385, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I64x2 |
| 3646 | { 384, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I64_S |
| 3647 | { 383, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I64 |
| 3648 | { 382, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I32x4_S |
| 3649 | { 381, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I32x4 |
| 3650 | { 380, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I32_S |
| 3651 | { 379, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I32 |
| 3652 | { 378, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I16x8_S |
| 3653 | { 377, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I16x8 |
| 3654 | { 376, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F64x2_S |
| 3655 | { 375, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F64x2 |
| 3656 | { 374, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F64_S |
| 3657 | { 373, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 167, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F64 |
| 3658 | { 372, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F32x4_S |
| 3659 | { 371, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F32x4 |
| 3660 | { 370, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F32_S |
| 3661 | { 369, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 164, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F32 |
| 3662 | { 368, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F16x8_S |
| 3663 | { 367, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F16x8 |
| 3664 | { 366, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_I8x16_S |
| 3665 | { 365, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_I8x16 |
| 3666 | { 364, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_I64x2_S |
| 3667 | { 363, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_I64x2 |
| 3668 | { 362, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_I32x4_S |
| 3669 | { 361, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_I32x4 |
| 3670 | { 360, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_I16x8_S |
| 3671 | { 359, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_I16x8 |
| 3672 | { 358, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_F64x2_S |
| 3673 | { 357, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_F64x2 |
| 3674 | { 356, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_F64_S |
| 3675 | { 355, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_F64 |
| 3676 | { 354, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_F32x4_S |
| 3677 | { 353, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_F32x4 |
| 3678 | { 352, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_F32_S |
| 3679 | { 351, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 157, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_F32 |
| 3680 | { 350, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_F16x8_S |
| 3681 | { 349, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_F16x8 |
| 3682 | { 348, 0, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // RET_CALL_RESULTS_S |
| 3683 | { 347, 0, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // RET_CALL_RESULTS |
| 3684 | { 346, 1, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 151, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RET_CALL_PARAMS_S |
| 3685 | { 345, 1, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 151, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RET_CALL_PARAMS |
| 3686 | { 344, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COMPILER_FENCE_S |
| 3687 | { 343, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COMPILER_FENCE |
| 3688 | { 342, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 154, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLEANUPRET_S |
| 3689 | { 341, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 154, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLEANUPRET |
| 3690 | { 340, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 152, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CATCHRET_S |
| 3691 | { 339, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 152, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CATCHRET |
| 3692 | { 338, 0, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CALL_RESULTS_S |
| 3693 | { 337, 0, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CALL_RESULTS |
| 3694 | { 336, 1, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 151, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CALL_PARAMS_S |
| 3695 | { 335, 1, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 151, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CALL_PARAMS |
| 3696 | { 334, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBFX |
| 3697 | { 333, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SBFX |
| 3698 | { 332, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMIN |
| 3699 | { 331, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMAX |
| 3700 | { 330, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMIN |
| 3701 | { 329, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMAX |
| 3702 | { 328, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_XOR |
| 3703 | { 327, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_OR |
| 3704 | { 326, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_AND |
| 3705 | { 325, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_MUL |
| 3706 | { 324, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_ADD |
| 3707 | { 323, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMINIMUMNUM |
| 3708 | { 322, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAXIMUMNUM |
| 3709 | { 321, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMINIMUM |
| 3710 | { 320, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAXIMUM |
| 3711 | { 319, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMIN |
| 3712 | { 318, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAX |
| 3713 | { 317, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMUL |
| 3714 | { 316, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FADD |
| 3715 | { 315, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FMUL |
| 3716 | { 314, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FADD |
| 3717 | { 313, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBSANTRAP |
| 3718 | { 312, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DEBUGTRAP |
| 3719 | { 311, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRAP |
| 3720 | { 310, 3, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET_INLINE |
| 3721 | { 309, 3, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BZERO |
| 3722 | { 308, 4, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET |
| 3723 | { 307, 4, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMMOVE |
| 3724 | { 306, 3, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY_INLINE |
| 3725 | { 305, 4, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY |
| 3726 | { 304, 2, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 141, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_WRITE_REGISTER |
| 3727 | { 303, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_READ_REGISTER |
| 3728 | { 302, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FCMPS |
| 3729 | { 301, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FCMP |
| 3730 | { 300, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FLDEXP |
| 3731 | { 299, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSQRT |
| 3732 | { 298, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMA |
| 3733 | { 297, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FREM |
| 3734 | { 296, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FDIV |
| 3735 | { 295, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMUL |
| 3736 | { 294, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSUB |
| 3737 | { 293, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FADD |
| 3738 | { 292, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKRESTORE |
| 3739 | { 291, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKSAVE |
| 3740 | { 290, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DYN_STACKALLOC |
| 3741 | { 289, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_JUMP_TABLE |
| 3742 | { 288, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BLOCK_ADDR |
| 3743 | { 287, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADDRSPACE_CAST |
| 3744 | { 286, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEARBYINT |
| 3745 | { 285, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRINT |
| 3746 | { 284, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFLOOR |
| 3747 | { 283, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSQRT |
| 3748 | { 282, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTANH |
| 3749 | { 281, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINH |
| 3750 | { 280, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOSH |
| 3751 | { 279, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN2 |
| 3752 | { 278, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN |
| 3753 | { 277, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FASIN |
| 3754 | { 276, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FACOS |
| 3755 | { 275, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTAN |
| 3756 | { 274, 3, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINCOS |
| 3757 | { 273, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSIN |
| 3758 | { 272, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOS |
| 3759 | { 271, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCEIL |
| 3760 | { 270, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CLMULR |
| 3761 | { 269, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CLMULH |
| 3762 | { 268, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CLMUL |
| 3763 | { 267, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITREVERSE |
| 3764 | { 266, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BSWAP |
| 3765 | { 265, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTPOP |
| 3766 | { 264, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLS |
| 3767 | { 263, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ_ZERO_POISON |
| 3768 | { 262, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ |
| 3769 | { 261, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ_ZERO_POISON |
| 3770 | { 260, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ |
| 3771 | { 259, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 137, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECTOR_COMPRESS |
| 3772 | { 258, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STEP_VECTOR |
| 3773 | { 257, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SPLAT_VECTOR |
| 3774 | { 256, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 133, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHUFFLE_VECTOR |
| 3775 | { 255, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_VECTOR_ELT |
| 3776 | { 254, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 126, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_VECTOR_ELT |
| 3777 | { 253, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_SUBVECTOR |
| 3778 | { 252, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_SUBVECTOR |
| 3779 | { 251, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VSCALE |
| 3780 | { 250, 3, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRJT |
| 3781 | { 249, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BR |
| 3782 | { 248, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LLROUND |
| 3783 | { 247, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LROUND |
| 3784 | { 246, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABS |
| 3785 | { 245, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMAX |
| 3786 | { 244, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMIN |
| 3787 | { 243, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMAX |
| 3788 | { 242, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMIN |
| 3789 | { 241, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRMASK |
| 3790 | { 240, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTR_ADD |
| 3791 | { 239, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_ROUNDING |
| 3792 | { 238, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_ROUNDING |
| 3793 | { 237, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPMODE |
| 3794 | { 236, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPMODE |
| 3795 | { 235, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPMODE |
| 3796 | { 234, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPENV |
| 3797 | { 233, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPENV |
| 3798 | { 232, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPENV |
| 3799 | { 231, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUMNUM |
| 3800 | { 230, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUMNUM |
| 3801 | { 229, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUM |
| 3802 | { 228, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUM |
| 3803 | { 227, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM_IEEE |
| 3804 | { 226, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM_IEEE |
| 3805 | { 225, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM |
| 3806 | { 224, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM |
| 3807 | { 223, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCANONICALIZE |
| 3808 | { 222, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IS_FPCLASS |
| 3809 | { 221, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOPYSIGN |
| 3810 | { 220, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FABS |
| 3811 | { 219, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI_SAT |
| 3812 | { 218, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI_SAT |
| 3813 | { 217, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UITOFP |
| 3814 | { 216, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SITOFP |
| 3815 | { 215, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI |
| 3816 | { 214, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI |
| 3817 | { 213, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNC |
| 3818 | { 212, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXT |
| 3819 | { 211, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEG |
| 3820 | { 210, 3, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFREXP |
| 3821 | { 209, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLDEXP |
| 3822 | { 208, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG10 |
| 3823 | { 207, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG2 |
| 3824 | { 206, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG |
| 3825 | { 205, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP10 |
| 3826 | { 204, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP2 |
| 3827 | { 203, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP |
| 3828 | { 202, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOWI |
| 3829 | { 201, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOW |
| 3830 | { 200, 3, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMODF |
| 3831 | { 199, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREM |
| 3832 | { 198, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FDIV |
| 3833 | { 197, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAD |
| 3834 | { 196, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMA |
| 3835 | { 195, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMUL |
| 3836 | { 194, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSUB |
| 3837 | { 193, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FADD |
| 3838 | { 192, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIXSAT |
| 3839 | { 191, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIXSAT |
| 3840 | { 190, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIX |
| 3841 | { 189, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIX |
| 3842 | { 188, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIXSAT |
| 3843 | { 187, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIXSAT |
| 3844 | { 186, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIX |
| 3845 | { 185, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIX |
| 3846 | { 184, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSHLSAT |
| 3847 | { 183, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USHLSAT |
| 3848 | { 182, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBSAT |
| 3849 | { 181, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBSAT |
| 3850 | { 180, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDSAT |
| 3851 | { 179, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDSAT |
| 3852 | { 178, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULH |
| 3853 | { 177, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULH |
| 3854 | { 176, 4, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULO |
| 3855 | { 175, 4, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULO |
| 3856 | { 174, 5, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBE |
| 3857 | { 173, 4, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBO |
| 3858 | { 172, 5, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDE |
| 3859 | { 171, 4, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDO |
| 3860 | { 170, 5, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBE |
| 3861 | { 169, 4, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBO |
| 3862 | { 168, 5, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDE |
| 3863 | { 167, 4, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDO |
| 3864 | { 166, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SELECT |
| 3865 | { 165, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UCMP |
| 3866 | { 164, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SCMP |
| 3867 | { 163, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCMP |
| 3868 | { 162, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ICMP |
| 3869 | { 161, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTL |
| 3870 | { 160, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTR |
| 3871 | { 159, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHR |
| 3872 | { 158, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHL |
| 3873 | { 157, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASHR |
| 3874 | { 156, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LSHR |
| 3875 | { 155, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHL |
| 3876 | { 154, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXT |
| 3877 | { 153, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT_INREG |
| 3878 | { 152, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT |
| 3879 | { 151, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VAARG |
| 3880 | { 150, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VASTART |
| 3881 | { 149, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCONSTANT |
| 3882 | { 148, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT |
| 3883 | { 147, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_USAT_U |
| 3884 | { 146, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_U |
| 3885 | { 145, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_S |
| 3886 | { 144, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC |
| 3887 | { 143, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ANYEXT |
| 3888 | { 142, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS |
| 3889 | { 141, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT |
| 3890 | { 140, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_W_SIDE_EFFECTS |
| 3891 | { 139, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC |
| 3892 | { 138, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INVOKE_REGION_START |
| 3893 | { 137, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRINDIRECT |
| 3894 | { 136, 2, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRCOND |
| 3895 | { 135, 4, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 93, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PREFETCH |
| 3896 | { 134, 2, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 20, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FENCE |
| 3897 | { 133, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_SAT |
| 3898 | { 132, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_COND |
| 3899 | { 131, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UDEC_WRAP |
| 3900 | { 130, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UINC_WRAP |
| 3901 | { 129, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUMNUM |
| 3902 | { 128, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUMNUM |
| 3903 | { 127, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUM |
| 3904 | { 126, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUM |
| 3905 | { 125, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMIN |
| 3906 | { 124, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAX |
| 3907 | { 123, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FSUB |
| 3908 | { 122, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FADD |
| 3909 | { 121, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMIN |
| 3910 | { 120, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMAX |
| 3911 | { 119, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MIN |
| 3912 | { 118, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MAX |
| 3913 | { 117, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XOR |
| 3914 | { 116, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_OR |
| 3915 | { 115, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_NAND |
| 3916 | { 114, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_AND |
| 3917 | { 113, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_SUB |
| 3918 | { 112, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_ADD |
| 3919 | { 111, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XCHG |
| 3920 | { 110, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG |
| 3921 | { 109, 5, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 81, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG_WITH_SUCCESS |
| 3922 | { 108, 5, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 76, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_STORE |
| 3923 | { 107, 2, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNCSTORE |
| 3924 | { 106, 2, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STORE |
| 3925 | { 105, 5, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_ZEXTLOAD |
| 3926 | { 104, 5, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_SEXTLOAD |
| 3927 | { 103, 5, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_LOAD |
| 3928 | { 102, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXTLOAD |
| 3929 | { 101, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXTLOAD |
| 3930 | { 100, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXTLOAD |
| 3931 | { 99, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LOAD |
| 3932 | { 98, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READSTEADYCOUNTER |
| 3933 | { 97, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READCYCLECOUNTER |
| 3934 | { 96, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUNDEVEN |
| 3935 | { 95, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LLRINT |
| 3936 | { 94, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LRINT |
| 3937 | { 93, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUND |
| 3938 | { 92, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_TRUNC |
| 3939 | { 91, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_FPTRUNC_ROUND |
| 3940 | { 90, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_FOLD_BARRIER |
| 3941 | { 89, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREEZE |
| 3942 | { 88, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITCAST |
| 3943 | { 87, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTTOPTR |
| 3944 | { 86, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRTOINT |
| 3945 | { 85, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONCAT_VECTORS |
| 3946 | { 84, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR_TRUNC |
| 3947 | { 83, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR |
| 3948 | { 82, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MERGE_VALUES |
| 3949 | { 81, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT |
| 3950 | { 80, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UNMERGE_VALUES |
| 3951 | { 79, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT |
| 3952 | { 78, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_POOL |
| 3953 | { 77, 5, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 52, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRAUTH_GLOBAL_VALUE |
| 3954 | { 76, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GLOBAL_VALUE |
| 3955 | { 75, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRAME_INDEX |
| 3956 | { 74, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PHI |
| 3957 | { 73, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IMPLICIT_DEF |
| 3958 | { 72, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGCEIL |
| 3959 | { 71, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGFLOOR |
| 3960 | { 70, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGCEIL |
| 3961 | { 69, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGFLOOR |
| 3962 | { 68, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDU |
| 3963 | { 67, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDS |
| 3964 | { 66, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_XOR |
| 3965 | { 65, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_OR |
| 3966 | { 64, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_AND |
| 3967 | { 63, 4, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVREM |
| 3968 | { 62, 4, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVREM |
| 3969 | { 61, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UREM |
| 3970 | { 60, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SREM |
| 3971 | { 59, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIV |
| 3972 | { 58, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIV |
| 3973 | { 57, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MUL |
| 3974 | { 56, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SUB |
| 3975 | { 55, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADD |
| 3976 | { 54, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ALIGN |
| 3977 | { 53, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ZEXT |
| 3978 | { 52, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_SEXT |
| 3979 | { 51, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_GLUE |
| 3980 | { 50, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_LOOP |
| 3981 | { 49, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ANCHOR |
| 3982 | { 48, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ENTRY |
| 3983 | { 47, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELOC_NONE |
| 3984 | { 46, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUMP_TABLE_DEBUG_INFO |
| 3985 | { 45, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMBARRIER |
| 3986 | { 44, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAKE_USE |
| 3987 | { 43, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ICALL_BRANCH_FUNNEL |
| 3988 | { 42, 3, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 36, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_15722 |
| 3989 | { 41, 2, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 34, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_15721 |
| 3990 | { 40, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_TAIL_CALL |
| 3991 | { 39, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_EXIT |
| 3992 | { 38, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_RET |
| 3993 | { 37, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_ENTER |
| 3994 | { 36, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_OP |
| 3995 | { 35, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAULTING_OP |
| 3996 | { 34, 2, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 32, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_ESCAPE |
| 3997 | { 33, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STATEPOINT |
| 3998 | { 32, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 29, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_15720 |
| 3999 | { 31, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PREALLOCATED_SETUP |
| 4000 | { 30, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 28, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14417 |
| 4001 | { 29, 6, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 22, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHPOINT |
| 4002 | { 28, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FENTRY_CALL |
| 4003 | { 27, 2, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STACKMAP |
| 4004 | { 26, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 18, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARITH_FENCE |
| 4005 | { 25, 4, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 14, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PSEUDO_PROBE |
| 4006 | { 24, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_END |
| 4007 | { 23, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_START |
| 4008 | { 22, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BUNDLE |
| 4009 | { 21, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 11, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_LANEMASK |
| 4010 | { 20, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY |
| 4011 | { 19, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REG_SEQUENCE |
| 4012 | { 18, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_LABEL |
| 4013 | { 17, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_PHI |
| 4014 | { 16, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_INSTR_REF |
| 4015 | { 15, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE_LIST |
| 4016 | { 14, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE |
| 4017 | { 13, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_TO_REGCLASS |
| 4018 | { 12, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBREG_TO_REG |
| 4019 | { 11, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INIT_UNDEF |
| 4020 | { 10, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // IMPLICIT_DEF |
| 4021 | { 9, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 5, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INSERT_SUBREG |
| 4022 | { 8, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_SUBREG |
| 4023 | { 7, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KILL |
| 4024 | { 6, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANNOTATION_LABEL |
| 4025 | { 5, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GC_LABEL |
| 4026 | { 4, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EH_LABEL |
| 4027 | { 3, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CFI_INSTRUCTION |
| 4028 | { 2, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM_BR |
| 4029 | { 1, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM |
| 4030 | { 0, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PHI |
| 4031 | }, { |
| 4032 | /* 0 */ |
| 4033 | /* 0 */ WebAssembly::SP32, WebAssembly::SP64, WebAssembly::ARGUMENTS, |
| 4034 | /* 3 */ WebAssembly::ARGUMENTS, |
| 4035 | /* 4 */ WebAssembly::SP32, WebAssembly::SP64, WebAssembly::SP32, WebAssembly::SP64, |
| 4036 | /* 8 */ WebAssembly::VALUE_STACK, WebAssembly::VALUE_STACK, |
| 4037 | }, { |
| 4038 | 0 |
| 4039 | }, { |
| 4040 | /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 4041 | /* 1 */ |
| 4042 | /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 4043 | /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 4044 | /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 4045 | /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 4046 | /* 11 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 4047 | /* 14 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 4048 | /* 18 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, |
| 4049 | /* 20 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 4050 | /* 22 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 4051 | /* 28 */ { WebAssembly::wasm_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 }, |
| 4052 | /* 29 */ { WebAssembly::wasm_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 4053 | /* 32 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 4054 | /* 34 */ { WebAssembly::wasm_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 4055 | /* 36 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { WebAssembly::wasm_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 4056 | /* 39 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, |
| 4057 | /* 42 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 4058 | /* 45 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 4059 | /* 49 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 4060 | /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 4061 | /* 52 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 4062 | /* 57 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, |
| 4063 | /* 60 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 4064 | /* 62 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, |
| 4065 | /* 66 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 4066 | /* 68 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 4067 | /* 71 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 4068 | /* 76 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 4069 | /* 81 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 4070 | /* 86 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 4071 | /* 90 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 4072 | /* 93 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_2, 0 }, |
| 4073 | /* 97 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 4074 | /* 100 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 4075 | /* 103 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 4076 | /* 107 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 4077 | /* 111 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 4078 | /* 114 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 4079 | /* 119 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, |
| 4080 | /* 123 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 4081 | /* 126 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, |
| 4082 | /* 130 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, |
| 4083 | /* 133 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 4084 | /* 137 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 4085 | /* 141 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 4086 | /* 143 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, |
| 4087 | /* 147 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 4088 | /* 151 */ { -1, 0, WebAssembly::OPERAND_FUNCTION32, 0 }, |
| 4089 | /* 152 */ { -1, 0, WebAssembly::OPERAND_BASIC_BLOCK, 0 }, { -1, 0, WebAssembly::OPERAND_BASIC_BLOCK, 0 }, |
| 4090 | /* 154 */ { -1, 0, WebAssembly::OPERAND_BASIC_BLOCK, 0 }, |
| 4091 | /* 155 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4092 | /* 157 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4093 | /* 159 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4094 | /* 161 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4095 | /* 164 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4096 | /* 167 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4097 | /* 170 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4098 | /* 173 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4099 | /* 176 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4100 | /* 178 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 4101 | /* 180 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 4102 | /* 182 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 4103 | /* 184 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 4104 | /* 186 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 4105 | /* 188 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 4106 | /* 190 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 4107 | /* 192 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 4108 | /* 194 */ { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, |
| 4109 | /* 195 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4110 | /* 200 */ { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, |
| 4111 | /* 203 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4112 | /* 208 */ { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, |
| 4113 | /* 211 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4114 | /* 216 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4115 | /* 221 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4116 | /* 227 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4117 | /* 233 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4118 | /* 239 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4119 | /* 245 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4120 | /* 252 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4121 | /* 259 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4122 | /* 266 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4123 | /* 273 */ { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4124 | /* 278 */ { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4125 | /* 283 */ { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4126 | /* 288 */ { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4127 | /* 293 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4128 | /* 297 */ { -1, 0, WebAssembly::OPERAND_SIGNATURE, 0 }, |
| 4129 | /* 298 */ { -1, 0, WebAssembly::OPERAND_BASIC_BLOCK, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4130 | /* 300 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4131 | /* 301 */ { -1, 0, WebAssembly::OPERAND_BRLIST, 0 }, |
| 4132 | /* 302 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4133 | /* 303 */ { -1, 0, WebAssembly::OPERAND_TYPEINDEX, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, |
| 4134 | /* 305 */ { -1, 0, WebAssembly::OPERAND_TYPEINDEX, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4135 | /* 307 */ { -1, 0, WebAssembly::OPERAND_TYPEINDEX, 0 }, |
| 4136 | /* 308 */ { -1, 0, WebAssembly::OPERAND_TAG, 0 }, |
| 4137 | /* 309 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4138 | /* 310 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4139 | /* 312 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4140 | /* 314 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, |
| 4141 | /* 316 */ { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, |
| 4142 | /* 317 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_F64IMM, 0 }, |
| 4143 | /* 319 */ { -1, 0, WebAssembly::OPERAND_F64IMM, 0 }, |
| 4144 | /* 320 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, |
| 4145 | /* 322 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, |
| 4146 | /* 323 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_I64IMM, 0 }, |
| 4147 | /* 325 */ { -1, 0, WebAssembly::OPERAND_I64IMM, 0 }, |
| 4148 | /* 326 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, |
| 4149 | /* 331 */ { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, |
| 4150 | /* 335 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_F64IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F64IMM, 0 }, |
| 4151 | /* 338 */ { -1, 0, WebAssembly::OPERAND_F64IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F64IMM, 0 }, |
| 4152 | /* 340 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, |
| 4153 | /* 349 */ { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, |
| 4154 | /* 357 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, |
| 4155 | /* 362 */ { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, |
| 4156 | /* 366 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I64IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I64IMM, 0 }, |
| 4157 | /* 369 */ { -1, 0, WebAssembly::OPERAND_VEC_I64IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I64IMM, 0 }, |
| 4158 | /* 371 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, |
| 4159 | /* 388 */ { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, |
| 4160 | /* 404 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4161 | /* 406 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4162 | /* 408 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4163 | /* 410 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4164 | /* 411 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4165 | /* 412 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4166 | /* 413 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4167 | /* 414 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4168 | /* 415 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4169 | /* 417 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4170 | /* 420 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4171 | /* 423 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4172 | /* 426 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, |
| 4173 | /* 429 */ { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, |
| 4174 | /* 430 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, |
| 4175 | /* 433 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, |
| 4176 | /* 436 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, |
| 4177 | /* 439 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4178 | /* 441 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4179 | /* 443 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4180 | /* 445 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4181 | /* 447 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4182 | /* 449 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4183 | /* 451 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4184 | /* 453 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4185 | /* 455 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4186 | /* 457 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4187 | /* 459 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, |
| 4188 | /* 461 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, |
| 4189 | /* 462 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, |
| 4190 | /* 464 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, |
| 4191 | /* 466 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, |
| 4192 | /* 468 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, |
| 4193 | /* 470 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, |
| 4194 | /* 472 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, |
| 4195 | /* 474 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, |
| 4196 | /* 476 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4197 | /* 478 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4198 | /* 480 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4199 | /* 482 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4200 | /* 484 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4201 | /* 486 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4202 | /* 488 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4203 | /* 490 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4204 | /* 492 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4205 | /* 498 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4206 | /* 500 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4207 | /* 504 */ { -1, 0, WebAssembly::OPERAND_SIGNATURE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4208 | /* 506 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4209 | /* 510 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, |
| 4210 | /* 512 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4211 | /* 516 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, |
| 4212 | /* 518 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4213 | /* 522 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4214 | /* 526 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4215 | /* 530 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4216 | /* 534 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4217 | /* 538 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4218 | /* 542 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4219 | /* 546 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4220 | /* 550 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4221 | /* 556 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, |
| 4222 | /* 559 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4223 | /* 565 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, |
| 4224 | /* 568 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, |
| 4225 | /* 570 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, |
| 4226 | /* 571 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, |
| 4227 | /* 573 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, |
| 4228 | /* 575 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, |
| 4229 | /* 577 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, |
| 4230 | /* 579 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, |
| 4231 | /* 581 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, |
| 4232 | /* 583 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, |
| 4233 | /* 585 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4234 | /* 587 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4235 | /* 589 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4236 | /* 591 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4237 | /* 593 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4238 | /* 595 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4239 | /* 597 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4240 | /* 599 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4241 | /* 601 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4242 | /* 604 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4243 | /* 607 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4244 | /* 610 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4245 | /* 613 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4246 | /* 616 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4247 | /* 619 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4248 | /* 622 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4249 | /* 625 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4250 | /* 630 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, |
| 4251 | /* 632 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4252 | /* 637 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4253 | /* 644 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4254 | /* 651 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4255 | /* 658 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4256 | /* 665 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4257 | /* 669 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4258 | /* 673 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4259 | /* 678 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TYPEINDEX, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4260 | /* 681 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_FUNCTION32, 0 }, |
| 4261 | /* 683 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4262 | /* 685 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4263 | /* 687 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4264 | /* 689 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TYPEINDEX, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4265 | /* 692 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4266 | /* 696 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4267 | /* 700 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4268 | /* 704 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4269 | /* 708 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4270 | /* 712 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4271 | /* 716 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4272 | /* 720 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4273 | /* 724 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4274 | /* 728 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4275 | /* 732 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4276 | /* 736 */ { -1, 0, WebAssembly::OPERAND_VALTYPE_LIST, 0 }, |
| 4277 | /* 737 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4278 | /* 741 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4279 | /* 744 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, |
| 4280 | /* 763 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4281 | /* 765 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4282 | /* 767 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4283 | /* 769 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4284 | /* 771 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4285 | /* 775 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4286 | /* 779 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4287 | /* 783 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4288 | /* 787 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4289 | /* 791 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4290 | /* 795 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4291 | /* 799 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4292 | /* 803 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4293 | /* 808 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4294 | /* 813 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4295 | /* 817 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4296 | /* 821 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4297 | /* 826 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, |
| 4298 | /* 828 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4299 | /* 832 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, |
| 4300 | /* 833 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4301 | /* 837 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4302 | /* 841 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4303 | /* 844 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4304 | /* 847 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4305 | /* 850 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4306 | /* 854 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4307 | /* 858 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4308 | /* 862 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4309 | /* 865 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4310 | /* 868 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4311 | /* 871 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, |
| 4312 | /* 873 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4313 | /* 876 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4314 | /* 879 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4315 | /* 882 */ { -1, 0, WebAssembly::OPERAND_SIGNATURE, 0 }, { -1, 0, WebAssembly::OPERAND_CATCH_LIST, 0 }, |
| 4316 | /* 884 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4317 | /* 887 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4318 | } |
| 4319 | }; |
| 4320 | |
| 4321 | |
| 4322 | #ifdef __GNUC__ |
| 4323 | #pragma GCC diagnostic push |
| 4324 | #pragma GCC diagnostic ignored "-Woverlength-strings" |
| 4325 | #endif |
| 4326 | extern const char WebAssemblyInstrNameData[] = { |
| 4327 | /* 0 */ "G_FLOG10\000" |
| 4328 | /* 9 */ "G_FEXP10\000" |
| 4329 | /* 18 */ "LOAD_F16_F32_A32\000" |
| 4330 | /* 35 */ "STORE_F16_F32_A32\000" |
| 4331 | /* 53 */ "LOAD_F32_A32\000" |
| 4332 | /* 66 */ "STORE_F32_A32\000" |
| 4333 | /* 80 */ "ATOMIC_STORE16_I32_A32\000" |
| 4334 | /* 103 */ "ATOMIC_STORE8_I32_A32\000" |
| 4335 | /* 125 */ "ATOMIC_RMW16_U_SUB_I32_A32\000" |
| 4336 | /* 152 */ "ATOMIC_RMW8_U_SUB_I32_A32\000" |
| 4337 | /* 178 */ "ATOMIC_RMW_SUB_I32_A32\000" |
| 4338 | /* 201 */ "ATOMIC_LOAD_I32_A32\000" |
| 4339 | /* 221 */ "ATOMIC_RMW16_U_ADD_I32_A32\000" |
| 4340 | /* 248 */ "ATOMIC_RMW8_U_ADD_I32_A32\000" |
| 4341 | /* 274 */ "ATOMIC_RMW_ADD_I32_A32\000" |
| 4342 | /* 297 */ "ATOMIC_RMW16_U_AND_I32_A32\000" |
| 4343 | /* 324 */ "ATOMIC_RMW8_U_AND_I32_A32\000" |
| 4344 | /* 350 */ "ATOMIC_RMW_AND_I32_A32\000" |
| 4345 | /* 373 */ "ATOMIC_STORE_I32_A32\000" |
| 4346 | /* 394 */ "ATOMIC_RMW16_U_CMPXCHG_I32_A32\000" |
| 4347 | /* 425 */ "ATOMIC_RMW8_U_CMPXCHG_I32_A32\000" |
| 4348 | /* 455 */ "ATOMIC_RMW_CMPXCHG_I32_A32\000" |
| 4349 | /* 482 */ "ATOMIC_RMW16_U_XCHG_I32_A32\000" |
| 4350 | /* 510 */ "ATOMIC_RMW8_U_XCHG_I32_A32\000" |
| 4351 | /* 537 */ "ATOMIC_RMW_XCHG_I32_A32\000" |
| 4352 | /* 561 */ "ATOMIC_RMW16_U_XOR_I32_A32\000" |
| 4353 | /* 588 */ "ATOMIC_RMW8_U_XOR_I32_A32\000" |
| 4354 | /* 614 */ "ATOMIC_RMW_XOR_I32_A32\000" |
| 4355 | /* 637 */ "ATOMIC_RMW16_U_OR_I32_A32\000" |
| 4356 | /* 663 */ "ATOMIC_RMW8_U_OR_I32_A32\000" |
| 4357 | /* 688 */ "ATOMIC_RMW_OR_I32_A32\000" |
| 4358 | /* 710 */ "LOAD16_S_I32_A32\000" |
| 4359 | /* 727 */ "LOAD8_S_I32_A32\000" |
| 4360 | /* 743 */ "ATOMIC_LOAD16_U_I32_A32\000" |
| 4361 | /* 767 */ "ATOMIC_LOAD8_U_I32_A32\000" |
| 4362 | /* 790 */ "MEMORY_ATOMIC_WAIT32_A32\000" |
| 4363 | /* 815 */ "LOAD_LANE_32_A32\000" |
| 4364 | /* 832 */ "LOAD_ZERO_32_A32\000" |
| 4365 | /* 849 */ "STORE_LANE_I64x2_A32\000" |
| 4366 | /* 870 */ "LOAD_EXTEND_S_I64x2_A32\000" |
| 4367 | /* 894 */ "LOAD_EXTEND_U_I64x2_A32\000" |
| 4368 | /* 918 */ "LOAD_F64_A32\000" |
| 4369 | /* 931 */ "STORE_F64_A32\000" |
| 4370 | /* 945 */ "ATOMIC_STORE32_I64_A32\000" |
| 4371 | /* 968 */ "ATOMIC_STORE16_I64_A32\000" |
| 4372 | /* 991 */ "ATOMIC_STORE8_I64_A32\000" |
| 4373 | /* 1013 */ "ATOMIC_RMW32_U_SUB_I64_A32\000" |
| 4374 | /* 1040 */ "ATOMIC_RMW16_U_SUB_I64_A32\000" |
| 4375 | /* 1067 */ "ATOMIC_RMW8_U_SUB_I64_A32\000" |
| 4376 | /* 1093 */ "ATOMIC_RMW_SUB_I64_A32\000" |
| 4377 | /* 1116 */ "ATOMIC_LOAD_I64_A32\000" |
| 4378 | /* 1136 */ "ATOMIC_RMW32_U_ADD_I64_A32\000" |
| 4379 | /* 1163 */ "ATOMIC_RMW16_U_ADD_I64_A32\000" |
| 4380 | /* 1190 */ "ATOMIC_RMW8_U_ADD_I64_A32\000" |
| 4381 | /* 1216 */ "ATOMIC_RMW_ADD_I64_A32\000" |
| 4382 | /* 1239 */ "ATOMIC_RMW32_U_AND_I64_A32\000" |
| 4383 | /* 1266 */ "ATOMIC_RMW16_U_AND_I64_A32\000" |
| 4384 | /* 1293 */ "ATOMIC_RMW8_U_AND_I64_A32\000" |
| 4385 | /* 1319 */ "ATOMIC_RMW_AND_I64_A32\000" |
| 4386 | /* 1342 */ "ATOMIC_STORE_I64_A32\000" |
| 4387 | /* 1363 */ "ATOMIC_RMW32_U_CMPXCHG_I64_A32\000" |
| 4388 | /* 1394 */ "ATOMIC_RMW16_U_CMPXCHG_I64_A32\000" |
| 4389 | /* 1425 */ "ATOMIC_RMW8_U_CMPXCHG_I64_A32\000" |
| 4390 | /* 1455 */ "ATOMIC_RMW_CMPXCHG_I64_A32\000" |
| 4391 | /* 1482 */ "ATOMIC_RMW32_U_XCHG_I64_A32\000" |
| 4392 | /* 1510 */ "ATOMIC_RMW16_U_XCHG_I64_A32\000" |
| 4393 | /* 1538 */ "ATOMIC_RMW8_U_XCHG_I64_A32\000" |
| 4394 | /* 1565 */ "ATOMIC_RMW_XCHG_I64_A32\000" |
| 4395 | /* 1589 */ "ATOMIC_RMW32_U_XOR_I64_A32\000" |
| 4396 | /* 1616 */ "ATOMIC_RMW16_U_XOR_I64_A32\000" |
| 4397 | /* 1643 */ "ATOMIC_RMW8_U_XOR_I64_A32\000" |
| 4398 | /* 1669 */ "ATOMIC_RMW_XOR_I64_A32\000" |
| 4399 | /* 1692 */ "ATOMIC_RMW32_U_OR_I64_A32\000" |
| 4400 | /* 1718 */ "ATOMIC_RMW16_U_OR_I64_A32\000" |
| 4401 | /* 1744 */ "ATOMIC_RMW8_U_OR_I64_A32\000" |
| 4402 | /* 1769 */ "ATOMIC_RMW_OR_I64_A32\000" |
| 4403 | /* 1791 */ "LOAD32_S_I64_A32\000" |
| 4404 | /* 1808 */ "LOAD16_S_I64_A32\000" |
| 4405 | /* 1825 */ "LOAD8_S_I64_A32\000" |
| 4406 | /* 1841 */ "ATOMIC_LOAD32_U_I64_A32\000" |
| 4407 | /* 1865 */ "ATOMIC_LOAD16_U_I64_A32\000" |
| 4408 | /* 1889 */ "ATOMIC_LOAD8_U_I64_A32\000" |
| 4409 | /* 1912 */ "MEMORY_ATOMIC_WAIT64_A32\000" |
| 4410 | /* 1937 */ "LOAD_LANE_64_A32\000" |
| 4411 | /* 1954 */ "LOAD_ZERO_64_A32\000" |
| 4412 | /* 1971 */ "STORE_LANE_I32x4_A32\000" |
| 4413 | /* 1992 */ "LOAD_EXTEND_S_I32x4_A32\000" |
| 4414 | /* 2016 */ "LOAD_EXTEND_U_I32x4_A32\000" |
| 4415 | /* 2040 */ "LOAD_LANE_16_A32\000" |
| 4416 | /* 2057 */ "STORE_LANE_I8x16_A32\000" |
| 4417 | /* 2078 */ "LOAD_V128_A32\000" |
| 4418 | /* 2092 */ "STORE_V128_A32\000" |
| 4419 | /* 2107 */ "LOAD_LANE_8_A32\000" |
| 4420 | /* 2123 */ "STORE_LANE_I16x8_A32\000" |
| 4421 | /* 2144 */ "LOAD_EXTEND_S_I16x8_A32\000" |
| 4422 | /* 2168 */ "LOAD_EXTEND_U_I16x8_A32\000" |
| 4423 | /* 2192 */ "anonymous_14864MEMORY_SIZE_A32\000" |
| 4424 | /* 2223 */ "MEMORY_FILL_A32\000" |
| 4425 | /* 2239 */ "LOAD32_SPLAT_A32\000" |
| 4426 | /* 2256 */ "LOAD64_SPLAT_A32\000" |
| 4427 | /* 2273 */ "LOAD16_SPLAT_A32\000" |
| 4428 | /* 2290 */ "LOAD8_SPLAT_A32\000" |
| 4429 | /* 2306 */ "MEMSET_A32\000" |
| 4430 | /* 2317 */ "MEMORY_INIT_A32\000" |
| 4431 | /* 2333 */ "anonymous_14864MEMORY_GROW_A32\000" |
| 4432 | /* 2364 */ "MEMORY_ATOMIC_NOTIFY_A32\000" |
| 4433 | /* 2389 */ "MEMCPY_A32\000" |
| 4434 | /* 2400 */ "MEMORY_COPY_A32\000" |
| 4435 | /* 2416 */ "FP_TO_SINT_I32_F32\000" |
| 4436 | /* 2435 */ "FP_TO_UINT_I32_F32\000" |
| 4437 | /* 2454 */ "FP_TO_SINT_I64_F32\000" |
| 4438 | /* 2473 */ "FP_TO_UINT_I64_F32\000" |
| 4439 | /* 2492 */ "SUB_F32\000" |
| 4440 | /* 2500 */ "TRUNC_F32\000" |
| 4441 | /* 2510 */ "ADD_F32\000" |
| 4442 | /* 2518 */ "LOCAL_TEE_F32\000" |
| 4443 | /* 2532 */ "GE_F32\000" |
| 4444 | /* 2539 */ "LE_F32\000" |
| 4445 | /* 2546 */ "NE_F32\000" |
| 4446 | /* 2553 */ "F64_PROMOTE_F32\000" |
| 4447 | /* 2569 */ "NEG_F32\000" |
| 4448 | /* 2577 */ "CEIL_F32\000" |
| 4449 | /* 2586 */ "MUL_F32\000" |
| 4450 | /* 2594 */ "COPYSIGN_F32\000" |
| 4451 | /* 2607 */ "MIN_F32\000" |
| 4452 | /* 2615 */ "DROP_F32\000" |
| 4453 | /* 2624 */ "EQ_F32\000" |
| 4454 | /* 2631 */ "FLOOR_F32\000" |
| 4455 | /* 2641 */ "ABS_F32\000" |
| 4456 | /* 2649 */ "I32_TRUNC_S_F32\000" |
| 4457 | /* 2665 */ "I64_TRUNC_S_F32\000" |
| 4458 | /* 2681 */ "I32_TRUNC_S_SAT_F32\000" |
| 4459 | /* 2701 */ "I64_TRUNC_S_SAT_F32\000" |
| 4460 | /* 2721 */ "I32_TRUNC_U_SAT_F32\000" |
| 4461 | /* 2741 */ "I64_TRUNC_U_SAT_F32\000" |
| 4462 | /* 2761 */ "SELECT_F32\000" |
| 4463 | /* 2772 */ "GLOBAL_GET_F32\000" |
| 4464 | /* 2787 */ "LOCAL_GET_F32\000" |
| 4465 | /* 2801 */ "I32_REINTERPRET_F32\000" |
| 4466 | /* 2821 */ "GLOBAL_SET_F32\000" |
| 4467 | /* 2836 */ "LOCAL_SET_F32\000" |
| 4468 | /* 2850 */ "GT_F32\000" |
| 4469 | /* 2857 */ "LT_F32\000" |
| 4470 | /* 2864 */ "SQRT_F32\000" |
| 4471 | /* 2873 */ "NEAREST_F32\000" |
| 4472 | /* 2885 */ "CONST_F32\000" |
| 4473 | /* 2895 */ "I32_TRUNC_U_F32\000" |
| 4474 | /* 2911 */ "I64_TRUNC_U_F32\000" |
| 4475 | /* 2927 */ "DIV_F32\000" |
| 4476 | /* 2935 */ "MAX_F32\000" |
| 4477 | /* 2943 */ "COPY_F32\000" |
| 4478 | /* 2952 */ "SUB_I32\000" |
| 4479 | /* 2960 */ "ADD_I32\000" |
| 4480 | /* 2968 */ "AND_I32\000" |
| 4481 | /* 2976 */ "LOCAL_TEE_I32\000" |
| 4482 | /* 2990 */ "BR_TABLE_I32\000" |
| 4483 | /* 3003 */ "NE_I32\000" |
| 4484 | /* 3010 */ "SHL_I32\000" |
| 4485 | /* 3018 */ "ROTL_I32\000" |
| 4486 | /* 3027 */ "MUL_I32\000" |
| 4487 | /* 3035 */ "DROP_I32\000" |
| 4488 | /* 3044 */ "EQ_I32\000" |
| 4489 | /* 3051 */ "XOR_I32\000" |
| 4490 | /* 3059 */ "ROTR_I32\000" |
| 4491 | /* 3068 */ "I32_EXTEND16_S_I32\000" |
| 4492 | /* 3087 */ "I32_EXTEND8_S_I32\000" |
| 4493 | /* 3105 */ "I64_EXTEND_S_I32\000" |
| 4494 | /* 3122 */ "GE_S_I32\000" |
| 4495 | /* 3131 */ "LE_S_I32\000" |
| 4496 | /* 3140 */ "REM_S_I32\000" |
| 4497 | /* 3150 */ "SHR_S_I32\000" |
| 4498 | /* 3160 */ "GT_S_I32\000" |
| 4499 | /* 3169 */ "LT_S_I32\000" |
| 4500 | /* 3178 */ "F32_CONVERT_S_I32\000" |
| 4501 | /* 3196 */ "F64_CONVERT_S_I32\000" |
| 4502 | /* 3214 */ "DIV_S_I32\000" |
| 4503 | /* 3224 */ "SELECT_I32\000" |
| 4504 | /* 3235 */ "GLOBAL_GET_I32\000" |
| 4505 | /* 3250 */ "LOCAL_GET_I32\000" |
| 4506 | /* 3264 */ "F32_REINTERPRET_I32\000" |
| 4507 | /* 3284 */ "GLOBAL_SET_I32\000" |
| 4508 | /* 3299 */ "LOCAL_SET_I32\000" |
| 4509 | /* 3313 */ "POPCNT_I32\000" |
| 4510 | /* 3324 */ "CONST_I32\000" |
| 4511 | /* 3334 */ "I64_EXTEND_U_I32\000" |
| 4512 | /* 3351 */ "GE_U_I32\000" |
| 4513 | /* 3360 */ "LE_U_I32\000" |
| 4514 | /* 3369 */ "REM_U_I32\000" |
| 4515 | /* 3379 */ "SHR_U_I32\000" |
| 4516 | /* 3389 */ "GT_U_I32\000" |
| 4517 | /* 3398 */ "LT_U_I32\000" |
| 4518 | /* 3407 */ "F32_CONVERT_U_I32\000" |
| 4519 | /* 3425 */ "F64_CONVERT_U_I32\000" |
| 4520 | /* 3443 */ "DIV_U_I32\000" |
| 4521 | /* 3453 */ "COPY_I32\000" |
| 4522 | /* 3462 */ "CLZ_I32\000" |
| 4523 | /* 3470 */ "EQZ_I32\000" |
| 4524 | /* 3478 */ "CTZ_I32\000" |
| 4525 | /* 3486 */ "ARGUMENT_v4f32\000" |
| 4526 | /* 3501 */ "ARGUMENT_f32\000" |
| 4527 | /* 3514 */ "ARGUMENT_v4i32\000" |
| 4528 | /* 3529 */ "ARGUMENT_i32\000" |
| 4529 | /* 3542 */ "G_FLOG2\000" |
| 4530 | /* 3550 */ "G_FATAN2\000" |
| 4531 | /* 3559 */ "G_FEXP2\000" |
| 4532 | /* 3567 */ "CONST_V128_F64x2\000" |
| 4533 | /* 3584 */ "SUB_F64x2\000" |
| 4534 | /* 3594 */ "TRUNC_F64x2\000" |
| 4535 | /* 3606 */ "NMADD_F64x2\000" |
| 4536 | /* 3618 */ "GE_F64x2\000" |
| 4537 | /* 3627 */ "LE_F64x2\000" |
| 4538 | /* 3636 */ "REPLACE_LANE_F64x2\000" |
| 4539 | /* 3655 */ "EXTRACT_LANE_F64x2\000" |
| 4540 | /* 3674 */ "NEG_F64x2\000" |
| 4541 | /* 3684 */ "CEIL_F64x2\000" |
| 4542 | /* 3695 */ "MUL_F64x2\000" |
| 4543 | /* 3705 */ "SIMD_RELAXED_FMIN_F64x2\000" |
| 4544 | /* 3729 */ "PMIN_F64x2\000" |
| 4545 | /* 3740 */ "EQ_F64x2\000" |
| 4546 | /* 3749 */ "FLOOR_F64x2\000" |
| 4547 | /* 3761 */ "ABS_F64x2\000" |
| 4548 | /* 3771 */ "SPLAT_F64x2\000" |
| 4549 | /* 3783 */ "GT_F64x2\000" |
| 4550 | /* 3792 */ "LT_F64x2\000" |
| 4551 | /* 3801 */ "SQRT_F64x2\000" |
| 4552 | /* 3812 */ "NEAREST_F64x2\000" |
| 4553 | /* 3826 */ "DIV_F64x2\000" |
| 4554 | /* 3836 */ "SIMD_RELAXED_FMAX_F64x2\000" |
| 4555 | /* 3860 */ "PMAX_F64x2\000" |
| 4556 | /* 3871 */ "convert_low_s_F64x2\000" |
| 4557 | /* 3891 */ "convert_low_u_F64x2\000" |
| 4558 | /* 3911 */ "promote_low_F64x2\000" |
| 4559 | /* 3929 */ "CONST_V128_I64x2\000" |
| 4560 | /* 3946 */ "SUB_I64x2\000" |
| 4561 | /* 3956 */ "ADD_I64x2\000" |
| 4562 | /* 3966 */ "REPLACE_LANE_I64x2\000" |
| 4563 | /* 3985 */ "EXTRACT_LANE_I64x2\000" |
| 4564 | /* 4004 */ "ALLTRUE_I64x2\000" |
| 4565 | /* 4018 */ "NEG_I64x2\000" |
| 4566 | /* 4028 */ "BITMASK_I64x2\000" |
| 4567 | /* 4042 */ "SHL_I64x2\000" |
| 4568 | /* 4052 */ "MUL_I64x2\000" |
| 4569 | /* 4062 */ "EQ_I64x2\000" |
| 4570 | /* 4071 */ "ABS_I64x2\000" |
| 4571 | /* 4081 */ "GE_S_I64x2\000" |
| 4572 | /* 4092 */ "LE_S_I64x2\000" |
| 4573 | /* 4103 */ "EXTMUL_HIGH_S_I64x2\000" |
| 4574 | /* 4123 */ "SHR_S_I64x2\000" |
| 4575 | /* 4135 */ "GT_S_I64x2\000" |
| 4576 | /* 4146 */ "LT_S_I64x2\000" |
| 4577 | /* 4157 */ "EXTMUL_LOW_S_I64x2\000" |
| 4578 | /* 4176 */ "SPLAT_I64x2\000" |
| 4579 | /* 4188 */ "LANESELECT_I64x2\000" |
| 4580 | /* 4205 */ "EXTMUL_HIGH_U_I64x2\000" |
| 4581 | /* 4225 */ "SHR_U_I64x2\000" |
| 4582 | /* 4237 */ "EXTMUL_LOW_U_I64x2\000" |
| 4583 | /* 4256 */ "extend_high_s_I64x2\000" |
| 4584 | /* 4276 */ "extend_low_s_I64x2\000" |
| 4585 | /* 4295 */ "extend_high_u_I64x2\000" |
| 4586 | /* 4315 */ "extend_low_u_I64x2\000" |
| 4587 | /* 4334 */ "LOAD_F16_F32_A64\000" |
| 4588 | /* 4351 */ "STORE_F16_F32_A64\000" |
| 4589 | /* 4369 */ "LOAD_F32_A64\000" |
| 4590 | /* 4382 */ "STORE_F32_A64\000" |
| 4591 | /* 4396 */ "ATOMIC_STORE16_I32_A64\000" |
| 4592 | /* 4419 */ "ATOMIC_STORE8_I32_A64\000" |
| 4593 | /* 4441 */ "ATOMIC_RMW16_U_SUB_I32_A64\000" |
| 4594 | /* 4468 */ "ATOMIC_RMW8_U_SUB_I32_A64\000" |
| 4595 | /* 4494 */ "ATOMIC_RMW_SUB_I32_A64\000" |
| 4596 | /* 4517 */ "ATOMIC_LOAD_I32_A64\000" |
| 4597 | /* 4537 */ "ATOMIC_RMW16_U_ADD_I32_A64\000" |
| 4598 | /* 4564 */ "ATOMIC_RMW8_U_ADD_I32_A64\000" |
| 4599 | /* 4590 */ "ATOMIC_RMW_ADD_I32_A64\000" |
| 4600 | /* 4613 */ "ATOMIC_RMW16_U_AND_I32_A64\000" |
| 4601 | /* 4640 */ "ATOMIC_RMW8_U_AND_I32_A64\000" |
| 4602 | /* 4666 */ "ATOMIC_RMW_AND_I32_A64\000" |
| 4603 | /* 4689 */ "ATOMIC_STORE_I32_A64\000" |
| 4604 | /* 4710 */ "ATOMIC_RMW16_U_CMPXCHG_I32_A64\000" |
| 4605 | /* 4741 */ "ATOMIC_RMW8_U_CMPXCHG_I32_A64\000" |
| 4606 | /* 4771 */ "ATOMIC_RMW_CMPXCHG_I32_A64\000" |
| 4607 | /* 4798 */ "ATOMIC_RMW16_U_XCHG_I32_A64\000" |
| 4608 | /* 4826 */ "ATOMIC_RMW8_U_XCHG_I32_A64\000" |
| 4609 | /* 4853 */ "ATOMIC_RMW_XCHG_I32_A64\000" |
| 4610 | /* 4877 */ "ATOMIC_RMW16_U_XOR_I32_A64\000" |
| 4611 | /* 4904 */ "ATOMIC_RMW8_U_XOR_I32_A64\000" |
| 4612 | /* 4930 */ "ATOMIC_RMW_XOR_I32_A64\000" |
| 4613 | /* 4953 */ "ATOMIC_RMW16_U_OR_I32_A64\000" |
| 4614 | /* 4979 */ "ATOMIC_RMW8_U_OR_I32_A64\000" |
| 4615 | /* 5004 */ "ATOMIC_RMW_OR_I32_A64\000" |
| 4616 | /* 5026 */ "LOAD16_S_I32_A64\000" |
| 4617 | /* 5043 */ "LOAD8_S_I32_A64\000" |
| 4618 | /* 5059 */ "ATOMIC_LOAD16_U_I32_A64\000" |
| 4619 | /* 5083 */ "ATOMIC_LOAD8_U_I32_A64\000" |
| 4620 | /* 5106 */ "MEMORY_ATOMIC_WAIT32_A64\000" |
| 4621 | /* 5131 */ "LOAD_LANE_32_A64\000" |
| 4622 | /* 5148 */ "LOAD_ZERO_32_A64\000" |
| 4623 | /* 5165 */ "STORE_LANE_I64x2_A64\000" |
| 4624 | /* 5186 */ "LOAD_EXTEND_S_I64x2_A64\000" |
| 4625 | /* 5210 */ "LOAD_EXTEND_U_I64x2_A64\000" |
| 4626 | /* 5234 */ "LOAD_F64_A64\000" |
| 4627 | /* 5247 */ "STORE_F64_A64\000" |
| 4628 | /* 5261 */ "ATOMIC_STORE32_I64_A64\000" |
| 4629 | /* 5284 */ "ATOMIC_STORE16_I64_A64\000" |
| 4630 | /* 5307 */ "ATOMIC_STORE8_I64_A64\000" |
| 4631 | /* 5329 */ "ATOMIC_RMW32_U_SUB_I64_A64\000" |
| 4632 | /* 5356 */ "ATOMIC_RMW16_U_SUB_I64_A64\000" |
| 4633 | /* 5383 */ "ATOMIC_RMW8_U_SUB_I64_A64\000" |
| 4634 | /* 5409 */ "ATOMIC_RMW_SUB_I64_A64\000" |
| 4635 | /* 5432 */ "ATOMIC_LOAD_I64_A64\000" |
| 4636 | /* 5452 */ "ATOMIC_RMW32_U_ADD_I64_A64\000" |
| 4637 | /* 5479 */ "ATOMIC_RMW16_U_ADD_I64_A64\000" |
| 4638 | /* 5506 */ "ATOMIC_RMW8_U_ADD_I64_A64\000" |
| 4639 | /* 5532 */ "ATOMIC_RMW_ADD_I64_A64\000" |
| 4640 | /* 5555 */ "ATOMIC_RMW32_U_AND_I64_A64\000" |
| 4641 | /* 5582 */ "ATOMIC_RMW16_U_AND_I64_A64\000" |
| 4642 | /* 5609 */ "ATOMIC_RMW8_U_AND_I64_A64\000" |
| 4643 | /* 5635 */ "ATOMIC_RMW_AND_I64_A64\000" |
| 4644 | /* 5658 */ "ATOMIC_STORE_I64_A64\000" |
| 4645 | /* 5679 */ "ATOMIC_RMW32_U_CMPXCHG_I64_A64\000" |
| 4646 | /* 5710 */ "ATOMIC_RMW16_U_CMPXCHG_I64_A64\000" |
| 4647 | /* 5741 */ "ATOMIC_RMW8_U_CMPXCHG_I64_A64\000" |
| 4648 | /* 5771 */ "ATOMIC_RMW_CMPXCHG_I64_A64\000" |
| 4649 | /* 5798 */ "ATOMIC_RMW32_U_XCHG_I64_A64\000" |
| 4650 | /* 5826 */ "ATOMIC_RMW16_U_XCHG_I64_A64\000" |
| 4651 | /* 5854 */ "ATOMIC_RMW8_U_XCHG_I64_A64\000" |
| 4652 | /* 5881 */ "ATOMIC_RMW_XCHG_I64_A64\000" |
| 4653 | /* 5905 */ "ATOMIC_RMW32_U_XOR_I64_A64\000" |
| 4654 | /* 5932 */ "ATOMIC_RMW16_U_XOR_I64_A64\000" |
| 4655 | /* 5959 */ "ATOMIC_RMW8_U_XOR_I64_A64\000" |
| 4656 | /* 5985 */ "ATOMIC_RMW_XOR_I64_A64\000" |
| 4657 | /* 6008 */ "ATOMIC_RMW32_U_OR_I64_A64\000" |
| 4658 | /* 6034 */ "ATOMIC_RMW16_U_OR_I64_A64\000" |
| 4659 | /* 6060 */ "ATOMIC_RMW8_U_OR_I64_A64\000" |
| 4660 | /* 6085 */ "ATOMIC_RMW_OR_I64_A64\000" |
| 4661 | /* 6107 */ "LOAD32_S_I64_A64\000" |
| 4662 | /* 6124 */ "LOAD16_S_I64_A64\000" |
| 4663 | /* 6141 */ "LOAD8_S_I64_A64\000" |
| 4664 | /* 6157 */ "ATOMIC_LOAD32_U_I64_A64\000" |
| 4665 | /* 6181 */ "ATOMIC_LOAD16_U_I64_A64\000" |
| 4666 | /* 6205 */ "ATOMIC_LOAD8_U_I64_A64\000" |
| 4667 | /* 6228 */ "MEMORY_ATOMIC_WAIT64_A64\000" |
| 4668 | /* 6253 */ "LOAD_LANE_64_A64\000" |
| 4669 | /* 6270 */ "LOAD_ZERO_64_A64\000" |
| 4670 | /* 6287 */ "STORE_LANE_I32x4_A64\000" |
| 4671 | /* 6308 */ "LOAD_EXTEND_S_I32x4_A64\000" |
| 4672 | /* 6332 */ "LOAD_EXTEND_U_I32x4_A64\000" |
| 4673 | /* 6356 */ "LOAD_LANE_16_A64\000" |
| 4674 | /* 6373 */ "STORE_LANE_I8x16_A64\000" |
| 4675 | /* 6394 */ "LOAD_V128_A64\000" |
| 4676 | /* 6408 */ "STORE_V128_A64\000" |
| 4677 | /* 6423 */ "LOAD_LANE_8_A64\000" |
| 4678 | /* 6439 */ "STORE_LANE_I16x8_A64\000" |
| 4679 | /* 6460 */ "LOAD_EXTEND_S_I16x8_A64\000" |
| 4680 | /* 6484 */ "LOAD_EXTEND_U_I16x8_A64\000" |
| 4681 | /* 6508 */ "anonymous_14865MEMORY_SIZE_A64\000" |
| 4682 | /* 6539 */ "MEMORY_FILL_A64\000" |
| 4683 | /* 6555 */ "LOAD32_SPLAT_A64\000" |
| 4684 | /* 6572 */ "LOAD64_SPLAT_A64\000" |
| 4685 | /* 6589 */ "LOAD16_SPLAT_A64\000" |
| 4686 | /* 6606 */ "LOAD8_SPLAT_A64\000" |
| 4687 | /* 6622 */ "MEMSET_A64\000" |
| 4688 | /* 6633 */ "MEMORY_INIT_A64\000" |
| 4689 | /* 6649 */ "anonymous_14865MEMORY_GROW_A64\000" |
| 4690 | /* 6680 */ "MEMORY_ATOMIC_NOTIFY_A64\000" |
| 4691 | /* 6705 */ "MEMCPY_A64\000" |
| 4692 | /* 6716 */ "MEMORY_COPY_A64\000" |
| 4693 | /* 6732 */ "FP_TO_SINT_I32_F64\000" |
| 4694 | /* 6751 */ "FP_TO_UINT_I32_F64\000" |
| 4695 | /* 6770 */ "FP_TO_SINT_I64_F64\000" |
| 4696 | /* 6789 */ "FP_TO_UINT_I64_F64\000" |
| 4697 | /* 6808 */ "SUB_F64\000" |
| 4698 | /* 6816 */ "TRUNC_F64\000" |
| 4699 | /* 6826 */ "ADD_F64\000" |
| 4700 | /* 6834 */ "LOCAL_TEE_F64\000" |
| 4701 | /* 6848 */ "GE_F64\000" |
| 4702 | /* 6855 */ "LE_F64\000" |
| 4703 | /* 6862 */ "NE_F64\000" |
| 4704 | /* 6869 */ "F32_DEMOTE_F64\000" |
| 4705 | /* 6884 */ "NEG_F64\000" |
| 4706 | /* 6892 */ "CEIL_F64\000" |
| 4707 | /* 6901 */ "MUL_F64\000" |
| 4708 | /* 6909 */ "COPYSIGN_F64\000" |
| 4709 | /* 6922 */ "MIN_F64\000" |
| 4710 | /* 6930 */ "DROP_F64\000" |
| 4711 | /* 6939 */ "EQ_F64\000" |
| 4712 | /* 6946 */ "FLOOR_F64\000" |
| 4713 | /* 6956 */ "ABS_F64\000" |
| 4714 | /* 6964 */ "I32_TRUNC_S_F64\000" |
| 4715 | /* 6980 */ "I64_TRUNC_S_F64\000" |
| 4716 | /* 6996 */ "I32_TRUNC_S_SAT_F64\000" |
| 4717 | /* 7016 */ "I64_TRUNC_S_SAT_F64\000" |
| 4718 | /* 7036 */ "I32_TRUNC_U_SAT_F64\000" |
| 4719 | /* 7056 */ "I64_TRUNC_U_SAT_F64\000" |
| 4720 | /* 7076 */ "SELECT_F64\000" |
| 4721 | /* 7087 */ "GLOBAL_GET_F64\000" |
| 4722 | /* 7102 */ "LOCAL_GET_F64\000" |
| 4723 | /* 7116 */ "I64_REINTERPRET_F64\000" |
| 4724 | /* 7136 */ "GLOBAL_SET_F64\000" |
| 4725 | /* 7151 */ "LOCAL_SET_F64\000" |
| 4726 | /* 7165 */ "GT_F64\000" |
| 4727 | /* 7172 */ "LT_F64\000" |
| 4728 | /* 7179 */ "SQRT_F64\000" |
| 4729 | /* 7188 */ "NEAREST_F64\000" |
| 4730 | /* 7200 */ "CONST_F64\000" |
| 4731 | /* 7210 */ "I32_TRUNC_U_F64\000" |
| 4732 | /* 7226 */ "I64_TRUNC_U_F64\000" |
| 4733 | /* 7242 */ "DIV_F64\000" |
| 4734 | /* 7250 */ "MAX_F64\000" |
| 4735 | /* 7258 */ "COPY_F64\000" |
| 4736 | /* 7267 */ "SUB_I64\000" |
| 4737 | /* 7275 */ "ADD_I64\000" |
| 4738 | /* 7283 */ "AND_I64\000" |
| 4739 | /* 7291 */ "LOCAL_TEE_I64\000" |
| 4740 | /* 7305 */ "BR_TABLE_I64\000" |
| 4741 | /* 7318 */ "NE_I64\000" |
| 4742 | /* 7325 */ "SHL_I64\000" |
| 4743 | /* 7333 */ "ROTL_I64\000" |
| 4744 | /* 7342 */ "MUL_I64\000" |
| 4745 | /* 7350 */ "I32_WRAP_I64\000" |
| 4746 | /* 7363 */ "DROP_I64\000" |
| 4747 | /* 7372 */ "EQ_I64\000" |
| 4748 | /* 7379 */ "XOR_I64\000" |
| 4749 | /* 7387 */ "ROTR_I64\000" |
| 4750 | /* 7396 */ "I64_EXTEND32_S_I64\000" |
| 4751 | /* 7415 */ "I64_EXTEND16_S_I64\000" |
| 4752 | /* 7434 */ "I64_EXTEND8_S_I64\000" |
| 4753 | /* 7452 */ "GE_S_I64\000" |
| 4754 | /* 7461 */ "LE_S_I64\000" |
| 4755 | /* 7470 */ "REM_S_I64\000" |
| 4756 | /* 7480 */ "SHR_S_I64\000" |
| 4757 | /* 7490 */ "GT_S_I64\000" |
| 4758 | /* 7499 */ "LT_S_I64\000" |
| 4759 | /* 7508 */ "F32_CONVERT_S_I64\000" |
| 4760 | /* 7526 */ "F64_CONVERT_S_I64\000" |
| 4761 | /* 7544 */ "DIV_S_I64\000" |
| 4762 | /* 7554 */ "SELECT_I64\000" |
| 4763 | /* 7565 */ "GLOBAL_GET_I64\000" |
| 4764 | /* 7580 */ "LOCAL_GET_I64\000" |
| 4765 | /* 7594 */ "F64_REINTERPRET_I64\000" |
| 4766 | /* 7614 */ "GLOBAL_SET_I64\000" |
| 4767 | /* 7629 */ "LOCAL_SET_I64\000" |
| 4768 | /* 7643 */ "POPCNT_I64\000" |
| 4769 | /* 7654 */ "CONST_I64\000" |
| 4770 | /* 7664 */ "GE_U_I64\000" |
| 4771 | /* 7673 */ "LE_U_I64\000" |
| 4772 | /* 7682 */ "REM_U_I64\000" |
| 4773 | /* 7692 */ "SHR_U_I64\000" |
| 4774 | /* 7702 */ "GT_U_I64\000" |
| 4775 | /* 7711 */ "LT_U_I64\000" |
| 4776 | /* 7720 */ "F32_CONVERT_U_I64\000" |
| 4777 | /* 7738 */ "F64_CONVERT_U_I64\000" |
| 4778 | /* 7756 */ "DIV_U_I64\000" |
| 4779 | /* 7766 */ "COPY_I64\000" |
| 4780 | /* 7775 */ "CLZ_I64\000" |
| 4781 | /* 7783 */ "EQZ_I64\000" |
| 4782 | /* 7791 */ "CTZ_I64\000" |
| 4783 | /* 7799 */ "ARGUMENT_v2f64\000" |
| 4784 | /* 7814 */ "ARGUMENT_f64\000" |
| 4785 | /* 7827 */ "ARGUMENT_v2i64\000" |
| 4786 | /* 7842 */ "ARGUMENT_i64\000" |
| 4787 | /* 7855 */ "CONST_V128_F32x4\000" |
| 4788 | /* 7872 */ "SUB_F32x4\000" |
| 4789 | /* 7882 */ "TRUNC_F32x4\000" |
| 4790 | /* 7894 */ "NMADD_F32x4\000" |
| 4791 | /* 7906 */ "GE_F32x4\000" |
| 4792 | /* 7915 */ "LE_F32x4\000" |
| 4793 | /* 7924 */ "REPLACE_LANE_F32x4\000" |
| 4794 | /* 7943 */ "EXTRACT_LANE_F32x4\000" |
| 4795 | /* 7962 */ "NEG_F32x4\000" |
| 4796 | /* 7972 */ "CEIL_F32x4\000" |
| 4797 | /* 7983 */ "MUL_F32x4\000" |
| 4798 | /* 7993 */ "SIMD_RELAXED_FMIN_F32x4\000" |
| 4799 | /* 8017 */ "PMIN_F32x4\000" |
| 4800 | /* 8028 */ "EQ_F32x4\000" |
| 4801 | /* 8037 */ "FLOOR_F32x4\000" |
| 4802 | /* 8049 */ "ABS_F32x4\000" |
| 4803 | /* 8059 */ "SPLAT_F32x4\000" |
| 4804 | /* 8071 */ "GT_F32x4\000" |
| 4805 | /* 8080 */ "LT_F32x4\000" |
| 4806 | /* 8089 */ "SQRT_F32x4\000" |
| 4807 | /* 8100 */ "NEAREST_F32x4\000" |
| 4808 | /* 8114 */ "DIV_F32x4\000" |
| 4809 | /* 8124 */ "SIMD_RELAXED_FMAX_F32x4\000" |
| 4810 | /* 8148 */ "PMAX_F32x4\000" |
| 4811 | /* 8159 */ "demote_zero_F32x4\000" |
| 4812 | /* 8177 */ "sint_to_fp_F32x4\000" |
| 4813 | /* 8194 */ "uint_to_fp_F32x4\000" |
| 4814 | /* 8211 */ "promote_low_F32x4\000" |
| 4815 | /* 8229 */ "CONST_V128_I32x4\000" |
| 4816 | /* 8246 */ "SUB_I32x4\000" |
| 4817 | /* 8256 */ "ADD_I32x4\000" |
| 4818 | /* 8266 */ "REPLACE_LANE_I32x4\000" |
| 4819 | /* 8285 */ "EXTRACT_LANE_I32x4\000" |
| 4820 | /* 8304 */ "ALLTRUE_I32x4\000" |
| 4821 | /* 8318 */ "NEG_I32x4\000" |
| 4822 | /* 8328 */ "BITMASK_I32x4\000" |
| 4823 | /* 8342 */ "SHL_I32x4\000" |
| 4824 | /* 8352 */ "MUL_I32x4\000" |
| 4825 | /* 8362 */ "EQ_I32x4\000" |
| 4826 | /* 8371 */ "ABS_I32x4\000" |
| 4827 | /* 8381 */ "GE_S_I32x4\000" |
| 4828 | /* 8392 */ "LE_S_I32x4\000" |
| 4829 | /* 8403 */ "EXTMUL_HIGH_S_I32x4\000" |
| 4830 | /* 8423 */ "MIN_S_I32x4\000" |
| 4831 | /* 8435 */ "SHR_S_I32x4\000" |
| 4832 | /* 8447 */ "GT_S_I32x4\000" |
| 4833 | /* 8458 */ "LT_S_I32x4\000" |
| 4834 | /* 8469 */ "EXTMUL_LOW_S_I32x4\000" |
| 4835 | /* 8488 */ "MAX_S_I32x4\000" |
| 4836 | /* 8500 */ "SPLAT_I32x4\000" |
| 4837 | /* 8512 */ "LANESELECT_I32x4\000" |
| 4838 | /* 8529 */ "GE_U_I32x4\000" |
| 4839 | /* 8540 */ "LE_U_I32x4\000" |
| 4840 | /* 8551 */ "EXTMUL_HIGH_U_I32x4\000" |
| 4841 | /* 8571 */ "MIN_U_I32x4\000" |
| 4842 | /* 8583 */ "SHR_U_I32x4\000" |
| 4843 | /* 8595 */ "GT_U_I32x4\000" |
| 4844 | /* 8606 */ "LT_U_I32x4\000" |
| 4845 | /* 8617 */ "EXTMUL_LOW_U_I32x4\000" |
| 4846 | /* 8636 */ "MAX_U_I32x4\000" |
| 4847 | /* 8648 */ "int_wasm_relaxed_trunc_signed_I32x4\000" |
| 4848 | /* 8684 */ "int_wasm_relaxed_trunc_unsigned_I32x4\000" |
| 4849 | /* 8722 */ "int_wasm_relaxed_trunc_signed_zero_I32x4\000" |
| 4850 | /* 8763 */ "int_wasm_relaxed_trunc_unsigned_zero_I32x4\000" |
| 4851 | /* 8806 */ "extadd_pairwise_s_I32x4\000" |
| 4852 | /* 8830 */ "extend_high_s_I32x4\000" |
| 4853 | /* 8850 */ "trunc_sat_zero_s_I32x4\000" |
| 4854 | /* 8873 */ "extend_low_s_I32x4\000" |
| 4855 | /* 8892 */ "fp_to_sint_I32x4\000" |
| 4856 | /* 8909 */ "fp_to_uint_I32x4\000" |
| 4857 | /* 8926 */ "extadd_pairwise_u_I32x4\000" |
| 4858 | /* 8950 */ "extend_high_u_I32x4\000" |
| 4859 | /* 8970 */ "trunc_sat_zero_u_I32x4\000" |
| 4860 | /* 8993 */ "extend_low_u_I32x4\000" |
| 4861 | /* 9012 */ "ARGUMENT_v8f16\000" |
| 4862 | /* 9027 */ "ARGUMENT_v8i16\000" |
| 4863 | /* 9042 */ "CONST_V128_I8x16\000" |
| 4864 | /* 9059 */ "SUB_I8x16\000" |
| 4865 | /* 9069 */ "ADD_I8x16\000" |
| 4866 | /* 9079 */ "REPLACE_LANE_I8x16\000" |
| 4867 | /* 9098 */ "ALLTRUE_I8x16\000" |
| 4868 | /* 9112 */ "NEG_I8x16\000" |
| 4869 | /* 9122 */ "BITMASK_I8x16\000" |
| 4870 | /* 9136 */ "SHL_I8x16\000" |
| 4871 | /* 9146 */ "EQ_I8x16\000" |
| 4872 | /* 9155 */ "ABS_I8x16\000" |
| 4873 | /* 9165 */ "GE_S_I8x16\000" |
| 4874 | /* 9176 */ "LE_S_I8x16\000" |
| 4875 | /* 9187 */ "MIN_S_I8x16\000" |
| 4876 | /* 9199 */ "SHR_S_I8x16\000" |
| 4877 | /* 9211 */ "SUB_SAT_S_I8x16\000" |
| 4878 | /* 9227 */ "ADD_SAT_S_I8x16\000" |
| 4879 | /* 9243 */ "GT_S_I8x16\000" |
| 4880 | /* 9254 */ "LT_S_I8x16\000" |
| 4881 | /* 9265 */ "NARROW_S_I8x16\000" |
| 4882 | /* 9280 */ "MAX_S_I8x16\000" |
| 4883 | /* 9292 */ "SPLAT_I8x16\000" |
| 4884 | /* 9304 */ "LANESELECT_I8x16\000" |
| 4885 | /* 9321 */ "POPCNT_I8x16\000" |
| 4886 | /* 9334 */ "GE_U_I8x16\000" |
| 4887 | /* 9345 */ "LE_U_I8x16\000" |
| 4888 | /* 9356 */ "MIN_U_I8x16\000" |
| 4889 | /* 9368 */ "AVGR_U_I8x16\000" |
| 4890 | /* 9381 */ "SHR_U_I8x16\000" |
| 4891 | /* 9393 */ "SUB_SAT_U_I8x16\000" |
| 4892 | /* 9409 */ "ADD_SAT_U_I8x16\000" |
| 4893 | /* 9425 */ "GT_U_I8x16\000" |
| 4894 | /* 9436 */ "LT_U_I8x16\000" |
| 4895 | /* 9447 */ "NARROW_U_I8x16\000" |
| 4896 | /* 9462 */ "MAX_U_I8x16\000" |
| 4897 | /* 9474 */ "I64_SUB128\000" |
| 4898 | /* 9485 */ "I64_ADD128\000" |
| 4899 | /* 9496 */ "LOCAL_TEE_V128\000" |
| 4900 | /* 9511 */ "DROP_V128\000" |
| 4901 | /* 9521 */ "SELECT_V128\000" |
| 4902 | /* 9533 */ "GLOBAL_GET_V128\000" |
| 4903 | /* 9549 */ "LOCAL_GET_V128\000" |
| 4904 | /* 9564 */ "GLOBAL_SET_V128\000" |
| 4905 | /* 9580 */ "LOCAL_SET_V128\000" |
| 4906 | /* 9595 */ "COPY_V128\000" |
| 4907 | /* 9605 */ "ARGUMENT_v16i8\000" |
| 4908 | /* 9620 */ "SUB_F16x8\000" |
| 4909 | /* 9630 */ "TRUNC_F16x8\000" |
| 4910 | /* 9642 */ "NMADD_F16x8\000" |
| 4911 | /* 9654 */ "GE_F16x8\000" |
| 4912 | /* 9663 */ "LE_F16x8\000" |
| 4913 | /* 9672 */ "REPLACE_LANE_F16x8\000" |
| 4914 | /* 9691 */ "EXTRACT_LANE_F16x8\000" |
| 4915 | /* 9710 */ "NEG_F16x8\000" |
| 4916 | /* 9720 */ "CEIL_F16x8\000" |
| 4917 | /* 9731 */ "MUL_F16x8\000" |
| 4918 | /* 9741 */ "PMIN_F16x8\000" |
| 4919 | /* 9752 */ "EQ_F16x8\000" |
| 4920 | /* 9761 */ "FLOOR_F16x8\000" |
| 4921 | /* 9773 */ "ABS_F16x8\000" |
| 4922 | /* 9783 */ "SPLAT_F16x8\000" |
| 4923 | /* 9795 */ "GT_F16x8\000" |
| 4924 | /* 9804 */ "LT_F16x8\000" |
| 4925 | /* 9813 */ "SQRT_F16x8\000" |
| 4926 | /* 9824 */ "NEAREST_F16x8\000" |
| 4927 | /* 9838 */ "DIV_F16x8\000" |
| 4928 | /* 9848 */ "PMAX_F16x8\000" |
| 4929 | /* 9859 */ "demote_zero_F16x8\000" |
| 4930 | /* 9877 */ "sint_to_fp_F16x8\000" |
| 4931 | /* 9894 */ "uint_to_fp_F16x8\000" |
| 4932 | /* 9911 */ "CONST_V128_I16x8\000" |
| 4933 | /* 9928 */ "SUB_I16x8\000" |
| 4934 | /* 9938 */ "ADD_I16x8\000" |
| 4935 | /* 9948 */ "REPLACE_LANE_I16x8\000" |
| 4936 | /* 9967 */ "ALLTRUE_I16x8\000" |
| 4937 | /* 9981 */ "NEG_I16x8\000" |
| 4938 | /* 9991 */ "BITMASK_I16x8\000" |
| 4939 | /* 10005 */ "SHL_I16x8\000" |
| 4940 | /* 10015 */ "MUL_I16x8\000" |
| 4941 | /* 10025 */ "EQ_I16x8\000" |
| 4942 | /* 10034 */ "ABS_I16x8\000" |
| 4943 | /* 10044 */ "GE_S_I16x8\000" |
| 4944 | /* 10055 */ "LE_S_I16x8\000" |
| 4945 | /* 10066 */ "EXTMUL_HIGH_S_I16x8\000" |
| 4946 | /* 10086 */ "MIN_S_I16x8\000" |
| 4947 | /* 10098 */ "SHR_S_I16x8\000" |
| 4948 | /* 10110 */ "RELAXED_Q15MULR_S_I16x8\000" |
| 4949 | /* 10134 */ "SUB_SAT_S_I16x8\000" |
| 4950 | /* 10150 */ "ADD_SAT_S_I16x8\000" |
| 4951 | /* 10166 */ "Q15MULR_SAT_S_I16x8\000" |
| 4952 | /* 10186 */ "GT_S_I16x8\000" |
| 4953 | /* 10197 */ "LT_S_I16x8\000" |
| 4954 | /* 10208 */ "EXTMUL_LOW_S_I16x8\000" |
| 4955 | /* 10227 */ "NARROW_S_I16x8\000" |
| 4956 | /* 10242 */ "MAX_S_I16x8\000" |
| 4957 | /* 10254 */ "SPLAT_I16x8\000" |
| 4958 | /* 10266 */ "LANESELECT_I16x8\000" |
| 4959 | /* 10283 */ "GE_U_I16x8\000" |
| 4960 | /* 10294 */ "LE_U_I16x8\000" |
| 4961 | /* 10305 */ "EXTMUL_HIGH_U_I16x8\000" |
| 4962 | /* 10325 */ "MIN_U_I16x8\000" |
| 4963 | /* 10337 */ "AVGR_U_I16x8\000" |
| 4964 | /* 10350 */ "SHR_U_I16x8\000" |
| 4965 | /* 10362 */ "SUB_SAT_U_I16x8\000" |
| 4966 | /* 10378 */ "ADD_SAT_U_I16x8\000" |
| 4967 | /* 10394 */ "GT_U_I16x8\000" |
| 4968 | /* 10405 */ "LT_U_I16x8\000" |
| 4969 | /* 10416 */ "EXTMUL_LOW_U_I16x8\000" |
| 4970 | /* 10435 */ "NARROW_U_I16x8\000" |
| 4971 | /* 10450 */ "MAX_U_I16x8\000" |
| 4972 | /* 10462 */ "extadd_pairwise_s_I16x8\000" |
| 4973 | /* 10486 */ "extend_high_s_I16x8\000" |
| 4974 | /* 10506 */ "extend_low_s_I16x8\000" |
| 4975 | /* 10525 */ "fp_to_sint_I16x8\000" |
| 4976 | /* 10542 */ "fp_to_uint_I16x8\000" |
| 4977 | /* 10559 */ "extadd_pairwise_u_I16x8\000" |
| 4978 | /* 10583 */ "extend_high_u_I16x8\000" |
| 4979 | /* 10603 */ "extend_low_u_I16x8\000" |
| 4980 | /* 10622 */ "G_FMA\000" |
| 4981 | /* 10628 */ "G_STRICT_FMA\000" |
| 4982 | /* 10641 */ "G_FSUB\000" |
| 4983 | /* 10648 */ "G_STRICT_FSUB\000" |
| 4984 | /* 10662 */ "G_ATOMICRMW_FSUB\000" |
| 4985 | /* 10679 */ "G_SUB\000" |
| 4986 | /* 10685 */ "G_ATOMICRMW_SUB\000" |
| 4987 | /* 10701 */ "G_INTRINSIC\000" |
| 4988 | /* 10713 */ "REF_FUNC\000" |
| 4989 | /* 10722 */ "G_FPTRUNC\000" |
| 4990 | /* 10732 */ "G_INTRINSIC_TRUNC\000" |
| 4991 | /* 10750 */ "G_TRUNC\000" |
| 4992 | /* 10758 */ "G_BUILD_VECTOR_TRUNC\000" |
| 4993 | /* 10779 */ "G_DYN_STACKALLOC\000" |
| 4994 | /* 10796 */ "G_FMAD\000" |
| 4995 | /* 10803 */ "G_FPEXTLOAD\000" |
| 4996 | /* 10815 */ "G_INDEXED_SEXTLOAD\000" |
| 4997 | /* 10834 */ "G_SEXTLOAD\000" |
| 4998 | /* 10845 */ "G_INDEXED_ZEXTLOAD\000" |
| 4999 | /* 10864 */ "G_ZEXTLOAD\000" |
| 5000 | /* 10875 */ "G_INDEXED_LOAD\000" |
| 5001 | /* 10890 */ "G_LOAD\000" |
| 5002 | /* 10897 */ "G_VECREDUCE_FADD\000" |
| 5003 | /* 10914 */ "G_FADD\000" |
| 5004 | /* 10921 */ "G_VECREDUCE_SEQ_FADD\000" |
| 5005 | /* 10942 */ "G_STRICT_FADD\000" |
| 5006 | /* 10956 */ "G_ATOMICRMW_FADD\000" |
| 5007 | /* 10973 */ "G_VECREDUCE_ADD\000" |
| 5008 | /* 10989 */ "G_ADD\000" |
| 5009 | /* 10995 */ "G_PTR_ADD\000" |
| 5010 | /* 11005 */ "RELAXED_DOT_ADD\000" |
| 5011 | /* 11021 */ "G_ATOMICRMW_ADD\000" |
| 5012 | /* 11037 */ "G_ATOMICRMW_NAND\000" |
| 5013 | /* 11054 */ "G_VECREDUCE_AND\000" |
| 5014 | /* 11070 */ "G_AND\000" |
| 5015 | /* 11076 */ "G_ATOMICRMW_AND\000" |
| 5016 | /* 11092 */ "LIFETIME_END\000" |
| 5017 | /* 11105 */ "G_BRCOND\000" |
| 5018 | /* 11114 */ "G_ATOMICRMW_USUB_COND\000" |
| 5019 | /* 11136 */ "G_LLROUND\000" |
| 5020 | /* 11146 */ "G_LROUND\000" |
| 5021 | /* 11155 */ "G_INTRINSIC_ROUND\000" |
| 5022 | /* 11173 */ "G_INTRINSIC_FPTRUNC_ROUND\000" |
| 5023 | /* 11199 */ "LOAD_STACK_GUARD\000" |
| 5024 | /* 11216 */ "PSEUDO_PROBE\000" |
| 5025 | /* 11229 */ "G_SSUBE\000" |
| 5026 | /* 11237 */ "G_USUBE\000" |
| 5027 | /* 11245 */ "ATOMIC_FENCE\000" |
| 5028 | /* 11258 */ "G_FENCE\000" |
| 5029 | /* 11266 */ "ARITH_FENCE\000" |
| 5030 | /* 11278 */ "COMPILER_FENCE\000" |
| 5031 | /* 11293 */ "REG_SEQUENCE\000" |
| 5032 | /* 11306 */ "G_SADDE\000" |
| 5033 | /* 11314 */ "G_UADDE\000" |
| 5034 | /* 11322 */ "G_GET_FPMODE\000" |
| 5035 | /* 11335 */ "G_RESET_FPMODE\000" |
| 5036 | /* 11350 */ "G_SET_FPMODE\000" |
| 5037 | /* 11363 */ "G_FMINNUM_IEEE\000" |
| 5038 | /* 11378 */ "G_FMAXNUM_IEEE\000" |
| 5039 | /* 11393 */ "G_VSCALE\000" |
| 5040 | /* 11402 */ "DEBUG_UNREACHABLE\000" |
| 5041 | /* 11420 */ "G_JUMP_TABLE\000" |
| 5042 | /* 11433 */ "END_TRY_TABLE\000" |
| 5043 | /* 11447 */ "BUNDLE\000" |
| 5044 | /* 11454 */ "SHUFFLE\000" |
| 5045 | /* 11462 */ "RELAXED_SWIZZLE\000" |
| 5046 | /* 11478 */ "G_MEMSET_INLINE\000" |
| 5047 | /* 11494 */ "G_MEMCPY_INLINE\000" |
| 5048 | /* 11510 */ "RELOC_NONE\000" |
| 5049 | /* 11521 */ "LOCAL_ESCAPE\000" |
| 5050 | /* 11534 */ "G_FPTRUNCSTORE\000" |
| 5051 | /* 11549 */ "G_STACKRESTORE\000" |
| 5052 | /* 11564 */ "G_INDEXED_STORE\000" |
| 5053 | /* 11580 */ "G_STORE\000" |
| 5054 | /* 11588 */ "ELSE\000" |
| 5055 | /* 11593 */ "G_BITREVERSE\000" |
| 5056 | /* 11606 */ "FAKE_USE\000" |
| 5057 | /* 11615 */ "DELEGATE\000" |
| 5058 | /* 11624 */ "DBG_VALUE\000" |
| 5059 | /* 11634 */ "G_GLOBAL_VALUE\000" |
| 5060 | /* 11649 */ "G_PTRAUTH_GLOBAL_VALUE\000" |
| 5061 | /* 11672 */ "CONVERGENCECTRL_GLUE\000" |
| 5062 | /* 11693 */ "ANYTRUE\000" |
| 5063 | /* 11701 */ "G_STACKSAVE\000" |
| 5064 | /* 11713 */ "G_MEMMOVE\000" |
| 5065 | /* 11723 */ "G_FREEZE\000" |
| 5066 | /* 11732 */ "G_FCANONICALIZE\000" |
| 5067 | /* 11748 */ "TABLE_SIZE\000" |
| 5068 | /* 11759 */ "G_FMODF\000" |
| 5069 | /* 11767 */ "INIT_UNDEF\000" |
| 5070 | /* 11778 */ "G_IMPLICIT_DEF\000" |
| 5071 | /* 11793 */ "LOCAL_TEE_FUNCREF\000" |
| 5072 | /* 11811 */ "TABLE_FILL_FUNCREF\000" |
| 5073 | /* 11830 */ "REF_NULL_FUNCREF\000" |
| 5074 | /* 11847 */ "REF_IS_NULL_FUNCREF\000" |
| 5075 | /* 11867 */ "DROP_FUNCREF\000" |
| 5076 | /* 11880 */ "SELECT_FUNCREF\000" |
| 5077 | /* 11895 */ "TABLE_GET_FUNCREF\000" |
| 5078 | /* 11913 */ "GLOBAL_GET_FUNCREF\000" |
| 5079 | /* 11932 */ "LOCAL_GET_FUNCREF\000" |
| 5080 | /* 11950 */ "TABLE_SET_FUNCREF\000" |
| 5081 | /* 11968 */ "GLOBAL_SET_FUNCREF\000" |
| 5082 | /* 11987 */ "LOCAL_SET_FUNCREF\000" |
| 5083 | /* 12005 */ "REF_CAST_FUNCREF\000" |
| 5084 | /* 12022 */ "REF_TEST_FUNCREF\000" |
| 5085 | /* 12039 */ "TABLE_GROW_FUNCREF\000" |
| 5086 | /* 12058 */ "COPY_FUNCREF\000" |
| 5087 | /* 12071 */ "LOCAL_TEE_EXTERNREF\000" |
| 5088 | /* 12091 */ "TABLE_FILL_EXTERNREF\000" |
| 5089 | /* 12112 */ "REF_NULL_EXTERNREF\000" |
| 5090 | /* 12131 */ "REF_IS_NULL_EXTERNREF\000" |
| 5091 | /* 12153 */ "DROP_EXTERNREF\000" |
| 5092 | /* 12168 */ "SELECT_EXTERNREF\000" |
| 5093 | /* 12185 */ "TABLE_GET_EXTERNREF\000" |
| 5094 | /* 12205 */ "GLOBAL_GET_EXTERNREF\000" |
| 5095 | /* 12226 */ "LOCAL_GET_EXTERNREF\000" |
| 5096 | /* 12246 */ "TABLE_SET_EXTERNREF\000" |
| 5097 | /* 12266 */ "GLOBAL_SET_EXTERNREF\000" |
| 5098 | /* 12287 */ "LOCAL_SET_EXTERNREF\000" |
| 5099 | /* 12307 */ "TABLE_GROW_EXTERNREF\000" |
| 5100 | /* 12328 */ "COPY_EXTERNREF\000" |
| 5101 | /* 12343 */ "LOCAL_TEE_EXNREF\000" |
| 5102 | /* 12360 */ "TABLE_FILL_EXNREF\000" |
| 5103 | /* 12378 */ "REF_NULL_EXNREF\000" |
| 5104 | /* 12394 */ "REF_IS_NULL_EXNREF\000" |
| 5105 | /* 12413 */ "DROP_EXNREF\000" |
| 5106 | /* 12425 */ "SELECT_EXNREF\000" |
| 5107 | /* 12439 */ "TABLE_GET_EXNREF\000" |
| 5108 | /* 12456 */ "GLOBAL_GET_EXNREF\000" |
| 5109 | /* 12474 */ "LOCAL_GET_EXNREF\000" |
| 5110 | /* 12491 */ "TABLE_SET_EXNREF\000" |
| 5111 | /* 12508 */ "GLOBAL_SET_EXNREF\000" |
| 5112 | /* 12526 */ "LOCAL_SET_EXNREF\000" |
| 5113 | /* 12543 */ "TABLE_GROW_EXNREF\000" |
| 5114 | /* 12561 */ "COPY_EXNREF\000" |
| 5115 | /* 12573 */ "CATCH_REF\000" |
| 5116 | /* 12583 */ "RET_CALL_REF\000" |
| 5117 | /* 12596 */ "CATCH_ALL_REF\000" |
| 5118 | /* 12610 */ "DBG_INSTR_REF\000" |
| 5119 | /* 12624 */ "THROW_REF\000" |
| 5120 | /* 12634 */ "END_IF\000" |
| 5121 | /* 12641 */ "BR_IF\000" |
| 5122 | /* 12647 */ "G_FNEG\000" |
| 5123 | /* 12654 */ "EXTRACT_SUBREG\000" |
| 5124 | /* 12669 */ "INSERT_SUBREG\000" |
| 5125 | /* 12683 */ "G_SEXT_INREG\000" |
| 5126 | /* 12696 */ "SUBREG_TO_REG\000" |
| 5127 | /* 12710 */ "G_ATOMIC_CMPXCHG\000" |
| 5128 | /* 12727 */ "G_ATOMICRMW_XCHG\000" |
| 5129 | /* 12744 */ "G_GET_ROUNDING\000" |
| 5130 | /* 12759 */ "G_SET_ROUNDING\000" |
| 5131 | /* 12774 */ "G_FLOG\000" |
| 5132 | /* 12781 */ "G_VAARG\000" |
| 5133 | /* 12789 */ "PREALLOCATED_ARG\000" |
| 5134 | /* 12806 */ "CATCH\000" |
| 5135 | /* 12812 */ "G_PREFETCH\000" |
| 5136 | /* 12823 */ "G_CLMULH\000" |
| 5137 | /* 12832 */ "G_SMULH\000" |
| 5138 | /* 12840 */ "G_UMULH\000" |
| 5139 | /* 12848 */ "G_FTANH\000" |
| 5140 | /* 12856 */ "G_FSINH\000" |
| 5141 | /* 12864 */ "G_FCOSH\000" |
| 5142 | /* 12872 */ "DBG_PHI\000" |
| 5143 | /* 12880 */ "G_FPTOSI\000" |
| 5144 | /* 12889 */ "G_FPTOUI\000" |
| 5145 | /* 12898 */ "G_FPOWI\000" |
| 5146 | /* 12906 */ "END_BLOCK\000" |
| 5147 | /* 12916 */ "COPY_LANEMASK\000" |
| 5148 | /* 12930 */ "G_PTRMASK\000" |
| 5149 | /* 12940 */ "GC_LABEL\000" |
| 5150 | /* 12949 */ "DBG_LABEL\000" |
| 5151 | /* 12959 */ "EH_LABEL\000" |
| 5152 | /* 12968 */ "ANNOTATION_LABEL\000" |
| 5153 | /* 12985 */ "ICALL_BRANCH_FUNNEL\000" |
| 5154 | /* 13005 */ "G_FSHL\000" |
| 5155 | /* 13012 */ "G_SHL\000" |
| 5156 | /* 13018 */ "G_FCEIL\000" |
| 5157 | /* 13026 */ "G_SAVGCEIL\000" |
| 5158 | /* 13037 */ "G_UAVGCEIL\000" |
| 5159 | /* 13048 */ "PATCHABLE_TAIL_CALL\000" |
| 5160 | /* 13068 */ "RET_CALL\000" |
| 5161 | /* 13077 */ "PATCHABLE_TYPED_EVENT_CALL\000" |
| 5162 | /* 13104 */ "PATCHABLE_EVENT_CALL\000" |
| 5163 | /* 13125 */ "FENTRY_CALL\000" |
| 5164 | /* 13137 */ "CATCH_ALL\000" |
| 5165 | /* 13147 */ "KILL\000" |
| 5166 | /* 13152 */ "G_CONSTANT_POOL\000" |
| 5167 | /* 13168 */ "G_ROTL\000" |
| 5168 | /* 13175 */ "G_VECREDUCE_FMUL\000" |
| 5169 | /* 13192 */ "G_FMUL\000" |
| 5170 | /* 13199 */ "G_VECREDUCE_SEQ_FMUL\000" |
| 5171 | /* 13220 */ "G_STRICT_FMUL\000" |
| 5172 | /* 13234 */ "G_CLMUL\000" |
| 5173 | /* 13242 */ "G_VECREDUCE_MUL\000" |
| 5174 | /* 13258 */ "G_MUL\000" |
| 5175 | /* 13264 */ "G_FREM\000" |
| 5176 | /* 13271 */ "G_STRICT_FREM\000" |
| 5177 | /* 13285 */ "G_SREM\000" |
| 5178 | /* 13292 */ "G_UREM\000" |
| 5179 | /* 13299 */ "G_SDIVREM\000" |
| 5180 | /* 13309 */ "G_UDIVREM\000" |
| 5181 | /* 13319 */ "INLINEASM\000" |
| 5182 | /* 13329 */ "G_VECREDUCE_FMINIMUM\000" |
| 5183 | /* 13350 */ "G_FMINIMUM\000" |
| 5184 | /* 13361 */ "G_ATOMICRMW_FMINIMUM\000" |
| 5185 | /* 13382 */ "G_VECREDUCE_FMAXIMUM\000" |
| 5186 | /* 13403 */ "G_FMAXIMUM\000" |
| 5187 | /* 13414 */ "G_ATOMICRMW_FMAXIMUM\000" |
| 5188 | /* 13435 */ "G_VECREDUCE_FMINIMUMNUM\000" |
| 5189 | /* 13459 */ "G_FMINIMUMNUM\000" |
| 5190 | /* 13473 */ "G_ATOMICRMW_FMINIMUMNUM\000" |
| 5191 | /* 13497 */ "G_VECREDUCE_FMAXIMUMNUM\000" |
| 5192 | /* 13521 */ "G_FMAXIMUMNUM\000" |
| 5193 | /* 13535 */ "G_ATOMICRMW_FMAXIMUMNUM\000" |
| 5194 | /* 13559 */ "G_FMINNUM\000" |
| 5195 | /* 13569 */ "G_FMAXNUM\000" |
| 5196 | /* 13579 */ "G_FATAN\000" |
| 5197 | /* 13587 */ "G_FTAN\000" |
| 5198 | /* 13594 */ "G_INTRINSIC_ROUNDEVEN\000" |
| 5199 | /* 13616 */ "G_ASSERT_ALIGN\000" |
| 5200 | /* 13631 */ "G_FCOPYSIGN\000" |
| 5201 | /* 13643 */ "G_VECREDUCE_FMIN\000" |
| 5202 | /* 13660 */ "G_ATOMICRMW_FMIN\000" |
| 5203 | /* 13677 */ "G_VECREDUCE_SMIN\000" |
| 5204 | /* 13694 */ "G_SMIN\000" |
| 5205 | /* 13701 */ "G_VECREDUCE_UMIN\000" |
| 5206 | /* 13718 */ "G_UMIN\000" |
| 5207 | /* 13725 */ "G_ATOMICRMW_UMIN\000" |
| 5208 | /* 13742 */ "G_ATOMICRMW_MIN\000" |
| 5209 | /* 13758 */ "G_FASIN\000" |
| 5210 | /* 13766 */ "G_FSIN\000" |
| 5211 | /* 13773 */ "END_FUNCTION\000" |
| 5212 | /* 13786 */ "CFI_INSTRUCTION\000" |
| 5213 | /* 13802 */ "G_CTLZ_ZERO_POISON\000" |
| 5214 | /* 13821 */ "G_CTTZ_ZERO_POISON\000" |
| 5215 | /* 13840 */ "FALLTHROUGH_RETURN\000" |
| 5216 | /* 13859 */ "ADJCALLSTACKDOWN\000" |
| 5217 | /* 13876 */ "G_SSUBO\000" |
| 5218 | /* 13884 */ "G_USUBO\000" |
| 5219 | /* 13892 */ "G_SADDO\000" |
| 5220 | /* 13900 */ "G_UADDO\000" |
| 5221 | /* 13908 */ "JUMP_TABLE_DEBUG_INFO\000" |
| 5222 | /* 13930 */ "G_SMULO\000" |
| 5223 | /* 13938 */ "G_UMULO\000" |
| 5224 | /* 13946 */ "G_BZERO\000" |
| 5225 | /* 13954 */ "STACKMAP\000" |
| 5226 | /* 13963 */ "G_DEBUGTRAP\000" |
| 5227 | /* 13975 */ "G_UBSANTRAP\000" |
| 5228 | /* 13987 */ "G_TRAP\000" |
| 5229 | /* 13994 */ "G_ATOMICRMW_UDEC_WRAP\000" |
| 5230 | /* 14016 */ "G_ATOMICRMW_UINC_WRAP\000" |
| 5231 | /* 14038 */ "G_BSWAP\000" |
| 5232 | /* 14046 */ "G_SITOFP\000" |
| 5233 | /* 14055 */ "G_UITOFP\000" |
| 5234 | /* 14064 */ "G_FCMP\000" |
| 5235 | /* 14071 */ "G_STRICT_FCMP\000" |
| 5236 | /* 14085 */ "G_ICMP\000" |
| 5237 | /* 14092 */ "G_SCMP\000" |
| 5238 | /* 14099 */ "G_UCMP\000" |
| 5239 | /* 14106 */ "NOP\000" |
| 5240 | /* 14110 */ "END_LOOP\000" |
| 5241 | /* 14119 */ "CONVERGENCECTRL_LOOP\000" |
| 5242 | /* 14140 */ "G_CTPOP\000" |
| 5243 | /* 14148 */ "DATA_DROP\000" |
| 5244 | /* 14158 */ "PATCHABLE_OP\000" |
| 5245 | /* 14171 */ "FAULTING_OP\000" |
| 5246 | /* 14183 */ "ADJCALLSTACKUP\000" |
| 5247 | /* 14198 */ "PREALLOCATED_SETUP\000" |
| 5248 | /* 14217 */ "G_FLDEXP\000" |
| 5249 | /* 14226 */ "G_STRICT_FLDEXP\000" |
| 5250 | /* 14242 */ "G_FEXP\000" |
| 5251 | /* 14249 */ "G_FFREXP\000" |
| 5252 | /* 14258 */ "G_BR\000" |
| 5253 | /* 14263 */ "INLINEASM_BR\000" |
| 5254 | /* 14276 */ "G_BLOCK_ADDR\000" |
| 5255 | /* 14289 */ "MEMBARRIER\000" |
| 5256 | /* 14300 */ "G_CONSTANT_FOLD_BARRIER\000" |
| 5257 | /* 14324 */ "PATCHABLE_FUNCTION_ENTER\000" |
| 5258 | /* 14349 */ "G_READCYCLECOUNTER\000" |
| 5259 | /* 14368 */ "G_READSTEADYCOUNTER\000" |
| 5260 | /* 14388 */ "G_READ_REGISTER\000" |
| 5261 | /* 14404 */ "G_WRITE_REGISTER\000" |
| 5262 | /* 14421 */ "G_ASHR\000" |
| 5263 | /* 14428 */ "G_FSHR\000" |
| 5264 | /* 14435 */ "G_LSHR\000" |
| 5265 | /* 14442 */ "G_CLMULR\000" |
| 5266 | /* 14451 */ "CONVERGENCECTRL_ANCHOR\000" |
| 5267 | /* 14474 */ "G_FFLOOR\000" |
| 5268 | /* 14483 */ "G_SAVGFLOOR\000" |
| 5269 | /* 14495 */ "G_UAVGFLOOR\000" |
| 5270 | /* 14507 */ "G_EXTRACT_SUBVECTOR\000" |
| 5271 | /* 14527 */ "G_INSERT_SUBVECTOR\000" |
| 5272 | /* 14546 */ "G_BUILD_VECTOR\000" |
| 5273 | /* 14561 */ "G_SHUFFLE_VECTOR\000" |
| 5274 | /* 14578 */ "G_STEP_VECTOR\000" |
| 5275 | /* 14592 */ "G_SPLAT_VECTOR\000" |
| 5276 | /* 14607 */ "G_VECREDUCE_XOR\000" |
| 5277 | /* 14623 */ "G_XOR\000" |
| 5278 | /* 14629 */ "G_ATOMICRMW_XOR\000" |
| 5279 | /* 14645 */ "G_VECREDUCE_OR\000" |
| 5280 | /* 14660 */ "G_OR\000" |
| 5281 | /* 14665 */ "G_ATOMICRMW_OR\000" |
| 5282 | /* 14680 */ "G_ROTR\000" |
| 5283 | /* 14687 */ "G_INTTOPTR\000" |
| 5284 | /* 14698 */ "G_FABS\000" |
| 5285 | /* 14705 */ "G_ABS\000" |
| 5286 | /* 14711 */ "G_ABDS\000" |
| 5287 | /* 14718 */ "G_UNMERGE_VALUES\000" |
| 5288 | /* 14735 */ "G_MERGE_VALUES\000" |
| 5289 | /* 14750 */ "G_CTLS\000" |
| 5290 | /* 14757 */ "RET_CALL_PARAMS\000" |
| 5291 | /* 14773 */ "G_FACOS\000" |
| 5292 | /* 14781 */ "G_FCOS\000" |
| 5293 | /* 14788 */ "G_FSINCOS\000" |
| 5294 | /* 14798 */ "G_STRICT_FCMPS\000" |
| 5295 | /* 14813 */ "G_CONCAT_VECTORS\000" |
| 5296 | /* 14830 */ "COPY_TO_REGCLASS\000" |
| 5297 | /* 14847 */ "G_IS_FPCLASS\000" |
| 5298 | /* 14860 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000" |
| 5299 | /* 14890 */ "BR_UNLESS\000" |
| 5300 | /* 14900 */ "G_VECTOR_COMPRESS\000" |
| 5301 | /* 14918 */ "G_INTRINSIC_W_SIDE_EFFECTS\000" |
| 5302 | /* 14945 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000" |
| 5303 | /* 14983 */ "RET_CALL_RESULTS\000" |
| 5304 | /* 15000 */ "LOAD_F16_F32_A32_S\000" |
| 5305 | /* 15019 */ "STORE_F16_F32_A32_S\000" |
| 5306 | /* 15039 */ "LOAD_F32_A32_S\000" |
| 5307 | /* 15054 */ "STORE_F32_A32_S\000" |
| 5308 | /* 15070 */ "ATOMIC_STORE16_I32_A32_S\000" |
| 5309 | /* 15095 */ "ATOMIC_STORE8_I32_A32_S\000" |
| 5310 | /* 15119 */ "ATOMIC_RMW16_U_SUB_I32_A32_S\000" |
| 5311 | /* 15148 */ "ATOMIC_RMW8_U_SUB_I32_A32_S\000" |
| 5312 | /* 15176 */ "ATOMIC_RMW_SUB_I32_A32_S\000" |
| 5313 | /* 15201 */ "ATOMIC_LOAD_I32_A32_S\000" |
| 5314 | /* 15223 */ "ATOMIC_RMW16_U_ADD_I32_A32_S\000" |
| 5315 | /* 15252 */ "ATOMIC_RMW8_U_ADD_I32_A32_S\000" |
| 5316 | /* 15280 */ "ATOMIC_RMW_ADD_I32_A32_S\000" |
| 5317 | /* 15305 */ "ATOMIC_RMW16_U_AND_I32_A32_S\000" |
| 5318 | /* 15334 */ "ATOMIC_RMW8_U_AND_I32_A32_S\000" |
| 5319 | /* 15362 */ "ATOMIC_RMW_AND_I32_A32_S\000" |
| 5320 | /* 15387 */ "ATOMIC_STORE_I32_A32_S\000" |
| 5321 | /* 15410 */ "ATOMIC_RMW16_U_CMPXCHG_I32_A32_S\000" |
| 5322 | /* 15443 */ "ATOMIC_RMW8_U_CMPXCHG_I32_A32_S\000" |
| 5323 | /* 15475 */ "ATOMIC_RMW_CMPXCHG_I32_A32_S\000" |
| 5324 | /* 15504 */ "ATOMIC_RMW16_U_XCHG_I32_A32_S\000" |
| 5325 | /* 15534 */ "ATOMIC_RMW8_U_XCHG_I32_A32_S\000" |
| 5326 | /* 15563 */ "ATOMIC_RMW_XCHG_I32_A32_S\000" |
| 5327 | /* 15589 */ "ATOMIC_RMW16_U_XOR_I32_A32_S\000" |
| 5328 | /* 15618 */ "ATOMIC_RMW8_U_XOR_I32_A32_S\000" |
| 5329 | /* 15646 */ "ATOMIC_RMW_XOR_I32_A32_S\000" |
| 5330 | /* 15671 */ "ATOMIC_RMW16_U_OR_I32_A32_S\000" |
| 5331 | /* 15699 */ "ATOMIC_RMW8_U_OR_I32_A32_S\000" |
| 5332 | /* 15726 */ "ATOMIC_RMW_OR_I32_A32_S\000" |
| 5333 | /* 15750 */ "LOAD16_S_I32_A32_S\000" |
| 5334 | /* 15769 */ "LOAD8_S_I32_A32_S\000" |
| 5335 | /* 15787 */ "ATOMIC_LOAD16_U_I32_A32_S\000" |
| 5336 | /* 15813 */ "ATOMIC_LOAD8_U_I32_A32_S\000" |
| 5337 | /* 15838 */ "MEMORY_ATOMIC_WAIT32_A32_S\000" |
| 5338 | /* 15865 */ "LOAD_LANE_32_A32_S\000" |
| 5339 | /* 15884 */ "LOAD_ZERO_32_A32_S\000" |
| 5340 | /* 15903 */ "STORE_LANE_I64x2_A32_S\000" |
| 5341 | /* 15926 */ "LOAD_EXTEND_S_I64x2_A32_S\000" |
| 5342 | /* 15952 */ "LOAD_EXTEND_U_I64x2_A32_S\000" |
| 5343 | /* 15978 */ "LOAD_F64_A32_S\000" |
| 5344 | /* 15993 */ "STORE_F64_A32_S\000" |
| 5345 | /* 16009 */ "ATOMIC_STORE32_I64_A32_S\000" |
| 5346 | /* 16034 */ "ATOMIC_STORE16_I64_A32_S\000" |
| 5347 | /* 16059 */ "ATOMIC_STORE8_I64_A32_S\000" |
| 5348 | /* 16083 */ "ATOMIC_RMW32_U_SUB_I64_A32_S\000" |
| 5349 | /* 16112 */ "ATOMIC_RMW16_U_SUB_I64_A32_S\000" |
| 5350 | /* 16141 */ "ATOMIC_RMW8_U_SUB_I64_A32_S\000" |
| 5351 | /* 16169 */ "ATOMIC_RMW_SUB_I64_A32_S\000" |
| 5352 | /* 16194 */ "ATOMIC_LOAD_I64_A32_S\000" |
| 5353 | /* 16216 */ "ATOMIC_RMW32_U_ADD_I64_A32_S\000" |
| 5354 | /* 16245 */ "ATOMIC_RMW16_U_ADD_I64_A32_S\000" |
| 5355 | /* 16274 */ "ATOMIC_RMW8_U_ADD_I64_A32_S\000" |
| 5356 | /* 16302 */ "ATOMIC_RMW_ADD_I64_A32_S\000" |
| 5357 | /* 16327 */ "ATOMIC_RMW32_U_AND_I64_A32_S\000" |
| 5358 | /* 16356 */ "ATOMIC_RMW16_U_AND_I64_A32_S\000" |
| 5359 | /* 16385 */ "ATOMIC_RMW8_U_AND_I64_A32_S\000" |
| 5360 | /* 16413 */ "ATOMIC_RMW_AND_I64_A32_S\000" |
| 5361 | /* 16438 */ "ATOMIC_STORE_I64_A32_S\000" |
| 5362 | /* 16461 */ "ATOMIC_RMW32_U_CMPXCHG_I64_A32_S\000" |
| 5363 | /* 16494 */ "ATOMIC_RMW16_U_CMPXCHG_I64_A32_S\000" |
| 5364 | /* 16527 */ "ATOMIC_RMW8_U_CMPXCHG_I64_A32_S\000" |
| 5365 | /* 16559 */ "ATOMIC_RMW_CMPXCHG_I64_A32_S\000" |
| 5366 | /* 16588 */ "ATOMIC_RMW32_U_XCHG_I64_A32_S\000" |
| 5367 | /* 16618 */ "ATOMIC_RMW16_U_XCHG_I64_A32_S\000" |
| 5368 | /* 16648 */ "ATOMIC_RMW8_U_XCHG_I64_A32_S\000" |
| 5369 | /* 16677 */ "ATOMIC_RMW_XCHG_I64_A32_S\000" |
| 5370 | /* 16703 */ "ATOMIC_RMW32_U_XOR_I64_A32_S\000" |
| 5371 | /* 16732 */ "ATOMIC_RMW16_U_XOR_I64_A32_S\000" |
| 5372 | /* 16761 */ "ATOMIC_RMW8_U_XOR_I64_A32_S\000" |
| 5373 | /* 16789 */ "ATOMIC_RMW_XOR_I64_A32_S\000" |
| 5374 | /* 16814 */ "ATOMIC_RMW32_U_OR_I64_A32_S\000" |
| 5375 | /* 16842 */ "ATOMIC_RMW16_U_OR_I64_A32_S\000" |
| 5376 | /* 16870 */ "ATOMIC_RMW8_U_OR_I64_A32_S\000" |
| 5377 | /* 16897 */ "ATOMIC_RMW_OR_I64_A32_S\000" |
| 5378 | /* 16921 */ "LOAD32_S_I64_A32_S\000" |
| 5379 | /* 16940 */ "LOAD16_S_I64_A32_S\000" |
| 5380 | /* 16959 */ "LOAD8_S_I64_A32_S\000" |
| 5381 | /* 16977 */ "ATOMIC_LOAD32_U_I64_A32_S\000" |
| 5382 | /* 17003 */ "ATOMIC_LOAD16_U_I64_A32_S\000" |
| 5383 | /* 17029 */ "ATOMIC_LOAD8_U_I64_A32_S\000" |
| 5384 | /* 17054 */ "MEMORY_ATOMIC_WAIT64_A32_S\000" |
| 5385 | /* 17081 */ "LOAD_LANE_64_A32_S\000" |
| 5386 | /* 17100 */ "LOAD_ZERO_64_A32_S\000" |
| 5387 | /* 17119 */ "STORE_LANE_I32x4_A32_S\000" |
| 5388 | /* 17142 */ "LOAD_EXTEND_S_I32x4_A32_S\000" |
| 5389 | /* 17168 */ "LOAD_EXTEND_U_I32x4_A32_S\000" |
| 5390 | /* 17194 */ "LOAD_LANE_16_A32_S\000" |
| 5391 | /* 17213 */ "STORE_LANE_I8x16_A32_S\000" |
| 5392 | /* 17236 */ "LOAD_V128_A32_S\000" |
| 5393 | /* 17252 */ "STORE_V128_A32_S\000" |
| 5394 | /* 17269 */ "LOAD_LANE_8_A32_S\000" |
| 5395 | /* 17287 */ "STORE_LANE_I16x8_A32_S\000" |
| 5396 | /* 17310 */ "LOAD_EXTEND_S_I16x8_A32_S\000" |
| 5397 | /* 17336 */ "LOAD_EXTEND_U_I16x8_A32_S\000" |
| 5398 | /* 17362 */ "anonymous_14864MEMORY_SIZE_A32_S\000" |
| 5399 | /* 17395 */ "MEMORY_FILL_A32_S\000" |
| 5400 | /* 17413 */ "LOAD32_SPLAT_A32_S\000" |
| 5401 | /* 17432 */ "LOAD64_SPLAT_A32_S\000" |
| 5402 | /* 17451 */ "LOAD16_SPLAT_A32_S\000" |
| 5403 | /* 17470 */ "LOAD8_SPLAT_A32_S\000" |
| 5404 | /* 17488 */ "MEMSET_A32_S\000" |
| 5405 | /* 17501 */ "MEMORY_INIT_A32_S\000" |
| 5406 | /* 17519 */ "anonymous_14864MEMORY_GROW_A32_S\000" |
| 5407 | /* 17552 */ "MEMORY_ATOMIC_NOTIFY_A32_S\000" |
| 5408 | /* 17579 */ "MEMCPY_A32_S\000" |
| 5409 | /* 17592 */ "MEMORY_COPY_A32_S\000" |
| 5410 | /* 17610 */ "FP_TO_SINT_I32_F32_S\000" |
| 5411 | /* 17631 */ "FP_TO_UINT_I32_F32_S\000" |
| 5412 | /* 17652 */ "FP_TO_SINT_I64_F32_S\000" |
| 5413 | /* 17673 */ "FP_TO_UINT_I64_F32_S\000" |
| 5414 | /* 17694 */ "SUB_F32_S\000" |
| 5415 | /* 17704 */ "TRUNC_F32_S\000" |
| 5416 | /* 17716 */ "ADD_F32_S\000" |
| 5417 | /* 17726 */ "LOCAL_TEE_F32_S\000" |
| 5418 | /* 17742 */ "GE_F32_S\000" |
| 5419 | /* 17751 */ "LE_F32_S\000" |
| 5420 | /* 17760 */ "NE_F32_S\000" |
| 5421 | /* 17769 */ "F64_PROMOTE_F32_S\000" |
| 5422 | /* 17787 */ "NEG_F32_S\000" |
| 5423 | /* 17797 */ "CEIL_F32_S\000" |
| 5424 | /* 17808 */ "MUL_F32_S\000" |
| 5425 | /* 17818 */ "COPYSIGN_F32_S\000" |
| 5426 | /* 17833 */ "MIN_F32_S\000" |
| 5427 | /* 17843 */ "DROP_F32_S\000" |
| 5428 | /* 17854 */ "EQ_F32_S\000" |
| 5429 | /* 17863 */ "FLOOR_F32_S\000" |
| 5430 | /* 17875 */ "ABS_F32_S\000" |
| 5431 | /* 17885 */ "I32_TRUNC_S_F32_S\000" |
| 5432 | /* 17903 */ "I64_TRUNC_S_F32_S\000" |
| 5433 | /* 17921 */ "I32_TRUNC_S_SAT_F32_S\000" |
| 5434 | /* 17943 */ "I64_TRUNC_S_SAT_F32_S\000" |
| 5435 | /* 17965 */ "I32_TRUNC_U_SAT_F32_S\000" |
| 5436 | /* 17987 */ "I64_TRUNC_U_SAT_F32_S\000" |
| 5437 | /* 18009 */ "SELECT_F32_S\000" |
| 5438 | /* 18022 */ "GLOBAL_GET_F32_S\000" |
| 5439 | /* 18039 */ "LOCAL_GET_F32_S\000" |
| 5440 | /* 18055 */ "I32_REINTERPRET_F32_S\000" |
| 5441 | /* 18077 */ "GLOBAL_SET_F32_S\000" |
| 5442 | /* 18094 */ "LOCAL_SET_F32_S\000" |
| 5443 | /* 18110 */ "GT_F32_S\000" |
| 5444 | /* 18119 */ "LT_F32_S\000" |
| 5445 | /* 18128 */ "SQRT_F32_S\000" |
| 5446 | /* 18139 */ "NEAREST_F32_S\000" |
| 5447 | /* 18153 */ "CONST_F32_S\000" |
| 5448 | /* 18165 */ "I32_TRUNC_U_F32_S\000" |
| 5449 | /* 18183 */ "I64_TRUNC_U_F32_S\000" |
| 5450 | /* 18201 */ "DIV_F32_S\000" |
| 5451 | /* 18211 */ "MAX_F32_S\000" |
| 5452 | /* 18221 */ "COPY_F32_S\000" |
| 5453 | /* 18232 */ "SUB_I32_S\000" |
| 5454 | /* 18242 */ "ADD_I32_S\000" |
| 5455 | /* 18252 */ "AND_I32_S\000" |
| 5456 | /* 18262 */ "LOCAL_TEE_I32_S\000" |
| 5457 | /* 18278 */ "BR_TABLE_I32_S\000" |
| 5458 | /* 18293 */ "NE_I32_S\000" |
| 5459 | /* 18302 */ "SHL_I32_S\000" |
| 5460 | /* 18312 */ "ROTL_I32_S\000" |
| 5461 | /* 18323 */ "MUL_I32_S\000" |
| 5462 | /* 18333 */ "DROP_I32_S\000" |
| 5463 | /* 18344 */ "EQ_I32_S\000" |
| 5464 | /* 18353 */ "XOR_I32_S\000" |
| 5465 | /* 18363 */ "ROTR_I32_S\000" |
| 5466 | /* 18374 */ "I32_EXTEND16_S_I32_S\000" |
| 5467 | /* 18395 */ "I32_EXTEND8_S_I32_S\000" |
| 5468 | /* 18415 */ "I64_EXTEND_S_I32_S\000" |
| 5469 | /* 18434 */ "GE_S_I32_S\000" |
| 5470 | /* 18445 */ "LE_S_I32_S\000" |
| 5471 | /* 18456 */ "REM_S_I32_S\000" |
| 5472 | /* 18468 */ "SHR_S_I32_S\000" |
| 5473 | /* 18480 */ "GT_S_I32_S\000" |
| 5474 | /* 18491 */ "LT_S_I32_S\000" |
| 5475 | /* 18502 */ "F32_CONVERT_S_I32_S\000" |
| 5476 | /* 18522 */ "F64_CONVERT_S_I32_S\000" |
| 5477 | /* 18542 */ "DIV_S_I32_S\000" |
| 5478 | /* 18554 */ "SELECT_I32_S\000" |
| 5479 | /* 18567 */ "GLOBAL_GET_I32_S\000" |
| 5480 | /* 18584 */ "LOCAL_GET_I32_S\000" |
| 5481 | /* 18600 */ "F32_REINTERPRET_I32_S\000" |
| 5482 | /* 18622 */ "GLOBAL_SET_I32_S\000" |
| 5483 | /* 18639 */ "LOCAL_SET_I32_S\000" |
| 5484 | /* 18655 */ "POPCNT_I32_S\000" |
| 5485 | /* 18668 */ "CONST_I32_S\000" |
| 5486 | /* 18680 */ "I64_EXTEND_U_I32_S\000" |
| 5487 | /* 18699 */ "GE_U_I32_S\000" |
| 5488 | /* 18710 */ "LE_U_I32_S\000" |
| 5489 | /* 18721 */ "REM_U_I32_S\000" |
| 5490 | /* 18733 */ "SHR_U_I32_S\000" |
| 5491 | /* 18745 */ "GT_U_I32_S\000" |
| 5492 | /* 18756 */ "LT_U_I32_S\000" |
| 5493 | /* 18767 */ "F32_CONVERT_U_I32_S\000" |
| 5494 | /* 18787 */ "F64_CONVERT_U_I32_S\000" |
| 5495 | /* 18807 */ "DIV_U_I32_S\000" |
| 5496 | /* 18819 */ "COPY_I32_S\000" |
| 5497 | /* 18830 */ "CLZ_I32_S\000" |
| 5498 | /* 18840 */ "EQZ_I32_S\000" |
| 5499 | /* 18850 */ "CTZ_I32_S\000" |
| 5500 | /* 18860 */ "ARGUMENT_v4f32_S\000" |
| 5501 | /* 18877 */ "ARGUMENT_f32_S\000" |
| 5502 | /* 18892 */ "ARGUMENT_v4i32_S\000" |
| 5503 | /* 18909 */ "ARGUMENT_i32_S\000" |
| 5504 | /* 18924 */ "CONST_V128_F64x2_S\000" |
| 5505 | /* 18943 */ "SUB_F64x2_S\000" |
| 5506 | /* 18955 */ "TRUNC_F64x2_S\000" |
| 5507 | /* 18969 */ "NMADD_F64x2_S\000" |
| 5508 | /* 18983 */ "GE_F64x2_S\000" |
| 5509 | /* 18994 */ "LE_F64x2_S\000" |
| 5510 | /* 19005 */ "REPLACE_LANE_F64x2_S\000" |
| 5511 | /* 19026 */ "EXTRACT_LANE_F64x2_S\000" |
| 5512 | /* 19047 */ "NEG_F64x2_S\000" |
| 5513 | /* 19059 */ "CEIL_F64x2_S\000" |
| 5514 | /* 19072 */ "MUL_F64x2_S\000" |
| 5515 | /* 19084 */ "SIMD_RELAXED_FMIN_F64x2_S\000" |
| 5516 | /* 19110 */ "PMIN_F64x2_S\000" |
| 5517 | /* 19123 */ "EQ_F64x2_S\000" |
| 5518 | /* 19134 */ "FLOOR_F64x2_S\000" |
| 5519 | /* 19148 */ "ABS_F64x2_S\000" |
| 5520 | /* 19160 */ "SPLAT_F64x2_S\000" |
| 5521 | /* 19174 */ "GT_F64x2_S\000" |
| 5522 | /* 19185 */ "LT_F64x2_S\000" |
| 5523 | /* 19196 */ "SQRT_F64x2_S\000" |
| 5524 | /* 19209 */ "NEAREST_F64x2_S\000" |
| 5525 | /* 19225 */ "DIV_F64x2_S\000" |
| 5526 | /* 19237 */ "SIMD_RELAXED_FMAX_F64x2_S\000" |
| 5527 | /* 19263 */ "PMAX_F64x2_S\000" |
| 5528 | /* 19276 */ "convert_low_s_F64x2_S\000" |
| 5529 | /* 19298 */ "convert_low_u_F64x2_S\000" |
| 5530 | /* 19320 */ "promote_low_F64x2_S\000" |
| 5531 | /* 19340 */ "CONST_V128_I64x2_S\000" |
| 5532 | /* 19359 */ "SUB_I64x2_S\000" |
| 5533 | /* 19371 */ "ADD_I64x2_S\000" |
| 5534 | /* 19383 */ "REPLACE_LANE_I64x2_S\000" |
| 5535 | /* 19404 */ "EXTRACT_LANE_I64x2_S\000" |
| 5536 | /* 19425 */ "ALLTRUE_I64x2_S\000" |
| 5537 | /* 19441 */ "NEG_I64x2_S\000" |
| 5538 | /* 19453 */ "BITMASK_I64x2_S\000" |
| 5539 | /* 19469 */ "SHL_I64x2_S\000" |
| 5540 | /* 19481 */ "MUL_I64x2_S\000" |
| 5541 | /* 19493 */ "EQ_I64x2_S\000" |
| 5542 | /* 19504 */ "ABS_I64x2_S\000" |
| 5543 | /* 19516 */ "GE_S_I64x2_S\000" |
| 5544 | /* 19529 */ "LE_S_I64x2_S\000" |
| 5545 | /* 19542 */ "EXTMUL_HIGH_S_I64x2_S\000" |
| 5546 | /* 19564 */ "SHR_S_I64x2_S\000" |
| 5547 | /* 19578 */ "GT_S_I64x2_S\000" |
| 5548 | /* 19591 */ "LT_S_I64x2_S\000" |
| 5549 | /* 19604 */ "EXTMUL_LOW_S_I64x2_S\000" |
| 5550 | /* 19625 */ "SPLAT_I64x2_S\000" |
| 5551 | /* 19639 */ "LANESELECT_I64x2_S\000" |
| 5552 | /* 19658 */ "EXTMUL_HIGH_U_I64x2_S\000" |
| 5553 | /* 19680 */ "SHR_U_I64x2_S\000" |
| 5554 | /* 19694 */ "EXTMUL_LOW_U_I64x2_S\000" |
| 5555 | /* 19715 */ "extend_high_s_I64x2_S\000" |
| 5556 | /* 19737 */ "extend_low_s_I64x2_S\000" |
| 5557 | /* 19758 */ "extend_high_u_I64x2_S\000" |
| 5558 | /* 19780 */ "extend_low_u_I64x2_S\000" |
| 5559 | /* 19801 */ "LOAD_F16_F32_A64_S\000" |
| 5560 | /* 19820 */ "STORE_F16_F32_A64_S\000" |
| 5561 | /* 19840 */ "LOAD_F32_A64_S\000" |
| 5562 | /* 19855 */ "STORE_F32_A64_S\000" |
| 5563 | /* 19871 */ "ATOMIC_STORE16_I32_A64_S\000" |
| 5564 | /* 19896 */ "ATOMIC_STORE8_I32_A64_S\000" |
| 5565 | /* 19920 */ "ATOMIC_RMW16_U_SUB_I32_A64_S\000" |
| 5566 | /* 19949 */ "ATOMIC_RMW8_U_SUB_I32_A64_S\000" |
| 5567 | /* 19977 */ "ATOMIC_RMW_SUB_I32_A64_S\000" |
| 5568 | /* 20002 */ "ATOMIC_LOAD_I32_A64_S\000" |
| 5569 | /* 20024 */ "ATOMIC_RMW16_U_ADD_I32_A64_S\000" |
| 5570 | /* 20053 */ "ATOMIC_RMW8_U_ADD_I32_A64_S\000" |
| 5571 | /* 20081 */ "ATOMIC_RMW_ADD_I32_A64_S\000" |
| 5572 | /* 20106 */ "ATOMIC_RMW16_U_AND_I32_A64_S\000" |
| 5573 | /* 20135 */ "ATOMIC_RMW8_U_AND_I32_A64_S\000" |
| 5574 | /* 20163 */ "ATOMIC_RMW_AND_I32_A64_S\000" |
| 5575 | /* 20188 */ "ATOMIC_STORE_I32_A64_S\000" |
| 5576 | /* 20211 */ "ATOMIC_RMW16_U_CMPXCHG_I32_A64_S\000" |
| 5577 | /* 20244 */ "ATOMIC_RMW8_U_CMPXCHG_I32_A64_S\000" |
| 5578 | /* 20276 */ "ATOMIC_RMW_CMPXCHG_I32_A64_S\000" |
| 5579 | /* 20305 */ "ATOMIC_RMW16_U_XCHG_I32_A64_S\000" |
| 5580 | /* 20335 */ "ATOMIC_RMW8_U_XCHG_I32_A64_S\000" |
| 5581 | /* 20364 */ "ATOMIC_RMW_XCHG_I32_A64_S\000" |
| 5582 | /* 20390 */ "ATOMIC_RMW16_U_XOR_I32_A64_S\000" |
| 5583 | /* 20419 */ "ATOMIC_RMW8_U_XOR_I32_A64_S\000" |
| 5584 | /* 20447 */ "ATOMIC_RMW_XOR_I32_A64_S\000" |
| 5585 | /* 20472 */ "ATOMIC_RMW16_U_OR_I32_A64_S\000" |
| 5586 | /* 20500 */ "ATOMIC_RMW8_U_OR_I32_A64_S\000" |
| 5587 | /* 20527 */ "ATOMIC_RMW_OR_I32_A64_S\000" |
| 5588 | /* 20551 */ "LOAD16_S_I32_A64_S\000" |
| 5589 | /* 20570 */ "LOAD8_S_I32_A64_S\000" |
| 5590 | /* 20588 */ "ATOMIC_LOAD16_U_I32_A64_S\000" |
| 5591 | /* 20614 */ "ATOMIC_LOAD8_U_I32_A64_S\000" |
| 5592 | /* 20639 */ "MEMORY_ATOMIC_WAIT32_A64_S\000" |
| 5593 | /* 20666 */ "LOAD_LANE_32_A64_S\000" |
| 5594 | /* 20685 */ "LOAD_ZERO_32_A64_S\000" |
| 5595 | /* 20704 */ "STORE_LANE_I64x2_A64_S\000" |
| 5596 | /* 20727 */ "LOAD_EXTEND_S_I64x2_A64_S\000" |
| 5597 | /* 20753 */ "LOAD_EXTEND_U_I64x2_A64_S\000" |
| 5598 | /* 20779 */ "LOAD_F64_A64_S\000" |
| 5599 | /* 20794 */ "STORE_F64_A64_S\000" |
| 5600 | /* 20810 */ "ATOMIC_STORE32_I64_A64_S\000" |
| 5601 | /* 20835 */ "ATOMIC_STORE16_I64_A64_S\000" |
| 5602 | /* 20860 */ "ATOMIC_STORE8_I64_A64_S\000" |
| 5603 | /* 20884 */ "ATOMIC_RMW32_U_SUB_I64_A64_S\000" |
| 5604 | /* 20913 */ "ATOMIC_RMW16_U_SUB_I64_A64_S\000" |
| 5605 | /* 20942 */ "ATOMIC_RMW8_U_SUB_I64_A64_S\000" |
| 5606 | /* 20970 */ "ATOMIC_RMW_SUB_I64_A64_S\000" |
| 5607 | /* 20995 */ "ATOMIC_LOAD_I64_A64_S\000" |
| 5608 | /* 21017 */ "ATOMIC_RMW32_U_ADD_I64_A64_S\000" |
| 5609 | /* 21046 */ "ATOMIC_RMW16_U_ADD_I64_A64_S\000" |
| 5610 | /* 21075 */ "ATOMIC_RMW8_U_ADD_I64_A64_S\000" |
| 5611 | /* 21103 */ "ATOMIC_RMW_ADD_I64_A64_S\000" |
| 5612 | /* 21128 */ "ATOMIC_RMW32_U_AND_I64_A64_S\000" |
| 5613 | /* 21157 */ "ATOMIC_RMW16_U_AND_I64_A64_S\000" |
| 5614 | /* 21186 */ "ATOMIC_RMW8_U_AND_I64_A64_S\000" |
| 5615 | /* 21214 */ "ATOMIC_RMW_AND_I64_A64_S\000" |
| 5616 | /* 21239 */ "ATOMIC_STORE_I64_A64_S\000" |
| 5617 | /* 21262 */ "ATOMIC_RMW32_U_CMPXCHG_I64_A64_S\000" |
| 5618 | /* 21295 */ "ATOMIC_RMW16_U_CMPXCHG_I64_A64_S\000" |
| 5619 | /* 21328 */ "ATOMIC_RMW8_U_CMPXCHG_I64_A64_S\000" |
| 5620 | /* 21360 */ "ATOMIC_RMW_CMPXCHG_I64_A64_S\000" |
| 5621 | /* 21389 */ "ATOMIC_RMW32_U_XCHG_I64_A64_S\000" |
| 5622 | /* 21419 */ "ATOMIC_RMW16_U_XCHG_I64_A64_S\000" |
| 5623 | /* 21449 */ "ATOMIC_RMW8_U_XCHG_I64_A64_S\000" |
| 5624 | /* 21478 */ "ATOMIC_RMW_XCHG_I64_A64_S\000" |
| 5625 | /* 21504 */ "ATOMIC_RMW32_U_XOR_I64_A64_S\000" |
| 5626 | /* 21533 */ "ATOMIC_RMW16_U_XOR_I64_A64_S\000" |
| 5627 | /* 21562 */ "ATOMIC_RMW8_U_XOR_I64_A64_S\000" |
| 5628 | /* 21590 */ "ATOMIC_RMW_XOR_I64_A64_S\000" |
| 5629 | /* 21615 */ "ATOMIC_RMW32_U_OR_I64_A64_S\000" |
| 5630 | /* 21643 */ "ATOMIC_RMW16_U_OR_I64_A64_S\000" |
| 5631 | /* 21671 */ "ATOMIC_RMW8_U_OR_I64_A64_S\000" |
| 5632 | /* 21698 */ "ATOMIC_RMW_OR_I64_A64_S\000" |
| 5633 | /* 21722 */ "LOAD32_S_I64_A64_S\000" |
| 5634 | /* 21741 */ "LOAD16_S_I64_A64_S\000" |
| 5635 | /* 21760 */ "LOAD8_S_I64_A64_S\000" |
| 5636 | /* 21778 */ "ATOMIC_LOAD32_U_I64_A64_S\000" |
| 5637 | /* 21804 */ "ATOMIC_LOAD16_U_I64_A64_S\000" |
| 5638 | /* 21830 */ "ATOMIC_LOAD8_U_I64_A64_S\000" |
| 5639 | /* 21855 */ "MEMORY_ATOMIC_WAIT64_A64_S\000" |
| 5640 | /* 21882 */ "LOAD_LANE_64_A64_S\000" |
| 5641 | /* 21901 */ "LOAD_ZERO_64_A64_S\000" |
| 5642 | /* 21920 */ "STORE_LANE_I32x4_A64_S\000" |
| 5643 | /* 21943 */ "LOAD_EXTEND_S_I32x4_A64_S\000" |
| 5644 | /* 21969 */ "LOAD_EXTEND_U_I32x4_A64_S\000" |
| 5645 | /* 21995 */ "LOAD_LANE_16_A64_S\000" |
| 5646 | /* 22014 */ "STORE_LANE_I8x16_A64_S\000" |
| 5647 | /* 22037 */ "LOAD_V128_A64_S\000" |
| 5648 | /* 22053 */ "STORE_V128_A64_S\000" |
| 5649 | /* 22070 */ "LOAD_LANE_8_A64_S\000" |
| 5650 | /* 22088 */ "STORE_LANE_I16x8_A64_S\000" |
| 5651 | /* 22111 */ "LOAD_EXTEND_S_I16x8_A64_S\000" |
| 5652 | /* 22137 */ "LOAD_EXTEND_U_I16x8_A64_S\000" |
| 5653 | /* 22163 */ "anonymous_14865MEMORY_SIZE_A64_S\000" |
| 5654 | /* 22196 */ "MEMORY_FILL_A64_S\000" |
| 5655 | /* 22214 */ "LOAD32_SPLAT_A64_S\000" |
| 5656 | /* 22233 */ "LOAD64_SPLAT_A64_S\000" |
| 5657 | /* 22252 */ "LOAD16_SPLAT_A64_S\000" |
| 5658 | /* 22271 */ "LOAD8_SPLAT_A64_S\000" |
| 5659 | /* 22289 */ "MEMSET_A64_S\000" |
| 5660 | /* 22302 */ "MEMORY_INIT_A64_S\000" |
| 5661 | /* 22320 */ "anonymous_14865MEMORY_GROW_A64_S\000" |
| 5662 | /* 22353 */ "MEMORY_ATOMIC_NOTIFY_A64_S\000" |
| 5663 | /* 22380 */ "MEMCPY_A64_S\000" |
| 5664 | /* 22393 */ "MEMORY_COPY_A64_S\000" |
| 5665 | /* 22411 */ "FP_TO_SINT_I32_F64_S\000" |
| 5666 | /* 22432 */ "FP_TO_UINT_I32_F64_S\000" |
| 5667 | /* 22453 */ "FP_TO_SINT_I64_F64_S\000" |
| 5668 | /* 22474 */ "FP_TO_UINT_I64_F64_S\000" |
| 5669 | /* 22495 */ "SUB_F64_S\000" |
| 5670 | /* 22505 */ "TRUNC_F64_S\000" |
| 5671 | /* 22517 */ "ADD_F64_S\000" |
| 5672 | /* 22527 */ "LOCAL_TEE_F64_S\000" |
| 5673 | /* 22543 */ "GE_F64_S\000" |
| 5674 | /* 22552 */ "LE_F64_S\000" |
| 5675 | /* 22561 */ "NE_F64_S\000" |
| 5676 | /* 22570 */ "F32_DEMOTE_F64_S\000" |
| 5677 | /* 22587 */ "NEG_F64_S\000" |
| 5678 | /* 22597 */ "CEIL_F64_S\000" |
| 5679 | /* 22608 */ "MUL_F64_S\000" |
| 5680 | /* 22618 */ "COPYSIGN_F64_S\000" |
| 5681 | /* 22633 */ "MIN_F64_S\000" |
| 5682 | /* 22643 */ "DROP_F64_S\000" |
| 5683 | /* 22654 */ "EQ_F64_S\000" |
| 5684 | /* 22663 */ "FLOOR_F64_S\000" |
| 5685 | /* 22675 */ "ABS_F64_S\000" |
| 5686 | /* 22685 */ "I32_TRUNC_S_F64_S\000" |
| 5687 | /* 22703 */ "I64_TRUNC_S_F64_S\000" |
| 5688 | /* 22721 */ "I32_TRUNC_S_SAT_F64_S\000" |
| 5689 | /* 22743 */ "I64_TRUNC_S_SAT_F64_S\000" |
| 5690 | /* 22765 */ "I32_TRUNC_U_SAT_F64_S\000" |
| 5691 | /* 22787 */ "I64_TRUNC_U_SAT_F64_S\000" |
| 5692 | /* 22809 */ "SELECT_F64_S\000" |
| 5693 | /* 22822 */ "GLOBAL_GET_F64_S\000" |
| 5694 | /* 22839 */ "LOCAL_GET_F64_S\000" |
| 5695 | /* 22855 */ "I64_REINTERPRET_F64_S\000" |
| 5696 | /* 22877 */ "GLOBAL_SET_F64_S\000" |
| 5697 | /* 22894 */ "LOCAL_SET_F64_S\000" |
| 5698 | /* 22910 */ "GT_F64_S\000" |
| 5699 | /* 22919 */ "LT_F64_S\000" |
| 5700 | /* 22928 */ "SQRT_F64_S\000" |
| 5701 | /* 22939 */ "NEAREST_F64_S\000" |
| 5702 | /* 22953 */ "CONST_F64_S\000" |
| 5703 | /* 22965 */ "I32_TRUNC_U_F64_S\000" |
| 5704 | /* 22983 */ "I64_TRUNC_U_F64_S\000" |
| 5705 | /* 23001 */ "DIV_F64_S\000" |
| 5706 | /* 23011 */ "MAX_F64_S\000" |
| 5707 | /* 23021 */ "COPY_F64_S\000" |
| 5708 | /* 23032 */ "SUB_I64_S\000" |
| 5709 | /* 23042 */ "ADD_I64_S\000" |
| 5710 | /* 23052 */ "AND_I64_S\000" |
| 5711 | /* 23062 */ "LOCAL_TEE_I64_S\000" |
| 5712 | /* 23078 */ "BR_TABLE_I64_S\000" |
| 5713 | /* 23093 */ "NE_I64_S\000" |
| 5714 | /* 23102 */ "SHL_I64_S\000" |
| 5715 | /* 23112 */ "ROTL_I64_S\000" |
| 5716 | /* 23123 */ "MUL_I64_S\000" |
| 5717 | /* 23133 */ "I32_WRAP_I64_S\000" |
| 5718 | /* 23148 */ "DROP_I64_S\000" |
| 5719 | /* 23159 */ "EQ_I64_S\000" |
| 5720 | /* 23168 */ "XOR_I64_S\000" |
| 5721 | /* 23178 */ "ROTR_I64_S\000" |
| 5722 | /* 23189 */ "I64_EXTEND32_S_I64_S\000" |
| 5723 | /* 23210 */ "I64_EXTEND16_S_I64_S\000" |
| 5724 | /* 23231 */ "I64_EXTEND8_S_I64_S\000" |
| 5725 | /* 23251 */ "GE_S_I64_S\000" |
| 5726 | /* 23262 */ "LE_S_I64_S\000" |
| 5727 | /* 23273 */ "REM_S_I64_S\000" |
| 5728 | /* 23285 */ "SHR_S_I64_S\000" |
| 5729 | /* 23297 */ "GT_S_I64_S\000" |
| 5730 | /* 23308 */ "LT_S_I64_S\000" |
| 5731 | /* 23319 */ "F32_CONVERT_S_I64_S\000" |
| 5732 | /* 23339 */ "F64_CONVERT_S_I64_S\000" |
| 5733 | /* 23359 */ "DIV_S_I64_S\000" |
| 5734 | /* 23371 */ "SELECT_I64_S\000" |
| 5735 | /* 23384 */ "GLOBAL_GET_I64_S\000" |
| 5736 | /* 23401 */ "LOCAL_GET_I64_S\000" |
| 5737 | /* 23417 */ "F64_REINTERPRET_I64_S\000" |
| 5738 | /* 23439 */ "GLOBAL_SET_I64_S\000" |
| 5739 | /* 23456 */ "LOCAL_SET_I64_S\000" |
| 5740 | /* 23472 */ "POPCNT_I64_S\000" |
| 5741 | /* 23485 */ "CONST_I64_S\000" |
| 5742 | /* 23497 */ "GE_U_I64_S\000" |
| 5743 | /* 23508 */ "LE_U_I64_S\000" |
| 5744 | /* 23519 */ "REM_U_I64_S\000" |
| 5745 | /* 23531 */ "SHR_U_I64_S\000" |
| 5746 | /* 23543 */ "GT_U_I64_S\000" |
| 5747 | /* 23554 */ "LT_U_I64_S\000" |
| 5748 | /* 23565 */ "F32_CONVERT_U_I64_S\000" |
| 5749 | /* 23585 */ "F64_CONVERT_U_I64_S\000" |
| 5750 | /* 23605 */ "DIV_U_I64_S\000" |
| 5751 | /* 23617 */ "COPY_I64_S\000" |
| 5752 | /* 23628 */ "CLZ_I64_S\000" |
| 5753 | /* 23638 */ "EQZ_I64_S\000" |
| 5754 | /* 23648 */ "CTZ_I64_S\000" |
| 5755 | /* 23658 */ "ARGUMENT_v2f64_S\000" |
| 5756 | /* 23675 */ "ARGUMENT_f64_S\000" |
| 5757 | /* 23690 */ "ARGUMENT_v2i64_S\000" |
| 5758 | /* 23707 */ "ARGUMENT_i64_S\000" |
| 5759 | /* 23722 */ "CONST_V128_F32x4_S\000" |
| 5760 | /* 23741 */ "SUB_F32x4_S\000" |
| 5761 | /* 23753 */ "TRUNC_F32x4_S\000" |
| 5762 | /* 23767 */ "NMADD_F32x4_S\000" |
| 5763 | /* 23781 */ "GE_F32x4_S\000" |
| 5764 | /* 23792 */ "LE_F32x4_S\000" |
| 5765 | /* 23803 */ "REPLACE_LANE_F32x4_S\000" |
| 5766 | /* 23824 */ "EXTRACT_LANE_F32x4_S\000" |
| 5767 | /* 23845 */ "NEG_F32x4_S\000" |
| 5768 | /* 23857 */ "CEIL_F32x4_S\000" |
| 5769 | /* 23870 */ "MUL_F32x4_S\000" |
| 5770 | /* 23882 */ "SIMD_RELAXED_FMIN_F32x4_S\000" |
| 5771 | /* 23908 */ "PMIN_F32x4_S\000" |
| 5772 | /* 23921 */ "EQ_F32x4_S\000" |
| 5773 | /* 23932 */ "FLOOR_F32x4_S\000" |
| 5774 | /* 23946 */ "ABS_F32x4_S\000" |
| 5775 | /* 23958 */ "SPLAT_F32x4_S\000" |
| 5776 | /* 23972 */ "GT_F32x4_S\000" |
| 5777 | /* 23983 */ "LT_F32x4_S\000" |
| 5778 | /* 23994 */ "SQRT_F32x4_S\000" |
| 5779 | /* 24007 */ "NEAREST_F32x4_S\000" |
| 5780 | /* 24023 */ "DIV_F32x4_S\000" |
| 5781 | /* 24035 */ "SIMD_RELAXED_FMAX_F32x4_S\000" |
| 5782 | /* 24061 */ "PMAX_F32x4_S\000" |
| 5783 | /* 24074 */ "demote_zero_F32x4_S\000" |
| 5784 | /* 24094 */ "sint_to_fp_F32x4_S\000" |
| 5785 | /* 24113 */ "uint_to_fp_F32x4_S\000" |
| 5786 | /* 24132 */ "promote_low_F32x4_S\000" |
| 5787 | /* 24152 */ "CONST_V128_I32x4_S\000" |
| 5788 | /* 24171 */ "SUB_I32x4_S\000" |
| 5789 | /* 24183 */ "ADD_I32x4_S\000" |
| 5790 | /* 24195 */ "REPLACE_LANE_I32x4_S\000" |
| 5791 | /* 24216 */ "EXTRACT_LANE_I32x4_S\000" |
| 5792 | /* 24237 */ "ALLTRUE_I32x4_S\000" |
| 5793 | /* 24253 */ "NEG_I32x4_S\000" |
| 5794 | /* 24265 */ "BITMASK_I32x4_S\000" |
| 5795 | /* 24281 */ "SHL_I32x4_S\000" |
| 5796 | /* 24293 */ "MUL_I32x4_S\000" |
| 5797 | /* 24305 */ "EQ_I32x4_S\000" |
| 5798 | /* 24316 */ "ABS_I32x4_S\000" |
| 5799 | /* 24328 */ "GE_S_I32x4_S\000" |
| 5800 | /* 24341 */ "LE_S_I32x4_S\000" |
| 5801 | /* 24354 */ "EXTMUL_HIGH_S_I32x4_S\000" |
| 5802 | /* 24376 */ "MIN_S_I32x4_S\000" |
| 5803 | /* 24390 */ "SHR_S_I32x4_S\000" |
| 5804 | /* 24404 */ "GT_S_I32x4_S\000" |
| 5805 | /* 24417 */ "LT_S_I32x4_S\000" |
| 5806 | /* 24430 */ "EXTMUL_LOW_S_I32x4_S\000" |
| 5807 | /* 24451 */ "MAX_S_I32x4_S\000" |
| 5808 | /* 24465 */ "SPLAT_I32x4_S\000" |
| 5809 | /* 24479 */ "LANESELECT_I32x4_S\000" |
| 5810 | /* 24498 */ "GE_U_I32x4_S\000" |
| 5811 | /* 24511 */ "LE_U_I32x4_S\000" |
| 5812 | /* 24524 */ "EXTMUL_HIGH_U_I32x4_S\000" |
| 5813 | /* 24546 */ "MIN_U_I32x4_S\000" |
| 5814 | /* 24560 */ "SHR_U_I32x4_S\000" |
| 5815 | /* 24574 */ "GT_U_I32x4_S\000" |
| 5816 | /* 24587 */ "LT_U_I32x4_S\000" |
| 5817 | /* 24600 */ "EXTMUL_LOW_U_I32x4_S\000" |
| 5818 | /* 24621 */ "MAX_U_I32x4_S\000" |
| 5819 | /* 24635 */ "int_wasm_relaxed_trunc_signed_I32x4_S\000" |
| 5820 | /* 24673 */ "int_wasm_relaxed_trunc_unsigned_I32x4_S\000" |
| 5821 | /* 24713 */ "int_wasm_relaxed_trunc_signed_zero_I32x4_S\000" |
| 5822 | /* 24756 */ "int_wasm_relaxed_trunc_unsigned_zero_I32x4_S\000" |
| 5823 | /* 24801 */ "extadd_pairwise_s_I32x4_S\000" |
| 5824 | /* 24827 */ "extend_high_s_I32x4_S\000" |
| 5825 | /* 24849 */ "trunc_sat_zero_s_I32x4_S\000" |
| 5826 | /* 24874 */ "extend_low_s_I32x4_S\000" |
| 5827 | /* 24895 */ "fp_to_sint_I32x4_S\000" |
| 5828 | /* 24914 */ "fp_to_uint_I32x4_S\000" |
| 5829 | /* 24933 */ "extadd_pairwise_u_I32x4_S\000" |
| 5830 | /* 24959 */ "extend_high_u_I32x4_S\000" |
| 5831 | /* 24981 */ "trunc_sat_zero_u_I32x4_S\000" |
| 5832 | /* 25006 */ "extend_low_u_I32x4_S\000" |
| 5833 | /* 25027 */ "ARGUMENT_v8f16_S\000" |
| 5834 | /* 25044 */ "ARGUMENT_v8i16_S\000" |
| 5835 | /* 25061 */ "CONST_V128_I8x16_S\000" |
| 5836 | /* 25080 */ "SUB_I8x16_S\000" |
| 5837 | /* 25092 */ "ADD_I8x16_S\000" |
| 5838 | /* 25104 */ "REPLACE_LANE_I8x16_S\000" |
| 5839 | /* 25125 */ "ALLTRUE_I8x16_S\000" |
| 5840 | /* 25141 */ "NEG_I8x16_S\000" |
| 5841 | /* 25153 */ "BITMASK_I8x16_S\000" |
| 5842 | /* 25169 */ "SHL_I8x16_S\000" |
| 5843 | /* 25181 */ "EQ_I8x16_S\000" |
| 5844 | /* 25192 */ "ABS_I8x16_S\000" |
| 5845 | /* 25204 */ "GE_S_I8x16_S\000" |
| 5846 | /* 25217 */ "LE_S_I8x16_S\000" |
| 5847 | /* 25230 */ "MIN_S_I8x16_S\000" |
| 5848 | /* 25244 */ "SHR_S_I8x16_S\000" |
| 5849 | /* 25258 */ "SUB_SAT_S_I8x16_S\000" |
| 5850 | /* 25276 */ "ADD_SAT_S_I8x16_S\000" |
| 5851 | /* 25294 */ "GT_S_I8x16_S\000" |
| 5852 | /* 25307 */ "LT_S_I8x16_S\000" |
| 5853 | /* 25320 */ "NARROW_S_I8x16_S\000" |
| 5854 | /* 25337 */ "MAX_S_I8x16_S\000" |
| 5855 | /* 25351 */ "SPLAT_I8x16_S\000" |
| 5856 | /* 25365 */ "LANESELECT_I8x16_S\000" |
| 5857 | /* 25384 */ "POPCNT_I8x16_S\000" |
| 5858 | /* 25399 */ "GE_U_I8x16_S\000" |
| 5859 | /* 25412 */ "LE_U_I8x16_S\000" |
| 5860 | /* 25425 */ "MIN_U_I8x16_S\000" |
| 5861 | /* 25439 */ "AVGR_U_I8x16_S\000" |
| 5862 | /* 25454 */ "SHR_U_I8x16_S\000" |
| 5863 | /* 25468 */ "SUB_SAT_U_I8x16_S\000" |
| 5864 | /* 25486 */ "ADD_SAT_U_I8x16_S\000" |
| 5865 | /* 25504 */ "GT_U_I8x16_S\000" |
| 5866 | /* 25517 */ "LT_U_I8x16_S\000" |
| 5867 | /* 25530 */ "NARROW_U_I8x16_S\000" |
| 5868 | /* 25547 */ "MAX_U_I8x16_S\000" |
| 5869 | /* 25561 */ "I64_SUB128_S\000" |
| 5870 | /* 25574 */ "I64_ADD128_S\000" |
| 5871 | /* 25587 */ "LOCAL_TEE_V128_S\000" |
| 5872 | /* 25604 */ "DROP_V128_S\000" |
| 5873 | /* 25616 */ "SELECT_V128_S\000" |
| 5874 | /* 25630 */ "GLOBAL_GET_V128_S\000" |
| 5875 | /* 25648 */ "LOCAL_GET_V128_S\000" |
| 5876 | /* 25665 */ "GLOBAL_SET_V128_S\000" |
| 5877 | /* 25683 */ "LOCAL_SET_V128_S\000" |
| 5878 | /* 25700 */ "COPY_V128_S\000" |
| 5879 | /* 25712 */ "ARGUMENT_v16i8_S\000" |
| 5880 | /* 25729 */ "SUB_F16x8_S\000" |
| 5881 | /* 25741 */ "TRUNC_F16x8_S\000" |
| 5882 | /* 25755 */ "NMADD_F16x8_S\000" |
| 5883 | /* 25769 */ "GE_F16x8_S\000" |
| 5884 | /* 25780 */ "LE_F16x8_S\000" |
| 5885 | /* 25791 */ "REPLACE_LANE_F16x8_S\000" |
| 5886 | /* 25812 */ "EXTRACT_LANE_F16x8_S\000" |
| 5887 | /* 25833 */ "NEG_F16x8_S\000" |
| 5888 | /* 25845 */ "CEIL_F16x8_S\000" |
| 5889 | /* 25858 */ "MUL_F16x8_S\000" |
| 5890 | /* 25870 */ "PMIN_F16x8_S\000" |
| 5891 | /* 25883 */ "EQ_F16x8_S\000" |
| 5892 | /* 25894 */ "FLOOR_F16x8_S\000" |
| 5893 | /* 25908 */ "ABS_F16x8_S\000" |
| 5894 | /* 25920 */ "SPLAT_F16x8_S\000" |
| 5895 | /* 25934 */ "GT_F16x8_S\000" |
| 5896 | /* 25945 */ "LT_F16x8_S\000" |
| 5897 | /* 25956 */ "SQRT_F16x8_S\000" |
| 5898 | /* 25969 */ "NEAREST_F16x8_S\000" |
| 5899 | /* 25985 */ "DIV_F16x8_S\000" |
| 5900 | /* 25997 */ "PMAX_F16x8_S\000" |
| 5901 | /* 26010 */ "demote_zero_F16x8_S\000" |
| 5902 | /* 26030 */ "sint_to_fp_F16x8_S\000" |
| 5903 | /* 26049 */ "uint_to_fp_F16x8_S\000" |
| 5904 | /* 26068 */ "CONST_V128_I16x8_S\000" |
| 5905 | /* 26087 */ "SUB_I16x8_S\000" |
| 5906 | /* 26099 */ "ADD_I16x8_S\000" |
| 5907 | /* 26111 */ "REPLACE_LANE_I16x8_S\000" |
| 5908 | /* 26132 */ "ALLTRUE_I16x8_S\000" |
| 5909 | /* 26148 */ "NEG_I16x8_S\000" |
| 5910 | /* 26160 */ "BITMASK_I16x8_S\000" |
| 5911 | /* 26176 */ "SHL_I16x8_S\000" |
| 5912 | /* 26188 */ "MUL_I16x8_S\000" |
| 5913 | /* 26200 */ "EQ_I16x8_S\000" |
| 5914 | /* 26211 */ "ABS_I16x8_S\000" |
| 5915 | /* 26223 */ "GE_S_I16x8_S\000" |
| 5916 | /* 26236 */ "LE_S_I16x8_S\000" |
| 5917 | /* 26249 */ "EXTMUL_HIGH_S_I16x8_S\000" |
| 5918 | /* 26271 */ "MIN_S_I16x8_S\000" |
| 5919 | /* 26285 */ "SHR_S_I16x8_S\000" |
| 5920 | /* 26299 */ "RELAXED_Q15MULR_S_I16x8_S\000" |
| 5921 | /* 26325 */ "SUB_SAT_S_I16x8_S\000" |
| 5922 | /* 26343 */ "ADD_SAT_S_I16x8_S\000" |
| 5923 | /* 26361 */ "Q15MULR_SAT_S_I16x8_S\000" |
| 5924 | /* 26383 */ "GT_S_I16x8_S\000" |
| 5925 | /* 26396 */ "LT_S_I16x8_S\000" |
| 5926 | /* 26409 */ "EXTMUL_LOW_S_I16x8_S\000" |
| 5927 | /* 26430 */ "NARROW_S_I16x8_S\000" |
| 5928 | /* 26447 */ "MAX_S_I16x8_S\000" |
| 5929 | /* 26461 */ "SPLAT_I16x8_S\000" |
| 5930 | /* 26475 */ "LANESELECT_I16x8_S\000" |
| 5931 | /* 26494 */ "GE_U_I16x8_S\000" |
| 5932 | /* 26507 */ "LE_U_I16x8_S\000" |
| 5933 | /* 26520 */ "EXTMUL_HIGH_U_I16x8_S\000" |
| 5934 | /* 26542 */ "MIN_U_I16x8_S\000" |
| 5935 | /* 26556 */ "AVGR_U_I16x8_S\000" |
| 5936 | /* 26571 */ "SHR_U_I16x8_S\000" |
| 5937 | /* 26585 */ "SUB_SAT_U_I16x8_S\000" |
| 5938 | /* 26603 */ "ADD_SAT_U_I16x8_S\000" |
| 5939 | /* 26621 */ "GT_U_I16x8_S\000" |
| 5940 | /* 26634 */ "LT_U_I16x8_S\000" |
| 5941 | /* 26647 */ "EXTMUL_LOW_U_I16x8_S\000" |
| 5942 | /* 26668 */ "NARROW_U_I16x8_S\000" |
| 5943 | /* 26685 */ "MAX_U_I16x8_S\000" |
| 5944 | /* 26699 */ "extadd_pairwise_s_I16x8_S\000" |
| 5945 | /* 26725 */ "extend_high_s_I16x8_S\000" |
| 5946 | /* 26747 */ "extend_low_s_I16x8_S\000" |
| 5947 | /* 26768 */ "fp_to_sint_I16x8_S\000" |
| 5948 | /* 26787 */ "fp_to_uint_I16x8_S\000" |
| 5949 | /* 26806 */ "extadd_pairwise_u_I16x8_S\000" |
| 5950 | /* 26832 */ "extend_high_u_I16x8_S\000" |
| 5951 | /* 26854 */ "extend_low_u_I16x8_S\000" |
| 5952 | /* 26875 */ "REF_FUNC_S\000" |
| 5953 | /* 26886 */ "RELAXED_DOT_ADD_S\000" |
| 5954 | /* 26904 */ "AND_S\000" |
| 5955 | /* 26910 */ "END_S\000" |
| 5956 | /* 26916 */ "ATOMIC_FENCE_S\000" |
| 5957 | /* 26931 */ "COMPILER_FENCE_S\000" |
| 5958 | /* 26948 */ "I64_MUL_WIDE_S\000" |
| 5959 | /* 26963 */ "DEBUG_UNREACHABLE_S\000" |
| 5960 | /* 26983 */ "END_TRY_TABLE_S\000" |
| 5961 | /* 26999 */ "SHUFFLE_S\000" |
| 5962 | /* 27009 */ "RELAXED_SWIZZLE_S\000" |
| 5963 | /* 27027 */ "ELSE_S\000" |
| 5964 | /* 27034 */ "DELEGATE_S\000" |
| 5965 | /* 27045 */ "ANYTRUE_S\000" |
| 5966 | /* 27055 */ "TABLE_SIZE_S\000" |
| 5967 | /* 27068 */ "LOCAL_TEE_FUNCREF_S\000" |
| 5968 | /* 27088 */ "TABLE_FILL_FUNCREF_S\000" |
| 5969 | /* 27109 */ "REF_NULL_FUNCREF_S\000" |
| 5970 | /* 27128 */ "REF_IS_NULL_FUNCREF_S\000" |
| 5971 | /* 27150 */ "DROP_FUNCREF_S\000" |
| 5972 | /* 27165 */ "SELECT_FUNCREF_S\000" |
| 5973 | /* 27182 */ "TABLE_GET_FUNCREF_S\000" |
| 5974 | /* 27202 */ "GLOBAL_GET_FUNCREF_S\000" |
| 5975 | /* 27223 */ "LOCAL_GET_FUNCREF_S\000" |
| 5976 | /* 27243 */ "TABLE_SET_FUNCREF_S\000" |
| 5977 | /* 27263 */ "GLOBAL_SET_FUNCREF_S\000" |
| 5978 | /* 27284 */ "LOCAL_SET_FUNCREF_S\000" |
| 5979 | /* 27304 */ "REF_CAST_FUNCREF_S\000" |
| 5980 | /* 27323 */ "REF_TEST_FUNCREF_S\000" |
| 5981 | /* 27342 */ "TABLE_GROW_FUNCREF_S\000" |
| 5982 | /* 27363 */ "COPY_FUNCREF_S\000" |
| 5983 | /* 27378 */ "LOCAL_TEE_EXTERNREF_S\000" |
| 5984 | /* 27400 */ "TABLE_FILL_EXTERNREF_S\000" |
| 5985 | /* 27423 */ "REF_NULL_EXTERNREF_S\000" |
| 5986 | /* 27444 */ "REF_IS_NULL_EXTERNREF_S\000" |
| 5987 | /* 27468 */ "DROP_EXTERNREF_S\000" |
| 5988 | /* 27485 */ "SELECT_EXTERNREF_S\000" |
| 5989 | /* 27504 */ "TABLE_GET_EXTERNREF_S\000" |
| 5990 | /* 27526 */ "GLOBAL_GET_EXTERNREF_S\000" |
| 5991 | /* 27549 */ "LOCAL_GET_EXTERNREF_S\000" |
| 5992 | /* 27571 */ "TABLE_SET_EXTERNREF_S\000" |
| 5993 | /* 27593 */ "GLOBAL_SET_EXTERNREF_S\000" |
| 5994 | /* 27616 */ "LOCAL_SET_EXTERNREF_S\000" |
| 5995 | /* 27638 */ "TABLE_GROW_EXTERNREF_S\000" |
| 5996 | /* 27661 */ "COPY_EXTERNREF_S\000" |
| 5997 | /* 27678 */ "LOCAL_TEE_EXNREF_S\000" |
| 5998 | /* 27697 */ "TABLE_FILL_EXNREF_S\000" |
| 5999 | /* 27717 */ "REF_NULL_EXNREF_S\000" |
| 6000 | /* 27735 */ "REF_IS_NULL_EXNREF_S\000" |
| 6001 | /* 27756 */ "DROP_EXNREF_S\000" |
| 6002 | /* 27770 */ "SELECT_EXNREF_S\000" |
| 6003 | /* 27786 */ "TABLE_GET_EXNREF_S\000" |
| 6004 | /* 27805 */ "GLOBAL_GET_EXNREF_S\000" |
| 6005 | /* 27825 */ "LOCAL_GET_EXNREF_S\000" |
| 6006 | /* 27844 */ "TABLE_SET_EXNREF_S\000" |
| 6007 | /* 27863 */ "GLOBAL_SET_EXNREF_S\000" |
| 6008 | /* 27883 */ "LOCAL_SET_EXNREF_S\000" |
| 6009 | /* 27902 */ "TABLE_GROW_EXNREF_S\000" |
| 6010 | /* 27922 */ "COPY_EXNREF_S\000" |
| 6011 | /* 27936 */ "CATCH_REF_S\000" |
| 6012 | /* 27948 */ "RET_CALL_REF_S\000" |
| 6013 | /* 27963 */ "CATCH_ALL_REF_S\000" |
| 6014 | /* 27979 */ "THROW_REF_S\000" |
| 6015 | /* 27991 */ "END_IF_S\000" |
| 6016 | /* 28000 */ "BR_IF_S\000" |
| 6017 | /* 28008 */ "CATCH_S\000" |
| 6018 | /* 28016 */ "END_BLOCK_S\000" |
| 6019 | /* 28028 */ "RET_CALL_S\000" |
| 6020 | /* 28039 */ "CATCH_ALL_S\000" |
| 6021 | /* 28051 */ "END_FUNCTION_S\000" |
| 6022 | /* 28066 */ "FALLTHROUGH_RETURN_S\000" |
| 6023 | /* 28087 */ "ADJCALLSTACKDOWN_S\000" |
| 6024 | /* 28106 */ "NOP_S\000" |
| 6025 | /* 28112 */ "END_LOOP_S\000" |
| 6026 | /* 28123 */ "DATA_DROP_S\000" |
| 6027 | /* 28135 */ "ADJCALLSTACKUP_S\000" |
| 6028 | /* 28152 */ "BR_S\000" |
| 6029 | /* 28157 */ "XOR_S\000" |
| 6030 | /* 28163 */ "RET_CALL_PARAMS_S\000" |
| 6031 | /* 28181 */ "BR_UNLESS_S\000" |
| 6032 | /* 28193 */ "RET_CALL_RESULTS_S\000" |
| 6033 | /* 28212 */ "I64_MUL_WIDE_S_S\000" |
| 6034 | /* 28229 */ "RELAXED_DOT_BFLOAT_S\000" |
| 6035 | /* 28250 */ "G_TRUNC_SSAT_S\000" |
| 6036 | /* 28265 */ "BITSELECT_S\000" |
| 6037 | /* 28277 */ "RET_CALL_INDIRECT_S\000" |
| 6038 | /* 28297 */ "CATCHRET_S\000" |
| 6039 | /* 28308 */ "CLEANUPRET_S\000" |
| 6040 | /* 28321 */ "RELAXED_DOT_S\000" |
| 6041 | /* 28335 */ "ANDNOT_S\000" |
| 6042 | /* 28344 */ "SELECT_T_S\000" |
| 6043 | /* 28355 */ "I64_MUL_WIDE_U_S\000" |
| 6044 | /* 28372 */ "RETHROW_S\000" |
| 6045 | /* 28382 */ "CATCH_LEGACY_S\000" |
| 6046 | /* 28397 */ "CATCH_ALL_LEGACY_S\000" |
| 6047 | /* 28416 */ "TABLE_COPY_S\000" |
| 6048 | /* 28429 */ "END_TRY_S\000" |
| 6049 | /* 28439 */ "ARGUMENT_funcref_S\000" |
| 6050 | /* 28458 */ "ARGUMENT_externref_S\000" |
| 6051 | /* 28479 */ "ARGUMENT_exnref_S\000" |
| 6052 | /* 28497 */ "EXTRACT_LANE_I8x16_s_S\000" |
| 6053 | /* 28520 */ "EXTRACT_LANE_I16x8_s_S\000" |
| 6054 | /* 28543 */ "EXTRACT_LANE_I8x16_u_S\000" |
| 6055 | /* 28566 */ "EXTRACT_LANE_I16x8_u_S\000" |
| 6056 | /* 28589 */ "RELAXED_DOT_BFLOAT\000" |
| 6057 | /* 28608 */ "G_SSUBSAT\000" |
| 6058 | /* 28618 */ "G_USUBSAT\000" |
| 6059 | /* 28628 */ "G_SADDSAT\000" |
| 6060 | /* 28638 */ "G_UADDSAT\000" |
| 6061 | /* 28648 */ "G_SSHLSAT\000" |
| 6062 | /* 28658 */ "G_USHLSAT\000" |
| 6063 | /* 28668 */ "G_SMULFIXSAT\000" |
| 6064 | /* 28681 */ "G_UMULFIXSAT\000" |
| 6065 | /* 28694 */ "G_SDIVFIXSAT\000" |
| 6066 | /* 28707 */ "G_UDIVFIXSAT\000" |
| 6067 | /* 28720 */ "G_ATOMICRMW_USUB_SAT\000" |
| 6068 | /* 28741 */ "G_FPTOSI_SAT\000" |
| 6069 | /* 28754 */ "G_FPTOUI_SAT\000" |
| 6070 | /* 28767 */ "G_EXTRACT\000" |
| 6071 | /* 28777 */ "BITSELECT\000" |
| 6072 | /* 28787 */ "G_SELECT\000" |
| 6073 | /* 28796 */ "G_BRINDIRECT\000" |
| 6074 | /* 28809 */ "RET_CALL_INDIRECT\000" |
| 6075 | /* 28827 */ "CATCHRET\000" |
| 6076 | /* 28836 */ "CLEANUPRET\000" |
| 6077 | /* 28847 */ "PATCHABLE_RET\000" |
| 6078 | /* 28861 */ "G_MEMSET\000" |
| 6079 | /* 28870 */ "PATCHABLE_FUNCTION_EXIT\000" |
| 6080 | /* 28894 */ "G_BRJT\000" |
| 6081 | /* 28901 */ "G_EXTRACT_VECTOR_ELT\000" |
| 6082 | /* 28922 */ "G_INSERT_VECTOR_ELT\000" |
| 6083 | /* 28942 */ "G_FCONSTANT\000" |
| 6084 | /* 28954 */ "G_CONSTANT\000" |
| 6085 | /* 28965 */ "G_INTRINSIC_CONVERGENT\000" |
| 6086 | /* 28988 */ "STATEPOINT\000" |
| 6087 | /* 28999 */ "PATCHPOINT\000" |
| 6088 | /* 29010 */ "G_PTRTOINT\000" |
| 6089 | /* 29021 */ "G_FRINT\000" |
| 6090 | /* 29029 */ "G_INTRINSIC_LLRINT\000" |
| 6091 | /* 29048 */ "G_INTRINSIC_LRINT\000" |
| 6092 | /* 29066 */ "G_FNEARBYINT\000" |
| 6093 | /* 29079 */ "RELAXED_DOT\000" |
| 6094 | /* 29091 */ "ANDNOT\000" |
| 6095 | /* 29098 */ "G_VASTART\000" |
| 6096 | /* 29108 */ "LIFETIME_START\000" |
| 6097 | /* 29123 */ "G_INVOKE_REGION_START\000" |
| 6098 | /* 29145 */ "G_INSERT\000" |
| 6099 | /* 29154 */ "G_FSQRT\000" |
| 6100 | /* 29162 */ "G_STRICT_FSQRT\000" |
| 6101 | /* 29177 */ "G_BITCAST\000" |
| 6102 | /* 29187 */ "G_ADDRSPACE_CAST\000" |
| 6103 | /* 29204 */ "DBG_VALUE_LIST\000" |
| 6104 | /* 29219 */ "G_FPEXT\000" |
| 6105 | /* 29227 */ "G_SEXT\000" |
| 6106 | /* 29234 */ "G_ASSERT_SEXT\000" |
| 6107 | /* 29248 */ "G_ANYEXT\000" |
| 6108 | /* 29257 */ "G_ZEXT\000" |
| 6109 | /* 29264 */ "G_ASSERT_ZEXT\000" |
| 6110 | /* 29278 */ "SELECT_T\000" |
| 6111 | /* 29287 */ "G_ABDU\000" |
| 6112 | /* 29294 */ "I64_MUL_WIDE_U\000" |
| 6113 | /* 29309 */ "G_TRUNC_SSAT_U\000" |
| 6114 | /* 29324 */ "G_TRUNC_USAT_U\000" |
| 6115 | /* 29339 */ "G_FDIV\000" |
| 6116 | /* 29346 */ "G_STRICT_FDIV\000" |
| 6117 | /* 29360 */ "G_SDIV\000" |
| 6118 | /* 29367 */ "G_UDIV\000" |
| 6119 | /* 29374 */ "G_GET_FPENV\000" |
| 6120 | /* 29386 */ "G_RESET_FPENV\000" |
| 6121 | /* 29400 */ "G_SET_FPENV\000" |
| 6122 | /* 29412 */ "G_FPOW\000" |
| 6123 | /* 29419 */ "RETHROW\000" |
| 6124 | /* 29427 */ "G_VECREDUCE_FMAX\000" |
| 6125 | /* 29444 */ "G_ATOMICRMW_FMAX\000" |
| 6126 | /* 29461 */ "G_VECREDUCE_SMAX\000" |
| 6127 | /* 29478 */ "G_SMAX\000" |
| 6128 | /* 29485 */ "G_VECREDUCE_UMAX\000" |
| 6129 | /* 29502 */ "G_UMAX\000" |
| 6130 | /* 29509 */ "G_ATOMICRMW_UMAX\000" |
| 6131 | /* 29526 */ "G_ATOMICRMW_MAX\000" |
| 6132 | /* 29542 */ "G_FRAME_INDEX\000" |
| 6133 | /* 29556 */ "G_SBFX\000" |
| 6134 | /* 29563 */ "G_UBFX\000" |
| 6135 | /* 29570 */ "G_SMULFIX\000" |
| 6136 | /* 29580 */ "G_UMULFIX\000" |
| 6137 | /* 29590 */ "G_SDIVFIX\000" |
| 6138 | /* 29600 */ "G_UDIVFIX\000" |
| 6139 | /* 29610 */ "CATCH_LEGACY\000" |
| 6140 | /* 29623 */ "CATCH_ALL_LEGACY\000" |
| 6141 | /* 29640 */ "G_MEMCPY\000" |
| 6142 | /* 29649 */ "TABLE_COPY\000" |
| 6143 | /* 29660 */ "CONVERGENCECTRL_ENTRY\000" |
| 6144 | /* 29682 */ "END_TRY\000" |
| 6145 | /* 29690 */ "G_CTLZ\000" |
| 6146 | /* 29697 */ "G_CTTZ\000" |
| 6147 | /* 29704 */ "ARGUMENT_funcref\000" |
| 6148 | /* 29721 */ "ARGUMENT_externref\000" |
| 6149 | /* 29740 */ "ARGUMENT_exnref\000" |
| 6150 | /* 29756 */ "EXTRACT_LANE_I8x16_s\000" |
| 6151 | /* 29777 */ "EXTRACT_LANE_I16x8_s\000" |
| 6152 | /* 29798 */ "EXTRACT_LANE_I8x16_u\000" |
| 6153 | /* 29819 */ "EXTRACT_LANE_I16x8_u\000" |
| 6154 | }; |
| 6155 | #ifdef __GNUC__ |
| 6156 | #pragma GCC diagnostic pop |
| 6157 | #endif |
| 6158 | |
| 6159 | extern const unsigned WebAssemblyInstrNameIndices[] = { |
| 6160 | 12876U, 13319U, 14263U, 13786U, 12959U, 12940U, 12968U, 13147U, |
| 6161 | 12654U, 12669U, 11780U, 11767U, 12696U, 14830U, 11624U, 29204U, |
| 6162 | 12610U, 12872U, 12949U, 11293U, 29655U, 12916U, 11447U, 29108U, |
| 6163 | 11092U, 11216U, 11266U, 13954U, 13125U, 28999U, 11199U, 14198U, |
| 6164 | 12789U, 28988U, 11521U, 14171U, 14158U, 14324U, 28847U, 28870U, |
| 6165 | 13048U, 13104U, 13077U, 12985U, 11606U, 14289U, 13908U, 11510U, |
| 6166 | 29660U, 14451U, 14119U, 11672U, 29234U, 29264U, 13616U, 10989U, |
| 6167 | 10679U, 13258U, 29360U, 29367U, 13285U, 13292U, 13299U, 13309U, |
| 6168 | 11070U, 14660U, 14623U, 14711U, 29287U, 14495U, 13037U, 14483U, |
| 6169 | 13026U, 11778U, 12874U, 29542U, 11634U, 11649U, 13152U, 28767U, |
| 6170 | 14718U, 29145U, 14735U, 14546U, 10758U, 14813U, 29010U, 14687U, |
| 6171 | 29177U, 11723U, 14300U, 11173U, 10732U, 11155U, 29048U, 29029U, |
| 6172 | 13594U, 14349U, 14368U, 10890U, 10834U, 10864U, 10803U, 10875U, |
| 6173 | 10815U, 10845U, 11580U, 11534U, 11564U, 14860U, 12710U, 12727U, |
| 6174 | 11021U, 10685U, 11076U, 11037U, 14665U, 14629U, 29526U, 13742U, |
| 6175 | 29509U, 13725U, 10956U, 10662U, 29444U, 13660U, 13414U, 13361U, |
| 6176 | 13535U, 13473U, 14016U, 13994U, 11114U, 28720U, 11258U, 12812U, |
| 6177 | 11105U, 28796U, 29123U, 10701U, 14918U, 28965U, 14945U, 29248U, |
| 6178 | 10750U, 28250U, 29309U, 29324U, 28954U, 28942U, 29098U, 12781U, |
| 6179 | 29227U, 12683U, 29257U, 13012U, 14435U, 14421U, 13005U, 14428U, |
| 6180 | 14680U, 13168U, 14085U, 14064U, 14092U, 14099U, 28787U, 13900U, |
| 6181 | 11314U, 13884U, 11237U, 13892U, 11306U, 13876U, 11229U, 13938U, |
| 6182 | 13930U, 12840U, 12832U, 28638U, 28628U, 28618U, 28608U, 28658U, |
| 6183 | 28648U, 29570U, 29580U, 28668U, 28681U, 29590U, 29600U, 28694U, |
| 6184 | 28707U, 10914U, 10641U, 13192U, 10622U, 10796U, 29339U, 13264U, |
| 6185 | 11759U, 29412U, 12898U, 14242U, 3559U, 9U, 12774U, 3542U, |
| 6186 | 0U, 14217U, 14249U, 12647U, 29219U, 10722U, 12880U, 12889U, |
| 6187 | 14046U, 14055U, 28741U, 28754U, 14698U, 13631U, 14847U, 11732U, |
| 6188 | 13559U, 13569U, 11363U, 11378U, 13350U, 13403U, 13459U, 13521U, |
| 6189 | 29374U, 29400U, 29386U, 11322U, 11350U, 11335U, 12744U, 12759U, |
| 6190 | 10995U, 12930U, 13694U, 29478U, 13718U, 29502U, 14705U, 11146U, |
| 6191 | 11136U, 14258U, 28894U, 11393U, 14527U, 14507U, 28922U, 28901U, |
| 6192 | 14561U, 14592U, 14578U, 14900U, 29697U, 13821U, 29690U, 13802U, |
| 6193 | 14750U, 14140U, 14038U, 11593U, 13234U, 12823U, 14442U, 13018U, |
| 6194 | 14781U, 13766U, 14788U, 13587U, 14773U, 13758U, 13579U, 3550U, |
| 6195 | 12864U, 12856U, 12848U, 29154U, 14474U, 29021U, 29066U, 29187U, |
| 6196 | 14276U, 11420U, 10779U, 11701U, 11549U, 10942U, 10648U, 13220U, |
| 6197 | 29346U, 13271U, 10628U, 29162U, 14226U, 14071U, 14798U, 14388U, |
| 6198 | 14404U, 29640U, 11494U, 11713U, 28861U, 13946U, 11478U, 13987U, |
| 6199 | 13963U, 13975U, 10921U, 13199U, 10897U, 13175U, 29427U, 13643U, |
| 6200 | 13382U, 13329U, 13497U, 13435U, 10973U, 13242U, 11054U, 14645U, |
| 6201 | 14607U, 29461U, 13677U, 29485U, 13701U, 29556U, 29563U, 14761U, |
| 6202 | 28167U, 14987U, 28197U, 28827U, 28297U, 28836U, 28308U, 11278U, |
| 6203 | 26931U, 14757U, 28163U, 14983U, 28193U, 9773U, 25908U, 2641U, |
| 6204 | 17875U, 8049U, 23946U, 6956U, 22675U, 3761U, 19148U, 10034U, |
| 6205 | 26211U, 8371U, 24316U, 4071U, 19504U, 9155U, 25192U, 9644U, |
| 6206 | 25757U, 2510U, 17716U, 7896U, 23769U, 6826U, 22517U, 3608U, |
| 6207 | 18971U, 9938U, 26099U, 2960U, 18242U, 8256U, 24183U, 7275U, |
| 6208 | 23042U, 3956U, 19371U, 9069U, 25092U, 10150U, 26343U, 9227U, |
| 6209 | 25276U, 10378U, 26603U, 9409U, 25486U, 13859U, 28087U, 14183U, |
| 6210 | 28135U, 9967U, 26132U, 8304U, 24237U, 4004U, 19425U, 9098U, |
| 6211 | 25125U, 11050U, 29091U, 28335U, 2968U, 18252U, 7283U, 23052U, |
| 6212 | 26904U, 11693U, 27045U, 29740U, 28479U, 29721U, 28458U, 3501U, |
| 6213 | 18877U, 7814U, 23675U, 29704U, 28439U, 3529U, 18909U, 7842U, |
| 6214 | 23707U, 9605U, 25712U, 7799U, 23658U, 7827U, 23690U, 3486U, |
| 6215 | 18860U, 3514U, 18892U, 9012U, 25027U, 9027U, 25044U, 11245U, |
| 6216 | 26916U, 743U, 15787U, 5059U, 20588U, 1865U, 17003U, 6181U, |
| 6217 | 21804U, 1841U, 16977U, 6157U, 21778U, 767U, 15813U, 5083U, |
| 6218 | 20614U, 1889U, 17029U, 6205U, 21830U, 201U, 15201U, 4517U, |
| 6219 | 20002U, 1116U, 16194U, 5432U, 20995U, 221U, 15223U, 4537U, |
| 6220 | 20024U, 1163U, 16245U, 5479U, 21046U, 297U, 15305U, 4613U, |
| 6221 | 20106U, 1266U, 16356U, 5582U, 21157U, 394U, 15410U, 4710U, |
| 6222 | 20211U, 1394U, 16494U, 5710U, 21295U, 637U, 15671U, 4953U, |
| 6223 | 20472U, 1718U, 16842U, 6034U, 21643U, 125U, 15119U, 4441U, |
| 6224 | 19920U, 1040U, 16112U, 5356U, 20913U, 482U, 15504U, 4798U, |
| 6225 | 20305U, 1510U, 16618U, 5826U, 21419U, 561U, 15589U, 4877U, |
| 6226 | 20390U, 1616U, 16732U, 5932U, 21533U, 1136U, 16216U, 5452U, |
| 6227 | 21017U, 1239U, 16327U, 5555U, 21128U, 1363U, 16461U, 5679U, |
| 6228 | 21262U, 1692U, 16814U, 6008U, 21615U, 1013U, 16083U, 5329U, |
| 6229 | 20884U, 1482U, 16588U, 5798U, 21389U, 1589U, 16703U, 5905U, |
| 6230 | 21504U, 248U, 15252U, 4564U, 20053U, 1190U, 16274U, 5506U, |
| 6231 | 21075U, 324U, 15334U, 4640U, 20135U, 1293U, 16385U, 5609U, |
| 6232 | 21186U, 425U, 15443U, 4741U, 20244U, 1425U, 16527U, 5741U, |
| 6233 | 21328U, 663U, 15699U, 4979U, 20500U, 1744U, 16870U, 6060U, |
| 6234 | 21671U, 152U, 15148U, 4468U, 19949U, 1067U, 16141U, 5383U, |
| 6235 | 20942U, 510U, 15534U, 4826U, 20335U, 1538U, 16648U, 5854U, |
| 6236 | 21449U, 588U, 15618U, 4904U, 20419U, 1643U, 16761U, 5959U, |
| 6237 | 21562U, 274U, 15280U, 4590U, 20081U, 1216U, 16302U, 5532U, |
| 6238 | 21103U, 350U, 15362U, 4666U, 20163U, 1319U, 16413U, 5635U, |
| 6239 | 21214U, 455U, 15475U, 4771U, 20276U, 1455U, 16559U, 5771U, |
| 6240 | 21360U, 688U, 15726U, 5004U, 20527U, 1769U, 16897U, 6085U, |
| 6241 | 21698U, 178U, 15176U, 4494U, 19977U, 1093U, 16169U, 5409U, |
| 6242 | 20970U, 537U, 15563U, 4853U, 20364U, 1565U, 16677U, 5881U, |
| 6243 | 21478U, 614U, 15646U, 4930U, 20447U, 1669U, 16789U, 5985U, |
| 6244 | 21590U, 80U, 15070U, 4396U, 19871U, 968U, 16034U, 5284U, |
| 6245 | 20835U, 945U, 16009U, 5261U, 20810U, 103U, 15095U, 4419U, |
| 6246 | 19896U, 991U, 16059U, 5307U, 20860U, 373U, 15387U, 4689U, |
| 6247 | 20188U, 1342U, 16438U, 5658U, 21239U, 10337U, 26556U, 9368U, |
| 6248 | 25439U, 9991U, 26160U, 8328U, 24265U, 4028U, 19453U, 9122U, |
| 6249 | 25153U, 28777U, 28265U, 12910U, 28020U, 14260U, 12641U, 28000U, |
| 6250 | 28152U, 2990U, 18278U, 7305U, 23078U, 14890U, 28181U, 13063U, |
| 6251 | 28813U, 28281U, 12587U, 27952U, 28032U, 12806U, 13137U, 29623U, |
| 6252 | 28397U, 12596U, 27963U, 28039U, 29610U, 28382U, 12573U, 27936U, |
| 6253 | 28008U, 9720U, 25845U, 2577U, 17797U, 7972U, 23857U, 6892U, |
| 6254 | 22597U, 3684U, 19059U, 3462U, 18830U, 7775U, 23628U, 2885U, |
| 6255 | 18153U, 7200U, 22953U, 3324U, 18668U, 7654U, 23485U, 7855U, |
| 6256 | 23722U, 3567U, 18924U, 9911U, 26068U, 8229U, 24152U, 3929U, |
| 6257 | 19340U, 9042U, 25061U, 2594U, 17818U, 6909U, 22618U, 12561U, |
| 6258 | 27922U, 12328U, 27661U, 2943U, 18221U, 7258U, 23021U, 12058U, |
| 6259 | 27363U, 3453U, 18819U, 7766U, 23617U, 9595U, 25700U, 3478U, |
| 6260 | 18850U, 7791U, 23648U, 14148U, 28123U, 11402U, 26963U, 11615U, |
| 6261 | 27034U, 9838U, 25985U, 2927U, 18201U, 8114U, 24023U, 7242U, |
| 6262 | 23001U, 3826U, 19225U, 3214U, 18542U, 7544U, 23359U, 3443U, |
| 6263 | 18807U, 7756U, 23605U, 29087U, 28329U, 12413U, 27756U, 12153U, |
| 6264 | 27468U, 2615U, 17843U, 6930U, 22643U, 11867U, 27150U, 3035U, |
| 6265 | 18333U, 7363U, 23148U, 9511U, 25604U, 11588U, 27027U, 11101U, |
| 6266 | 12906U, 28016U, 13773U, 28051U, 12634U, 27991U, 14110U, 28112U, |
| 6267 | 26910U, 29682U, 28429U, 11433U, 26983U, 3470U, 18840U, 7783U, |
| 6268 | 23638U, 9752U, 25883U, 2624U, 17854U, 8028U, 23921U, 6939U, |
| 6269 | 22654U, 3740U, 19123U, 10025U, 26200U, 3044U, 18344U, 8362U, |
| 6270 | 24305U, 7372U, 23159U, 4062U, 19493U, 9146U, 25181U, 10066U, |
| 6271 | 26249U, 8403U, 24354U, 4103U, 19542U, 10305U, 26520U, 8551U, |
| 6272 | 24524U, 4205U, 19658U, 10208U, 26409U, 8469U, 24430U, 4157U, |
| 6273 | 19604U, 10416U, 26647U, 8617U, 24600U, 4237U, 19694U, 9691U, |
| 6274 | 25812U, 7943U, 23824U, 3655U, 19026U, 29777U, 28520U, 29819U, |
| 6275 | 28566U, 8285U, 24216U, 3985U, 19404U, 29756U, 28497U, 29798U, |
| 6276 | 28543U, 3178U, 18502U, 7508U, 23319U, 3407U, 18767U, 7720U, |
| 6277 | 23565U, 6869U, 22570U, 3264U, 18600U, 3196U, 18522U, 7526U, |
| 6278 | 23339U, 3425U, 18787U, 7738U, 23585U, 2553U, 17769U, 7594U, |
| 6279 | 23417U, 13840U, 28066U, 9761U, 25894U, 2631U, 17863U, 8037U, |
| 6280 | 23932U, 6946U, 22663U, 3749U, 19134U, 2416U, 17610U, 6732U, |
| 6281 | 22411U, 2454U, 17652U, 6770U, 22453U, 2435U, 17631U, 6751U, |
| 6282 | 22432U, 2473U, 17673U, 6789U, 22474U, 9654U, 25769U, 2532U, |
| 6283 | 17742U, 7906U, 23781U, 6848U, 22543U, 3618U, 18983U, 10044U, |
| 6284 | 26223U, 3122U, 18434U, 8381U, 24328U, 7452U, 23251U, 4081U, |
| 6285 | 19516U, 9165U, 25204U, 10283U, 26494U, 3351U, 18699U, 8529U, |
| 6286 | 24498U, 7664U, 23497U, 9334U, 25399U, 12456U, 27805U, 12205U, |
| 6287 | 27526U, 2772U, 18022U, 7087U, 22822U, 11913U, 27202U, 3235U, |
| 6288 | 18567U, 7565U, 23384U, 9533U, 25630U, 12508U, 27863U, 12266U, |
| 6289 | 27593U, 2821U, 18077U, 7136U, 22877U, 11968U, 27263U, 3284U, |
| 6290 | 18622U, 7614U, 23439U, 9564U, 25665U, 9795U, 25934U, 2850U, |
| 6291 | 18110U, 8071U, 23972U, 7165U, 22910U, 3783U, 19174U, 10186U, |
| 6292 | 26383U, 3160U, 18480U, 8447U, 24404U, 7490U, 23297U, 4135U, |
| 6293 | 19578U, 9243U, 25294U, 10394U, 26621U, 3389U, 18745U, 8595U, |
| 6294 | 24574U, 7702U, 23543U, 9425U, 25504U, 3068U, 18374U, 3087U, |
| 6295 | 18395U, 2801U, 18055U, 2649U, 17885U, 6964U, 22685U, 2681U, |
| 6296 | 17921U, 6996U, 22721U, 2895U, 18165U, 7210U, 22965U, 2721U, |
| 6297 | 17965U, 7036U, 22765U, 7350U, 23133U, 9485U, 25574U, 7415U, |
| 6298 | 23210U, 7396U, 23189U, 7434U, 23231U, 3105U, 18415U, 3334U, |
| 6299 | 18680U, 26948U, 28212U, 29294U, 28355U, 7116U, 22855U, 9474U, |
| 6300 | 25561U, 2665U, 17903U, 6980U, 22703U, 2701U, 17943U, 7016U, |
| 6301 | 22743U, 2911U, 18183U, 7226U, 22983U, 2741U, 17987U, 7056U, |
| 6302 | 22787U, 12638U, 27995U, 10266U, 26475U, 8512U, 24479U, 4188U, |
| 6303 | 19639U, 9304U, 25365U, 9663U, 25780U, 2539U, 17751U, 7915U, |
| 6304 | 23792U, 6855U, 22552U, 3627U, 18994U, 10055U, 26236U, 3131U, |
| 6305 | 18445U, 8392U, 24341U, 7461U, 23262U, 4092U, 19529U, 9176U, |
| 6306 | 25217U, 10294U, 26507U, 3360U, 18710U, 8540U, 24511U, 7673U, |
| 6307 | 23508U, 9345U, 25412U, 2273U, 17451U, 6589U, 22252U, 710U, |
| 6308 | 15750U, 5026U, 20551U, 1808U, 16940U, 6124U, 21741U, 750U, |
| 6309 | 15794U, 5066U, 20595U, 1872U, 17010U, 6188U, 21811U, 2239U, |
| 6310 | 17413U, 6555U, 22214U, 1791U, 16921U, 6107U, 21722U, 1848U, |
| 6311 | 16984U, 6164U, 21785U, 2256U, 17432U, 6572U, 22233U, 2290U, |
| 6312 | 17470U, 6606U, 22271U, 727U, 15769U, 5043U, 20570U, 1825U, |
| 6313 | 16959U, 6141U, 21760U, 774U, 15820U, 5090U, 20621U, 1896U, |
| 6314 | 17036U, 6212U, 21837U, 2144U, 17310U, 6460U, 22111U, 1992U, |
| 6315 | 17142U, 6308U, 21943U, 870U, 15926U, 5186U, 20727U, 2168U, |
| 6316 | 17336U, 6484U, 22137U, 2016U, 17168U, 6332U, 21969U, 894U, |
| 6317 | 15952U, 5210U, 20753U, 18U, 15000U, 4334U, 19801U, 53U, |
| 6318 | 15039U, 4369U, 19840U, 918U, 15978U, 5234U, 20779U, 208U, |
| 6319 | 15208U, 4524U, 20009U, 1123U, 16201U, 5439U, 21002U, 2040U, |
| 6320 | 17194U, 6356U, 21995U, 815U, 15865U, 5131U, 20666U, 1937U, |
| 6321 | 17081U, 6253U, 21882U, 2107U, 17269U, 6423U, 22070U, 2078U, |
| 6322 | 17236U, 6394U, 22037U, 832U, 15884U, 5148U, 20685U, 1954U, |
| 6323 | 17100U, 6270U, 21901U, 12474U, 27825U, 12226U, 27549U, 2787U, |
| 6324 | 18039U, 7102U, 22839U, 11932U, 27223U, 3250U, 18584U, 7580U, |
| 6325 | 23401U, 9549U, 25648U, 12526U, 27883U, 12287U, 27616U, 2836U, |
| 6326 | 18094U, 7151U, 22894U, 11987U, 27284U, 3299U, 18639U, 7629U, |
| 6327 | 23456U, 9580U, 25683U, 12343U, 27678U, 12071U, 27378U, 2518U, |
| 6328 | 17726U, 6834U, 22527U, 11793U, 27068U, 2976U, 18262U, 7291U, |
| 6329 | 23062U, 9496U, 25587U, 14114U, 28116U, 9804U, 25945U, 2857U, |
| 6330 | 18119U, 8080U, 23983U, 7172U, 22919U, 3792U, 19185U, 10197U, |
| 6331 | 26396U, 3169U, 18491U, 8458U, 24417U, 7499U, 23308U, 4146U, |
| 6332 | 19591U, 9254U, 25307U, 10405U, 26634U, 3398U, 18756U, 8606U, |
| 6333 | 24587U, 7711U, 23554U, 9436U, 25517U, 9643U, 25756U, 7895U, |
| 6334 | 23768U, 3607U, 18970U, 9849U, 25998U, 2935U, 18211U, 8138U, |
| 6335 | 24049U, 7250U, 23011U, 3850U, 19251U, 10242U, 26447U, 8488U, |
| 6336 | 24451U, 9280U, 25337U, 10450U, 26685U, 8636U, 24621U, 9462U, |
| 6337 | 25547U, 2389U, 17579U, 6705U, 22380U, 2364U, 17552U, 6680U, |
| 6338 | 22353U, 790U, 15838U, 5106U, 20639U, 1912U, 17054U, 6228U, |
| 6339 | 21855U, 2400U, 17592U, 6716U, 22393U, 2223U, 17395U, 6539U, |
| 6340 | 22196U, 2317U, 17501U, 6633U, 22302U, 2306U, 17488U, 6622U, |
| 6341 | 22289U, 9742U, 25871U, 2607U, 17833U, 8007U, 23896U, 6922U, |
| 6342 | 22633U, 3719U, 19098U, 10086U, 26271U, 8423U, 24376U, 9187U, |
| 6343 | 25230U, 10325U, 26542U, 8571U, 24546U, 9356U, 25425U, 9731U, |
| 6344 | 25858U, 2586U, 17808U, 7983U, 23870U, 6901U, 22608U, 3695U, |
| 6345 | 19072U, 10015U, 26188U, 3027U, 18323U, 8352U, 24293U, 7342U, |
| 6346 | 23123U, 4052U, 19481U, 10227U, 26430U, 9265U, 25320U, 10435U, |
| 6347 | 26668U, 9447U, 25530U, 9824U, 25969U, 2873U, 18139U, 8100U, |
| 6348 | 24007U, 7188U, 22939U, 3812U, 19209U, 9710U, 25833U, 2569U, |
| 6349 | 17787U, 7962U, 23845U, 6884U, 22587U, 3674U, 19047U, 9981U, |
| 6350 | 26148U, 8318U, 24253U, 4018U, 19441U, 9112U, 25141U, 9682U, |
| 6351 | 25801U, 2546U, 17760U, 7934U, 23813U, 6862U, 22561U, 3646U, |
| 6352 | 19015U, 9958U, 26121U, 3003U, 18293U, 8276U, 24205U, 7318U, |
| 6353 | 23093U, 3976U, 19393U, 9089U, 25114U, 9642U, 25755U, 7894U, |
| 6354 | 23767U, 3606U, 18969U, 14106U, 28106U, 29094U, 28338U, 14471U, |
| 6355 | 3052U, 18354U, 7380U, 23169U, 28158U, 9848U, 25997U, 8148U, |
| 6356 | 24061U, 3860U, 19263U, 9741U, 25870U, 8017U, 23908U, 3729U, |
| 6357 | 19110U, 3313U, 18655U, 7643U, 23472U, 9321U, 25384U, 10166U, |
| 6358 | 26361U, 12005U, 27304U, 10713U, 26875U, 12394U, 27735U, 12131U, |
| 6359 | 27444U, 11847U, 27128U, 12378U, 27717U, 12112U, 27423U, 11830U, |
| 6360 | 27109U, 12022U, 27323U, 29079U, 11005U, 26886U, 28589U, 28229U, |
| 6361 | 28321U, 10110U, 26299U, 11462U, 27009U, 3140U, 18456U, 7470U, |
| 6362 | 23273U, 3369U, 18721U, 7682U, 23519U, 9672U, 25791U, 7924U, |
| 6363 | 23803U, 3636U, 19005U, 9948U, 26111U, 8266U, 24195U, 3966U, |
| 6364 | 19383U, 9079U, 25104U, 29419U, 28372U, 13852U, 28078U, 13068U, |
| 6365 | 28809U, 28277U, 12583U, 27948U, 28028U, 3018U, 18312U, 7333U, |
| 6366 | 23112U, 3059U, 18363U, 7387U, 23178U, 12425U, 27770U, 12168U, |
| 6367 | 27485U, 2761U, 18009U, 7076U, 22809U, 11880U, 27165U, 3224U, |
| 6368 | 18554U, 7554U, 23371U, 29278U, 28344U, 9521U, 25616U, 10005U, |
| 6369 | 26176U, 3010U, 18302U, 8342U, 24281U, 7325U, 23102U, 4042U, |
| 6370 | 19469U, 9136U, 25169U, 10098U, 26285U, 3150U, 18468U, 8435U, |
| 6371 | 24390U, 7480U, 23285U, 4123U, 19564U, 9199U, 25244U, 10350U, |
| 6372 | 26571U, 3379U, 18733U, 8583U, 24560U, 7692U, 23531U, 4225U, |
| 6373 | 19680U, 9381U, 25454U, 11454U, 26999U, 8124U, 24035U, 3836U, |
| 6374 | 19237U, 7993U, 23882U, 3705U, 19084U, 9783U, 25920U, 8059U, |
| 6375 | 23958U, 3771U, 19160U, 10254U, 26461U, 8500U, 24465U, 4176U, |
| 6376 | 19625U, 9292U, 25351U, 9813U, 25956U, 2864U, 18128U, 8089U, |
| 6377 | 23994U, 7179U, 22928U, 3801U, 19196U, 87U, 15077U, 4403U, |
| 6378 | 19878U, 975U, 16041U, 5291U, 20842U, 952U, 16016U, 5268U, |
| 6379 | 20817U, 110U, 15102U, 4426U, 19903U, 998U, 16066U, 5314U, |
| 6380 | 20867U, 35U, 15019U, 4351U, 19820U, 66U, 15054U, 4382U, |
| 6381 | 19855U, 931U, 15993U, 5247U, 20794U, 380U, 15394U, 4696U, |
| 6382 | 20195U, 1349U, 16445U, 5665U, 21246U, 2123U, 17287U, 6439U, |
| 6383 | 22088U, 1971U, 17119U, 6287U, 21920U, 849U, 15903U, 5165U, |
| 6384 | 20704U, 2057U, 17213U, 6373U, 22014U, 2092U, 17252U, 6408U, |
| 6385 | 22053U, 9620U, 25729U, 2492U, 17694U, 7872U, 23741U, 6808U, |
| 6386 | 22495U, 3584U, 18943U, 9928U, 26087U, 2952U, 18232U, 8246U, |
| 6387 | 24171U, 7267U, 23032U, 3946U, 19359U, 9059U, 25080U, 10134U, |
| 6388 | 26325U, 9211U, 25258U, 10362U, 26585U, 9393U, 25468U, 11470U, |
| 6389 | 27017U, 29649U, 28416U, 12360U, 27697U, 12091U, 27400U, 11811U, |
| 6390 | 27088U, 12439U, 27786U, 12185U, 27504U, 11895U, 27182U, 12543U, |
| 6391 | 27902U, 12307U, 27638U, 12039U, 27342U, 12491U, 27844U, 12246U, |
| 6392 | 27571U, 11950U, 27243U, 11748U, 27055U, 12349U, 27684U, 12077U, |
| 6393 | 27384U, 2524U, 17732U, 6840U, 22533U, 11799U, 27074U, 2982U, |
| 6394 | 18268U, 7297U, 23068U, 9502U, 25593U, 29421U, 12624U, 27979U, |
| 6395 | 28374U, 9630U, 25741U, 2500U, 17704U, 7882U, 23753U, 6816U, |
| 6396 | 22505U, 3594U, 18955U, 29678U, 28433U, 11437U, 26987U, 11408U, |
| 6397 | 26969U, 14619U, 3051U, 18353U, 7379U, 23168U, 28157U, 2333U, |
| 6398 | 17519U, 2192U, 17362U, 6649U, 22320U, 6508U, 22163U, 3871U, |
| 6399 | 19276U, 3891U, 19298U, 9859U, 26010U, 8159U, 24074U, 10462U, |
| 6400 | 26699U, 8806U, 24801U, 10559U, 26806U, 8926U, 24933U, 10486U, |
| 6401 | 26725U, 8830U, 24827U, 4256U, 19715U, 10583U, 26832U, 8950U, |
| 6402 | 24959U, 4295U, 19758U, 10506U, 26747U, 8873U, 24874U, 4276U, |
| 6403 | 19737U, 10603U, 26854U, 8993U, 25006U, 4315U, 19780U, 10525U, |
| 6404 | 26768U, 8892U, 24895U, 10542U, 26787U, 8909U, 24914U, 8648U, |
| 6405 | 24635U, 8722U, 24713U, 8684U, 24673U, 8763U, 24756U, 8211U, |
| 6406 | 24132U, 3911U, 19320U, 9877U, 26030U, 8177U, 24094U, 8850U, |
| 6407 | 24849U, 8970U, 24981U, 9894U, 26049U, 8194U, 24113U, |
| 6408 | }; |
| 6409 | |
| 6410 | extern const int16_t WebAssemblyRegClassByHwModeTables[2][1] = { |
| 6411 | { // DefaultMode |
| 6412 | WebAssembly::I32RegClassID, // wasm_ptr_rc |
| 6413 | }, |
| 6414 | { // WASM64 |
| 6415 | WebAssembly::I64RegClassID, // wasm_ptr_rc |
| 6416 | }, |
| 6417 | }; |
| 6418 | |
| 6419 | static inline void InitWebAssemblyMCInstrInfo(MCInstrInfo *II) { |
| 6420 | II->InitMCInstrInfo(WebAssemblyDescs.Insts, WebAssemblyInstrNameIndices, WebAssemblyInstrNameData, nullptr, nullptr, 1983, &WebAssemblyRegClassByHwModeTables[0][0], 1); |
| 6421 | } |
| 6422 | |
| 6423 | |
| 6424 | } // namespace llvm |
| 6425 | |
| 6426 | #endif // GET_INSTRINFO_MC_DESC |
| 6427 | |
| 6428 | #ifdef GET_INSTRINFO_HEADER |
| 6429 | #undef GET_INSTRINFO_HEADER |
| 6430 | |
| 6431 | namespace llvm { |
| 6432 | |
| 6433 | struct WebAssemblyGenInstrInfo : public TargetInstrInfo { |
| 6434 | explicit WebAssemblyGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u); |
| 6435 | ~WebAssemblyGenInstrInfo() override = default; |
| 6436 | }; |
| 6437 | extern const int16_t WebAssemblyRegClassByHwModeTables[2][1]; |
| 6438 | |
| 6439 | } // namespace llvm |
| 6440 | |
| 6441 | namespace llvm::WebAssembly { |
| 6442 | |
| 6443 | |
| 6444 | } // namespace llvm::WebAssembly |
| 6445 | |
| 6446 | #endif // GET_INSTRINFO_HEADER |
| 6447 | |
| 6448 | #ifdef GET_INSTRINFO_HELPER_DECLS |
| 6449 | #undef GET_INSTRINFO_HELPER_DECLS |
| 6450 | |
| 6451 | |
| 6452 | #endif // GET_INSTRINFO_HELPER_DECLS |
| 6453 | |
| 6454 | #ifdef GET_INSTRINFO_HELPERS |
| 6455 | #undef GET_INSTRINFO_HELPERS |
| 6456 | |
| 6457 | |
| 6458 | #endif // GET_INSTRINFO_HELPERS |
| 6459 | |
| 6460 | #ifdef GET_INSTRINFO_CTOR_DTOR |
| 6461 | #undef GET_INSTRINFO_CTOR_DTOR |
| 6462 | |
| 6463 | namespace llvm { |
| 6464 | |
| 6465 | extern const WebAssemblyInstrTable WebAssemblyDescs; |
| 6466 | extern const unsigned WebAssemblyInstrNameIndices[]; |
| 6467 | extern const char WebAssemblyInstrNameData[]; |
| 6468 | WebAssemblyGenInstrInfo::WebAssemblyGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode) |
| 6469 | : TargetInstrInfo(TRI, CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode, WebAssemblyRegClassByHwModeTables[STI.getHwMode(MCSubtargetInfo::HwMode_RegInfo)]) { |
| 6470 | InitMCInstrInfo(WebAssemblyDescs.Insts, WebAssemblyInstrNameIndices, WebAssemblyInstrNameData, nullptr, nullptr, 1983, &WebAssemblyRegClassByHwModeTables[0][0], 1); |
| 6471 | } |
| 6472 | |
| 6473 | } // namespace llvm |
| 6474 | |
| 6475 | #endif // GET_INSTRINFO_CTOR_DTOR |
| 6476 | |
| 6477 | #ifdef GET_INSTRINFO_OPERAND_ENUM |
| 6478 | #undef GET_INSTRINFO_OPERAND_ENUM |
| 6479 | |
| 6480 | namespace llvm::WebAssembly { |
| 6481 | |
| 6482 | enum class OpName : uint8_t { |
| 6483 | dst = 0, |
| 6484 | order = 1, |
| 6485 | p2align = 2, |
| 6486 | off = 3, |
| 6487 | addr = 4, |
| 6488 | val = 5, |
| 6489 | exp = 6, |
| 6490 | new_ = 7, |
| 6491 | idx = 8, |
| 6492 | vec = 9, |
| 6493 | count = 10, |
| 6494 | timeout = 11, |
| 6495 | NUM_OPERAND_NAMES = 12, |
| 6496 | }; // enum class OpName |
| 6497 | |
| 6498 | LLVM_READONLY int16_t getNamedOperandIdx(uint32_t Opcode, OpName Name); |
| 6499 | LLVM_READONLY OpName getOperandIdxName(uint32_t Opcode, int16_t Idx); |
| 6500 | |
| 6501 | } // namespace llvm::WebAssembly |
| 6502 | |
| 6503 | #endif // GET_INSTRINFO_OPERAND_ENUM |
| 6504 | |
| 6505 | #ifdef GET_INSTRINFO_NAMED_OPS |
| 6506 | #undef GET_INSTRINFO_NAMED_OPS |
| 6507 | |
| 6508 | namespace llvm::WebAssembly { |
| 6509 | |
| 6510 | LLVM_READONLY static uint8_t getInstructionIndexForOpLookup(uint32_t Opcode) { |
| 6511 | static constexpr uint8_t InstructionIndex[] = { |
| 6512 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6513 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6514 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6515 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6516 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6517 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6518 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6519 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6520 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6521 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6522 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6523 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6524 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6525 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6526 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6527 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6528 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6529 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6530 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6531 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6532 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6533 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6534 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6535 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6536 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6537 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6538 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6539 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6540 | 0, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, |
| 6541 | 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 3, 2, 3, |
| 6542 | 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 4, 2, 4, |
| 6543 | 2, 4, 2, 4, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, |
| 6544 | 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, |
| 6545 | 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 4, 2, 4, |
| 6546 | 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, |
| 6547 | 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, |
| 6548 | 2, 4, 2, 4, 2, 4, 2, 4, 2, 3, 2, 3, 2, 3, 2, 3, |
| 6549 | 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, |
| 6550 | 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, |
| 6551 | 2, 3, 2, 3, 2, 3, 2, 3, 2, 4, 2, 4, 2, 4, 2, 4, |
| 6552 | 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, |
| 6553 | 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, |
| 6554 | 2, 5, 2, 5, 2, 5, 2, 5, 2, 5, 2, 5, 2, 5, 2, 5, |
| 6555 | 2, 5, 2, 5, 2, 5, 2, 5, 2, 5, 2, 5, 2, 0, 0, 0, |
| 6556 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6557 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6558 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6559 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6560 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6561 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6562 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6563 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6564 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6565 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6566 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6567 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6568 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6569 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6570 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6571 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6572 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6573 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6574 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6575 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6576 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6577 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6578 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6579 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6580 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6581 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6582 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6583 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6584 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6585 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 7, 6, 7, 6, |
| 6586 | 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, |
| 6587 | 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, |
| 6588 | 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, |
| 6589 | 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, |
| 6590 | 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, |
| 6591 | 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 8, |
| 6592 | 9, 8, 9, 8, 9, 8, 9, 8, 9, 8, 9, 8, 9, 8, 9, 6, |
| 6593 | 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 0, 0, 0, 0, 0, |
| 6594 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6595 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6596 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6597 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6598 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6599 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6600 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 2, 10, |
| 6601 | 2, 11, 2, 11, 2, 11, 2, 11, 2, 0, 0, 0, 0, 0, 0, 0, |
| 6602 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6603 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6604 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6605 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6606 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6607 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6608 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6609 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6610 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6611 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6612 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6613 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6614 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6615 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6616 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6617 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6618 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6619 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6620 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 12, 7, 12, |
| 6621 | 7, 12, 7, 12, 7, 12, 7, 12, 7, 12, 7, 12, 7, 12, 7, 12, |
| 6622 | 7, 12, 7, 12, 7, 12, 7, 12, 7, 12, 7, 12, 7, 12, 7, 12, |
| 6623 | 7, 12, 7, 12, 7, 13, 9, 13, 9, 13, 9, 13, 9, 13, 9, 13, |
| 6624 | 9, 13, 9, 13, 9, 14, 7, 14, 7, 0, 0, 0, 0, 0, 0, 0, |
| 6625 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6626 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6627 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6628 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6629 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6630 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6631 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6632 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6633 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6634 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6635 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6636 | }; |
| 6637 | return InstructionIndex[Opcode]; |
| 6638 | } |
| 6639 | LLVM_READONLY int16_t getNamedOperandIdx(uint32_t Opcode, OpName Name) { |
| 6640 | assert(Name != OpName::NUM_OPERAND_NAMES); |
| 6641 | static constexpr int8_t OperandMap[][12] = { |
| 6642 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, }, |
| 6643 | {0, 1, 2, 3, 4, -1, -1, -1, -1, -1, -1, -1, }, |
| 6644 | {-1, 0, 1, 2, -1, -1, -1, -1, -1, -1, -1, -1, }, |
| 6645 | {0, 1, 2, 3, 4, 5, -1, -1, -1, -1, -1, -1, }, |
| 6646 | {0, 1, 2, 3, 4, -1, 5, 6, -1, -1, -1, -1, }, |
| 6647 | {-1, 0, 1, 2, 3, 4, -1, -1, -1, -1, -1, -1, }, |
| 6648 | {0, -1, 1, 2, 3, -1, -1, -1, -1, -1, -1, -1, }, |
| 6649 | {-1, -1, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, }, |
| 6650 | {0, -1, 1, 2, 4, -1, -1, -1, 3, 5, -1, -1, }, |
| 6651 | {-1, -1, 0, 1, -1, -1, -1, -1, 2, -1, -1, -1, }, |
| 6652 | {0, 1, 2, 3, 4, -1, -1, -1, -1, -1, 5, -1, }, |
| 6653 | {0, 1, 2, 3, 4, -1, 5, -1, -1, -1, -1, 6, }, |
| 6654 | {-1, -1, 0, 1, 2, 3, -1, -1, -1, -1, -1, -1, }, |
| 6655 | {-1, -1, 0, 1, 3, -1, -1, -1, 2, 4, -1, -1, }, |
| 6656 | {-1, -1, 0, 1, 2, -1, -1, -1, -1, 3, -1, -1, }, |
| 6657 | }; |
| 6658 | unsigned InstrIdx = getInstructionIndexForOpLookup(Opcode); |
| 6659 | return OperandMap[InstrIdx][(unsigned)Name]; |
| 6660 | } |
| 6661 | LLVM_READONLY OpName getOperandIdxName(uint32_t Opcode, int16_t Idx) { |
| 6662 | assert(Idx >= 0 && Idx < 7); |
| 6663 | static constexpr OpName OperandMap[][7] = { |
| 6664 | {OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, }, |
| 6665 | {OpName::dst, OpName::order, OpName::p2align, OpName::off, OpName::addr, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, }, |
| 6666 | {OpName::order, OpName::p2align, OpName::off, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, }, |
| 6667 | {OpName::dst, OpName::order, OpName::p2align, OpName::off, OpName::addr, OpName::val, OpName::NUM_OPERAND_NAMES, }, |
| 6668 | {OpName::dst, OpName::order, OpName::p2align, OpName::off, OpName::addr, OpName::exp, OpName::new_, }, |
| 6669 | {OpName::order, OpName::p2align, OpName::off, OpName::addr, OpName::val, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, }, |
| 6670 | {OpName::dst, OpName::p2align, OpName::off, OpName::addr, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, }, |
| 6671 | {OpName::p2align, OpName::off, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, }, |
| 6672 | {OpName::dst, OpName::p2align, OpName::off, OpName::idx, OpName::addr, OpName::vec, OpName::NUM_OPERAND_NAMES, }, |
| 6673 | {OpName::p2align, OpName::off, OpName::idx, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, }, |
| 6674 | {OpName::dst, OpName::order, OpName::p2align, OpName::off, OpName::addr, OpName::count, OpName::NUM_OPERAND_NAMES, }, |
| 6675 | {OpName::dst, OpName::order, OpName::p2align, OpName::off, OpName::addr, OpName::exp, OpName::timeout, }, |
| 6676 | {OpName::p2align, OpName::off, OpName::addr, OpName::val, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, }, |
| 6677 | {OpName::p2align, OpName::off, OpName::idx, OpName::addr, OpName::vec, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, }, |
| 6678 | {OpName::p2align, OpName::off, OpName::addr, OpName::vec, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, }, |
| 6679 | }; |
| 6680 | unsigned InstrIdx = getInstructionIndexForOpLookup(Opcode); |
| 6681 | return OperandMap[InstrIdx][(unsigned)Idx]; |
| 6682 | } |
| 6683 | |
| 6684 | } // namespace llvm::WebAssembly |
| 6685 | |
| 6686 | #endif // GET_INSTRINFO_NAMED_OPS |
| 6687 | |
| 6688 | #ifdef GET_INSTRINFO_MC_HELPER_DECLS |
| 6689 | #undef GET_INSTRINFO_MC_HELPER_DECLS |
| 6690 | |
| 6691 | namespace llvm { |
| 6692 | |
| 6693 | class MCInst; |
| 6694 | class FeatureBitset; |
| 6695 | |
| 6696 | extern const int16_t WebAssemblyRegClassByHwModeTables[2][1]; |
| 6697 | |
| 6698 | namespace WebAssembly_MC { |
| 6699 | |
| 6700 | void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features); |
| 6701 | |
| 6702 | } // namespace WebAssembly_MC |
| 6703 | |
| 6704 | } // namespace llvm |
| 6705 | |
| 6706 | #endif // GET_INSTRINFO_MC_HELPER_DECLS |
| 6707 | |
| 6708 | #ifdef GET_INSTRINFO_MC_HELPERS |
| 6709 | #undef GET_INSTRINFO_MC_HELPERS |
| 6710 | |
| 6711 | namespace llvm::WebAssembly_MC { |
| 6712 | |
| 6713 | |
| 6714 | } // namespace llvm::WebAssembly_MC |
| 6715 | |
| 6716 | #endif // GET_INSTRINFO_MC_HELPERS |
| 6717 | |
| 6718 | #if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\ |
| 6719 | defined(GET_AVAILABLE_OPCODE_CHECKER) |
| 6720 | #define GET_COMPUTE_FEATURES |
| 6721 | #endif |
| 6722 | #ifdef GET_COMPUTE_FEATURES |
| 6723 | #undef GET_COMPUTE_FEATURES |
| 6724 | |
| 6725 | namespace llvm::WebAssembly_MC { |
| 6726 | |
| 6727 | // Bits for subtarget features that participate in instruction matching. |
| 6728 | enum SubtargetFeatureBits : uint8_t { |
| 6729 | Feature_HasAtomicsBit = 0, |
| 6730 | Feature_HasBulkMemoryBit = 1, |
| 6731 | Feature_HasBulkMemoryOptBit = 2, |
| 6732 | Feature_HasCallIndirectOverlongBit = 3, |
| 6733 | Feature_HasExceptionHandlingBit = 4, |
| 6734 | Feature_HasExtendedConstBit = 5, |
| 6735 | Feature_HasFP16Bit = 6, |
| 6736 | Feature_HasGCBit = 7, |
| 6737 | Feature_HasMultiMemoryBit = 8, |
| 6738 | Feature_HasMultivalueBit = 9, |
| 6739 | Feature_HasMutableGlobalsBit = 10, |
| 6740 | Feature_HasNontrappingFPToIntBit = 11, |
| 6741 | Feature_NotHasNontrappingFPToIntBit = 19, |
| 6742 | Feature_HasReferenceTypesBit = 12, |
| 6743 | Feature_HasRelaxedAtomicsBit = 13, |
| 6744 | Feature_HasRelaxedSIMDBit = 14, |
| 6745 | Feature_HasSignExtBit = 16, |
| 6746 | Feature_HasSIMD128Bit = 15, |
| 6747 | Feature_HasTailCallBit = 17, |
| 6748 | Feature_HasWideArithmeticBit = 18, |
| 6749 | }; |
| 6750 | |
| 6751 | inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) { |
| 6752 | FeatureBitset Features; |
| 6753 | if (FB[WebAssembly::FeatureAtomics]) |
| 6754 | Features.set(Feature_HasAtomicsBit); |
| 6755 | if (FB[WebAssembly::FeatureBulkMemory]) |
| 6756 | Features.set(Feature_HasBulkMemoryBit); |
| 6757 | if (FB[WebAssembly::FeatureBulkMemoryOpt]) |
| 6758 | Features.set(Feature_HasBulkMemoryOptBit); |
| 6759 | if (FB[WebAssembly::FeatureCallIndirectOverlong]) |
| 6760 | Features.set(Feature_HasCallIndirectOverlongBit); |
| 6761 | if (FB[WebAssembly::FeatureExceptionHandling]) |
| 6762 | Features.set(Feature_HasExceptionHandlingBit); |
| 6763 | if (FB[WebAssembly::FeatureExtendedConst]) |
| 6764 | Features.set(Feature_HasExtendedConstBit); |
| 6765 | if (FB[WebAssembly::FeatureFP16]) |
| 6766 | Features.set(Feature_HasFP16Bit); |
| 6767 | if (FB[WebAssembly::FeatureGC]) |
| 6768 | Features.set(Feature_HasGCBit); |
| 6769 | if (FB[WebAssembly::FeatureMultiMemory]) |
| 6770 | Features.set(Feature_HasMultiMemoryBit); |
| 6771 | if (FB[WebAssembly::FeatureMultivalue]) |
| 6772 | Features.set(Feature_HasMultivalueBit); |
| 6773 | if (FB[WebAssembly::FeatureMutableGlobals]) |
| 6774 | Features.set(Feature_HasMutableGlobalsBit); |
| 6775 | if (FB[WebAssembly::FeatureNontrappingFPToInt]) |
| 6776 | Features.set(Feature_HasNontrappingFPToIntBit); |
| 6777 | if (!(FB[WebAssembly::FeatureNontrappingFPToInt])) |
| 6778 | Features.set(Feature_NotHasNontrappingFPToIntBit); |
| 6779 | if (FB[WebAssembly::FeatureReferenceTypes]) |
| 6780 | Features.set(Feature_HasReferenceTypesBit); |
| 6781 | if (FB[WebAssembly::FeatureRelaxedAtomics]) |
| 6782 | Features.set(Feature_HasRelaxedAtomicsBit); |
| 6783 | if (FB[WebAssembly::FeatureRelaxedSIMD]) |
| 6784 | Features.set(Feature_HasRelaxedSIMDBit); |
| 6785 | if (FB[WebAssembly::FeatureSignExt]) |
| 6786 | Features.set(Feature_HasSignExtBit); |
| 6787 | if (FB[WebAssembly::FeatureSIMD128] || FB[WebAssembly::FeatureRelaxedSIMD]) |
| 6788 | Features.set(Feature_HasSIMD128Bit); |
| 6789 | if (FB[WebAssembly::FeatureTailCall]) |
| 6790 | Features.set(Feature_HasTailCallBit); |
| 6791 | if (FB[WebAssembly::FeatureWideArithmetic]) |
| 6792 | Features.set(Feature_HasWideArithmeticBit); |
| 6793 | return Features; |
| 6794 | } |
| 6795 | |
| 6796 | inline FeatureBitset computeRequiredFeatures(unsigned Opcode) { |
| 6797 | enum : uint8_t { |
| 6798 | CEFBS_None, |
| 6799 | CEFBS_HasAtomics, |
| 6800 | CEFBS_HasBulkMemoryOpt, |
| 6801 | CEFBS_HasExceptionHandling, |
| 6802 | CEFBS_HasFP16, |
| 6803 | CEFBS_HasGC, |
| 6804 | CEFBS_HasNontrappingFPToInt, |
| 6805 | CEFBS_HasReferenceTypes, |
| 6806 | CEFBS_HasRelaxedSIMD, |
| 6807 | CEFBS_HasSIMD128, |
| 6808 | CEFBS_HasSignExt, |
| 6809 | CEFBS_HasTailCall, |
| 6810 | CEFBS_HasWideArithmetic, |
| 6811 | CEFBS_NotHasNontrappingFPToInt, |
| 6812 | CEFBS_HasReferenceTypes_HasExceptionHandling, |
| 6813 | CEFBS_HasSIMD128_HasFP16, |
| 6814 | CEFBS_HasSIMD128_HasRelaxedSIMD, |
| 6815 | CEFBS_HasTailCall_HasGC, |
| 6816 | }; |
| 6817 | |
| 6818 | static constexpr FeatureBitset FeatureBitsets[] = { |
| 6819 | {}, // CEFBS_None |
| 6820 | {Feature_HasAtomicsBit, }, |
| 6821 | {Feature_HasBulkMemoryOptBit, }, |
| 6822 | {Feature_HasExceptionHandlingBit, }, |
| 6823 | {Feature_HasFP16Bit, }, |
| 6824 | {Feature_HasGCBit, }, |
| 6825 | {Feature_HasNontrappingFPToIntBit, }, |
| 6826 | {Feature_HasReferenceTypesBit, }, |
| 6827 | {Feature_HasRelaxedSIMDBit, }, |
| 6828 | {Feature_HasSIMD128Bit, }, |
| 6829 | {Feature_HasSignExtBit, }, |
| 6830 | {Feature_HasTailCallBit, }, |
| 6831 | {Feature_HasWideArithmeticBit, }, |
| 6832 | {Feature_NotHasNontrappingFPToIntBit, }, |
| 6833 | {Feature_HasReferenceTypesBit, Feature_HasExceptionHandlingBit, }, |
| 6834 | {Feature_HasSIMD128Bit, Feature_HasFP16Bit, }, |
| 6835 | {Feature_HasSIMD128Bit, Feature_HasRelaxedSIMDBit, }, |
| 6836 | {Feature_HasTailCallBit, Feature_HasGCBit, }, |
| 6837 | }; |
| 6838 | static constexpr uint8_t RequiredFeaturesRefs[] = { |
| 6839 | CEFBS_None, // PHI |
| 6840 | CEFBS_None, // INLINEASM |
| 6841 | CEFBS_None, // INLINEASM_BR |
| 6842 | CEFBS_None, // CFI_INSTRUCTION |
| 6843 | CEFBS_None, // EH_LABEL |
| 6844 | CEFBS_None, // GC_LABEL |
| 6845 | CEFBS_None, // ANNOTATION_LABEL |
| 6846 | CEFBS_None, // KILL |
| 6847 | CEFBS_None, // EXTRACT_SUBREG |
| 6848 | CEFBS_None, // INSERT_SUBREG |
| 6849 | CEFBS_None, // IMPLICIT_DEF |
| 6850 | CEFBS_None, // INIT_UNDEF |
| 6851 | CEFBS_None, // SUBREG_TO_REG |
| 6852 | CEFBS_None, // COPY_TO_REGCLASS |
| 6853 | CEFBS_None, // DBG_VALUE |
| 6854 | CEFBS_None, // DBG_VALUE_LIST |
| 6855 | CEFBS_None, // DBG_INSTR_REF |
| 6856 | CEFBS_None, // DBG_PHI |
| 6857 | CEFBS_None, // DBG_LABEL |
| 6858 | CEFBS_None, // REG_SEQUENCE |
| 6859 | CEFBS_None, // COPY |
| 6860 | CEFBS_None, // COPY_LANEMASK |
| 6861 | CEFBS_None, // BUNDLE |
| 6862 | CEFBS_None, // LIFETIME_START |
| 6863 | CEFBS_None, // LIFETIME_END |
| 6864 | CEFBS_None, // PSEUDO_PROBE |
| 6865 | CEFBS_None, // ARITH_FENCE |
| 6866 | CEFBS_None, // STACKMAP |
| 6867 | CEFBS_None, // FENTRY_CALL |
| 6868 | CEFBS_None, // PATCHPOINT |
| 6869 | CEFBS_None, // LOAD_STACK_GUARD |
| 6870 | CEFBS_None, // PREALLOCATED_SETUP |
| 6871 | CEFBS_None, // PREALLOCATED_ARG |
| 6872 | CEFBS_None, // STATEPOINT |
| 6873 | CEFBS_None, // LOCAL_ESCAPE |
| 6874 | CEFBS_None, // FAULTING_OP |
| 6875 | CEFBS_None, // PATCHABLE_OP |
| 6876 | CEFBS_None, // PATCHABLE_FUNCTION_ENTER |
| 6877 | CEFBS_None, // PATCHABLE_RET |
| 6878 | CEFBS_None, // PATCHABLE_FUNCTION_EXIT |
| 6879 | CEFBS_None, // PATCHABLE_TAIL_CALL |
| 6880 | CEFBS_None, // PATCHABLE_EVENT_CALL |
| 6881 | CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL |
| 6882 | CEFBS_None, // ICALL_BRANCH_FUNNEL |
| 6883 | CEFBS_None, // FAKE_USE |
| 6884 | CEFBS_None, // MEMBARRIER |
| 6885 | CEFBS_None, // JUMP_TABLE_DEBUG_INFO |
| 6886 | CEFBS_None, // RELOC_NONE |
| 6887 | CEFBS_None, // CONVERGENCECTRL_ENTRY |
| 6888 | CEFBS_None, // CONVERGENCECTRL_ANCHOR |
| 6889 | CEFBS_None, // CONVERGENCECTRL_LOOP |
| 6890 | CEFBS_None, // CONVERGENCECTRL_GLUE |
| 6891 | CEFBS_None, // G_ASSERT_SEXT |
| 6892 | CEFBS_None, // G_ASSERT_ZEXT |
| 6893 | CEFBS_None, // G_ASSERT_ALIGN |
| 6894 | CEFBS_None, // G_ADD |
| 6895 | CEFBS_None, // G_SUB |
| 6896 | CEFBS_None, // G_MUL |
| 6897 | CEFBS_None, // G_SDIV |
| 6898 | CEFBS_None, // G_UDIV |
| 6899 | CEFBS_None, // G_SREM |
| 6900 | CEFBS_None, // G_UREM |
| 6901 | CEFBS_None, // G_SDIVREM |
| 6902 | CEFBS_None, // G_UDIVREM |
| 6903 | CEFBS_None, // G_AND |
| 6904 | CEFBS_None, // G_OR |
| 6905 | CEFBS_None, // G_XOR |
| 6906 | CEFBS_None, // G_ABDS |
| 6907 | CEFBS_None, // G_ABDU |
| 6908 | CEFBS_None, // G_UAVGFLOOR |
| 6909 | CEFBS_None, // G_UAVGCEIL |
| 6910 | CEFBS_None, // G_SAVGFLOOR |
| 6911 | CEFBS_None, // G_SAVGCEIL |
| 6912 | CEFBS_None, // G_IMPLICIT_DEF |
| 6913 | CEFBS_None, // G_PHI |
| 6914 | CEFBS_None, // G_FRAME_INDEX |
| 6915 | CEFBS_None, // G_GLOBAL_VALUE |
| 6916 | CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE |
| 6917 | CEFBS_None, // G_CONSTANT_POOL |
| 6918 | CEFBS_None, // G_EXTRACT |
| 6919 | CEFBS_None, // G_UNMERGE_VALUES |
| 6920 | CEFBS_None, // G_INSERT |
| 6921 | CEFBS_None, // G_MERGE_VALUES |
| 6922 | CEFBS_None, // G_BUILD_VECTOR |
| 6923 | CEFBS_None, // G_BUILD_VECTOR_TRUNC |
| 6924 | CEFBS_None, // G_CONCAT_VECTORS |
| 6925 | CEFBS_None, // G_PTRTOINT |
| 6926 | CEFBS_None, // G_INTTOPTR |
| 6927 | CEFBS_None, // G_BITCAST |
| 6928 | CEFBS_None, // G_FREEZE |
| 6929 | CEFBS_None, // G_CONSTANT_FOLD_BARRIER |
| 6930 | CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND |
| 6931 | CEFBS_None, // G_INTRINSIC_TRUNC |
| 6932 | CEFBS_None, // G_INTRINSIC_ROUND |
| 6933 | CEFBS_None, // G_INTRINSIC_LRINT |
| 6934 | CEFBS_None, // G_INTRINSIC_LLRINT |
| 6935 | CEFBS_None, // G_INTRINSIC_ROUNDEVEN |
| 6936 | CEFBS_None, // G_READCYCLECOUNTER |
| 6937 | CEFBS_None, // G_READSTEADYCOUNTER |
| 6938 | CEFBS_None, // G_LOAD |
| 6939 | CEFBS_None, // G_SEXTLOAD |
| 6940 | CEFBS_None, // G_ZEXTLOAD |
| 6941 | CEFBS_None, // G_FPEXTLOAD |
| 6942 | CEFBS_None, // G_INDEXED_LOAD |
| 6943 | CEFBS_None, // G_INDEXED_SEXTLOAD |
| 6944 | CEFBS_None, // G_INDEXED_ZEXTLOAD |
| 6945 | CEFBS_None, // G_STORE |
| 6946 | CEFBS_None, // G_FPTRUNCSTORE |
| 6947 | CEFBS_None, // G_INDEXED_STORE |
| 6948 | CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS |
| 6949 | CEFBS_None, // G_ATOMIC_CMPXCHG |
| 6950 | CEFBS_None, // G_ATOMICRMW_XCHG |
| 6951 | CEFBS_None, // G_ATOMICRMW_ADD |
| 6952 | CEFBS_None, // G_ATOMICRMW_SUB |
| 6953 | CEFBS_None, // G_ATOMICRMW_AND |
| 6954 | CEFBS_None, // G_ATOMICRMW_NAND |
| 6955 | CEFBS_None, // G_ATOMICRMW_OR |
| 6956 | CEFBS_None, // G_ATOMICRMW_XOR |
| 6957 | CEFBS_None, // G_ATOMICRMW_MAX |
| 6958 | CEFBS_None, // G_ATOMICRMW_MIN |
| 6959 | CEFBS_None, // G_ATOMICRMW_UMAX |
| 6960 | CEFBS_None, // G_ATOMICRMW_UMIN |
| 6961 | CEFBS_None, // G_ATOMICRMW_FADD |
| 6962 | CEFBS_None, // G_ATOMICRMW_FSUB |
| 6963 | CEFBS_None, // G_ATOMICRMW_FMAX |
| 6964 | CEFBS_None, // G_ATOMICRMW_FMIN |
| 6965 | CEFBS_None, // G_ATOMICRMW_FMAXIMUM |
| 6966 | CEFBS_None, // G_ATOMICRMW_FMINIMUM |
| 6967 | CEFBS_None, // G_ATOMICRMW_FMAXIMUMNUM |
| 6968 | CEFBS_None, // G_ATOMICRMW_FMINIMUMNUM |
| 6969 | CEFBS_None, // G_ATOMICRMW_UINC_WRAP |
| 6970 | CEFBS_None, // G_ATOMICRMW_UDEC_WRAP |
| 6971 | CEFBS_None, // G_ATOMICRMW_USUB_COND |
| 6972 | CEFBS_None, // G_ATOMICRMW_USUB_SAT |
| 6973 | CEFBS_None, // G_FENCE |
| 6974 | CEFBS_None, // G_PREFETCH |
| 6975 | CEFBS_None, // G_BRCOND |
| 6976 | CEFBS_None, // G_BRINDIRECT |
| 6977 | CEFBS_None, // G_INVOKE_REGION_START |
| 6978 | CEFBS_None, // G_INTRINSIC |
| 6979 | CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS |
| 6980 | CEFBS_None, // G_INTRINSIC_CONVERGENT |
| 6981 | CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS |
| 6982 | CEFBS_None, // G_ANYEXT |
| 6983 | CEFBS_None, // G_TRUNC |
| 6984 | CEFBS_None, // G_TRUNC_SSAT_S |
| 6985 | CEFBS_None, // G_TRUNC_SSAT_U |
| 6986 | CEFBS_None, // G_TRUNC_USAT_U |
| 6987 | CEFBS_None, // G_CONSTANT |
| 6988 | CEFBS_None, // G_FCONSTANT |
| 6989 | CEFBS_None, // G_VASTART |
| 6990 | CEFBS_None, // G_VAARG |
| 6991 | CEFBS_None, // G_SEXT |
| 6992 | CEFBS_None, // G_SEXT_INREG |
| 6993 | CEFBS_None, // G_ZEXT |
| 6994 | CEFBS_None, // G_SHL |
| 6995 | CEFBS_None, // G_LSHR |
| 6996 | CEFBS_None, // G_ASHR |
| 6997 | CEFBS_None, // G_FSHL |
| 6998 | CEFBS_None, // G_FSHR |
| 6999 | CEFBS_None, // G_ROTR |
| 7000 | CEFBS_None, // G_ROTL |
| 7001 | CEFBS_None, // G_ICMP |
| 7002 | CEFBS_None, // G_FCMP |
| 7003 | CEFBS_None, // G_SCMP |
| 7004 | CEFBS_None, // G_UCMP |
| 7005 | CEFBS_None, // G_SELECT |
| 7006 | CEFBS_None, // G_UADDO |
| 7007 | CEFBS_None, // G_UADDE |
| 7008 | CEFBS_None, // G_USUBO |
| 7009 | CEFBS_None, // G_USUBE |
| 7010 | CEFBS_None, // G_SADDO |
| 7011 | CEFBS_None, // G_SADDE |
| 7012 | CEFBS_None, // G_SSUBO |
| 7013 | CEFBS_None, // G_SSUBE |
| 7014 | CEFBS_None, // G_UMULO |
| 7015 | CEFBS_None, // G_SMULO |
| 7016 | CEFBS_None, // G_UMULH |
| 7017 | CEFBS_None, // G_SMULH |
| 7018 | CEFBS_None, // G_UADDSAT |
| 7019 | CEFBS_None, // G_SADDSAT |
| 7020 | CEFBS_None, // G_USUBSAT |
| 7021 | CEFBS_None, // G_SSUBSAT |
| 7022 | CEFBS_None, // G_USHLSAT |
| 7023 | CEFBS_None, // G_SSHLSAT |
| 7024 | CEFBS_None, // G_SMULFIX |
| 7025 | CEFBS_None, // G_UMULFIX |
| 7026 | CEFBS_None, // G_SMULFIXSAT |
| 7027 | CEFBS_None, // G_UMULFIXSAT |
| 7028 | CEFBS_None, // G_SDIVFIX |
| 7029 | CEFBS_None, // G_UDIVFIX |
| 7030 | CEFBS_None, // G_SDIVFIXSAT |
| 7031 | CEFBS_None, // G_UDIVFIXSAT |
| 7032 | CEFBS_None, // G_FADD |
| 7033 | CEFBS_None, // G_FSUB |
| 7034 | CEFBS_None, // G_FMUL |
| 7035 | CEFBS_None, // G_FMA |
| 7036 | CEFBS_None, // G_FMAD |
| 7037 | CEFBS_None, // G_FDIV |
| 7038 | CEFBS_None, // G_FREM |
| 7039 | CEFBS_None, // G_FMODF |
| 7040 | CEFBS_None, // G_FPOW |
| 7041 | CEFBS_None, // G_FPOWI |
| 7042 | CEFBS_None, // G_FEXP |
| 7043 | CEFBS_None, // G_FEXP2 |
| 7044 | CEFBS_None, // G_FEXP10 |
| 7045 | CEFBS_None, // G_FLOG |
| 7046 | CEFBS_None, // G_FLOG2 |
| 7047 | CEFBS_None, // G_FLOG10 |
| 7048 | CEFBS_None, // G_FLDEXP |
| 7049 | CEFBS_None, // G_FFREXP |
| 7050 | CEFBS_None, // G_FNEG |
| 7051 | CEFBS_None, // G_FPEXT |
| 7052 | CEFBS_None, // G_FPTRUNC |
| 7053 | CEFBS_None, // G_FPTOSI |
| 7054 | CEFBS_None, // G_FPTOUI |
| 7055 | CEFBS_None, // G_SITOFP |
| 7056 | CEFBS_None, // G_UITOFP |
| 7057 | CEFBS_None, // G_FPTOSI_SAT |
| 7058 | CEFBS_None, // G_FPTOUI_SAT |
| 7059 | CEFBS_None, // G_FABS |
| 7060 | CEFBS_None, // G_FCOPYSIGN |
| 7061 | CEFBS_None, // G_IS_FPCLASS |
| 7062 | CEFBS_None, // G_FCANONICALIZE |
| 7063 | CEFBS_None, // G_FMINNUM |
| 7064 | CEFBS_None, // G_FMAXNUM |
| 7065 | CEFBS_None, // G_FMINNUM_IEEE |
| 7066 | CEFBS_None, // G_FMAXNUM_IEEE |
| 7067 | CEFBS_None, // G_FMINIMUM |
| 7068 | CEFBS_None, // G_FMAXIMUM |
| 7069 | CEFBS_None, // G_FMINIMUMNUM |
| 7070 | CEFBS_None, // G_FMAXIMUMNUM |
| 7071 | CEFBS_None, // G_GET_FPENV |
| 7072 | CEFBS_None, // G_SET_FPENV |
| 7073 | CEFBS_None, // G_RESET_FPENV |
| 7074 | CEFBS_None, // G_GET_FPMODE |
| 7075 | CEFBS_None, // G_SET_FPMODE |
| 7076 | CEFBS_None, // G_RESET_FPMODE |
| 7077 | CEFBS_None, // G_GET_ROUNDING |
| 7078 | CEFBS_None, // G_SET_ROUNDING |
| 7079 | CEFBS_None, // G_PTR_ADD |
| 7080 | CEFBS_None, // G_PTRMASK |
| 7081 | CEFBS_None, // G_SMIN |
| 7082 | CEFBS_None, // G_SMAX |
| 7083 | CEFBS_None, // G_UMIN |
| 7084 | CEFBS_None, // G_UMAX |
| 7085 | CEFBS_None, // G_ABS |
| 7086 | CEFBS_None, // G_LROUND |
| 7087 | CEFBS_None, // G_LLROUND |
| 7088 | CEFBS_None, // G_BR |
| 7089 | CEFBS_None, // G_BRJT |
| 7090 | CEFBS_None, // G_VSCALE |
| 7091 | CEFBS_None, // G_INSERT_SUBVECTOR |
| 7092 | CEFBS_None, // G_EXTRACT_SUBVECTOR |
| 7093 | CEFBS_None, // G_INSERT_VECTOR_ELT |
| 7094 | CEFBS_None, // G_EXTRACT_VECTOR_ELT |
| 7095 | CEFBS_None, // G_SHUFFLE_VECTOR |
| 7096 | CEFBS_None, // G_SPLAT_VECTOR |
| 7097 | CEFBS_None, // G_STEP_VECTOR |
| 7098 | CEFBS_None, // G_VECTOR_COMPRESS |
| 7099 | CEFBS_None, // G_CTTZ |
| 7100 | CEFBS_None, // G_CTTZ_ZERO_POISON |
| 7101 | CEFBS_None, // G_CTLZ |
| 7102 | CEFBS_None, // G_CTLZ_ZERO_POISON |
| 7103 | CEFBS_None, // G_CTLS |
| 7104 | CEFBS_None, // G_CTPOP |
| 7105 | CEFBS_None, // G_BSWAP |
| 7106 | CEFBS_None, // G_BITREVERSE |
| 7107 | CEFBS_None, // G_CLMUL |
| 7108 | CEFBS_None, // G_CLMULH |
| 7109 | CEFBS_None, // G_CLMULR |
| 7110 | CEFBS_None, // G_FCEIL |
| 7111 | CEFBS_None, // G_FCOS |
| 7112 | CEFBS_None, // G_FSIN |
| 7113 | CEFBS_None, // G_FSINCOS |
| 7114 | CEFBS_None, // G_FTAN |
| 7115 | CEFBS_None, // G_FACOS |
| 7116 | CEFBS_None, // G_FASIN |
| 7117 | CEFBS_None, // G_FATAN |
| 7118 | CEFBS_None, // G_FATAN2 |
| 7119 | CEFBS_None, // G_FCOSH |
| 7120 | CEFBS_None, // G_FSINH |
| 7121 | CEFBS_None, // G_FTANH |
| 7122 | CEFBS_None, // G_FSQRT |
| 7123 | CEFBS_None, // G_FFLOOR |
| 7124 | CEFBS_None, // G_FRINT |
| 7125 | CEFBS_None, // G_FNEARBYINT |
| 7126 | CEFBS_None, // G_ADDRSPACE_CAST |
| 7127 | CEFBS_None, // G_BLOCK_ADDR |
| 7128 | CEFBS_None, // G_JUMP_TABLE |
| 7129 | CEFBS_None, // G_DYN_STACKALLOC |
| 7130 | CEFBS_None, // G_STACKSAVE |
| 7131 | CEFBS_None, // G_STACKRESTORE |
| 7132 | CEFBS_None, // G_STRICT_FADD |
| 7133 | CEFBS_None, // G_STRICT_FSUB |
| 7134 | CEFBS_None, // G_STRICT_FMUL |
| 7135 | CEFBS_None, // G_STRICT_FDIV |
| 7136 | CEFBS_None, // G_STRICT_FREM |
| 7137 | CEFBS_None, // G_STRICT_FMA |
| 7138 | CEFBS_None, // G_STRICT_FSQRT |
| 7139 | CEFBS_None, // G_STRICT_FLDEXP |
| 7140 | CEFBS_None, // G_STRICT_FCMP |
| 7141 | CEFBS_None, // G_STRICT_FCMPS |
| 7142 | CEFBS_None, // G_READ_REGISTER |
| 7143 | CEFBS_None, // G_WRITE_REGISTER |
| 7144 | CEFBS_None, // G_MEMCPY |
| 7145 | CEFBS_None, // G_MEMCPY_INLINE |
| 7146 | CEFBS_None, // G_MEMMOVE |
| 7147 | CEFBS_None, // G_MEMSET |
| 7148 | CEFBS_None, // G_BZERO |
| 7149 | CEFBS_None, // G_MEMSET_INLINE |
| 7150 | CEFBS_None, // G_TRAP |
| 7151 | CEFBS_None, // G_DEBUGTRAP |
| 7152 | CEFBS_None, // G_UBSANTRAP |
| 7153 | CEFBS_None, // G_VECREDUCE_SEQ_FADD |
| 7154 | CEFBS_None, // G_VECREDUCE_SEQ_FMUL |
| 7155 | CEFBS_None, // G_VECREDUCE_FADD |
| 7156 | CEFBS_None, // G_VECREDUCE_FMUL |
| 7157 | CEFBS_None, // G_VECREDUCE_FMAX |
| 7158 | CEFBS_None, // G_VECREDUCE_FMIN |
| 7159 | CEFBS_None, // G_VECREDUCE_FMAXIMUM |
| 7160 | CEFBS_None, // G_VECREDUCE_FMINIMUM |
| 7161 | CEFBS_None, // G_VECREDUCE_FMAXIMUMNUM |
| 7162 | CEFBS_None, // G_VECREDUCE_FMINIMUMNUM |
| 7163 | CEFBS_None, // G_VECREDUCE_ADD |
| 7164 | CEFBS_None, // G_VECREDUCE_MUL |
| 7165 | CEFBS_None, // G_VECREDUCE_AND |
| 7166 | CEFBS_None, // G_VECREDUCE_OR |
| 7167 | CEFBS_None, // G_VECREDUCE_XOR |
| 7168 | CEFBS_None, // G_VECREDUCE_SMAX |
| 7169 | CEFBS_None, // G_VECREDUCE_SMIN |
| 7170 | CEFBS_None, // G_VECREDUCE_UMAX |
| 7171 | CEFBS_None, // G_VECREDUCE_UMIN |
| 7172 | CEFBS_None, // G_SBFX |
| 7173 | CEFBS_None, // G_UBFX |
| 7174 | CEFBS_None, // CALL_PARAMS |
| 7175 | CEFBS_None, // CALL_PARAMS_S |
| 7176 | CEFBS_None, // CALL_RESULTS |
| 7177 | CEFBS_None, // CALL_RESULTS_S |
| 7178 | CEFBS_HasExceptionHandling, // CATCHRET |
| 7179 | CEFBS_HasExceptionHandling, // CATCHRET_S |
| 7180 | CEFBS_HasExceptionHandling, // CLEANUPRET |
| 7181 | CEFBS_HasExceptionHandling, // CLEANUPRET_S |
| 7182 | CEFBS_HasAtomics, // COMPILER_FENCE |
| 7183 | CEFBS_HasAtomics, // COMPILER_FENCE_S |
| 7184 | CEFBS_None, // RET_CALL_PARAMS |
| 7185 | CEFBS_None, // RET_CALL_PARAMS_S |
| 7186 | CEFBS_None, // RET_CALL_RESULTS |
| 7187 | CEFBS_None, // RET_CALL_RESULTS_S |
| 7188 | CEFBS_HasSIMD128_HasFP16, // ABS_F16x8 |
| 7189 | CEFBS_HasSIMD128_HasFP16, // ABS_F16x8_S |
| 7190 | CEFBS_None, // ABS_F32 |
| 7191 | CEFBS_None, // ABS_F32_S |
| 7192 | CEFBS_HasSIMD128, // ABS_F32x4 |
| 7193 | CEFBS_HasSIMD128, // ABS_F32x4_S |
| 7194 | CEFBS_None, // ABS_F64 |
| 7195 | CEFBS_None, // ABS_F64_S |
| 7196 | CEFBS_HasSIMD128, // ABS_F64x2 |
| 7197 | CEFBS_HasSIMD128, // ABS_F64x2_S |
| 7198 | CEFBS_HasSIMD128, // ABS_I16x8 |
| 7199 | CEFBS_HasSIMD128, // ABS_I16x8_S |
| 7200 | CEFBS_HasSIMD128, // ABS_I32x4 |
| 7201 | CEFBS_HasSIMD128, // ABS_I32x4_S |
| 7202 | CEFBS_HasSIMD128, // ABS_I64x2 |
| 7203 | CEFBS_HasSIMD128, // ABS_I64x2_S |
| 7204 | CEFBS_HasSIMD128, // ABS_I8x16 |
| 7205 | CEFBS_HasSIMD128, // ABS_I8x16_S |
| 7206 | CEFBS_HasSIMD128_HasFP16, // ADD_F16x8 |
| 7207 | CEFBS_HasSIMD128_HasFP16, // ADD_F16x8_S |
| 7208 | CEFBS_None, // ADD_F32 |
| 7209 | CEFBS_None, // ADD_F32_S |
| 7210 | CEFBS_HasSIMD128, // ADD_F32x4 |
| 7211 | CEFBS_HasSIMD128, // ADD_F32x4_S |
| 7212 | CEFBS_None, // ADD_F64 |
| 7213 | CEFBS_None, // ADD_F64_S |
| 7214 | CEFBS_HasSIMD128, // ADD_F64x2 |
| 7215 | CEFBS_HasSIMD128, // ADD_F64x2_S |
| 7216 | CEFBS_HasSIMD128, // ADD_I16x8 |
| 7217 | CEFBS_HasSIMD128, // ADD_I16x8_S |
| 7218 | CEFBS_None, // ADD_I32 |
| 7219 | CEFBS_None, // ADD_I32_S |
| 7220 | CEFBS_HasSIMD128, // ADD_I32x4 |
| 7221 | CEFBS_HasSIMD128, // ADD_I32x4_S |
| 7222 | CEFBS_None, // ADD_I64 |
| 7223 | CEFBS_None, // ADD_I64_S |
| 7224 | CEFBS_HasSIMD128, // ADD_I64x2 |
| 7225 | CEFBS_HasSIMD128, // ADD_I64x2_S |
| 7226 | CEFBS_HasSIMD128, // ADD_I8x16 |
| 7227 | CEFBS_HasSIMD128, // ADD_I8x16_S |
| 7228 | CEFBS_HasSIMD128, // ADD_SAT_S_I16x8 |
| 7229 | CEFBS_HasSIMD128, // ADD_SAT_S_I16x8_S |
| 7230 | CEFBS_HasSIMD128, // ADD_SAT_S_I8x16 |
| 7231 | CEFBS_HasSIMD128, // ADD_SAT_S_I8x16_S |
| 7232 | CEFBS_HasSIMD128, // ADD_SAT_U_I16x8 |
| 7233 | CEFBS_HasSIMD128, // ADD_SAT_U_I16x8_S |
| 7234 | CEFBS_HasSIMD128, // ADD_SAT_U_I8x16 |
| 7235 | CEFBS_HasSIMD128, // ADD_SAT_U_I8x16_S |
| 7236 | CEFBS_None, // ADJCALLSTACKDOWN |
| 7237 | CEFBS_None, // ADJCALLSTACKDOWN_S |
| 7238 | CEFBS_None, // ADJCALLSTACKUP |
| 7239 | CEFBS_None, // ADJCALLSTACKUP_S |
| 7240 | CEFBS_HasSIMD128, // ALLTRUE_I16x8 |
| 7241 | CEFBS_HasSIMD128, // ALLTRUE_I16x8_S |
| 7242 | CEFBS_HasSIMD128, // ALLTRUE_I32x4 |
| 7243 | CEFBS_HasSIMD128, // ALLTRUE_I32x4_S |
| 7244 | CEFBS_HasSIMD128, // ALLTRUE_I64x2 |
| 7245 | CEFBS_HasSIMD128, // ALLTRUE_I64x2_S |
| 7246 | CEFBS_HasSIMD128, // ALLTRUE_I8x16 |
| 7247 | CEFBS_HasSIMD128, // ALLTRUE_I8x16_S |
| 7248 | CEFBS_HasSIMD128, // AND |
| 7249 | CEFBS_HasSIMD128, // ANDNOT |
| 7250 | CEFBS_HasSIMD128, // ANDNOT_S |
| 7251 | CEFBS_None, // AND_I32 |
| 7252 | CEFBS_None, // AND_I32_S |
| 7253 | CEFBS_None, // AND_I64 |
| 7254 | CEFBS_None, // AND_I64_S |
| 7255 | CEFBS_HasSIMD128, // AND_S |
| 7256 | CEFBS_HasSIMD128, // ANYTRUE |
| 7257 | CEFBS_HasSIMD128, // ANYTRUE_S |
| 7258 | CEFBS_None, // ARGUMENT_exnref |
| 7259 | CEFBS_None, // ARGUMENT_exnref_S |
| 7260 | CEFBS_None, // ARGUMENT_externref |
| 7261 | CEFBS_None, // ARGUMENT_externref_S |
| 7262 | CEFBS_None, // ARGUMENT_f32 |
| 7263 | CEFBS_None, // ARGUMENT_f32_S |
| 7264 | CEFBS_None, // ARGUMENT_f64 |
| 7265 | CEFBS_None, // ARGUMENT_f64_S |
| 7266 | CEFBS_None, // ARGUMENT_funcref |
| 7267 | CEFBS_None, // ARGUMENT_funcref_S |
| 7268 | CEFBS_None, // ARGUMENT_i32 |
| 7269 | CEFBS_None, // ARGUMENT_i32_S |
| 7270 | CEFBS_None, // ARGUMENT_i64 |
| 7271 | CEFBS_None, // ARGUMENT_i64_S |
| 7272 | CEFBS_None, // ARGUMENT_v16i8 |
| 7273 | CEFBS_None, // ARGUMENT_v16i8_S |
| 7274 | CEFBS_None, // ARGUMENT_v2f64 |
| 7275 | CEFBS_None, // ARGUMENT_v2f64_S |
| 7276 | CEFBS_None, // ARGUMENT_v2i64 |
| 7277 | CEFBS_None, // ARGUMENT_v2i64_S |
| 7278 | CEFBS_None, // ARGUMENT_v4f32 |
| 7279 | CEFBS_None, // ARGUMENT_v4f32_S |
| 7280 | CEFBS_None, // ARGUMENT_v4i32 |
| 7281 | CEFBS_None, // ARGUMENT_v4i32_S |
| 7282 | CEFBS_None, // ARGUMENT_v8f16 |
| 7283 | CEFBS_None, // ARGUMENT_v8f16_S |
| 7284 | CEFBS_None, // ARGUMENT_v8i16 |
| 7285 | CEFBS_None, // ARGUMENT_v8i16_S |
| 7286 | CEFBS_HasAtomics, // ATOMIC_FENCE |
| 7287 | CEFBS_HasAtomics, // ATOMIC_FENCE_S |
| 7288 | CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I32_A32 |
| 7289 | CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I32_A32_S |
| 7290 | CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I32_A64 |
| 7291 | CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I32_A64_S |
| 7292 | CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I64_A32 |
| 7293 | CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I64_A32_S |
| 7294 | CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I64_A64 |
| 7295 | CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I64_A64_S |
| 7296 | CEFBS_HasAtomics, // ATOMIC_LOAD32_U_I64_A32 |
| 7297 | CEFBS_HasAtomics, // ATOMIC_LOAD32_U_I64_A32_S |
| 7298 | CEFBS_HasAtomics, // ATOMIC_LOAD32_U_I64_A64 |
| 7299 | CEFBS_HasAtomics, // ATOMIC_LOAD32_U_I64_A64_S |
| 7300 | CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I32_A32 |
| 7301 | CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I32_A32_S |
| 7302 | CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I32_A64 |
| 7303 | CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I32_A64_S |
| 7304 | CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I64_A32 |
| 7305 | CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I64_A32_S |
| 7306 | CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I64_A64 |
| 7307 | CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I64_A64_S |
| 7308 | CEFBS_HasAtomics, // ATOMIC_LOAD_I32_A32 |
| 7309 | CEFBS_HasAtomics, // ATOMIC_LOAD_I32_A32_S |
| 7310 | CEFBS_HasAtomics, // ATOMIC_LOAD_I32_A64 |
| 7311 | CEFBS_HasAtomics, // ATOMIC_LOAD_I32_A64_S |
| 7312 | CEFBS_HasAtomics, // ATOMIC_LOAD_I64_A32 |
| 7313 | CEFBS_HasAtomics, // ATOMIC_LOAD_I64_A32_S |
| 7314 | CEFBS_HasAtomics, // ATOMIC_LOAD_I64_A64 |
| 7315 | CEFBS_HasAtomics, // ATOMIC_LOAD_I64_A64_S |
| 7316 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I32_A32 |
| 7317 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I32_A32_S |
| 7318 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I32_A64 |
| 7319 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I32_A64_S |
| 7320 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I64_A32 |
| 7321 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I64_A32_S |
| 7322 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I64_A64 |
| 7323 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I64_A64_S |
| 7324 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I32_A32 |
| 7325 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I32_A32_S |
| 7326 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I32_A64 |
| 7327 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I32_A64_S |
| 7328 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I64_A32 |
| 7329 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I64_A32_S |
| 7330 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I64_A64 |
| 7331 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I64_A64_S |
| 7332 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I32_A32 |
| 7333 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I32_A32_S |
| 7334 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I32_A64 |
| 7335 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I32_A64_S |
| 7336 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I64_A32 |
| 7337 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I64_A32_S |
| 7338 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I64_A64 |
| 7339 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I64_A64_S |
| 7340 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I32_A32 |
| 7341 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I32_A32_S |
| 7342 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I32_A64 |
| 7343 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I32_A64_S |
| 7344 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I64_A32 |
| 7345 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I64_A32_S |
| 7346 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I64_A64 |
| 7347 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I64_A64_S |
| 7348 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I32_A32 |
| 7349 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I32_A32_S |
| 7350 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I32_A64 |
| 7351 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I32_A64_S |
| 7352 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I64_A32 |
| 7353 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I64_A32_S |
| 7354 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I64_A64 |
| 7355 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I64_A64_S |
| 7356 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I32_A32 |
| 7357 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I32_A32_S |
| 7358 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I32_A64 |
| 7359 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I32_A64_S |
| 7360 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I64_A32 |
| 7361 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I64_A32_S |
| 7362 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I64_A64 |
| 7363 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I64_A64_S |
| 7364 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I32_A32 |
| 7365 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I32_A32_S |
| 7366 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I32_A64 |
| 7367 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I32_A64_S |
| 7368 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I64_A32 |
| 7369 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I64_A32_S |
| 7370 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I64_A64 |
| 7371 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I64_A64_S |
| 7372 | CEFBS_HasAtomics, // ATOMIC_RMW32_U_ADD_I64_A32 |
| 7373 | CEFBS_HasAtomics, // ATOMIC_RMW32_U_ADD_I64_A32_S |
| 7374 | CEFBS_HasAtomics, // ATOMIC_RMW32_U_ADD_I64_A64 |
| 7375 | CEFBS_HasAtomics, // ATOMIC_RMW32_U_ADD_I64_A64_S |
| 7376 | CEFBS_HasAtomics, // ATOMIC_RMW32_U_AND_I64_A32 |
| 7377 | CEFBS_HasAtomics, // ATOMIC_RMW32_U_AND_I64_A32_S |
| 7378 | CEFBS_HasAtomics, // ATOMIC_RMW32_U_AND_I64_A64 |
| 7379 | CEFBS_HasAtomics, // ATOMIC_RMW32_U_AND_I64_A64_S |
| 7380 | CEFBS_HasAtomics, // ATOMIC_RMW32_U_CMPXCHG_I64_A32 |
| 7381 | CEFBS_HasAtomics, // ATOMIC_RMW32_U_CMPXCHG_I64_A32_S |
| 7382 | CEFBS_HasAtomics, // ATOMIC_RMW32_U_CMPXCHG_I64_A64 |
| 7383 | CEFBS_HasAtomics, // ATOMIC_RMW32_U_CMPXCHG_I64_A64_S |
| 7384 | CEFBS_HasAtomics, // ATOMIC_RMW32_U_OR_I64_A32 |
| 7385 | CEFBS_HasAtomics, // ATOMIC_RMW32_U_OR_I64_A32_S |
| 7386 | CEFBS_HasAtomics, // ATOMIC_RMW32_U_OR_I64_A64 |
| 7387 | CEFBS_HasAtomics, // ATOMIC_RMW32_U_OR_I64_A64_S |
| 7388 | CEFBS_HasAtomics, // ATOMIC_RMW32_U_SUB_I64_A32 |
| 7389 | CEFBS_HasAtomics, // ATOMIC_RMW32_U_SUB_I64_A32_S |
| 7390 | CEFBS_HasAtomics, // ATOMIC_RMW32_U_SUB_I64_A64 |
| 7391 | CEFBS_HasAtomics, // ATOMIC_RMW32_U_SUB_I64_A64_S |
| 7392 | CEFBS_HasAtomics, // ATOMIC_RMW32_U_XCHG_I64_A32 |
| 7393 | CEFBS_HasAtomics, // ATOMIC_RMW32_U_XCHG_I64_A32_S |
| 7394 | CEFBS_HasAtomics, // ATOMIC_RMW32_U_XCHG_I64_A64 |
| 7395 | CEFBS_HasAtomics, // ATOMIC_RMW32_U_XCHG_I64_A64_S |
| 7396 | CEFBS_HasAtomics, // ATOMIC_RMW32_U_XOR_I64_A32 |
| 7397 | CEFBS_HasAtomics, // ATOMIC_RMW32_U_XOR_I64_A32_S |
| 7398 | CEFBS_HasAtomics, // ATOMIC_RMW32_U_XOR_I64_A64 |
| 7399 | CEFBS_HasAtomics, // ATOMIC_RMW32_U_XOR_I64_A64_S |
| 7400 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I32_A32 |
| 7401 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I32_A32_S |
| 7402 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I32_A64 |
| 7403 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I32_A64_S |
| 7404 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I64_A32 |
| 7405 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I64_A32_S |
| 7406 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I64_A64 |
| 7407 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I64_A64_S |
| 7408 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I32_A32 |
| 7409 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I32_A32_S |
| 7410 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I32_A64 |
| 7411 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I32_A64_S |
| 7412 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I64_A32 |
| 7413 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I64_A32_S |
| 7414 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I64_A64 |
| 7415 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I64_A64_S |
| 7416 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I32_A32 |
| 7417 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I32_A32_S |
| 7418 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I32_A64 |
| 7419 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I32_A64_S |
| 7420 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I64_A32 |
| 7421 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I64_A32_S |
| 7422 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I64_A64 |
| 7423 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I64_A64_S |
| 7424 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I32_A32 |
| 7425 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I32_A32_S |
| 7426 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I32_A64 |
| 7427 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I32_A64_S |
| 7428 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I64_A32 |
| 7429 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I64_A32_S |
| 7430 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I64_A64 |
| 7431 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I64_A64_S |
| 7432 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I32_A32 |
| 7433 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I32_A32_S |
| 7434 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I32_A64 |
| 7435 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I32_A64_S |
| 7436 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I64_A32 |
| 7437 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I64_A32_S |
| 7438 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I64_A64 |
| 7439 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I64_A64_S |
| 7440 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I32_A32 |
| 7441 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I32_A32_S |
| 7442 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I32_A64 |
| 7443 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I32_A64_S |
| 7444 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I64_A32 |
| 7445 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I64_A32_S |
| 7446 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I64_A64 |
| 7447 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I64_A64_S |
| 7448 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I32_A32 |
| 7449 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I32_A32_S |
| 7450 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I32_A64 |
| 7451 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I32_A64_S |
| 7452 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I64_A32 |
| 7453 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I64_A32_S |
| 7454 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I64_A64 |
| 7455 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I64_A64_S |
| 7456 | CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I32_A32 |
| 7457 | CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I32_A32_S |
| 7458 | CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I32_A64 |
| 7459 | CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I32_A64_S |
| 7460 | CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I64_A32 |
| 7461 | CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I64_A32_S |
| 7462 | CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I64_A64 |
| 7463 | CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I64_A64_S |
| 7464 | CEFBS_HasAtomics, // ATOMIC_RMW_AND_I32_A32 |
| 7465 | CEFBS_HasAtomics, // ATOMIC_RMW_AND_I32_A32_S |
| 7466 | CEFBS_HasAtomics, // ATOMIC_RMW_AND_I32_A64 |
| 7467 | CEFBS_HasAtomics, // ATOMIC_RMW_AND_I32_A64_S |
| 7468 | CEFBS_HasAtomics, // ATOMIC_RMW_AND_I64_A32 |
| 7469 | CEFBS_HasAtomics, // ATOMIC_RMW_AND_I64_A32_S |
| 7470 | CEFBS_HasAtomics, // ATOMIC_RMW_AND_I64_A64 |
| 7471 | CEFBS_HasAtomics, // ATOMIC_RMW_AND_I64_A64_S |
| 7472 | CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I32_A32 |
| 7473 | CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I32_A32_S |
| 7474 | CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I32_A64 |
| 7475 | CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I32_A64_S |
| 7476 | CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I64_A32 |
| 7477 | CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I64_A32_S |
| 7478 | CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I64_A64 |
| 7479 | CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I64_A64_S |
| 7480 | CEFBS_HasAtomics, // ATOMIC_RMW_OR_I32_A32 |
| 7481 | CEFBS_HasAtomics, // ATOMIC_RMW_OR_I32_A32_S |
| 7482 | CEFBS_HasAtomics, // ATOMIC_RMW_OR_I32_A64 |
| 7483 | CEFBS_HasAtomics, // ATOMIC_RMW_OR_I32_A64_S |
| 7484 | CEFBS_HasAtomics, // ATOMIC_RMW_OR_I64_A32 |
| 7485 | CEFBS_HasAtomics, // ATOMIC_RMW_OR_I64_A32_S |
| 7486 | CEFBS_HasAtomics, // ATOMIC_RMW_OR_I64_A64 |
| 7487 | CEFBS_HasAtomics, // ATOMIC_RMW_OR_I64_A64_S |
| 7488 | CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I32_A32 |
| 7489 | CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I32_A32_S |
| 7490 | CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I32_A64 |
| 7491 | CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I32_A64_S |
| 7492 | CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I64_A32 |
| 7493 | CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I64_A32_S |
| 7494 | CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I64_A64 |
| 7495 | CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I64_A64_S |
| 7496 | CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I32_A32 |
| 7497 | CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I32_A32_S |
| 7498 | CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I32_A64 |
| 7499 | CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I32_A64_S |
| 7500 | CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I64_A32 |
| 7501 | CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I64_A32_S |
| 7502 | CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I64_A64 |
| 7503 | CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I64_A64_S |
| 7504 | CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I32_A32 |
| 7505 | CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I32_A32_S |
| 7506 | CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I32_A64 |
| 7507 | CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I32_A64_S |
| 7508 | CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I64_A32 |
| 7509 | CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I64_A32_S |
| 7510 | CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I64_A64 |
| 7511 | CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I64_A64_S |
| 7512 | CEFBS_HasAtomics, // ATOMIC_STORE16_I32_A32 |
| 7513 | CEFBS_HasAtomics, // ATOMIC_STORE16_I32_A32_S |
| 7514 | CEFBS_HasAtomics, // ATOMIC_STORE16_I32_A64 |
| 7515 | CEFBS_HasAtomics, // ATOMIC_STORE16_I32_A64_S |
| 7516 | CEFBS_HasAtomics, // ATOMIC_STORE16_I64_A32 |
| 7517 | CEFBS_HasAtomics, // ATOMIC_STORE16_I64_A32_S |
| 7518 | CEFBS_HasAtomics, // ATOMIC_STORE16_I64_A64 |
| 7519 | CEFBS_HasAtomics, // ATOMIC_STORE16_I64_A64_S |
| 7520 | CEFBS_HasAtomics, // ATOMIC_STORE32_I64_A32 |
| 7521 | CEFBS_HasAtomics, // ATOMIC_STORE32_I64_A32_S |
| 7522 | CEFBS_HasAtomics, // ATOMIC_STORE32_I64_A64 |
| 7523 | CEFBS_HasAtomics, // ATOMIC_STORE32_I64_A64_S |
| 7524 | CEFBS_HasAtomics, // ATOMIC_STORE8_I32_A32 |
| 7525 | CEFBS_HasAtomics, // ATOMIC_STORE8_I32_A32_S |
| 7526 | CEFBS_HasAtomics, // ATOMIC_STORE8_I32_A64 |
| 7527 | CEFBS_HasAtomics, // ATOMIC_STORE8_I32_A64_S |
| 7528 | CEFBS_HasAtomics, // ATOMIC_STORE8_I64_A32 |
| 7529 | CEFBS_HasAtomics, // ATOMIC_STORE8_I64_A32_S |
| 7530 | CEFBS_HasAtomics, // ATOMIC_STORE8_I64_A64 |
| 7531 | CEFBS_HasAtomics, // ATOMIC_STORE8_I64_A64_S |
| 7532 | CEFBS_HasAtomics, // ATOMIC_STORE_I32_A32 |
| 7533 | CEFBS_HasAtomics, // ATOMIC_STORE_I32_A32_S |
| 7534 | CEFBS_HasAtomics, // ATOMIC_STORE_I32_A64 |
| 7535 | CEFBS_HasAtomics, // ATOMIC_STORE_I32_A64_S |
| 7536 | CEFBS_HasAtomics, // ATOMIC_STORE_I64_A32 |
| 7537 | CEFBS_HasAtomics, // ATOMIC_STORE_I64_A32_S |
| 7538 | CEFBS_HasAtomics, // ATOMIC_STORE_I64_A64 |
| 7539 | CEFBS_HasAtomics, // ATOMIC_STORE_I64_A64_S |
| 7540 | CEFBS_HasSIMD128, // AVGR_U_I16x8 |
| 7541 | CEFBS_HasSIMD128, // AVGR_U_I16x8_S |
| 7542 | CEFBS_HasSIMD128, // AVGR_U_I8x16 |
| 7543 | CEFBS_HasSIMD128, // AVGR_U_I8x16_S |
| 7544 | CEFBS_HasSIMD128, // BITMASK_I16x8 |
| 7545 | CEFBS_HasSIMD128, // BITMASK_I16x8_S |
| 7546 | CEFBS_HasSIMD128, // BITMASK_I32x4 |
| 7547 | CEFBS_HasSIMD128, // BITMASK_I32x4_S |
| 7548 | CEFBS_HasSIMD128, // BITMASK_I64x2 |
| 7549 | CEFBS_HasSIMD128, // BITMASK_I64x2_S |
| 7550 | CEFBS_HasSIMD128, // BITMASK_I8x16 |
| 7551 | CEFBS_HasSIMD128, // BITMASK_I8x16_S |
| 7552 | CEFBS_HasSIMD128, // BITSELECT |
| 7553 | CEFBS_HasSIMD128, // BITSELECT_S |
| 7554 | CEFBS_None, // BLOCK |
| 7555 | CEFBS_None, // BLOCK_S |
| 7556 | CEFBS_None, // BR |
| 7557 | CEFBS_None, // BR_IF |
| 7558 | CEFBS_None, // BR_IF_S |
| 7559 | CEFBS_None, // BR_S |
| 7560 | CEFBS_None, // BR_TABLE_I32 |
| 7561 | CEFBS_None, // BR_TABLE_I32_S |
| 7562 | CEFBS_None, // BR_TABLE_I64 |
| 7563 | CEFBS_None, // BR_TABLE_I64_S |
| 7564 | CEFBS_None, // BR_UNLESS |
| 7565 | CEFBS_None, // BR_UNLESS_S |
| 7566 | CEFBS_None, // CALL |
| 7567 | CEFBS_None, // CALL_INDIRECT |
| 7568 | CEFBS_None, // CALL_INDIRECT_S |
| 7569 | CEFBS_HasGC, // CALL_REF |
| 7570 | CEFBS_HasGC, // CALL_REF_S |
| 7571 | CEFBS_None, // CALL_S |
| 7572 | CEFBS_HasExceptionHandling, // CATCH |
| 7573 | CEFBS_HasExceptionHandling, // CATCH_ALL |
| 7574 | CEFBS_HasExceptionHandling, // CATCH_ALL_LEGACY |
| 7575 | CEFBS_HasExceptionHandling, // CATCH_ALL_LEGACY_S |
| 7576 | CEFBS_HasExceptionHandling, // CATCH_ALL_REF |
| 7577 | CEFBS_HasExceptionHandling, // CATCH_ALL_REF_S |
| 7578 | CEFBS_HasExceptionHandling, // CATCH_ALL_S |
| 7579 | CEFBS_HasExceptionHandling, // CATCH_LEGACY |
| 7580 | CEFBS_HasExceptionHandling, // CATCH_LEGACY_S |
| 7581 | CEFBS_HasExceptionHandling, // CATCH_REF |
| 7582 | CEFBS_HasExceptionHandling, // CATCH_REF_S |
| 7583 | CEFBS_HasExceptionHandling, // CATCH_S |
| 7584 | CEFBS_HasSIMD128_HasFP16, // CEIL_F16x8 |
| 7585 | CEFBS_HasSIMD128_HasFP16, // CEIL_F16x8_S |
| 7586 | CEFBS_None, // CEIL_F32 |
| 7587 | CEFBS_None, // CEIL_F32_S |
| 7588 | CEFBS_HasSIMD128, // CEIL_F32x4 |
| 7589 | CEFBS_HasSIMD128, // CEIL_F32x4_S |
| 7590 | CEFBS_None, // CEIL_F64 |
| 7591 | CEFBS_None, // CEIL_F64_S |
| 7592 | CEFBS_HasSIMD128, // CEIL_F64x2 |
| 7593 | CEFBS_HasSIMD128, // CEIL_F64x2_S |
| 7594 | CEFBS_None, // CLZ_I32 |
| 7595 | CEFBS_None, // CLZ_I32_S |
| 7596 | CEFBS_None, // CLZ_I64 |
| 7597 | CEFBS_None, // CLZ_I64_S |
| 7598 | CEFBS_None, // CONST_F32 |
| 7599 | CEFBS_None, // CONST_F32_S |
| 7600 | CEFBS_None, // CONST_F64 |
| 7601 | CEFBS_None, // CONST_F64_S |
| 7602 | CEFBS_None, // CONST_I32 |
| 7603 | CEFBS_None, // CONST_I32_S |
| 7604 | CEFBS_None, // CONST_I64 |
| 7605 | CEFBS_None, // CONST_I64_S |
| 7606 | CEFBS_HasSIMD128, // CONST_V128_F32x4 |
| 7607 | CEFBS_HasSIMD128, // CONST_V128_F32x4_S |
| 7608 | CEFBS_HasSIMD128, // CONST_V128_F64x2 |
| 7609 | CEFBS_HasSIMD128, // CONST_V128_F64x2_S |
| 7610 | CEFBS_HasSIMD128, // CONST_V128_I16x8 |
| 7611 | CEFBS_HasSIMD128, // CONST_V128_I16x8_S |
| 7612 | CEFBS_HasSIMD128, // CONST_V128_I32x4 |
| 7613 | CEFBS_HasSIMD128, // CONST_V128_I32x4_S |
| 7614 | CEFBS_HasSIMD128, // CONST_V128_I64x2 |
| 7615 | CEFBS_HasSIMD128, // CONST_V128_I64x2_S |
| 7616 | CEFBS_HasSIMD128, // CONST_V128_I8x16 |
| 7617 | CEFBS_HasSIMD128, // CONST_V128_I8x16_S |
| 7618 | CEFBS_None, // COPYSIGN_F32 |
| 7619 | CEFBS_None, // COPYSIGN_F32_S |
| 7620 | CEFBS_None, // COPYSIGN_F64 |
| 7621 | CEFBS_None, // COPYSIGN_F64_S |
| 7622 | CEFBS_HasReferenceTypes_HasExceptionHandling, // COPY_EXNREF |
| 7623 | CEFBS_HasReferenceTypes_HasExceptionHandling, // COPY_EXNREF_S |
| 7624 | CEFBS_HasReferenceTypes, // COPY_EXTERNREF |
| 7625 | CEFBS_HasReferenceTypes, // COPY_EXTERNREF_S |
| 7626 | CEFBS_None, // COPY_F32 |
| 7627 | CEFBS_None, // COPY_F32_S |
| 7628 | CEFBS_None, // COPY_F64 |
| 7629 | CEFBS_None, // COPY_F64_S |
| 7630 | CEFBS_HasReferenceTypes, // COPY_FUNCREF |
| 7631 | CEFBS_HasReferenceTypes, // COPY_FUNCREF_S |
| 7632 | CEFBS_None, // COPY_I32 |
| 7633 | CEFBS_None, // COPY_I32_S |
| 7634 | CEFBS_None, // COPY_I64 |
| 7635 | CEFBS_None, // COPY_I64_S |
| 7636 | CEFBS_HasSIMD128, // COPY_V128 |
| 7637 | CEFBS_HasSIMD128, // COPY_V128_S |
| 7638 | CEFBS_None, // CTZ_I32 |
| 7639 | CEFBS_None, // CTZ_I32_S |
| 7640 | CEFBS_None, // CTZ_I64 |
| 7641 | CEFBS_None, // CTZ_I64_S |
| 7642 | CEFBS_HasBulkMemoryOpt, // DATA_DROP |
| 7643 | CEFBS_HasBulkMemoryOpt, // DATA_DROP_S |
| 7644 | CEFBS_None, // DEBUG_UNREACHABLE |
| 7645 | CEFBS_None, // DEBUG_UNREACHABLE_S |
| 7646 | CEFBS_HasExceptionHandling, // DELEGATE |
| 7647 | CEFBS_HasExceptionHandling, // DELEGATE_S |
| 7648 | CEFBS_HasSIMD128_HasFP16, // DIV_F16x8 |
| 7649 | CEFBS_HasSIMD128_HasFP16, // DIV_F16x8_S |
| 7650 | CEFBS_None, // DIV_F32 |
| 7651 | CEFBS_None, // DIV_F32_S |
| 7652 | CEFBS_HasSIMD128, // DIV_F32x4 |
| 7653 | CEFBS_HasSIMD128, // DIV_F32x4_S |
| 7654 | CEFBS_None, // DIV_F64 |
| 7655 | CEFBS_None, // DIV_F64_S |
| 7656 | CEFBS_HasSIMD128, // DIV_F64x2 |
| 7657 | CEFBS_HasSIMD128, // DIV_F64x2_S |
| 7658 | CEFBS_None, // DIV_S_I32 |
| 7659 | CEFBS_None, // DIV_S_I32_S |
| 7660 | CEFBS_None, // DIV_S_I64 |
| 7661 | CEFBS_None, // DIV_S_I64_S |
| 7662 | CEFBS_None, // DIV_U_I32 |
| 7663 | CEFBS_None, // DIV_U_I32_S |
| 7664 | CEFBS_None, // DIV_U_I64 |
| 7665 | CEFBS_None, // DIV_U_I64_S |
| 7666 | CEFBS_HasSIMD128, // DOT |
| 7667 | CEFBS_HasSIMD128, // DOT_S |
| 7668 | CEFBS_HasReferenceTypes_HasExceptionHandling, // DROP_EXNREF |
| 7669 | CEFBS_HasReferenceTypes_HasExceptionHandling, // DROP_EXNREF_S |
| 7670 | CEFBS_HasReferenceTypes, // DROP_EXTERNREF |
| 7671 | CEFBS_HasReferenceTypes, // DROP_EXTERNREF_S |
| 7672 | CEFBS_None, // DROP_F32 |
| 7673 | CEFBS_None, // DROP_F32_S |
| 7674 | CEFBS_None, // DROP_F64 |
| 7675 | CEFBS_None, // DROP_F64_S |
| 7676 | CEFBS_HasReferenceTypes, // DROP_FUNCREF |
| 7677 | CEFBS_HasReferenceTypes, // DROP_FUNCREF_S |
| 7678 | CEFBS_None, // DROP_I32 |
| 7679 | CEFBS_None, // DROP_I32_S |
| 7680 | CEFBS_None, // DROP_I64 |
| 7681 | CEFBS_None, // DROP_I64_S |
| 7682 | CEFBS_HasSIMD128, // DROP_V128 |
| 7683 | CEFBS_HasSIMD128, // DROP_V128_S |
| 7684 | CEFBS_None, // ELSE |
| 7685 | CEFBS_None, // ELSE_S |
| 7686 | CEFBS_None, // END |
| 7687 | CEFBS_None, // END_BLOCK |
| 7688 | CEFBS_None, // END_BLOCK_S |
| 7689 | CEFBS_None, // END_FUNCTION |
| 7690 | CEFBS_None, // END_FUNCTION_S |
| 7691 | CEFBS_None, // END_IF |
| 7692 | CEFBS_None, // END_IF_S |
| 7693 | CEFBS_None, // END_LOOP |
| 7694 | CEFBS_None, // END_LOOP_S |
| 7695 | CEFBS_None, // END_S |
| 7696 | CEFBS_HasExceptionHandling, // END_TRY |
| 7697 | CEFBS_HasExceptionHandling, // END_TRY_S |
| 7698 | CEFBS_HasExceptionHandling, // END_TRY_TABLE |
| 7699 | CEFBS_HasExceptionHandling, // END_TRY_TABLE_S |
| 7700 | CEFBS_None, // EQZ_I32 |
| 7701 | CEFBS_None, // EQZ_I32_S |
| 7702 | CEFBS_None, // EQZ_I64 |
| 7703 | CEFBS_None, // EQZ_I64_S |
| 7704 | CEFBS_HasSIMD128_HasFP16, // EQ_F16x8 |
| 7705 | CEFBS_HasSIMD128_HasFP16, // EQ_F16x8_S |
| 7706 | CEFBS_None, // EQ_F32 |
| 7707 | CEFBS_None, // EQ_F32_S |
| 7708 | CEFBS_HasSIMD128, // EQ_F32x4 |
| 7709 | CEFBS_HasSIMD128, // EQ_F32x4_S |
| 7710 | CEFBS_None, // EQ_F64 |
| 7711 | CEFBS_None, // EQ_F64_S |
| 7712 | CEFBS_HasSIMD128, // EQ_F64x2 |
| 7713 | CEFBS_HasSIMD128, // EQ_F64x2_S |
| 7714 | CEFBS_HasSIMD128, // EQ_I16x8 |
| 7715 | CEFBS_HasSIMD128, // EQ_I16x8_S |
| 7716 | CEFBS_None, // EQ_I32 |
| 7717 | CEFBS_None, // EQ_I32_S |
| 7718 | CEFBS_HasSIMD128, // EQ_I32x4 |
| 7719 | CEFBS_HasSIMD128, // EQ_I32x4_S |
| 7720 | CEFBS_None, // EQ_I64 |
| 7721 | CEFBS_None, // EQ_I64_S |
| 7722 | CEFBS_HasSIMD128, // EQ_I64x2 |
| 7723 | CEFBS_HasSIMD128, // EQ_I64x2_S |
| 7724 | CEFBS_HasSIMD128, // EQ_I8x16 |
| 7725 | CEFBS_HasSIMD128, // EQ_I8x16_S |
| 7726 | CEFBS_HasSIMD128, // EXTMUL_HIGH_S_I16x8 |
| 7727 | CEFBS_HasSIMD128, // EXTMUL_HIGH_S_I16x8_S |
| 7728 | CEFBS_HasSIMD128, // EXTMUL_HIGH_S_I32x4 |
| 7729 | CEFBS_HasSIMD128, // EXTMUL_HIGH_S_I32x4_S |
| 7730 | CEFBS_HasSIMD128, // EXTMUL_HIGH_S_I64x2 |
| 7731 | CEFBS_HasSIMD128, // EXTMUL_HIGH_S_I64x2_S |
| 7732 | CEFBS_HasSIMD128, // EXTMUL_HIGH_U_I16x8 |
| 7733 | CEFBS_HasSIMD128, // EXTMUL_HIGH_U_I16x8_S |
| 7734 | CEFBS_HasSIMD128, // EXTMUL_HIGH_U_I32x4 |
| 7735 | CEFBS_HasSIMD128, // EXTMUL_HIGH_U_I32x4_S |
| 7736 | CEFBS_HasSIMD128, // EXTMUL_HIGH_U_I64x2 |
| 7737 | CEFBS_HasSIMD128, // EXTMUL_HIGH_U_I64x2_S |
| 7738 | CEFBS_HasSIMD128, // EXTMUL_LOW_S_I16x8 |
| 7739 | CEFBS_HasSIMD128, // EXTMUL_LOW_S_I16x8_S |
| 7740 | CEFBS_HasSIMD128, // EXTMUL_LOW_S_I32x4 |
| 7741 | CEFBS_HasSIMD128, // EXTMUL_LOW_S_I32x4_S |
| 7742 | CEFBS_HasSIMD128, // EXTMUL_LOW_S_I64x2 |
| 7743 | CEFBS_HasSIMD128, // EXTMUL_LOW_S_I64x2_S |
| 7744 | CEFBS_HasSIMD128, // EXTMUL_LOW_U_I16x8 |
| 7745 | CEFBS_HasSIMD128, // EXTMUL_LOW_U_I16x8_S |
| 7746 | CEFBS_HasSIMD128, // EXTMUL_LOW_U_I32x4 |
| 7747 | CEFBS_HasSIMD128, // EXTMUL_LOW_U_I32x4_S |
| 7748 | CEFBS_HasSIMD128, // EXTMUL_LOW_U_I64x2 |
| 7749 | CEFBS_HasSIMD128, // EXTMUL_LOW_U_I64x2_S |
| 7750 | CEFBS_HasFP16, // EXTRACT_LANE_F16x8 |
| 7751 | CEFBS_HasFP16, // EXTRACT_LANE_F16x8_S |
| 7752 | CEFBS_HasSIMD128, // EXTRACT_LANE_F32x4 |
| 7753 | CEFBS_HasSIMD128, // EXTRACT_LANE_F32x4_S |
| 7754 | CEFBS_HasSIMD128, // EXTRACT_LANE_F64x2 |
| 7755 | CEFBS_HasSIMD128, // EXTRACT_LANE_F64x2_S |
| 7756 | CEFBS_HasSIMD128, // EXTRACT_LANE_I16x8_s |
| 7757 | CEFBS_HasSIMD128, // EXTRACT_LANE_I16x8_s_S |
| 7758 | CEFBS_HasSIMD128, // EXTRACT_LANE_I16x8_u |
| 7759 | CEFBS_HasSIMD128, // EXTRACT_LANE_I16x8_u_S |
| 7760 | CEFBS_HasSIMD128, // EXTRACT_LANE_I32x4 |
| 7761 | CEFBS_HasSIMD128, // EXTRACT_LANE_I32x4_S |
| 7762 | CEFBS_HasSIMD128, // EXTRACT_LANE_I64x2 |
| 7763 | CEFBS_HasSIMD128, // EXTRACT_LANE_I64x2_S |
| 7764 | CEFBS_HasSIMD128, // EXTRACT_LANE_I8x16_s |
| 7765 | CEFBS_HasSIMD128, // EXTRACT_LANE_I8x16_s_S |
| 7766 | CEFBS_HasSIMD128, // EXTRACT_LANE_I8x16_u |
| 7767 | CEFBS_HasSIMD128, // EXTRACT_LANE_I8x16_u_S |
| 7768 | CEFBS_None, // F32_CONVERT_S_I32 |
| 7769 | CEFBS_None, // F32_CONVERT_S_I32_S |
| 7770 | CEFBS_None, // F32_CONVERT_S_I64 |
| 7771 | CEFBS_None, // F32_CONVERT_S_I64_S |
| 7772 | CEFBS_None, // F32_CONVERT_U_I32 |
| 7773 | CEFBS_None, // F32_CONVERT_U_I32_S |
| 7774 | CEFBS_None, // F32_CONVERT_U_I64 |
| 7775 | CEFBS_None, // F32_CONVERT_U_I64_S |
| 7776 | CEFBS_None, // F32_DEMOTE_F64 |
| 7777 | CEFBS_None, // F32_DEMOTE_F64_S |
| 7778 | CEFBS_None, // F32_REINTERPRET_I32 |
| 7779 | CEFBS_None, // F32_REINTERPRET_I32_S |
| 7780 | CEFBS_None, // F64_CONVERT_S_I32 |
| 7781 | CEFBS_None, // F64_CONVERT_S_I32_S |
| 7782 | CEFBS_None, // F64_CONVERT_S_I64 |
| 7783 | CEFBS_None, // F64_CONVERT_S_I64_S |
| 7784 | CEFBS_None, // F64_CONVERT_U_I32 |
| 7785 | CEFBS_None, // F64_CONVERT_U_I32_S |
| 7786 | CEFBS_None, // F64_CONVERT_U_I64 |
| 7787 | CEFBS_None, // F64_CONVERT_U_I64_S |
| 7788 | CEFBS_None, // F64_PROMOTE_F32 |
| 7789 | CEFBS_None, // F64_PROMOTE_F32_S |
| 7790 | CEFBS_None, // F64_REINTERPRET_I64 |
| 7791 | CEFBS_None, // F64_REINTERPRET_I64_S |
| 7792 | CEFBS_None, // FALLTHROUGH_RETURN |
| 7793 | CEFBS_None, // FALLTHROUGH_RETURN_S |
| 7794 | CEFBS_HasSIMD128_HasFP16, // FLOOR_F16x8 |
| 7795 | CEFBS_HasSIMD128_HasFP16, // FLOOR_F16x8_S |
| 7796 | CEFBS_None, // FLOOR_F32 |
| 7797 | CEFBS_None, // FLOOR_F32_S |
| 7798 | CEFBS_HasSIMD128, // FLOOR_F32x4 |
| 7799 | CEFBS_HasSIMD128, // FLOOR_F32x4_S |
| 7800 | CEFBS_None, // FLOOR_F64 |
| 7801 | CEFBS_None, // FLOOR_F64_S |
| 7802 | CEFBS_HasSIMD128, // FLOOR_F64x2 |
| 7803 | CEFBS_HasSIMD128, // FLOOR_F64x2_S |
| 7804 | CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I32_F32 |
| 7805 | CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I32_F32_S |
| 7806 | CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I32_F64 |
| 7807 | CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I32_F64_S |
| 7808 | CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I64_F32 |
| 7809 | CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I64_F32_S |
| 7810 | CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I64_F64 |
| 7811 | CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I64_F64_S |
| 7812 | CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I32_F32 |
| 7813 | CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I32_F32_S |
| 7814 | CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I32_F64 |
| 7815 | CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I32_F64_S |
| 7816 | CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I64_F32 |
| 7817 | CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I64_F32_S |
| 7818 | CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I64_F64 |
| 7819 | CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I64_F64_S |
| 7820 | CEFBS_HasSIMD128_HasFP16, // GE_F16x8 |
| 7821 | CEFBS_HasSIMD128_HasFP16, // GE_F16x8_S |
| 7822 | CEFBS_None, // GE_F32 |
| 7823 | CEFBS_None, // GE_F32_S |
| 7824 | CEFBS_HasSIMD128, // GE_F32x4 |
| 7825 | CEFBS_HasSIMD128, // GE_F32x4_S |
| 7826 | CEFBS_None, // GE_F64 |
| 7827 | CEFBS_None, // GE_F64_S |
| 7828 | CEFBS_HasSIMD128, // GE_F64x2 |
| 7829 | CEFBS_HasSIMD128, // GE_F64x2_S |
| 7830 | CEFBS_HasSIMD128, // GE_S_I16x8 |
| 7831 | CEFBS_HasSIMD128, // GE_S_I16x8_S |
| 7832 | CEFBS_None, // GE_S_I32 |
| 7833 | CEFBS_None, // GE_S_I32_S |
| 7834 | CEFBS_HasSIMD128, // GE_S_I32x4 |
| 7835 | CEFBS_HasSIMD128, // GE_S_I32x4_S |
| 7836 | CEFBS_None, // GE_S_I64 |
| 7837 | CEFBS_None, // GE_S_I64_S |
| 7838 | CEFBS_HasSIMD128, // GE_S_I64x2 |
| 7839 | CEFBS_HasSIMD128, // GE_S_I64x2_S |
| 7840 | CEFBS_HasSIMD128, // GE_S_I8x16 |
| 7841 | CEFBS_HasSIMD128, // GE_S_I8x16_S |
| 7842 | CEFBS_HasSIMD128, // GE_U_I16x8 |
| 7843 | CEFBS_HasSIMD128, // GE_U_I16x8_S |
| 7844 | CEFBS_None, // GE_U_I32 |
| 7845 | CEFBS_None, // GE_U_I32_S |
| 7846 | CEFBS_HasSIMD128, // GE_U_I32x4 |
| 7847 | CEFBS_HasSIMD128, // GE_U_I32x4_S |
| 7848 | CEFBS_None, // GE_U_I64 |
| 7849 | CEFBS_None, // GE_U_I64_S |
| 7850 | CEFBS_HasSIMD128, // GE_U_I8x16 |
| 7851 | CEFBS_HasSIMD128, // GE_U_I8x16_S |
| 7852 | CEFBS_HasReferenceTypes_HasExceptionHandling, // GLOBAL_GET_EXNREF |
| 7853 | CEFBS_HasReferenceTypes_HasExceptionHandling, // GLOBAL_GET_EXNREF_S |
| 7854 | CEFBS_HasReferenceTypes, // GLOBAL_GET_EXTERNREF |
| 7855 | CEFBS_HasReferenceTypes, // GLOBAL_GET_EXTERNREF_S |
| 7856 | CEFBS_None, // GLOBAL_GET_F32 |
| 7857 | CEFBS_None, // GLOBAL_GET_F32_S |
| 7858 | CEFBS_None, // GLOBAL_GET_F64 |
| 7859 | CEFBS_None, // GLOBAL_GET_F64_S |
| 7860 | CEFBS_HasReferenceTypes, // GLOBAL_GET_FUNCREF |
| 7861 | CEFBS_HasReferenceTypes, // GLOBAL_GET_FUNCREF_S |
| 7862 | CEFBS_None, // GLOBAL_GET_I32 |
| 7863 | CEFBS_None, // GLOBAL_GET_I32_S |
| 7864 | CEFBS_None, // GLOBAL_GET_I64 |
| 7865 | CEFBS_None, // GLOBAL_GET_I64_S |
| 7866 | CEFBS_HasSIMD128, // GLOBAL_GET_V128 |
| 7867 | CEFBS_HasSIMD128, // GLOBAL_GET_V128_S |
| 7868 | CEFBS_HasReferenceTypes_HasExceptionHandling, // GLOBAL_SET_EXNREF |
| 7869 | CEFBS_HasReferenceTypes_HasExceptionHandling, // GLOBAL_SET_EXNREF_S |
| 7870 | CEFBS_HasReferenceTypes, // GLOBAL_SET_EXTERNREF |
| 7871 | CEFBS_HasReferenceTypes, // GLOBAL_SET_EXTERNREF_S |
| 7872 | CEFBS_None, // GLOBAL_SET_F32 |
| 7873 | CEFBS_None, // GLOBAL_SET_F32_S |
| 7874 | CEFBS_None, // GLOBAL_SET_F64 |
| 7875 | CEFBS_None, // GLOBAL_SET_F64_S |
| 7876 | CEFBS_HasReferenceTypes, // GLOBAL_SET_FUNCREF |
| 7877 | CEFBS_HasReferenceTypes, // GLOBAL_SET_FUNCREF_S |
| 7878 | CEFBS_None, // GLOBAL_SET_I32 |
| 7879 | CEFBS_None, // GLOBAL_SET_I32_S |
| 7880 | CEFBS_None, // GLOBAL_SET_I64 |
| 7881 | CEFBS_None, // GLOBAL_SET_I64_S |
| 7882 | CEFBS_HasSIMD128, // GLOBAL_SET_V128 |
| 7883 | CEFBS_HasSIMD128, // GLOBAL_SET_V128_S |
| 7884 | CEFBS_HasSIMD128_HasFP16, // GT_F16x8 |
| 7885 | CEFBS_HasSIMD128_HasFP16, // GT_F16x8_S |
| 7886 | CEFBS_None, // GT_F32 |
| 7887 | CEFBS_None, // GT_F32_S |
| 7888 | CEFBS_HasSIMD128, // GT_F32x4 |
| 7889 | CEFBS_HasSIMD128, // GT_F32x4_S |
| 7890 | CEFBS_None, // GT_F64 |
| 7891 | CEFBS_None, // GT_F64_S |
| 7892 | CEFBS_HasSIMD128, // GT_F64x2 |
| 7893 | CEFBS_HasSIMD128, // GT_F64x2_S |
| 7894 | CEFBS_HasSIMD128, // GT_S_I16x8 |
| 7895 | CEFBS_HasSIMD128, // GT_S_I16x8_S |
| 7896 | CEFBS_None, // GT_S_I32 |
| 7897 | CEFBS_None, // GT_S_I32_S |
| 7898 | CEFBS_HasSIMD128, // GT_S_I32x4 |
| 7899 | CEFBS_HasSIMD128, // GT_S_I32x4_S |
| 7900 | CEFBS_None, // GT_S_I64 |
| 7901 | CEFBS_None, // GT_S_I64_S |
| 7902 | CEFBS_HasSIMD128, // GT_S_I64x2 |
| 7903 | CEFBS_HasSIMD128, // GT_S_I64x2_S |
| 7904 | CEFBS_HasSIMD128, // GT_S_I8x16 |
| 7905 | CEFBS_HasSIMD128, // GT_S_I8x16_S |
| 7906 | CEFBS_HasSIMD128, // GT_U_I16x8 |
| 7907 | CEFBS_HasSIMD128, // GT_U_I16x8_S |
| 7908 | CEFBS_None, // GT_U_I32 |
| 7909 | CEFBS_None, // GT_U_I32_S |
| 7910 | CEFBS_HasSIMD128, // GT_U_I32x4 |
| 7911 | CEFBS_HasSIMD128, // GT_U_I32x4_S |
| 7912 | CEFBS_None, // GT_U_I64 |
| 7913 | CEFBS_None, // GT_U_I64_S |
| 7914 | CEFBS_HasSIMD128, // GT_U_I8x16 |
| 7915 | CEFBS_HasSIMD128, // GT_U_I8x16_S |
| 7916 | CEFBS_HasSignExt, // I32_EXTEND16_S_I32 |
| 7917 | CEFBS_HasSignExt, // I32_EXTEND16_S_I32_S |
| 7918 | CEFBS_HasSignExt, // I32_EXTEND8_S_I32 |
| 7919 | CEFBS_HasSignExt, // I32_EXTEND8_S_I32_S |
| 7920 | CEFBS_None, // I32_REINTERPRET_F32 |
| 7921 | CEFBS_None, // I32_REINTERPRET_F32_S |
| 7922 | CEFBS_None, // I32_TRUNC_S_F32 |
| 7923 | CEFBS_None, // I32_TRUNC_S_F32_S |
| 7924 | CEFBS_None, // I32_TRUNC_S_F64 |
| 7925 | CEFBS_None, // I32_TRUNC_S_F64_S |
| 7926 | CEFBS_HasNontrappingFPToInt, // I32_TRUNC_S_SAT_F32 |
| 7927 | CEFBS_HasNontrappingFPToInt, // I32_TRUNC_S_SAT_F32_S |
| 7928 | CEFBS_HasNontrappingFPToInt, // I32_TRUNC_S_SAT_F64 |
| 7929 | CEFBS_HasNontrappingFPToInt, // I32_TRUNC_S_SAT_F64_S |
| 7930 | CEFBS_None, // I32_TRUNC_U_F32 |
| 7931 | CEFBS_None, // I32_TRUNC_U_F32_S |
| 7932 | CEFBS_None, // I32_TRUNC_U_F64 |
| 7933 | CEFBS_None, // I32_TRUNC_U_F64_S |
| 7934 | CEFBS_HasNontrappingFPToInt, // I32_TRUNC_U_SAT_F32 |
| 7935 | CEFBS_HasNontrappingFPToInt, // I32_TRUNC_U_SAT_F32_S |
| 7936 | CEFBS_HasNontrappingFPToInt, // I32_TRUNC_U_SAT_F64 |
| 7937 | CEFBS_HasNontrappingFPToInt, // I32_TRUNC_U_SAT_F64_S |
| 7938 | CEFBS_None, // I32_WRAP_I64 |
| 7939 | CEFBS_None, // I32_WRAP_I64_S |
| 7940 | CEFBS_HasWideArithmetic, // I64_ADD128 |
| 7941 | CEFBS_HasWideArithmetic, // I64_ADD128_S |
| 7942 | CEFBS_HasSignExt, // I64_EXTEND16_S_I64 |
| 7943 | CEFBS_HasSignExt, // I64_EXTEND16_S_I64_S |
| 7944 | CEFBS_HasSignExt, // I64_EXTEND32_S_I64 |
| 7945 | CEFBS_HasSignExt, // I64_EXTEND32_S_I64_S |
| 7946 | CEFBS_HasSignExt, // I64_EXTEND8_S_I64 |
| 7947 | CEFBS_HasSignExt, // I64_EXTEND8_S_I64_S |
| 7948 | CEFBS_None, // I64_EXTEND_S_I32 |
| 7949 | CEFBS_None, // I64_EXTEND_S_I32_S |
| 7950 | CEFBS_None, // I64_EXTEND_U_I32 |
| 7951 | CEFBS_None, // I64_EXTEND_U_I32_S |
| 7952 | CEFBS_HasWideArithmetic, // I64_MUL_WIDE_S |
| 7953 | CEFBS_HasWideArithmetic, // I64_MUL_WIDE_S_S |
| 7954 | CEFBS_HasWideArithmetic, // I64_MUL_WIDE_U |
| 7955 | CEFBS_HasWideArithmetic, // I64_MUL_WIDE_U_S |
| 7956 | CEFBS_None, // I64_REINTERPRET_F64 |
| 7957 | CEFBS_None, // I64_REINTERPRET_F64_S |
| 7958 | CEFBS_HasWideArithmetic, // I64_SUB128 |
| 7959 | CEFBS_HasWideArithmetic, // I64_SUB128_S |
| 7960 | CEFBS_None, // I64_TRUNC_S_F32 |
| 7961 | CEFBS_None, // I64_TRUNC_S_F32_S |
| 7962 | CEFBS_None, // I64_TRUNC_S_F64 |
| 7963 | CEFBS_None, // I64_TRUNC_S_F64_S |
| 7964 | CEFBS_HasNontrappingFPToInt, // I64_TRUNC_S_SAT_F32 |
| 7965 | CEFBS_HasNontrappingFPToInt, // I64_TRUNC_S_SAT_F32_S |
| 7966 | CEFBS_HasNontrappingFPToInt, // I64_TRUNC_S_SAT_F64 |
| 7967 | CEFBS_HasNontrappingFPToInt, // I64_TRUNC_S_SAT_F64_S |
| 7968 | CEFBS_None, // I64_TRUNC_U_F32 |
| 7969 | CEFBS_None, // I64_TRUNC_U_F32_S |
| 7970 | CEFBS_None, // I64_TRUNC_U_F64 |
| 7971 | CEFBS_None, // I64_TRUNC_U_F64_S |
| 7972 | CEFBS_HasNontrappingFPToInt, // I64_TRUNC_U_SAT_F32 |
| 7973 | CEFBS_HasNontrappingFPToInt, // I64_TRUNC_U_SAT_F32_S |
| 7974 | CEFBS_HasNontrappingFPToInt, // I64_TRUNC_U_SAT_F64 |
| 7975 | CEFBS_HasNontrappingFPToInt, // I64_TRUNC_U_SAT_F64_S |
| 7976 | CEFBS_None, // IF |
| 7977 | CEFBS_None, // IF_S |
| 7978 | CEFBS_HasRelaxedSIMD, // LANESELECT_I16x8 |
| 7979 | CEFBS_HasRelaxedSIMD, // LANESELECT_I16x8_S |
| 7980 | CEFBS_HasRelaxedSIMD, // LANESELECT_I32x4 |
| 7981 | CEFBS_HasRelaxedSIMD, // LANESELECT_I32x4_S |
| 7982 | CEFBS_HasRelaxedSIMD, // LANESELECT_I64x2 |
| 7983 | CEFBS_HasRelaxedSIMD, // LANESELECT_I64x2_S |
| 7984 | CEFBS_HasRelaxedSIMD, // LANESELECT_I8x16 |
| 7985 | CEFBS_HasRelaxedSIMD, // LANESELECT_I8x16_S |
| 7986 | CEFBS_HasSIMD128_HasFP16, // LE_F16x8 |
| 7987 | CEFBS_HasSIMD128_HasFP16, // LE_F16x8_S |
| 7988 | CEFBS_None, // LE_F32 |
| 7989 | CEFBS_None, // LE_F32_S |
| 7990 | CEFBS_HasSIMD128, // LE_F32x4 |
| 7991 | CEFBS_HasSIMD128, // LE_F32x4_S |
| 7992 | CEFBS_None, // LE_F64 |
| 7993 | CEFBS_None, // LE_F64_S |
| 7994 | CEFBS_HasSIMD128, // LE_F64x2 |
| 7995 | CEFBS_HasSIMD128, // LE_F64x2_S |
| 7996 | CEFBS_HasSIMD128, // LE_S_I16x8 |
| 7997 | CEFBS_HasSIMD128, // LE_S_I16x8_S |
| 7998 | CEFBS_None, // LE_S_I32 |
| 7999 | CEFBS_None, // LE_S_I32_S |
| 8000 | CEFBS_HasSIMD128, // LE_S_I32x4 |
| 8001 | CEFBS_HasSIMD128, // LE_S_I32x4_S |
| 8002 | CEFBS_None, // LE_S_I64 |
| 8003 | CEFBS_None, // LE_S_I64_S |
| 8004 | CEFBS_HasSIMD128, // LE_S_I64x2 |
| 8005 | CEFBS_HasSIMD128, // LE_S_I64x2_S |
| 8006 | CEFBS_HasSIMD128, // LE_S_I8x16 |
| 8007 | CEFBS_HasSIMD128, // LE_S_I8x16_S |
| 8008 | CEFBS_HasSIMD128, // LE_U_I16x8 |
| 8009 | CEFBS_HasSIMD128, // LE_U_I16x8_S |
| 8010 | CEFBS_None, // LE_U_I32 |
| 8011 | CEFBS_None, // LE_U_I32_S |
| 8012 | CEFBS_HasSIMD128, // LE_U_I32x4 |
| 8013 | CEFBS_HasSIMD128, // LE_U_I32x4_S |
| 8014 | CEFBS_None, // LE_U_I64 |
| 8015 | CEFBS_None, // LE_U_I64_S |
| 8016 | CEFBS_HasSIMD128, // LE_U_I8x16 |
| 8017 | CEFBS_HasSIMD128, // LE_U_I8x16_S |
| 8018 | CEFBS_HasSIMD128, // LOAD16_SPLAT_A32 |
| 8019 | CEFBS_HasSIMD128, // LOAD16_SPLAT_A32_S |
| 8020 | CEFBS_HasSIMD128, // LOAD16_SPLAT_A64 |
| 8021 | CEFBS_HasSIMD128, // LOAD16_SPLAT_A64_S |
| 8022 | CEFBS_None, // LOAD16_S_I32_A32 |
| 8023 | CEFBS_None, // LOAD16_S_I32_A32_S |
| 8024 | CEFBS_None, // LOAD16_S_I32_A64 |
| 8025 | CEFBS_None, // LOAD16_S_I32_A64_S |
| 8026 | CEFBS_None, // LOAD16_S_I64_A32 |
| 8027 | CEFBS_None, // LOAD16_S_I64_A32_S |
| 8028 | CEFBS_None, // LOAD16_S_I64_A64 |
| 8029 | CEFBS_None, // LOAD16_S_I64_A64_S |
| 8030 | CEFBS_None, // LOAD16_U_I32_A32 |
| 8031 | CEFBS_None, // LOAD16_U_I32_A32_S |
| 8032 | CEFBS_None, // LOAD16_U_I32_A64 |
| 8033 | CEFBS_None, // LOAD16_U_I32_A64_S |
| 8034 | CEFBS_None, // LOAD16_U_I64_A32 |
| 8035 | CEFBS_None, // LOAD16_U_I64_A32_S |
| 8036 | CEFBS_None, // LOAD16_U_I64_A64 |
| 8037 | CEFBS_None, // LOAD16_U_I64_A64_S |
| 8038 | CEFBS_HasSIMD128, // LOAD32_SPLAT_A32 |
| 8039 | CEFBS_HasSIMD128, // LOAD32_SPLAT_A32_S |
| 8040 | CEFBS_HasSIMD128, // LOAD32_SPLAT_A64 |
| 8041 | CEFBS_HasSIMD128, // LOAD32_SPLAT_A64_S |
| 8042 | CEFBS_None, // LOAD32_S_I64_A32 |
| 8043 | CEFBS_None, // LOAD32_S_I64_A32_S |
| 8044 | CEFBS_None, // LOAD32_S_I64_A64 |
| 8045 | CEFBS_None, // LOAD32_S_I64_A64_S |
| 8046 | CEFBS_None, // LOAD32_U_I64_A32 |
| 8047 | CEFBS_None, // LOAD32_U_I64_A32_S |
| 8048 | CEFBS_None, // LOAD32_U_I64_A64 |
| 8049 | CEFBS_None, // LOAD32_U_I64_A64_S |
| 8050 | CEFBS_HasSIMD128, // LOAD64_SPLAT_A32 |
| 8051 | CEFBS_HasSIMD128, // LOAD64_SPLAT_A32_S |
| 8052 | CEFBS_HasSIMD128, // LOAD64_SPLAT_A64 |
| 8053 | CEFBS_HasSIMD128, // LOAD64_SPLAT_A64_S |
| 8054 | CEFBS_HasSIMD128, // LOAD8_SPLAT_A32 |
| 8055 | CEFBS_HasSIMD128, // LOAD8_SPLAT_A32_S |
| 8056 | CEFBS_HasSIMD128, // LOAD8_SPLAT_A64 |
| 8057 | CEFBS_HasSIMD128, // LOAD8_SPLAT_A64_S |
| 8058 | CEFBS_None, // LOAD8_S_I32_A32 |
| 8059 | CEFBS_None, // LOAD8_S_I32_A32_S |
| 8060 | CEFBS_None, // LOAD8_S_I32_A64 |
| 8061 | CEFBS_None, // LOAD8_S_I32_A64_S |
| 8062 | CEFBS_None, // LOAD8_S_I64_A32 |
| 8063 | CEFBS_None, // LOAD8_S_I64_A32_S |
| 8064 | CEFBS_None, // LOAD8_S_I64_A64 |
| 8065 | CEFBS_None, // LOAD8_S_I64_A64_S |
| 8066 | CEFBS_None, // LOAD8_U_I32_A32 |
| 8067 | CEFBS_None, // LOAD8_U_I32_A32_S |
| 8068 | CEFBS_None, // LOAD8_U_I32_A64 |
| 8069 | CEFBS_None, // LOAD8_U_I32_A64_S |
| 8070 | CEFBS_None, // LOAD8_U_I64_A32 |
| 8071 | CEFBS_None, // LOAD8_U_I64_A32_S |
| 8072 | CEFBS_None, // LOAD8_U_I64_A64 |
| 8073 | CEFBS_None, // LOAD8_U_I64_A64_S |
| 8074 | CEFBS_HasSIMD128, // LOAD_EXTEND_S_I16x8_A32 |
| 8075 | CEFBS_HasSIMD128, // LOAD_EXTEND_S_I16x8_A32_S |
| 8076 | CEFBS_HasSIMD128, // LOAD_EXTEND_S_I16x8_A64 |
| 8077 | CEFBS_HasSIMD128, // LOAD_EXTEND_S_I16x8_A64_S |
| 8078 | CEFBS_HasSIMD128, // LOAD_EXTEND_S_I32x4_A32 |
| 8079 | CEFBS_HasSIMD128, // LOAD_EXTEND_S_I32x4_A32_S |
| 8080 | CEFBS_HasSIMD128, // LOAD_EXTEND_S_I32x4_A64 |
| 8081 | CEFBS_HasSIMD128, // LOAD_EXTEND_S_I32x4_A64_S |
| 8082 | CEFBS_HasSIMD128, // LOAD_EXTEND_S_I64x2_A32 |
| 8083 | CEFBS_HasSIMD128, // LOAD_EXTEND_S_I64x2_A32_S |
| 8084 | CEFBS_HasSIMD128, // LOAD_EXTEND_S_I64x2_A64 |
| 8085 | CEFBS_HasSIMD128, // LOAD_EXTEND_S_I64x2_A64_S |
| 8086 | CEFBS_HasSIMD128, // LOAD_EXTEND_U_I16x8_A32 |
| 8087 | CEFBS_HasSIMD128, // LOAD_EXTEND_U_I16x8_A32_S |
| 8088 | CEFBS_HasSIMD128, // LOAD_EXTEND_U_I16x8_A64 |
| 8089 | CEFBS_HasSIMD128, // LOAD_EXTEND_U_I16x8_A64_S |
| 8090 | CEFBS_HasSIMD128, // LOAD_EXTEND_U_I32x4_A32 |
| 8091 | CEFBS_HasSIMD128, // LOAD_EXTEND_U_I32x4_A32_S |
| 8092 | CEFBS_HasSIMD128, // LOAD_EXTEND_U_I32x4_A64 |
| 8093 | CEFBS_HasSIMD128, // LOAD_EXTEND_U_I32x4_A64_S |
| 8094 | CEFBS_HasSIMD128, // LOAD_EXTEND_U_I64x2_A32 |
| 8095 | CEFBS_HasSIMD128, // LOAD_EXTEND_U_I64x2_A32_S |
| 8096 | CEFBS_HasSIMD128, // LOAD_EXTEND_U_I64x2_A64 |
| 8097 | CEFBS_HasSIMD128, // LOAD_EXTEND_U_I64x2_A64_S |
| 8098 | CEFBS_HasFP16, // LOAD_F16_F32_A32 |
| 8099 | CEFBS_HasFP16, // LOAD_F16_F32_A32_S |
| 8100 | CEFBS_HasFP16, // LOAD_F16_F32_A64 |
| 8101 | CEFBS_HasFP16, // LOAD_F16_F32_A64_S |
| 8102 | CEFBS_None, // LOAD_F32_A32 |
| 8103 | CEFBS_None, // LOAD_F32_A32_S |
| 8104 | CEFBS_None, // LOAD_F32_A64 |
| 8105 | CEFBS_None, // LOAD_F32_A64_S |
| 8106 | CEFBS_None, // LOAD_F64_A32 |
| 8107 | CEFBS_None, // LOAD_F64_A32_S |
| 8108 | CEFBS_None, // LOAD_F64_A64 |
| 8109 | CEFBS_None, // LOAD_F64_A64_S |
| 8110 | CEFBS_None, // LOAD_I32_A32 |
| 8111 | CEFBS_None, // LOAD_I32_A32_S |
| 8112 | CEFBS_None, // LOAD_I32_A64 |
| 8113 | CEFBS_None, // LOAD_I32_A64_S |
| 8114 | CEFBS_None, // LOAD_I64_A32 |
| 8115 | CEFBS_None, // LOAD_I64_A32_S |
| 8116 | CEFBS_None, // LOAD_I64_A64 |
| 8117 | CEFBS_None, // LOAD_I64_A64_S |
| 8118 | CEFBS_HasSIMD128, // LOAD_LANE_16_A32 |
| 8119 | CEFBS_HasSIMD128, // LOAD_LANE_16_A32_S |
| 8120 | CEFBS_HasSIMD128, // LOAD_LANE_16_A64 |
| 8121 | CEFBS_HasSIMD128, // LOAD_LANE_16_A64_S |
| 8122 | CEFBS_HasSIMD128, // LOAD_LANE_32_A32 |
| 8123 | CEFBS_HasSIMD128, // LOAD_LANE_32_A32_S |
| 8124 | CEFBS_HasSIMD128, // LOAD_LANE_32_A64 |
| 8125 | CEFBS_HasSIMD128, // LOAD_LANE_32_A64_S |
| 8126 | CEFBS_HasSIMD128, // LOAD_LANE_64_A32 |
| 8127 | CEFBS_HasSIMD128, // LOAD_LANE_64_A32_S |
| 8128 | CEFBS_HasSIMD128, // LOAD_LANE_64_A64 |
| 8129 | CEFBS_HasSIMD128, // LOAD_LANE_64_A64_S |
| 8130 | CEFBS_HasSIMD128, // LOAD_LANE_8_A32 |
| 8131 | CEFBS_HasSIMD128, // LOAD_LANE_8_A32_S |
| 8132 | CEFBS_HasSIMD128, // LOAD_LANE_8_A64 |
| 8133 | CEFBS_HasSIMD128, // LOAD_LANE_8_A64_S |
| 8134 | CEFBS_HasSIMD128, // LOAD_V128_A32 |
| 8135 | CEFBS_HasSIMD128, // LOAD_V128_A32_S |
| 8136 | CEFBS_HasSIMD128, // LOAD_V128_A64 |
| 8137 | CEFBS_HasSIMD128, // LOAD_V128_A64_S |
| 8138 | CEFBS_HasSIMD128, // LOAD_ZERO_32_A32 |
| 8139 | CEFBS_HasSIMD128, // LOAD_ZERO_32_A32_S |
| 8140 | CEFBS_HasSIMD128, // LOAD_ZERO_32_A64 |
| 8141 | CEFBS_HasSIMD128, // LOAD_ZERO_32_A64_S |
| 8142 | CEFBS_HasSIMD128, // LOAD_ZERO_64_A32 |
| 8143 | CEFBS_HasSIMD128, // LOAD_ZERO_64_A32_S |
| 8144 | CEFBS_HasSIMD128, // LOAD_ZERO_64_A64 |
| 8145 | CEFBS_HasSIMD128, // LOAD_ZERO_64_A64_S |
| 8146 | CEFBS_HasReferenceTypes_HasExceptionHandling, // LOCAL_GET_EXNREF |
| 8147 | CEFBS_HasReferenceTypes_HasExceptionHandling, // LOCAL_GET_EXNREF_S |
| 8148 | CEFBS_HasReferenceTypes, // LOCAL_GET_EXTERNREF |
| 8149 | CEFBS_HasReferenceTypes, // LOCAL_GET_EXTERNREF_S |
| 8150 | CEFBS_None, // LOCAL_GET_F32 |
| 8151 | CEFBS_None, // LOCAL_GET_F32_S |
| 8152 | CEFBS_None, // LOCAL_GET_F64 |
| 8153 | CEFBS_None, // LOCAL_GET_F64_S |
| 8154 | CEFBS_HasReferenceTypes, // LOCAL_GET_FUNCREF |
| 8155 | CEFBS_HasReferenceTypes, // LOCAL_GET_FUNCREF_S |
| 8156 | CEFBS_None, // LOCAL_GET_I32 |
| 8157 | CEFBS_None, // LOCAL_GET_I32_S |
| 8158 | CEFBS_None, // LOCAL_GET_I64 |
| 8159 | CEFBS_None, // LOCAL_GET_I64_S |
| 8160 | CEFBS_HasSIMD128, // LOCAL_GET_V128 |
| 8161 | CEFBS_HasSIMD128, // LOCAL_GET_V128_S |
| 8162 | CEFBS_HasReferenceTypes_HasExceptionHandling, // LOCAL_SET_EXNREF |
| 8163 | CEFBS_HasReferenceTypes_HasExceptionHandling, // LOCAL_SET_EXNREF_S |
| 8164 | CEFBS_HasReferenceTypes, // LOCAL_SET_EXTERNREF |
| 8165 | CEFBS_HasReferenceTypes, // LOCAL_SET_EXTERNREF_S |
| 8166 | CEFBS_None, // LOCAL_SET_F32 |
| 8167 | CEFBS_None, // LOCAL_SET_F32_S |
| 8168 | CEFBS_None, // LOCAL_SET_F64 |
| 8169 | CEFBS_None, // LOCAL_SET_F64_S |
| 8170 | CEFBS_HasReferenceTypes, // LOCAL_SET_FUNCREF |
| 8171 | CEFBS_HasReferenceTypes, // LOCAL_SET_FUNCREF_S |
| 8172 | CEFBS_None, // LOCAL_SET_I32 |
| 8173 | CEFBS_None, // LOCAL_SET_I32_S |
| 8174 | CEFBS_None, // LOCAL_SET_I64 |
| 8175 | CEFBS_None, // LOCAL_SET_I64_S |
| 8176 | CEFBS_HasSIMD128, // LOCAL_SET_V128 |
| 8177 | CEFBS_HasSIMD128, // LOCAL_SET_V128_S |
| 8178 | CEFBS_HasReferenceTypes_HasExceptionHandling, // LOCAL_TEE_EXNREF |
| 8179 | CEFBS_HasReferenceTypes_HasExceptionHandling, // LOCAL_TEE_EXNREF_S |
| 8180 | CEFBS_HasReferenceTypes, // LOCAL_TEE_EXTERNREF |
| 8181 | CEFBS_HasReferenceTypes, // LOCAL_TEE_EXTERNREF_S |
| 8182 | CEFBS_None, // LOCAL_TEE_F32 |
| 8183 | CEFBS_None, // LOCAL_TEE_F32_S |
| 8184 | CEFBS_None, // LOCAL_TEE_F64 |
| 8185 | CEFBS_None, // LOCAL_TEE_F64_S |
| 8186 | CEFBS_HasReferenceTypes, // LOCAL_TEE_FUNCREF |
| 8187 | CEFBS_HasReferenceTypes, // LOCAL_TEE_FUNCREF_S |
| 8188 | CEFBS_None, // LOCAL_TEE_I32 |
| 8189 | CEFBS_None, // LOCAL_TEE_I32_S |
| 8190 | CEFBS_None, // LOCAL_TEE_I64 |
| 8191 | CEFBS_None, // LOCAL_TEE_I64_S |
| 8192 | CEFBS_HasSIMD128, // LOCAL_TEE_V128 |
| 8193 | CEFBS_HasSIMD128, // LOCAL_TEE_V128_S |
| 8194 | CEFBS_None, // LOOP |
| 8195 | CEFBS_None, // LOOP_S |
| 8196 | CEFBS_HasSIMD128_HasFP16, // LT_F16x8 |
| 8197 | CEFBS_HasSIMD128_HasFP16, // LT_F16x8_S |
| 8198 | CEFBS_None, // LT_F32 |
| 8199 | CEFBS_None, // LT_F32_S |
| 8200 | CEFBS_HasSIMD128, // LT_F32x4 |
| 8201 | CEFBS_HasSIMD128, // LT_F32x4_S |
| 8202 | CEFBS_None, // LT_F64 |
| 8203 | CEFBS_None, // LT_F64_S |
| 8204 | CEFBS_HasSIMD128, // LT_F64x2 |
| 8205 | CEFBS_HasSIMD128, // LT_F64x2_S |
| 8206 | CEFBS_HasSIMD128, // LT_S_I16x8 |
| 8207 | CEFBS_HasSIMD128, // LT_S_I16x8_S |
| 8208 | CEFBS_None, // LT_S_I32 |
| 8209 | CEFBS_None, // LT_S_I32_S |
| 8210 | CEFBS_HasSIMD128, // LT_S_I32x4 |
| 8211 | CEFBS_HasSIMD128, // LT_S_I32x4_S |
| 8212 | CEFBS_None, // LT_S_I64 |
| 8213 | CEFBS_None, // LT_S_I64_S |
| 8214 | CEFBS_HasSIMD128, // LT_S_I64x2 |
| 8215 | CEFBS_HasSIMD128, // LT_S_I64x2_S |
| 8216 | CEFBS_HasSIMD128, // LT_S_I8x16 |
| 8217 | CEFBS_HasSIMD128, // LT_S_I8x16_S |
| 8218 | CEFBS_HasSIMD128, // LT_U_I16x8 |
| 8219 | CEFBS_HasSIMD128, // LT_U_I16x8_S |
| 8220 | CEFBS_None, // LT_U_I32 |
| 8221 | CEFBS_None, // LT_U_I32_S |
| 8222 | CEFBS_HasSIMD128, // LT_U_I32x4 |
| 8223 | CEFBS_HasSIMD128, // LT_U_I32x4_S |
| 8224 | CEFBS_None, // LT_U_I64 |
| 8225 | CEFBS_None, // LT_U_I64_S |
| 8226 | CEFBS_HasSIMD128, // LT_U_I8x16 |
| 8227 | CEFBS_HasSIMD128, // LT_U_I8x16_S |
| 8228 | CEFBS_HasSIMD128_HasFP16, // MADD_F16x8 |
| 8229 | CEFBS_HasSIMD128_HasFP16, // MADD_F16x8_S |
| 8230 | CEFBS_HasSIMD128_HasRelaxedSIMD, // MADD_F32x4 |
| 8231 | CEFBS_HasSIMD128_HasRelaxedSIMD, // MADD_F32x4_S |
| 8232 | CEFBS_HasSIMD128_HasRelaxedSIMD, // MADD_F64x2 |
| 8233 | CEFBS_HasSIMD128_HasRelaxedSIMD, // MADD_F64x2_S |
| 8234 | CEFBS_HasSIMD128_HasFP16, // MAX_F16x8 |
| 8235 | CEFBS_HasSIMD128_HasFP16, // MAX_F16x8_S |
| 8236 | CEFBS_None, // MAX_F32 |
| 8237 | CEFBS_None, // MAX_F32_S |
| 8238 | CEFBS_HasSIMD128, // MAX_F32x4 |
| 8239 | CEFBS_HasSIMD128, // MAX_F32x4_S |
| 8240 | CEFBS_None, // MAX_F64 |
| 8241 | CEFBS_None, // MAX_F64_S |
| 8242 | CEFBS_HasSIMD128, // MAX_F64x2 |
| 8243 | CEFBS_HasSIMD128, // MAX_F64x2_S |
| 8244 | CEFBS_HasSIMD128, // MAX_S_I16x8 |
| 8245 | CEFBS_HasSIMD128, // MAX_S_I16x8_S |
| 8246 | CEFBS_HasSIMD128, // MAX_S_I32x4 |
| 8247 | CEFBS_HasSIMD128, // MAX_S_I32x4_S |
| 8248 | CEFBS_HasSIMD128, // MAX_S_I8x16 |
| 8249 | CEFBS_HasSIMD128, // MAX_S_I8x16_S |
| 8250 | CEFBS_HasSIMD128, // MAX_U_I16x8 |
| 8251 | CEFBS_HasSIMD128, // MAX_U_I16x8_S |
| 8252 | CEFBS_HasSIMD128, // MAX_U_I32x4 |
| 8253 | CEFBS_HasSIMD128, // MAX_U_I32x4_S |
| 8254 | CEFBS_HasSIMD128, // MAX_U_I8x16 |
| 8255 | CEFBS_HasSIMD128, // MAX_U_I8x16_S |
| 8256 | CEFBS_HasBulkMemoryOpt, // MEMCPY_A32 |
| 8257 | CEFBS_HasBulkMemoryOpt, // MEMCPY_A32_S |
| 8258 | CEFBS_HasBulkMemoryOpt, // MEMCPY_A64 |
| 8259 | CEFBS_HasBulkMemoryOpt, // MEMCPY_A64_S |
| 8260 | CEFBS_HasAtomics, // MEMORY_ATOMIC_NOTIFY_A32 |
| 8261 | CEFBS_HasAtomics, // MEMORY_ATOMIC_NOTIFY_A32_S |
| 8262 | CEFBS_HasAtomics, // MEMORY_ATOMIC_NOTIFY_A64 |
| 8263 | CEFBS_HasAtomics, // MEMORY_ATOMIC_NOTIFY_A64_S |
| 8264 | CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT32_A32 |
| 8265 | CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT32_A32_S |
| 8266 | CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT32_A64 |
| 8267 | CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT32_A64_S |
| 8268 | CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT64_A32 |
| 8269 | CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT64_A32_S |
| 8270 | CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT64_A64 |
| 8271 | CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT64_A64_S |
| 8272 | CEFBS_HasBulkMemoryOpt, // MEMORY_COPY_A32 |
| 8273 | CEFBS_HasBulkMemoryOpt, // MEMORY_COPY_A32_S |
| 8274 | CEFBS_HasBulkMemoryOpt, // MEMORY_COPY_A64 |
| 8275 | CEFBS_HasBulkMemoryOpt, // MEMORY_COPY_A64_S |
| 8276 | CEFBS_HasBulkMemoryOpt, // MEMORY_FILL_A32 |
| 8277 | CEFBS_HasBulkMemoryOpt, // MEMORY_FILL_A32_S |
| 8278 | CEFBS_HasBulkMemoryOpt, // MEMORY_FILL_A64 |
| 8279 | CEFBS_HasBulkMemoryOpt, // MEMORY_FILL_A64_S |
| 8280 | CEFBS_HasBulkMemoryOpt, // MEMORY_INIT_A32 |
| 8281 | CEFBS_HasBulkMemoryOpt, // MEMORY_INIT_A32_S |
| 8282 | CEFBS_HasBulkMemoryOpt, // MEMORY_INIT_A64 |
| 8283 | CEFBS_HasBulkMemoryOpt, // MEMORY_INIT_A64_S |
| 8284 | CEFBS_HasBulkMemoryOpt, // MEMSET_A32 |
| 8285 | CEFBS_HasBulkMemoryOpt, // MEMSET_A32_S |
| 8286 | CEFBS_HasBulkMemoryOpt, // MEMSET_A64 |
| 8287 | CEFBS_HasBulkMemoryOpt, // MEMSET_A64_S |
| 8288 | CEFBS_HasSIMD128_HasFP16, // MIN_F16x8 |
| 8289 | CEFBS_HasSIMD128_HasFP16, // MIN_F16x8_S |
| 8290 | CEFBS_None, // MIN_F32 |
| 8291 | CEFBS_None, // MIN_F32_S |
| 8292 | CEFBS_HasSIMD128, // MIN_F32x4 |
| 8293 | CEFBS_HasSIMD128, // MIN_F32x4_S |
| 8294 | CEFBS_None, // MIN_F64 |
| 8295 | CEFBS_None, // MIN_F64_S |
| 8296 | CEFBS_HasSIMD128, // MIN_F64x2 |
| 8297 | CEFBS_HasSIMD128, // MIN_F64x2_S |
| 8298 | CEFBS_HasSIMD128, // MIN_S_I16x8 |
| 8299 | CEFBS_HasSIMD128, // MIN_S_I16x8_S |
| 8300 | CEFBS_HasSIMD128, // MIN_S_I32x4 |
| 8301 | CEFBS_HasSIMD128, // MIN_S_I32x4_S |
| 8302 | CEFBS_HasSIMD128, // MIN_S_I8x16 |
| 8303 | CEFBS_HasSIMD128, // MIN_S_I8x16_S |
| 8304 | CEFBS_HasSIMD128, // MIN_U_I16x8 |
| 8305 | CEFBS_HasSIMD128, // MIN_U_I16x8_S |
| 8306 | CEFBS_HasSIMD128, // MIN_U_I32x4 |
| 8307 | CEFBS_HasSIMD128, // MIN_U_I32x4_S |
| 8308 | CEFBS_HasSIMD128, // MIN_U_I8x16 |
| 8309 | CEFBS_HasSIMD128, // MIN_U_I8x16_S |
| 8310 | CEFBS_HasSIMD128_HasFP16, // MUL_F16x8 |
| 8311 | CEFBS_HasSIMD128_HasFP16, // MUL_F16x8_S |
| 8312 | CEFBS_None, // MUL_F32 |
| 8313 | CEFBS_None, // MUL_F32_S |
| 8314 | CEFBS_HasSIMD128, // MUL_F32x4 |
| 8315 | CEFBS_HasSIMD128, // MUL_F32x4_S |
| 8316 | CEFBS_None, // MUL_F64 |
| 8317 | CEFBS_None, // MUL_F64_S |
| 8318 | CEFBS_HasSIMD128, // MUL_F64x2 |
| 8319 | CEFBS_HasSIMD128, // MUL_F64x2_S |
| 8320 | CEFBS_HasSIMD128, // MUL_I16x8 |
| 8321 | CEFBS_HasSIMD128, // MUL_I16x8_S |
| 8322 | CEFBS_None, // MUL_I32 |
| 8323 | CEFBS_None, // MUL_I32_S |
| 8324 | CEFBS_HasSIMD128, // MUL_I32x4 |
| 8325 | CEFBS_HasSIMD128, // MUL_I32x4_S |
| 8326 | CEFBS_None, // MUL_I64 |
| 8327 | CEFBS_None, // MUL_I64_S |
| 8328 | CEFBS_HasSIMD128, // MUL_I64x2 |
| 8329 | CEFBS_HasSIMD128, // MUL_I64x2_S |
| 8330 | CEFBS_HasSIMD128, // NARROW_S_I16x8 |
| 8331 | CEFBS_HasSIMD128, // NARROW_S_I16x8_S |
| 8332 | CEFBS_HasSIMD128, // NARROW_S_I8x16 |
| 8333 | CEFBS_HasSIMD128, // NARROW_S_I8x16_S |
| 8334 | CEFBS_HasSIMD128, // NARROW_U_I16x8 |
| 8335 | CEFBS_HasSIMD128, // NARROW_U_I16x8_S |
| 8336 | CEFBS_HasSIMD128, // NARROW_U_I8x16 |
| 8337 | CEFBS_HasSIMD128, // NARROW_U_I8x16_S |
| 8338 | CEFBS_HasSIMD128_HasFP16, // NEAREST_F16x8 |
| 8339 | CEFBS_HasSIMD128_HasFP16, // NEAREST_F16x8_S |
| 8340 | CEFBS_None, // NEAREST_F32 |
| 8341 | CEFBS_None, // NEAREST_F32_S |
| 8342 | CEFBS_HasSIMD128, // NEAREST_F32x4 |
| 8343 | CEFBS_HasSIMD128, // NEAREST_F32x4_S |
| 8344 | CEFBS_None, // NEAREST_F64 |
| 8345 | CEFBS_None, // NEAREST_F64_S |
| 8346 | CEFBS_HasSIMD128, // NEAREST_F64x2 |
| 8347 | CEFBS_HasSIMD128, // NEAREST_F64x2_S |
| 8348 | CEFBS_HasSIMD128_HasFP16, // NEG_F16x8 |
| 8349 | CEFBS_HasSIMD128_HasFP16, // NEG_F16x8_S |
| 8350 | CEFBS_None, // NEG_F32 |
| 8351 | CEFBS_None, // NEG_F32_S |
| 8352 | CEFBS_HasSIMD128, // NEG_F32x4 |
| 8353 | CEFBS_HasSIMD128, // NEG_F32x4_S |
| 8354 | CEFBS_None, // NEG_F64 |
| 8355 | CEFBS_None, // NEG_F64_S |
| 8356 | CEFBS_HasSIMD128, // NEG_F64x2 |
| 8357 | CEFBS_HasSIMD128, // NEG_F64x2_S |
| 8358 | CEFBS_HasSIMD128, // NEG_I16x8 |
| 8359 | CEFBS_HasSIMD128, // NEG_I16x8_S |
| 8360 | CEFBS_HasSIMD128, // NEG_I32x4 |
| 8361 | CEFBS_HasSIMD128, // NEG_I32x4_S |
| 8362 | CEFBS_HasSIMD128, // NEG_I64x2 |
| 8363 | CEFBS_HasSIMD128, // NEG_I64x2_S |
| 8364 | CEFBS_HasSIMD128, // NEG_I8x16 |
| 8365 | CEFBS_HasSIMD128, // NEG_I8x16_S |
| 8366 | CEFBS_HasSIMD128_HasFP16, // NE_F16x8 |
| 8367 | CEFBS_HasSIMD128_HasFP16, // NE_F16x8_S |
| 8368 | CEFBS_None, // NE_F32 |
| 8369 | CEFBS_None, // NE_F32_S |
| 8370 | CEFBS_HasSIMD128, // NE_F32x4 |
| 8371 | CEFBS_HasSIMD128, // NE_F32x4_S |
| 8372 | CEFBS_None, // NE_F64 |
| 8373 | CEFBS_None, // NE_F64_S |
| 8374 | CEFBS_HasSIMD128, // NE_F64x2 |
| 8375 | CEFBS_HasSIMD128, // NE_F64x2_S |
| 8376 | CEFBS_HasSIMD128, // NE_I16x8 |
| 8377 | CEFBS_HasSIMD128, // NE_I16x8_S |
| 8378 | CEFBS_None, // NE_I32 |
| 8379 | CEFBS_None, // NE_I32_S |
| 8380 | CEFBS_HasSIMD128, // NE_I32x4 |
| 8381 | CEFBS_HasSIMD128, // NE_I32x4_S |
| 8382 | CEFBS_None, // NE_I64 |
| 8383 | CEFBS_None, // NE_I64_S |
| 8384 | CEFBS_HasSIMD128, // NE_I64x2 |
| 8385 | CEFBS_HasSIMD128, // NE_I64x2_S |
| 8386 | CEFBS_HasSIMD128, // NE_I8x16 |
| 8387 | CEFBS_HasSIMD128, // NE_I8x16_S |
| 8388 | CEFBS_HasSIMD128_HasFP16, // NMADD_F16x8 |
| 8389 | CEFBS_HasSIMD128_HasFP16, // NMADD_F16x8_S |
| 8390 | CEFBS_HasSIMD128_HasRelaxedSIMD, // NMADD_F32x4 |
| 8391 | CEFBS_HasSIMD128_HasRelaxedSIMD, // NMADD_F32x4_S |
| 8392 | CEFBS_HasSIMD128_HasRelaxedSIMD, // NMADD_F64x2 |
| 8393 | CEFBS_HasSIMD128_HasRelaxedSIMD, // NMADD_F64x2_S |
| 8394 | CEFBS_None, // NOP |
| 8395 | CEFBS_None, // NOP_S |
| 8396 | CEFBS_HasSIMD128, // NOT |
| 8397 | CEFBS_HasSIMD128, // NOT_S |
| 8398 | CEFBS_HasSIMD128, // OR |
| 8399 | CEFBS_None, // OR_I32 |
| 8400 | CEFBS_None, // OR_I32_S |
| 8401 | CEFBS_None, // OR_I64 |
| 8402 | CEFBS_None, // OR_I64_S |
| 8403 | CEFBS_HasSIMD128, // OR_S |
| 8404 | CEFBS_HasSIMD128_HasFP16, // PMAX_F16x8 |
| 8405 | CEFBS_HasSIMD128_HasFP16, // PMAX_F16x8_S |
| 8406 | CEFBS_HasSIMD128, // PMAX_F32x4 |
| 8407 | CEFBS_HasSIMD128, // PMAX_F32x4_S |
| 8408 | CEFBS_HasSIMD128, // PMAX_F64x2 |
| 8409 | CEFBS_HasSIMD128, // PMAX_F64x2_S |
| 8410 | CEFBS_HasSIMD128_HasFP16, // PMIN_F16x8 |
| 8411 | CEFBS_HasSIMD128_HasFP16, // PMIN_F16x8_S |
| 8412 | CEFBS_HasSIMD128, // PMIN_F32x4 |
| 8413 | CEFBS_HasSIMD128, // PMIN_F32x4_S |
| 8414 | CEFBS_HasSIMD128, // PMIN_F64x2 |
| 8415 | CEFBS_HasSIMD128, // PMIN_F64x2_S |
| 8416 | CEFBS_None, // POPCNT_I32 |
| 8417 | CEFBS_None, // POPCNT_I32_S |
| 8418 | CEFBS_None, // POPCNT_I64 |
| 8419 | CEFBS_None, // POPCNT_I64_S |
| 8420 | CEFBS_HasSIMD128, // POPCNT_I8x16 |
| 8421 | CEFBS_HasSIMD128, // POPCNT_I8x16_S |
| 8422 | CEFBS_HasSIMD128, // Q15MULR_SAT_S_I16x8 |
| 8423 | CEFBS_HasSIMD128, // Q15MULR_SAT_S_I16x8_S |
| 8424 | CEFBS_HasGC, // REF_CAST_FUNCREF |
| 8425 | CEFBS_HasGC, // REF_CAST_FUNCREF_S |
| 8426 | CEFBS_HasReferenceTypes, // REF_FUNC |
| 8427 | CEFBS_HasReferenceTypes, // REF_FUNC_S |
| 8428 | CEFBS_HasReferenceTypes, // REF_IS_NULL_EXNREF |
| 8429 | CEFBS_HasReferenceTypes, // REF_IS_NULL_EXNREF_S |
| 8430 | CEFBS_HasReferenceTypes, // REF_IS_NULL_EXTERNREF |
| 8431 | CEFBS_HasReferenceTypes, // REF_IS_NULL_EXTERNREF_S |
| 8432 | CEFBS_HasReferenceTypes, // REF_IS_NULL_FUNCREF |
| 8433 | CEFBS_HasReferenceTypes, // REF_IS_NULL_FUNCREF_S |
| 8434 | CEFBS_HasReferenceTypes, // REF_NULL_EXNREF |
| 8435 | CEFBS_HasReferenceTypes, // REF_NULL_EXNREF_S |
| 8436 | CEFBS_HasReferenceTypes, // REF_NULL_EXTERNREF |
| 8437 | CEFBS_HasReferenceTypes, // REF_NULL_EXTERNREF_S |
| 8438 | CEFBS_HasReferenceTypes, // REF_NULL_FUNCREF |
| 8439 | CEFBS_HasReferenceTypes, // REF_NULL_FUNCREF_S |
| 8440 | CEFBS_HasGC, // REF_TEST_FUNCREF |
| 8441 | CEFBS_HasGC, // REF_TEST_FUNCREF_S |
| 8442 | CEFBS_HasRelaxedSIMD, // RELAXED_DOT |
| 8443 | CEFBS_HasRelaxedSIMD, // RELAXED_DOT_ADD |
| 8444 | CEFBS_HasRelaxedSIMD, // RELAXED_DOT_ADD_S |
| 8445 | CEFBS_HasRelaxedSIMD, // RELAXED_DOT_BFLOAT |
| 8446 | CEFBS_HasRelaxedSIMD, // RELAXED_DOT_BFLOAT_S |
| 8447 | CEFBS_HasRelaxedSIMD, // RELAXED_DOT_S |
| 8448 | CEFBS_HasRelaxedSIMD, // RELAXED_Q15MULR_S_I16x8 |
| 8449 | CEFBS_HasRelaxedSIMD, // RELAXED_Q15MULR_S_I16x8_S |
| 8450 | CEFBS_HasRelaxedSIMD, // RELAXED_SWIZZLE |
| 8451 | CEFBS_HasRelaxedSIMD, // RELAXED_SWIZZLE_S |
| 8452 | CEFBS_None, // REM_S_I32 |
| 8453 | CEFBS_None, // REM_S_I32_S |
| 8454 | CEFBS_None, // REM_S_I64 |
| 8455 | CEFBS_None, // REM_S_I64_S |
| 8456 | CEFBS_None, // REM_U_I32 |
| 8457 | CEFBS_None, // REM_U_I32_S |
| 8458 | CEFBS_None, // REM_U_I64 |
| 8459 | CEFBS_None, // REM_U_I64_S |
| 8460 | CEFBS_HasFP16, // REPLACE_LANE_F16x8 |
| 8461 | CEFBS_HasFP16, // REPLACE_LANE_F16x8_S |
| 8462 | CEFBS_HasSIMD128, // REPLACE_LANE_F32x4 |
| 8463 | CEFBS_HasSIMD128, // REPLACE_LANE_F32x4_S |
| 8464 | CEFBS_HasSIMD128, // REPLACE_LANE_F64x2 |
| 8465 | CEFBS_HasSIMD128, // REPLACE_LANE_F64x2_S |
| 8466 | CEFBS_HasSIMD128, // REPLACE_LANE_I16x8 |
| 8467 | CEFBS_HasSIMD128, // REPLACE_LANE_I16x8_S |
| 8468 | CEFBS_HasSIMD128, // REPLACE_LANE_I32x4 |
| 8469 | CEFBS_HasSIMD128, // REPLACE_LANE_I32x4_S |
| 8470 | CEFBS_HasSIMD128, // REPLACE_LANE_I64x2 |
| 8471 | CEFBS_HasSIMD128, // REPLACE_LANE_I64x2_S |
| 8472 | CEFBS_HasSIMD128, // REPLACE_LANE_I8x16 |
| 8473 | CEFBS_HasSIMD128, // REPLACE_LANE_I8x16_S |
| 8474 | CEFBS_HasExceptionHandling, // RETHROW |
| 8475 | CEFBS_HasExceptionHandling, // RETHROW_S |
| 8476 | CEFBS_None, // RETURN |
| 8477 | CEFBS_None, // RETURN_S |
| 8478 | CEFBS_HasTailCall, // RET_CALL |
| 8479 | CEFBS_HasTailCall, // RET_CALL_INDIRECT |
| 8480 | CEFBS_HasTailCall, // RET_CALL_INDIRECT_S |
| 8481 | CEFBS_HasTailCall_HasGC, // RET_CALL_REF |
| 8482 | CEFBS_HasTailCall_HasGC, // RET_CALL_REF_S |
| 8483 | CEFBS_HasTailCall, // RET_CALL_S |
| 8484 | CEFBS_None, // ROTL_I32 |
| 8485 | CEFBS_None, // ROTL_I32_S |
| 8486 | CEFBS_None, // ROTL_I64 |
| 8487 | CEFBS_None, // ROTL_I64_S |
| 8488 | CEFBS_None, // ROTR_I32 |
| 8489 | CEFBS_None, // ROTR_I32_S |
| 8490 | CEFBS_None, // ROTR_I64 |
| 8491 | CEFBS_None, // ROTR_I64_S |
| 8492 | CEFBS_HasReferenceTypes, // SELECT_EXNREF |
| 8493 | CEFBS_HasReferenceTypes, // SELECT_EXNREF_S |
| 8494 | CEFBS_HasReferenceTypes, // SELECT_EXTERNREF |
| 8495 | CEFBS_HasReferenceTypes, // SELECT_EXTERNREF_S |
| 8496 | CEFBS_None, // SELECT_F32 |
| 8497 | CEFBS_None, // SELECT_F32_S |
| 8498 | CEFBS_None, // SELECT_F64 |
| 8499 | CEFBS_None, // SELECT_F64_S |
| 8500 | CEFBS_HasReferenceTypes, // SELECT_FUNCREF |
| 8501 | CEFBS_HasReferenceTypes, // SELECT_FUNCREF_S |
| 8502 | CEFBS_None, // SELECT_I32 |
| 8503 | CEFBS_None, // SELECT_I32_S |
| 8504 | CEFBS_None, // SELECT_I64 |
| 8505 | CEFBS_None, // SELECT_I64_S |
| 8506 | CEFBS_HasReferenceTypes, // SELECT_T |
| 8507 | CEFBS_HasReferenceTypes, // SELECT_T_S |
| 8508 | CEFBS_None, // SELECT_V128 |
| 8509 | CEFBS_None, // SELECT_V128_S |
| 8510 | CEFBS_HasSIMD128, // SHL_I16x8 |
| 8511 | CEFBS_HasSIMD128, // SHL_I16x8_S |
| 8512 | CEFBS_None, // SHL_I32 |
| 8513 | CEFBS_None, // SHL_I32_S |
| 8514 | CEFBS_HasSIMD128, // SHL_I32x4 |
| 8515 | CEFBS_HasSIMD128, // SHL_I32x4_S |
| 8516 | CEFBS_None, // SHL_I64 |
| 8517 | CEFBS_None, // SHL_I64_S |
| 8518 | CEFBS_HasSIMD128, // SHL_I64x2 |
| 8519 | CEFBS_HasSIMD128, // SHL_I64x2_S |
| 8520 | CEFBS_HasSIMD128, // SHL_I8x16 |
| 8521 | CEFBS_HasSIMD128, // SHL_I8x16_S |
| 8522 | CEFBS_HasSIMD128, // SHR_S_I16x8 |
| 8523 | CEFBS_HasSIMD128, // SHR_S_I16x8_S |
| 8524 | CEFBS_None, // SHR_S_I32 |
| 8525 | CEFBS_None, // SHR_S_I32_S |
| 8526 | CEFBS_HasSIMD128, // SHR_S_I32x4 |
| 8527 | CEFBS_HasSIMD128, // SHR_S_I32x4_S |
| 8528 | CEFBS_None, // SHR_S_I64 |
| 8529 | CEFBS_None, // SHR_S_I64_S |
| 8530 | CEFBS_HasSIMD128, // SHR_S_I64x2 |
| 8531 | CEFBS_HasSIMD128, // SHR_S_I64x2_S |
| 8532 | CEFBS_HasSIMD128, // SHR_S_I8x16 |
| 8533 | CEFBS_HasSIMD128, // SHR_S_I8x16_S |
| 8534 | CEFBS_HasSIMD128, // SHR_U_I16x8 |
| 8535 | CEFBS_HasSIMD128, // SHR_U_I16x8_S |
| 8536 | CEFBS_None, // SHR_U_I32 |
| 8537 | CEFBS_None, // SHR_U_I32_S |
| 8538 | CEFBS_HasSIMD128, // SHR_U_I32x4 |
| 8539 | CEFBS_HasSIMD128, // SHR_U_I32x4_S |
| 8540 | CEFBS_None, // SHR_U_I64 |
| 8541 | CEFBS_None, // SHR_U_I64_S |
| 8542 | CEFBS_HasSIMD128, // SHR_U_I64x2 |
| 8543 | CEFBS_HasSIMD128, // SHR_U_I64x2_S |
| 8544 | CEFBS_HasSIMD128, // SHR_U_I8x16 |
| 8545 | CEFBS_HasSIMD128, // SHR_U_I8x16_S |
| 8546 | CEFBS_HasSIMD128, // SHUFFLE |
| 8547 | CEFBS_HasSIMD128, // SHUFFLE_S |
| 8548 | CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMAX_F32x4 |
| 8549 | CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMAX_F32x4_S |
| 8550 | CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMAX_F64x2 |
| 8551 | CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMAX_F64x2_S |
| 8552 | CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMIN_F32x4 |
| 8553 | CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMIN_F32x4_S |
| 8554 | CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMIN_F64x2 |
| 8555 | CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMIN_F64x2_S |
| 8556 | CEFBS_HasFP16, // SPLAT_F16x8 |
| 8557 | CEFBS_HasFP16, // SPLAT_F16x8_S |
| 8558 | CEFBS_HasSIMD128, // SPLAT_F32x4 |
| 8559 | CEFBS_HasSIMD128, // SPLAT_F32x4_S |
| 8560 | CEFBS_HasSIMD128, // SPLAT_F64x2 |
| 8561 | CEFBS_HasSIMD128, // SPLAT_F64x2_S |
| 8562 | CEFBS_HasSIMD128, // SPLAT_I16x8 |
| 8563 | CEFBS_HasSIMD128, // SPLAT_I16x8_S |
| 8564 | CEFBS_HasSIMD128, // SPLAT_I32x4 |
| 8565 | CEFBS_HasSIMD128, // SPLAT_I32x4_S |
| 8566 | CEFBS_HasSIMD128, // SPLAT_I64x2 |
| 8567 | CEFBS_HasSIMD128, // SPLAT_I64x2_S |
| 8568 | CEFBS_HasSIMD128, // SPLAT_I8x16 |
| 8569 | CEFBS_HasSIMD128, // SPLAT_I8x16_S |
| 8570 | CEFBS_HasSIMD128_HasFP16, // SQRT_F16x8 |
| 8571 | CEFBS_HasSIMD128_HasFP16, // SQRT_F16x8_S |
| 8572 | CEFBS_None, // SQRT_F32 |
| 8573 | CEFBS_None, // SQRT_F32_S |
| 8574 | CEFBS_HasSIMD128, // SQRT_F32x4 |
| 8575 | CEFBS_HasSIMD128, // SQRT_F32x4_S |
| 8576 | CEFBS_None, // SQRT_F64 |
| 8577 | CEFBS_None, // SQRT_F64_S |
| 8578 | CEFBS_HasSIMD128, // SQRT_F64x2 |
| 8579 | CEFBS_HasSIMD128, // SQRT_F64x2_S |
| 8580 | CEFBS_None, // STORE16_I32_A32 |
| 8581 | CEFBS_None, // STORE16_I32_A32_S |
| 8582 | CEFBS_None, // STORE16_I32_A64 |
| 8583 | CEFBS_None, // STORE16_I32_A64_S |
| 8584 | CEFBS_None, // STORE16_I64_A32 |
| 8585 | CEFBS_None, // STORE16_I64_A32_S |
| 8586 | CEFBS_None, // STORE16_I64_A64 |
| 8587 | CEFBS_None, // STORE16_I64_A64_S |
| 8588 | CEFBS_None, // STORE32_I64_A32 |
| 8589 | CEFBS_None, // STORE32_I64_A32_S |
| 8590 | CEFBS_None, // STORE32_I64_A64 |
| 8591 | CEFBS_None, // STORE32_I64_A64_S |
| 8592 | CEFBS_None, // STORE8_I32_A32 |
| 8593 | CEFBS_None, // STORE8_I32_A32_S |
| 8594 | CEFBS_None, // STORE8_I32_A64 |
| 8595 | CEFBS_None, // STORE8_I32_A64_S |
| 8596 | CEFBS_None, // STORE8_I64_A32 |
| 8597 | CEFBS_None, // STORE8_I64_A32_S |
| 8598 | CEFBS_None, // STORE8_I64_A64 |
| 8599 | CEFBS_None, // STORE8_I64_A64_S |
| 8600 | CEFBS_HasFP16, // STORE_F16_F32_A32 |
| 8601 | CEFBS_HasFP16, // STORE_F16_F32_A32_S |
| 8602 | CEFBS_HasFP16, // STORE_F16_F32_A64 |
| 8603 | CEFBS_HasFP16, // STORE_F16_F32_A64_S |
| 8604 | CEFBS_None, // STORE_F32_A32 |
| 8605 | CEFBS_None, // STORE_F32_A32_S |
| 8606 | CEFBS_None, // STORE_F32_A64 |
| 8607 | CEFBS_None, // STORE_F32_A64_S |
| 8608 | CEFBS_None, // STORE_F64_A32 |
| 8609 | CEFBS_None, // STORE_F64_A32_S |
| 8610 | CEFBS_None, // STORE_F64_A64 |
| 8611 | CEFBS_None, // STORE_F64_A64_S |
| 8612 | CEFBS_None, // STORE_I32_A32 |
| 8613 | CEFBS_None, // STORE_I32_A32_S |
| 8614 | CEFBS_None, // STORE_I32_A64 |
| 8615 | CEFBS_None, // STORE_I32_A64_S |
| 8616 | CEFBS_None, // STORE_I64_A32 |
| 8617 | CEFBS_None, // STORE_I64_A32_S |
| 8618 | CEFBS_None, // STORE_I64_A64 |
| 8619 | CEFBS_None, // STORE_I64_A64_S |
| 8620 | CEFBS_HasSIMD128, // STORE_LANE_I16x8_A32 |
| 8621 | CEFBS_HasSIMD128, // STORE_LANE_I16x8_A32_S |
| 8622 | CEFBS_HasSIMD128, // STORE_LANE_I16x8_A64 |
| 8623 | CEFBS_HasSIMD128, // STORE_LANE_I16x8_A64_S |
| 8624 | CEFBS_HasSIMD128, // STORE_LANE_I32x4_A32 |
| 8625 | CEFBS_HasSIMD128, // STORE_LANE_I32x4_A32_S |
| 8626 | CEFBS_HasSIMD128, // STORE_LANE_I32x4_A64 |
| 8627 | CEFBS_HasSIMD128, // STORE_LANE_I32x4_A64_S |
| 8628 | CEFBS_HasSIMD128, // STORE_LANE_I64x2_A32 |
| 8629 | CEFBS_HasSIMD128, // STORE_LANE_I64x2_A32_S |
| 8630 | CEFBS_HasSIMD128, // STORE_LANE_I64x2_A64 |
| 8631 | CEFBS_HasSIMD128, // STORE_LANE_I64x2_A64_S |
| 8632 | CEFBS_HasSIMD128, // STORE_LANE_I8x16_A32 |
| 8633 | CEFBS_HasSIMD128, // STORE_LANE_I8x16_A32_S |
| 8634 | CEFBS_HasSIMD128, // STORE_LANE_I8x16_A64 |
| 8635 | CEFBS_HasSIMD128, // STORE_LANE_I8x16_A64_S |
| 8636 | CEFBS_HasSIMD128, // STORE_V128_A32 |
| 8637 | CEFBS_HasSIMD128, // STORE_V128_A32_S |
| 8638 | CEFBS_HasSIMD128, // STORE_V128_A64 |
| 8639 | CEFBS_HasSIMD128, // STORE_V128_A64_S |
| 8640 | CEFBS_HasSIMD128_HasFP16, // SUB_F16x8 |
| 8641 | CEFBS_HasSIMD128_HasFP16, // SUB_F16x8_S |
| 8642 | CEFBS_None, // SUB_F32 |
| 8643 | CEFBS_None, // SUB_F32_S |
| 8644 | CEFBS_HasSIMD128, // SUB_F32x4 |
| 8645 | CEFBS_HasSIMD128, // SUB_F32x4_S |
| 8646 | CEFBS_None, // SUB_F64 |
| 8647 | CEFBS_None, // SUB_F64_S |
| 8648 | CEFBS_HasSIMD128, // SUB_F64x2 |
| 8649 | CEFBS_HasSIMD128, // SUB_F64x2_S |
| 8650 | CEFBS_HasSIMD128, // SUB_I16x8 |
| 8651 | CEFBS_HasSIMD128, // SUB_I16x8_S |
| 8652 | CEFBS_None, // SUB_I32 |
| 8653 | CEFBS_None, // SUB_I32_S |
| 8654 | CEFBS_HasSIMD128, // SUB_I32x4 |
| 8655 | CEFBS_HasSIMD128, // SUB_I32x4_S |
| 8656 | CEFBS_None, // SUB_I64 |
| 8657 | CEFBS_None, // SUB_I64_S |
| 8658 | CEFBS_HasSIMD128, // SUB_I64x2 |
| 8659 | CEFBS_HasSIMD128, // SUB_I64x2_S |
| 8660 | CEFBS_HasSIMD128, // SUB_I8x16 |
| 8661 | CEFBS_HasSIMD128, // SUB_I8x16_S |
| 8662 | CEFBS_HasSIMD128, // SUB_SAT_S_I16x8 |
| 8663 | CEFBS_HasSIMD128, // SUB_SAT_S_I16x8_S |
| 8664 | CEFBS_HasSIMD128, // SUB_SAT_S_I8x16 |
| 8665 | CEFBS_HasSIMD128, // SUB_SAT_S_I8x16_S |
| 8666 | CEFBS_HasSIMD128, // SUB_SAT_U_I16x8 |
| 8667 | CEFBS_HasSIMD128, // SUB_SAT_U_I16x8_S |
| 8668 | CEFBS_HasSIMD128, // SUB_SAT_U_I8x16 |
| 8669 | CEFBS_HasSIMD128, // SUB_SAT_U_I8x16_S |
| 8670 | CEFBS_HasSIMD128, // SWIZZLE |
| 8671 | CEFBS_HasSIMD128, // SWIZZLE_S |
| 8672 | CEFBS_HasReferenceTypes, // TABLE_COPY |
| 8673 | CEFBS_HasReferenceTypes, // TABLE_COPY_S |
| 8674 | CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_FILL_EXNREF |
| 8675 | CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_FILL_EXNREF_S |
| 8676 | CEFBS_HasReferenceTypes, // TABLE_FILL_EXTERNREF |
| 8677 | CEFBS_HasReferenceTypes, // TABLE_FILL_EXTERNREF_S |
| 8678 | CEFBS_HasReferenceTypes, // TABLE_FILL_FUNCREF |
| 8679 | CEFBS_HasReferenceTypes, // TABLE_FILL_FUNCREF_S |
| 8680 | CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_GET_EXNREF |
| 8681 | CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_GET_EXNREF_S |
| 8682 | CEFBS_HasReferenceTypes, // TABLE_GET_EXTERNREF |
| 8683 | CEFBS_HasReferenceTypes, // TABLE_GET_EXTERNREF_S |
| 8684 | CEFBS_HasReferenceTypes, // TABLE_GET_FUNCREF |
| 8685 | CEFBS_HasReferenceTypes, // TABLE_GET_FUNCREF_S |
| 8686 | CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_GROW_EXNREF |
| 8687 | CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_GROW_EXNREF_S |
| 8688 | CEFBS_HasReferenceTypes, // TABLE_GROW_EXTERNREF |
| 8689 | CEFBS_HasReferenceTypes, // TABLE_GROW_EXTERNREF_S |
| 8690 | CEFBS_HasReferenceTypes, // TABLE_GROW_FUNCREF |
| 8691 | CEFBS_HasReferenceTypes, // TABLE_GROW_FUNCREF_S |
| 8692 | CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_SET_EXNREF |
| 8693 | CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_SET_EXNREF_S |
| 8694 | CEFBS_HasReferenceTypes, // TABLE_SET_EXTERNREF |
| 8695 | CEFBS_HasReferenceTypes, // TABLE_SET_EXTERNREF_S |
| 8696 | CEFBS_HasReferenceTypes, // TABLE_SET_FUNCREF |
| 8697 | CEFBS_HasReferenceTypes, // TABLE_SET_FUNCREF_S |
| 8698 | CEFBS_HasReferenceTypes, // TABLE_SIZE |
| 8699 | CEFBS_HasReferenceTypes, // TABLE_SIZE_S |
| 8700 | CEFBS_HasReferenceTypes_HasExceptionHandling, // TEE_EXNREF |
| 8701 | CEFBS_HasReferenceTypes_HasExceptionHandling, // TEE_EXNREF_S |
| 8702 | CEFBS_HasReferenceTypes, // TEE_EXTERNREF |
| 8703 | CEFBS_HasReferenceTypes, // TEE_EXTERNREF_S |
| 8704 | CEFBS_None, // TEE_F32 |
| 8705 | CEFBS_None, // TEE_F32_S |
| 8706 | CEFBS_None, // TEE_F64 |
| 8707 | CEFBS_None, // TEE_F64_S |
| 8708 | CEFBS_HasReferenceTypes, // TEE_FUNCREF |
| 8709 | CEFBS_HasReferenceTypes, // TEE_FUNCREF_S |
| 8710 | CEFBS_None, // TEE_I32 |
| 8711 | CEFBS_None, // TEE_I32_S |
| 8712 | CEFBS_None, // TEE_I64 |
| 8713 | CEFBS_None, // TEE_I64_S |
| 8714 | CEFBS_HasSIMD128, // TEE_V128 |
| 8715 | CEFBS_HasSIMD128, // TEE_V128_S |
| 8716 | CEFBS_HasExceptionHandling, // THROW |
| 8717 | CEFBS_HasExceptionHandling, // THROW_REF |
| 8718 | CEFBS_HasExceptionHandling, // THROW_REF_S |
| 8719 | CEFBS_HasExceptionHandling, // THROW_S |
| 8720 | CEFBS_HasSIMD128_HasFP16, // TRUNC_F16x8 |
| 8721 | CEFBS_HasSIMD128_HasFP16, // TRUNC_F16x8_S |
| 8722 | CEFBS_None, // TRUNC_F32 |
| 8723 | CEFBS_None, // TRUNC_F32_S |
| 8724 | CEFBS_HasSIMD128, // TRUNC_F32x4 |
| 8725 | CEFBS_HasSIMD128, // TRUNC_F32x4_S |
| 8726 | CEFBS_None, // TRUNC_F64 |
| 8727 | CEFBS_None, // TRUNC_F64_S |
| 8728 | CEFBS_HasSIMD128, // TRUNC_F64x2 |
| 8729 | CEFBS_HasSIMD128, // TRUNC_F64x2_S |
| 8730 | CEFBS_HasExceptionHandling, // TRY |
| 8731 | CEFBS_HasExceptionHandling, // TRY_S |
| 8732 | CEFBS_HasExceptionHandling, // TRY_TABLE |
| 8733 | CEFBS_HasExceptionHandling, // TRY_TABLE_S |
| 8734 | CEFBS_None, // UNREACHABLE |
| 8735 | CEFBS_None, // UNREACHABLE_S |
| 8736 | CEFBS_HasSIMD128, // XOR |
| 8737 | CEFBS_None, // XOR_I32 |
| 8738 | CEFBS_None, // XOR_I32_S |
| 8739 | CEFBS_None, // XOR_I64 |
| 8740 | CEFBS_None, // XOR_I64_S |
| 8741 | CEFBS_HasSIMD128, // XOR_S |
| 8742 | CEFBS_None, // anonymous_14864MEMORY_GROW_A32 |
| 8743 | CEFBS_None, // anonymous_14864MEMORY_GROW_A32_S |
| 8744 | CEFBS_None, // anonymous_14864MEMORY_SIZE_A32 |
| 8745 | CEFBS_None, // anonymous_14864MEMORY_SIZE_A32_S |
| 8746 | CEFBS_None, // anonymous_14865MEMORY_GROW_A64 |
| 8747 | CEFBS_None, // anonymous_14865MEMORY_GROW_A64_S |
| 8748 | CEFBS_None, // anonymous_14865MEMORY_SIZE_A64 |
| 8749 | CEFBS_None, // anonymous_14865MEMORY_SIZE_A64_S |
| 8750 | CEFBS_HasSIMD128, // convert_low_s_F64x2 |
| 8751 | CEFBS_HasSIMD128, // convert_low_s_F64x2_S |
| 8752 | CEFBS_HasSIMD128, // convert_low_u_F64x2 |
| 8753 | CEFBS_HasSIMD128, // convert_low_u_F64x2_S |
| 8754 | CEFBS_HasSIMD128_HasFP16, // demote_zero_F16x8 |
| 8755 | CEFBS_HasSIMD128_HasFP16, // demote_zero_F16x8_S |
| 8756 | CEFBS_HasSIMD128, // demote_zero_F32x4 |
| 8757 | CEFBS_HasSIMD128, // demote_zero_F32x4_S |
| 8758 | CEFBS_HasSIMD128, // extadd_pairwise_s_I16x8 |
| 8759 | CEFBS_HasSIMD128, // extadd_pairwise_s_I16x8_S |
| 8760 | CEFBS_HasSIMD128, // extadd_pairwise_s_I32x4 |
| 8761 | CEFBS_HasSIMD128, // extadd_pairwise_s_I32x4_S |
| 8762 | CEFBS_HasSIMD128, // extadd_pairwise_u_I16x8 |
| 8763 | CEFBS_HasSIMD128, // extadd_pairwise_u_I16x8_S |
| 8764 | CEFBS_HasSIMD128, // extadd_pairwise_u_I32x4 |
| 8765 | CEFBS_HasSIMD128, // extadd_pairwise_u_I32x4_S |
| 8766 | CEFBS_HasSIMD128, // extend_high_s_I16x8 |
| 8767 | CEFBS_HasSIMD128, // extend_high_s_I16x8_S |
| 8768 | CEFBS_HasSIMD128, // extend_high_s_I32x4 |
| 8769 | CEFBS_HasSIMD128, // extend_high_s_I32x4_S |
| 8770 | CEFBS_HasSIMD128, // extend_high_s_I64x2 |
| 8771 | CEFBS_HasSIMD128, // extend_high_s_I64x2_S |
| 8772 | CEFBS_HasSIMD128, // extend_high_u_I16x8 |
| 8773 | CEFBS_HasSIMD128, // extend_high_u_I16x8_S |
| 8774 | CEFBS_HasSIMD128, // extend_high_u_I32x4 |
| 8775 | CEFBS_HasSIMD128, // extend_high_u_I32x4_S |
| 8776 | CEFBS_HasSIMD128, // extend_high_u_I64x2 |
| 8777 | CEFBS_HasSIMD128, // extend_high_u_I64x2_S |
| 8778 | CEFBS_HasSIMD128, // extend_low_s_I16x8 |
| 8779 | CEFBS_HasSIMD128, // extend_low_s_I16x8_S |
| 8780 | CEFBS_HasSIMD128, // extend_low_s_I32x4 |
| 8781 | CEFBS_HasSIMD128, // extend_low_s_I32x4_S |
| 8782 | CEFBS_HasSIMD128, // extend_low_s_I64x2 |
| 8783 | CEFBS_HasSIMD128, // extend_low_s_I64x2_S |
| 8784 | CEFBS_HasSIMD128, // extend_low_u_I16x8 |
| 8785 | CEFBS_HasSIMD128, // extend_low_u_I16x8_S |
| 8786 | CEFBS_HasSIMD128, // extend_low_u_I32x4 |
| 8787 | CEFBS_HasSIMD128, // extend_low_u_I32x4_S |
| 8788 | CEFBS_HasSIMD128, // extend_low_u_I64x2 |
| 8789 | CEFBS_HasSIMD128, // extend_low_u_I64x2_S |
| 8790 | CEFBS_HasSIMD128_HasFP16, // fp_to_sint_I16x8 |
| 8791 | CEFBS_HasSIMD128_HasFP16, // fp_to_sint_I16x8_S |
| 8792 | CEFBS_HasSIMD128, // fp_to_sint_I32x4 |
| 8793 | CEFBS_HasSIMD128, // fp_to_sint_I32x4_S |
| 8794 | CEFBS_HasSIMD128_HasFP16, // fp_to_uint_I16x8 |
| 8795 | CEFBS_HasSIMD128_HasFP16, // fp_to_uint_I16x8_S |
| 8796 | CEFBS_HasSIMD128, // fp_to_uint_I32x4 |
| 8797 | CEFBS_HasSIMD128, // fp_to_uint_I32x4_S |
| 8798 | CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_signed_I32x4 |
| 8799 | CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_signed_I32x4_S |
| 8800 | CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_signed_zero_I32x4 |
| 8801 | CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_signed_zero_I32x4_S |
| 8802 | CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_unsigned_I32x4 |
| 8803 | CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_unsigned_I32x4_S |
| 8804 | CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_unsigned_zero_I32x4 |
| 8805 | CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_unsigned_zero_I32x4_S |
| 8806 | CEFBS_HasSIMD128_HasFP16, // promote_low_F32x4 |
| 8807 | CEFBS_HasSIMD128_HasFP16, // promote_low_F32x4_S |
| 8808 | CEFBS_HasSIMD128, // promote_low_F64x2 |
| 8809 | CEFBS_HasSIMD128, // promote_low_F64x2_S |
| 8810 | CEFBS_HasSIMD128_HasFP16, // sint_to_fp_F16x8 |
| 8811 | CEFBS_HasSIMD128_HasFP16, // sint_to_fp_F16x8_S |
| 8812 | CEFBS_HasSIMD128, // sint_to_fp_F32x4 |
| 8813 | CEFBS_HasSIMD128, // sint_to_fp_F32x4_S |
| 8814 | CEFBS_HasSIMD128, // trunc_sat_zero_s_I32x4 |
| 8815 | CEFBS_HasSIMD128, // trunc_sat_zero_s_I32x4_S |
| 8816 | CEFBS_HasSIMD128, // trunc_sat_zero_u_I32x4 |
| 8817 | CEFBS_HasSIMD128, // trunc_sat_zero_u_I32x4_S |
| 8818 | CEFBS_HasSIMD128_HasFP16, // uint_to_fp_F16x8 |
| 8819 | CEFBS_HasSIMD128_HasFP16, // uint_to_fp_F16x8_S |
| 8820 | CEFBS_HasSIMD128, // uint_to_fp_F32x4 |
| 8821 | CEFBS_HasSIMD128, // uint_to_fp_F32x4_S |
| 8822 | }; |
| 8823 | |
| 8824 | assert(Opcode < 1983); |
| 8825 | return FeatureBitsets[RequiredFeaturesRefs[Opcode]]; |
| 8826 | } |
| 8827 | |
| 8828 | |
| 8829 | } // namespace llvm::WebAssembly_MC |
| 8830 | |
| 8831 | #endif // GET_COMPUTE_FEATURES |
| 8832 | |
| 8833 | #ifdef GET_AVAILABLE_OPCODE_CHECKER |
| 8834 | #undef GET_AVAILABLE_OPCODE_CHECKER |
| 8835 | |
| 8836 | namespace llvm::WebAssembly_MC { |
| 8837 | |
| 8838 | bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) { |
| 8839 | FeatureBitset AvailableFeatures = computeAvailableFeatures(Features); |
| 8840 | FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode); |
| 8841 | FeatureBitset MissingFeatures = |
| 8842 | (AvailableFeatures & RequiredFeatures) ^ |
| 8843 | RequiredFeatures; |
| 8844 | return !MissingFeatures.any(); |
| 8845 | } |
| 8846 | |
| 8847 | } // namespace llvm::WebAssembly_MC |
| 8848 | |
| 8849 | #endif // GET_AVAILABLE_OPCODE_CHECKER |
| 8850 | |
| 8851 | #ifdef ENABLE_INSTR_PREDICATE_VERIFIER |
| 8852 | #undef ENABLE_INSTR_PREDICATE_VERIFIER |
| 8853 | |
| 8854 | #include <sstream> |
| 8855 | |
| 8856 | namespace llvm::WebAssembly_MC { |
| 8857 | |
| 8858 | #ifndef NDEBUG |
| 8859 | static const char *SubtargetFeatureNames[] = { |
| 8860 | "Feature_HasAtomics", |
| 8861 | "Feature_HasBulkMemory", |
| 8862 | "Feature_HasBulkMemoryOpt", |
| 8863 | "Feature_HasCallIndirectOverlong", |
| 8864 | "Feature_HasExceptionHandling", |
| 8865 | "Feature_HasExtendedConst", |
| 8866 | "Feature_HasFP16", |
| 8867 | "Feature_HasGC", |
| 8868 | "Feature_HasMultiMemory", |
| 8869 | "Feature_HasMultivalue", |
| 8870 | "Feature_HasMutableGlobals", |
| 8871 | "Feature_HasNontrappingFPToInt", |
| 8872 | "Feature_HasReferenceTypes", |
| 8873 | "Feature_HasRelaxedAtomics", |
| 8874 | "Feature_HasRelaxedSIMD", |
| 8875 | "Feature_HasSIMD128", |
| 8876 | "Feature_HasSignExt", |
| 8877 | "Feature_HasTailCall", |
| 8878 | "Feature_HasWideArithmetic", |
| 8879 | "Feature_NotHasNontrappingFPToInt", |
| 8880 | nullptr |
| 8881 | }; |
| 8882 | |
| 8883 | #endif // NDEBUG |
| 8884 | |
| 8885 | void verifyInstructionPredicates( |
| 8886 | unsigned Opcode, const FeatureBitset &Features) { |
| 8887 | #ifndef NDEBUG |
| 8888 | FeatureBitset AvailableFeatures = computeAvailableFeatures(Features); |
| 8889 | FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode); |
| 8890 | FeatureBitset MissingFeatures = |
| 8891 | (AvailableFeatures & RequiredFeatures) ^ |
| 8892 | RequiredFeatures; |
| 8893 | if (MissingFeatures.any()) { |
| 8894 | std::ostringstream Msg; |
| 8895 | Msg << "Attempting to emit "<< &WebAssemblyInstrNameData[WebAssemblyInstrNameIndices[Opcode]] |
| 8896 | << " instruction but the "; |
| 8897 | for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i) |
| 8898 | if (MissingFeatures.test(i)) |
| 8899 | Msg << SubtargetFeatureNames[i] << " "; |
| 8900 | Msg << "predicate(s) are not met"; |
| 8901 | report_fatal_error(Msg.str().c_str()); |
| 8902 | } |
| 8903 | #endif // NDEBUG |
| 8904 | } |
| 8905 | |
| 8906 | } // namespace llvm::WebAssembly_MC |
| 8907 | |
| 8908 | #endif // ENABLE_INSTR_PREDICATE_VERIFIER |
| 8909 | |
| 8910 | #ifdef GET_INSTRMAP_INFO |
| 8911 | #undef GET_INSTRMAP_INFO |
| 8912 | |
| 8913 | namespace llvm::WebAssembly { |
| 8914 | |
| 8915 | enum IsWasm64 { |
| 8916 | IsWasm64_1 |
| 8917 | }; |
| 8918 | |
| 8919 | enum StackBased { |
| 8920 | StackBased_0, |
| 8921 | StackBased_1 |
| 8922 | }; |
| 8923 | |
| 8924 | // getRegisterOpcode |
| 8925 | LLVM_READONLY |
| 8926 | int32_t getRegisterOpcode(uint32_t Opcode) { |
| 8927 | using namespace WebAssembly; |
| 8928 | static constexpr uint32_t Table[][2] = { |
| 8929 | { CALL_PARAMS_S, CALL_PARAMS }, |
| 8930 | { CALL_RESULTS_S, CALL_RESULTS }, |
| 8931 | { CATCHRET_S, CATCHRET }, |
| 8932 | { CLEANUPRET_S, CLEANUPRET }, |
| 8933 | { COMPILER_FENCE_S, COMPILER_FENCE }, |
| 8934 | { RET_CALL_PARAMS_S, RET_CALL_PARAMS }, |
| 8935 | { RET_CALL_RESULTS_S, RET_CALL_RESULTS }, |
| 8936 | { ABS_F16x8_S, ABS_F16x8 }, |
| 8937 | { ABS_F32_S, ABS_F32 }, |
| 8938 | { ABS_F32x4_S, ABS_F32x4 }, |
| 8939 | { ABS_F64_S, ABS_F64 }, |
| 8940 | { ABS_F64x2_S, ABS_F64x2 }, |
| 8941 | { ABS_I16x8_S, ABS_I16x8 }, |
| 8942 | { ABS_I32x4_S, ABS_I32x4 }, |
| 8943 | { ABS_I64x2_S, ABS_I64x2 }, |
| 8944 | { ABS_I8x16_S, ABS_I8x16 }, |
| 8945 | { ADD_F16x8_S, ADD_F16x8 }, |
| 8946 | { ADD_F32_S, ADD_F32 }, |
| 8947 | { ADD_F32x4_S, ADD_F32x4 }, |
| 8948 | { ADD_F64_S, ADD_F64 }, |
| 8949 | { ADD_F64x2_S, ADD_F64x2 }, |
| 8950 | { ADD_I16x8_S, ADD_I16x8 }, |
| 8951 | { ADD_I32_S, ADD_I32 }, |
| 8952 | { ADD_I32x4_S, ADD_I32x4 }, |
| 8953 | { ADD_I64_S, ADD_I64 }, |
| 8954 | { ADD_I64x2_S, ADD_I64x2 }, |
| 8955 | { ADD_I8x16_S, ADD_I8x16 }, |
| 8956 | { ADD_SAT_S_I16x8_S, ADD_SAT_S_I16x8 }, |
| 8957 | { ADD_SAT_S_I8x16_S, ADD_SAT_S_I8x16 }, |
| 8958 | { ADD_SAT_U_I16x8_S, ADD_SAT_U_I16x8 }, |
| 8959 | { ADD_SAT_U_I8x16_S, ADD_SAT_U_I8x16 }, |
| 8960 | { ADJCALLSTACKDOWN_S, ADJCALLSTACKDOWN }, |
| 8961 | { ADJCALLSTACKUP_S, ADJCALLSTACKUP }, |
| 8962 | { ALLTRUE_I16x8_S, ALLTRUE_I16x8 }, |
| 8963 | { ALLTRUE_I32x4_S, ALLTRUE_I32x4 }, |
| 8964 | { ALLTRUE_I64x2_S, ALLTRUE_I64x2 }, |
| 8965 | { ALLTRUE_I8x16_S, ALLTRUE_I8x16 }, |
| 8966 | { ANDNOT_S, ANDNOT }, |
| 8967 | { AND_I32_S, AND_I32 }, |
| 8968 | { AND_I64_S, AND_I64 }, |
| 8969 | { AND_S, AND }, |
| 8970 | { ANYTRUE_S, ANYTRUE }, |
| 8971 | { ARGUMENT_exnref_S, ARGUMENT_exnref }, |
| 8972 | { ARGUMENT_externref_S, ARGUMENT_externref }, |
| 8973 | { ARGUMENT_f32_S, ARGUMENT_f32 }, |
| 8974 | { ARGUMENT_f64_S, ARGUMENT_f64 }, |
| 8975 | { ARGUMENT_funcref_S, ARGUMENT_funcref }, |
| 8976 | { ARGUMENT_i32_S, ARGUMENT_i32 }, |
| 8977 | { ARGUMENT_i64_S, ARGUMENT_i64 }, |
| 8978 | { ARGUMENT_v16i8_S, ARGUMENT_v16i8 }, |
| 8979 | { ARGUMENT_v2f64_S, ARGUMENT_v2f64 }, |
| 8980 | { ARGUMENT_v2i64_S, ARGUMENT_v2i64 }, |
| 8981 | { ARGUMENT_v4f32_S, ARGUMENT_v4f32 }, |
| 8982 | { ARGUMENT_v4i32_S, ARGUMENT_v4i32 }, |
| 8983 | { ARGUMENT_v8f16_S, ARGUMENT_v8f16 }, |
| 8984 | { ARGUMENT_v8i16_S, ARGUMENT_v8i16 }, |
| 8985 | { ATOMIC_FENCE_S, ATOMIC_FENCE }, |
| 8986 | { ATOMIC_LOAD16_U_I32_A32_S, ATOMIC_LOAD16_U_I32_A32 }, |
| 8987 | { ATOMIC_LOAD16_U_I32_A64_S, ATOMIC_LOAD16_U_I32_A64 }, |
| 8988 | { ATOMIC_LOAD16_U_I64_A32_S, ATOMIC_LOAD16_U_I64_A32 }, |
| 8989 | { ATOMIC_LOAD16_U_I64_A64_S, ATOMIC_LOAD16_U_I64_A64 }, |
| 8990 | { ATOMIC_LOAD32_U_I64_A32_S, ATOMIC_LOAD32_U_I64_A32 }, |
| 8991 | { ATOMIC_LOAD32_U_I64_A64_S, ATOMIC_LOAD32_U_I64_A64 }, |
| 8992 | { ATOMIC_LOAD8_U_I32_A32_S, ATOMIC_LOAD8_U_I32_A32 }, |
| 8993 | { ATOMIC_LOAD8_U_I32_A64_S, ATOMIC_LOAD8_U_I32_A64 }, |
| 8994 | { ATOMIC_LOAD8_U_I64_A32_S, ATOMIC_LOAD8_U_I64_A32 }, |
| 8995 | { ATOMIC_LOAD8_U_I64_A64_S, ATOMIC_LOAD8_U_I64_A64 }, |
| 8996 | { ATOMIC_LOAD_I32_A32_S, ATOMIC_LOAD_I32_A32 }, |
| 8997 | { ATOMIC_LOAD_I32_A64_S, ATOMIC_LOAD_I32_A64 }, |
| 8998 | { ATOMIC_LOAD_I64_A32_S, ATOMIC_LOAD_I64_A32 }, |
| 8999 | { ATOMIC_LOAD_I64_A64_S, ATOMIC_LOAD_I64_A64 }, |
| 9000 | { ATOMIC_RMW16_U_ADD_I32_A32_S, ATOMIC_RMW16_U_ADD_I32_A32 }, |
| 9001 | { ATOMIC_RMW16_U_ADD_I32_A64_S, ATOMIC_RMW16_U_ADD_I32_A64 }, |
| 9002 | { ATOMIC_RMW16_U_ADD_I64_A32_S, ATOMIC_RMW16_U_ADD_I64_A32 }, |
| 9003 | { ATOMIC_RMW16_U_ADD_I64_A64_S, ATOMIC_RMW16_U_ADD_I64_A64 }, |
| 9004 | { ATOMIC_RMW16_U_AND_I32_A32_S, ATOMIC_RMW16_U_AND_I32_A32 }, |
| 9005 | { ATOMIC_RMW16_U_AND_I32_A64_S, ATOMIC_RMW16_U_AND_I32_A64 }, |
| 9006 | { ATOMIC_RMW16_U_AND_I64_A32_S, ATOMIC_RMW16_U_AND_I64_A32 }, |
| 9007 | { ATOMIC_RMW16_U_AND_I64_A64_S, ATOMIC_RMW16_U_AND_I64_A64 }, |
| 9008 | { ATOMIC_RMW16_U_CMPXCHG_I32_A32_S, ATOMIC_RMW16_U_CMPXCHG_I32_A32 }, |
| 9009 | { ATOMIC_RMW16_U_CMPXCHG_I32_A64_S, ATOMIC_RMW16_U_CMPXCHG_I32_A64 }, |
| 9010 | { ATOMIC_RMW16_U_CMPXCHG_I64_A32_S, ATOMIC_RMW16_U_CMPXCHG_I64_A32 }, |
| 9011 | { ATOMIC_RMW16_U_CMPXCHG_I64_A64_S, ATOMIC_RMW16_U_CMPXCHG_I64_A64 }, |
| 9012 | { ATOMIC_RMW16_U_OR_I32_A32_S, ATOMIC_RMW16_U_OR_I32_A32 }, |
| 9013 | { ATOMIC_RMW16_U_OR_I32_A64_S, ATOMIC_RMW16_U_OR_I32_A64 }, |
| 9014 | { ATOMIC_RMW16_U_OR_I64_A32_S, ATOMIC_RMW16_U_OR_I64_A32 }, |
| 9015 | { ATOMIC_RMW16_U_OR_I64_A64_S, ATOMIC_RMW16_U_OR_I64_A64 }, |
| 9016 | { ATOMIC_RMW16_U_SUB_I32_A32_S, ATOMIC_RMW16_U_SUB_I32_A32 }, |
| 9017 | { ATOMIC_RMW16_U_SUB_I32_A64_S, ATOMIC_RMW16_U_SUB_I32_A64 }, |
| 9018 | { ATOMIC_RMW16_U_SUB_I64_A32_S, ATOMIC_RMW16_U_SUB_I64_A32 }, |
| 9019 | { ATOMIC_RMW16_U_SUB_I64_A64_S, ATOMIC_RMW16_U_SUB_I64_A64 }, |
| 9020 | { ATOMIC_RMW16_U_XCHG_I32_A32_S, ATOMIC_RMW16_U_XCHG_I32_A32 }, |
| 9021 | { ATOMIC_RMW16_U_XCHG_I32_A64_S, ATOMIC_RMW16_U_XCHG_I32_A64 }, |
| 9022 | { ATOMIC_RMW16_U_XCHG_I64_A32_S, ATOMIC_RMW16_U_XCHG_I64_A32 }, |
| 9023 | { ATOMIC_RMW16_U_XCHG_I64_A64_S, ATOMIC_RMW16_U_XCHG_I64_A64 }, |
| 9024 | { ATOMIC_RMW16_U_XOR_I32_A32_S, ATOMIC_RMW16_U_XOR_I32_A32 }, |
| 9025 | { ATOMIC_RMW16_U_XOR_I32_A64_S, ATOMIC_RMW16_U_XOR_I32_A64 }, |
| 9026 | { ATOMIC_RMW16_U_XOR_I64_A32_S, ATOMIC_RMW16_U_XOR_I64_A32 }, |
| 9027 | { ATOMIC_RMW16_U_XOR_I64_A64_S, ATOMIC_RMW16_U_XOR_I64_A64 }, |
| 9028 | { ATOMIC_RMW32_U_ADD_I64_A32_S, ATOMIC_RMW32_U_ADD_I64_A32 }, |
| 9029 | { ATOMIC_RMW32_U_ADD_I64_A64_S, ATOMIC_RMW32_U_ADD_I64_A64 }, |
| 9030 | { ATOMIC_RMW32_U_AND_I64_A32_S, ATOMIC_RMW32_U_AND_I64_A32 }, |
| 9031 | { ATOMIC_RMW32_U_AND_I64_A64_S, ATOMIC_RMW32_U_AND_I64_A64 }, |
| 9032 | { ATOMIC_RMW32_U_CMPXCHG_I64_A32_S, ATOMIC_RMW32_U_CMPXCHG_I64_A32 }, |
| 9033 | { ATOMIC_RMW32_U_CMPXCHG_I64_A64_S, ATOMIC_RMW32_U_CMPXCHG_I64_A64 }, |
| 9034 | { ATOMIC_RMW32_U_OR_I64_A32_S, ATOMIC_RMW32_U_OR_I64_A32 }, |
| 9035 | { ATOMIC_RMW32_U_OR_I64_A64_S, ATOMIC_RMW32_U_OR_I64_A64 }, |
| 9036 | { ATOMIC_RMW32_U_SUB_I64_A32_S, ATOMIC_RMW32_U_SUB_I64_A32 }, |
| 9037 | { ATOMIC_RMW32_U_SUB_I64_A64_S, ATOMIC_RMW32_U_SUB_I64_A64 }, |
| 9038 | { ATOMIC_RMW32_U_XCHG_I64_A32_S, ATOMIC_RMW32_U_XCHG_I64_A32 }, |
| 9039 | { ATOMIC_RMW32_U_XCHG_I64_A64_S, ATOMIC_RMW32_U_XCHG_I64_A64 }, |
| 9040 | { ATOMIC_RMW32_U_XOR_I64_A32_S, ATOMIC_RMW32_U_XOR_I64_A32 }, |
| 9041 | { ATOMIC_RMW32_U_XOR_I64_A64_S, ATOMIC_RMW32_U_XOR_I64_A64 }, |
| 9042 | { ATOMIC_RMW8_U_ADD_I32_A32_S, ATOMIC_RMW8_U_ADD_I32_A32 }, |
| 9043 | { ATOMIC_RMW8_U_ADD_I32_A64_S, ATOMIC_RMW8_U_ADD_I32_A64 }, |
| 9044 | { ATOMIC_RMW8_U_ADD_I64_A32_S, ATOMIC_RMW8_U_ADD_I64_A32 }, |
| 9045 | { ATOMIC_RMW8_U_ADD_I64_A64_S, ATOMIC_RMW8_U_ADD_I64_A64 }, |
| 9046 | { ATOMIC_RMW8_U_AND_I32_A32_S, ATOMIC_RMW8_U_AND_I32_A32 }, |
| 9047 | { ATOMIC_RMW8_U_AND_I32_A64_S, ATOMIC_RMW8_U_AND_I32_A64 }, |
| 9048 | { ATOMIC_RMW8_U_AND_I64_A32_S, ATOMIC_RMW8_U_AND_I64_A32 }, |
| 9049 | { ATOMIC_RMW8_U_AND_I64_A64_S, ATOMIC_RMW8_U_AND_I64_A64 }, |
| 9050 | { ATOMIC_RMW8_U_CMPXCHG_I32_A32_S, ATOMIC_RMW8_U_CMPXCHG_I32_A32 }, |
| 9051 | { ATOMIC_RMW8_U_CMPXCHG_I32_A64_S, ATOMIC_RMW8_U_CMPXCHG_I32_A64 }, |
| 9052 | { ATOMIC_RMW8_U_CMPXCHG_I64_A32_S, ATOMIC_RMW8_U_CMPXCHG_I64_A32 }, |
| 9053 | { ATOMIC_RMW8_U_CMPXCHG_I64_A64_S, ATOMIC_RMW8_U_CMPXCHG_I64_A64 }, |
| 9054 | { ATOMIC_RMW8_U_OR_I32_A32_S, ATOMIC_RMW8_U_OR_I32_A32 }, |
| 9055 | { ATOMIC_RMW8_U_OR_I32_A64_S, ATOMIC_RMW8_U_OR_I32_A64 }, |
| 9056 | { ATOMIC_RMW8_U_OR_I64_A32_S, ATOMIC_RMW8_U_OR_I64_A32 }, |
| 9057 | { ATOMIC_RMW8_U_OR_I64_A64_S, ATOMIC_RMW8_U_OR_I64_A64 }, |
| 9058 | { ATOMIC_RMW8_U_SUB_I32_A32_S, ATOMIC_RMW8_U_SUB_I32_A32 }, |
| 9059 | { ATOMIC_RMW8_U_SUB_I32_A64_S, ATOMIC_RMW8_U_SUB_I32_A64 }, |
| 9060 | { ATOMIC_RMW8_U_SUB_I64_A32_S, ATOMIC_RMW8_U_SUB_I64_A32 }, |
| 9061 | { ATOMIC_RMW8_U_SUB_I64_A64_S, ATOMIC_RMW8_U_SUB_I64_A64 }, |
| 9062 | { ATOMIC_RMW8_U_XCHG_I32_A32_S, ATOMIC_RMW8_U_XCHG_I32_A32 }, |
| 9063 | { ATOMIC_RMW8_U_XCHG_I32_A64_S, ATOMIC_RMW8_U_XCHG_I32_A64 }, |
| 9064 | { ATOMIC_RMW8_U_XCHG_I64_A32_S, ATOMIC_RMW8_U_XCHG_I64_A32 }, |
| 9065 | { ATOMIC_RMW8_U_XCHG_I64_A64_S, ATOMIC_RMW8_U_XCHG_I64_A64 }, |
| 9066 | { ATOMIC_RMW8_U_XOR_I32_A32_S, ATOMIC_RMW8_U_XOR_I32_A32 }, |
| 9067 | { ATOMIC_RMW8_U_XOR_I32_A64_S, ATOMIC_RMW8_U_XOR_I32_A64 }, |
| 9068 | { ATOMIC_RMW8_U_XOR_I64_A32_S, ATOMIC_RMW8_U_XOR_I64_A32 }, |
| 9069 | { ATOMIC_RMW8_U_XOR_I64_A64_S, ATOMIC_RMW8_U_XOR_I64_A64 }, |
| 9070 | { ATOMIC_RMW_ADD_I32_A32_S, ATOMIC_RMW_ADD_I32_A32 }, |
| 9071 | { ATOMIC_RMW_ADD_I32_A64_S, ATOMIC_RMW_ADD_I32_A64 }, |
| 9072 | { ATOMIC_RMW_ADD_I64_A32_S, ATOMIC_RMW_ADD_I64_A32 }, |
| 9073 | { ATOMIC_RMW_ADD_I64_A64_S, ATOMIC_RMW_ADD_I64_A64 }, |
| 9074 | { ATOMIC_RMW_AND_I32_A32_S, ATOMIC_RMW_AND_I32_A32 }, |
| 9075 | { ATOMIC_RMW_AND_I32_A64_S, ATOMIC_RMW_AND_I32_A64 }, |
| 9076 | { ATOMIC_RMW_AND_I64_A32_S, ATOMIC_RMW_AND_I64_A32 }, |
| 9077 | { ATOMIC_RMW_AND_I64_A64_S, ATOMIC_RMW_AND_I64_A64 }, |
| 9078 | { ATOMIC_RMW_CMPXCHG_I32_A32_S, ATOMIC_RMW_CMPXCHG_I32_A32 }, |
| 9079 | { ATOMIC_RMW_CMPXCHG_I32_A64_S, ATOMIC_RMW_CMPXCHG_I32_A64 }, |
| 9080 | { ATOMIC_RMW_CMPXCHG_I64_A32_S, ATOMIC_RMW_CMPXCHG_I64_A32 }, |
| 9081 | { ATOMIC_RMW_CMPXCHG_I64_A64_S, ATOMIC_RMW_CMPXCHG_I64_A64 }, |
| 9082 | { ATOMIC_RMW_OR_I32_A32_S, ATOMIC_RMW_OR_I32_A32 }, |
| 9083 | { ATOMIC_RMW_OR_I32_A64_S, ATOMIC_RMW_OR_I32_A64 }, |
| 9084 | { ATOMIC_RMW_OR_I64_A32_S, ATOMIC_RMW_OR_I64_A32 }, |
| 9085 | { ATOMIC_RMW_OR_I64_A64_S, ATOMIC_RMW_OR_I64_A64 }, |
| 9086 | { ATOMIC_RMW_SUB_I32_A32_S, ATOMIC_RMW_SUB_I32_A32 }, |
| 9087 | { ATOMIC_RMW_SUB_I32_A64_S, ATOMIC_RMW_SUB_I32_A64 }, |
| 9088 | { ATOMIC_RMW_SUB_I64_A32_S, ATOMIC_RMW_SUB_I64_A32 }, |
| 9089 | { ATOMIC_RMW_SUB_I64_A64_S, ATOMIC_RMW_SUB_I64_A64 }, |
| 9090 | { ATOMIC_RMW_XCHG_I32_A32_S, ATOMIC_RMW_XCHG_I32_A32 }, |
| 9091 | { ATOMIC_RMW_XCHG_I32_A64_S, ATOMIC_RMW_XCHG_I32_A64 }, |
| 9092 | { ATOMIC_RMW_XCHG_I64_A32_S, ATOMIC_RMW_XCHG_I64_A32 }, |
| 9093 | { ATOMIC_RMW_XCHG_I64_A64_S, ATOMIC_RMW_XCHG_I64_A64 }, |
| 9094 | { ATOMIC_RMW_XOR_I32_A32_S, ATOMIC_RMW_XOR_I32_A32 }, |
| 9095 | { ATOMIC_RMW_XOR_I32_A64_S, ATOMIC_RMW_XOR_I32_A64 }, |
| 9096 | { ATOMIC_RMW_XOR_I64_A32_S, ATOMIC_RMW_XOR_I64_A32 }, |
| 9097 | { ATOMIC_RMW_XOR_I64_A64_S, ATOMIC_RMW_XOR_I64_A64 }, |
| 9098 | { ATOMIC_STORE16_I32_A32_S, ATOMIC_STORE16_I32_A32 }, |
| 9099 | { ATOMIC_STORE16_I32_A64_S, ATOMIC_STORE16_I32_A64 }, |
| 9100 | { ATOMIC_STORE16_I64_A32_S, ATOMIC_STORE16_I64_A32 }, |
| 9101 | { ATOMIC_STORE16_I64_A64_S, ATOMIC_STORE16_I64_A64 }, |
| 9102 | { ATOMIC_STORE32_I64_A32_S, ATOMIC_STORE32_I64_A32 }, |
| 9103 | { ATOMIC_STORE32_I64_A64_S, ATOMIC_STORE32_I64_A64 }, |
| 9104 | { ATOMIC_STORE8_I32_A32_S, ATOMIC_STORE8_I32_A32 }, |
| 9105 | { ATOMIC_STORE8_I32_A64_S, ATOMIC_STORE8_I32_A64 }, |
| 9106 | { ATOMIC_STORE8_I64_A32_S, ATOMIC_STORE8_I64_A32 }, |
| 9107 | { ATOMIC_STORE8_I64_A64_S, ATOMIC_STORE8_I64_A64 }, |
| 9108 | { ATOMIC_STORE_I32_A32_S, ATOMIC_STORE_I32_A32 }, |
| 9109 | { ATOMIC_STORE_I32_A64_S, ATOMIC_STORE_I32_A64 }, |
| 9110 | { ATOMIC_STORE_I64_A32_S, ATOMIC_STORE_I64_A32 }, |
| 9111 | { ATOMIC_STORE_I64_A64_S, ATOMIC_STORE_I64_A64 }, |
| 9112 | { AVGR_U_I16x8_S, AVGR_U_I16x8 }, |
| 9113 | { AVGR_U_I8x16_S, AVGR_U_I8x16 }, |
| 9114 | { BITMASK_I16x8_S, BITMASK_I16x8 }, |
| 9115 | { BITMASK_I32x4_S, BITMASK_I32x4 }, |
| 9116 | { BITMASK_I64x2_S, BITMASK_I64x2 }, |
| 9117 | { BITMASK_I8x16_S, BITMASK_I8x16 }, |
| 9118 | { BITSELECT_S, BITSELECT }, |
| 9119 | { BLOCK_S, BLOCK }, |
| 9120 | { BR_IF_S, BR_IF }, |
| 9121 | { BR_S, BR }, |
| 9122 | { BR_TABLE_I32_S, BR_TABLE_I32 }, |
| 9123 | { BR_TABLE_I64_S, BR_TABLE_I64 }, |
| 9124 | { BR_UNLESS_S, BR_UNLESS }, |
| 9125 | { CALL_INDIRECT_S, CALL_INDIRECT }, |
| 9126 | { CALL_REF_S, CALL_REF }, |
| 9127 | { CALL_S, CALL }, |
| 9128 | { CATCH_ALL_LEGACY_S, CATCH_ALL_LEGACY }, |
| 9129 | { CATCH_ALL_REF_S, CATCH_ALL_REF }, |
| 9130 | { CATCH_ALL_S, CATCH_ALL }, |
| 9131 | { CATCH_LEGACY_S, CATCH_LEGACY }, |
| 9132 | { CATCH_REF_S, CATCH_REF }, |
| 9133 | { CATCH_S, CATCH }, |
| 9134 | { CEIL_F16x8_S, CEIL_F16x8 }, |
| 9135 | { CEIL_F32_S, CEIL_F32 }, |
| 9136 | { CEIL_F32x4_S, CEIL_F32x4 }, |
| 9137 | { CEIL_F64_S, CEIL_F64 }, |
| 9138 | { CEIL_F64x2_S, CEIL_F64x2 }, |
| 9139 | { CLZ_I32_S, CLZ_I32 }, |
| 9140 | { CLZ_I64_S, CLZ_I64 }, |
| 9141 | { CONST_F32_S, CONST_F32 }, |
| 9142 | { CONST_F64_S, CONST_F64 }, |
| 9143 | { CONST_I32_S, CONST_I32 }, |
| 9144 | { CONST_I64_S, CONST_I64 }, |
| 9145 | { CONST_V128_F32x4_S, CONST_V128_F32x4 }, |
| 9146 | { CONST_V128_F64x2_S, CONST_V128_F64x2 }, |
| 9147 | { CONST_V128_I16x8_S, CONST_V128_I16x8 }, |
| 9148 | { CONST_V128_I32x4_S, CONST_V128_I32x4 }, |
| 9149 | { CONST_V128_I64x2_S, CONST_V128_I64x2 }, |
| 9150 | { CONST_V128_I8x16_S, CONST_V128_I8x16 }, |
| 9151 | { COPYSIGN_F32_S, COPYSIGN_F32 }, |
| 9152 | { COPYSIGN_F64_S, COPYSIGN_F64 }, |
| 9153 | { COPY_EXNREF_S, COPY_EXNREF }, |
| 9154 | { COPY_EXTERNREF_S, COPY_EXTERNREF }, |
| 9155 | { COPY_F32_S, COPY_F32 }, |
| 9156 | { COPY_F64_S, COPY_F64 }, |
| 9157 | { COPY_FUNCREF_S, COPY_FUNCREF }, |
| 9158 | { COPY_I32_S, COPY_I32 }, |
| 9159 | { COPY_I64_S, COPY_I64 }, |
| 9160 | { COPY_V128_S, COPY_V128 }, |
| 9161 | { CTZ_I32_S, CTZ_I32 }, |
| 9162 | { CTZ_I64_S, CTZ_I64 }, |
| 9163 | { DATA_DROP_S, DATA_DROP }, |
| 9164 | { DEBUG_UNREACHABLE_S, DEBUG_UNREACHABLE }, |
| 9165 | { DELEGATE_S, DELEGATE }, |
| 9166 | { DIV_F16x8_S, DIV_F16x8 }, |
| 9167 | { DIV_F32_S, DIV_F32 }, |
| 9168 | { DIV_F32x4_S, DIV_F32x4 }, |
| 9169 | { DIV_F64_S, DIV_F64 }, |
| 9170 | { DIV_F64x2_S, DIV_F64x2 }, |
| 9171 | { DIV_S_I32_S, DIV_S_I32 }, |
| 9172 | { DIV_S_I64_S, DIV_S_I64 }, |
| 9173 | { DIV_U_I32_S, DIV_U_I32 }, |
| 9174 | { DIV_U_I64_S, DIV_U_I64 }, |
| 9175 | { DOT_S, DOT }, |
| 9176 | { DROP_EXNREF_S, DROP_EXNREF }, |
| 9177 | { DROP_EXTERNREF_S, DROP_EXTERNREF }, |
| 9178 | { DROP_F32_S, DROP_F32 }, |
| 9179 | { DROP_F64_S, DROP_F64 }, |
| 9180 | { DROP_FUNCREF_S, DROP_FUNCREF }, |
| 9181 | { DROP_I32_S, DROP_I32 }, |
| 9182 | { DROP_I64_S, DROP_I64 }, |
| 9183 | { DROP_V128_S, DROP_V128 }, |
| 9184 | { ELSE_S, ELSE }, |
| 9185 | { END_BLOCK_S, END_BLOCK }, |
| 9186 | { END_FUNCTION_S, END_FUNCTION }, |
| 9187 | { END_IF_S, END_IF }, |
| 9188 | { END_LOOP_S, END_LOOP }, |
| 9189 | { END_S, END }, |
| 9190 | { END_TRY_S, END_TRY }, |
| 9191 | { END_TRY_TABLE_S, END_TRY_TABLE }, |
| 9192 | { EQZ_I32_S, EQZ_I32 }, |
| 9193 | { EQZ_I64_S, EQZ_I64 }, |
| 9194 | { EQ_F16x8_S, EQ_F16x8 }, |
| 9195 | { EQ_F32_S, EQ_F32 }, |
| 9196 | { EQ_F32x4_S, EQ_F32x4 }, |
| 9197 | { EQ_F64_S, EQ_F64 }, |
| 9198 | { EQ_F64x2_S, EQ_F64x2 }, |
| 9199 | { EQ_I16x8_S, EQ_I16x8 }, |
| 9200 | { EQ_I32_S, EQ_I32 }, |
| 9201 | { EQ_I32x4_S, EQ_I32x4 }, |
| 9202 | { EQ_I64_S, EQ_I64 }, |
| 9203 | { EQ_I64x2_S, EQ_I64x2 }, |
| 9204 | { EQ_I8x16_S, EQ_I8x16 }, |
| 9205 | { EXTMUL_HIGH_S_I16x8_S, EXTMUL_HIGH_S_I16x8 }, |
| 9206 | { EXTMUL_HIGH_S_I32x4_S, EXTMUL_HIGH_S_I32x4 }, |
| 9207 | { EXTMUL_HIGH_S_I64x2_S, EXTMUL_HIGH_S_I64x2 }, |
| 9208 | { EXTMUL_HIGH_U_I16x8_S, EXTMUL_HIGH_U_I16x8 }, |
| 9209 | { EXTMUL_HIGH_U_I32x4_S, EXTMUL_HIGH_U_I32x4 }, |
| 9210 | { EXTMUL_HIGH_U_I64x2_S, EXTMUL_HIGH_U_I64x2 }, |
| 9211 | { EXTMUL_LOW_S_I16x8_S, EXTMUL_LOW_S_I16x8 }, |
| 9212 | { EXTMUL_LOW_S_I32x4_S, EXTMUL_LOW_S_I32x4 }, |
| 9213 | { EXTMUL_LOW_S_I64x2_S, EXTMUL_LOW_S_I64x2 }, |
| 9214 | { EXTMUL_LOW_U_I16x8_S, EXTMUL_LOW_U_I16x8 }, |
| 9215 | { EXTMUL_LOW_U_I32x4_S, EXTMUL_LOW_U_I32x4 }, |
| 9216 | { EXTMUL_LOW_U_I64x2_S, EXTMUL_LOW_U_I64x2 }, |
| 9217 | { EXTRACT_LANE_F16x8_S, EXTRACT_LANE_F16x8 }, |
| 9218 | { EXTRACT_LANE_F32x4_S, EXTRACT_LANE_F32x4 }, |
| 9219 | { EXTRACT_LANE_F64x2_S, EXTRACT_LANE_F64x2 }, |
| 9220 | { EXTRACT_LANE_I16x8_s_S, EXTRACT_LANE_I16x8_s }, |
| 9221 | { EXTRACT_LANE_I16x8_u_S, EXTRACT_LANE_I16x8_u }, |
| 9222 | { EXTRACT_LANE_I32x4_S, EXTRACT_LANE_I32x4 }, |
| 9223 | { EXTRACT_LANE_I64x2_S, EXTRACT_LANE_I64x2 }, |
| 9224 | { EXTRACT_LANE_I8x16_s_S, EXTRACT_LANE_I8x16_s }, |
| 9225 | { EXTRACT_LANE_I8x16_u_S, EXTRACT_LANE_I8x16_u }, |
| 9226 | { F32_CONVERT_S_I32_S, F32_CONVERT_S_I32 }, |
| 9227 | { F32_CONVERT_S_I64_S, F32_CONVERT_S_I64 }, |
| 9228 | { F32_CONVERT_U_I32_S, F32_CONVERT_U_I32 }, |
| 9229 | { F32_CONVERT_U_I64_S, F32_CONVERT_U_I64 }, |
| 9230 | { F32_DEMOTE_F64_S, F32_DEMOTE_F64 }, |
| 9231 | { F32_REINTERPRET_I32_S, F32_REINTERPRET_I32 }, |
| 9232 | { F64_CONVERT_S_I32_S, F64_CONVERT_S_I32 }, |
| 9233 | { F64_CONVERT_S_I64_S, F64_CONVERT_S_I64 }, |
| 9234 | { F64_CONVERT_U_I32_S, F64_CONVERT_U_I32 }, |
| 9235 | { F64_CONVERT_U_I64_S, F64_CONVERT_U_I64 }, |
| 9236 | { F64_PROMOTE_F32_S, F64_PROMOTE_F32 }, |
| 9237 | { F64_REINTERPRET_I64_S, F64_REINTERPRET_I64 }, |
| 9238 | { FALLTHROUGH_RETURN_S, FALLTHROUGH_RETURN }, |
| 9239 | { FLOOR_F16x8_S, FLOOR_F16x8 }, |
| 9240 | { FLOOR_F32_S, FLOOR_F32 }, |
| 9241 | { FLOOR_F32x4_S, FLOOR_F32x4 }, |
| 9242 | { FLOOR_F64_S, FLOOR_F64 }, |
| 9243 | { FLOOR_F64x2_S, FLOOR_F64x2 }, |
| 9244 | { FP_TO_SINT_I32_F32_S, FP_TO_SINT_I32_F32 }, |
| 9245 | { FP_TO_SINT_I32_F64_S, FP_TO_SINT_I32_F64 }, |
| 9246 | { FP_TO_SINT_I64_F32_S, FP_TO_SINT_I64_F32 }, |
| 9247 | { FP_TO_SINT_I64_F64_S, FP_TO_SINT_I64_F64 }, |
| 9248 | { FP_TO_UINT_I32_F32_S, FP_TO_UINT_I32_F32 }, |
| 9249 | { FP_TO_UINT_I32_F64_S, FP_TO_UINT_I32_F64 }, |
| 9250 | { FP_TO_UINT_I64_F32_S, FP_TO_UINT_I64_F32 }, |
| 9251 | { FP_TO_UINT_I64_F64_S, FP_TO_UINT_I64_F64 }, |
| 9252 | { GE_F16x8_S, GE_F16x8 }, |
| 9253 | { GE_F32_S, GE_F32 }, |
| 9254 | { GE_F32x4_S, GE_F32x4 }, |
| 9255 | { GE_F64_S, GE_F64 }, |
| 9256 | { GE_F64x2_S, GE_F64x2 }, |
| 9257 | { GE_S_I16x8_S, GE_S_I16x8 }, |
| 9258 | { GE_S_I32_S, GE_S_I32 }, |
| 9259 | { GE_S_I32x4_S, GE_S_I32x4 }, |
| 9260 | { GE_S_I64_S, GE_S_I64 }, |
| 9261 | { GE_S_I64x2_S, GE_S_I64x2 }, |
| 9262 | { GE_S_I8x16_S, GE_S_I8x16 }, |
| 9263 | { GE_U_I16x8_S, GE_U_I16x8 }, |
| 9264 | { GE_U_I32_S, GE_U_I32 }, |
| 9265 | { GE_U_I32x4_S, GE_U_I32x4 }, |
| 9266 | { GE_U_I64_S, GE_U_I64 }, |
| 9267 | { GE_U_I8x16_S, GE_U_I8x16 }, |
| 9268 | { GLOBAL_GET_EXNREF_S, GLOBAL_GET_EXNREF }, |
| 9269 | { GLOBAL_GET_EXTERNREF_S, GLOBAL_GET_EXTERNREF }, |
| 9270 | { GLOBAL_GET_F32_S, GLOBAL_GET_F32 }, |
| 9271 | { GLOBAL_GET_F64_S, GLOBAL_GET_F64 }, |
| 9272 | { GLOBAL_GET_FUNCREF_S, GLOBAL_GET_FUNCREF }, |
| 9273 | { GLOBAL_GET_I32_S, GLOBAL_GET_I32 }, |
| 9274 | { GLOBAL_GET_I64_S, GLOBAL_GET_I64 }, |
| 9275 | { GLOBAL_GET_V128_S, GLOBAL_GET_V128 }, |
| 9276 | { GLOBAL_SET_EXNREF_S, GLOBAL_SET_EXNREF }, |
| 9277 | { GLOBAL_SET_EXTERNREF_S, GLOBAL_SET_EXTERNREF }, |
| 9278 | { GLOBAL_SET_F32_S, GLOBAL_SET_F32 }, |
| 9279 | { GLOBAL_SET_F64_S, GLOBAL_SET_F64 }, |
| 9280 | { GLOBAL_SET_FUNCREF_S, GLOBAL_SET_FUNCREF }, |
| 9281 | { GLOBAL_SET_I32_S, GLOBAL_SET_I32 }, |
| 9282 | { GLOBAL_SET_I64_S, GLOBAL_SET_I64 }, |
| 9283 | { GLOBAL_SET_V128_S, GLOBAL_SET_V128 }, |
| 9284 | { GT_F16x8_S, GT_F16x8 }, |
| 9285 | { GT_F32_S, GT_F32 }, |
| 9286 | { GT_F32x4_S, GT_F32x4 }, |
| 9287 | { GT_F64_S, GT_F64 }, |
| 9288 | { GT_F64x2_S, GT_F64x2 }, |
| 9289 | { GT_S_I16x8_S, GT_S_I16x8 }, |
| 9290 | { GT_S_I32_S, GT_S_I32 }, |
| 9291 | { GT_S_I32x4_S, GT_S_I32x4 }, |
| 9292 | { GT_S_I64_S, GT_S_I64 }, |
| 9293 | { GT_S_I64x2_S, GT_S_I64x2 }, |
| 9294 | { GT_S_I8x16_S, GT_S_I8x16 }, |
| 9295 | { GT_U_I16x8_S, GT_U_I16x8 }, |
| 9296 | { GT_U_I32_S, GT_U_I32 }, |
| 9297 | { GT_U_I32x4_S, GT_U_I32x4 }, |
| 9298 | { GT_U_I64_S, GT_U_I64 }, |
| 9299 | { GT_U_I8x16_S, GT_U_I8x16 }, |
| 9300 | { I32_EXTEND16_S_I32_S, I32_EXTEND16_S_I32 }, |
| 9301 | { I32_EXTEND8_S_I32_S, I32_EXTEND8_S_I32 }, |
| 9302 | { I32_REINTERPRET_F32_S, I32_REINTERPRET_F32 }, |
| 9303 | { I32_TRUNC_S_F32_S, I32_TRUNC_S_F32 }, |
| 9304 | { I32_TRUNC_S_F64_S, I32_TRUNC_S_F64 }, |
| 9305 | { I32_TRUNC_S_SAT_F32_S, I32_TRUNC_S_SAT_F32 }, |
| 9306 | { I32_TRUNC_S_SAT_F64_S, I32_TRUNC_S_SAT_F64 }, |
| 9307 | { I32_TRUNC_U_F32_S, I32_TRUNC_U_F32 }, |
| 9308 | { I32_TRUNC_U_F64_S, I32_TRUNC_U_F64 }, |
| 9309 | { I32_TRUNC_U_SAT_F32_S, I32_TRUNC_U_SAT_F32 }, |
| 9310 | { I32_TRUNC_U_SAT_F64_S, I32_TRUNC_U_SAT_F64 }, |
| 9311 | { I32_WRAP_I64_S, I32_WRAP_I64 }, |
| 9312 | { I64_ADD128_S, I64_ADD128 }, |
| 9313 | { I64_EXTEND16_S_I64_S, I64_EXTEND16_S_I64 }, |
| 9314 | { I64_EXTEND32_S_I64_S, I64_EXTEND32_S_I64 }, |
| 9315 | { I64_EXTEND8_S_I64_S, I64_EXTEND8_S_I64 }, |
| 9316 | { I64_EXTEND_S_I32_S, I64_EXTEND_S_I32 }, |
| 9317 | { I64_EXTEND_U_I32_S, I64_EXTEND_U_I32 }, |
| 9318 | { I64_MUL_WIDE_S_S, I64_MUL_WIDE_S }, |
| 9319 | { I64_MUL_WIDE_U_S, I64_MUL_WIDE_U }, |
| 9320 | { I64_REINTERPRET_F64_S, I64_REINTERPRET_F64 }, |
| 9321 | { I64_SUB128_S, I64_SUB128 }, |
| 9322 | { I64_TRUNC_S_F32_S, I64_TRUNC_S_F32 }, |
| 9323 | { I64_TRUNC_S_F64_S, I64_TRUNC_S_F64 }, |
| 9324 | { I64_TRUNC_S_SAT_F32_S, I64_TRUNC_S_SAT_F32 }, |
| 9325 | { I64_TRUNC_S_SAT_F64_S, I64_TRUNC_S_SAT_F64 }, |
| 9326 | { I64_TRUNC_U_F32_S, I64_TRUNC_U_F32 }, |
| 9327 | { I64_TRUNC_U_F64_S, I64_TRUNC_U_F64 }, |
| 9328 | { I64_TRUNC_U_SAT_F32_S, I64_TRUNC_U_SAT_F32 }, |
| 9329 | { I64_TRUNC_U_SAT_F64_S, I64_TRUNC_U_SAT_F64 }, |
| 9330 | { IF_S, IF }, |
| 9331 | { LANESELECT_I16x8_S, LANESELECT_I16x8 }, |
| 9332 | { LANESELECT_I32x4_S, LANESELECT_I32x4 }, |
| 9333 | { LANESELECT_I64x2_S, LANESELECT_I64x2 }, |
| 9334 | { LANESELECT_I8x16_S, LANESELECT_I8x16 }, |
| 9335 | { LE_F16x8_S, LE_F16x8 }, |
| 9336 | { LE_F32_S, LE_F32 }, |
| 9337 | { LE_F32x4_S, LE_F32x4 }, |
| 9338 | { LE_F64_S, LE_F64 }, |
| 9339 | { LE_F64x2_S, LE_F64x2 }, |
| 9340 | { LE_S_I16x8_S, LE_S_I16x8 }, |
| 9341 | { LE_S_I32_S, LE_S_I32 }, |
| 9342 | { LE_S_I32x4_S, LE_S_I32x4 }, |
| 9343 | { LE_S_I64_S, LE_S_I64 }, |
| 9344 | { LE_S_I64x2_S, LE_S_I64x2 }, |
| 9345 | { LE_S_I8x16_S, LE_S_I8x16 }, |
| 9346 | { LE_U_I16x8_S, LE_U_I16x8 }, |
| 9347 | { LE_U_I32_S, LE_U_I32 }, |
| 9348 | { LE_U_I32x4_S, LE_U_I32x4 }, |
| 9349 | { LE_U_I64_S, LE_U_I64 }, |
| 9350 | { LE_U_I8x16_S, LE_U_I8x16 }, |
| 9351 | { LOAD16_SPLAT_A32_S, LOAD16_SPLAT_A32 }, |
| 9352 | { LOAD16_SPLAT_A64_S, LOAD16_SPLAT_A64 }, |
| 9353 | { LOAD16_S_I32_A32_S, LOAD16_S_I32_A32 }, |
| 9354 | { LOAD16_S_I32_A64_S, LOAD16_S_I32_A64 }, |
| 9355 | { LOAD16_S_I64_A32_S, LOAD16_S_I64_A32 }, |
| 9356 | { LOAD16_S_I64_A64_S, LOAD16_S_I64_A64 }, |
| 9357 | { LOAD16_U_I32_A32_S, LOAD16_U_I32_A32 }, |
| 9358 | { LOAD16_U_I32_A64_S, LOAD16_U_I32_A64 }, |
| 9359 | { LOAD16_U_I64_A32_S, LOAD16_U_I64_A32 }, |
| 9360 | { LOAD16_U_I64_A64_S, LOAD16_U_I64_A64 }, |
| 9361 | { LOAD32_SPLAT_A32_S, LOAD32_SPLAT_A32 }, |
| 9362 | { LOAD32_SPLAT_A64_S, LOAD32_SPLAT_A64 }, |
| 9363 | { LOAD32_S_I64_A32_S, LOAD32_S_I64_A32 }, |
| 9364 | { LOAD32_S_I64_A64_S, LOAD32_S_I64_A64 }, |
| 9365 | { LOAD32_U_I64_A32_S, LOAD32_U_I64_A32 }, |
| 9366 | { LOAD32_U_I64_A64_S, LOAD32_U_I64_A64 }, |
| 9367 | { LOAD64_SPLAT_A32_S, LOAD64_SPLAT_A32 }, |
| 9368 | { LOAD64_SPLAT_A64_S, LOAD64_SPLAT_A64 }, |
| 9369 | { LOAD8_SPLAT_A32_S, LOAD8_SPLAT_A32 }, |
| 9370 | { LOAD8_SPLAT_A64_S, LOAD8_SPLAT_A64 }, |
| 9371 | { LOAD8_S_I32_A32_S, LOAD8_S_I32_A32 }, |
| 9372 | { LOAD8_S_I32_A64_S, LOAD8_S_I32_A64 }, |
| 9373 | { LOAD8_S_I64_A32_S, LOAD8_S_I64_A32 }, |
| 9374 | { LOAD8_S_I64_A64_S, LOAD8_S_I64_A64 }, |
| 9375 | { LOAD8_U_I32_A32_S, LOAD8_U_I32_A32 }, |
| 9376 | { LOAD8_U_I32_A64_S, LOAD8_U_I32_A64 }, |
| 9377 | { LOAD8_U_I64_A32_S, LOAD8_U_I64_A32 }, |
| 9378 | { LOAD8_U_I64_A64_S, LOAD8_U_I64_A64 }, |
| 9379 | { LOAD_EXTEND_S_I16x8_A32_S, LOAD_EXTEND_S_I16x8_A32 }, |
| 9380 | { LOAD_EXTEND_S_I16x8_A64_S, LOAD_EXTEND_S_I16x8_A64 }, |
| 9381 | { LOAD_EXTEND_S_I32x4_A32_S, LOAD_EXTEND_S_I32x4_A32 }, |
| 9382 | { LOAD_EXTEND_S_I32x4_A64_S, LOAD_EXTEND_S_I32x4_A64 }, |
| 9383 | { LOAD_EXTEND_S_I64x2_A32_S, LOAD_EXTEND_S_I64x2_A32 }, |
| 9384 | { LOAD_EXTEND_S_I64x2_A64_S, LOAD_EXTEND_S_I64x2_A64 }, |
| 9385 | { LOAD_EXTEND_U_I16x8_A32_S, LOAD_EXTEND_U_I16x8_A32 }, |
| 9386 | { LOAD_EXTEND_U_I16x8_A64_S, LOAD_EXTEND_U_I16x8_A64 }, |
| 9387 | { LOAD_EXTEND_U_I32x4_A32_S, LOAD_EXTEND_U_I32x4_A32 }, |
| 9388 | { LOAD_EXTEND_U_I32x4_A64_S, LOAD_EXTEND_U_I32x4_A64 }, |
| 9389 | { LOAD_EXTEND_U_I64x2_A32_S, LOAD_EXTEND_U_I64x2_A32 }, |
| 9390 | { LOAD_EXTEND_U_I64x2_A64_S, LOAD_EXTEND_U_I64x2_A64 }, |
| 9391 | { LOAD_F16_F32_A32_S, LOAD_F16_F32_A32 }, |
| 9392 | { LOAD_F16_F32_A64_S, LOAD_F16_F32_A64 }, |
| 9393 | { LOAD_F32_A32_S, LOAD_F32_A32 }, |
| 9394 | { LOAD_F32_A64_S, LOAD_F32_A64 }, |
| 9395 | { LOAD_F64_A32_S, LOAD_F64_A32 }, |
| 9396 | { LOAD_F64_A64_S, LOAD_F64_A64 }, |
| 9397 | { LOAD_I32_A32_S, LOAD_I32_A32 }, |
| 9398 | { LOAD_I32_A64_S, LOAD_I32_A64 }, |
| 9399 | { LOAD_I64_A32_S, LOAD_I64_A32 }, |
| 9400 | { LOAD_I64_A64_S, LOAD_I64_A64 }, |
| 9401 | { LOAD_LANE_16_A32_S, LOAD_LANE_16_A32 }, |
| 9402 | { LOAD_LANE_16_A64_S, LOAD_LANE_16_A64 }, |
| 9403 | { LOAD_LANE_32_A32_S, LOAD_LANE_32_A32 }, |
| 9404 | { LOAD_LANE_32_A64_S, LOAD_LANE_32_A64 }, |
| 9405 | { LOAD_LANE_64_A32_S, LOAD_LANE_64_A32 }, |
| 9406 | { LOAD_LANE_64_A64_S, LOAD_LANE_64_A64 }, |
| 9407 | { LOAD_LANE_8_A32_S, LOAD_LANE_8_A32 }, |
| 9408 | { LOAD_LANE_8_A64_S, LOAD_LANE_8_A64 }, |
| 9409 | { LOAD_V128_A32_S, LOAD_V128_A32 }, |
| 9410 | { LOAD_V128_A64_S, LOAD_V128_A64 }, |
| 9411 | { LOAD_ZERO_32_A32_S, LOAD_ZERO_32_A32 }, |
| 9412 | { LOAD_ZERO_32_A64_S, LOAD_ZERO_32_A64 }, |
| 9413 | { LOAD_ZERO_64_A32_S, LOAD_ZERO_64_A32 }, |
| 9414 | { LOAD_ZERO_64_A64_S, LOAD_ZERO_64_A64 }, |
| 9415 | { LOCAL_GET_EXNREF_S, LOCAL_GET_EXNREF }, |
| 9416 | { LOCAL_GET_EXTERNREF_S, LOCAL_GET_EXTERNREF }, |
| 9417 | { LOCAL_GET_F32_S, LOCAL_GET_F32 }, |
| 9418 | { LOCAL_GET_F64_S, LOCAL_GET_F64 }, |
| 9419 | { LOCAL_GET_FUNCREF_S, LOCAL_GET_FUNCREF }, |
| 9420 | { LOCAL_GET_I32_S, LOCAL_GET_I32 }, |
| 9421 | { LOCAL_GET_I64_S, LOCAL_GET_I64 }, |
| 9422 | { LOCAL_GET_V128_S, LOCAL_GET_V128 }, |
| 9423 | { LOCAL_SET_EXNREF_S, LOCAL_SET_EXNREF }, |
| 9424 | { LOCAL_SET_EXTERNREF_S, LOCAL_SET_EXTERNREF }, |
| 9425 | { LOCAL_SET_F32_S, LOCAL_SET_F32 }, |
| 9426 | { LOCAL_SET_F64_S, LOCAL_SET_F64 }, |
| 9427 | { LOCAL_SET_FUNCREF_S, LOCAL_SET_FUNCREF }, |
| 9428 | { LOCAL_SET_I32_S, LOCAL_SET_I32 }, |
| 9429 | { LOCAL_SET_I64_S, LOCAL_SET_I64 }, |
| 9430 | { LOCAL_SET_V128_S, LOCAL_SET_V128 }, |
| 9431 | { LOCAL_TEE_EXNREF_S, LOCAL_TEE_EXNREF }, |
| 9432 | { LOCAL_TEE_EXTERNREF_S, LOCAL_TEE_EXTERNREF }, |
| 9433 | { LOCAL_TEE_F32_S, LOCAL_TEE_F32 }, |
| 9434 | { LOCAL_TEE_F64_S, LOCAL_TEE_F64 }, |
| 9435 | { LOCAL_TEE_FUNCREF_S, LOCAL_TEE_FUNCREF }, |
| 9436 | { LOCAL_TEE_I32_S, LOCAL_TEE_I32 }, |
| 9437 | { LOCAL_TEE_I64_S, LOCAL_TEE_I64 }, |
| 9438 | { LOCAL_TEE_V128_S, LOCAL_TEE_V128 }, |
| 9439 | { LOOP_S, LOOP }, |
| 9440 | { LT_F16x8_S, LT_F16x8 }, |
| 9441 | { LT_F32_S, LT_F32 }, |
| 9442 | { LT_F32x4_S, LT_F32x4 }, |
| 9443 | { LT_F64_S, LT_F64 }, |
| 9444 | { LT_F64x2_S, LT_F64x2 }, |
| 9445 | { LT_S_I16x8_S, LT_S_I16x8 }, |
| 9446 | { LT_S_I32_S, LT_S_I32 }, |
| 9447 | { LT_S_I32x4_S, LT_S_I32x4 }, |
| 9448 | { LT_S_I64_S, LT_S_I64 }, |
| 9449 | { LT_S_I64x2_S, LT_S_I64x2 }, |
| 9450 | { LT_S_I8x16_S, LT_S_I8x16 }, |
| 9451 | { LT_U_I16x8_S, LT_U_I16x8 }, |
| 9452 | { LT_U_I32_S, LT_U_I32 }, |
| 9453 | { LT_U_I32x4_S, LT_U_I32x4 }, |
| 9454 | { LT_U_I64_S, LT_U_I64 }, |
| 9455 | { LT_U_I8x16_S, LT_U_I8x16 }, |
| 9456 | { MADD_F16x8_S, MADD_F16x8 }, |
| 9457 | { MADD_F32x4_S, MADD_F32x4 }, |
| 9458 | { MADD_F64x2_S, MADD_F64x2 }, |
| 9459 | { MAX_F16x8_S, MAX_F16x8 }, |
| 9460 | { MAX_F32_S, MAX_F32 }, |
| 9461 | { MAX_F32x4_S, MAX_F32x4 }, |
| 9462 | { MAX_F64_S, MAX_F64 }, |
| 9463 | { MAX_F64x2_S, MAX_F64x2 }, |
| 9464 | { MAX_S_I16x8_S, MAX_S_I16x8 }, |
| 9465 | { MAX_S_I32x4_S, MAX_S_I32x4 }, |
| 9466 | { MAX_S_I8x16_S, MAX_S_I8x16 }, |
| 9467 | { MAX_U_I16x8_S, MAX_U_I16x8 }, |
| 9468 | { MAX_U_I32x4_S, MAX_U_I32x4 }, |
| 9469 | { MAX_U_I8x16_S, MAX_U_I8x16 }, |
| 9470 | { MEMCPY_A32_S, MEMCPY_A32 }, |
| 9471 | { MEMCPY_A64_S, MEMCPY_A64 }, |
| 9472 | { MEMORY_ATOMIC_NOTIFY_A32_S, MEMORY_ATOMIC_NOTIFY_A32 }, |
| 9473 | { MEMORY_ATOMIC_NOTIFY_A64_S, MEMORY_ATOMIC_NOTIFY_A64 }, |
| 9474 | { MEMORY_ATOMIC_WAIT32_A32_S, MEMORY_ATOMIC_WAIT32_A32 }, |
| 9475 | { MEMORY_ATOMIC_WAIT32_A64_S, MEMORY_ATOMIC_WAIT32_A64 }, |
| 9476 | { MEMORY_ATOMIC_WAIT64_A32_S, MEMORY_ATOMIC_WAIT64_A32 }, |
| 9477 | { MEMORY_ATOMIC_WAIT64_A64_S, MEMORY_ATOMIC_WAIT64_A64 }, |
| 9478 | { MEMORY_COPY_A32_S, MEMORY_COPY_A32 }, |
| 9479 | { MEMORY_COPY_A64_S, MEMORY_COPY_A64 }, |
| 9480 | { MEMORY_FILL_A32_S, MEMORY_FILL_A32 }, |
| 9481 | { MEMORY_FILL_A64_S, MEMORY_FILL_A64 }, |
| 9482 | { MEMORY_INIT_A32_S, MEMORY_INIT_A32 }, |
| 9483 | { MEMORY_INIT_A64_S, MEMORY_INIT_A64 }, |
| 9484 | { MEMSET_A32_S, MEMSET_A32 }, |
| 9485 | { MEMSET_A64_S, MEMSET_A64 }, |
| 9486 | { MIN_F16x8_S, MIN_F16x8 }, |
| 9487 | { MIN_F32_S, MIN_F32 }, |
| 9488 | { MIN_F32x4_S, MIN_F32x4 }, |
| 9489 | { MIN_F64_S, MIN_F64 }, |
| 9490 | { MIN_F64x2_S, MIN_F64x2 }, |
| 9491 | { MIN_S_I16x8_S, MIN_S_I16x8 }, |
| 9492 | { MIN_S_I32x4_S, MIN_S_I32x4 }, |
| 9493 | { MIN_S_I8x16_S, MIN_S_I8x16 }, |
| 9494 | { MIN_U_I16x8_S, MIN_U_I16x8 }, |
| 9495 | { MIN_U_I32x4_S, MIN_U_I32x4 }, |
| 9496 | { MIN_U_I8x16_S, MIN_U_I8x16 }, |
| 9497 | { MUL_F16x8_S, MUL_F16x8 }, |
| 9498 | { MUL_F32_S, MUL_F32 }, |
| 9499 | { MUL_F32x4_S, MUL_F32x4 }, |
| 9500 | { MUL_F64_S, MUL_F64 }, |
| 9501 | { MUL_F64x2_S, MUL_F64x2 }, |
| 9502 | { MUL_I16x8_S, MUL_I16x8 }, |
| 9503 | { MUL_I32_S, MUL_I32 }, |
| 9504 | { MUL_I32x4_S, MUL_I32x4 }, |
| 9505 | { MUL_I64_S, MUL_I64 }, |
| 9506 | { MUL_I64x2_S, MUL_I64x2 }, |
| 9507 | { NARROW_S_I16x8_S, NARROW_S_I16x8 }, |
| 9508 | { NARROW_S_I8x16_S, NARROW_S_I8x16 }, |
| 9509 | { NARROW_U_I16x8_S, NARROW_U_I16x8 }, |
| 9510 | { NARROW_U_I8x16_S, NARROW_U_I8x16 }, |
| 9511 | { NEAREST_F16x8_S, NEAREST_F16x8 }, |
| 9512 | { NEAREST_F32_S, NEAREST_F32 }, |
| 9513 | { NEAREST_F32x4_S, NEAREST_F32x4 }, |
| 9514 | { NEAREST_F64_S, NEAREST_F64 }, |
| 9515 | { NEAREST_F64x2_S, NEAREST_F64x2 }, |
| 9516 | { NEG_F16x8_S, NEG_F16x8 }, |
| 9517 | { NEG_F32_S, NEG_F32 }, |
| 9518 | { NEG_F32x4_S, NEG_F32x4 }, |
| 9519 | { NEG_F64_S, NEG_F64 }, |
| 9520 | { NEG_F64x2_S, NEG_F64x2 }, |
| 9521 | { NEG_I16x8_S, NEG_I16x8 }, |
| 9522 | { NEG_I32x4_S, NEG_I32x4 }, |
| 9523 | { NEG_I64x2_S, NEG_I64x2 }, |
| 9524 | { NEG_I8x16_S, NEG_I8x16 }, |
| 9525 | { NE_F16x8_S, NE_F16x8 }, |
| 9526 | { NE_F32_S, NE_F32 }, |
| 9527 | { NE_F32x4_S, NE_F32x4 }, |
| 9528 | { NE_F64_S, NE_F64 }, |
| 9529 | { NE_F64x2_S, NE_F64x2 }, |
| 9530 | { NE_I16x8_S, NE_I16x8 }, |
| 9531 | { NE_I32_S, NE_I32 }, |
| 9532 | { NE_I32x4_S, NE_I32x4 }, |
| 9533 | { NE_I64_S, NE_I64 }, |
| 9534 | { NE_I64x2_S, NE_I64x2 }, |
| 9535 | { NE_I8x16_S, NE_I8x16 }, |
| 9536 | { NMADD_F16x8_S, NMADD_F16x8 }, |
| 9537 | { NMADD_F32x4_S, NMADD_F32x4 }, |
| 9538 | { NMADD_F64x2_S, NMADD_F64x2 }, |
| 9539 | { NOP_S, NOP }, |
| 9540 | { NOT_S, NOT }, |
| 9541 | { OR_I32_S, OR_I32 }, |
| 9542 | { OR_I64_S, OR_I64 }, |
| 9543 | { OR_S, OR }, |
| 9544 | { PMAX_F16x8_S, PMAX_F16x8 }, |
| 9545 | { PMAX_F32x4_S, PMAX_F32x4 }, |
| 9546 | { PMAX_F64x2_S, PMAX_F64x2 }, |
| 9547 | { PMIN_F16x8_S, PMIN_F16x8 }, |
| 9548 | { PMIN_F32x4_S, PMIN_F32x4 }, |
| 9549 | { PMIN_F64x2_S, PMIN_F64x2 }, |
| 9550 | { POPCNT_I32_S, POPCNT_I32 }, |
| 9551 | { POPCNT_I64_S, POPCNT_I64 }, |
| 9552 | { POPCNT_I8x16_S, POPCNT_I8x16 }, |
| 9553 | { Q15MULR_SAT_S_I16x8_S, Q15MULR_SAT_S_I16x8 }, |
| 9554 | { REF_CAST_FUNCREF_S, REF_CAST_FUNCREF }, |
| 9555 | { REF_FUNC_S, REF_FUNC }, |
| 9556 | { REF_IS_NULL_EXNREF_S, REF_IS_NULL_EXNREF }, |
| 9557 | { REF_IS_NULL_EXTERNREF_S, REF_IS_NULL_EXTERNREF }, |
| 9558 | { REF_IS_NULL_FUNCREF_S, REF_IS_NULL_FUNCREF }, |
| 9559 | { REF_NULL_EXNREF_S, REF_NULL_EXNREF }, |
| 9560 | { REF_NULL_EXTERNREF_S, REF_NULL_EXTERNREF }, |
| 9561 | { REF_NULL_FUNCREF_S, REF_NULL_FUNCREF }, |
| 9562 | { REF_TEST_FUNCREF_S, REF_TEST_FUNCREF }, |
| 9563 | { RELAXED_DOT_ADD_S, RELAXED_DOT_ADD }, |
| 9564 | { RELAXED_DOT_BFLOAT_S, RELAXED_DOT_BFLOAT }, |
| 9565 | { RELAXED_DOT_S, RELAXED_DOT }, |
| 9566 | { RELAXED_Q15MULR_S_I16x8_S, RELAXED_Q15MULR_S_I16x8 }, |
| 9567 | { RELAXED_SWIZZLE_S, RELAXED_SWIZZLE }, |
| 9568 | { REM_S_I32_S, REM_S_I32 }, |
| 9569 | { REM_S_I64_S, REM_S_I64 }, |
| 9570 | { REM_U_I32_S, REM_U_I32 }, |
| 9571 | { REM_U_I64_S, REM_U_I64 }, |
| 9572 | { REPLACE_LANE_F16x8_S, REPLACE_LANE_F16x8 }, |
| 9573 | { REPLACE_LANE_F32x4_S, REPLACE_LANE_F32x4 }, |
| 9574 | { REPLACE_LANE_F64x2_S, REPLACE_LANE_F64x2 }, |
| 9575 | { REPLACE_LANE_I16x8_S, REPLACE_LANE_I16x8 }, |
| 9576 | { REPLACE_LANE_I32x4_S, REPLACE_LANE_I32x4 }, |
| 9577 | { REPLACE_LANE_I64x2_S, REPLACE_LANE_I64x2 }, |
| 9578 | { REPLACE_LANE_I8x16_S, REPLACE_LANE_I8x16 }, |
| 9579 | { RETHROW_S, RETHROW }, |
| 9580 | { RETURN_S, RETURN }, |
| 9581 | { RET_CALL_INDIRECT_S, RET_CALL_INDIRECT }, |
| 9582 | { RET_CALL_REF_S, RET_CALL_REF }, |
| 9583 | { RET_CALL_S, RET_CALL }, |
| 9584 | { ROTL_I32_S, ROTL_I32 }, |
| 9585 | { ROTL_I64_S, ROTL_I64 }, |
| 9586 | { ROTR_I32_S, ROTR_I32 }, |
| 9587 | { ROTR_I64_S, ROTR_I64 }, |
| 9588 | { SELECT_EXNREF_S, SELECT_EXNREF }, |
| 9589 | { SELECT_EXTERNREF_S, SELECT_EXTERNREF }, |
| 9590 | { SELECT_F32_S, SELECT_F32 }, |
| 9591 | { SELECT_F64_S, SELECT_F64 }, |
| 9592 | { SELECT_FUNCREF_S, SELECT_FUNCREF }, |
| 9593 | { SELECT_I32_S, SELECT_I32 }, |
| 9594 | { SELECT_I64_S, SELECT_I64 }, |
| 9595 | { SELECT_T_S, SELECT_T }, |
| 9596 | { SELECT_V128_S, SELECT_V128 }, |
| 9597 | { SHL_I16x8_S, SHL_I16x8 }, |
| 9598 | { SHL_I32_S, SHL_I32 }, |
| 9599 | { SHL_I32x4_S, SHL_I32x4 }, |
| 9600 | { SHL_I64_S, SHL_I64 }, |
| 9601 | { SHL_I64x2_S, SHL_I64x2 }, |
| 9602 | { SHL_I8x16_S, SHL_I8x16 }, |
| 9603 | { SHR_S_I16x8_S, SHR_S_I16x8 }, |
| 9604 | { SHR_S_I32_S, SHR_S_I32 }, |
| 9605 | { SHR_S_I32x4_S, SHR_S_I32x4 }, |
| 9606 | { SHR_S_I64_S, SHR_S_I64 }, |
| 9607 | { SHR_S_I64x2_S, SHR_S_I64x2 }, |
| 9608 | { SHR_S_I8x16_S, SHR_S_I8x16 }, |
| 9609 | { SHR_U_I16x8_S, SHR_U_I16x8 }, |
| 9610 | { SHR_U_I32_S, SHR_U_I32 }, |
| 9611 | { SHR_U_I32x4_S, SHR_U_I32x4 }, |
| 9612 | { SHR_U_I64_S, SHR_U_I64 }, |
| 9613 | { SHR_U_I64x2_S, SHR_U_I64x2 }, |
| 9614 | { SHR_U_I8x16_S, SHR_U_I8x16 }, |
| 9615 | { SHUFFLE_S, SHUFFLE }, |
| 9616 | { SIMD_RELAXED_FMAX_F32x4_S, SIMD_RELAXED_FMAX_F32x4 }, |
| 9617 | { SIMD_RELAXED_FMAX_F64x2_S, SIMD_RELAXED_FMAX_F64x2 }, |
| 9618 | { SIMD_RELAXED_FMIN_F32x4_S, SIMD_RELAXED_FMIN_F32x4 }, |
| 9619 | { SIMD_RELAXED_FMIN_F64x2_S, SIMD_RELAXED_FMIN_F64x2 }, |
| 9620 | { SPLAT_F16x8_S, SPLAT_F16x8 }, |
| 9621 | { SPLAT_F32x4_S, SPLAT_F32x4 }, |
| 9622 | { SPLAT_F64x2_S, SPLAT_F64x2 }, |
| 9623 | { SPLAT_I16x8_S, SPLAT_I16x8 }, |
| 9624 | { SPLAT_I32x4_S, SPLAT_I32x4 }, |
| 9625 | { SPLAT_I64x2_S, SPLAT_I64x2 }, |
| 9626 | { SPLAT_I8x16_S, SPLAT_I8x16 }, |
| 9627 | { SQRT_F16x8_S, SQRT_F16x8 }, |
| 9628 | { SQRT_F32_S, SQRT_F32 }, |
| 9629 | { SQRT_F32x4_S, SQRT_F32x4 }, |
| 9630 | { SQRT_F64_S, SQRT_F64 }, |
| 9631 | { SQRT_F64x2_S, SQRT_F64x2 }, |
| 9632 | { STORE16_I32_A32_S, STORE16_I32_A32 }, |
| 9633 | { STORE16_I32_A64_S, STORE16_I32_A64 }, |
| 9634 | { STORE16_I64_A32_S, STORE16_I64_A32 }, |
| 9635 | { STORE16_I64_A64_S, STORE16_I64_A64 }, |
| 9636 | { STORE32_I64_A32_S, STORE32_I64_A32 }, |
| 9637 | { STORE32_I64_A64_S, STORE32_I64_A64 }, |
| 9638 | { STORE8_I32_A32_S, STORE8_I32_A32 }, |
| 9639 | { STORE8_I32_A64_S, STORE8_I32_A64 }, |
| 9640 | { STORE8_I64_A32_S, STORE8_I64_A32 }, |
| 9641 | { STORE8_I64_A64_S, STORE8_I64_A64 }, |
| 9642 | { STORE_F16_F32_A32_S, STORE_F16_F32_A32 }, |
| 9643 | { STORE_F16_F32_A64_S, STORE_F16_F32_A64 }, |
| 9644 | { STORE_F32_A32_S, STORE_F32_A32 }, |
| 9645 | { STORE_F32_A64_S, STORE_F32_A64 }, |
| 9646 | { STORE_F64_A32_S, STORE_F64_A32 }, |
| 9647 | { STORE_F64_A64_S, STORE_F64_A64 }, |
| 9648 | { STORE_I32_A32_S, STORE_I32_A32 }, |
| 9649 | { STORE_I32_A64_S, STORE_I32_A64 }, |
| 9650 | { STORE_I64_A32_S, STORE_I64_A32 }, |
| 9651 | { STORE_I64_A64_S, STORE_I64_A64 }, |
| 9652 | { STORE_LANE_I16x8_A32_S, STORE_LANE_I16x8_A32 }, |
| 9653 | { STORE_LANE_I16x8_A64_S, STORE_LANE_I16x8_A64 }, |
| 9654 | { STORE_LANE_I32x4_A32_S, STORE_LANE_I32x4_A32 }, |
| 9655 | { STORE_LANE_I32x4_A64_S, STORE_LANE_I32x4_A64 }, |
| 9656 | { STORE_LANE_I64x2_A32_S, STORE_LANE_I64x2_A32 }, |
| 9657 | { STORE_LANE_I64x2_A64_S, STORE_LANE_I64x2_A64 }, |
| 9658 | { STORE_LANE_I8x16_A32_S, STORE_LANE_I8x16_A32 }, |
| 9659 | { STORE_LANE_I8x16_A64_S, STORE_LANE_I8x16_A64 }, |
| 9660 | { STORE_V128_A32_S, STORE_V128_A32 }, |
| 9661 | { STORE_V128_A64_S, STORE_V128_A64 }, |
| 9662 | { SUB_F16x8_S, SUB_F16x8 }, |
| 9663 | { SUB_F32_S, SUB_F32 }, |
| 9664 | { SUB_F32x4_S, SUB_F32x4 }, |
| 9665 | { SUB_F64_S, SUB_F64 }, |
| 9666 | { SUB_F64x2_S, SUB_F64x2 }, |
| 9667 | { SUB_I16x8_S, SUB_I16x8 }, |
| 9668 | { SUB_I32_S, SUB_I32 }, |
| 9669 | { SUB_I32x4_S, SUB_I32x4 }, |
| 9670 | { SUB_I64_S, SUB_I64 }, |
| 9671 | { SUB_I64x2_S, SUB_I64x2 }, |
| 9672 | { SUB_I8x16_S, SUB_I8x16 }, |
| 9673 | { SUB_SAT_S_I16x8_S, SUB_SAT_S_I16x8 }, |
| 9674 | { SUB_SAT_S_I8x16_S, SUB_SAT_S_I8x16 }, |
| 9675 | { SUB_SAT_U_I16x8_S, SUB_SAT_U_I16x8 }, |
| 9676 | { SUB_SAT_U_I8x16_S, SUB_SAT_U_I8x16 }, |
| 9677 | { SWIZZLE_S, SWIZZLE }, |
| 9678 | { TABLE_COPY_S, TABLE_COPY }, |
| 9679 | { TABLE_FILL_EXNREF_S, TABLE_FILL_EXNREF }, |
| 9680 | { TABLE_FILL_EXTERNREF_S, TABLE_FILL_EXTERNREF }, |
| 9681 | { TABLE_FILL_FUNCREF_S, TABLE_FILL_FUNCREF }, |
| 9682 | { TABLE_GET_EXNREF_S, TABLE_GET_EXNREF }, |
| 9683 | { TABLE_GET_EXTERNREF_S, TABLE_GET_EXTERNREF }, |
| 9684 | { TABLE_GET_FUNCREF_S, TABLE_GET_FUNCREF }, |
| 9685 | { TABLE_GROW_EXNREF_S, TABLE_GROW_EXNREF }, |
| 9686 | { TABLE_GROW_EXTERNREF_S, TABLE_GROW_EXTERNREF }, |
| 9687 | { TABLE_GROW_FUNCREF_S, TABLE_GROW_FUNCREF }, |
| 9688 | { TABLE_SET_EXNREF_S, TABLE_SET_EXNREF }, |
| 9689 | { TABLE_SET_EXTERNREF_S, TABLE_SET_EXTERNREF }, |
| 9690 | { TABLE_SET_FUNCREF_S, TABLE_SET_FUNCREF }, |
| 9691 | { TABLE_SIZE_S, TABLE_SIZE }, |
| 9692 | { TEE_EXNREF_S, TEE_EXNREF }, |
| 9693 | { TEE_EXTERNREF_S, TEE_EXTERNREF }, |
| 9694 | { TEE_F32_S, TEE_F32 }, |
| 9695 | { TEE_F64_S, TEE_F64 }, |
| 9696 | { TEE_FUNCREF_S, TEE_FUNCREF }, |
| 9697 | { TEE_I32_S, TEE_I32 }, |
| 9698 | { TEE_I64_S, TEE_I64 }, |
| 9699 | { TEE_V128_S, TEE_V128 }, |
| 9700 | { THROW_REF_S, THROW_REF }, |
| 9701 | { THROW_S, THROW }, |
| 9702 | { TRUNC_F16x8_S, TRUNC_F16x8 }, |
| 9703 | { TRUNC_F32_S, TRUNC_F32 }, |
| 9704 | { TRUNC_F32x4_S, TRUNC_F32x4 }, |
| 9705 | { TRUNC_F64_S, TRUNC_F64 }, |
| 9706 | { TRUNC_F64x2_S, TRUNC_F64x2 }, |
| 9707 | { TRY_S, TRY }, |
| 9708 | { TRY_TABLE_S, TRY_TABLE }, |
| 9709 | { UNREACHABLE_S, UNREACHABLE }, |
| 9710 | { XOR_I32_S, XOR_I32 }, |
| 9711 | { XOR_I64_S, XOR_I64 }, |
| 9712 | { XOR_S, XOR }, |
| 9713 | { anonymous_14864MEMORY_GROW_A32_S, anonymous_14864MEMORY_GROW_A32 }, |
| 9714 | { anonymous_14864MEMORY_SIZE_A32_S, anonymous_14864MEMORY_SIZE_A32 }, |
| 9715 | { anonymous_14865MEMORY_GROW_A64_S, anonymous_14865MEMORY_GROW_A64 }, |
| 9716 | { anonymous_14865MEMORY_SIZE_A64_S, anonymous_14865MEMORY_SIZE_A64 }, |
| 9717 | { convert_low_s_F64x2_S, convert_low_s_F64x2 }, |
| 9718 | { convert_low_u_F64x2_S, convert_low_u_F64x2 }, |
| 9719 | { demote_zero_F16x8_S, demote_zero_F16x8 }, |
| 9720 | { demote_zero_F32x4_S, demote_zero_F32x4 }, |
| 9721 | { extadd_pairwise_s_I16x8_S, extadd_pairwise_s_I16x8 }, |
| 9722 | { extadd_pairwise_s_I32x4_S, extadd_pairwise_s_I32x4 }, |
| 9723 | { extadd_pairwise_u_I16x8_S, extadd_pairwise_u_I16x8 }, |
| 9724 | { extadd_pairwise_u_I32x4_S, extadd_pairwise_u_I32x4 }, |
| 9725 | { extend_high_s_I16x8_S, extend_high_s_I16x8 }, |
| 9726 | { extend_high_s_I32x4_S, extend_high_s_I32x4 }, |
| 9727 | { extend_high_s_I64x2_S, extend_high_s_I64x2 }, |
| 9728 | { extend_high_u_I16x8_S, extend_high_u_I16x8 }, |
| 9729 | { extend_high_u_I32x4_S, extend_high_u_I32x4 }, |
| 9730 | { extend_high_u_I64x2_S, extend_high_u_I64x2 }, |
| 9731 | { extend_low_s_I16x8_S, extend_low_s_I16x8 }, |
| 9732 | { extend_low_s_I32x4_S, extend_low_s_I32x4 }, |
| 9733 | { extend_low_s_I64x2_S, extend_low_s_I64x2 }, |
| 9734 | { extend_low_u_I16x8_S, extend_low_u_I16x8 }, |
| 9735 | { extend_low_u_I32x4_S, extend_low_u_I32x4 }, |
| 9736 | { extend_low_u_I64x2_S, extend_low_u_I64x2 }, |
| 9737 | { fp_to_sint_I16x8_S, fp_to_sint_I16x8 }, |
| 9738 | { fp_to_sint_I32x4_S, fp_to_sint_I32x4 }, |
| 9739 | { fp_to_uint_I16x8_S, fp_to_uint_I16x8 }, |
| 9740 | { fp_to_uint_I32x4_S, fp_to_uint_I32x4 }, |
| 9741 | { int_wasm_relaxed_trunc_signed_I32x4_S, int_wasm_relaxed_trunc_signed_I32x4 }, |
| 9742 | { int_wasm_relaxed_trunc_signed_zero_I32x4_S, int_wasm_relaxed_trunc_signed_zero_I32x4 }, |
| 9743 | { int_wasm_relaxed_trunc_unsigned_I32x4_S, int_wasm_relaxed_trunc_unsigned_I32x4 }, |
| 9744 | { int_wasm_relaxed_trunc_unsigned_zero_I32x4_S, int_wasm_relaxed_trunc_unsigned_zero_I32x4 }, |
| 9745 | { promote_low_F32x4_S, promote_low_F32x4 }, |
| 9746 | { promote_low_F64x2_S, promote_low_F64x2 }, |
| 9747 | { sint_to_fp_F16x8_S, sint_to_fp_F16x8 }, |
| 9748 | { sint_to_fp_F32x4_S, sint_to_fp_F32x4 }, |
| 9749 | { trunc_sat_zero_s_I32x4_S, trunc_sat_zero_s_I32x4 }, |
| 9750 | { trunc_sat_zero_u_I32x4_S, trunc_sat_zero_u_I32x4 }, |
| 9751 | { uint_to_fp_F16x8_S, uint_to_fp_F16x8 }, |
| 9752 | { uint_to_fp_F32x4_S, uint_to_fp_F32x4 }, |
| 9753 | }; // End of Table |
| 9754 | |
| 9755 | unsigned mid; |
| 9756 | unsigned start = 0; |
| 9757 | unsigned end = 824; |
| 9758 | while (start < end) { |
| 9759 | mid = start + (end - start) / 2; |
| 9760 | if (Opcode == Table[mid][0]) |
| 9761 | break; |
| 9762 | if (Opcode < Table[mid][0]) |
| 9763 | end = mid; |
| 9764 | else |
| 9765 | start = mid + 1; |
| 9766 | } |
| 9767 | if (start == end) |
| 9768 | return -1; // Instruction doesn't exist in this table. |
| 9769 | |
| 9770 | return Table[mid][1]; |
| 9771 | } |
| 9772 | |
| 9773 | // getStackOpcode |
| 9774 | LLVM_READONLY |
| 9775 | int32_t getStackOpcode(uint32_t Opcode) { |
| 9776 | using namespace WebAssembly; |
| 9777 | static constexpr uint32_t Table[][2] = { |
| 9778 | { CALL_PARAMS, CALL_PARAMS_S }, |
| 9779 | { CALL_RESULTS, CALL_RESULTS_S }, |
| 9780 | { CATCHRET, CATCHRET_S }, |
| 9781 | { CLEANUPRET, CLEANUPRET_S }, |
| 9782 | { COMPILER_FENCE, COMPILER_FENCE_S }, |
| 9783 | { RET_CALL_PARAMS, RET_CALL_PARAMS_S }, |
| 9784 | { RET_CALL_RESULTS, RET_CALL_RESULTS_S }, |
| 9785 | { ABS_F16x8, ABS_F16x8_S }, |
| 9786 | { ABS_F32, ABS_F32_S }, |
| 9787 | { ABS_F32x4, ABS_F32x4_S }, |
| 9788 | { ABS_F64, ABS_F64_S }, |
| 9789 | { ABS_F64x2, ABS_F64x2_S }, |
| 9790 | { ABS_I16x8, ABS_I16x8_S }, |
| 9791 | { ABS_I32x4, ABS_I32x4_S }, |
| 9792 | { ABS_I64x2, ABS_I64x2_S }, |
| 9793 | { ABS_I8x16, ABS_I8x16_S }, |
| 9794 | { ADD_F16x8, ADD_F16x8_S }, |
| 9795 | { ADD_F32, ADD_F32_S }, |
| 9796 | { ADD_F32x4, ADD_F32x4_S }, |
| 9797 | { ADD_F64, ADD_F64_S }, |
| 9798 | { ADD_F64x2, ADD_F64x2_S }, |
| 9799 | { ADD_I16x8, ADD_I16x8_S }, |
| 9800 | { ADD_I32, ADD_I32_S }, |
| 9801 | { ADD_I32x4, ADD_I32x4_S }, |
| 9802 | { ADD_I64, ADD_I64_S }, |
| 9803 | { ADD_I64x2, ADD_I64x2_S }, |
| 9804 | { ADD_I8x16, ADD_I8x16_S }, |
| 9805 | { ADD_SAT_S_I16x8, ADD_SAT_S_I16x8_S }, |
| 9806 | { ADD_SAT_S_I8x16, ADD_SAT_S_I8x16_S }, |
| 9807 | { ADD_SAT_U_I16x8, ADD_SAT_U_I16x8_S }, |
| 9808 | { ADD_SAT_U_I8x16, ADD_SAT_U_I8x16_S }, |
| 9809 | { ADJCALLSTACKDOWN, ADJCALLSTACKDOWN_S }, |
| 9810 | { ADJCALLSTACKUP, ADJCALLSTACKUP_S }, |
| 9811 | { ALLTRUE_I16x8, ALLTRUE_I16x8_S }, |
| 9812 | { ALLTRUE_I32x4, ALLTRUE_I32x4_S }, |
| 9813 | { ALLTRUE_I64x2, ALLTRUE_I64x2_S }, |
| 9814 | { ALLTRUE_I8x16, ALLTRUE_I8x16_S }, |
| 9815 | { AND, AND_S }, |
| 9816 | { ANDNOT, ANDNOT_S }, |
| 9817 | { AND_I32, AND_I32_S }, |
| 9818 | { AND_I64, AND_I64_S }, |
| 9819 | { ANYTRUE, ANYTRUE_S }, |
| 9820 | { ARGUMENT_exnref, ARGUMENT_exnref_S }, |
| 9821 | { ARGUMENT_externref, ARGUMENT_externref_S }, |
| 9822 | { ARGUMENT_f32, ARGUMENT_f32_S }, |
| 9823 | { ARGUMENT_f64, ARGUMENT_f64_S }, |
| 9824 | { ARGUMENT_funcref, ARGUMENT_funcref_S }, |
| 9825 | { ARGUMENT_i32, ARGUMENT_i32_S }, |
| 9826 | { ARGUMENT_i64, ARGUMENT_i64_S }, |
| 9827 | { ARGUMENT_v16i8, ARGUMENT_v16i8_S }, |
| 9828 | { ARGUMENT_v2f64, ARGUMENT_v2f64_S }, |
| 9829 | { ARGUMENT_v2i64, ARGUMENT_v2i64_S }, |
| 9830 | { ARGUMENT_v4f32, ARGUMENT_v4f32_S }, |
| 9831 | { ARGUMENT_v4i32, ARGUMENT_v4i32_S }, |
| 9832 | { ARGUMENT_v8f16, ARGUMENT_v8f16_S }, |
| 9833 | { ARGUMENT_v8i16, ARGUMENT_v8i16_S }, |
| 9834 | { ATOMIC_FENCE, ATOMIC_FENCE_S }, |
| 9835 | { ATOMIC_LOAD16_U_I32_A32, ATOMIC_LOAD16_U_I32_A32_S }, |
| 9836 | { ATOMIC_LOAD16_U_I32_A64, ATOMIC_LOAD16_U_I32_A64_S }, |
| 9837 | { ATOMIC_LOAD16_U_I64_A32, ATOMIC_LOAD16_U_I64_A32_S }, |
| 9838 | { ATOMIC_LOAD16_U_I64_A64, ATOMIC_LOAD16_U_I64_A64_S }, |
| 9839 | { ATOMIC_LOAD32_U_I64_A32, ATOMIC_LOAD32_U_I64_A32_S }, |
| 9840 | { ATOMIC_LOAD32_U_I64_A64, ATOMIC_LOAD32_U_I64_A64_S }, |
| 9841 | { ATOMIC_LOAD8_U_I32_A32, ATOMIC_LOAD8_U_I32_A32_S }, |
| 9842 | { ATOMIC_LOAD8_U_I32_A64, ATOMIC_LOAD8_U_I32_A64_S }, |
| 9843 | { ATOMIC_LOAD8_U_I64_A32, ATOMIC_LOAD8_U_I64_A32_S }, |
| 9844 | { ATOMIC_LOAD8_U_I64_A64, ATOMIC_LOAD8_U_I64_A64_S }, |
| 9845 | { ATOMIC_LOAD_I32_A32, ATOMIC_LOAD_I32_A32_S }, |
| 9846 | { ATOMIC_LOAD_I32_A64, ATOMIC_LOAD_I32_A64_S }, |
| 9847 | { ATOMIC_LOAD_I64_A32, ATOMIC_LOAD_I64_A32_S }, |
| 9848 | { ATOMIC_LOAD_I64_A64, ATOMIC_LOAD_I64_A64_S }, |
| 9849 | { ATOMIC_RMW16_U_ADD_I32_A32, ATOMIC_RMW16_U_ADD_I32_A32_S }, |
| 9850 | { ATOMIC_RMW16_U_ADD_I32_A64, ATOMIC_RMW16_U_ADD_I32_A64_S }, |
| 9851 | { ATOMIC_RMW16_U_ADD_I64_A32, ATOMIC_RMW16_U_ADD_I64_A32_S }, |
| 9852 | { ATOMIC_RMW16_U_ADD_I64_A64, ATOMIC_RMW16_U_ADD_I64_A64_S }, |
| 9853 | { ATOMIC_RMW16_U_AND_I32_A32, ATOMIC_RMW16_U_AND_I32_A32_S }, |
| 9854 | { ATOMIC_RMW16_U_AND_I32_A64, ATOMIC_RMW16_U_AND_I32_A64_S }, |
| 9855 | { ATOMIC_RMW16_U_AND_I64_A32, ATOMIC_RMW16_U_AND_I64_A32_S }, |
| 9856 | { ATOMIC_RMW16_U_AND_I64_A64, ATOMIC_RMW16_U_AND_I64_A64_S }, |
| 9857 | { ATOMIC_RMW16_U_CMPXCHG_I32_A32, ATOMIC_RMW16_U_CMPXCHG_I32_A32_S }, |
| 9858 | { ATOMIC_RMW16_U_CMPXCHG_I32_A64, ATOMIC_RMW16_U_CMPXCHG_I32_A64_S }, |
| 9859 | { ATOMIC_RMW16_U_CMPXCHG_I64_A32, ATOMIC_RMW16_U_CMPXCHG_I64_A32_S }, |
| 9860 | { ATOMIC_RMW16_U_CMPXCHG_I64_A64, ATOMIC_RMW16_U_CMPXCHG_I64_A64_S }, |
| 9861 | { ATOMIC_RMW16_U_OR_I32_A32, ATOMIC_RMW16_U_OR_I32_A32_S }, |
| 9862 | { ATOMIC_RMW16_U_OR_I32_A64, ATOMIC_RMW16_U_OR_I32_A64_S }, |
| 9863 | { ATOMIC_RMW16_U_OR_I64_A32, ATOMIC_RMW16_U_OR_I64_A32_S }, |
| 9864 | { ATOMIC_RMW16_U_OR_I64_A64, ATOMIC_RMW16_U_OR_I64_A64_S }, |
| 9865 | { ATOMIC_RMW16_U_SUB_I32_A32, ATOMIC_RMW16_U_SUB_I32_A32_S }, |
| 9866 | { ATOMIC_RMW16_U_SUB_I32_A64, ATOMIC_RMW16_U_SUB_I32_A64_S }, |
| 9867 | { ATOMIC_RMW16_U_SUB_I64_A32, ATOMIC_RMW16_U_SUB_I64_A32_S }, |
| 9868 | { ATOMIC_RMW16_U_SUB_I64_A64, ATOMIC_RMW16_U_SUB_I64_A64_S }, |
| 9869 | { ATOMIC_RMW16_U_XCHG_I32_A32, ATOMIC_RMW16_U_XCHG_I32_A32_S }, |
| 9870 | { ATOMIC_RMW16_U_XCHG_I32_A64, ATOMIC_RMW16_U_XCHG_I32_A64_S }, |
| 9871 | { ATOMIC_RMW16_U_XCHG_I64_A32, ATOMIC_RMW16_U_XCHG_I64_A32_S }, |
| 9872 | { ATOMIC_RMW16_U_XCHG_I64_A64, ATOMIC_RMW16_U_XCHG_I64_A64_S }, |
| 9873 | { ATOMIC_RMW16_U_XOR_I32_A32, ATOMIC_RMW16_U_XOR_I32_A32_S }, |
| 9874 | { ATOMIC_RMW16_U_XOR_I32_A64, ATOMIC_RMW16_U_XOR_I32_A64_S }, |
| 9875 | { ATOMIC_RMW16_U_XOR_I64_A32, ATOMIC_RMW16_U_XOR_I64_A32_S }, |
| 9876 | { ATOMIC_RMW16_U_XOR_I64_A64, ATOMIC_RMW16_U_XOR_I64_A64_S }, |
| 9877 | { ATOMIC_RMW32_U_ADD_I64_A32, ATOMIC_RMW32_U_ADD_I64_A32_S }, |
| 9878 | { ATOMIC_RMW32_U_ADD_I64_A64, ATOMIC_RMW32_U_ADD_I64_A64_S }, |
| 9879 | { ATOMIC_RMW32_U_AND_I64_A32, ATOMIC_RMW32_U_AND_I64_A32_S }, |
| 9880 | { ATOMIC_RMW32_U_AND_I64_A64, ATOMIC_RMW32_U_AND_I64_A64_S }, |
| 9881 | { ATOMIC_RMW32_U_CMPXCHG_I64_A32, ATOMIC_RMW32_U_CMPXCHG_I64_A32_S }, |
| 9882 | { ATOMIC_RMW32_U_CMPXCHG_I64_A64, ATOMIC_RMW32_U_CMPXCHG_I64_A64_S }, |
| 9883 | { ATOMIC_RMW32_U_OR_I64_A32, ATOMIC_RMW32_U_OR_I64_A32_S }, |
| 9884 | { ATOMIC_RMW32_U_OR_I64_A64, ATOMIC_RMW32_U_OR_I64_A64_S }, |
| 9885 | { ATOMIC_RMW32_U_SUB_I64_A32, ATOMIC_RMW32_U_SUB_I64_A32_S }, |
| 9886 | { ATOMIC_RMW32_U_SUB_I64_A64, ATOMIC_RMW32_U_SUB_I64_A64_S }, |
| 9887 | { ATOMIC_RMW32_U_XCHG_I64_A32, ATOMIC_RMW32_U_XCHG_I64_A32_S }, |
| 9888 | { ATOMIC_RMW32_U_XCHG_I64_A64, ATOMIC_RMW32_U_XCHG_I64_A64_S }, |
| 9889 | { ATOMIC_RMW32_U_XOR_I64_A32, ATOMIC_RMW32_U_XOR_I64_A32_S }, |
| 9890 | { ATOMIC_RMW32_U_XOR_I64_A64, ATOMIC_RMW32_U_XOR_I64_A64_S }, |
| 9891 | { ATOMIC_RMW8_U_ADD_I32_A32, ATOMIC_RMW8_U_ADD_I32_A32_S }, |
| 9892 | { ATOMIC_RMW8_U_ADD_I32_A64, ATOMIC_RMW8_U_ADD_I32_A64_S }, |
| 9893 | { ATOMIC_RMW8_U_ADD_I64_A32, ATOMIC_RMW8_U_ADD_I64_A32_S }, |
| 9894 | { ATOMIC_RMW8_U_ADD_I64_A64, ATOMIC_RMW8_U_ADD_I64_A64_S }, |
| 9895 | { ATOMIC_RMW8_U_AND_I32_A32, ATOMIC_RMW8_U_AND_I32_A32_S }, |
| 9896 | { ATOMIC_RMW8_U_AND_I32_A64, ATOMIC_RMW8_U_AND_I32_A64_S }, |
| 9897 | { ATOMIC_RMW8_U_AND_I64_A32, ATOMIC_RMW8_U_AND_I64_A32_S }, |
| 9898 | { ATOMIC_RMW8_U_AND_I64_A64, ATOMIC_RMW8_U_AND_I64_A64_S }, |
| 9899 | { ATOMIC_RMW8_U_CMPXCHG_I32_A32, ATOMIC_RMW8_U_CMPXCHG_I32_A32_S }, |
| 9900 | { ATOMIC_RMW8_U_CMPXCHG_I32_A64, ATOMIC_RMW8_U_CMPXCHG_I32_A64_S }, |
| 9901 | { ATOMIC_RMW8_U_CMPXCHG_I64_A32, ATOMIC_RMW8_U_CMPXCHG_I64_A32_S }, |
| 9902 | { ATOMIC_RMW8_U_CMPXCHG_I64_A64, ATOMIC_RMW8_U_CMPXCHG_I64_A64_S }, |
| 9903 | { ATOMIC_RMW8_U_OR_I32_A32, ATOMIC_RMW8_U_OR_I32_A32_S }, |
| 9904 | { ATOMIC_RMW8_U_OR_I32_A64, ATOMIC_RMW8_U_OR_I32_A64_S }, |
| 9905 | { ATOMIC_RMW8_U_OR_I64_A32, ATOMIC_RMW8_U_OR_I64_A32_S }, |
| 9906 | { ATOMIC_RMW8_U_OR_I64_A64, ATOMIC_RMW8_U_OR_I64_A64_S }, |
| 9907 | { ATOMIC_RMW8_U_SUB_I32_A32, ATOMIC_RMW8_U_SUB_I32_A32_S }, |
| 9908 | { ATOMIC_RMW8_U_SUB_I32_A64, ATOMIC_RMW8_U_SUB_I32_A64_S }, |
| 9909 | { ATOMIC_RMW8_U_SUB_I64_A32, ATOMIC_RMW8_U_SUB_I64_A32_S }, |
| 9910 | { ATOMIC_RMW8_U_SUB_I64_A64, ATOMIC_RMW8_U_SUB_I64_A64_S }, |
| 9911 | { ATOMIC_RMW8_U_XCHG_I32_A32, ATOMIC_RMW8_U_XCHG_I32_A32_S }, |
| 9912 | { ATOMIC_RMW8_U_XCHG_I32_A64, ATOMIC_RMW8_U_XCHG_I32_A64_S }, |
| 9913 | { ATOMIC_RMW8_U_XCHG_I64_A32, ATOMIC_RMW8_U_XCHG_I64_A32_S }, |
| 9914 | { ATOMIC_RMW8_U_XCHG_I64_A64, ATOMIC_RMW8_U_XCHG_I64_A64_S }, |
| 9915 | { ATOMIC_RMW8_U_XOR_I32_A32, ATOMIC_RMW8_U_XOR_I32_A32_S }, |
| 9916 | { ATOMIC_RMW8_U_XOR_I32_A64, ATOMIC_RMW8_U_XOR_I32_A64_S }, |
| 9917 | { ATOMIC_RMW8_U_XOR_I64_A32, ATOMIC_RMW8_U_XOR_I64_A32_S }, |
| 9918 | { ATOMIC_RMW8_U_XOR_I64_A64, ATOMIC_RMW8_U_XOR_I64_A64_S }, |
| 9919 | { ATOMIC_RMW_ADD_I32_A32, ATOMIC_RMW_ADD_I32_A32_S }, |
| 9920 | { ATOMIC_RMW_ADD_I32_A64, ATOMIC_RMW_ADD_I32_A64_S }, |
| 9921 | { ATOMIC_RMW_ADD_I64_A32, ATOMIC_RMW_ADD_I64_A32_S }, |
| 9922 | { ATOMIC_RMW_ADD_I64_A64, ATOMIC_RMW_ADD_I64_A64_S }, |
| 9923 | { ATOMIC_RMW_AND_I32_A32, ATOMIC_RMW_AND_I32_A32_S }, |
| 9924 | { ATOMIC_RMW_AND_I32_A64, ATOMIC_RMW_AND_I32_A64_S }, |
| 9925 | { ATOMIC_RMW_AND_I64_A32, ATOMIC_RMW_AND_I64_A32_S }, |
| 9926 | { ATOMIC_RMW_AND_I64_A64, ATOMIC_RMW_AND_I64_A64_S }, |
| 9927 | { ATOMIC_RMW_CMPXCHG_I32_A32, ATOMIC_RMW_CMPXCHG_I32_A32_S }, |
| 9928 | { ATOMIC_RMW_CMPXCHG_I32_A64, ATOMIC_RMW_CMPXCHG_I32_A64_S }, |
| 9929 | { ATOMIC_RMW_CMPXCHG_I64_A32, ATOMIC_RMW_CMPXCHG_I64_A32_S }, |
| 9930 | { ATOMIC_RMW_CMPXCHG_I64_A64, ATOMIC_RMW_CMPXCHG_I64_A64_S }, |
| 9931 | { ATOMIC_RMW_OR_I32_A32, ATOMIC_RMW_OR_I32_A32_S }, |
| 9932 | { ATOMIC_RMW_OR_I32_A64, ATOMIC_RMW_OR_I32_A64_S }, |
| 9933 | { ATOMIC_RMW_OR_I64_A32, ATOMIC_RMW_OR_I64_A32_S }, |
| 9934 | { ATOMIC_RMW_OR_I64_A64, ATOMIC_RMW_OR_I64_A64_S }, |
| 9935 | { ATOMIC_RMW_SUB_I32_A32, ATOMIC_RMW_SUB_I32_A32_S }, |
| 9936 | { ATOMIC_RMW_SUB_I32_A64, ATOMIC_RMW_SUB_I32_A64_S }, |
| 9937 | { ATOMIC_RMW_SUB_I64_A32, ATOMIC_RMW_SUB_I64_A32_S }, |
| 9938 | { ATOMIC_RMW_SUB_I64_A64, ATOMIC_RMW_SUB_I64_A64_S }, |
| 9939 | { ATOMIC_RMW_XCHG_I32_A32, ATOMIC_RMW_XCHG_I32_A32_S }, |
| 9940 | { ATOMIC_RMW_XCHG_I32_A64, ATOMIC_RMW_XCHG_I32_A64_S }, |
| 9941 | { ATOMIC_RMW_XCHG_I64_A32, ATOMIC_RMW_XCHG_I64_A32_S }, |
| 9942 | { ATOMIC_RMW_XCHG_I64_A64, ATOMIC_RMW_XCHG_I64_A64_S }, |
| 9943 | { ATOMIC_RMW_XOR_I32_A32, ATOMIC_RMW_XOR_I32_A32_S }, |
| 9944 | { ATOMIC_RMW_XOR_I32_A64, ATOMIC_RMW_XOR_I32_A64_S }, |
| 9945 | { ATOMIC_RMW_XOR_I64_A32, ATOMIC_RMW_XOR_I64_A32_S }, |
| 9946 | { ATOMIC_RMW_XOR_I64_A64, ATOMIC_RMW_XOR_I64_A64_S }, |
| 9947 | { ATOMIC_STORE16_I32_A32, ATOMIC_STORE16_I32_A32_S }, |
| 9948 | { ATOMIC_STORE16_I32_A64, ATOMIC_STORE16_I32_A64_S }, |
| 9949 | { ATOMIC_STORE16_I64_A32, ATOMIC_STORE16_I64_A32_S }, |
| 9950 | { ATOMIC_STORE16_I64_A64, ATOMIC_STORE16_I64_A64_S }, |
| 9951 | { ATOMIC_STORE32_I64_A32, ATOMIC_STORE32_I64_A32_S }, |
| 9952 | { ATOMIC_STORE32_I64_A64, ATOMIC_STORE32_I64_A64_S }, |
| 9953 | { ATOMIC_STORE8_I32_A32, ATOMIC_STORE8_I32_A32_S }, |
| 9954 | { ATOMIC_STORE8_I32_A64, ATOMIC_STORE8_I32_A64_S }, |
| 9955 | { ATOMIC_STORE8_I64_A32, ATOMIC_STORE8_I64_A32_S }, |
| 9956 | { ATOMIC_STORE8_I64_A64, ATOMIC_STORE8_I64_A64_S }, |
| 9957 | { ATOMIC_STORE_I32_A32, ATOMIC_STORE_I32_A32_S }, |
| 9958 | { ATOMIC_STORE_I32_A64, ATOMIC_STORE_I32_A64_S }, |
| 9959 | { ATOMIC_STORE_I64_A32, ATOMIC_STORE_I64_A32_S }, |
| 9960 | { ATOMIC_STORE_I64_A64, ATOMIC_STORE_I64_A64_S }, |
| 9961 | { AVGR_U_I16x8, AVGR_U_I16x8_S }, |
| 9962 | { AVGR_U_I8x16, AVGR_U_I8x16_S }, |
| 9963 | { BITMASK_I16x8, BITMASK_I16x8_S }, |
| 9964 | { BITMASK_I32x4, BITMASK_I32x4_S }, |
| 9965 | { BITMASK_I64x2, BITMASK_I64x2_S }, |
| 9966 | { BITMASK_I8x16, BITMASK_I8x16_S }, |
| 9967 | { BITSELECT, BITSELECT_S }, |
| 9968 | { BLOCK, BLOCK_S }, |
| 9969 | { BR, BR_S }, |
| 9970 | { BR_IF, BR_IF_S }, |
| 9971 | { BR_TABLE_I32, BR_TABLE_I32_S }, |
| 9972 | { BR_TABLE_I64, BR_TABLE_I64_S }, |
| 9973 | { BR_UNLESS, BR_UNLESS_S }, |
| 9974 | { CALL, CALL_S }, |
| 9975 | { CALL_INDIRECT, CALL_INDIRECT_S }, |
| 9976 | { CALL_REF, CALL_REF_S }, |
| 9977 | { CATCH, CATCH_S }, |
| 9978 | { CATCH_ALL, CATCH_ALL_S }, |
| 9979 | { CATCH_ALL_LEGACY, CATCH_ALL_LEGACY_S }, |
| 9980 | { CATCH_ALL_REF, CATCH_ALL_REF_S }, |
| 9981 | { CATCH_LEGACY, CATCH_LEGACY_S }, |
| 9982 | { CATCH_REF, CATCH_REF_S }, |
| 9983 | { CEIL_F16x8, CEIL_F16x8_S }, |
| 9984 | { CEIL_F32, CEIL_F32_S }, |
| 9985 | { CEIL_F32x4, CEIL_F32x4_S }, |
| 9986 | { CEIL_F64, CEIL_F64_S }, |
| 9987 | { CEIL_F64x2, CEIL_F64x2_S }, |
| 9988 | { CLZ_I32, CLZ_I32_S }, |
| 9989 | { CLZ_I64, CLZ_I64_S }, |
| 9990 | { CONST_F32, CONST_F32_S }, |
| 9991 | { CONST_F64, CONST_F64_S }, |
| 9992 | { CONST_I32, CONST_I32_S }, |
| 9993 | { CONST_I64, CONST_I64_S }, |
| 9994 | { CONST_V128_F32x4, CONST_V128_F32x4_S }, |
| 9995 | { CONST_V128_F64x2, CONST_V128_F64x2_S }, |
| 9996 | { CONST_V128_I16x8, CONST_V128_I16x8_S }, |
| 9997 | { CONST_V128_I32x4, CONST_V128_I32x4_S }, |
| 9998 | { CONST_V128_I64x2, CONST_V128_I64x2_S }, |
| 9999 | { CONST_V128_I8x16, CONST_V128_I8x16_S }, |
| 10000 | { COPYSIGN_F32, COPYSIGN_F32_S }, |
| 10001 | { COPYSIGN_F64, COPYSIGN_F64_S }, |
| 10002 | { COPY_EXNREF, COPY_EXNREF_S }, |
| 10003 | { COPY_EXTERNREF, COPY_EXTERNREF_S }, |
| 10004 | { COPY_F32, COPY_F32_S }, |
| 10005 | { COPY_F64, COPY_F64_S }, |
| 10006 | { COPY_FUNCREF, COPY_FUNCREF_S }, |
| 10007 | { COPY_I32, COPY_I32_S }, |
| 10008 | { COPY_I64, COPY_I64_S }, |
| 10009 | { COPY_V128, COPY_V128_S }, |
| 10010 | { CTZ_I32, CTZ_I32_S }, |
| 10011 | { CTZ_I64, CTZ_I64_S }, |
| 10012 | { DATA_DROP, DATA_DROP_S }, |
| 10013 | { DEBUG_UNREACHABLE, DEBUG_UNREACHABLE_S }, |
| 10014 | { DELEGATE, DELEGATE_S }, |
| 10015 | { DIV_F16x8, DIV_F16x8_S }, |
| 10016 | { DIV_F32, DIV_F32_S }, |
| 10017 | { DIV_F32x4, DIV_F32x4_S }, |
| 10018 | { DIV_F64, DIV_F64_S }, |
| 10019 | { DIV_F64x2, DIV_F64x2_S }, |
| 10020 | { DIV_S_I32, DIV_S_I32_S }, |
| 10021 | { DIV_S_I64, DIV_S_I64_S }, |
| 10022 | { DIV_U_I32, DIV_U_I32_S }, |
| 10023 | { DIV_U_I64, DIV_U_I64_S }, |
| 10024 | { DOT, DOT_S }, |
| 10025 | { DROP_EXNREF, DROP_EXNREF_S }, |
| 10026 | { DROP_EXTERNREF, DROP_EXTERNREF_S }, |
| 10027 | { DROP_F32, DROP_F32_S }, |
| 10028 | { DROP_F64, DROP_F64_S }, |
| 10029 | { DROP_FUNCREF, DROP_FUNCREF_S }, |
| 10030 | { DROP_I32, DROP_I32_S }, |
| 10031 | { DROP_I64, DROP_I64_S }, |
| 10032 | { DROP_V128, DROP_V128_S }, |
| 10033 | { ELSE, ELSE_S }, |
| 10034 | { END, END_S }, |
| 10035 | { END_BLOCK, END_BLOCK_S }, |
| 10036 | { END_FUNCTION, END_FUNCTION_S }, |
| 10037 | { END_IF, END_IF_S }, |
| 10038 | { END_LOOP, END_LOOP_S }, |
| 10039 | { END_TRY, END_TRY_S }, |
| 10040 | { END_TRY_TABLE, END_TRY_TABLE_S }, |
| 10041 | { EQZ_I32, EQZ_I32_S }, |
| 10042 | { EQZ_I64, EQZ_I64_S }, |
| 10043 | { EQ_F16x8, EQ_F16x8_S }, |
| 10044 | { EQ_F32, EQ_F32_S }, |
| 10045 | { EQ_F32x4, EQ_F32x4_S }, |
| 10046 | { EQ_F64, EQ_F64_S }, |
| 10047 | { EQ_F64x2, EQ_F64x2_S }, |
| 10048 | { EQ_I16x8, EQ_I16x8_S }, |
| 10049 | { EQ_I32, EQ_I32_S }, |
| 10050 | { EQ_I32x4, EQ_I32x4_S }, |
| 10051 | { EQ_I64, EQ_I64_S }, |
| 10052 | { EQ_I64x2, EQ_I64x2_S }, |
| 10053 | { EQ_I8x16, EQ_I8x16_S }, |
| 10054 | { EXTMUL_HIGH_S_I16x8, EXTMUL_HIGH_S_I16x8_S }, |
| 10055 | { EXTMUL_HIGH_S_I32x4, EXTMUL_HIGH_S_I32x4_S }, |
| 10056 | { EXTMUL_HIGH_S_I64x2, EXTMUL_HIGH_S_I64x2_S }, |
| 10057 | { EXTMUL_HIGH_U_I16x8, EXTMUL_HIGH_U_I16x8_S }, |
| 10058 | { EXTMUL_HIGH_U_I32x4, EXTMUL_HIGH_U_I32x4_S }, |
| 10059 | { EXTMUL_HIGH_U_I64x2, EXTMUL_HIGH_U_I64x2_S }, |
| 10060 | { EXTMUL_LOW_S_I16x8, EXTMUL_LOW_S_I16x8_S }, |
| 10061 | { EXTMUL_LOW_S_I32x4, EXTMUL_LOW_S_I32x4_S }, |
| 10062 | { EXTMUL_LOW_S_I64x2, EXTMUL_LOW_S_I64x2_S }, |
| 10063 | { EXTMUL_LOW_U_I16x8, EXTMUL_LOW_U_I16x8_S }, |
| 10064 | { EXTMUL_LOW_U_I32x4, EXTMUL_LOW_U_I32x4_S }, |
| 10065 | { EXTMUL_LOW_U_I64x2, EXTMUL_LOW_U_I64x2_S }, |
| 10066 | { EXTRACT_LANE_F16x8, EXTRACT_LANE_F16x8_S }, |
| 10067 | { EXTRACT_LANE_F32x4, EXTRACT_LANE_F32x4_S }, |
| 10068 | { EXTRACT_LANE_F64x2, EXTRACT_LANE_F64x2_S }, |
| 10069 | { EXTRACT_LANE_I16x8_s, EXTRACT_LANE_I16x8_s_S }, |
| 10070 | { EXTRACT_LANE_I16x8_u, EXTRACT_LANE_I16x8_u_S }, |
| 10071 | { EXTRACT_LANE_I32x4, EXTRACT_LANE_I32x4_S }, |
| 10072 | { EXTRACT_LANE_I64x2, EXTRACT_LANE_I64x2_S }, |
| 10073 | { EXTRACT_LANE_I8x16_s, EXTRACT_LANE_I8x16_s_S }, |
| 10074 | { EXTRACT_LANE_I8x16_u, EXTRACT_LANE_I8x16_u_S }, |
| 10075 | { F32_CONVERT_S_I32, F32_CONVERT_S_I32_S }, |
| 10076 | { F32_CONVERT_S_I64, F32_CONVERT_S_I64_S }, |
| 10077 | { F32_CONVERT_U_I32, F32_CONVERT_U_I32_S }, |
| 10078 | { F32_CONVERT_U_I64, F32_CONVERT_U_I64_S }, |
| 10079 | { F32_DEMOTE_F64, F32_DEMOTE_F64_S }, |
| 10080 | { F32_REINTERPRET_I32, F32_REINTERPRET_I32_S }, |
| 10081 | { F64_CONVERT_S_I32, F64_CONVERT_S_I32_S }, |
| 10082 | { F64_CONVERT_S_I64, F64_CONVERT_S_I64_S }, |
| 10083 | { F64_CONVERT_U_I32, F64_CONVERT_U_I32_S }, |
| 10084 | { F64_CONVERT_U_I64, F64_CONVERT_U_I64_S }, |
| 10085 | { F64_PROMOTE_F32, F64_PROMOTE_F32_S }, |
| 10086 | { F64_REINTERPRET_I64, F64_REINTERPRET_I64_S }, |
| 10087 | { FALLTHROUGH_RETURN, FALLTHROUGH_RETURN_S }, |
| 10088 | { FLOOR_F16x8, FLOOR_F16x8_S }, |
| 10089 | { FLOOR_F32, FLOOR_F32_S }, |
| 10090 | { FLOOR_F32x4, FLOOR_F32x4_S }, |
| 10091 | { FLOOR_F64, FLOOR_F64_S }, |
| 10092 | { FLOOR_F64x2, FLOOR_F64x2_S }, |
| 10093 | { FP_TO_SINT_I32_F32, FP_TO_SINT_I32_F32_S }, |
| 10094 | { FP_TO_SINT_I32_F64, FP_TO_SINT_I32_F64_S }, |
| 10095 | { FP_TO_SINT_I64_F32, FP_TO_SINT_I64_F32_S }, |
| 10096 | { FP_TO_SINT_I64_F64, FP_TO_SINT_I64_F64_S }, |
| 10097 | { FP_TO_UINT_I32_F32, FP_TO_UINT_I32_F32_S }, |
| 10098 | { FP_TO_UINT_I32_F64, FP_TO_UINT_I32_F64_S }, |
| 10099 | { FP_TO_UINT_I64_F32, FP_TO_UINT_I64_F32_S }, |
| 10100 | { FP_TO_UINT_I64_F64, FP_TO_UINT_I64_F64_S }, |
| 10101 | { GE_F16x8, GE_F16x8_S }, |
| 10102 | { GE_F32, GE_F32_S }, |
| 10103 | { GE_F32x4, GE_F32x4_S }, |
| 10104 | { GE_F64, GE_F64_S }, |
| 10105 | { GE_F64x2, GE_F64x2_S }, |
| 10106 | { GE_S_I16x8, GE_S_I16x8_S }, |
| 10107 | { GE_S_I32, GE_S_I32_S }, |
| 10108 | { GE_S_I32x4, GE_S_I32x4_S }, |
| 10109 | { GE_S_I64, GE_S_I64_S }, |
| 10110 | { GE_S_I64x2, GE_S_I64x2_S }, |
| 10111 | { GE_S_I8x16, GE_S_I8x16_S }, |
| 10112 | { GE_U_I16x8, GE_U_I16x8_S }, |
| 10113 | { GE_U_I32, GE_U_I32_S }, |
| 10114 | { GE_U_I32x4, GE_U_I32x4_S }, |
| 10115 | { GE_U_I64, GE_U_I64_S }, |
| 10116 | { GE_U_I8x16, GE_U_I8x16_S }, |
| 10117 | { GLOBAL_GET_EXNREF, GLOBAL_GET_EXNREF_S }, |
| 10118 | { GLOBAL_GET_EXTERNREF, GLOBAL_GET_EXTERNREF_S }, |
| 10119 | { GLOBAL_GET_F32, GLOBAL_GET_F32_S }, |
| 10120 | { GLOBAL_GET_F64, GLOBAL_GET_F64_S }, |
| 10121 | { GLOBAL_GET_FUNCREF, GLOBAL_GET_FUNCREF_S }, |
| 10122 | { GLOBAL_GET_I32, GLOBAL_GET_I32_S }, |
| 10123 | { GLOBAL_GET_I64, GLOBAL_GET_I64_S }, |
| 10124 | { GLOBAL_GET_V128, GLOBAL_GET_V128_S }, |
| 10125 | { GLOBAL_SET_EXNREF, GLOBAL_SET_EXNREF_S }, |
| 10126 | { GLOBAL_SET_EXTERNREF, GLOBAL_SET_EXTERNREF_S }, |
| 10127 | { GLOBAL_SET_F32, GLOBAL_SET_F32_S }, |
| 10128 | { GLOBAL_SET_F64, GLOBAL_SET_F64_S }, |
| 10129 | { GLOBAL_SET_FUNCREF, GLOBAL_SET_FUNCREF_S }, |
| 10130 | { GLOBAL_SET_I32, GLOBAL_SET_I32_S }, |
| 10131 | { GLOBAL_SET_I64, GLOBAL_SET_I64_S }, |
| 10132 | { GLOBAL_SET_V128, GLOBAL_SET_V128_S }, |
| 10133 | { GT_F16x8, GT_F16x8_S }, |
| 10134 | { GT_F32, GT_F32_S }, |
| 10135 | { GT_F32x4, GT_F32x4_S }, |
| 10136 | { GT_F64, GT_F64_S }, |
| 10137 | { GT_F64x2, GT_F64x2_S }, |
| 10138 | { GT_S_I16x8, GT_S_I16x8_S }, |
| 10139 | { GT_S_I32, GT_S_I32_S }, |
| 10140 | { GT_S_I32x4, GT_S_I32x4_S }, |
| 10141 | { GT_S_I64, GT_S_I64_S }, |
| 10142 | { GT_S_I64x2, GT_S_I64x2_S }, |
| 10143 | { GT_S_I8x16, GT_S_I8x16_S }, |
| 10144 | { GT_U_I16x8, GT_U_I16x8_S }, |
| 10145 | { GT_U_I32, GT_U_I32_S }, |
| 10146 | { GT_U_I32x4, GT_U_I32x4_S }, |
| 10147 | { GT_U_I64, GT_U_I64_S }, |
| 10148 | { GT_U_I8x16, GT_U_I8x16_S }, |
| 10149 | { I32_EXTEND16_S_I32, I32_EXTEND16_S_I32_S }, |
| 10150 | { I32_EXTEND8_S_I32, I32_EXTEND8_S_I32_S }, |
| 10151 | { I32_REINTERPRET_F32, I32_REINTERPRET_F32_S }, |
| 10152 | { I32_TRUNC_S_F32, I32_TRUNC_S_F32_S }, |
| 10153 | { I32_TRUNC_S_F64, I32_TRUNC_S_F64_S }, |
| 10154 | { I32_TRUNC_S_SAT_F32, I32_TRUNC_S_SAT_F32_S }, |
| 10155 | { I32_TRUNC_S_SAT_F64, I32_TRUNC_S_SAT_F64_S }, |
| 10156 | { I32_TRUNC_U_F32, I32_TRUNC_U_F32_S }, |
| 10157 | { I32_TRUNC_U_F64, I32_TRUNC_U_F64_S }, |
| 10158 | { I32_TRUNC_U_SAT_F32, I32_TRUNC_U_SAT_F32_S }, |
| 10159 | { I32_TRUNC_U_SAT_F64, I32_TRUNC_U_SAT_F64_S }, |
| 10160 | { I32_WRAP_I64, I32_WRAP_I64_S }, |
| 10161 | { I64_ADD128, I64_ADD128_S }, |
| 10162 | { I64_EXTEND16_S_I64, I64_EXTEND16_S_I64_S }, |
| 10163 | { I64_EXTEND32_S_I64, I64_EXTEND32_S_I64_S }, |
| 10164 | { I64_EXTEND8_S_I64, I64_EXTEND8_S_I64_S }, |
| 10165 | { I64_EXTEND_S_I32, I64_EXTEND_S_I32_S }, |
| 10166 | { I64_EXTEND_U_I32, I64_EXTEND_U_I32_S }, |
| 10167 | { I64_MUL_WIDE_S, I64_MUL_WIDE_S_S }, |
| 10168 | { I64_MUL_WIDE_U, I64_MUL_WIDE_U_S }, |
| 10169 | { I64_REINTERPRET_F64, I64_REINTERPRET_F64_S }, |
| 10170 | { I64_SUB128, I64_SUB128_S }, |
| 10171 | { I64_TRUNC_S_F32, I64_TRUNC_S_F32_S }, |
| 10172 | { I64_TRUNC_S_F64, I64_TRUNC_S_F64_S }, |
| 10173 | { I64_TRUNC_S_SAT_F32, I64_TRUNC_S_SAT_F32_S }, |
| 10174 | { I64_TRUNC_S_SAT_F64, I64_TRUNC_S_SAT_F64_S }, |
| 10175 | { I64_TRUNC_U_F32, I64_TRUNC_U_F32_S }, |
| 10176 | { I64_TRUNC_U_F64, I64_TRUNC_U_F64_S }, |
| 10177 | { I64_TRUNC_U_SAT_F32, I64_TRUNC_U_SAT_F32_S }, |
| 10178 | { I64_TRUNC_U_SAT_F64, I64_TRUNC_U_SAT_F64_S }, |
| 10179 | { IF, IF_S }, |
| 10180 | { LANESELECT_I16x8, LANESELECT_I16x8_S }, |
| 10181 | { LANESELECT_I32x4, LANESELECT_I32x4_S }, |
| 10182 | { LANESELECT_I64x2, LANESELECT_I64x2_S }, |
| 10183 | { LANESELECT_I8x16, LANESELECT_I8x16_S }, |
| 10184 | { LE_F16x8, LE_F16x8_S }, |
| 10185 | { LE_F32, LE_F32_S }, |
| 10186 | { LE_F32x4, LE_F32x4_S }, |
| 10187 | { LE_F64, LE_F64_S }, |
| 10188 | { LE_F64x2, LE_F64x2_S }, |
| 10189 | { LE_S_I16x8, LE_S_I16x8_S }, |
| 10190 | { LE_S_I32, LE_S_I32_S }, |
| 10191 | { LE_S_I32x4, LE_S_I32x4_S }, |
| 10192 | { LE_S_I64, LE_S_I64_S }, |
| 10193 | { LE_S_I64x2, LE_S_I64x2_S }, |
| 10194 | { LE_S_I8x16, LE_S_I8x16_S }, |
| 10195 | { LE_U_I16x8, LE_U_I16x8_S }, |
| 10196 | { LE_U_I32, LE_U_I32_S }, |
| 10197 | { LE_U_I32x4, LE_U_I32x4_S }, |
| 10198 | { LE_U_I64, LE_U_I64_S }, |
| 10199 | { LE_U_I8x16, LE_U_I8x16_S }, |
| 10200 | { LOAD16_SPLAT_A32, LOAD16_SPLAT_A32_S }, |
| 10201 | { LOAD16_SPLAT_A64, LOAD16_SPLAT_A64_S }, |
| 10202 | { LOAD16_S_I32_A32, LOAD16_S_I32_A32_S }, |
| 10203 | { LOAD16_S_I32_A64, LOAD16_S_I32_A64_S }, |
| 10204 | { LOAD16_S_I64_A32, LOAD16_S_I64_A32_S }, |
| 10205 | { LOAD16_S_I64_A64, LOAD16_S_I64_A64_S }, |
| 10206 | { LOAD16_U_I32_A32, LOAD16_U_I32_A32_S }, |
| 10207 | { LOAD16_U_I32_A64, LOAD16_U_I32_A64_S }, |
| 10208 | { LOAD16_U_I64_A32, LOAD16_U_I64_A32_S }, |
| 10209 | { LOAD16_U_I64_A64, LOAD16_U_I64_A64_S }, |
| 10210 | { LOAD32_SPLAT_A32, LOAD32_SPLAT_A32_S }, |
| 10211 | { LOAD32_SPLAT_A64, LOAD32_SPLAT_A64_S }, |
| 10212 | { LOAD32_S_I64_A32, LOAD32_S_I64_A32_S }, |
| 10213 | { LOAD32_S_I64_A64, LOAD32_S_I64_A64_S }, |
| 10214 | { LOAD32_U_I64_A32, LOAD32_U_I64_A32_S }, |
| 10215 | { LOAD32_U_I64_A64, LOAD32_U_I64_A64_S }, |
| 10216 | { LOAD64_SPLAT_A32, LOAD64_SPLAT_A32_S }, |
| 10217 | { LOAD64_SPLAT_A64, LOAD64_SPLAT_A64_S }, |
| 10218 | { LOAD8_SPLAT_A32, LOAD8_SPLAT_A32_S }, |
| 10219 | { LOAD8_SPLAT_A64, LOAD8_SPLAT_A64_S }, |
| 10220 | { LOAD8_S_I32_A32, LOAD8_S_I32_A32_S }, |
| 10221 | { LOAD8_S_I32_A64, LOAD8_S_I32_A64_S }, |
| 10222 | { LOAD8_S_I64_A32, LOAD8_S_I64_A32_S }, |
| 10223 | { LOAD8_S_I64_A64, LOAD8_S_I64_A64_S }, |
| 10224 | { LOAD8_U_I32_A32, LOAD8_U_I32_A32_S }, |
| 10225 | { LOAD8_U_I32_A64, LOAD8_U_I32_A64_S }, |
| 10226 | { LOAD8_U_I64_A32, LOAD8_U_I64_A32_S }, |
| 10227 | { LOAD8_U_I64_A64, LOAD8_U_I64_A64_S }, |
| 10228 | { LOAD_EXTEND_S_I16x8_A32, LOAD_EXTEND_S_I16x8_A32_S }, |
| 10229 | { LOAD_EXTEND_S_I16x8_A64, LOAD_EXTEND_S_I16x8_A64_S }, |
| 10230 | { LOAD_EXTEND_S_I32x4_A32, LOAD_EXTEND_S_I32x4_A32_S }, |
| 10231 | { LOAD_EXTEND_S_I32x4_A64, LOAD_EXTEND_S_I32x4_A64_S }, |
| 10232 | { LOAD_EXTEND_S_I64x2_A32, LOAD_EXTEND_S_I64x2_A32_S }, |
| 10233 | { LOAD_EXTEND_S_I64x2_A64, LOAD_EXTEND_S_I64x2_A64_S }, |
| 10234 | { LOAD_EXTEND_U_I16x8_A32, LOAD_EXTEND_U_I16x8_A32_S }, |
| 10235 | { LOAD_EXTEND_U_I16x8_A64, LOAD_EXTEND_U_I16x8_A64_S }, |
| 10236 | { LOAD_EXTEND_U_I32x4_A32, LOAD_EXTEND_U_I32x4_A32_S }, |
| 10237 | { LOAD_EXTEND_U_I32x4_A64, LOAD_EXTEND_U_I32x4_A64_S }, |
| 10238 | { LOAD_EXTEND_U_I64x2_A32, LOAD_EXTEND_U_I64x2_A32_S }, |
| 10239 | { LOAD_EXTEND_U_I64x2_A64, LOAD_EXTEND_U_I64x2_A64_S }, |
| 10240 | { LOAD_F16_F32_A32, LOAD_F16_F32_A32_S }, |
| 10241 | { LOAD_F16_F32_A64, LOAD_F16_F32_A64_S }, |
| 10242 | { LOAD_F32_A32, LOAD_F32_A32_S }, |
| 10243 | { LOAD_F32_A64, LOAD_F32_A64_S }, |
| 10244 | { LOAD_F64_A32, LOAD_F64_A32_S }, |
| 10245 | { LOAD_F64_A64, LOAD_F64_A64_S }, |
| 10246 | { LOAD_I32_A32, LOAD_I32_A32_S }, |
| 10247 | { LOAD_I32_A64, LOAD_I32_A64_S }, |
| 10248 | { LOAD_I64_A32, LOAD_I64_A32_S }, |
| 10249 | { LOAD_I64_A64, LOAD_I64_A64_S }, |
| 10250 | { LOAD_LANE_16_A32, LOAD_LANE_16_A32_S }, |
| 10251 | { LOAD_LANE_16_A64, LOAD_LANE_16_A64_S }, |
| 10252 | { LOAD_LANE_32_A32, LOAD_LANE_32_A32_S }, |
| 10253 | { LOAD_LANE_32_A64, LOAD_LANE_32_A64_S }, |
| 10254 | { LOAD_LANE_64_A32, LOAD_LANE_64_A32_S }, |
| 10255 | { LOAD_LANE_64_A64, LOAD_LANE_64_A64_S }, |
| 10256 | { LOAD_LANE_8_A32, LOAD_LANE_8_A32_S }, |
| 10257 | { LOAD_LANE_8_A64, LOAD_LANE_8_A64_S }, |
| 10258 | { LOAD_V128_A32, LOAD_V128_A32_S }, |
| 10259 | { LOAD_V128_A64, LOAD_V128_A64_S }, |
| 10260 | { LOAD_ZERO_32_A32, LOAD_ZERO_32_A32_S }, |
| 10261 | { LOAD_ZERO_32_A64, LOAD_ZERO_32_A64_S }, |
| 10262 | { LOAD_ZERO_64_A32, LOAD_ZERO_64_A32_S }, |
| 10263 | { LOAD_ZERO_64_A64, LOAD_ZERO_64_A64_S }, |
| 10264 | { LOCAL_GET_EXNREF, LOCAL_GET_EXNREF_S }, |
| 10265 | { LOCAL_GET_EXTERNREF, LOCAL_GET_EXTERNREF_S }, |
| 10266 | { LOCAL_GET_F32, LOCAL_GET_F32_S }, |
| 10267 | { LOCAL_GET_F64, LOCAL_GET_F64_S }, |
| 10268 | { LOCAL_GET_FUNCREF, LOCAL_GET_FUNCREF_S }, |
| 10269 | { LOCAL_GET_I32, LOCAL_GET_I32_S }, |
| 10270 | { LOCAL_GET_I64, LOCAL_GET_I64_S }, |
| 10271 | { LOCAL_GET_V128, LOCAL_GET_V128_S }, |
| 10272 | { LOCAL_SET_EXNREF, LOCAL_SET_EXNREF_S }, |
| 10273 | { LOCAL_SET_EXTERNREF, LOCAL_SET_EXTERNREF_S }, |
| 10274 | { LOCAL_SET_F32, LOCAL_SET_F32_S }, |
| 10275 | { LOCAL_SET_F64, LOCAL_SET_F64_S }, |
| 10276 | { LOCAL_SET_FUNCREF, LOCAL_SET_FUNCREF_S }, |
| 10277 | { LOCAL_SET_I32, LOCAL_SET_I32_S }, |
| 10278 | { LOCAL_SET_I64, LOCAL_SET_I64_S }, |
| 10279 | { LOCAL_SET_V128, LOCAL_SET_V128_S }, |
| 10280 | { LOCAL_TEE_EXNREF, LOCAL_TEE_EXNREF_S }, |
| 10281 | { LOCAL_TEE_EXTERNREF, LOCAL_TEE_EXTERNREF_S }, |
| 10282 | { LOCAL_TEE_F32, LOCAL_TEE_F32_S }, |
| 10283 | { LOCAL_TEE_F64, LOCAL_TEE_F64_S }, |
| 10284 | { LOCAL_TEE_FUNCREF, LOCAL_TEE_FUNCREF_S }, |
| 10285 | { LOCAL_TEE_I32, LOCAL_TEE_I32_S }, |
| 10286 | { LOCAL_TEE_I64, LOCAL_TEE_I64_S }, |
| 10287 | { LOCAL_TEE_V128, LOCAL_TEE_V128_S }, |
| 10288 | { LOOP, LOOP_S }, |
| 10289 | { LT_F16x8, LT_F16x8_S }, |
| 10290 | { LT_F32, LT_F32_S }, |
| 10291 | { LT_F32x4, LT_F32x4_S }, |
| 10292 | { LT_F64, LT_F64_S }, |
| 10293 | { LT_F64x2, LT_F64x2_S }, |
| 10294 | { LT_S_I16x8, LT_S_I16x8_S }, |
| 10295 | { LT_S_I32, LT_S_I32_S }, |
| 10296 | { LT_S_I32x4, LT_S_I32x4_S }, |
| 10297 | { LT_S_I64, LT_S_I64_S }, |
| 10298 | { LT_S_I64x2, LT_S_I64x2_S }, |
| 10299 | { LT_S_I8x16, LT_S_I8x16_S }, |
| 10300 | { LT_U_I16x8, LT_U_I16x8_S }, |
| 10301 | { LT_U_I32, LT_U_I32_S }, |
| 10302 | { LT_U_I32x4, LT_U_I32x4_S }, |
| 10303 | { LT_U_I64, LT_U_I64_S }, |
| 10304 | { LT_U_I8x16, LT_U_I8x16_S }, |
| 10305 | { MADD_F16x8, MADD_F16x8_S }, |
| 10306 | { MADD_F32x4, MADD_F32x4_S }, |
| 10307 | { MADD_F64x2, MADD_F64x2_S }, |
| 10308 | { MAX_F16x8, MAX_F16x8_S }, |
| 10309 | { MAX_F32, MAX_F32_S }, |
| 10310 | { MAX_F32x4, MAX_F32x4_S }, |
| 10311 | { MAX_F64, MAX_F64_S }, |
| 10312 | { MAX_F64x2, MAX_F64x2_S }, |
| 10313 | { MAX_S_I16x8, MAX_S_I16x8_S }, |
| 10314 | { MAX_S_I32x4, MAX_S_I32x4_S }, |
| 10315 | { MAX_S_I8x16, MAX_S_I8x16_S }, |
| 10316 | { MAX_U_I16x8, MAX_U_I16x8_S }, |
| 10317 | { MAX_U_I32x4, MAX_U_I32x4_S }, |
| 10318 | { MAX_U_I8x16, MAX_U_I8x16_S }, |
| 10319 | { MEMCPY_A32, MEMCPY_A32_S }, |
| 10320 | { MEMCPY_A64, MEMCPY_A64_S }, |
| 10321 | { MEMORY_ATOMIC_NOTIFY_A32, MEMORY_ATOMIC_NOTIFY_A32_S }, |
| 10322 | { MEMORY_ATOMIC_NOTIFY_A64, MEMORY_ATOMIC_NOTIFY_A64_S }, |
| 10323 | { MEMORY_ATOMIC_WAIT32_A32, MEMORY_ATOMIC_WAIT32_A32_S }, |
| 10324 | { MEMORY_ATOMIC_WAIT32_A64, MEMORY_ATOMIC_WAIT32_A64_S }, |
| 10325 | { MEMORY_ATOMIC_WAIT64_A32, MEMORY_ATOMIC_WAIT64_A32_S }, |
| 10326 | { MEMORY_ATOMIC_WAIT64_A64, MEMORY_ATOMIC_WAIT64_A64_S }, |
| 10327 | { MEMORY_COPY_A32, MEMORY_COPY_A32_S }, |
| 10328 | { MEMORY_COPY_A64, MEMORY_COPY_A64_S }, |
| 10329 | { MEMORY_FILL_A32, MEMORY_FILL_A32_S }, |
| 10330 | { MEMORY_FILL_A64, MEMORY_FILL_A64_S }, |
| 10331 | { MEMORY_INIT_A32, MEMORY_INIT_A32_S }, |
| 10332 | { MEMORY_INIT_A64, MEMORY_INIT_A64_S }, |
| 10333 | { MEMSET_A32, MEMSET_A32_S }, |
| 10334 | { MEMSET_A64, MEMSET_A64_S }, |
| 10335 | { MIN_F16x8, MIN_F16x8_S }, |
| 10336 | { MIN_F32, MIN_F32_S }, |
| 10337 | { MIN_F32x4, MIN_F32x4_S }, |
| 10338 | { MIN_F64, MIN_F64_S }, |
| 10339 | { MIN_F64x2, MIN_F64x2_S }, |
| 10340 | { MIN_S_I16x8, MIN_S_I16x8_S }, |
| 10341 | { MIN_S_I32x4, MIN_S_I32x4_S }, |
| 10342 | { MIN_S_I8x16, MIN_S_I8x16_S }, |
| 10343 | { MIN_U_I16x8, MIN_U_I16x8_S }, |
| 10344 | { MIN_U_I32x4, MIN_U_I32x4_S }, |
| 10345 | { MIN_U_I8x16, MIN_U_I8x16_S }, |
| 10346 | { MUL_F16x8, MUL_F16x8_S }, |
| 10347 | { MUL_F32, MUL_F32_S }, |
| 10348 | { MUL_F32x4, MUL_F32x4_S }, |
| 10349 | { MUL_F64, MUL_F64_S }, |
| 10350 | { MUL_F64x2, MUL_F64x2_S }, |
| 10351 | { MUL_I16x8, MUL_I16x8_S }, |
| 10352 | { MUL_I32, MUL_I32_S }, |
| 10353 | { MUL_I32x4, MUL_I32x4_S }, |
| 10354 | { MUL_I64, MUL_I64_S }, |
| 10355 | { MUL_I64x2, MUL_I64x2_S }, |
| 10356 | { NARROW_S_I16x8, NARROW_S_I16x8_S }, |
| 10357 | { NARROW_S_I8x16, NARROW_S_I8x16_S }, |
| 10358 | { NARROW_U_I16x8, NARROW_U_I16x8_S }, |
| 10359 | { NARROW_U_I8x16, NARROW_U_I8x16_S }, |
| 10360 | { NEAREST_F16x8, NEAREST_F16x8_S }, |
| 10361 | { NEAREST_F32, NEAREST_F32_S }, |
| 10362 | { NEAREST_F32x4, NEAREST_F32x4_S }, |
| 10363 | { NEAREST_F64, NEAREST_F64_S }, |
| 10364 | { NEAREST_F64x2, NEAREST_F64x2_S }, |
| 10365 | { NEG_F16x8, NEG_F16x8_S }, |
| 10366 | { NEG_F32, NEG_F32_S }, |
| 10367 | { NEG_F32x4, NEG_F32x4_S }, |
| 10368 | { NEG_F64, NEG_F64_S }, |
| 10369 | { NEG_F64x2, NEG_F64x2_S }, |
| 10370 | { NEG_I16x8, NEG_I16x8_S }, |
| 10371 | { NEG_I32x4, NEG_I32x4_S }, |
| 10372 | { NEG_I64x2, NEG_I64x2_S }, |
| 10373 | { NEG_I8x16, NEG_I8x16_S }, |
| 10374 | { NE_F16x8, NE_F16x8_S }, |
| 10375 | { NE_F32, NE_F32_S }, |
| 10376 | { NE_F32x4, NE_F32x4_S }, |
| 10377 | { NE_F64, NE_F64_S }, |
| 10378 | { NE_F64x2, NE_F64x2_S }, |
| 10379 | { NE_I16x8, NE_I16x8_S }, |
| 10380 | { NE_I32, NE_I32_S }, |
| 10381 | { NE_I32x4, NE_I32x4_S }, |
| 10382 | { NE_I64, NE_I64_S }, |
| 10383 | { NE_I64x2, NE_I64x2_S }, |
| 10384 | { NE_I8x16, NE_I8x16_S }, |
| 10385 | { NMADD_F16x8, NMADD_F16x8_S }, |
| 10386 | { NMADD_F32x4, NMADD_F32x4_S }, |
| 10387 | { NMADD_F64x2, NMADD_F64x2_S }, |
| 10388 | { NOP, NOP_S }, |
| 10389 | { NOT, NOT_S }, |
| 10390 | { OR, OR_S }, |
| 10391 | { OR_I32, OR_I32_S }, |
| 10392 | { OR_I64, OR_I64_S }, |
| 10393 | { PMAX_F16x8, PMAX_F16x8_S }, |
| 10394 | { PMAX_F32x4, PMAX_F32x4_S }, |
| 10395 | { PMAX_F64x2, PMAX_F64x2_S }, |
| 10396 | { PMIN_F16x8, PMIN_F16x8_S }, |
| 10397 | { PMIN_F32x4, PMIN_F32x4_S }, |
| 10398 | { PMIN_F64x2, PMIN_F64x2_S }, |
| 10399 | { POPCNT_I32, POPCNT_I32_S }, |
| 10400 | { POPCNT_I64, POPCNT_I64_S }, |
| 10401 | { POPCNT_I8x16, POPCNT_I8x16_S }, |
| 10402 | { Q15MULR_SAT_S_I16x8, Q15MULR_SAT_S_I16x8_S }, |
| 10403 | { REF_CAST_FUNCREF, REF_CAST_FUNCREF_S }, |
| 10404 | { REF_FUNC, REF_FUNC_S }, |
| 10405 | { REF_IS_NULL_EXNREF, REF_IS_NULL_EXNREF_S }, |
| 10406 | { REF_IS_NULL_EXTERNREF, REF_IS_NULL_EXTERNREF_S }, |
| 10407 | { REF_IS_NULL_FUNCREF, REF_IS_NULL_FUNCREF_S }, |
| 10408 | { REF_NULL_EXNREF, REF_NULL_EXNREF_S }, |
| 10409 | { REF_NULL_EXTERNREF, REF_NULL_EXTERNREF_S }, |
| 10410 | { REF_NULL_FUNCREF, REF_NULL_FUNCREF_S }, |
| 10411 | { REF_TEST_FUNCREF, REF_TEST_FUNCREF_S }, |
| 10412 | { RELAXED_DOT, RELAXED_DOT_S }, |
| 10413 | { RELAXED_DOT_ADD, RELAXED_DOT_ADD_S }, |
| 10414 | { RELAXED_DOT_BFLOAT, RELAXED_DOT_BFLOAT_S }, |
| 10415 | { RELAXED_Q15MULR_S_I16x8, RELAXED_Q15MULR_S_I16x8_S }, |
| 10416 | { RELAXED_SWIZZLE, RELAXED_SWIZZLE_S }, |
| 10417 | { REM_S_I32, REM_S_I32_S }, |
| 10418 | { REM_S_I64, REM_S_I64_S }, |
| 10419 | { REM_U_I32, REM_U_I32_S }, |
| 10420 | { REM_U_I64, REM_U_I64_S }, |
| 10421 | { REPLACE_LANE_F16x8, REPLACE_LANE_F16x8_S }, |
| 10422 | { REPLACE_LANE_F32x4, REPLACE_LANE_F32x4_S }, |
| 10423 | { REPLACE_LANE_F64x2, REPLACE_LANE_F64x2_S }, |
| 10424 | { REPLACE_LANE_I16x8, REPLACE_LANE_I16x8_S }, |
| 10425 | { REPLACE_LANE_I32x4, REPLACE_LANE_I32x4_S }, |
| 10426 | { REPLACE_LANE_I64x2, REPLACE_LANE_I64x2_S }, |
| 10427 | { REPLACE_LANE_I8x16, REPLACE_LANE_I8x16_S }, |
| 10428 | { RETHROW, RETHROW_S }, |
| 10429 | { RETURN, RETURN_S }, |
| 10430 | { RET_CALL, RET_CALL_S }, |
| 10431 | { RET_CALL_INDIRECT, RET_CALL_INDIRECT_S }, |
| 10432 | { RET_CALL_REF, RET_CALL_REF_S }, |
| 10433 | { ROTL_I32, ROTL_I32_S }, |
| 10434 | { ROTL_I64, ROTL_I64_S }, |
| 10435 | { ROTR_I32, ROTR_I32_S }, |
| 10436 | { ROTR_I64, ROTR_I64_S }, |
| 10437 | { SELECT_EXNREF, SELECT_EXNREF_S }, |
| 10438 | { SELECT_EXTERNREF, SELECT_EXTERNREF_S }, |
| 10439 | { SELECT_F32, SELECT_F32_S }, |
| 10440 | { SELECT_F64, SELECT_F64_S }, |
| 10441 | { SELECT_FUNCREF, SELECT_FUNCREF_S }, |
| 10442 | { SELECT_I32, SELECT_I32_S }, |
| 10443 | { SELECT_I64, SELECT_I64_S }, |
| 10444 | { SELECT_T, SELECT_T_S }, |
| 10445 | { SELECT_V128, SELECT_V128_S }, |
| 10446 | { SHL_I16x8, SHL_I16x8_S }, |
| 10447 | { SHL_I32, SHL_I32_S }, |
| 10448 | { SHL_I32x4, SHL_I32x4_S }, |
| 10449 | { SHL_I64, SHL_I64_S }, |
| 10450 | { SHL_I64x2, SHL_I64x2_S }, |
| 10451 | { SHL_I8x16, SHL_I8x16_S }, |
| 10452 | { SHR_S_I16x8, SHR_S_I16x8_S }, |
| 10453 | { SHR_S_I32, SHR_S_I32_S }, |
| 10454 | { SHR_S_I32x4, SHR_S_I32x4_S }, |
| 10455 | { SHR_S_I64, SHR_S_I64_S }, |
| 10456 | { SHR_S_I64x2, SHR_S_I64x2_S }, |
| 10457 | { SHR_S_I8x16, SHR_S_I8x16_S }, |
| 10458 | { SHR_U_I16x8, SHR_U_I16x8_S }, |
| 10459 | { SHR_U_I32, SHR_U_I32_S }, |
| 10460 | { SHR_U_I32x4, SHR_U_I32x4_S }, |
| 10461 | { SHR_U_I64, SHR_U_I64_S }, |
| 10462 | { SHR_U_I64x2, SHR_U_I64x2_S }, |
| 10463 | { SHR_U_I8x16, SHR_U_I8x16_S }, |
| 10464 | { SHUFFLE, SHUFFLE_S }, |
| 10465 | { SIMD_RELAXED_FMAX_F32x4, SIMD_RELAXED_FMAX_F32x4_S }, |
| 10466 | { SIMD_RELAXED_FMAX_F64x2, SIMD_RELAXED_FMAX_F64x2_S }, |
| 10467 | { SIMD_RELAXED_FMIN_F32x4, SIMD_RELAXED_FMIN_F32x4_S }, |
| 10468 | { SIMD_RELAXED_FMIN_F64x2, SIMD_RELAXED_FMIN_F64x2_S }, |
| 10469 | { SPLAT_F16x8, SPLAT_F16x8_S }, |
| 10470 | { SPLAT_F32x4, SPLAT_F32x4_S }, |
| 10471 | { SPLAT_F64x2, SPLAT_F64x2_S }, |
| 10472 | { SPLAT_I16x8, SPLAT_I16x8_S }, |
| 10473 | { SPLAT_I32x4, SPLAT_I32x4_S }, |
| 10474 | { SPLAT_I64x2, SPLAT_I64x2_S }, |
| 10475 | { SPLAT_I8x16, SPLAT_I8x16_S }, |
| 10476 | { SQRT_F16x8, SQRT_F16x8_S }, |
| 10477 | { SQRT_F32, SQRT_F32_S }, |
| 10478 | { SQRT_F32x4, SQRT_F32x4_S }, |
| 10479 | { SQRT_F64, SQRT_F64_S }, |
| 10480 | { SQRT_F64x2, SQRT_F64x2_S }, |
| 10481 | { STORE16_I32_A32, STORE16_I32_A32_S }, |
| 10482 | { STORE16_I32_A64, STORE16_I32_A64_S }, |
| 10483 | { STORE16_I64_A32, STORE16_I64_A32_S }, |
| 10484 | { STORE16_I64_A64, STORE16_I64_A64_S }, |
| 10485 | { STORE32_I64_A32, STORE32_I64_A32_S }, |
| 10486 | { STORE32_I64_A64, STORE32_I64_A64_S }, |
| 10487 | { STORE8_I32_A32, STORE8_I32_A32_S }, |
| 10488 | { STORE8_I32_A64, STORE8_I32_A64_S }, |
| 10489 | { STORE8_I64_A32, STORE8_I64_A32_S }, |
| 10490 | { STORE8_I64_A64, STORE8_I64_A64_S }, |
| 10491 | { STORE_F16_F32_A32, STORE_F16_F32_A32_S }, |
| 10492 | { STORE_F16_F32_A64, STORE_F16_F32_A64_S }, |
| 10493 | { STORE_F32_A32, STORE_F32_A32_S }, |
| 10494 | { STORE_F32_A64, STORE_F32_A64_S }, |
| 10495 | { STORE_F64_A32, STORE_F64_A32_S }, |
| 10496 | { STORE_F64_A64, STORE_F64_A64_S }, |
| 10497 | { STORE_I32_A32, STORE_I32_A32_S }, |
| 10498 | { STORE_I32_A64, STORE_I32_A64_S }, |
| 10499 | { STORE_I64_A32, STORE_I64_A32_S }, |
| 10500 | { STORE_I64_A64, STORE_I64_A64_S }, |
| 10501 | { STORE_LANE_I16x8_A32, STORE_LANE_I16x8_A32_S }, |
| 10502 | { STORE_LANE_I16x8_A64, STORE_LANE_I16x8_A64_S }, |
| 10503 | { STORE_LANE_I32x4_A32, STORE_LANE_I32x4_A32_S }, |
| 10504 | { STORE_LANE_I32x4_A64, STORE_LANE_I32x4_A64_S }, |
| 10505 | { STORE_LANE_I64x2_A32, STORE_LANE_I64x2_A32_S }, |
| 10506 | { STORE_LANE_I64x2_A64, STORE_LANE_I64x2_A64_S }, |
| 10507 | { STORE_LANE_I8x16_A32, STORE_LANE_I8x16_A32_S }, |
| 10508 | { STORE_LANE_I8x16_A64, STORE_LANE_I8x16_A64_S }, |
| 10509 | { STORE_V128_A32, STORE_V128_A32_S }, |
| 10510 | { STORE_V128_A64, STORE_V128_A64_S }, |
| 10511 | { SUB_F16x8, SUB_F16x8_S }, |
| 10512 | { SUB_F32, SUB_F32_S }, |
| 10513 | { SUB_F32x4, SUB_F32x4_S }, |
| 10514 | { SUB_F64, SUB_F64_S }, |
| 10515 | { SUB_F64x2, SUB_F64x2_S }, |
| 10516 | { SUB_I16x8, SUB_I16x8_S }, |
| 10517 | { SUB_I32, SUB_I32_S }, |
| 10518 | { SUB_I32x4, SUB_I32x4_S }, |
| 10519 | { SUB_I64, SUB_I64_S }, |
| 10520 | { SUB_I64x2, SUB_I64x2_S }, |
| 10521 | { SUB_I8x16, SUB_I8x16_S }, |
| 10522 | { SUB_SAT_S_I16x8, SUB_SAT_S_I16x8_S }, |
| 10523 | { SUB_SAT_S_I8x16, SUB_SAT_S_I8x16_S }, |
| 10524 | { SUB_SAT_U_I16x8, SUB_SAT_U_I16x8_S }, |
| 10525 | { SUB_SAT_U_I8x16, SUB_SAT_U_I8x16_S }, |
| 10526 | { SWIZZLE, SWIZZLE_S }, |
| 10527 | { TABLE_COPY, TABLE_COPY_S }, |
| 10528 | { TABLE_FILL_EXNREF, TABLE_FILL_EXNREF_S }, |
| 10529 | { TABLE_FILL_EXTERNREF, TABLE_FILL_EXTERNREF_S }, |
| 10530 | { TABLE_FILL_FUNCREF, TABLE_FILL_FUNCREF_S }, |
| 10531 | { TABLE_GET_EXNREF, TABLE_GET_EXNREF_S }, |
| 10532 | { TABLE_GET_EXTERNREF, TABLE_GET_EXTERNREF_S }, |
| 10533 | { TABLE_GET_FUNCREF, TABLE_GET_FUNCREF_S }, |
| 10534 | { TABLE_GROW_EXNREF, TABLE_GROW_EXNREF_S }, |
| 10535 | { TABLE_GROW_EXTERNREF, TABLE_GROW_EXTERNREF_S }, |
| 10536 | { TABLE_GROW_FUNCREF, TABLE_GROW_FUNCREF_S }, |
| 10537 | { TABLE_SET_EXNREF, TABLE_SET_EXNREF_S }, |
| 10538 | { TABLE_SET_EXTERNREF, TABLE_SET_EXTERNREF_S }, |
| 10539 | { TABLE_SET_FUNCREF, TABLE_SET_FUNCREF_S }, |
| 10540 | { TABLE_SIZE, TABLE_SIZE_S }, |
| 10541 | { TEE_EXNREF, TEE_EXNREF_S }, |
| 10542 | { TEE_EXTERNREF, TEE_EXTERNREF_S }, |
| 10543 | { TEE_F32, TEE_F32_S }, |
| 10544 | { TEE_F64, TEE_F64_S }, |
| 10545 | { TEE_FUNCREF, TEE_FUNCREF_S }, |
| 10546 | { TEE_I32, TEE_I32_S }, |
| 10547 | { TEE_I64, TEE_I64_S }, |
| 10548 | { TEE_V128, TEE_V128_S }, |
| 10549 | { THROW, THROW_S }, |
| 10550 | { THROW_REF, THROW_REF_S }, |
| 10551 | { TRUNC_F16x8, TRUNC_F16x8_S }, |
| 10552 | { TRUNC_F32, TRUNC_F32_S }, |
| 10553 | { TRUNC_F32x4, TRUNC_F32x4_S }, |
| 10554 | { TRUNC_F64, TRUNC_F64_S }, |
| 10555 | { TRUNC_F64x2, TRUNC_F64x2_S }, |
| 10556 | { TRY, TRY_S }, |
| 10557 | { TRY_TABLE, TRY_TABLE_S }, |
| 10558 | { UNREACHABLE, UNREACHABLE_S }, |
| 10559 | { XOR, XOR_S }, |
| 10560 | { XOR_I32, XOR_I32_S }, |
| 10561 | { XOR_I64, XOR_I64_S }, |
| 10562 | { anonymous_14864MEMORY_GROW_A32, anonymous_14864MEMORY_GROW_A32_S }, |
| 10563 | { anonymous_14864MEMORY_SIZE_A32, anonymous_14864MEMORY_SIZE_A32_S }, |
| 10564 | { anonymous_14865MEMORY_GROW_A64, anonymous_14865MEMORY_GROW_A64_S }, |
| 10565 | { anonymous_14865MEMORY_SIZE_A64, anonymous_14865MEMORY_SIZE_A64_S }, |
| 10566 | { convert_low_s_F64x2, convert_low_s_F64x2_S }, |
| 10567 | { convert_low_u_F64x2, convert_low_u_F64x2_S }, |
| 10568 | { demote_zero_F16x8, demote_zero_F16x8_S }, |
| 10569 | { demote_zero_F32x4, demote_zero_F32x4_S }, |
| 10570 | { extadd_pairwise_s_I16x8, extadd_pairwise_s_I16x8_S }, |
| 10571 | { extadd_pairwise_s_I32x4, extadd_pairwise_s_I32x4_S }, |
| 10572 | { extadd_pairwise_u_I16x8, extadd_pairwise_u_I16x8_S }, |
| 10573 | { extadd_pairwise_u_I32x4, extadd_pairwise_u_I32x4_S }, |
| 10574 | { extend_high_s_I16x8, extend_high_s_I16x8_S }, |
| 10575 | { extend_high_s_I32x4, extend_high_s_I32x4_S }, |
| 10576 | { extend_high_s_I64x2, extend_high_s_I64x2_S }, |
| 10577 | { extend_high_u_I16x8, extend_high_u_I16x8_S }, |
| 10578 | { extend_high_u_I32x4, extend_high_u_I32x4_S }, |
| 10579 | { extend_high_u_I64x2, extend_high_u_I64x2_S }, |
| 10580 | { extend_low_s_I16x8, extend_low_s_I16x8_S }, |
| 10581 | { extend_low_s_I32x4, extend_low_s_I32x4_S }, |
| 10582 | { extend_low_s_I64x2, extend_low_s_I64x2_S }, |
| 10583 | { extend_low_u_I16x8, extend_low_u_I16x8_S }, |
| 10584 | { extend_low_u_I32x4, extend_low_u_I32x4_S }, |
| 10585 | { extend_low_u_I64x2, extend_low_u_I64x2_S }, |
| 10586 | { fp_to_sint_I16x8, fp_to_sint_I16x8_S }, |
| 10587 | { fp_to_sint_I32x4, fp_to_sint_I32x4_S }, |
| 10588 | { fp_to_uint_I16x8, fp_to_uint_I16x8_S }, |
| 10589 | { fp_to_uint_I32x4, fp_to_uint_I32x4_S }, |
| 10590 | { int_wasm_relaxed_trunc_signed_I32x4, int_wasm_relaxed_trunc_signed_I32x4_S }, |
| 10591 | { int_wasm_relaxed_trunc_signed_zero_I32x4, int_wasm_relaxed_trunc_signed_zero_I32x4_S }, |
| 10592 | { int_wasm_relaxed_trunc_unsigned_I32x4, int_wasm_relaxed_trunc_unsigned_I32x4_S }, |
| 10593 | { int_wasm_relaxed_trunc_unsigned_zero_I32x4, int_wasm_relaxed_trunc_unsigned_zero_I32x4_S }, |
| 10594 | { promote_low_F32x4, promote_low_F32x4_S }, |
| 10595 | { promote_low_F64x2, promote_low_F64x2_S }, |
| 10596 | { sint_to_fp_F16x8, sint_to_fp_F16x8_S }, |
| 10597 | { sint_to_fp_F32x4, sint_to_fp_F32x4_S }, |
| 10598 | { trunc_sat_zero_s_I32x4, trunc_sat_zero_s_I32x4_S }, |
| 10599 | { trunc_sat_zero_u_I32x4, trunc_sat_zero_u_I32x4_S }, |
| 10600 | { uint_to_fp_F16x8, uint_to_fp_F16x8_S }, |
| 10601 | { uint_to_fp_F32x4, uint_to_fp_F32x4_S }, |
| 10602 | }; // End of Table |
| 10603 | |
| 10604 | unsigned mid; |
| 10605 | unsigned start = 0; |
| 10606 | unsigned end = 824; |
| 10607 | while (start < end) { |
| 10608 | mid = start + (end - start) / 2; |
| 10609 | if (Opcode == Table[mid][0]) |
| 10610 | break; |
| 10611 | if (Opcode < Table[mid][0]) |
| 10612 | end = mid; |
| 10613 | else |
| 10614 | start = mid + 1; |
| 10615 | } |
| 10616 | if (start == end) |
| 10617 | return -1; // Instruction doesn't exist in this table. |
| 10618 | |
| 10619 | return Table[mid][1]; |
| 10620 | } |
| 10621 | |
| 10622 | // getWasm64Opcode |
| 10623 | LLVM_READONLY |
| 10624 | int32_t getWasm64Opcode(uint32_t Opcode) { |
| 10625 | using namespace WebAssembly; |
| 10626 | static constexpr uint32_t Table[][2] = { |
| 10627 | { ATOMIC_LOAD16_U_I32_A32, ATOMIC_LOAD16_U_I32_A64 }, |
| 10628 | { ATOMIC_LOAD16_U_I32_A32_S, ATOMIC_LOAD16_U_I32_A64_S }, |
| 10629 | { ATOMIC_LOAD16_U_I64_A32, ATOMIC_LOAD16_U_I64_A64 }, |
| 10630 | { ATOMIC_LOAD16_U_I64_A32_S, ATOMIC_LOAD16_U_I64_A64_S }, |
| 10631 | { ATOMIC_LOAD32_U_I64_A32, ATOMIC_LOAD32_U_I64_A64 }, |
| 10632 | { ATOMIC_LOAD32_U_I64_A32_S, ATOMIC_LOAD32_U_I64_A64_S }, |
| 10633 | { ATOMIC_LOAD8_U_I32_A32, ATOMIC_LOAD8_U_I32_A64 }, |
| 10634 | { ATOMIC_LOAD8_U_I32_A32_S, ATOMIC_LOAD8_U_I32_A64_S }, |
| 10635 | { ATOMIC_LOAD8_U_I64_A32, ATOMIC_LOAD8_U_I64_A64 }, |
| 10636 | { ATOMIC_LOAD8_U_I64_A32_S, ATOMIC_LOAD8_U_I64_A64_S }, |
| 10637 | { ATOMIC_LOAD_I32_A32, ATOMIC_LOAD_I32_A64 }, |
| 10638 | { ATOMIC_LOAD_I32_A32_S, ATOMIC_LOAD_I32_A64_S }, |
| 10639 | { ATOMIC_LOAD_I64_A32, ATOMIC_LOAD_I64_A64 }, |
| 10640 | { ATOMIC_LOAD_I64_A32_S, ATOMIC_LOAD_I64_A64_S }, |
| 10641 | { ATOMIC_RMW16_U_ADD_I32_A32, ATOMIC_RMW16_U_ADD_I32_A64 }, |
| 10642 | { ATOMIC_RMW16_U_ADD_I32_A32_S, ATOMIC_RMW16_U_ADD_I32_A64_S }, |
| 10643 | { ATOMIC_RMW16_U_ADD_I64_A32, ATOMIC_RMW16_U_ADD_I64_A64 }, |
| 10644 | { ATOMIC_RMW16_U_ADD_I64_A32_S, ATOMIC_RMW16_U_ADD_I64_A64_S }, |
| 10645 | { ATOMIC_RMW16_U_AND_I32_A32, ATOMIC_RMW16_U_AND_I32_A64 }, |
| 10646 | { ATOMIC_RMW16_U_AND_I32_A32_S, ATOMIC_RMW16_U_AND_I32_A64_S }, |
| 10647 | { ATOMIC_RMW16_U_AND_I64_A32, ATOMIC_RMW16_U_AND_I64_A64 }, |
| 10648 | { ATOMIC_RMW16_U_AND_I64_A32_S, ATOMIC_RMW16_U_AND_I64_A64_S }, |
| 10649 | { ATOMIC_RMW16_U_CMPXCHG_I32_A32, ATOMIC_RMW16_U_CMPXCHG_I32_A64 }, |
| 10650 | { ATOMIC_RMW16_U_CMPXCHG_I32_A32_S, ATOMIC_RMW16_U_CMPXCHG_I32_A64_S }, |
| 10651 | { ATOMIC_RMW16_U_CMPXCHG_I64_A32, ATOMIC_RMW16_U_CMPXCHG_I64_A64 }, |
| 10652 | { ATOMIC_RMW16_U_CMPXCHG_I64_A32_S, ATOMIC_RMW16_U_CMPXCHG_I64_A64_S }, |
| 10653 | { ATOMIC_RMW16_U_OR_I32_A32, ATOMIC_RMW16_U_OR_I32_A64 }, |
| 10654 | { ATOMIC_RMW16_U_OR_I32_A32_S, ATOMIC_RMW16_U_OR_I32_A64_S }, |
| 10655 | { ATOMIC_RMW16_U_OR_I64_A32, ATOMIC_RMW16_U_OR_I64_A64 }, |
| 10656 | { ATOMIC_RMW16_U_OR_I64_A32_S, ATOMIC_RMW16_U_OR_I64_A64_S }, |
| 10657 | { ATOMIC_RMW16_U_SUB_I32_A32, ATOMIC_RMW16_U_SUB_I32_A64 }, |
| 10658 | { ATOMIC_RMW16_U_SUB_I32_A32_S, ATOMIC_RMW16_U_SUB_I32_A64_S }, |
| 10659 | { ATOMIC_RMW16_U_SUB_I64_A32, ATOMIC_RMW16_U_SUB_I64_A64 }, |
| 10660 | { ATOMIC_RMW16_U_SUB_I64_A32_S, ATOMIC_RMW16_U_SUB_I64_A64_S }, |
| 10661 | { ATOMIC_RMW16_U_XCHG_I32_A32, ATOMIC_RMW16_U_XCHG_I32_A64 }, |
| 10662 | { ATOMIC_RMW16_U_XCHG_I32_A32_S, ATOMIC_RMW16_U_XCHG_I32_A64_S }, |
| 10663 | { ATOMIC_RMW16_U_XCHG_I64_A32, ATOMIC_RMW16_U_XCHG_I64_A64 }, |
| 10664 | { ATOMIC_RMW16_U_XCHG_I64_A32_S, ATOMIC_RMW16_U_XCHG_I64_A64_S }, |
| 10665 | { ATOMIC_RMW16_U_XOR_I32_A32, ATOMIC_RMW16_U_XOR_I32_A64 }, |
| 10666 | { ATOMIC_RMW16_U_XOR_I32_A32_S, ATOMIC_RMW16_U_XOR_I32_A64_S }, |
| 10667 | { ATOMIC_RMW16_U_XOR_I64_A32, ATOMIC_RMW16_U_XOR_I64_A64 }, |
| 10668 | { ATOMIC_RMW16_U_XOR_I64_A32_S, ATOMIC_RMW16_U_XOR_I64_A64_S }, |
| 10669 | { ATOMIC_RMW32_U_ADD_I64_A32, ATOMIC_RMW32_U_ADD_I64_A64 }, |
| 10670 | { ATOMIC_RMW32_U_ADD_I64_A32_S, ATOMIC_RMW32_U_ADD_I64_A64_S }, |
| 10671 | { ATOMIC_RMW32_U_AND_I64_A32, ATOMIC_RMW32_U_AND_I64_A64 }, |
| 10672 | { ATOMIC_RMW32_U_AND_I64_A32_S, ATOMIC_RMW32_U_AND_I64_A64_S }, |
| 10673 | { ATOMIC_RMW32_U_CMPXCHG_I64_A32, ATOMIC_RMW32_U_CMPXCHG_I64_A64 }, |
| 10674 | { ATOMIC_RMW32_U_CMPXCHG_I64_A32_S, ATOMIC_RMW32_U_CMPXCHG_I64_A64_S }, |
| 10675 | { ATOMIC_RMW32_U_OR_I64_A32, ATOMIC_RMW32_U_OR_I64_A64 }, |
| 10676 | { ATOMIC_RMW32_U_OR_I64_A32_S, ATOMIC_RMW32_U_OR_I64_A64_S }, |
| 10677 | { ATOMIC_RMW32_U_SUB_I64_A32, ATOMIC_RMW32_U_SUB_I64_A64 }, |
| 10678 | { ATOMIC_RMW32_U_SUB_I64_A32_S, ATOMIC_RMW32_U_SUB_I64_A64_S }, |
| 10679 | { ATOMIC_RMW32_U_XCHG_I64_A32, ATOMIC_RMW32_U_XCHG_I64_A64 }, |
| 10680 | { ATOMIC_RMW32_U_XCHG_I64_A32_S, ATOMIC_RMW32_U_XCHG_I64_A64_S }, |
| 10681 | { ATOMIC_RMW32_U_XOR_I64_A32, ATOMIC_RMW32_U_XOR_I64_A64 }, |
| 10682 | { ATOMIC_RMW32_U_XOR_I64_A32_S, ATOMIC_RMW32_U_XOR_I64_A64_S }, |
| 10683 | { ATOMIC_RMW8_U_ADD_I32_A32, ATOMIC_RMW8_U_ADD_I32_A64 }, |
| 10684 | { ATOMIC_RMW8_U_ADD_I32_A32_S, ATOMIC_RMW8_U_ADD_I32_A64_S }, |
| 10685 | { ATOMIC_RMW8_U_ADD_I64_A32, ATOMIC_RMW8_U_ADD_I64_A64 }, |
| 10686 | { ATOMIC_RMW8_U_ADD_I64_A32_S, ATOMIC_RMW8_U_ADD_I64_A64_S }, |
| 10687 | { ATOMIC_RMW8_U_AND_I32_A32, ATOMIC_RMW8_U_AND_I32_A64 }, |
| 10688 | { ATOMIC_RMW8_U_AND_I32_A32_S, ATOMIC_RMW8_U_AND_I32_A64_S }, |
| 10689 | { ATOMIC_RMW8_U_AND_I64_A32, ATOMIC_RMW8_U_AND_I64_A64 }, |
| 10690 | { ATOMIC_RMW8_U_AND_I64_A32_S, ATOMIC_RMW8_U_AND_I64_A64_S }, |
| 10691 | { ATOMIC_RMW8_U_CMPXCHG_I32_A32, ATOMIC_RMW8_U_CMPXCHG_I32_A64 }, |
| 10692 | { ATOMIC_RMW8_U_CMPXCHG_I32_A32_S, ATOMIC_RMW8_U_CMPXCHG_I32_A64_S }, |
| 10693 | { ATOMIC_RMW8_U_CMPXCHG_I64_A32, ATOMIC_RMW8_U_CMPXCHG_I64_A64 }, |
| 10694 | { ATOMIC_RMW8_U_CMPXCHG_I64_A32_S, ATOMIC_RMW8_U_CMPXCHG_I64_A64_S }, |
| 10695 | { ATOMIC_RMW8_U_OR_I32_A32, ATOMIC_RMW8_U_OR_I32_A64 }, |
| 10696 | { ATOMIC_RMW8_U_OR_I32_A32_S, ATOMIC_RMW8_U_OR_I32_A64_S }, |
| 10697 | { ATOMIC_RMW8_U_OR_I64_A32, ATOMIC_RMW8_U_OR_I64_A64 }, |
| 10698 | { ATOMIC_RMW8_U_OR_I64_A32_S, ATOMIC_RMW8_U_OR_I64_A64_S }, |
| 10699 | { ATOMIC_RMW8_U_SUB_I32_A32, ATOMIC_RMW8_U_SUB_I32_A64 }, |
| 10700 | { ATOMIC_RMW8_U_SUB_I32_A32_S, ATOMIC_RMW8_U_SUB_I32_A64_S }, |
| 10701 | { ATOMIC_RMW8_U_SUB_I64_A32, ATOMIC_RMW8_U_SUB_I64_A64 }, |
| 10702 | { ATOMIC_RMW8_U_SUB_I64_A32_S, ATOMIC_RMW8_U_SUB_I64_A64_S }, |
| 10703 | { ATOMIC_RMW8_U_XCHG_I32_A32, ATOMIC_RMW8_U_XCHG_I32_A64 }, |
| 10704 | { ATOMIC_RMW8_U_XCHG_I32_A32_S, ATOMIC_RMW8_U_XCHG_I32_A64_S }, |
| 10705 | { ATOMIC_RMW8_U_XCHG_I64_A32, ATOMIC_RMW8_U_XCHG_I64_A64 }, |
| 10706 | { ATOMIC_RMW8_U_XCHG_I64_A32_S, ATOMIC_RMW8_U_XCHG_I64_A64_S }, |
| 10707 | { ATOMIC_RMW8_U_XOR_I32_A32, ATOMIC_RMW8_U_XOR_I32_A64 }, |
| 10708 | { ATOMIC_RMW8_U_XOR_I32_A32_S, ATOMIC_RMW8_U_XOR_I32_A64_S }, |
| 10709 | { ATOMIC_RMW8_U_XOR_I64_A32, ATOMIC_RMW8_U_XOR_I64_A64 }, |
| 10710 | { ATOMIC_RMW8_U_XOR_I64_A32_S, ATOMIC_RMW8_U_XOR_I64_A64_S }, |
| 10711 | { ATOMIC_RMW_ADD_I32_A32, ATOMIC_RMW_ADD_I32_A64 }, |
| 10712 | { ATOMIC_RMW_ADD_I32_A32_S, ATOMIC_RMW_ADD_I32_A64_S }, |
| 10713 | { ATOMIC_RMW_ADD_I64_A32, ATOMIC_RMW_ADD_I64_A64 }, |
| 10714 | { ATOMIC_RMW_ADD_I64_A32_S, ATOMIC_RMW_ADD_I64_A64_S }, |
| 10715 | { ATOMIC_RMW_AND_I32_A32, ATOMIC_RMW_AND_I32_A64 }, |
| 10716 | { ATOMIC_RMW_AND_I32_A32_S, ATOMIC_RMW_AND_I32_A64_S }, |
| 10717 | { ATOMIC_RMW_AND_I64_A32, ATOMIC_RMW_AND_I64_A64 }, |
| 10718 | { ATOMIC_RMW_AND_I64_A32_S, ATOMIC_RMW_AND_I64_A64_S }, |
| 10719 | { ATOMIC_RMW_CMPXCHG_I32_A32, ATOMIC_RMW_CMPXCHG_I32_A64 }, |
| 10720 | { ATOMIC_RMW_CMPXCHG_I32_A32_S, ATOMIC_RMW_CMPXCHG_I32_A64_S }, |
| 10721 | { ATOMIC_RMW_CMPXCHG_I64_A32, ATOMIC_RMW_CMPXCHG_I64_A64 }, |
| 10722 | { ATOMIC_RMW_CMPXCHG_I64_A32_S, ATOMIC_RMW_CMPXCHG_I64_A64_S }, |
| 10723 | { ATOMIC_RMW_OR_I32_A32, ATOMIC_RMW_OR_I32_A64 }, |
| 10724 | { ATOMIC_RMW_OR_I32_A32_S, ATOMIC_RMW_OR_I32_A64_S }, |
| 10725 | { ATOMIC_RMW_OR_I64_A32, ATOMIC_RMW_OR_I64_A64 }, |
| 10726 | { ATOMIC_RMW_OR_I64_A32_S, ATOMIC_RMW_OR_I64_A64_S }, |
| 10727 | { ATOMIC_RMW_SUB_I32_A32, ATOMIC_RMW_SUB_I32_A64 }, |
| 10728 | { ATOMIC_RMW_SUB_I32_A32_S, ATOMIC_RMW_SUB_I32_A64_S }, |
| 10729 | { ATOMIC_RMW_SUB_I64_A32, ATOMIC_RMW_SUB_I64_A64 }, |
| 10730 | { ATOMIC_RMW_SUB_I64_A32_S, ATOMIC_RMW_SUB_I64_A64_S }, |
| 10731 | { ATOMIC_RMW_XCHG_I32_A32, ATOMIC_RMW_XCHG_I32_A64 }, |
| 10732 | { ATOMIC_RMW_XCHG_I32_A32_S, ATOMIC_RMW_XCHG_I32_A64_S }, |
| 10733 | { ATOMIC_RMW_XCHG_I64_A32, ATOMIC_RMW_XCHG_I64_A64 }, |
| 10734 | { ATOMIC_RMW_XCHG_I64_A32_S, ATOMIC_RMW_XCHG_I64_A64_S }, |
| 10735 | { ATOMIC_RMW_XOR_I32_A32, ATOMIC_RMW_XOR_I32_A64 }, |
| 10736 | { ATOMIC_RMW_XOR_I32_A32_S, ATOMIC_RMW_XOR_I32_A64_S }, |
| 10737 | { ATOMIC_RMW_XOR_I64_A32, ATOMIC_RMW_XOR_I64_A64 }, |
| 10738 | { ATOMIC_RMW_XOR_I64_A32_S, ATOMIC_RMW_XOR_I64_A64_S }, |
| 10739 | { ATOMIC_STORE16_I32_A32, ATOMIC_STORE16_I32_A64 }, |
| 10740 | { ATOMIC_STORE16_I32_A32_S, ATOMIC_STORE16_I32_A64_S }, |
| 10741 | { ATOMIC_STORE16_I64_A32, ATOMIC_STORE16_I64_A64 }, |
| 10742 | { ATOMIC_STORE16_I64_A32_S, ATOMIC_STORE16_I64_A64_S }, |
| 10743 | { ATOMIC_STORE32_I64_A32, ATOMIC_STORE32_I64_A64 }, |
| 10744 | { ATOMIC_STORE32_I64_A32_S, ATOMIC_STORE32_I64_A64_S }, |
| 10745 | { ATOMIC_STORE8_I32_A32, ATOMIC_STORE8_I32_A64 }, |
| 10746 | { ATOMIC_STORE8_I32_A32_S, ATOMIC_STORE8_I32_A64_S }, |
| 10747 | { ATOMIC_STORE8_I64_A32, ATOMIC_STORE8_I64_A64 }, |
| 10748 | { ATOMIC_STORE8_I64_A32_S, ATOMIC_STORE8_I64_A64_S }, |
| 10749 | { ATOMIC_STORE_I32_A32, ATOMIC_STORE_I32_A64 }, |
| 10750 | { ATOMIC_STORE_I32_A32_S, ATOMIC_STORE_I32_A64_S }, |
| 10751 | { ATOMIC_STORE_I64_A32, ATOMIC_STORE_I64_A64 }, |
| 10752 | { ATOMIC_STORE_I64_A32_S, ATOMIC_STORE_I64_A64_S }, |
| 10753 | { LOAD16_S_I32_A32, LOAD16_S_I32_A64 }, |
| 10754 | { LOAD16_S_I32_A32_S, LOAD16_S_I32_A64_S }, |
| 10755 | { LOAD16_S_I64_A32, LOAD16_S_I64_A64 }, |
| 10756 | { LOAD16_S_I64_A32_S, LOAD16_S_I64_A64_S }, |
| 10757 | { LOAD16_U_I32_A32, LOAD16_U_I32_A64 }, |
| 10758 | { LOAD16_U_I32_A32_S, LOAD16_U_I32_A64_S }, |
| 10759 | { LOAD16_U_I64_A32, LOAD16_U_I64_A64 }, |
| 10760 | { LOAD16_U_I64_A32_S, LOAD16_U_I64_A64_S }, |
| 10761 | { LOAD32_S_I64_A32, LOAD32_S_I64_A64 }, |
| 10762 | { LOAD32_S_I64_A32_S, LOAD32_S_I64_A64_S }, |
| 10763 | { LOAD32_U_I64_A32, LOAD32_U_I64_A64 }, |
| 10764 | { LOAD32_U_I64_A32_S, LOAD32_U_I64_A64_S }, |
| 10765 | { LOAD8_S_I32_A32, LOAD8_S_I32_A64 }, |
| 10766 | { LOAD8_S_I32_A32_S, LOAD8_S_I32_A64_S }, |
| 10767 | { LOAD8_S_I64_A32, LOAD8_S_I64_A64 }, |
| 10768 | { LOAD8_S_I64_A32_S, LOAD8_S_I64_A64_S }, |
| 10769 | { LOAD8_U_I32_A32, LOAD8_U_I32_A64 }, |
| 10770 | { LOAD8_U_I32_A32_S, LOAD8_U_I32_A64_S }, |
| 10771 | { LOAD8_U_I64_A32, LOAD8_U_I64_A64 }, |
| 10772 | { LOAD8_U_I64_A32_S, LOAD8_U_I64_A64_S }, |
| 10773 | { LOAD_F16_F32_A32, LOAD_F16_F32_A64 }, |
| 10774 | { LOAD_F16_F32_A32_S, LOAD_F16_F32_A64_S }, |
| 10775 | { LOAD_F32_A32, LOAD_F32_A64 }, |
| 10776 | { LOAD_F32_A32_S, LOAD_F32_A64_S }, |
| 10777 | { LOAD_F64_A32, LOAD_F64_A64 }, |
| 10778 | { LOAD_F64_A32_S, LOAD_F64_A64_S }, |
| 10779 | { LOAD_I32_A32, LOAD_I32_A64 }, |
| 10780 | { LOAD_I32_A32_S, LOAD_I32_A64_S }, |
| 10781 | { LOAD_I64_A32, LOAD_I64_A64 }, |
| 10782 | { LOAD_I64_A32_S, LOAD_I64_A64_S }, |
| 10783 | { MEMORY_ATOMIC_NOTIFY_A32, MEMORY_ATOMIC_NOTIFY_A64 }, |
| 10784 | { MEMORY_ATOMIC_NOTIFY_A32_S, MEMORY_ATOMIC_NOTIFY_A64_S }, |
| 10785 | { MEMORY_ATOMIC_WAIT32_A32, MEMORY_ATOMIC_WAIT32_A64 }, |
| 10786 | { MEMORY_ATOMIC_WAIT32_A32_S, MEMORY_ATOMIC_WAIT32_A64_S }, |
| 10787 | { MEMORY_ATOMIC_WAIT64_A32, MEMORY_ATOMIC_WAIT64_A64 }, |
| 10788 | { MEMORY_ATOMIC_WAIT64_A32_S, MEMORY_ATOMIC_WAIT64_A64_S }, |
| 10789 | { STORE16_I32_A32, STORE16_I32_A64 }, |
| 10790 | { STORE16_I32_A32_S, STORE16_I32_A64_S }, |
| 10791 | { STORE16_I64_A32, STORE16_I64_A64 }, |
| 10792 | { STORE16_I64_A32_S, STORE16_I64_A64_S }, |
| 10793 | { STORE32_I64_A32, STORE32_I64_A64 }, |
| 10794 | { STORE32_I64_A32_S, STORE32_I64_A64_S }, |
| 10795 | { STORE8_I32_A32, STORE8_I32_A64 }, |
| 10796 | { STORE8_I32_A32_S, STORE8_I32_A64_S }, |
| 10797 | { STORE8_I64_A32, STORE8_I64_A64 }, |
| 10798 | { STORE8_I64_A32_S, STORE8_I64_A64_S }, |
| 10799 | { STORE_F16_F32_A32, STORE_F16_F32_A64 }, |
| 10800 | { STORE_F16_F32_A32_S, STORE_F16_F32_A64_S }, |
| 10801 | { STORE_F32_A32, STORE_F32_A64 }, |
| 10802 | { STORE_F32_A32_S, STORE_F32_A64_S }, |
| 10803 | { STORE_F64_A32, STORE_F64_A64 }, |
| 10804 | { STORE_F64_A32_S, STORE_F64_A64_S }, |
| 10805 | { STORE_I32_A32, STORE_I32_A64 }, |
| 10806 | { STORE_I32_A32_S, STORE_I32_A64_S }, |
| 10807 | { STORE_I64_A32, STORE_I64_A64 }, |
| 10808 | { STORE_I64_A32_S, STORE_I64_A64_S }, |
| 10809 | }; // End of Table |
| 10810 | |
| 10811 | unsigned mid; |
| 10812 | unsigned start = 0; |
| 10813 | unsigned end = 182; |
| 10814 | while (start < end) { |
| 10815 | mid = start + (end - start) / 2; |
| 10816 | if (Opcode == Table[mid][0]) |
| 10817 | break; |
| 10818 | if (Opcode < Table[mid][0]) |
| 10819 | end = mid; |
| 10820 | else |
| 10821 | start = mid + 1; |
| 10822 | } |
| 10823 | if (start == end) |
| 10824 | return -1; // Instruction doesn't exist in this table. |
| 10825 | |
| 10826 | return Table[mid][1]; |
| 10827 | } |
| 10828 | |
| 10829 | |
| 10830 | } // namespace llvm::WebAssembly |
| 10831 | |
| 10832 | #endif // GET_INSTRMAP_INFO |
| 10833 | |
| 10834 |
Generated while processing llvm_projects/llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
Generated on 2026-Oct-20 from project llvm_projects revision 7be7bc433
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