1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11
12namespace llvm::WebAssembly {
13
14 enum {
15 PHI = 0, // Target.td:1329
16 INLINEASM = 1, // Target.td:1335
17 INLINEASM_BR = 2, // Target.td:1341
18 CFI_INSTRUCTION = 3, // Target.td:1350
19 EH_LABEL = 4, // Target.td:1359
20 GC_LABEL = 5, // Target.td:1368
21 ANNOTATION_LABEL = 6, // Target.td:1377
22 KILL = 7, // Target.td:1385
23 EXTRACT_SUBREG = 8, // Target.td:1392
24 INSERT_SUBREG = 9, // Target.td:1398
25 IMPLICIT_DEF = 10, // Target.td:1405
26 INIT_UNDEF = 11, // Target.td:1414
27 SUBREG_TO_REG = 12, // Target.td:1421
28 COPY_TO_REGCLASS = 13, // Target.td:1427
29 DBG_VALUE = 14, // Target.td:1434
30 DBG_VALUE_LIST = 15, // Target.td:1441
31 DBG_INSTR_REF = 16, // Target.td:1448
32 DBG_PHI = 17, // Target.td:1455
33 DBG_LABEL = 18, // Target.td:1462
34 REG_SEQUENCE = 19, // Target.td:1469
35 COPY = 20, // Target.td:1476
36 COPY_LANEMASK = 21, // Target.td:1484
37 BUNDLE = 22, // Target.td:1491
38 LIFETIME_START = 23, // Target.td:1497
39 LIFETIME_END = 24, // Target.td:1504
40 PSEUDO_PROBE = 25, // Target.td:1511
41 ARITH_FENCE = 26, // Target.td:1518
42 STACKMAP = 27, // Target.td:1527
43 FENTRY_CALL = 28, // Target.td:1662
44 PATCHPOINT = 29, // Target.td:1535
45 LOAD_STACK_GUARD = 30, // Target.td:1553
46 PREALLOCATED_SETUP = 31, // Target.td:1561
47 PREALLOCATED_ARG = 32, // Target.td:1567
48 STATEPOINT = 33, // Target.td:1544
49 LOCAL_ESCAPE = 34, // Target.td:1573
50 FAULTING_OP = 35, // Target.td:1582
51 PATCHABLE_OP = 36, // Target.td:1602
52 PATCHABLE_FUNCTION_ENTER = 37, // Target.td:1610
53 PATCHABLE_RET = 38, // Target.td:1617
54 PATCHABLE_FUNCTION_EXIT = 39, // Target.td:1626
55 PATCHABLE_TAIL_CALL = 40, // Target.td:1634
56 PATCHABLE_EVENT_CALL = 41, // Target.td:1642
57 PATCHABLE_TYPED_EVENT_CALL = 42, // Target.td:1652
58 ICALL_BRANCH_FUNNEL = 43, // Target.td:1672
59 FAKE_USE = 44, // Target.td:1592
60 MEMBARRIER = 45, // Target.td:1678
61 JUMP_TABLE_DEBUG_INFO = 46, // Target.td:1686
62 RELOC_NONE = 47, // Target.td:1694
63 CONVERGENCECTRL_ENTRY = 48, // Target.td:1706
64 CONVERGENCECTRL_ANCHOR = 49, // Target.td:1702
65 CONVERGENCECTRL_LOOP = 50, // Target.td:1710
66 CONVERGENCECTRL_GLUE = 51, // Target.td:1714
67 G_ASSERT_SEXT = 52, // GenericOpcodes.td:1937
68 G_ASSERT_ZEXT = 53, // GenericOpcodes.td:1929
69 G_ASSERT_ALIGN = 54, // GenericOpcodes.td:1944
70 G_ADD = 55, // GenericOpcodes.td:308
71 G_SUB = 56, // GenericOpcodes.td:316
72 G_MUL = 57, // GenericOpcodes.td:324
73 G_SDIV = 58, // GenericOpcodes.td:332
74 G_UDIV = 59, // GenericOpcodes.td:340
75 G_SREM = 60, // GenericOpcodes.td:348
76 G_UREM = 61, // GenericOpcodes.td:356
77 G_SDIVREM = 62, // GenericOpcodes.td:364
78 G_UDIVREM = 63, // GenericOpcodes.td:372
79 G_AND = 64, // GenericOpcodes.td:380
80 G_OR = 65, // GenericOpcodes.td:388
81 G_XOR = 66, // GenericOpcodes.td:396
82 G_ABDS = 67, // GenericOpcodes.td:425
83 G_ABDU = 68, // GenericOpcodes.td:433
84 G_UAVGFLOOR = 69, // GenericOpcodes.td:441
85 G_UAVGCEIL = 70, // GenericOpcodes.td:448
86 G_SAVGFLOOR = 71, // GenericOpcodes.td:455
87 G_SAVGCEIL = 72, // GenericOpcodes.td:462
88 G_IMPLICIT_DEF = 73, // GenericOpcodes.td:111
89 G_PHI = 74, // GenericOpcodes.td:118
90 G_FRAME_INDEX = 75, // GenericOpcodes.td:125
91 G_GLOBAL_VALUE = 76, // GenericOpcodes.td:131
92 G_PTRAUTH_GLOBAL_VALUE = 77, // GenericOpcodes.td:137
93 G_CONSTANT_POOL = 78, // GenericOpcodes.td:143
94 G_EXTRACT = 79, // GenericOpcodes.td:1522
95 G_UNMERGE_VALUES = 80, // GenericOpcodes.td:1535
96 G_INSERT = 81, // GenericOpcodes.td:1544
97 G_MERGE_VALUES = 82, // GenericOpcodes.td:1554
98 G_BUILD_VECTOR = 83, // GenericOpcodes.td:1574
99 G_BUILD_VECTOR_TRUNC = 84, // GenericOpcodes.td:1584
100 G_CONCAT_VECTORS = 85, // GenericOpcodes.td:1591
101 G_PTRTOINT = 86, // GenericOpcodes.td:155
102 G_INTTOPTR = 87, // GenericOpcodes.td:149
103 G_BITCAST = 88, // GenericOpcodes.td:161
104 G_FREEZE = 89, // GenericOpcodes.td:284
105 G_CONSTANT_FOLD_BARRIER = 90, // GenericOpcodes.td:1951
106 G_INTRINSIC_FPTRUNC_ROUND = 91, // GenericOpcodes.td:1280
107 G_INTRINSIC_TRUNC = 92, // GenericOpcodes.td:1286
108 G_INTRINSIC_ROUND = 93, // GenericOpcodes.td:1292
109 G_INTRINSIC_LRINT = 94, // GenericOpcodes.td:1298
110 G_INTRINSIC_LLRINT = 95, // GenericOpcodes.td:1304
111 G_INTRINSIC_ROUNDEVEN = 96, // GenericOpcodes.td:1310
112 G_READCYCLECOUNTER = 97, // GenericOpcodes.td:1316
113 G_READSTEADYCOUNTER = 98, // GenericOpcodes.td:1322
114 G_LOAD = 99, // GenericOpcodes.td:1349
115 G_SEXTLOAD = 100, // GenericOpcodes.td:1358
116 G_ZEXTLOAD = 101, // GenericOpcodes.td:1366
117 G_FPEXTLOAD = 102, // GenericOpcodes.td:1375
118 G_INDEXED_LOAD = 103, // GenericOpcodes.td:1385
119 G_INDEXED_SEXTLOAD = 104, // GenericOpcodes.td:1394
120 G_INDEXED_ZEXTLOAD = 105, // GenericOpcodes.td:1402
121 G_STORE = 106, // GenericOpcodes.td:1410
122 G_FPTRUNCSTORE = 107, // GenericOpcodes.td:1420
123 G_INDEXED_STORE = 108, // GenericOpcodes.td:1428
124 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 109, // GenericOpcodes.td:1439
125 G_ATOMIC_CMPXCHG = 110, // GenericOpcodes.td:1450
126 G_ATOMICRMW_XCHG = 111, // GenericOpcodes.td:1470
127 G_ATOMICRMW_ADD = 112, // GenericOpcodes.td:1471
128 G_ATOMICRMW_SUB = 113, // GenericOpcodes.td:1472
129 G_ATOMICRMW_AND = 114, // GenericOpcodes.td:1473
130 G_ATOMICRMW_NAND = 115, // GenericOpcodes.td:1474
131 G_ATOMICRMW_OR = 116, // GenericOpcodes.td:1475
132 G_ATOMICRMW_XOR = 117, // GenericOpcodes.td:1476
133 G_ATOMICRMW_MAX = 118, // GenericOpcodes.td:1477
134 G_ATOMICRMW_MIN = 119, // GenericOpcodes.td:1478
135 G_ATOMICRMW_UMAX = 120, // GenericOpcodes.td:1479
136 G_ATOMICRMW_UMIN = 121, // GenericOpcodes.td:1480
137 G_ATOMICRMW_FADD = 122, // GenericOpcodes.td:1491
138 G_ATOMICRMW_FSUB = 123, // GenericOpcodes.td:1492
139 G_ATOMICRMW_FMAX = 124, // GenericOpcodes.td:1493
140 G_ATOMICRMW_FMIN = 125, // GenericOpcodes.td:1494
141 G_ATOMICRMW_FMAXIMUM = 126, // GenericOpcodes.td:1495
142 G_ATOMICRMW_FMINIMUM = 127, // GenericOpcodes.td:1496
143 G_ATOMICRMW_FMAXIMUMNUM = 128, // GenericOpcodes.td:1497
144 G_ATOMICRMW_FMINIMUMNUM = 129, // GenericOpcodes.td:1498
145 G_ATOMICRMW_UINC_WRAP = 130, // GenericOpcodes.td:1481
146 G_ATOMICRMW_UDEC_WRAP = 131, // GenericOpcodes.td:1482
147 G_ATOMICRMW_USUB_COND = 132, // GenericOpcodes.td:1483
148 G_ATOMICRMW_USUB_SAT = 133, // GenericOpcodes.td:1484
149 G_FENCE = 134, // GenericOpcodes.td:1500
150 G_PREFETCH = 135, // GenericOpcodes.td:1507
151 G_BRCOND = 136, // GenericOpcodes.td:1647
152 G_BRINDIRECT = 137, // GenericOpcodes.td:1656
153 G_INVOKE_REGION_START = 138, // GenericOpcodes.td:1679
154 G_INTRINSIC = 139, // GenericOpcodes.td:1599
155 G_INTRINSIC_W_SIDE_EFFECTS = 140, // GenericOpcodes.td:1606
156 G_INTRINSIC_CONVERGENT = 141, // GenericOpcodes.td:1615
157 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 142, // GenericOpcodes.td:1623
158 G_ANYEXT = 143, // GenericOpcodes.td:44
159 G_TRUNC = 144, // GenericOpcodes.td:83
160 G_TRUNC_SSAT_S = 145, // GenericOpcodes.td:91
161 G_TRUNC_SSAT_U = 146, // GenericOpcodes.td:98
162 G_TRUNC_USAT_U = 147, // GenericOpcodes.td:105
163 G_CONSTANT = 148, // GenericOpcodes.td:169
164 G_FCONSTANT = 149, // GenericOpcodes.td:177
165 G_VASTART = 150, // GenericOpcodes.td:184
166 G_VAARG = 151, // GenericOpcodes.td:191
167 G_SEXT = 152, // GenericOpcodes.td:52
168 G_SEXT_INREG = 153, // GenericOpcodes.td:66
169 G_ZEXT = 154, // GenericOpcodes.td:74
170 G_SHL = 155, // GenericOpcodes.td:404
171 G_LSHR = 156, // GenericOpcodes.td:411
172 G_ASHR = 157, // GenericOpcodes.td:418
173 G_FSHL = 158, // GenericOpcodes.td:470
174 G_FSHR = 159, // GenericOpcodes.td:478
175 G_ROTR = 160, // GenericOpcodes.td:485
176 G_ROTL = 161, // GenericOpcodes.td:492
177 G_ICMP = 162, // GenericOpcodes.td:499
178 G_FCMP = 163, // GenericOpcodes.td:506
179 G_SCMP = 164, // GenericOpcodes.td:513
180 G_UCMP = 165, // GenericOpcodes.td:520
181 G_SELECT = 166, // GenericOpcodes.td:527
182 G_UADDO = 167, // GenericOpcodes.td:601
183 G_UADDE = 168, // GenericOpcodes.td:609
184 G_USUBO = 169, // GenericOpcodes.td:631
185 G_USUBE = 170, // GenericOpcodes.td:637
186 G_SADDO = 171, // GenericOpcodes.td:616
187 G_SADDE = 172, // GenericOpcodes.td:624
188 G_SSUBO = 173, // GenericOpcodes.td:644
189 G_SSUBE = 174, // GenericOpcodes.td:651
190 G_UMULO = 175, // GenericOpcodes.td:658
191 G_SMULO = 176, // GenericOpcodes.td:666
192 G_UMULH = 177, // GenericOpcodes.td:675
193 G_SMULH = 178, // GenericOpcodes.td:684
194 G_UADDSAT = 179, // GenericOpcodes.td:696
195 G_SADDSAT = 180, // GenericOpcodes.td:704
196 G_USUBSAT = 181, // GenericOpcodes.td:712
197 G_SSUBSAT = 182, // GenericOpcodes.td:720
198 G_USHLSAT = 183, // GenericOpcodes.td:728
199 G_SSHLSAT = 184, // GenericOpcodes.td:736
200 G_SMULFIX = 185, // GenericOpcodes.td:748
201 G_UMULFIX = 186, // GenericOpcodes.td:755
202 G_SMULFIXSAT = 187, // GenericOpcodes.td:765
203 G_UMULFIXSAT = 188, // GenericOpcodes.td:772
204 G_SDIVFIX = 189, // GenericOpcodes.td:783
205 G_UDIVFIX = 190, // GenericOpcodes.td:790
206 G_SDIVFIXSAT = 191, // GenericOpcodes.td:800
207 G_UDIVFIXSAT = 192, // GenericOpcodes.td:807
208 G_FADD = 193, // GenericOpcodes.td:980
209 G_FSUB = 194, // GenericOpcodes.td:988
210 G_FMUL = 195, // GenericOpcodes.td:996
211 G_FMA = 196, // GenericOpcodes.td:1005
212 G_FMAD = 197, // GenericOpcodes.td:1014
213 G_FDIV = 198, // GenericOpcodes.td:1022
214 G_FREM = 199, // GenericOpcodes.td:1029
215 G_FMODF = 200, // GenericOpcodes.td:1036
216 G_FPOW = 201, // GenericOpcodes.td:1043
217 G_FPOWI = 202, // GenericOpcodes.td:1050
218 G_FEXP = 203, // GenericOpcodes.td:1057
219 G_FEXP2 = 204, // GenericOpcodes.td:1064
220 G_FEXP10 = 205, // GenericOpcodes.td:1071
221 G_FLOG = 206, // GenericOpcodes.td:1078
222 G_FLOG2 = 207, // GenericOpcodes.td:1085
223 G_FLOG10 = 208, // GenericOpcodes.td:1092
224 G_FLDEXP = 209, // GenericOpcodes.td:1099
225 G_FFREXP = 210, // GenericOpcodes.td:1106
226 G_FNEG = 211, // GenericOpcodes.td:818
227 G_FPEXT = 212, // GenericOpcodes.td:824
228 G_FPTRUNC = 213, // GenericOpcodes.td:830
229 G_FPTOSI = 214, // GenericOpcodes.td:836
230 G_FPTOUI = 215, // GenericOpcodes.td:842
231 G_SITOFP = 216, // GenericOpcodes.td:848
232 G_UITOFP = 217, // GenericOpcodes.td:854
233 G_FPTOSI_SAT = 218, // GenericOpcodes.td:860
234 G_FPTOUI_SAT = 219, // GenericOpcodes.td:866
235 G_FABS = 220, // GenericOpcodes.td:872
236 G_FCOPYSIGN = 221, // GenericOpcodes.td:878
237 G_IS_FPCLASS = 222, // GenericOpcodes.td:891
238 G_FCANONICALIZE = 223, // GenericOpcodes.td:884
239 G_FMINNUM = 224, // GenericOpcodes.td:904
240 G_FMAXNUM = 225, // GenericOpcodes.td:911
241 G_FMINNUM_IEEE = 226, // GenericOpcodes.td:929
242 G_FMAXNUM_IEEE = 227, // GenericOpcodes.td:936
243 G_FMINIMUM = 228, // GenericOpcodes.td:946
244 G_FMAXIMUM = 229, // GenericOpcodes.td:953
245 G_FMINIMUMNUM = 230, // GenericOpcodes.td:961
246 G_FMAXIMUMNUM = 231, // GenericOpcodes.td:968
247 G_GET_FPENV = 232, // GenericOpcodes.td:1236
248 G_SET_FPENV = 233, // GenericOpcodes.td:1243
249 G_RESET_FPENV = 234, // GenericOpcodes.td:1250
250 G_GET_FPMODE = 235, // GenericOpcodes.td:1257
251 G_SET_FPMODE = 236, // GenericOpcodes.td:1264
252 G_RESET_FPMODE = 237, // GenericOpcodes.td:1271
253 G_GET_ROUNDING = 238, // GenericOpcodes.td:1328
254 G_SET_ROUNDING = 239, // GenericOpcodes.td:1334
255 G_PTR_ADD = 240, // GenericOpcodes.td:534
256 G_PTRMASK = 241, // GenericOpcodes.td:542
257 G_SMIN = 242, // GenericOpcodes.td:549
258 G_SMAX = 243, // GenericOpcodes.td:557
259 G_UMIN = 244, // GenericOpcodes.td:565
260 G_UMAX = 245, // GenericOpcodes.td:573
261 G_ABS = 246, // GenericOpcodes.td:581
262 G_LROUND = 247, // GenericOpcodes.td:291
263 G_LLROUND = 248, // GenericOpcodes.td:297
264 G_BR = 249, // GenericOpcodes.td:1637
265 G_BRJT = 250, // GenericOpcodes.td:1667
266 G_VSCALE = 251, // GenericOpcodes.td:1565
267 G_INSERT_SUBVECTOR = 252, // GenericOpcodes.td:1711
268 G_EXTRACT_SUBVECTOR = 253, // GenericOpcodes.td:1719
269 G_INSERT_VECTOR_ELT = 254, // GenericOpcodes.td:1727
270 G_EXTRACT_VECTOR_ELT = 255, // GenericOpcodes.td:1735
271 G_SHUFFLE_VECTOR = 256, // GenericOpcodes.td:1746
272 G_SPLAT_VECTOR = 257, // GenericOpcodes.td:1754
273 G_STEP_VECTOR = 258, // GenericOpcodes.td:1762
274 G_VECTOR_COMPRESS = 259, // GenericOpcodes.td:1769
275 G_CTTZ = 260, // GenericOpcodes.td:211
276 G_CTTZ_ZERO_POISON = 261, // GenericOpcodes.td:217
277 G_CTLZ = 262, // GenericOpcodes.td:199
278 G_CTLZ_ZERO_POISON = 263, // GenericOpcodes.td:205
279 G_CTLS = 264, // GenericOpcodes.td:223
280 G_CTPOP = 265, // GenericOpcodes.td:229
281 G_BSWAP = 266, // GenericOpcodes.td:235
282 G_BITREVERSE = 267, // GenericOpcodes.td:242
283 G_CLMUL = 268, // GenericOpcodes.td:588
284 G_FCEIL = 269, // GenericOpcodes.td:1113
285 G_FCOS = 270, // GenericOpcodes.td:1120
286 G_FSIN = 271, // GenericOpcodes.td:1127
287 G_FSINCOS = 272, // GenericOpcodes.td:1134
288 G_FTAN = 273, // GenericOpcodes.td:1141
289 G_FACOS = 274, // GenericOpcodes.td:1148
290 G_FASIN = 275, // GenericOpcodes.td:1155
291 G_FATAN = 276, // GenericOpcodes.td:1162
292 G_FATAN2 = 277, // GenericOpcodes.td:1169
293 G_FCOSH = 278, // GenericOpcodes.td:1176
294 G_FSINH = 279, // GenericOpcodes.td:1183
295 G_FTANH = 280, // GenericOpcodes.td:1190
296 G_FSQRT = 281, // GenericOpcodes.td:1200
297 G_FFLOOR = 282, // GenericOpcodes.td:1207
298 G_FRINT = 283, // GenericOpcodes.td:1214
299 G_FNEARBYINT = 284, // GenericOpcodes.td:1221
300 G_ADDRSPACE_CAST = 285, // GenericOpcodes.td:248
301 G_BLOCK_ADDR = 286, // GenericOpcodes.td:254
302 G_JUMP_TABLE = 287, // GenericOpcodes.td:260
303 G_DYN_STACKALLOC = 288, // GenericOpcodes.td:266
304 G_STACKSAVE = 289, // GenericOpcodes.td:272
305 G_STACKRESTORE = 290, // GenericOpcodes.td:278
306 G_STRICT_FADD = 291, // GenericOpcodes.td:1821
307 G_STRICT_FSUB = 292, // GenericOpcodes.td:1822
308 G_STRICT_FMUL = 293, // GenericOpcodes.td:1823
309 G_STRICT_FDIV = 294, // GenericOpcodes.td:1824
310 G_STRICT_FREM = 295, // GenericOpcodes.td:1825
311 G_STRICT_FMA = 296, // GenericOpcodes.td:1826
312 G_STRICT_FSQRT = 297, // GenericOpcodes.td:1827
313 G_STRICT_FLDEXP = 298, // GenericOpcodes.td:1828
314 G_STRICT_FCMP = 299, // GenericOpcodes.td:1829
315 G_STRICT_FCMPS = 300, // GenericOpcodes.td:1830
316 G_READ_REGISTER = 301, // GenericOpcodes.td:1686
317 G_WRITE_REGISTER = 302, // GenericOpcodes.td:1696
318 G_MEMCPY = 303, // GenericOpcodes.td:1836
319 G_MEMCPY_INLINE = 304, // GenericOpcodes.td:1844
320 G_MEMMOVE = 305, // GenericOpcodes.td:1852
321 G_MEMSET = 306, // GenericOpcodes.td:1860
322 G_BZERO = 307, // GenericOpcodes.td:1867
323 G_MEMSET_INLINE = 308, // GenericOpcodes.td:1874
324 G_TRAP = 309, // GenericOpcodes.td:1884
325 G_DEBUGTRAP = 310, // GenericOpcodes.td:1891
326 G_UBSANTRAP = 311, // GenericOpcodes.td:1897
327 G_VECREDUCE_SEQ_FADD = 312, // GenericOpcodes.td:1785
328 G_VECREDUCE_SEQ_FMUL = 313, // GenericOpcodes.td:1791
329 G_VECREDUCE_FADD = 314, // GenericOpcodes.td:1797
330 G_VECREDUCE_FMUL = 315, // GenericOpcodes.td:1798
331 G_VECREDUCE_FMAX = 316, // GenericOpcodes.td:1800
332 G_VECREDUCE_FMIN = 317, // GenericOpcodes.td:1801
333 G_VECREDUCE_FMAXIMUM = 318, // GenericOpcodes.td:1802
334 G_VECREDUCE_FMINIMUM = 319, // GenericOpcodes.td:1803
335 G_VECREDUCE_FMAXIMUMNUM = 320, // GenericOpcodes.td:1804
336 G_VECREDUCE_FMINIMUMNUM = 321, // GenericOpcodes.td:1805
337 G_VECREDUCE_ADD = 322, // GenericOpcodes.td:1807
338 G_VECREDUCE_MUL = 323, // GenericOpcodes.td:1808
339 G_VECREDUCE_AND = 324, // GenericOpcodes.td:1809
340 G_VECREDUCE_OR = 325, // GenericOpcodes.td:1810
341 G_VECREDUCE_XOR = 326, // GenericOpcodes.td:1811
342 G_VECREDUCE_SMAX = 327, // GenericOpcodes.td:1812
343 G_VECREDUCE_SMIN = 328, // GenericOpcodes.td:1813
344 G_VECREDUCE_UMAX = 329, // GenericOpcodes.td:1814
345 G_VECREDUCE_UMIN = 330, // GenericOpcodes.td:1815
346 G_SBFX = 331, // GenericOpcodes.td:1909
347 G_UBFX = 332, // GenericOpcodes.td:1917
348 CALL_PARAMS = 333, // WebAssemblyInstrFormats.td:59
349 CALL_PARAMS_S = 334, // WebAssemblyInstrFormats.td:61
350 CALL_RESULTS = 335, // WebAssemblyInstrFormats.td:59
351 CALL_RESULTS_S = 336, // WebAssemblyInstrFormats.td:61
352 CATCHRET = 337, // WebAssemblyInstrFormats.td:59
353 CATCHRET_S = 338, // WebAssemblyInstrFormats.td:61
354 CLEANUPRET = 339, // WebAssemblyInstrFormats.td:59
355 CLEANUPRET_S = 340, // WebAssemblyInstrFormats.td:61
356 COMPILER_FENCE = 341, // WebAssemblyInstrFormats.td:59
357 COMPILER_FENCE_S = 342, // WebAssemblyInstrFormats.td:61
358 RET_CALL_RESULTS = 343, // WebAssemblyInstrFormats.td:59
359 RET_CALL_RESULTS_S = 344, // WebAssemblyInstrFormats.td:61
360 ABS_F16x8 = 345, // WebAssemblyInstrFormats.td:59
361 ABS_F16x8_S = 346, // WebAssemblyInstrFormats.td:61
362 ABS_F32 = 347, // WebAssemblyInstrFormats.td:59
363 ABS_F32_S = 348, // WebAssemblyInstrFormats.td:61
364 ABS_F32x4 = 349, // WebAssemblyInstrFormats.td:59
365 ABS_F32x4_S = 350, // WebAssemblyInstrFormats.td:61
366 ABS_F64 = 351, // WebAssemblyInstrFormats.td:59
367 ABS_F64_S = 352, // WebAssemblyInstrFormats.td:61
368 ABS_F64x2 = 353, // WebAssemblyInstrFormats.td:59
369 ABS_F64x2_S = 354, // WebAssemblyInstrFormats.td:61
370 ABS_I16x8 = 355, // WebAssemblyInstrFormats.td:59
371 ABS_I16x8_S = 356, // WebAssemblyInstrFormats.td:61
372 ABS_I32x4 = 357, // WebAssemblyInstrFormats.td:59
373 ABS_I32x4_S = 358, // WebAssemblyInstrFormats.td:61
374 ABS_I64x2 = 359, // WebAssemblyInstrFormats.td:59
375 ABS_I64x2_S = 360, // WebAssemblyInstrFormats.td:61
376 ABS_I8x16 = 361, // WebAssemblyInstrFormats.td:59
377 ABS_I8x16_S = 362, // WebAssemblyInstrFormats.td:61
378 ADD_F16x8 = 363, // WebAssemblyInstrFormats.td:59
379 ADD_F16x8_S = 364, // WebAssemblyInstrFormats.td:61
380 ADD_F32 = 365, // WebAssemblyInstrFormats.td:59
381 ADD_F32_S = 366, // WebAssemblyInstrFormats.td:61
382 ADD_F32x4 = 367, // WebAssemblyInstrFormats.td:59
383 ADD_F32x4_S = 368, // WebAssemblyInstrFormats.td:61
384 ADD_F64 = 369, // WebAssemblyInstrFormats.td:59
385 ADD_F64_S = 370, // WebAssemblyInstrFormats.td:61
386 ADD_F64x2 = 371, // WebAssemblyInstrFormats.td:59
387 ADD_F64x2_S = 372, // WebAssemblyInstrFormats.td:61
388 ADD_I16x8 = 373, // WebAssemblyInstrFormats.td:59
389 ADD_I16x8_S = 374, // WebAssemblyInstrFormats.td:61
390 ADD_I32 = 375, // WebAssemblyInstrFormats.td:59
391 ADD_I32_S = 376, // WebAssemblyInstrFormats.td:61
392 ADD_I32x4 = 377, // WebAssemblyInstrFormats.td:59
393 ADD_I32x4_S = 378, // WebAssemblyInstrFormats.td:61
394 ADD_I64 = 379, // WebAssemblyInstrFormats.td:59
395 ADD_I64_S = 380, // WebAssemblyInstrFormats.td:61
396 ADD_I64x2 = 381, // WebAssemblyInstrFormats.td:59
397 ADD_I64x2_S = 382, // WebAssemblyInstrFormats.td:61
398 ADD_I8x16 = 383, // WebAssemblyInstrFormats.td:59
399 ADD_I8x16_S = 384, // WebAssemblyInstrFormats.td:61
400 ADD_SAT_S_I16x8 = 385, // WebAssemblyInstrFormats.td:59
401 ADD_SAT_S_I16x8_S = 386, // WebAssemblyInstrFormats.td:61
402 ADD_SAT_S_I8x16 = 387, // WebAssemblyInstrFormats.td:59
403 ADD_SAT_S_I8x16_S = 388, // WebAssemblyInstrFormats.td:61
404 ADD_SAT_U_I16x8 = 389, // WebAssemblyInstrFormats.td:59
405 ADD_SAT_U_I16x8_S = 390, // WebAssemblyInstrFormats.td:61
406 ADD_SAT_U_I8x16 = 391, // WebAssemblyInstrFormats.td:59
407 ADD_SAT_U_I8x16_S = 392, // WebAssemblyInstrFormats.td:61
408 ADJCALLSTACKDOWN = 393, // WebAssemblyInstrFormats.td:59
409 ADJCALLSTACKDOWN_S = 394, // WebAssemblyInstrFormats.td:61
410 ADJCALLSTACKUP = 395, // WebAssemblyInstrFormats.td:59
411 ADJCALLSTACKUP_S = 396, // WebAssemblyInstrFormats.td:61
412 ALLTRUE_I16x8 = 397, // WebAssemblyInstrFormats.td:59
413 ALLTRUE_I16x8_S = 398, // WebAssemblyInstrFormats.td:61
414 ALLTRUE_I32x4 = 399, // WebAssemblyInstrFormats.td:59
415 ALLTRUE_I32x4_S = 400, // WebAssemblyInstrFormats.td:61
416 ALLTRUE_I64x2 = 401, // WebAssemblyInstrFormats.td:59
417 ALLTRUE_I64x2_S = 402, // WebAssemblyInstrFormats.td:61
418 ALLTRUE_I8x16 = 403, // WebAssemblyInstrFormats.td:59
419 ALLTRUE_I8x16_S = 404, // WebAssemblyInstrFormats.td:61
420 AND = 405, // WebAssemblyInstrFormats.td:59
421 ANDNOT = 406, // WebAssemblyInstrFormats.td:59
422 ANDNOT_S = 407, // WebAssemblyInstrFormats.td:61
423 AND_I32 = 408, // WebAssemblyInstrFormats.td:59
424 AND_I32_S = 409, // WebAssemblyInstrFormats.td:61
425 AND_I64 = 410, // WebAssemblyInstrFormats.td:59
426 AND_I64_S = 411, // WebAssemblyInstrFormats.td:61
427 AND_S = 412, // WebAssemblyInstrFormats.td:61
428 ANYTRUE = 413, // WebAssemblyInstrFormats.td:59
429 ANYTRUE_S = 414, // WebAssemblyInstrFormats.td:61
430 ARGUMENT_exnref = 415, // WebAssemblyInstrFormats.td:59
431 ARGUMENT_exnref_S = 416, // WebAssemblyInstrFormats.td:61
432 ARGUMENT_externref = 417, // WebAssemblyInstrFormats.td:59
433 ARGUMENT_externref_S = 418, // WebAssemblyInstrFormats.td:61
434 ARGUMENT_f32 = 419, // WebAssemblyInstrFormats.td:59
435 ARGUMENT_f32_S = 420, // WebAssemblyInstrFormats.td:61
436 ARGUMENT_f64 = 421, // WebAssemblyInstrFormats.td:59
437 ARGUMENT_f64_S = 422, // WebAssemblyInstrFormats.td:61
438 ARGUMENT_funcref = 423, // WebAssemblyInstrFormats.td:59
439 ARGUMENT_funcref_S = 424, // WebAssemblyInstrFormats.td:61
440 ARGUMENT_i32 = 425, // WebAssemblyInstrFormats.td:59
441 ARGUMENT_i32_S = 426, // WebAssemblyInstrFormats.td:61
442 ARGUMENT_i64 = 427, // WebAssemblyInstrFormats.td:59
443 ARGUMENT_i64_S = 428, // WebAssemblyInstrFormats.td:61
444 ARGUMENT_v16i8 = 429, // WebAssemblyInstrFormats.td:59
445 ARGUMENT_v16i8_S = 430, // WebAssemblyInstrFormats.td:61
446 ARGUMENT_v2f64 = 431, // WebAssemblyInstrFormats.td:59
447 ARGUMENT_v2f64_S = 432, // WebAssemblyInstrFormats.td:61
448 ARGUMENT_v2i64 = 433, // WebAssemblyInstrFormats.td:59
449 ARGUMENT_v2i64_S = 434, // WebAssemblyInstrFormats.td:61
450 ARGUMENT_v4f32 = 435, // WebAssemblyInstrFormats.td:59
451 ARGUMENT_v4f32_S = 436, // WebAssemblyInstrFormats.td:61
452 ARGUMENT_v4i32 = 437, // WebAssemblyInstrFormats.td:59
453 ARGUMENT_v4i32_S = 438, // WebAssemblyInstrFormats.td:61
454 ARGUMENT_v8f16 = 439, // WebAssemblyInstrFormats.td:59
455 ARGUMENT_v8f16_S = 440, // WebAssemblyInstrFormats.td:61
456 ARGUMENT_v8i16 = 441, // WebAssemblyInstrFormats.td:59
457 ARGUMENT_v8i16_S = 442, // WebAssemblyInstrFormats.td:61
458 ATOMIC_FENCE = 443, // WebAssemblyInstrFormats.td:59
459 ATOMIC_FENCE_S = 444, // WebAssemblyInstrFormats.td:61
460 ATOMIC_LOAD16_U_I32_A32 = 445, // WebAssemblyInstrFormats.td:59
461 ATOMIC_LOAD16_U_I32_A32_S = 446, // WebAssemblyInstrFormats.td:61
462 ATOMIC_LOAD16_U_I32_A64 = 447, // WebAssemblyInstrFormats.td:59
463 ATOMIC_LOAD16_U_I32_A64_S = 448, // WebAssemblyInstrFormats.td:61
464 ATOMIC_LOAD16_U_I64_A32 = 449, // WebAssemblyInstrFormats.td:59
465 ATOMIC_LOAD16_U_I64_A32_S = 450, // WebAssemblyInstrFormats.td:61
466 ATOMIC_LOAD16_U_I64_A64 = 451, // WebAssemblyInstrFormats.td:59
467 ATOMIC_LOAD16_U_I64_A64_S = 452, // WebAssemblyInstrFormats.td:61
468 ATOMIC_LOAD32_U_I64_A32 = 453, // WebAssemblyInstrFormats.td:59
469 ATOMIC_LOAD32_U_I64_A32_S = 454, // WebAssemblyInstrFormats.td:61
470 ATOMIC_LOAD32_U_I64_A64 = 455, // WebAssemblyInstrFormats.td:59
471 ATOMIC_LOAD32_U_I64_A64_S = 456, // WebAssemblyInstrFormats.td:61
472 ATOMIC_LOAD8_U_I32_A32 = 457, // WebAssemblyInstrFormats.td:59
473 ATOMIC_LOAD8_U_I32_A32_S = 458, // WebAssemblyInstrFormats.td:61
474 ATOMIC_LOAD8_U_I32_A64 = 459, // WebAssemblyInstrFormats.td:59
475 ATOMIC_LOAD8_U_I32_A64_S = 460, // WebAssemblyInstrFormats.td:61
476 ATOMIC_LOAD8_U_I64_A32 = 461, // WebAssemblyInstrFormats.td:59
477 ATOMIC_LOAD8_U_I64_A32_S = 462, // WebAssemblyInstrFormats.td:61
478 ATOMIC_LOAD8_U_I64_A64 = 463, // WebAssemblyInstrFormats.td:59
479 ATOMIC_LOAD8_U_I64_A64_S = 464, // WebAssemblyInstrFormats.td:61
480 ATOMIC_LOAD_I32_A32 = 465, // WebAssemblyInstrFormats.td:59
481 ATOMIC_LOAD_I32_A32_S = 466, // WebAssemblyInstrFormats.td:61
482 ATOMIC_LOAD_I32_A64 = 467, // WebAssemblyInstrFormats.td:59
483 ATOMIC_LOAD_I32_A64_S = 468, // WebAssemblyInstrFormats.td:61
484 ATOMIC_LOAD_I64_A32 = 469, // WebAssemblyInstrFormats.td:59
485 ATOMIC_LOAD_I64_A32_S = 470, // WebAssemblyInstrFormats.td:61
486 ATOMIC_LOAD_I64_A64 = 471, // WebAssemblyInstrFormats.td:59
487 ATOMIC_LOAD_I64_A64_S = 472, // WebAssemblyInstrFormats.td:61
488 ATOMIC_RMW16_U_ADD_I32_A32 = 473, // WebAssemblyInstrFormats.td:59
489 ATOMIC_RMW16_U_ADD_I32_A32_S = 474, // WebAssemblyInstrFormats.td:61
490 ATOMIC_RMW16_U_ADD_I32_A64 = 475, // WebAssemblyInstrFormats.td:59
491 ATOMIC_RMW16_U_ADD_I32_A64_S = 476, // WebAssemblyInstrFormats.td:61
492 ATOMIC_RMW16_U_ADD_I64_A32 = 477, // WebAssemblyInstrFormats.td:59
493 ATOMIC_RMW16_U_ADD_I64_A32_S = 478, // WebAssemblyInstrFormats.td:61
494 ATOMIC_RMW16_U_ADD_I64_A64 = 479, // WebAssemblyInstrFormats.td:59
495 ATOMIC_RMW16_U_ADD_I64_A64_S = 480, // WebAssemblyInstrFormats.td:61
496 ATOMIC_RMW16_U_AND_I32_A32 = 481, // WebAssemblyInstrFormats.td:59
497 ATOMIC_RMW16_U_AND_I32_A32_S = 482, // WebAssemblyInstrFormats.td:61
498 ATOMIC_RMW16_U_AND_I32_A64 = 483, // WebAssemblyInstrFormats.td:59
499 ATOMIC_RMW16_U_AND_I32_A64_S = 484, // WebAssemblyInstrFormats.td:61
500 ATOMIC_RMW16_U_AND_I64_A32 = 485, // WebAssemblyInstrFormats.td:59
501 ATOMIC_RMW16_U_AND_I64_A32_S = 486, // WebAssemblyInstrFormats.td:61
502 ATOMIC_RMW16_U_AND_I64_A64 = 487, // WebAssemblyInstrFormats.td:59
503 ATOMIC_RMW16_U_AND_I64_A64_S = 488, // WebAssemblyInstrFormats.td:61
504 ATOMIC_RMW16_U_CMPXCHG_I32_A32 = 489, // WebAssemblyInstrFormats.td:59
505 ATOMIC_RMW16_U_CMPXCHG_I32_A32_S = 490, // WebAssemblyInstrFormats.td:61
506 ATOMIC_RMW16_U_CMPXCHG_I32_A64 = 491, // WebAssemblyInstrFormats.td:59
507 ATOMIC_RMW16_U_CMPXCHG_I32_A64_S = 492, // WebAssemblyInstrFormats.td:61
508 ATOMIC_RMW16_U_CMPXCHG_I64_A32 = 493, // WebAssemblyInstrFormats.td:59
509 ATOMIC_RMW16_U_CMPXCHG_I64_A32_S = 494, // WebAssemblyInstrFormats.td:61
510 ATOMIC_RMW16_U_CMPXCHG_I64_A64 = 495, // WebAssemblyInstrFormats.td:59
511 ATOMIC_RMW16_U_CMPXCHG_I64_A64_S = 496, // WebAssemblyInstrFormats.td:61
512 ATOMIC_RMW16_U_OR_I32_A32 = 497, // WebAssemblyInstrFormats.td:59
513 ATOMIC_RMW16_U_OR_I32_A32_S = 498, // WebAssemblyInstrFormats.td:61
514 ATOMIC_RMW16_U_OR_I32_A64 = 499, // WebAssemblyInstrFormats.td:59
515 ATOMIC_RMW16_U_OR_I32_A64_S = 500, // WebAssemblyInstrFormats.td:61
516 ATOMIC_RMW16_U_OR_I64_A32 = 501, // WebAssemblyInstrFormats.td:59
517 ATOMIC_RMW16_U_OR_I64_A32_S = 502, // WebAssemblyInstrFormats.td:61
518 ATOMIC_RMW16_U_OR_I64_A64 = 503, // WebAssemblyInstrFormats.td:59
519 ATOMIC_RMW16_U_OR_I64_A64_S = 504, // WebAssemblyInstrFormats.td:61
520 ATOMIC_RMW16_U_SUB_I32_A32 = 505, // WebAssemblyInstrFormats.td:59
521 ATOMIC_RMW16_U_SUB_I32_A32_S = 506, // WebAssemblyInstrFormats.td:61
522 ATOMIC_RMW16_U_SUB_I32_A64 = 507, // WebAssemblyInstrFormats.td:59
523 ATOMIC_RMW16_U_SUB_I32_A64_S = 508, // WebAssemblyInstrFormats.td:61
524 ATOMIC_RMW16_U_SUB_I64_A32 = 509, // WebAssemblyInstrFormats.td:59
525 ATOMIC_RMW16_U_SUB_I64_A32_S = 510, // WebAssemblyInstrFormats.td:61
526 ATOMIC_RMW16_U_SUB_I64_A64 = 511, // WebAssemblyInstrFormats.td:59
527 ATOMIC_RMW16_U_SUB_I64_A64_S = 512, // WebAssemblyInstrFormats.td:61
528 ATOMIC_RMW16_U_XCHG_I32_A32 = 513, // WebAssemblyInstrFormats.td:59
529 ATOMIC_RMW16_U_XCHG_I32_A32_S = 514, // WebAssemblyInstrFormats.td:61
530 ATOMIC_RMW16_U_XCHG_I32_A64 = 515, // WebAssemblyInstrFormats.td:59
531 ATOMIC_RMW16_U_XCHG_I32_A64_S = 516, // WebAssemblyInstrFormats.td:61
532 ATOMIC_RMW16_U_XCHG_I64_A32 = 517, // WebAssemblyInstrFormats.td:59
533 ATOMIC_RMW16_U_XCHG_I64_A32_S = 518, // WebAssemblyInstrFormats.td:61
534 ATOMIC_RMW16_U_XCHG_I64_A64 = 519, // WebAssemblyInstrFormats.td:59
535 ATOMIC_RMW16_U_XCHG_I64_A64_S = 520, // WebAssemblyInstrFormats.td:61
536 ATOMIC_RMW16_U_XOR_I32_A32 = 521, // WebAssemblyInstrFormats.td:59
537 ATOMIC_RMW16_U_XOR_I32_A32_S = 522, // WebAssemblyInstrFormats.td:61
538 ATOMIC_RMW16_U_XOR_I32_A64 = 523, // WebAssemblyInstrFormats.td:59
539 ATOMIC_RMW16_U_XOR_I32_A64_S = 524, // WebAssemblyInstrFormats.td:61
540 ATOMIC_RMW16_U_XOR_I64_A32 = 525, // WebAssemblyInstrFormats.td:59
541 ATOMIC_RMW16_U_XOR_I64_A32_S = 526, // WebAssemblyInstrFormats.td:61
542 ATOMIC_RMW16_U_XOR_I64_A64 = 527, // WebAssemblyInstrFormats.td:59
543 ATOMIC_RMW16_U_XOR_I64_A64_S = 528, // WebAssemblyInstrFormats.td:61
544 ATOMIC_RMW32_U_ADD_I64_A32 = 529, // WebAssemblyInstrFormats.td:59
545 ATOMIC_RMW32_U_ADD_I64_A32_S = 530, // WebAssemblyInstrFormats.td:61
546 ATOMIC_RMW32_U_ADD_I64_A64 = 531, // WebAssemblyInstrFormats.td:59
547 ATOMIC_RMW32_U_ADD_I64_A64_S = 532, // WebAssemblyInstrFormats.td:61
548 ATOMIC_RMW32_U_AND_I64_A32 = 533, // WebAssemblyInstrFormats.td:59
549 ATOMIC_RMW32_U_AND_I64_A32_S = 534, // WebAssemblyInstrFormats.td:61
550 ATOMIC_RMW32_U_AND_I64_A64 = 535, // WebAssemblyInstrFormats.td:59
551 ATOMIC_RMW32_U_AND_I64_A64_S = 536, // WebAssemblyInstrFormats.td:61
552 ATOMIC_RMW32_U_CMPXCHG_I64_A32 = 537, // WebAssemblyInstrFormats.td:59
553 ATOMIC_RMW32_U_CMPXCHG_I64_A32_S = 538, // WebAssemblyInstrFormats.td:61
554 ATOMIC_RMW32_U_CMPXCHG_I64_A64 = 539, // WebAssemblyInstrFormats.td:59
555 ATOMIC_RMW32_U_CMPXCHG_I64_A64_S = 540, // WebAssemblyInstrFormats.td:61
556 ATOMIC_RMW32_U_OR_I64_A32 = 541, // WebAssemblyInstrFormats.td:59
557 ATOMIC_RMW32_U_OR_I64_A32_S = 542, // WebAssemblyInstrFormats.td:61
558 ATOMIC_RMW32_U_OR_I64_A64 = 543, // WebAssemblyInstrFormats.td:59
559 ATOMIC_RMW32_U_OR_I64_A64_S = 544, // WebAssemblyInstrFormats.td:61
560 ATOMIC_RMW32_U_SUB_I64_A32 = 545, // WebAssemblyInstrFormats.td:59
561 ATOMIC_RMW32_U_SUB_I64_A32_S = 546, // WebAssemblyInstrFormats.td:61
562 ATOMIC_RMW32_U_SUB_I64_A64 = 547, // WebAssemblyInstrFormats.td:59
563 ATOMIC_RMW32_U_SUB_I64_A64_S = 548, // WebAssemblyInstrFormats.td:61
564 ATOMIC_RMW32_U_XCHG_I64_A32 = 549, // WebAssemblyInstrFormats.td:59
565 ATOMIC_RMW32_U_XCHG_I64_A32_S = 550, // WebAssemblyInstrFormats.td:61
566 ATOMIC_RMW32_U_XCHG_I64_A64 = 551, // WebAssemblyInstrFormats.td:59
567 ATOMIC_RMW32_U_XCHG_I64_A64_S = 552, // WebAssemblyInstrFormats.td:61
568 ATOMIC_RMW32_U_XOR_I64_A32 = 553, // WebAssemblyInstrFormats.td:59
569 ATOMIC_RMW32_U_XOR_I64_A32_S = 554, // WebAssemblyInstrFormats.td:61
570 ATOMIC_RMW32_U_XOR_I64_A64 = 555, // WebAssemblyInstrFormats.td:59
571 ATOMIC_RMW32_U_XOR_I64_A64_S = 556, // WebAssemblyInstrFormats.td:61
572 ATOMIC_RMW8_U_ADD_I32_A32 = 557, // WebAssemblyInstrFormats.td:59
573 ATOMIC_RMW8_U_ADD_I32_A32_S = 558, // WebAssemblyInstrFormats.td:61
574 ATOMIC_RMW8_U_ADD_I32_A64 = 559, // WebAssemblyInstrFormats.td:59
575 ATOMIC_RMW8_U_ADD_I32_A64_S = 560, // WebAssemblyInstrFormats.td:61
576 ATOMIC_RMW8_U_ADD_I64_A32 = 561, // WebAssemblyInstrFormats.td:59
577 ATOMIC_RMW8_U_ADD_I64_A32_S = 562, // WebAssemblyInstrFormats.td:61
578 ATOMIC_RMW8_U_ADD_I64_A64 = 563, // WebAssemblyInstrFormats.td:59
579 ATOMIC_RMW8_U_ADD_I64_A64_S = 564, // WebAssemblyInstrFormats.td:61
580 ATOMIC_RMW8_U_AND_I32_A32 = 565, // WebAssemblyInstrFormats.td:59
581 ATOMIC_RMW8_U_AND_I32_A32_S = 566, // WebAssemblyInstrFormats.td:61
582 ATOMIC_RMW8_U_AND_I32_A64 = 567, // WebAssemblyInstrFormats.td:59
583 ATOMIC_RMW8_U_AND_I32_A64_S = 568, // WebAssemblyInstrFormats.td:61
584 ATOMIC_RMW8_U_AND_I64_A32 = 569, // WebAssemblyInstrFormats.td:59
585 ATOMIC_RMW8_U_AND_I64_A32_S = 570, // WebAssemblyInstrFormats.td:61
586 ATOMIC_RMW8_U_AND_I64_A64 = 571, // WebAssemblyInstrFormats.td:59
587 ATOMIC_RMW8_U_AND_I64_A64_S = 572, // WebAssemblyInstrFormats.td:61
588 ATOMIC_RMW8_U_CMPXCHG_I32_A32 = 573, // WebAssemblyInstrFormats.td:59
589 ATOMIC_RMW8_U_CMPXCHG_I32_A32_S = 574, // WebAssemblyInstrFormats.td:61
590 ATOMIC_RMW8_U_CMPXCHG_I32_A64 = 575, // WebAssemblyInstrFormats.td:59
591 ATOMIC_RMW8_U_CMPXCHG_I32_A64_S = 576, // WebAssemblyInstrFormats.td:61
592 ATOMIC_RMW8_U_CMPXCHG_I64_A32 = 577, // WebAssemblyInstrFormats.td:59
593 ATOMIC_RMW8_U_CMPXCHG_I64_A32_S = 578, // WebAssemblyInstrFormats.td:61
594 ATOMIC_RMW8_U_CMPXCHG_I64_A64 = 579, // WebAssemblyInstrFormats.td:59
595 ATOMIC_RMW8_U_CMPXCHG_I64_A64_S = 580, // WebAssemblyInstrFormats.td:61
596 ATOMIC_RMW8_U_OR_I32_A32 = 581, // WebAssemblyInstrFormats.td:59
597 ATOMIC_RMW8_U_OR_I32_A32_S = 582, // WebAssemblyInstrFormats.td:61
598 ATOMIC_RMW8_U_OR_I32_A64 = 583, // WebAssemblyInstrFormats.td:59
599 ATOMIC_RMW8_U_OR_I32_A64_S = 584, // WebAssemblyInstrFormats.td:61
600 ATOMIC_RMW8_U_OR_I64_A32 = 585, // WebAssemblyInstrFormats.td:59
601 ATOMIC_RMW8_U_OR_I64_A32_S = 586, // WebAssemblyInstrFormats.td:61
602 ATOMIC_RMW8_U_OR_I64_A64 = 587, // WebAssemblyInstrFormats.td:59
603 ATOMIC_RMW8_U_OR_I64_A64_S = 588, // WebAssemblyInstrFormats.td:61
604 ATOMIC_RMW8_U_SUB_I32_A32 = 589, // WebAssemblyInstrFormats.td:59
605 ATOMIC_RMW8_U_SUB_I32_A32_S = 590, // WebAssemblyInstrFormats.td:61
606 ATOMIC_RMW8_U_SUB_I32_A64 = 591, // WebAssemblyInstrFormats.td:59
607 ATOMIC_RMW8_U_SUB_I32_A64_S = 592, // WebAssemblyInstrFormats.td:61
608 ATOMIC_RMW8_U_SUB_I64_A32 = 593, // WebAssemblyInstrFormats.td:59
609 ATOMIC_RMW8_U_SUB_I64_A32_S = 594, // WebAssemblyInstrFormats.td:61
610 ATOMIC_RMW8_U_SUB_I64_A64 = 595, // WebAssemblyInstrFormats.td:59
611 ATOMIC_RMW8_U_SUB_I64_A64_S = 596, // WebAssemblyInstrFormats.td:61
612 ATOMIC_RMW8_U_XCHG_I32_A32 = 597, // WebAssemblyInstrFormats.td:59
613 ATOMIC_RMW8_U_XCHG_I32_A32_S = 598, // WebAssemblyInstrFormats.td:61
614 ATOMIC_RMW8_U_XCHG_I32_A64 = 599, // WebAssemblyInstrFormats.td:59
615 ATOMIC_RMW8_U_XCHG_I32_A64_S = 600, // WebAssemblyInstrFormats.td:61
616 ATOMIC_RMW8_U_XCHG_I64_A32 = 601, // WebAssemblyInstrFormats.td:59
617 ATOMIC_RMW8_U_XCHG_I64_A32_S = 602, // WebAssemblyInstrFormats.td:61
618 ATOMIC_RMW8_U_XCHG_I64_A64 = 603, // WebAssemblyInstrFormats.td:59
619 ATOMIC_RMW8_U_XCHG_I64_A64_S = 604, // WebAssemblyInstrFormats.td:61
620 ATOMIC_RMW8_U_XOR_I32_A32 = 605, // WebAssemblyInstrFormats.td:59
621 ATOMIC_RMW8_U_XOR_I32_A32_S = 606, // WebAssemblyInstrFormats.td:61
622 ATOMIC_RMW8_U_XOR_I32_A64 = 607, // WebAssemblyInstrFormats.td:59
623 ATOMIC_RMW8_U_XOR_I32_A64_S = 608, // WebAssemblyInstrFormats.td:61
624 ATOMIC_RMW8_U_XOR_I64_A32 = 609, // WebAssemblyInstrFormats.td:59
625 ATOMIC_RMW8_U_XOR_I64_A32_S = 610, // WebAssemblyInstrFormats.td:61
626 ATOMIC_RMW8_U_XOR_I64_A64 = 611, // WebAssemblyInstrFormats.td:59
627 ATOMIC_RMW8_U_XOR_I64_A64_S = 612, // WebAssemblyInstrFormats.td:61
628 ATOMIC_RMW_ADD_I32_A32 = 613, // WebAssemblyInstrFormats.td:59
629 ATOMIC_RMW_ADD_I32_A32_S = 614, // WebAssemblyInstrFormats.td:61
630 ATOMIC_RMW_ADD_I32_A64 = 615, // WebAssemblyInstrFormats.td:59
631 ATOMIC_RMW_ADD_I32_A64_S = 616, // WebAssemblyInstrFormats.td:61
632 ATOMIC_RMW_ADD_I64_A32 = 617, // WebAssemblyInstrFormats.td:59
633 ATOMIC_RMW_ADD_I64_A32_S = 618, // WebAssemblyInstrFormats.td:61
634 ATOMIC_RMW_ADD_I64_A64 = 619, // WebAssemblyInstrFormats.td:59
635 ATOMIC_RMW_ADD_I64_A64_S = 620, // WebAssemblyInstrFormats.td:61
636 ATOMIC_RMW_AND_I32_A32 = 621, // WebAssemblyInstrFormats.td:59
637 ATOMIC_RMW_AND_I32_A32_S = 622, // WebAssemblyInstrFormats.td:61
638 ATOMIC_RMW_AND_I32_A64 = 623, // WebAssemblyInstrFormats.td:59
639 ATOMIC_RMW_AND_I32_A64_S = 624, // WebAssemblyInstrFormats.td:61
640 ATOMIC_RMW_AND_I64_A32 = 625, // WebAssemblyInstrFormats.td:59
641 ATOMIC_RMW_AND_I64_A32_S = 626, // WebAssemblyInstrFormats.td:61
642 ATOMIC_RMW_AND_I64_A64 = 627, // WebAssemblyInstrFormats.td:59
643 ATOMIC_RMW_AND_I64_A64_S = 628, // WebAssemblyInstrFormats.td:61
644 ATOMIC_RMW_CMPXCHG_I32_A32 = 629, // WebAssemblyInstrFormats.td:59
645 ATOMIC_RMW_CMPXCHG_I32_A32_S = 630, // WebAssemblyInstrFormats.td:61
646 ATOMIC_RMW_CMPXCHG_I32_A64 = 631, // WebAssemblyInstrFormats.td:59
647 ATOMIC_RMW_CMPXCHG_I32_A64_S = 632, // WebAssemblyInstrFormats.td:61
648 ATOMIC_RMW_CMPXCHG_I64_A32 = 633, // WebAssemblyInstrFormats.td:59
649 ATOMIC_RMW_CMPXCHG_I64_A32_S = 634, // WebAssemblyInstrFormats.td:61
650 ATOMIC_RMW_CMPXCHG_I64_A64 = 635, // WebAssemblyInstrFormats.td:59
651 ATOMIC_RMW_CMPXCHG_I64_A64_S = 636, // WebAssemblyInstrFormats.td:61
652 ATOMIC_RMW_OR_I32_A32 = 637, // WebAssemblyInstrFormats.td:59
653 ATOMIC_RMW_OR_I32_A32_S = 638, // WebAssemblyInstrFormats.td:61
654 ATOMIC_RMW_OR_I32_A64 = 639, // WebAssemblyInstrFormats.td:59
655 ATOMIC_RMW_OR_I32_A64_S = 640, // WebAssemblyInstrFormats.td:61
656 ATOMIC_RMW_OR_I64_A32 = 641, // WebAssemblyInstrFormats.td:59
657 ATOMIC_RMW_OR_I64_A32_S = 642, // WebAssemblyInstrFormats.td:61
658 ATOMIC_RMW_OR_I64_A64 = 643, // WebAssemblyInstrFormats.td:59
659 ATOMIC_RMW_OR_I64_A64_S = 644, // WebAssemblyInstrFormats.td:61
660 ATOMIC_RMW_SUB_I32_A32 = 645, // WebAssemblyInstrFormats.td:59
661 ATOMIC_RMW_SUB_I32_A32_S = 646, // WebAssemblyInstrFormats.td:61
662 ATOMIC_RMW_SUB_I32_A64 = 647, // WebAssemblyInstrFormats.td:59
663 ATOMIC_RMW_SUB_I32_A64_S = 648, // WebAssemblyInstrFormats.td:61
664 ATOMIC_RMW_SUB_I64_A32 = 649, // WebAssemblyInstrFormats.td:59
665 ATOMIC_RMW_SUB_I64_A32_S = 650, // WebAssemblyInstrFormats.td:61
666 ATOMIC_RMW_SUB_I64_A64 = 651, // WebAssemblyInstrFormats.td:59
667 ATOMIC_RMW_SUB_I64_A64_S = 652, // WebAssemblyInstrFormats.td:61
668 ATOMIC_RMW_XCHG_I32_A32 = 653, // WebAssemblyInstrFormats.td:59
669 ATOMIC_RMW_XCHG_I32_A32_S = 654, // WebAssemblyInstrFormats.td:61
670 ATOMIC_RMW_XCHG_I32_A64 = 655, // WebAssemblyInstrFormats.td:59
671 ATOMIC_RMW_XCHG_I32_A64_S = 656, // WebAssemblyInstrFormats.td:61
672 ATOMIC_RMW_XCHG_I64_A32 = 657, // WebAssemblyInstrFormats.td:59
673 ATOMIC_RMW_XCHG_I64_A32_S = 658, // WebAssemblyInstrFormats.td:61
674 ATOMIC_RMW_XCHG_I64_A64 = 659, // WebAssemblyInstrFormats.td:59
675 ATOMIC_RMW_XCHG_I64_A64_S = 660, // WebAssemblyInstrFormats.td:61
676 ATOMIC_RMW_XOR_I32_A32 = 661, // WebAssemblyInstrFormats.td:59
677 ATOMIC_RMW_XOR_I32_A32_S = 662, // WebAssemblyInstrFormats.td:61
678 ATOMIC_RMW_XOR_I32_A64 = 663, // WebAssemblyInstrFormats.td:59
679 ATOMIC_RMW_XOR_I32_A64_S = 664, // WebAssemblyInstrFormats.td:61
680 ATOMIC_RMW_XOR_I64_A32 = 665, // WebAssemblyInstrFormats.td:59
681 ATOMIC_RMW_XOR_I64_A32_S = 666, // WebAssemblyInstrFormats.td:61
682 ATOMIC_RMW_XOR_I64_A64 = 667, // WebAssemblyInstrFormats.td:59
683 ATOMIC_RMW_XOR_I64_A64_S = 668, // WebAssemblyInstrFormats.td:61
684 ATOMIC_STORE16_I32_A32 = 669, // WebAssemblyInstrFormats.td:59
685 ATOMIC_STORE16_I32_A32_S = 670, // WebAssemblyInstrFormats.td:61
686 ATOMIC_STORE16_I32_A64 = 671, // WebAssemblyInstrFormats.td:59
687 ATOMIC_STORE16_I32_A64_S = 672, // WebAssemblyInstrFormats.td:61
688 ATOMIC_STORE16_I64_A32 = 673, // WebAssemblyInstrFormats.td:59
689 ATOMIC_STORE16_I64_A32_S = 674, // WebAssemblyInstrFormats.td:61
690 ATOMIC_STORE16_I64_A64 = 675, // WebAssemblyInstrFormats.td:59
691 ATOMIC_STORE16_I64_A64_S = 676, // WebAssemblyInstrFormats.td:61
692 ATOMIC_STORE32_I64_A32 = 677, // WebAssemblyInstrFormats.td:59
693 ATOMIC_STORE32_I64_A32_S = 678, // WebAssemblyInstrFormats.td:61
694 ATOMIC_STORE32_I64_A64 = 679, // WebAssemblyInstrFormats.td:59
695 ATOMIC_STORE32_I64_A64_S = 680, // WebAssemblyInstrFormats.td:61
696 ATOMIC_STORE8_I32_A32 = 681, // WebAssemblyInstrFormats.td:59
697 ATOMIC_STORE8_I32_A32_S = 682, // WebAssemblyInstrFormats.td:61
698 ATOMIC_STORE8_I32_A64 = 683, // WebAssemblyInstrFormats.td:59
699 ATOMIC_STORE8_I32_A64_S = 684, // WebAssemblyInstrFormats.td:61
700 ATOMIC_STORE8_I64_A32 = 685, // WebAssemblyInstrFormats.td:59
701 ATOMIC_STORE8_I64_A32_S = 686, // WebAssemblyInstrFormats.td:61
702 ATOMIC_STORE8_I64_A64 = 687, // WebAssemblyInstrFormats.td:59
703 ATOMIC_STORE8_I64_A64_S = 688, // WebAssemblyInstrFormats.td:61
704 ATOMIC_STORE_I32_A32 = 689, // WebAssemblyInstrFormats.td:59
705 ATOMIC_STORE_I32_A32_S = 690, // WebAssemblyInstrFormats.td:61
706 ATOMIC_STORE_I32_A64 = 691, // WebAssemblyInstrFormats.td:59
707 ATOMIC_STORE_I32_A64_S = 692, // WebAssemblyInstrFormats.td:61
708 ATOMIC_STORE_I64_A32 = 693, // WebAssemblyInstrFormats.td:59
709 ATOMIC_STORE_I64_A32_S = 694, // WebAssemblyInstrFormats.td:61
710 ATOMIC_STORE_I64_A64 = 695, // WebAssemblyInstrFormats.td:59
711 ATOMIC_STORE_I64_A64_S = 696, // WebAssemblyInstrFormats.td:61
712 AVGR_U_I16x8 = 697, // WebAssemblyInstrFormats.td:59
713 AVGR_U_I16x8_S = 698, // WebAssemblyInstrFormats.td:61
714 AVGR_U_I8x16 = 699, // WebAssemblyInstrFormats.td:59
715 AVGR_U_I8x16_S = 700, // WebAssemblyInstrFormats.td:61
716 BITMASK_I16x8 = 701, // WebAssemblyInstrFormats.td:59
717 BITMASK_I16x8_S = 702, // WebAssemblyInstrFormats.td:61
718 BITMASK_I32x4 = 703, // WebAssemblyInstrFormats.td:59
719 BITMASK_I32x4_S = 704, // WebAssemblyInstrFormats.td:61
720 BITMASK_I64x2 = 705, // WebAssemblyInstrFormats.td:59
721 BITMASK_I64x2_S = 706, // WebAssemblyInstrFormats.td:61
722 BITMASK_I8x16 = 707, // WebAssemblyInstrFormats.td:59
723 BITMASK_I8x16_S = 708, // WebAssemblyInstrFormats.td:61
724 BITSELECT = 709, // WebAssemblyInstrFormats.td:59
725 BITSELECT_S = 710, // WebAssemblyInstrFormats.td:61
726 BLOCK = 711, // WebAssemblyInstrFormats.td:59
727 BLOCK_S = 712, // WebAssemblyInstrFormats.td:61
728 BR = 713, // WebAssemblyInstrFormats.td:59
729 BR_IF = 714, // WebAssemblyInstrFormats.td:59
730 BR_IF_S = 715, // WebAssemblyInstrFormats.td:61
731 BR_S = 716, // WebAssemblyInstrFormats.td:61
732 BR_TABLE_I32 = 717, // WebAssemblyInstrFormats.td:59
733 BR_TABLE_I32_S = 718, // WebAssemblyInstrFormats.td:61
734 BR_TABLE_I64 = 719, // WebAssemblyInstrFormats.td:59
735 BR_TABLE_I64_S = 720, // WebAssemblyInstrFormats.td:61
736 BR_UNLESS = 721, // WebAssemblyInstrFormats.td:59
737 BR_UNLESS_S = 722, // WebAssemblyInstrFormats.td:61
738 CALL = 723, // WebAssemblyInstrFormats.td:59
739 CALL_INDIRECT = 724, // WebAssemblyInstrFormats.td:59
740 CALL_INDIRECT_S = 725, // WebAssemblyInstrFormats.td:61
741 CALL_REF = 726, // WebAssemblyInstrFormats.td:59
742 CALL_REF_S = 727, // WebAssemblyInstrFormats.td:61
743 CALL_S = 728, // WebAssemblyInstrFormats.td:61
744 CATCH = 729, // WebAssemblyInstrFormats.td:59
745 CATCH_ALL = 730, // WebAssemblyInstrFormats.td:59
746 CATCH_ALL_LEGACY = 731, // WebAssemblyInstrFormats.td:59
747 CATCH_ALL_LEGACY_S = 732, // WebAssemblyInstrFormats.td:61
748 CATCH_ALL_REF = 733, // WebAssemblyInstrFormats.td:59
749 CATCH_ALL_REF_S = 734, // WebAssemblyInstrFormats.td:61
750 CATCH_ALL_S = 735, // WebAssemblyInstrFormats.td:61
751 CATCH_LEGACY = 736, // WebAssemblyInstrFormats.td:59
752 CATCH_LEGACY_S = 737, // WebAssemblyInstrFormats.td:61
753 CATCH_REF = 738, // WebAssemblyInstrFormats.td:59
754 CATCH_REF_S = 739, // WebAssemblyInstrFormats.td:61
755 CATCH_S = 740, // WebAssemblyInstrFormats.td:61
756 CEIL_F16x8 = 741, // WebAssemblyInstrFormats.td:59
757 CEIL_F16x8_S = 742, // WebAssemblyInstrFormats.td:61
758 CEIL_F32 = 743, // WebAssemblyInstrFormats.td:59
759 CEIL_F32_S = 744, // WebAssemblyInstrFormats.td:61
760 CEIL_F32x4 = 745, // WebAssemblyInstrFormats.td:59
761 CEIL_F32x4_S = 746, // WebAssemblyInstrFormats.td:61
762 CEIL_F64 = 747, // WebAssemblyInstrFormats.td:59
763 CEIL_F64_S = 748, // WebAssemblyInstrFormats.td:61
764 CEIL_F64x2 = 749, // WebAssemblyInstrFormats.td:59
765 CEIL_F64x2_S = 750, // WebAssemblyInstrFormats.td:61
766 CLZ_I32 = 751, // WebAssemblyInstrFormats.td:59
767 CLZ_I32_S = 752, // WebAssemblyInstrFormats.td:61
768 CLZ_I64 = 753, // WebAssemblyInstrFormats.td:59
769 CLZ_I64_S = 754, // WebAssemblyInstrFormats.td:61
770 CONST_F32 = 755, // WebAssemblyInstrFormats.td:59
771 CONST_F32_S = 756, // WebAssemblyInstrFormats.td:61
772 CONST_F64 = 757, // WebAssemblyInstrFormats.td:59
773 CONST_F64_S = 758, // WebAssemblyInstrFormats.td:61
774 CONST_I32 = 759, // WebAssemblyInstrFormats.td:59
775 CONST_I32_S = 760, // WebAssemblyInstrFormats.td:61
776 CONST_I64 = 761, // WebAssemblyInstrFormats.td:59
777 CONST_I64_S = 762, // WebAssemblyInstrFormats.td:61
778 CONST_V128_F32x4 = 763, // WebAssemblyInstrFormats.td:59
779 CONST_V128_F32x4_S = 764, // WebAssemblyInstrFormats.td:61
780 CONST_V128_F64x2 = 765, // WebAssemblyInstrFormats.td:59
781 CONST_V128_F64x2_S = 766, // WebAssemblyInstrFormats.td:61
782 CONST_V128_I16x8 = 767, // WebAssemblyInstrFormats.td:59
783 CONST_V128_I16x8_S = 768, // WebAssemblyInstrFormats.td:61
784 CONST_V128_I32x4 = 769, // WebAssemblyInstrFormats.td:59
785 CONST_V128_I32x4_S = 770, // WebAssemblyInstrFormats.td:61
786 CONST_V128_I64x2 = 771, // WebAssemblyInstrFormats.td:59
787 CONST_V128_I64x2_S = 772, // WebAssemblyInstrFormats.td:61
788 CONST_V128_I8x16 = 773, // WebAssemblyInstrFormats.td:59
789 CONST_V128_I8x16_S = 774, // WebAssemblyInstrFormats.td:61
790 COPYSIGN_F32 = 775, // WebAssemblyInstrFormats.td:59
791 COPYSIGN_F32_S = 776, // WebAssemblyInstrFormats.td:61
792 COPYSIGN_F64 = 777, // WebAssemblyInstrFormats.td:59
793 COPYSIGN_F64_S = 778, // WebAssemblyInstrFormats.td:61
794 COPY_EXNREF = 779, // WebAssemblyInstrFormats.td:59
795 COPY_EXNREF_S = 780, // WebAssemblyInstrFormats.td:61
796 COPY_EXTERNREF = 781, // WebAssemblyInstrFormats.td:59
797 COPY_EXTERNREF_S = 782, // WebAssemblyInstrFormats.td:61
798 COPY_F32 = 783, // WebAssemblyInstrFormats.td:59
799 COPY_F32_S = 784, // WebAssemblyInstrFormats.td:61
800 COPY_F64 = 785, // WebAssemblyInstrFormats.td:59
801 COPY_F64_S = 786, // WebAssemblyInstrFormats.td:61
802 COPY_FUNCREF = 787, // WebAssemblyInstrFormats.td:59
803 COPY_FUNCREF_S = 788, // WebAssemblyInstrFormats.td:61
804 COPY_I32 = 789, // WebAssemblyInstrFormats.td:59
805 COPY_I32_S = 790, // WebAssemblyInstrFormats.td:61
806 COPY_I64 = 791, // WebAssemblyInstrFormats.td:59
807 COPY_I64_S = 792, // WebAssemblyInstrFormats.td:61
808 COPY_V128 = 793, // WebAssemblyInstrFormats.td:59
809 COPY_V128_S = 794, // WebAssemblyInstrFormats.td:61
810 CTZ_I32 = 795, // WebAssemblyInstrFormats.td:59
811 CTZ_I32_S = 796, // WebAssemblyInstrFormats.td:61
812 CTZ_I64 = 797, // WebAssemblyInstrFormats.td:59
813 CTZ_I64_S = 798, // WebAssemblyInstrFormats.td:61
814 DATA_DROP = 799, // WebAssemblyInstrFormats.td:59
815 DATA_DROP_S = 800, // WebAssemblyInstrFormats.td:61
816 DEBUG_UNREACHABLE = 801, // WebAssemblyInstrFormats.td:59
817 DEBUG_UNREACHABLE_S = 802, // WebAssemblyInstrFormats.td:61
818 DELEGATE = 803, // WebAssemblyInstrFormats.td:59
819 DELEGATE_S = 804, // WebAssemblyInstrFormats.td:61
820 DIV_F16x8 = 805, // WebAssemblyInstrFormats.td:59
821 DIV_F16x8_S = 806, // WebAssemblyInstrFormats.td:61
822 DIV_F32 = 807, // WebAssemblyInstrFormats.td:59
823 DIV_F32_S = 808, // WebAssemblyInstrFormats.td:61
824 DIV_F32x4 = 809, // WebAssemblyInstrFormats.td:59
825 DIV_F32x4_S = 810, // WebAssemblyInstrFormats.td:61
826 DIV_F64 = 811, // WebAssemblyInstrFormats.td:59
827 DIV_F64_S = 812, // WebAssemblyInstrFormats.td:61
828 DIV_F64x2 = 813, // WebAssemblyInstrFormats.td:59
829 DIV_F64x2_S = 814, // WebAssemblyInstrFormats.td:61
830 DIV_S_I32 = 815, // WebAssemblyInstrFormats.td:59
831 DIV_S_I32_S = 816, // WebAssemblyInstrFormats.td:61
832 DIV_S_I64 = 817, // WebAssemblyInstrFormats.td:59
833 DIV_S_I64_S = 818, // WebAssemblyInstrFormats.td:61
834 DIV_U_I32 = 819, // WebAssemblyInstrFormats.td:59
835 DIV_U_I32_S = 820, // WebAssemblyInstrFormats.td:61
836 DIV_U_I64 = 821, // WebAssemblyInstrFormats.td:59
837 DIV_U_I64_S = 822, // WebAssemblyInstrFormats.td:61
838 DOT = 823, // WebAssemblyInstrFormats.td:59
839 DOT_S = 824, // WebAssemblyInstrFormats.td:61
840 DROP_EXNREF = 825, // WebAssemblyInstrFormats.td:59
841 DROP_EXNREF_S = 826, // WebAssemblyInstrFormats.td:61
842 DROP_EXTERNREF = 827, // WebAssemblyInstrFormats.td:59
843 DROP_EXTERNREF_S = 828, // WebAssemblyInstrFormats.td:61
844 DROP_F32 = 829, // WebAssemblyInstrFormats.td:59
845 DROP_F32_S = 830, // WebAssemblyInstrFormats.td:61
846 DROP_F64 = 831, // WebAssemblyInstrFormats.td:59
847 DROP_F64_S = 832, // WebAssemblyInstrFormats.td:61
848 DROP_FUNCREF = 833, // WebAssemblyInstrFormats.td:59
849 DROP_FUNCREF_S = 834, // WebAssemblyInstrFormats.td:61
850 DROP_I32 = 835, // WebAssemblyInstrFormats.td:59
851 DROP_I32_S = 836, // WebAssemblyInstrFormats.td:61
852 DROP_I64 = 837, // WebAssemblyInstrFormats.td:59
853 DROP_I64_S = 838, // WebAssemblyInstrFormats.td:61
854 DROP_V128 = 839, // WebAssemblyInstrFormats.td:59
855 DROP_V128_S = 840, // WebAssemblyInstrFormats.td:61
856 ELSE = 841, // WebAssemblyInstrFormats.td:59
857 ELSE_S = 842, // WebAssemblyInstrFormats.td:61
858 END = 843, // WebAssemblyInstrFormats.td:59
859 END_BLOCK = 844, // WebAssemblyInstrFormats.td:59
860 END_BLOCK_S = 845, // WebAssemblyInstrFormats.td:61
861 END_FUNCTION = 846, // WebAssemblyInstrFormats.td:59
862 END_FUNCTION_S = 847, // WebAssemblyInstrFormats.td:61
863 END_IF = 848, // WebAssemblyInstrFormats.td:59
864 END_IF_S = 849, // WebAssemblyInstrFormats.td:61
865 END_LOOP = 850, // WebAssemblyInstrFormats.td:59
866 END_LOOP_S = 851, // WebAssemblyInstrFormats.td:61
867 END_S = 852, // WebAssemblyInstrFormats.td:61
868 END_TRY = 853, // WebAssemblyInstrFormats.td:59
869 END_TRY_S = 854, // WebAssemblyInstrFormats.td:61
870 END_TRY_TABLE = 855, // WebAssemblyInstrFormats.td:59
871 END_TRY_TABLE_S = 856, // WebAssemblyInstrFormats.td:61
872 EQZ_I32 = 857, // WebAssemblyInstrFormats.td:59
873 EQZ_I32_S = 858, // WebAssemblyInstrFormats.td:61
874 EQZ_I64 = 859, // WebAssemblyInstrFormats.td:59
875 EQZ_I64_S = 860, // WebAssemblyInstrFormats.td:61
876 EQ_F16x8 = 861, // WebAssemblyInstrFormats.td:59
877 EQ_F16x8_S = 862, // WebAssemblyInstrFormats.td:61
878 EQ_F32 = 863, // WebAssemblyInstrFormats.td:59
879 EQ_F32_S = 864, // WebAssemblyInstrFormats.td:61
880 EQ_F32x4 = 865, // WebAssemblyInstrFormats.td:59
881 EQ_F32x4_S = 866, // WebAssemblyInstrFormats.td:61
882 EQ_F64 = 867, // WebAssemblyInstrFormats.td:59
883 EQ_F64_S = 868, // WebAssemblyInstrFormats.td:61
884 EQ_F64x2 = 869, // WebAssemblyInstrFormats.td:59
885 EQ_F64x2_S = 870, // WebAssemblyInstrFormats.td:61
886 EQ_I16x8 = 871, // WebAssemblyInstrFormats.td:59
887 EQ_I16x8_S = 872, // WebAssemblyInstrFormats.td:61
888 EQ_I32 = 873, // WebAssemblyInstrFormats.td:59
889 EQ_I32_S = 874, // WebAssemblyInstrFormats.td:61
890 EQ_I32x4 = 875, // WebAssemblyInstrFormats.td:59
891 EQ_I32x4_S = 876, // WebAssemblyInstrFormats.td:61
892 EQ_I64 = 877, // WebAssemblyInstrFormats.td:59
893 EQ_I64_S = 878, // WebAssemblyInstrFormats.td:61
894 EQ_I64x2 = 879, // WebAssemblyInstrFormats.td:59
895 EQ_I64x2_S = 880, // WebAssemblyInstrFormats.td:61
896 EQ_I8x16 = 881, // WebAssemblyInstrFormats.td:59
897 EQ_I8x16_S = 882, // WebAssemblyInstrFormats.td:61
898 EXTMUL_HIGH_S_I16x8 = 883, // WebAssemblyInstrFormats.td:59
899 EXTMUL_HIGH_S_I16x8_S = 884, // WebAssemblyInstrFormats.td:61
900 EXTMUL_HIGH_S_I32x4 = 885, // WebAssemblyInstrFormats.td:59
901 EXTMUL_HIGH_S_I32x4_S = 886, // WebAssemblyInstrFormats.td:61
902 EXTMUL_HIGH_S_I64x2 = 887, // WebAssemblyInstrFormats.td:59
903 EXTMUL_HIGH_S_I64x2_S = 888, // WebAssemblyInstrFormats.td:61
904 EXTMUL_HIGH_U_I16x8 = 889, // WebAssemblyInstrFormats.td:59
905 EXTMUL_HIGH_U_I16x8_S = 890, // WebAssemblyInstrFormats.td:61
906 EXTMUL_HIGH_U_I32x4 = 891, // WebAssemblyInstrFormats.td:59
907 EXTMUL_HIGH_U_I32x4_S = 892, // WebAssemblyInstrFormats.td:61
908 EXTMUL_HIGH_U_I64x2 = 893, // WebAssemblyInstrFormats.td:59
909 EXTMUL_HIGH_U_I64x2_S = 894, // WebAssemblyInstrFormats.td:61
910 EXTMUL_LOW_S_I16x8 = 895, // WebAssemblyInstrFormats.td:59
911 EXTMUL_LOW_S_I16x8_S = 896, // WebAssemblyInstrFormats.td:61
912 EXTMUL_LOW_S_I32x4 = 897, // WebAssemblyInstrFormats.td:59
913 EXTMUL_LOW_S_I32x4_S = 898, // WebAssemblyInstrFormats.td:61
914 EXTMUL_LOW_S_I64x2 = 899, // WebAssemblyInstrFormats.td:59
915 EXTMUL_LOW_S_I64x2_S = 900, // WebAssemblyInstrFormats.td:61
916 EXTMUL_LOW_U_I16x8 = 901, // WebAssemblyInstrFormats.td:59
917 EXTMUL_LOW_U_I16x8_S = 902, // WebAssemblyInstrFormats.td:61
918 EXTMUL_LOW_U_I32x4 = 903, // WebAssemblyInstrFormats.td:59
919 EXTMUL_LOW_U_I32x4_S = 904, // WebAssemblyInstrFormats.td:61
920 EXTMUL_LOW_U_I64x2 = 905, // WebAssemblyInstrFormats.td:59
921 EXTMUL_LOW_U_I64x2_S = 906, // WebAssemblyInstrFormats.td:61
922 EXTRACT_LANE_F16x8 = 907, // WebAssemblyInstrFormats.td:59
923 EXTRACT_LANE_F16x8_S = 908, // WebAssemblyInstrFormats.td:61
924 EXTRACT_LANE_F32x4 = 909, // WebAssemblyInstrFormats.td:59
925 EXTRACT_LANE_F32x4_S = 910, // WebAssemblyInstrFormats.td:61
926 EXTRACT_LANE_F64x2 = 911, // WebAssemblyInstrFormats.td:59
927 EXTRACT_LANE_F64x2_S = 912, // WebAssemblyInstrFormats.td:61
928 EXTRACT_LANE_I16x8_s = 913, // WebAssemblyInstrFormats.td:59
929 EXTRACT_LANE_I16x8_s_S = 914, // WebAssemblyInstrFormats.td:61
930 EXTRACT_LANE_I16x8_u = 915, // WebAssemblyInstrFormats.td:59
931 EXTRACT_LANE_I16x8_u_S = 916, // WebAssemblyInstrFormats.td:61
932 EXTRACT_LANE_I32x4 = 917, // WebAssemblyInstrFormats.td:59
933 EXTRACT_LANE_I32x4_S = 918, // WebAssemblyInstrFormats.td:61
934 EXTRACT_LANE_I64x2 = 919, // WebAssemblyInstrFormats.td:59
935 EXTRACT_LANE_I64x2_S = 920, // WebAssemblyInstrFormats.td:61
936 EXTRACT_LANE_I8x16_s = 921, // WebAssemblyInstrFormats.td:59
937 EXTRACT_LANE_I8x16_s_S = 922, // WebAssemblyInstrFormats.td:61
938 EXTRACT_LANE_I8x16_u = 923, // WebAssemblyInstrFormats.td:59
939 EXTRACT_LANE_I8x16_u_S = 924, // WebAssemblyInstrFormats.td:61
940 F32_CONVERT_S_I32 = 925, // WebAssemblyInstrFormats.td:59
941 F32_CONVERT_S_I32_S = 926, // WebAssemblyInstrFormats.td:61
942 F32_CONVERT_S_I64 = 927, // WebAssemblyInstrFormats.td:59
943 F32_CONVERT_S_I64_S = 928, // WebAssemblyInstrFormats.td:61
944 F32_CONVERT_U_I32 = 929, // WebAssemblyInstrFormats.td:59
945 F32_CONVERT_U_I32_S = 930, // WebAssemblyInstrFormats.td:61
946 F32_CONVERT_U_I64 = 931, // WebAssemblyInstrFormats.td:59
947 F32_CONVERT_U_I64_S = 932, // WebAssemblyInstrFormats.td:61
948 F32_DEMOTE_F64 = 933, // WebAssemblyInstrFormats.td:59
949 F32_DEMOTE_F64_S = 934, // WebAssemblyInstrFormats.td:61
950 F32_REINTERPRET_I32 = 935, // WebAssemblyInstrFormats.td:59
951 F32_REINTERPRET_I32_S = 936, // WebAssemblyInstrFormats.td:61
952 F64_CONVERT_S_I32 = 937, // WebAssemblyInstrFormats.td:59
953 F64_CONVERT_S_I32_S = 938, // WebAssemblyInstrFormats.td:61
954 F64_CONVERT_S_I64 = 939, // WebAssemblyInstrFormats.td:59
955 F64_CONVERT_S_I64_S = 940, // WebAssemblyInstrFormats.td:61
956 F64_CONVERT_U_I32 = 941, // WebAssemblyInstrFormats.td:59
957 F64_CONVERT_U_I32_S = 942, // WebAssemblyInstrFormats.td:61
958 F64_CONVERT_U_I64 = 943, // WebAssemblyInstrFormats.td:59
959 F64_CONVERT_U_I64_S = 944, // WebAssemblyInstrFormats.td:61
960 F64_PROMOTE_F32 = 945, // WebAssemblyInstrFormats.td:59
961 F64_PROMOTE_F32_S = 946, // WebAssemblyInstrFormats.td:61
962 F64_REINTERPRET_I64 = 947, // WebAssemblyInstrFormats.td:59
963 F64_REINTERPRET_I64_S = 948, // WebAssemblyInstrFormats.td:61
964 FALLTHROUGH_RETURN = 949, // WebAssemblyInstrFormats.td:59
965 FALLTHROUGH_RETURN_S = 950, // WebAssemblyInstrFormats.td:61
966 FLOOR_F16x8 = 951, // WebAssemblyInstrFormats.td:59
967 FLOOR_F16x8_S = 952, // WebAssemblyInstrFormats.td:61
968 FLOOR_F32 = 953, // WebAssemblyInstrFormats.td:59
969 FLOOR_F32_S = 954, // WebAssemblyInstrFormats.td:61
970 FLOOR_F32x4 = 955, // WebAssemblyInstrFormats.td:59
971 FLOOR_F32x4_S = 956, // WebAssemblyInstrFormats.td:61
972 FLOOR_F64 = 957, // WebAssemblyInstrFormats.td:59
973 FLOOR_F64_S = 958, // WebAssemblyInstrFormats.td:61
974 FLOOR_F64x2 = 959, // WebAssemblyInstrFormats.td:59
975 FLOOR_F64x2_S = 960, // WebAssemblyInstrFormats.td:61
976 FP_TO_SINT_I32_F32 = 961, // WebAssemblyInstrFormats.td:59
977 FP_TO_SINT_I32_F32_S = 962, // WebAssemblyInstrFormats.td:61
978 FP_TO_SINT_I32_F64 = 963, // WebAssemblyInstrFormats.td:59
979 FP_TO_SINT_I32_F64_S = 964, // WebAssemblyInstrFormats.td:61
980 FP_TO_SINT_I64_F32 = 965, // WebAssemblyInstrFormats.td:59
981 FP_TO_SINT_I64_F32_S = 966, // WebAssemblyInstrFormats.td:61
982 FP_TO_SINT_I64_F64 = 967, // WebAssemblyInstrFormats.td:59
983 FP_TO_SINT_I64_F64_S = 968, // WebAssemblyInstrFormats.td:61
984 FP_TO_UINT_I32_F32 = 969, // WebAssemblyInstrFormats.td:59
985 FP_TO_UINT_I32_F32_S = 970, // WebAssemblyInstrFormats.td:61
986 FP_TO_UINT_I32_F64 = 971, // WebAssemblyInstrFormats.td:59
987 FP_TO_UINT_I32_F64_S = 972, // WebAssemblyInstrFormats.td:61
988 FP_TO_UINT_I64_F32 = 973, // WebAssemblyInstrFormats.td:59
989 FP_TO_UINT_I64_F32_S = 974, // WebAssemblyInstrFormats.td:61
990 FP_TO_UINT_I64_F64 = 975, // WebAssemblyInstrFormats.td:59
991 FP_TO_UINT_I64_F64_S = 976, // WebAssemblyInstrFormats.td:61
992 GE_F16x8 = 977, // WebAssemblyInstrFormats.td:59
993 GE_F16x8_S = 978, // WebAssemblyInstrFormats.td:61
994 GE_F32 = 979, // WebAssemblyInstrFormats.td:59
995 GE_F32_S = 980, // WebAssemblyInstrFormats.td:61
996 GE_F32x4 = 981, // WebAssemblyInstrFormats.td:59
997 GE_F32x4_S = 982, // WebAssemblyInstrFormats.td:61
998 GE_F64 = 983, // WebAssemblyInstrFormats.td:59
999 GE_F64_S = 984, // WebAssemblyInstrFormats.td:61
1000 GE_F64x2 = 985, // WebAssemblyInstrFormats.td:59
1001 GE_F64x2_S = 986, // WebAssemblyInstrFormats.td:61
1002 GE_S_I16x8 = 987, // WebAssemblyInstrFormats.td:59
1003 GE_S_I16x8_S = 988, // WebAssemblyInstrFormats.td:61
1004 GE_S_I32 = 989, // WebAssemblyInstrFormats.td:59
1005 GE_S_I32_S = 990, // WebAssemblyInstrFormats.td:61
1006 GE_S_I32x4 = 991, // WebAssemblyInstrFormats.td:59
1007 GE_S_I32x4_S = 992, // WebAssemblyInstrFormats.td:61
1008 GE_S_I64 = 993, // WebAssemblyInstrFormats.td:59
1009 GE_S_I64_S = 994, // WebAssemblyInstrFormats.td:61
1010 GE_S_I64x2 = 995, // WebAssemblyInstrFormats.td:59
1011 GE_S_I64x2_S = 996, // WebAssemblyInstrFormats.td:61
1012 GE_S_I8x16 = 997, // WebAssemblyInstrFormats.td:59
1013 GE_S_I8x16_S = 998, // WebAssemblyInstrFormats.td:61
1014 GE_U_I16x8 = 999, // WebAssemblyInstrFormats.td:59
1015 GE_U_I16x8_S = 1000, // WebAssemblyInstrFormats.td:61
1016 GE_U_I32 = 1001, // WebAssemblyInstrFormats.td:59
1017 GE_U_I32_S = 1002, // WebAssemblyInstrFormats.td:61
1018 GE_U_I32x4 = 1003, // WebAssemblyInstrFormats.td:59
1019 GE_U_I32x4_S = 1004, // WebAssemblyInstrFormats.td:61
1020 GE_U_I64 = 1005, // WebAssemblyInstrFormats.td:59
1021 GE_U_I64_S = 1006, // WebAssemblyInstrFormats.td:61
1022 GE_U_I8x16 = 1007, // WebAssemblyInstrFormats.td:59
1023 GE_U_I8x16_S = 1008, // WebAssemblyInstrFormats.td:61
1024 GLOBAL_GET_EXNREF = 1009, // WebAssemblyInstrFormats.td:59
1025 GLOBAL_GET_EXNREF_S = 1010, // WebAssemblyInstrFormats.td:61
1026 GLOBAL_GET_EXTERNREF = 1011, // WebAssemblyInstrFormats.td:59
1027 GLOBAL_GET_EXTERNREF_S = 1012, // WebAssemblyInstrFormats.td:61
1028 GLOBAL_GET_F32 = 1013, // WebAssemblyInstrFormats.td:59
1029 GLOBAL_GET_F32_S = 1014, // WebAssemblyInstrFormats.td:61
1030 GLOBAL_GET_F64 = 1015, // WebAssemblyInstrFormats.td:59
1031 GLOBAL_GET_F64_S = 1016, // WebAssemblyInstrFormats.td:61
1032 GLOBAL_GET_FUNCREF = 1017, // WebAssemblyInstrFormats.td:59
1033 GLOBAL_GET_FUNCREF_S = 1018, // WebAssemblyInstrFormats.td:61
1034 GLOBAL_GET_I32 = 1019, // WebAssemblyInstrFormats.td:59
1035 GLOBAL_GET_I32_S = 1020, // WebAssemblyInstrFormats.td:61
1036 GLOBAL_GET_I64 = 1021, // WebAssemblyInstrFormats.td:59
1037 GLOBAL_GET_I64_S = 1022, // WebAssemblyInstrFormats.td:61
1038 GLOBAL_GET_V128 = 1023, // WebAssemblyInstrFormats.td:59
1039 GLOBAL_GET_V128_S = 1024, // WebAssemblyInstrFormats.td:61
1040 GLOBAL_SET_EXNREF = 1025, // WebAssemblyInstrFormats.td:59
1041 GLOBAL_SET_EXNREF_S = 1026, // WebAssemblyInstrFormats.td:61
1042 GLOBAL_SET_EXTERNREF = 1027, // WebAssemblyInstrFormats.td:59
1043 GLOBAL_SET_EXTERNREF_S = 1028, // WebAssemblyInstrFormats.td:61
1044 GLOBAL_SET_F32 = 1029, // WebAssemblyInstrFormats.td:59
1045 GLOBAL_SET_F32_S = 1030, // WebAssemblyInstrFormats.td:61
1046 GLOBAL_SET_F64 = 1031, // WebAssemblyInstrFormats.td:59
1047 GLOBAL_SET_F64_S = 1032, // WebAssemblyInstrFormats.td:61
1048 GLOBAL_SET_FUNCREF = 1033, // WebAssemblyInstrFormats.td:59
1049 GLOBAL_SET_FUNCREF_S = 1034, // WebAssemblyInstrFormats.td:61
1050 GLOBAL_SET_I32 = 1035, // WebAssemblyInstrFormats.td:59
1051 GLOBAL_SET_I32_S = 1036, // WebAssemblyInstrFormats.td:61
1052 GLOBAL_SET_I64 = 1037, // WebAssemblyInstrFormats.td:59
1053 GLOBAL_SET_I64_S = 1038, // WebAssemblyInstrFormats.td:61
1054 GLOBAL_SET_V128 = 1039, // WebAssemblyInstrFormats.td:59
1055 GLOBAL_SET_V128_S = 1040, // WebAssemblyInstrFormats.td:61
1056 GT_F16x8 = 1041, // WebAssemblyInstrFormats.td:59
1057 GT_F16x8_S = 1042, // WebAssemblyInstrFormats.td:61
1058 GT_F32 = 1043, // WebAssemblyInstrFormats.td:59
1059 GT_F32_S = 1044, // WebAssemblyInstrFormats.td:61
1060 GT_F32x4 = 1045, // WebAssemblyInstrFormats.td:59
1061 GT_F32x4_S = 1046, // WebAssemblyInstrFormats.td:61
1062 GT_F64 = 1047, // WebAssemblyInstrFormats.td:59
1063 GT_F64_S = 1048, // WebAssemblyInstrFormats.td:61
1064 GT_F64x2 = 1049, // WebAssemblyInstrFormats.td:59
1065 GT_F64x2_S = 1050, // WebAssemblyInstrFormats.td:61
1066 GT_S_I16x8 = 1051, // WebAssemblyInstrFormats.td:59
1067 GT_S_I16x8_S = 1052, // WebAssemblyInstrFormats.td:61
1068 GT_S_I32 = 1053, // WebAssemblyInstrFormats.td:59
1069 GT_S_I32_S = 1054, // WebAssemblyInstrFormats.td:61
1070 GT_S_I32x4 = 1055, // WebAssemblyInstrFormats.td:59
1071 GT_S_I32x4_S = 1056, // WebAssemblyInstrFormats.td:61
1072 GT_S_I64 = 1057, // WebAssemblyInstrFormats.td:59
1073 GT_S_I64_S = 1058, // WebAssemblyInstrFormats.td:61
1074 GT_S_I64x2 = 1059, // WebAssemblyInstrFormats.td:59
1075 GT_S_I64x2_S = 1060, // WebAssemblyInstrFormats.td:61
1076 GT_S_I8x16 = 1061, // WebAssemblyInstrFormats.td:59
1077 GT_S_I8x16_S = 1062, // WebAssemblyInstrFormats.td:61
1078 GT_U_I16x8 = 1063, // WebAssemblyInstrFormats.td:59
1079 GT_U_I16x8_S = 1064, // WebAssemblyInstrFormats.td:61
1080 GT_U_I32 = 1065, // WebAssemblyInstrFormats.td:59
1081 GT_U_I32_S = 1066, // WebAssemblyInstrFormats.td:61
1082 GT_U_I32x4 = 1067, // WebAssemblyInstrFormats.td:59
1083 GT_U_I32x4_S = 1068, // WebAssemblyInstrFormats.td:61
1084 GT_U_I64 = 1069, // WebAssemblyInstrFormats.td:59
1085 GT_U_I64_S = 1070, // WebAssemblyInstrFormats.td:61
1086 GT_U_I8x16 = 1071, // WebAssemblyInstrFormats.td:59
1087 GT_U_I8x16_S = 1072, // WebAssemblyInstrFormats.td:61
1088 I32_EXTEND16_S_I32 = 1073, // WebAssemblyInstrFormats.td:59
1089 I32_EXTEND16_S_I32_S = 1074, // WebAssemblyInstrFormats.td:61
1090 I32_EXTEND8_S_I32 = 1075, // WebAssemblyInstrFormats.td:59
1091 I32_EXTEND8_S_I32_S = 1076, // WebAssemblyInstrFormats.td:61
1092 I32_REINTERPRET_F32 = 1077, // WebAssemblyInstrFormats.td:59
1093 I32_REINTERPRET_F32_S = 1078, // WebAssemblyInstrFormats.td:61
1094 I32_TRUNC_S_F32 = 1079, // WebAssemblyInstrFormats.td:59
1095 I32_TRUNC_S_F32_S = 1080, // WebAssemblyInstrFormats.td:61
1096 I32_TRUNC_S_F64 = 1081, // WebAssemblyInstrFormats.td:59
1097 I32_TRUNC_S_F64_S = 1082, // WebAssemblyInstrFormats.td:61
1098 I32_TRUNC_S_SAT_F32 = 1083, // WebAssemblyInstrFormats.td:59
1099 I32_TRUNC_S_SAT_F32_S = 1084, // WebAssemblyInstrFormats.td:61
1100 I32_TRUNC_S_SAT_F64 = 1085, // WebAssemblyInstrFormats.td:59
1101 I32_TRUNC_S_SAT_F64_S = 1086, // WebAssemblyInstrFormats.td:61
1102 I32_TRUNC_U_F32 = 1087, // WebAssemblyInstrFormats.td:59
1103 I32_TRUNC_U_F32_S = 1088, // WebAssemblyInstrFormats.td:61
1104 I32_TRUNC_U_F64 = 1089, // WebAssemblyInstrFormats.td:59
1105 I32_TRUNC_U_F64_S = 1090, // WebAssemblyInstrFormats.td:61
1106 I32_TRUNC_U_SAT_F32 = 1091, // WebAssemblyInstrFormats.td:59
1107 I32_TRUNC_U_SAT_F32_S = 1092, // WebAssemblyInstrFormats.td:61
1108 I32_TRUNC_U_SAT_F64 = 1093, // WebAssemblyInstrFormats.td:59
1109 I32_TRUNC_U_SAT_F64_S = 1094, // WebAssemblyInstrFormats.td:61
1110 I32_WRAP_I64 = 1095, // WebAssemblyInstrFormats.td:59
1111 I32_WRAP_I64_S = 1096, // WebAssemblyInstrFormats.td:61
1112 I64_ADD128 = 1097, // WebAssemblyInstrFormats.td:59
1113 I64_ADD128_S = 1098, // WebAssemblyInstrFormats.td:61
1114 I64_EXTEND16_S_I64 = 1099, // WebAssemblyInstrFormats.td:59
1115 I64_EXTEND16_S_I64_S = 1100, // WebAssemblyInstrFormats.td:61
1116 I64_EXTEND32_S_I64 = 1101, // WebAssemblyInstrFormats.td:59
1117 I64_EXTEND32_S_I64_S = 1102, // WebAssemblyInstrFormats.td:61
1118 I64_EXTEND8_S_I64 = 1103, // WebAssemblyInstrFormats.td:59
1119 I64_EXTEND8_S_I64_S = 1104, // WebAssemblyInstrFormats.td:61
1120 I64_EXTEND_S_I32 = 1105, // WebAssemblyInstrFormats.td:59
1121 I64_EXTEND_S_I32_S = 1106, // WebAssemblyInstrFormats.td:61
1122 I64_EXTEND_U_I32 = 1107, // WebAssemblyInstrFormats.td:59
1123 I64_EXTEND_U_I32_S = 1108, // WebAssemblyInstrFormats.td:61
1124 I64_MUL_WIDE_S = 1109, // WebAssemblyInstrFormats.td:59
1125 I64_MUL_WIDE_S_S = 1110, // WebAssemblyInstrFormats.td:61
1126 I64_MUL_WIDE_U = 1111, // WebAssemblyInstrFormats.td:59
1127 I64_MUL_WIDE_U_S = 1112, // WebAssemblyInstrFormats.td:61
1128 I64_REINTERPRET_F64 = 1113, // WebAssemblyInstrFormats.td:59
1129 I64_REINTERPRET_F64_S = 1114, // WebAssemblyInstrFormats.td:61
1130 I64_SUB128 = 1115, // WebAssemblyInstrFormats.td:59
1131 I64_SUB128_S = 1116, // WebAssemblyInstrFormats.td:61
1132 I64_TRUNC_S_F32 = 1117, // WebAssemblyInstrFormats.td:59
1133 I64_TRUNC_S_F32_S = 1118, // WebAssemblyInstrFormats.td:61
1134 I64_TRUNC_S_F64 = 1119, // WebAssemblyInstrFormats.td:59
1135 I64_TRUNC_S_F64_S = 1120, // WebAssemblyInstrFormats.td:61
1136 I64_TRUNC_S_SAT_F32 = 1121, // WebAssemblyInstrFormats.td:59
1137 I64_TRUNC_S_SAT_F32_S = 1122, // WebAssemblyInstrFormats.td:61
1138 I64_TRUNC_S_SAT_F64 = 1123, // WebAssemblyInstrFormats.td:59
1139 I64_TRUNC_S_SAT_F64_S = 1124, // WebAssemblyInstrFormats.td:61
1140 I64_TRUNC_U_F32 = 1125, // WebAssemblyInstrFormats.td:59
1141 I64_TRUNC_U_F32_S = 1126, // WebAssemblyInstrFormats.td:61
1142 I64_TRUNC_U_F64 = 1127, // WebAssemblyInstrFormats.td:59
1143 I64_TRUNC_U_F64_S = 1128, // WebAssemblyInstrFormats.td:61
1144 I64_TRUNC_U_SAT_F32 = 1129, // WebAssemblyInstrFormats.td:59
1145 I64_TRUNC_U_SAT_F32_S = 1130, // WebAssemblyInstrFormats.td:61
1146 I64_TRUNC_U_SAT_F64 = 1131, // WebAssemblyInstrFormats.td:59
1147 I64_TRUNC_U_SAT_F64_S = 1132, // WebAssemblyInstrFormats.td:61
1148 IF = 1133, // WebAssemblyInstrFormats.td:59
1149 IF_S = 1134, // WebAssemblyInstrFormats.td:61
1150 LANESELECT_I16x8 = 1135, // WebAssemblyInstrFormats.td:59
1151 LANESELECT_I16x8_S = 1136, // WebAssemblyInstrFormats.td:61
1152 LANESELECT_I32x4 = 1137, // WebAssemblyInstrFormats.td:59
1153 LANESELECT_I32x4_S = 1138, // WebAssemblyInstrFormats.td:61
1154 LANESELECT_I64x2 = 1139, // WebAssemblyInstrFormats.td:59
1155 LANESELECT_I64x2_S = 1140, // WebAssemblyInstrFormats.td:61
1156 LANESELECT_I8x16 = 1141, // WebAssemblyInstrFormats.td:59
1157 LANESELECT_I8x16_S = 1142, // WebAssemblyInstrFormats.td:61
1158 LE_F16x8 = 1143, // WebAssemblyInstrFormats.td:59
1159 LE_F16x8_S = 1144, // WebAssemblyInstrFormats.td:61
1160 LE_F32 = 1145, // WebAssemblyInstrFormats.td:59
1161 LE_F32_S = 1146, // WebAssemblyInstrFormats.td:61
1162 LE_F32x4 = 1147, // WebAssemblyInstrFormats.td:59
1163 LE_F32x4_S = 1148, // WebAssemblyInstrFormats.td:61
1164 LE_F64 = 1149, // WebAssemblyInstrFormats.td:59
1165 LE_F64_S = 1150, // WebAssemblyInstrFormats.td:61
1166 LE_F64x2 = 1151, // WebAssemblyInstrFormats.td:59
1167 LE_F64x2_S = 1152, // WebAssemblyInstrFormats.td:61
1168 LE_S_I16x8 = 1153, // WebAssemblyInstrFormats.td:59
1169 LE_S_I16x8_S = 1154, // WebAssemblyInstrFormats.td:61
1170 LE_S_I32 = 1155, // WebAssemblyInstrFormats.td:59
1171 LE_S_I32_S = 1156, // WebAssemblyInstrFormats.td:61
1172 LE_S_I32x4 = 1157, // WebAssemblyInstrFormats.td:59
1173 LE_S_I32x4_S = 1158, // WebAssemblyInstrFormats.td:61
1174 LE_S_I64 = 1159, // WebAssemblyInstrFormats.td:59
1175 LE_S_I64_S = 1160, // WebAssemblyInstrFormats.td:61
1176 LE_S_I64x2 = 1161, // WebAssemblyInstrFormats.td:59
1177 LE_S_I64x2_S = 1162, // WebAssemblyInstrFormats.td:61
1178 LE_S_I8x16 = 1163, // WebAssemblyInstrFormats.td:59
1179 LE_S_I8x16_S = 1164, // WebAssemblyInstrFormats.td:61
1180 LE_U_I16x8 = 1165, // WebAssemblyInstrFormats.td:59
1181 LE_U_I16x8_S = 1166, // WebAssemblyInstrFormats.td:61
1182 LE_U_I32 = 1167, // WebAssemblyInstrFormats.td:59
1183 LE_U_I32_S = 1168, // WebAssemblyInstrFormats.td:61
1184 LE_U_I32x4 = 1169, // WebAssemblyInstrFormats.td:59
1185 LE_U_I32x4_S = 1170, // WebAssemblyInstrFormats.td:61
1186 LE_U_I64 = 1171, // WebAssemblyInstrFormats.td:59
1187 LE_U_I64_S = 1172, // WebAssemblyInstrFormats.td:61
1188 LE_U_I8x16 = 1173, // WebAssemblyInstrFormats.td:59
1189 LE_U_I8x16_S = 1174, // WebAssemblyInstrFormats.td:61
1190 LOAD16_SPLAT_A32 = 1175, // WebAssemblyInstrFormats.td:59
1191 LOAD16_SPLAT_A32_S = 1176, // WebAssemblyInstrFormats.td:61
1192 LOAD16_SPLAT_A64 = 1177, // WebAssemblyInstrFormats.td:59
1193 LOAD16_SPLAT_A64_S = 1178, // WebAssemblyInstrFormats.td:61
1194 LOAD16_S_I32_A32 = 1179, // WebAssemblyInstrFormats.td:59
1195 LOAD16_S_I32_A32_S = 1180, // WebAssemblyInstrFormats.td:61
1196 LOAD16_S_I32_A64 = 1181, // WebAssemblyInstrFormats.td:59
1197 LOAD16_S_I32_A64_S = 1182, // WebAssemblyInstrFormats.td:61
1198 LOAD16_S_I64_A32 = 1183, // WebAssemblyInstrFormats.td:59
1199 LOAD16_S_I64_A32_S = 1184, // WebAssemblyInstrFormats.td:61
1200 LOAD16_S_I64_A64 = 1185, // WebAssemblyInstrFormats.td:59
1201 LOAD16_S_I64_A64_S = 1186, // WebAssemblyInstrFormats.td:61
1202 LOAD16_U_I32_A32 = 1187, // WebAssemblyInstrFormats.td:59
1203 LOAD16_U_I32_A32_S = 1188, // WebAssemblyInstrFormats.td:61
1204 LOAD16_U_I32_A64 = 1189, // WebAssemblyInstrFormats.td:59
1205 LOAD16_U_I32_A64_S = 1190, // WebAssemblyInstrFormats.td:61
1206 LOAD16_U_I64_A32 = 1191, // WebAssemblyInstrFormats.td:59
1207 LOAD16_U_I64_A32_S = 1192, // WebAssemblyInstrFormats.td:61
1208 LOAD16_U_I64_A64 = 1193, // WebAssemblyInstrFormats.td:59
1209 LOAD16_U_I64_A64_S = 1194, // WebAssemblyInstrFormats.td:61
1210 LOAD32_SPLAT_A32 = 1195, // WebAssemblyInstrFormats.td:59
1211 LOAD32_SPLAT_A32_S = 1196, // WebAssemblyInstrFormats.td:61
1212 LOAD32_SPLAT_A64 = 1197, // WebAssemblyInstrFormats.td:59
1213 LOAD32_SPLAT_A64_S = 1198, // WebAssemblyInstrFormats.td:61
1214 LOAD32_S_I64_A32 = 1199, // WebAssemblyInstrFormats.td:59
1215 LOAD32_S_I64_A32_S = 1200, // WebAssemblyInstrFormats.td:61
1216 LOAD32_S_I64_A64 = 1201, // WebAssemblyInstrFormats.td:59
1217 LOAD32_S_I64_A64_S = 1202, // WebAssemblyInstrFormats.td:61
1218 LOAD32_U_I64_A32 = 1203, // WebAssemblyInstrFormats.td:59
1219 LOAD32_U_I64_A32_S = 1204, // WebAssemblyInstrFormats.td:61
1220 LOAD32_U_I64_A64 = 1205, // WebAssemblyInstrFormats.td:59
1221 LOAD32_U_I64_A64_S = 1206, // WebAssemblyInstrFormats.td:61
1222 LOAD64_SPLAT_A32 = 1207, // WebAssemblyInstrFormats.td:59
1223 LOAD64_SPLAT_A32_S = 1208, // WebAssemblyInstrFormats.td:61
1224 LOAD64_SPLAT_A64 = 1209, // WebAssemblyInstrFormats.td:59
1225 LOAD64_SPLAT_A64_S = 1210, // WebAssemblyInstrFormats.td:61
1226 LOAD8_SPLAT_A32 = 1211, // WebAssemblyInstrFormats.td:59
1227 LOAD8_SPLAT_A32_S = 1212, // WebAssemblyInstrFormats.td:61
1228 LOAD8_SPLAT_A64 = 1213, // WebAssemblyInstrFormats.td:59
1229 LOAD8_SPLAT_A64_S = 1214, // WebAssemblyInstrFormats.td:61
1230 LOAD8_S_I32_A32 = 1215, // WebAssemblyInstrFormats.td:59
1231 LOAD8_S_I32_A32_S = 1216, // WebAssemblyInstrFormats.td:61
1232 LOAD8_S_I32_A64 = 1217, // WebAssemblyInstrFormats.td:59
1233 LOAD8_S_I32_A64_S = 1218, // WebAssemblyInstrFormats.td:61
1234 LOAD8_S_I64_A32 = 1219, // WebAssemblyInstrFormats.td:59
1235 LOAD8_S_I64_A32_S = 1220, // WebAssemblyInstrFormats.td:61
1236 LOAD8_S_I64_A64 = 1221, // WebAssemblyInstrFormats.td:59
1237 LOAD8_S_I64_A64_S = 1222, // WebAssemblyInstrFormats.td:61
1238 LOAD8_U_I32_A32 = 1223, // WebAssemblyInstrFormats.td:59
1239 LOAD8_U_I32_A32_S = 1224, // WebAssemblyInstrFormats.td:61
1240 LOAD8_U_I32_A64 = 1225, // WebAssemblyInstrFormats.td:59
1241 LOAD8_U_I32_A64_S = 1226, // WebAssemblyInstrFormats.td:61
1242 LOAD8_U_I64_A32 = 1227, // WebAssemblyInstrFormats.td:59
1243 LOAD8_U_I64_A32_S = 1228, // WebAssemblyInstrFormats.td:61
1244 LOAD8_U_I64_A64 = 1229, // WebAssemblyInstrFormats.td:59
1245 LOAD8_U_I64_A64_S = 1230, // WebAssemblyInstrFormats.td:61
1246 LOAD_EXTEND_S_I16x8_A32 = 1231, // WebAssemblyInstrFormats.td:59
1247 LOAD_EXTEND_S_I16x8_A32_S = 1232, // WebAssemblyInstrFormats.td:61
1248 LOAD_EXTEND_S_I16x8_A64 = 1233, // WebAssemblyInstrFormats.td:59
1249 LOAD_EXTEND_S_I16x8_A64_S = 1234, // WebAssemblyInstrFormats.td:61
1250 LOAD_EXTEND_S_I32x4_A32 = 1235, // WebAssemblyInstrFormats.td:59
1251 LOAD_EXTEND_S_I32x4_A32_S = 1236, // WebAssemblyInstrFormats.td:61
1252 LOAD_EXTEND_S_I32x4_A64 = 1237, // WebAssemblyInstrFormats.td:59
1253 LOAD_EXTEND_S_I32x4_A64_S = 1238, // WebAssemblyInstrFormats.td:61
1254 LOAD_EXTEND_S_I64x2_A32 = 1239, // WebAssemblyInstrFormats.td:59
1255 LOAD_EXTEND_S_I64x2_A32_S = 1240, // WebAssemblyInstrFormats.td:61
1256 LOAD_EXTEND_S_I64x2_A64 = 1241, // WebAssemblyInstrFormats.td:59
1257 LOAD_EXTEND_S_I64x2_A64_S = 1242, // WebAssemblyInstrFormats.td:61
1258 LOAD_EXTEND_U_I16x8_A32 = 1243, // WebAssemblyInstrFormats.td:59
1259 LOAD_EXTEND_U_I16x8_A32_S = 1244, // WebAssemblyInstrFormats.td:61
1260 LOAD_EXTEND_U_I16x8_A64 = 1245, // WebAssemblyInstrFormats.td:59
1261 LOAD_EXTEND_U_I16x8_A64_S = 1246, // WebAssemblyInstrFormats.td:61
1262 LOAD_EXTEND_U_I32x4_A32 = 1247, // WebAssemblyInstrFormats.td:59
1263 LOAD_EXTEND_U_I32x4_A32_S = 1248, // WebAssemblyInstrFormats.td:61
1264 LOAD_EXTEND_U_I32x4_A64 = 1249, // WebAssemblyInstrFormats.td:59
1265 LOAD_EXTEND_U_I32x4_A64_S = 1250, // WebAssemblyInstrFormats.td:61
1266 LOAD_EXTEND_U_I64x2_A32 = 1251, // WebAssemblyInstrFormats.td:59
1267 LOAD_EXTEND_U_I64x2_A32_S = 1252, // WebAssemblyInstrFormats.td:61
1268 LOAD_EXTEND_U_I64x2_A64 = 1253, // WebAssemblyInstrFormats.td:59
1269 LOAD_EXTEND_U_I64x2_A64_S = 1254, // WebAssemblyInstrFormats.td:61
1270 LOAD_F16_F32_A32 = 1255, // WebAssemblyInstrFormats.td:59
1271 LOAD_F16_F32_A32_S = 1256, // WebAssemblyInstrFormats.td:61
1272 LOAD_F16_F32_A64 = 1257, // WebAssemblyInstrFormats.td:59
1273 LOAD_F16_F32_A64_S = 1258, // WebAssemblyInstrFormats.td:61
1274 LOAD_F32_A32 = 1259, // WebAssemblyInstrFormats.td:59
1275 LOAD_F32_A32_S = 1260, // WebAssemblyInstrFormats.td:61
1276 LOAD_F32_A64 = 1261, // WebAssemblyInstrFormats.td:59
1277 LOAD_F32_A64_S = 1262, // WebAssemblyInstrFormats.td:61
1278 LOAD_F64_A32 = 1263, // WebAssemblyInstrFormats.td:59
1279 LOAD_F64_A32_S = 1264, // WebAssemblyInstrFormats.td:61
1280 LOAD_F64_A64 = 1265, // WebAssemblyInstrFormats.td:59
1281 LOAD_F64_A64_S = 1266, // WebAssemblyInstrFormats.td:61
1282 LOAD_I32_A32 = 1267, // WebAssemblyInstrFormats.td:59
1283 LOAD_I32_A32_S = 1268, // WebAssemblyInstrFormats.td:61
1284 LOAD_I32_A64 = 1269, // WebAssemblyInstrFormats.td:59
1285 LOAD_I32_A64_S = 1270, // WebAssemblyInstrFormats.td:61
1286 LOAD_I64_A32 = 1271, // WebAssemblyInstrFormats.td:59
1287 LOAD_I64_A32_S = 1272, // WebAssemblyInstrFormats.td:61
1288 LOAD_I64_A64 = 1273, // WebAssemblyInstrFormats.td:59
1289 LOAD_I64_A64_S = 1274, // WebAssemblyInstrFormats.td:61
1290 LOAD_LANE_16_A32 = 1275, // WebAssemblyInstrFormats.td:59
1291 LOAD_LANE_16_A32_S = 1276, // WebAssemblyInstrFormats.td:61
1292 LOAD_LANE_16_A64 = 1277, // WebAssemblyInstrFormats.td:59
1293 LOAD_LANE_16_A64_S = 1278, // WebAssemblyInstrFormats.td:61
1294 LOAD_LANE_32_A32 = 1279, // WebAssemblyInstrFormats.td:59
1295 LOAD_LANE_32_A32_S = 1280, // WebAssemblyInstrFormats.td:61
1296 LOAD_LANE_32_A64 = 1281, // WebAssemblyInstrFormats.td:59
1297 LOAD_LANE_32_A64_S = 1282, // WebAssemblyInstrFormats.td:61
1298 LOAD_LANE_64_A32 = 1283, // WebAssemblyInstrFormats.td:59
1299 LOAD_LANE_64_A32_S = 1284, // WebAssemblyInstrFormats.td:61
1300 LOAD_LANE_64_A64 = 1285, // WebAssemblyInstrFormats.td:59
1301 LOAD_LANE_64_A64_S = 1286, // WebAssemblyInstrFormats.td:61
1302 LOAD_LANE_8_A32 = 1287, // WebAssemblyInstrFormats.td:59
1303 LOAD_LANE_8_A32_S = 1288, // WebAssemblyInstrFormats.td:61
1304 LOAD_LANE_8_A64 = 1289, // WebAssemblyInstrFormats.td:59
1305 LOAD_LANE_8_A64_S = 1290, // WebAssemblyInstrFormats.td:61
1306 LOAD_V128_A32 = 1291, // WebAssemblyInstrFormats.td:59
1307 LOAD_V128_A32_S = 1292, // WebAssemblyInstrFormats.td:61
1308 LOAD_V128_A64 = 1293, // WebAssemblyInstrFormats.td:59
1309 LOAD_V128_A64_S = 1294, // WebAssemblyInstrFormats.td:61
1310 LOAD_ZERO_32_A32 = 1295, // WebAssemblyInstrFormats.td:59
1311 LOAD_ZERO_32_A32_S = 1296, // WebAssemblyInstrFormats.td:61
1312 LOAD_ZERO_32_A64 = 1297, // WebAssemblyInstrFormats.td:59
1313 LOAD_ZERO_32_A64_S = 1298, // WebAssemblyInstrFormats.td:61
1314 LOAD_ZERO_64_A32 = 1299, // WebAssemblyInstrFormats.td:59
1315 LOAD_ZERO_64_A32_S = 1300, // WebAssemblyInstrFormats.td:61
1316 LOAD_ZERO_64_A64 = 1301, // WebAssemblyInstrFormats.td:59
1317 LOAD_ZERO_64_A64_S = 1302, // WebAssemblyInstrFormats.td:61
1318 LOCAL_GET_EXNREF = 1303, // WebAssemblyInstrFormats.td:59
1319 LOCAL_GET_EXNREF_S = 1304, // WebAssemblyInstrFormats.td:61
1320 LOCAL_GET_EXTERNREF = 1305, // WebAssemblyInstrFormats.td:59
1321 LOCAL_GET_EXTERNREF_S = 1306, // WebAssemblyInstrFormats.td:61
1322 LOCAL_GET_F32 = 1307, // WebAssemblyInstrFormats.td:59
1323 LOCAL_GET_F32_S = 1308, // WebAssemblyInstrFormats.td:61
1324 LOCAL_GET_F64 = 1309, // WebAssemblyInstrFormats.td:59
1325 LOCAL_GET_F64_S = 1310, // WebAssemblyInstrFormats.td:61
1326 LOCAL_GET_FUNCREF = 1311, // WebAssemblyInstrFormats.td:59
1327 LOCAL_GET_FUNCREF_S = 1312, // WebAssemblyInstrFormats.td:61
1328 LOCAL_GET_I32 = 1313, // WebAssemblyInstrFormats.td:59
1329 LOCAL_GET_I32_S = 1314, // WebAssemblyInstrFormats.td:61
1330 LOCAL_GET_I64 = 1315, // WebAssemblyInstrFormats.td:59
1331 LOCAL_GET_I64_S = 1316, // WebAssemblyInstrFormats.td:61
1332 LOCAL_GET_V128 = 1317, // WebAssemblyInstrFormats.td:59
1333 LOCAL_GET_V128_S = 1318, // WebAssemblyInstrFormats.td:61
1334 LOCAL_SET_EXNREF = 1319, // WebAssemblyInstrFormats.td:59
1335 LOCAL_SET_EXNREF_S = 1320, // WebAssemblyInstrFormats.td:61
1336 LOCAL_SET_EXTERNREF = 1321, // WebAssemblyInstrFormats.td:59
1337 LOCAL_SET_EXTERNREF_S = 1322, // WebAssemblyInstrFormats.td:61
1338 LOCAL_SET_F32 = 1323, // WebAssemblyInstrFormats.td:59
1339 LOCAL_SET_F32_S = 1324, // WebAssemblyInstrFormats.td:61
1340 LOCAL_SET_F64 = 1325, // WebAssemblyInstrFormats.td:59
1341 LOCAL_SET_F64_S = 1326, // WebAssemblyInstrFormats.td:61
1342 LOCAL_SET_FUNCREF = 1327, // WebAssemblyInstrFormats.td:59
1343 LOCAL_SET_FUNCREF_S = 1328, // WebAssemblyInstrFormats.td:61
1344 LOCAL_SET_I32 = 1329, // WebAssemblyInstrFormats.td:59
1345 LOCAL_SET_I32_S = 1330, // WebAssemblyInstrFormats.td:61
1346 LOCAL_SET_I64 = 1331, // WebAssemblyInstrFormats.td:59
1347 LOCAL_SET_I64_S = 1332, // WebAssemblyInstrFormats.td:61
1348 LOCAL_SET_V128 = 1333, // WebAssemblyInstrFormats.td:59
1349 LOCAL_SET_V128_S = 1334, // WebAssemblyInstrFormats.td:61
1350 LOCAL_TEE_EXNREF = 1335, // WebAssemblyInstrFormats.td:59
1351 LOCAL_TEE_EXNREF_S = 1336, // WebAssemblyInstrFormats.td:61
1352 LOCAL_TEE_EXTERNREF = 1337, // WebAssemblyInstrFormats.td:59
1353 LOCAL_TEE_EXTERNREF_S = 1338, // WebAssemblyInstrFormats.td:61
1354 LOCAL_TEE_F32 = 1339, // WebAssemblyInstrFormats.td:59
1355 LOCAL_TEE_F32_S = 1340, // WebAssemblyInstrFormats.td:61
1356 LOCAL_TEE_F64 = 1341, // WebAssemblyInstrFormats.td:59
1357 LOCAL_TEE_F64_S = 1342, // WebAssemblyInstrFormats.td:61
1358 LOCAL_TEE_FUNCREF = 1343, // WebAssemblyInstrFormats.td:59
1359 LOCAL_TEE_FUNCREF_S = 1344, // WebAssemblyInstrFormats.td:61
1360 LOCAL_TEE_I32 = 1345, // WebAssemblyInstrFormats.td:59
1361 LOCAL_TEE_I32_S = 1346, // WebAssemblyInstrFormats.td:61
1362 LOCAL_TEE_I64 = 1347, // WebAssemblyInstrFormats.td:59
1363 LOCAL_TEE_I64_S = 1348, // WebAssemblyInstrFormats.td:61
1364 LOCAL_TEE_V128 = 1349, // WebAssemblyInstrFormats.td:59
1365 LOCAL_TEE_V128_S = 1350, // WebAssemblyInstrFormats.td:61
1366 LOOP = 1351, // WebAssemblyInstrFormats.td:59
1367 LOOP_S = 1352, // WebAssemblyInstrFormats.td:61
1368 LT_F16x8 = 1353, // WebAssemblyInstrFormats.td:59
1369 LT_F16x8_S = 1354, // WebAssemblyInstrFormats.td:61
1370 LT_F32 = 1355, // WebAssemblyInstrFormats.td:59
1371 LT_F32_S = 1356, // WebAssemblyInstrFormats.td:61
1372 LT_F32x4 = 1357, // WebAssemblyInstrFormats.td:59
1373 LT_F32x4_S = 1358, // WebAssemblyInstrFormats.td:61
1374 LT_F64 = 1359, // WebAssemblyInstrFormats.td:59
1375 LT_F64_S = 1360, // WebAssemblyInstrFormats.td:61
1376 LT_F64x2 = 1361, // WebAssemblyInstrFormats.td:59
1377 LT_F64x2_S = 1362, // WebAssemblyInstrFormats.td:61
1378 LT_S_I16x8 = 1363, // WebAssemblyInstrFormats.td:59
1379 LT_S_I16x8_S = 1364, // WebAssemblyInstrFormats.td:61
1380 LT_S_I32 = 1365, // WebAssemblyInstrFormats.td:59
1381 LT_S_I32_S = 1366, // WebAssemblyInstrFormats.td:61
1382 LT_S_I32x4 = 1367, // WebAssemblyInstrFormats.td:59
1383 LT_S_I32x4_S = 1368, // WebAssemblyInstrFormats.td:61
1384 LT_S_I64 = 1369, // WebAssemblyInstrFormats.td:59
1385 LT_S_I64_S = 1370, // WebAssemblyInstrFormats.td:61
1386 LT_S_I64x2 = 1371, // WebAssemblyInstrFormats.td:59
1387 LT_S_I64x2_S = 1372, // WebAssemblyInstrFormats.td:61
1388 LT_S_I8x16 = 1373, // WebAssemblyInstrFormats.td:59
1389 LT_S_I8x16_S = 1374, // WebAssemblyInstrFormats.td:61
1390 LT_U_I16x8 = 1375, // WebAssemblyInstrFormats.td:59
1391 LT_U_I16x8_S = 1376, // WebAssemblyInstrFormats.td:61
1392 LT_U_I32 = 1377, // WebAssemblyInstrFormats.td:59
1393 LT_U_I32_S = 1378, // WebAssemblyInstrFormats.td:61
1394 LT_U_I32x4 = 1379, // WebAssemblyInstrFormats.td:59
1395 LT_U_I32x4_S = 1380, // WebAssemblyInstrFormats.td:61
1396 LT_U_I64 = 1381, // WebAssemblyInstrFormats.td:59
1397 LT_U_I64_S = 1382, // WebAssemblyInstrFormats.td:61
1398 LT_U_I8x16 = 1383, // WebAssemblyInstrFormats.td:59
1399 LT_U_I8x16_S = 1384, // WebAssemblyInstrFormats.td:61
1400 MADD_F16x8 = 1385, // WebAssemblyInstrFormats.td:59
1401 MADD_F16x8_S = 1386, // WebAssemblyInstrFormats.td:61
1402 MADD_F32x4 = 1387, // WebAssemblyInstrFormats.td:59
1403 MADD_F32x4_S = 1388, // WebAssemblyInstrFormats.td:61
1404 MADD_F64x2 = 1389, // WebAssemblyInstrFormats.td:59
1405 MADD_F64x2_S = 1390, // WebAssemblyInstrFormats.td:61
1406 MAX_F16x8 = 1391, // WebAssemblyInstrFormats.td:59
1407 MAX_F16x8_S = 1392, // WebAssemblyInstrFormats.td:61
1408 MAX_F32 = 1393, // WebAssemblyInstrFormats.td:59
1409 MAX_F32_S = 1394, // WebAssemblyInstrFormats.td:61
1410 MAX_F32x4 = 1395, // WebAssemblyInstrFormats.td:59
1411 MAX_F32x4_S = 1396, // WebAssemblyInstrFormats.td:61
1412 MAX_F64 = 1397, // WebAssemblyInstrFormats.td:59
1413 MAX_F64_S = 1398, // WebAssemblyInstrFormats.td:61
1414 MAX_F64x2 = 1399, // WebAssemblyInstrFormats.td:59
1415 MAX_F64x2_S = 1400, // WebAssemblyInstrFormats.td:61
1416 MAX_S_I16x8 = 1401, // WebAssemblyInstrFormats.td:59
1417 MAX_S_I16x8_S = 1402, // WebAssemblyInstrFormats.td:61
1418 MAX_S_I32x4 = 1403, // WebAssemblyInstrFormats.td:59
1419 MAX_S_I32x4_S = 1404, // WebAssemblyInstrFormats.td:61
1420 MAX_S_I8x16 = 1405, // WebAssemblyInstrFormats.td:59
1421 MAX_S_I8x16_S = 1406, // WebAssemblyInstrFormats.td:61
1422 MAX_U_I16x8 = 1407, // WebAssemblyInstrFormats.td:59
1423 MAX_U_I16x8_S = 1408, // WebAssemblyInstrFormats.td:61
1424 MAX_U_I32x4 = 1409, // WebAssemblyInstrFormats.td:59
1425 MAX_U_I32x4_S = 1410, // WebAssemblyInstrFormats.td:61
1426 MAX_U_I8x16 = 1411, // WebAssemblyInstrFormats.td:59
1427 MAX_U_I8x16_S = 1412, // WebAssemblyInstrFormats.td:61
1428 MEMCPY_A32 = 1413, // WebAssemblyInstrFormats.td:59
1429 MEMCPY_A32_S = 1414, // WebAssemblyInstrFormats.td:61
1430 MEMCPY_A64 = 1415, // WebAssemblyInstrFormats.td:59
1431 MEMCPY_A64_S = 1416, // WebAssemblyInstrFormats.td:61
1432 MEMORY_ATOMIC_NOTIFY_A32 = 1417, // WebAssemblyInstrFormats.td:59
1433 MEMORY_ATOMIC_NOTIFY_A32_S = 1418, // WebAssemblyInstrFormats.td:61
1434 MEMORY_ATOMIC_NOTIFY_A64 = 1419, // WebAssemblyInstrFormats.td:59
1435 MEMORY_ATOMIC_NOTIFY_A64_S = 1420, // WebAssemblyInstrFormats.td:61
1436 MEMORY_ATOMIC_WAIT32_A32 = 1421, // WebAssemblyInstrFormats.td:59
1437 MEMORY_ATOMIC_WAIT32_A32_S = 1422, // WebAssemblyInstrFormats.td:61
1438 MEMORY_ATOMIC_WAIT32_A64 = 1423, // WebAssemblyInstrFormats.td:59
1439 MEMORY_ATOMIC_WAIT32_A64_S = 1424, // WebAssemblyInstrFormats.td:61
1440 MEMORY_ATOMIC_WAIT64_A32 = 1425, // WebAssemblyInstrFormats.td:59
1441 MEMORY_ATOMIC_WAIT64_A32_S = 1426, // WebAssemblyInstrFormats.td:61
1442 MEMORY_ATOMIC_WAIT64_A64 = 1427, // WebAssemblyInstrFormats.td:59
1443 MEMORY_ATOMIC_WAIT64_A64_S = 1428, // WebAssemblyInstrFormats.td:61
1444 MEMORY_COPY_A32 = 1429, // WebAssemblyInstrFormats.td:59
1445 MEMORY_COPY_A32_S = 1430, // WebAssemblyInstrFormats.td:61
1446 MEMORY_COPY_A64 = 1431, // WebAssemblyInstrFormats.td:59
1447 MEMORY_COPY_A64_S = 1432, // WebAssemblyInstrFormats.td:61
1448 MEMORY_FILL_A32 = 1433, // WebAssemblyInstrFormats.td:59
1449 MEMORY_FILL_A32_S = 1434, // WebAssemblyInstrFormats.td:61
1450 MEMORY_FILL_A64 = 1435, // WebAssemblyInstrFormats.td:59
1451 MEMORY_FILL_A64_S = 1436, // WebAssemblyInstrFormats.td:61
1452 MEMORY_INIT_A32 = 1437, // WebAssemblyInstrFormats.td:59
1453 MEMORY_INIT_A32_S = 1438, // WebAssemblyInstrFormats.td:61
1454 MEMORY_INIT_A64 = 1439, // WebAssemblyInstrFormats.td:59
1455 MEMORY_INIT_A64_S = 1440, // WebAssemblyInstrFormats.td:61
1456 MEMSET_A32 = 1441, // WebAssemblyInstrFormats.td:59
1457 MEMSET_A32_S = 1442, // WebAssemblyInstrFormats.td:61
1458 MEMSET_A64 = 1443, // WebAssemblyInstrFormats.td:59
1459 MEMSET_A64_S = 1444, // WebAssemblyInstrFormats.td:61
1460 MIN_F16x8 = 1445, // WebAssemblyInstrFormats.td:59
1461 MIN_F16x8_S = 1446, // WebAssemblyInstrFormats.td:61
1462 MIN_F32 = 1447, // WebAssemblyInstrFormats.td:59
1463 MIN_F32_S = 1448, // WebAssemblyInstrFormats.td:61
1464 MIN_F32x4 = 1449, // WebAssemblyInstrFormats.td:59
1465 MIN_F32x4_S = 1450, // WebAssemblyInstrFormats.td:61
1466 MIN_F64 = 1451, // WebAssemblyInstrFormats.td:59
1467 MIN_F64_S = 1452, // WebAssemblyInstrFormats.td:61
1468 MIN_F64x2 = 1453, // WebAssemblyInstrFormats.td:59
1469 MIN_F64x2_S = 1454, // WebAssemblyInstrFormats.td:61
1470 MIN_S_I16x8 = 1455, // WebAssemblyInstrFormats.td:59
1471 MIN_S_I16x8_S = 1456, // WebAssemblyInstrFormats.td:61
1472 MIN_S_I32x4 = 1457, // WebAssemblyInstrFormats.td:59
1473 MIN_S_I32x4_S = 1458, // WebAssemblyInstrFormats.td:61
1474 MIN_S_I8x16 = 1459, // WebAssemblyInstrFormats.td:59
1475 MIN_S_I8x16_S = 1460, // WebAssemblyInstrFormats.td:61
1476 MIN_U_I16x8 = 1461, // WebAssemblyInstrFormats.td:59
1477 MIN_U_I16x8_S = 1462, // WebAssemblyInstrFormats.td:61
1478 MIN_U_I32x4 = 1463, // WebAssemblyInstrFormats.td:59
1479 MIN_U_I32x4_S = 1464, // WebAssemblyInstrFormats.td:61
1480 MIN_U_I8x16 = 1465, // WebAssemblyInstrFormats.td:59
1481 MIN_U_I8x16_S = 1466, // WebAssemblyInstrFormats.td:61
1482 MUL_F16x8 = 1467, // WebAssemblyInstrFormats.td:59
1483 MUL_F16x8_S = 1468, // WebAssemblyInstrFormats.td:61
1484 MUL_F32 = 1469, // WebAssemblyInstrFormats.td:59
1485 MUL_F32_S = 1470, // WebAssemblyInstrFormats.td:61
1486 MUL_F32x4 = 1471, // WebAssemblyInstrFormats.td:59
1487 MUL_F32x4_S = 1472, // WebAssemblyInstrFormats.td:61
1488 MUL_F64 = 1473, // WebAssemblyInstrFormats.td:59
1489 MUL_F64_S = 1474, // WebAssemblyInstrFormats.td:61
1490 MUL_F64x2 = 1475, // WebAssemblyInstrFormats.td:59
1491 MUL_F64x2_S = 1476, // WebAssemblyInstrFormats.td:61
1492 MUL_I16x8 = 1477, // WebAssemblyInstrFormats.td:59
1493 MUL_I16x8_S = 1478, // WebAssemblyInstrFormats.td:61
1494 MUL_I32 = 1479, // WebAssemblyInstrFormats.td:59
1495 MUL_I32_S = 1480, // WebAssemblyInstrFormats.td:61
1496 MUL_I32x4 = 1481, // WebAssemblyInstrFormats.td:59
1497 MUL_I32x4_S = 1482, // WebAssemblyInstrFormats.td:61
1498 MUL_I64 = 1483, // WebAssemblyInstrFormats.td:59
1499 MUL_I64_S = 1484, // WebAssemblyInstrFormats.td:61
1500 MUL_I64x2 = 1485, // WebAssemblyInstrFormats.td:59
1501 MUL_I64x2_S = 1486, // WebAssemblyInstrFormats.td:61
1502 NARROW_S_I16x8 = 1487, // WebAssemblyInstrFormats.td:59
1503 NARROW_S_I16x8_S = 1488, // WebAssemblyInstrFormats.td:61
1504 NARROW_S_I8x16 = 1489, // WebAssemblyInstrFormats.td:59
1505 NARROW_S_I8x16_S = 1490, // WebAssemblyInstrFormats.td:61
1506 NARROW_U_I16x8 = 1491, // WebAssemblyInstrFormats.td:59
1507 NARROW_U_I16x8_S = 1492, // WebAssemblyInstrFormats.td:61
1508 NARROW_U_I8x16 = 1493, // WebAssemblyInstrFormats.td:59
1509 NARROW_U_I8x16_S = 1494, // WebAssemblyInstrFormats.td:61
1510 NEAREST_F16x8 = 1495, // WebAssemblyInstrFormats.td:59
1511 NEAREST_F16x8_S = 1496, // WebAssemblyInstrFormats.td:61
1512 NEAREST_F32 = 1497, // WebAssemblyInstrFormats.td:59
1513 NEAREST_F32_S = 1498, // WebAssemblyInstrFormats.td:61
1514 NEAREST_F32x4 = 1499, // WebAssemblyInstrFormats.td:59
1515 NEAREST_F32x4_S = 1500, // WebAssemblyInstrFormats.td:61
1516 NEAREST_F64 = 1501, // WebAssemblyInstrFormats.td:59
1517 NEAREST_F64_S = 1502, // WebAssemblyInstrFormats.td:61
1518 NEAREST_F64x2 = 1503, // WebAssemblyInstrFormats.td:59
1519 NEAREST_F64x2_S = 1504, // WebAssemblyInstrFormats.td:61
1520 NEG_F16x8 = 1505, // WebAssemblyInstrFormats.td:59
1521 NEG_F16x8_S = 1506, // WebAssemblyInstrFormats.td:61
1522 NEG_F32 = 1507, // WebAssemblyInstrFormats.td:59
1523 NEG_F32_S = 1508, // WebAssemblyInstrFormats.td:61
1524 NEG_F32x4 = 1509, // WebAssemblyInstrFormats.td:59
1525 NEG_F32x4_S = 1510, // WebAssemblyInstrFormats.td:61
1526 NEG_F64 = 1511, // WebAssemblyInstrFormats.td:59
1527 NEG_F64_S = 1512, // WebAssemblyInstrFormats.td:61
1528 NEG_F64x2 = 1513, // WebAssemblyInstrFormats.td:59
1529 NEG_F64x2_S = 1514, // WebAssemblyInstrFormats.td:61
1530 NEG_I16x8 = 1515, // WebAssemblyInstrFormats.td:59
1531 NEG_I16x8_S = 1516, // WebAssemblyInstrFormats.td:61
1532 NEG_I32x4 = 1517, // WebAssemblyInstrFormats.td:59
1533 NEG_I32x4_S = 1518, // WebAssemblyInstrFormats.td:61
1534 NEG_I64x2 = 1519, // WebAssemblyInstrFormats.td:59
1535 NEG_I64x2_S = 1520, // WebAssemblyInstrFormats.td:61
1536 NEG_I8x16 = 1521, // WebAssemblyInstrFormats.td:59
1537 NEG_I8x16_S = 1522, // WebAssemblyInstrFormats.td:61
1538 NE_F16x8 = 1523, // WebAssemblyInstrFormats.td:59
1539 NE_F16x8_S = 1524, // WebAssemblyInstrFormats.td:61
1540 NE_F32 = 1525, // WebAssemblyInstrFormats.td:59
1541 NE_F32_S = 1526, // WebAssemblyInstrFormats.td:61
1542 NE_F32x4 = 1527, // WebAssemblyInstrFormats.td:59
1543 NE_F32x4_S = 1528, // WebAssemblyInstrFormats.td:61
1544 NE_F64 = 1529, // WebAssemblyInstrFormats.td:59
1545 NE_F64_S = 1530, // WebAssemblyInstrFormats.td:61
1546 NE_F64x2 = 1531, // WebAssemblyInstrFormats.td:59
1547 NE_F64x2_S = 1532, // WebAssemblyInstrFormats.td:61
1548 NE_I16x8 = 1533, // WebAssemblyInstrFormats.td:59
1549 NE_I16x8_S = 1534, // WebAssemblyInstrFormats.td:61
1550 NE_I32 = 1535, // WebAssemblyInstrFormats.td:59
1551 NE_I32_S = 1536, // WebAssemblyInstrFormats.td:61
1552 NE_I32x4 = 1537, // WebAssemblyInstrFormats.td:59
1553 NE_I32x4_S = 1538, // WebAssemblyInstrFormats.td:61
1554 NE_I64 = 1539, // WebAssemblyInstrFormats.td:59
1555 NE_I64_S = 1540, // WebAssemblyInstrFormats.td:61
1556 NE_I64x2 = 1541, // WebAssemblyInstrFormats.td:59
1557 NE_I64x2_S = 1542, // WebAssemblyInstrFormats.td:61
1558 NE_I8x16 = 1543, // WebAssemblyInstrFormats.td:59
1559 NE_I8x16_S = 1544, // WebAssemblyInstrFormats.td:61
1560 NMADD_F16x8 = 1545, // WebAssemblyInstrFormats.td:59
1561 NMADD_F16x8_S = 1546, // WebAssemblyInstrFormats.td:61
1562 NMADD_F32x4 = 1547, // WebAssemblyInstrFormats.td:59
1563 NMADD_F32x4_S = 1548, // WebAssemblyInstrFormats.td:61
1564 NMADD_F64x2 = 1549, // WebAssemblyInstrFormats.td:59
1565 NMADD_F64x2_S = 1550, // WebAssemblyInstrFormats.td:61
1566 NOP = 1551, // WebAssemblyInstrFormats.td:59
1567 NOP_S = 1552, // WebAssemblyInstrFormats.td:61
1568 NOT = 1553, // WebAssemblyInstrFormats.td:59
1569 NOT_S = 1554, // WebAssemblyInstrFormats.td:61
1570 OR = 1555, // WebAssemblyInstrFormats.td:59
1571 OR_I32 = 1556, // WebAssemblyInstrFormats.td:59
1572 OR_I32_S = 1557, // WebAssemblyInstrFormats.td:61
1573 OR_I64 = 1558, // WebAssemblyInstrFormats.td:59
1574 OR_I64_S = 1559, // WebAssemblyInstrFormats.td:61
1575 OR_S = 1560, // WebAssemblyInstrFormats.td:61
1576 PMAX_F16x8 = 1561, // WebAssemblyInstrFormats.td:59
1577 PMAX_F16x8_S = 1562, // WebAssemblyInstrFormats.td:61
1578 PMAX_F32x4 = 1563, // WebAssemblyInstrFormats.td:59
1579 PMAX_F32x4_S = 1564, // WebAssemblyInstrFormats.td:61
1580 PMAX_F64x2 = 1565, // WebAssemblyInstrFormats.td:59
1581 PMAX_F64x2_S = 1566, // WebAssemblyInstrFormats.td:61
1582 PMIN_F16x8 = 1567, // WebAssemblyInstrFormats.td:59
1583 PMIN_F16x8_S = 1568, // WebAssemblyInstrFormats.td:61
1584 PMIN_F32x4 = 1569, // WebAssemblyInstrFormats.td:59
1585 PMIN_F32x4_S = 1570, // WebAssemblyInstrFormats.td:61
1586 PMIN_F64x2 = 1571, // WebAssemblyInstrFormats.td:59
1587 PMIN_F64x2_S = 1572, // WebAssemblyInstrFormats.td:61
1588 POPCNT_I32 = 1573, // WebAssemblyInstrFormats.td:59
1589 POPCNT_I32_S = 1574, // WebAssemblyInstrFormats.td:61
1590 POPCNT_I64 = 1575, // WebAssemblyInstrFormats.td:59
1591 POPCNT_I64_S = 1576, // WebAssemblyInstrFormats.td:61
1592 POPCNT_I8x16 = 1577, // WebAssemblyInstrFormats.td:59
1593 POPCNT_I8x16_S = 1578, // WebAssemblyInstrFormats.td:61
1594 Q15MULR_SAT_S_I16x8 = 1579, // WebAssemblyInstrFormats.td:59
1595 Q15MULR_SAT_S_I16x8_S = 1580, // WebAssemblyInstrFormats.td:61
1596 REF_CAST_FUNCREF = 1581, // WebAssemblyInstrFormats.td:59
1597 REF_CAST_FUNCREF_S = 1582, // WebAssemblyInstrFormats.td:61
1598 REF_FUNC = 1583, // WebAssemblyInstrFormats.td:59
1599 REF_FUNC_S = 1584, // WebAssemblyInstrFormats.td:61
1600 REF_IS_NULL_EXNREF = 1585, // WebAssemblyInstrFormats.td:59
1601 REF_IS_NULL_EXNREF_S = 1586, // WebAssemblyInstrFormats.td:61
1602 REF_IS_NULL_EXTERNREF = 1587, // WebAssemblyInstrFormats.td:59
1603 REF_IS_NULL_EXTERNREF_S = 1588, // WebAssemblyInstrFormats.td:61
1604 REF_IS_NULL_FUNCREF = 1589, // WebAssemblyInstrFormats.td:59
1605 REF_IS_NULL_FUNCREF_S = 1590, // WebAssemblyInstrFormats.td:61
1606 REF_NULL_EXNREF = 1591, // WebAssemblyInstrFormats.td:59
1607 REF_NULL_EXNREF_S = 1592, // WebAssemblyInstrFormats.td:61
1608 REF_NULL_EXTERNREF = 1593, // WebAssemblyInstrFormats.td:59
1609 REF_NULL_EXTERNREF_S = 1594, // WebAssemblyInstrFormats.td:61
1610 REF_NULL_FUNCREF = 1595, // WebAssemblyInstrFormats.td:59
1611 REF_NULL_FUNCREF_S = 1596, // WebAssemblyInstrFormats.td:61
1612 REF_TEST_FUNCREF = 1597, // WebAssemblyInstrFormats.td:59
1613 REF_TEST_FUNCREF_S = 1598, // WebAssemblyInstrFormats.td:61
1614 RELAXED_DOT = 1599, // WebAssemblyInstrFormats.td:59
1615 RELAXED_DOT_ADD = 1600, // WebAssemblyInstrFormats.td:59
1616 RELAXED_DOT_ADD_S = 1601, // WebAssemblyInstrFormats.td:61
1617 RELAXED_DOT_BFLOAT = 1602, // WebAssemblyInstrFormats.td:59
1618 RELAXED_DOT_BFLOAT_S = 1603, // WebAssemblyInstrFormats.td:61
1619 RELAXED_DOT_S = 1604, // WebAssemblyInstrFormats.td:61
1620 RELAXED_Q15MULR_S_I16x8 = 1605, // WebAssemblyInstrFormats.td:59
1621 RELAXED_Q15MULR_S_I16x8_S = 1606, // WebAssemblyInstrFormats.td:61
1622 RELAXED_SWIZZLE = 1607, // WebAssemblyInstrFormats.td:59
1623 RELAXED_SWIZZLE_S = 1608, // WebAssemblyInstrFormats.td:61
1624 REM_S_I32 = 1609, // WebAssemblyInstrFormats.td:59
1625 REM_S_I32_S = 1610, // WebAssemblyInstrFormats.td:61
1626 REM_S_I64 = 1611, // WebAssemblyInstrFormats.td:59
1627 REM_S_I64_S = 1612, // WebAssemblyInstrFormats.td:61
1628 REM_U_I32 = 1613, // WebAssemblyInstrFormats.td:59
1629 REM_U_I32_S = 1614, // WebAssemblyInstrFormats.td:61
1630 REM_U_I64 = 1615, // WebAssemblyInstrFormats.td:59
1631 REM_U_I64_S = 1616, // WebAssemblyInstrFormats.td:61
1632 REPLACE_LANE_F16x8 = 1617, // WebAssemblyInstrFormats.td:59
1633 REPLACE_LANE_F16x8_S = 1618, // WebAssemblyInstrFormats.td:61
1634 REPLACE_LANE_F32x4 = 1619, // WebAssemblyInstrFormats.td:59
1635 REPLACE_LANE_F32x4_S = 1620, // WebAssemblyInstrFormats.td:61
1636 REPLACE_LANE_F64x2 = 1621, // WebAssemblyInstrFormats.td:59
1637 REPLACE_LANE_F64x2_S = 1622, // WebAssemblyInstrFormats.td:61
1638 REPLACE_LANE_I16x8 = 1623, // WebAssemblyInstrFormats.td:59
1639 REPLACE_LANE_I16x8_S = 1624, // WebAssemblyInstrFormats.td:61
1640 REPLACE_LANE_I32x4 = 1625, // WebAssemblyInstrFormats.td:59
1641 REPLACE_LANE_I32x4_S = 1626, // WebAssemblyInstrFormats.td:61
1642 REPLACE_LANE_I64x2 = 1627, // WebAssemblyInstrFormats.td:59
1643 REPLACE_LANE_I64x2_S = 1628, // WebAssemblyInstrFormats.td:61
1644 REPLACE_LANE_I8x16 = 1629, // WebAssemblyInstrFormats.td:59
1645 REPLACE_LANE_I8x16_S = 1630, // WebAssemblyInstrFormats.td:61
1646 RETHROW = 1631, // WebAssemblyInstrFormats.td:59
1647 RETHROW_S = 1632, // WebAssemblyInstrFormats.td:61
1648 RETURN = 1633, // WebAssemblyInstrFormats.td:59
1649 RETURN_S = 1634, // WebAssemblyInstrFormats.td:61
1650 RET_CALL = 1635, // WebAssemblyInstrFormats.td:59
1651 RET_CALL_INDIRECT = 1636, // WebAssemblyInstrFormats.td:59
1652 RET_CALL_INDIRECT_S = 1637, // WebAssemblyInstrFormats.td:61
1653 RET_CALL_REF = 1638, // WebAssemblyInstrFormats.td:59
1654 RET_CALL_REF_S = 1639, // WebAssemblyInstrFormats.td:61
1655 RET_CALL_S = 1640, // WebAssemblyInstrFormats.td:61
1656 ROTL_I32 = 1641, // WebAssemblyInstrFormats.td:59
1657 ROTL_I32_S = 1642, // WebAssemblyInstrFormats.td:61
1658 ROTL_I64 = 1643, // WebAssemblyInstrFormats.td:59
1659 ROTL_I64_S = 1644, // WebAssemblyInstrFormats.td:61
1660 ROTR_I32 = 1645, // WebAssemblyInstrFormats.td:59
1661 ROTR_I32_S = 1646, // WebAssemblyInstrFormats.td:61
1662 ROTR_I64 = 1647, // WebAssemblyInstrFormats.td:59
1663 ROTR_I64_S = 1648, // WebAssemblyInstrFormats.td:61
1664 SELECT_EXNREF = 1649, // WebAssemblyInstrFormats.td:59
1665 SELECT_EXNREF_S = 1650, // WebAssemblyInstrFormats.td:61
1666 SELECT_EXTERNREF = 1651, // WebAssemblyInstrFormats.td:59
1667 SELECT_EXTERNREF_S = 1652, // WebAssemblyInstrFormats.td:61
1668 SELECT_F32 = 1653, // WebAssemblyInstrFormats.td:59
1669 SELECT_F32_S = 1654, // WebAssemblyInstrFormats.td:61
1670 SELECT_F64 = 1655, // WebAssemblyInstrFormats.td:59
1671 SELECT_F64_S = 1656, // WebAssemblyInstrFormats.td:61
1672 SELECT_FUNCREF = 1657, // WebAssemblyInstrFormats.td:59
1673 SELECT_FUNCREF_S = 1658, // WebAssemblyInstrFormats.td:61
1674 SELECT_I32 = 1659, // WebAssemblyInstrFormats.td:59
1675 SELECT_I32_S = 1660, // WebAssemblyInstrFormats.td:61
1676 SELECT_I64 = 1661, // WebAssemblyInstrFormats.td:59
1677 SELECT_I64_S = 1662, // WebAssemblyInstrFormats.td:61
1678 SELECT_T = 1663, // WebAssemblyInstrFormats.td:59
1679 SELECT_T_S = 1664, // WebAssemblyInstrFormats.td:61
1680 SELECT_V128 = 1665, // WebAssemblyInstrFormats.td:59
1681 SELECT_V128_S = 1666, // WebAssemblyInstrFormats.td:61
1682 SHL_I16x8 = 1667, // WebAssemblyInstrFormats.td:59
1683 SHL_I16x8_S = 1668, // WebAssemblyInstrFormats.td:61
1684 SHL_I32 = 1669, // WebAssemblyInstrFormats.td:59
1685 SHL_I32_S = 1670, // WebAssemblyInstrFormats.td:61
1686 SHL_I32x4 = 1671, // WebAssemblyInstrFormats.td:59
1687 SHL_I32x4_S = 1672, // WebAssemblyInstrFormats.td:61
1688 SHL_I64 = 1673, // WebAssemblyInstrFormats.td:59
1689 SHL_I64_S = 1674, // WebAssemblyInstrFormats.td:61
1690 SHL_I64x2 = 1675, // WebAssemblyInstrFormats.td:59
1691 SHL_I64x2_S = 1676, // WebAssemblyInstrFormats.td:61
1692 SHL_I8x16 = 1677, // WebAssemblyInstrFormats.td:59
1693 SHL_I8x16_S = 1678, // WebAssemblyInstrFormats.td:61
1694 SHR_S_I16x8 = 1679, // WebAssemblyInstrFormats.td:59
1695 SHR_S_I16x8_S = 1680, // WebAssemblyInstrFormats.td:61
1696 SHR_S_I32 = 1681, // WebAssemblyInstrFormats.td:59
1697 SHR_S_I32_S = 1682, // WebAssemblyInstrFormats.td:61
1698 SHR_S_I32x4 = 1683, // WebAssemblyInstrFormats.td:59
1699 SHR_S_I32x4_S = 1684, // WebAssemblyInstrFormats.td:61
1700 SHR_S_I64 = 1685, // WebAssemblyInstrFormats.td:59
1701 SHR_S_I64_S = 1686, // WebAssemblyInstrFormats.td:61
1702 SHR_S_I64x2 = 1687, // WebAssemblyInstrFormats.td:59
1703 SHR_S_I64x2_S = 1688, // WebAssemblyInstrFormats.td:61
1704 SHR_S_I8x16 = 1689, // WebAssemblyInstrFormats.td:59
1705 SHR_S_I8x16_S = 1690, // WebAssemblyInstrFormats.td:61
1706 SHR_U_I16x8 = 1691, // WebAssemblyInstrFormats.td:59
1707 SHR_U_I16x8_S = 1692, // WebAssemblyInstrFormats.td:61
1708 SHR_U_I32 = 1693, // WebAssemblyInstrFormats.td:59
1709 SHR_U_I32_S = 1694, // WebAssemblyInstrFormats.td:61
1710 SHR_U_I32x4 = 1695, // WebAssemblyInstrFormats.td:59
1711 SHR_U_I32x4_S = 1696, // WebAssemblyInstrFormats.td:61
1712 SHR_U_I64 = 1697, // WebAssemblyInstrFormats.td:59
1713 SHR_U_I64_S = 1698, // WebAssemblyInstrFormats.td:61
1714 SHR_U_I64x2 = 1699, // WebAssemblyInstrFormats.td:59
1715 SHR_U_I64x2_S = 1700, // WebAssemblyInstrFormats.td:61
1716 SHR_U_I8x16 = 1701, // WebAssemblyInstrFormats.td:59
1717 SHR_U_I8x16_S = 1702, // WebAssemblyInstrFormats.td:61
1718 SHUFFLE = 1703, // WebAssemblyInstrFormats.td:59
1719 SHUFFLE_S = 1704, // WebAssemblyInstrFormats.td:61
1720 SIMD_RELAXED_FMAX_F32x4 = 1705, // WebAssemblyInstrFormats.td:59
1721 SIMD_RELAXED_FMAX_F32x4_S = 1706, // WebAssemblyInstrFormats.td:61
1722 SIMD_RELAXED_FMAX_F64x2 = 1707, // WebAssemblyInstrFormats.td:59
1723 SIMD_RELAXED_FMAX_F64x2_S = 1708, // WebAssemblyInstrFormats.td:61
1724 SIMD_RELAXED_FMIN_F32x4 = 1709, // WebAssemblyInstrFormats.td:59
1725 SIMD_RELAXED_FMIN_F32x4_S = 1710, // WebAssemblyInstrFormats.td:61
1726 SIMD_RELAXED_FMIN_F64x2 = 1711, // WebAssemblyInstrFormats.td:59
1727 SIMD_RELAXED_FMIN_F64x2_S = 1712, // WebAssemblyInstrFormats.td:61
1728 SPLAT_F16x8 = 1713, // WebAssemblyInstrFormats.td:59
1729 SPLAT_F16x8_S = 1714, // WebAssemblyInstrFormats.td:61
1730 SPLAT_F32x4 = 1715, // WebAssemblyInstrFormats.td:59
1731 SPLAT_F32x4_S = 1716, // WebAssemblyInstrFormats.td:61
1732 SPLAT_F64x2 = 1717, // WebAssemblyInstrFormats.td:59
1733 SPLAT_F64x2_S = 1718, // WebAssemblyInstrFormats.td:61
1734 SPLAT_I16x8 = 1719, // WebAssemblyInstrFormats.td:59
1735 SPLAT_I16x8_S = 1720, // WebAssemblyInstrFormats.td:61
1736 SPLAT_I32x4 = 1721, // WebAssemblyInstrFormats.td:59
1737 SPLAT_I32x4_S = 1722, // WebAssemblyInstrFormats.td:61
1738 SPLAT_I64x2 = 1723, // WebAssemblyInstrFormats.td:59
1739 SPLAT_I64x2_S = 1724, // WebAssemblyInstrFormats.td:61
1740 SPLAT_I8x16 = 1725, // WebAssemblyInstrFormats.td:59
1741 SPLAT_I8x16_S = 1726, // WebAssemblyInstrFormats.td:61
1742 SQRT_F16x8 = 1727, // WebAssemblyInstrFormats.td:59
1743 SQRT_F16x8_S = 1728, // WebAssemblyInstrFormats.td:61
1744 SQRT_F32 = 1729, // WebAssemblyInstrFormats.td:59
1745 SQRT_F32_S = 1730, // WebAssemblyInstrFormats.td:61
1746 SQRT_F32x4 = 1731, // WebAssemblyInstrFormats.td:59
1747 SQRT_F32x4_S = 1732, // WebAssemblyInstrFormats.td:61
1748 SQRT_F64 = 1733, // WebAssemblyInstrFormats.td:59
1749 SQRT_F64_S = 1734, // WebAssemblyInstrFormats.td:61
1750 SQRT_F64x2 = 1735, // WebAssemblyInstrFormats.td:59
1751 SQRT_F64x2_S = 1736, // WebAssemblyInstrFormats.td:61
1752 STORE16_I32_A32 = 1737, // WebAssemblyInstrFormats.td:59
1753 STORE16_I32_A32_S = 1738, // WebAssemblyInstrFormats.td:61
1754 STORE16_I32_A64 = 1739, // WebAssemblyInstrFormats.td:59
1755 STORE16_I32_A64_S = 1740, // WebAssemblyInstrFormats.td:61
1756 STORE16_I64_A32 = 1741, // WebAssemblyInstrFormats.td:59
1757 STORE16_I64_A32_S = 1742, // WebAssemblyInstrFormats.td:61
1758 STORE16_I64_A64 = 1743, // WebAssemblyInstrFormats.td:59
1759 STORE16_I64_A64_S = 1744, // WebAssemblyInstrFormats.td:61
1760 STORE32_I64_A32 = 1745, // WebAssemblyInstrFormats.td:59
1761 STORE32_I64_A32_S = 1746, // WebAssemblyInstrFormats.td:61
1762 STORE32_I64_A64 = 1747, // WebAssemblyInstrFormats.td:59
1763 STORE32_I64_A64_S = 1748, // WebAssemblyInstrFormats.td:61
1764 STORE8_I32_A32 = 1749, // WebAssemblyInstrFormats.td:59
1765 STORE8_I32_A32_S = 1750, // WebAssemblyInstrFormats.td:61
1766 STORE8_I32_A64 = 1751, // WebAssemblyInstrFormats.td:59
1767 STORE8_I32_A64_S = 1752, // WebAssemblyInstrFormats.td:61
1768 STORE8_I64_A32 = 1753, // WebAssemblyInstrFormats.td:59
1769 STORE8_I64_A32_S = 1754, // WebAssemblyInstrFormats.td:61
1770 STORE8_I64_A64 = 1755, // WebAssemblyInstrFormats.td:59
1771 STORE8_I64_A64_S = 1756, // WebAssemblyInstrFormats.td:61
1772 STORE_F16_F32_A32 = 1757, // WebAssemblyInstrFormats.td:59
1773 STORE_F16_F32_A32_S = 1758, // WebAssemblyInstrFormats.td:61
1774 STORE_F16_F32_A64 = 1759, // WebAssemblyInstrFormats.td:59
1775 STORE_F16_F32_A64_S = 1760, // WebAssemblyInstrFormats.td:61
1776 STORE_F32_A32 = 1761, // WebAssemblyInstrFormats.td:59
1777 STORE_F32_A32_S = 1762, // WebAssemblyInstrFormats.td:61
1778 STORE_F32_A64 = 1763, // WebAssemblyInstrFormats.td:59
1779 STORE_F32_A64_S = 1764, // WebAssemblyInstrFormats.td:61
1780 STORE_F64_A32 = 1765, // WebAssemblyInstrFormats.td:59
1781 STORE_F64_A32_S = 1766, // WebAssemblyInstrFormats.td:61
1782 STORE_F64_A64 = 1767, // WebAssemblyInstrFormats.td:59
1783 STORE_F64_A64_S = 1768, // WebAssemblyInstrFormats.td:61
1784 STORE_I32_A32 = 1769, // WebAssemblyInstrFormats.td:59
1785 STORE_I32_A32_S = 1770, // WebAssemblyInstrFormats.td:61
1786 STORE_I32_A64 = 1771, // WebAssemblyInstrFormats.td:59
1787 STORE_I32_A64_S = 1772, // WebAssemblyInstrFormats.td:61
1788 STORE_I64_A32 = 1773, // WebAssemblyInstrFormats.td:59
1789 STORE_I64_A32_S = 1774, // WebAssemblyInstrFormats.td:61
1790 STORE_I64_A64 = 1775, // WebAssemblyInstrFormats.td:59
1791 STORE_I64_A64_S = 1776, // WebAssemblyInstrFormats.td:61
1792 STORE_LANE_I16x8_A32 = 1777, // WebAssemblyInstrFormats.td:59
1793 STORE_LANE_I16x8_A32_S = 1778, // WebAssemblyInstrFormats.td:61
1794 STORE_LANE_I16x8_A64 = 1779, // WebAssemblyInstrFormats.td:59
1795 STORE_LANE_I16x8_A64_S = 1780, // WebAssemblyInstrFormats.td:61
1796 STORE_LANE_I32x4_A32 = 1781, // WebAssemblyInstrFormats.td:59
1797 STORE_LANE_I32x4_A32_S = 1782, // WebAssemblyInstrFormats.td:61
1798 STORE_LANE_I32x4_A64 = 1783, // WebAssemblyInstrFormats.td:59
1799 STORE_LANE_I32x4_A64_S = 1784, // WebAssemblyInstrFormats.td:61
1800 STORE_LANE_I64x2_A32 = 1785, // WebAssemblyInstrFormats.td:59
1801 STORE_LANE_I64x2_A32_S = 1786, // WebAssemblyInstrFormats.td:61
1802 STORE_LANE_I64x2_A64 = 1787, // WebAssemblyInstrFormats.td:59
1803 STORE_LANE_I64x2_A64_S = 1788, // WebAssemblyInstrFormats.td:61
1804 STORE_LANE_I8x16_A32 = 1789, // WebAssemblyInstrFormats.td:59
1805 STORE_LANE_I8x16_A32_S = 1790, // WebAssemblyInstrFormats.td:61
1806 STORE_LANE_I8x16_A64 = 1791, // WebAssemblyInstrFormats.td:59
1807 STORE_LANE_I8x16_A64_S = 1792, // WebAssemblyInstrFormats.td:61
1808 STORE_V128_A32 = 1793, // WebAssemblyInstrFormats.td:59
1809 STORE_V128_A32_S = 1794, // WebAssemblyInstrFormats.td:61
1810 STORE_V128_A64 = 1795, // WebAssemblyInstrFormats.td:59
1811 STORE_V128_A64_S = 1796, // WebAssemblyInstrFormats.td:61
1812 SUB_F16x8 = 1797, // WebAssemblyInstrFormats.td:59
1813 SUB_F16x8_S = 1798, // WebAssemblyInstrFormats.td:61
1814 SUB_F32 = 1799, // WebAssemblyInstrFormats.td:59
1815 SUB_F32_S = 1800, // WebAssemblyInstrFormats.td:61
1816 SUB_F32x4 = 1801, // WebAssemblyInstrFormats.td:59
1817 SUB_F32x4_S = 1802, // WebAssemblyInstrFormats.td:61
1818 SUB_F64 = 1803, // WebAssemblyInstrFormats.td:59
1819 SUB_F64_S = 1804, // WebAssemblyInstrFormats.td:61
1820 SUB_F64x2 = 1805, // WebAssemblyInstrFormats.td:59
1821 SUB_F64x2_S = 1806, // WebAssemblyInstrFormats.td:61
1822 SUB_I16x8 = 1807, // WebAssemblyInstrFormats.td:59
1823 SUB_I16x8_S = 1808, // WebAssemblyInstrFormats.td:61
1824 SUB_I32 = 1809, // WebAssemblyInstrFormats.td:59
1825 SUB_I32_S = 1810, // WebAssemblyInstrFormats.td:61
1826 SUB_I32x4 = 1811, // WebAssemblyInstrFormats.td:59
1827 SUB_I32x4_S = 1812, // WebAssemblyInstrFormats.td:61
1828 SUB_I64 = 1813, // WebAssemblyInstrFormats.td:59
1829 SUB_I64_S = 1814, // WebAssemblyInstrFormats.td:61
1830 SUB_I64x2 = 1815, // WebAssemblyInstrFormats.td:59
1831 SUB_I64x2_S = 1816, // WebAssemblyInstrFormats.td:61
1832 SUB_I8x16 = 1817, // WebAssemblyInstrFormats.td:59
1833 SUB_I8x16_S = 1818, // WebAssemblyInstrFormats.td:61
1834 SUB_SAT_S_I16x8 = 1819, // WebAssemblyInstrFormats.td:59
1835 SUB_SAT_S_I16x8_S = 1820, // WebAssemblyInstrFormats.td:61
1836 SUB_SAT_S_I8x16 = 1821, // WebAssemblyInstrFormats.td:59
1837 SUB_SAT_S_I8x16_S = 1822, // WebAssemblyInstrFormats.td:61
1838 SUB_SAT_U_I16x8 = 1823, // WebAssemblyInstrFormats.td:59
1839 SUB_SAT_U_I16x8_S = 1824, // WebAssemblyInstrFormats.td:61
1840 SUB_SAT_U_I8x16 = 1825, // WebAssemblyInstrFormats.td:59
1841 SUB_SAT_U_I8x16_S = 1826, // WebAssemblyInstrFormats.td:61
1842 SWIZZLE = 1827, // WebAssemblyInstrFormats.td:59
1843 SWIZZLE_S = 1828, // WebAssemblyInstrFormats.td:61
1844 TABLE_COPY = 1829, // WebAssemblyInstrFormats.td:59
1845 TABLE_COPY_S = 1830, // WebAssemblyInstrFormats.td:61
1846 TABLE_FILL_EXNREF = 1831, // WebAssemblyInstrFormats.td:59
1847 TABLE_FILL_EXNREF_S = 1832, // WebAssemblyInstrFormats.td:61
1848 TABLE_FILL_EXTERNREF = 1833, // WebAssemblyInstrFormats.td:59
1849 TABLE_FILL_EXTERNREF_S = 1834, // WebAssemblyInstrFormats.td:61
1850 TABLE_FILL_FUNCREF = 1835, // WebAssemblyInstrFormats.td:59
1851 TABLE_FILL_FUNCREF_S = 1836, // WebAssemblyInstrFormats.td:61
1852 TABLE_GET_EXNREF = 1837, // WebAssemblyInstrFormats.td:59
1853 TABLE_GET_EXNREF_S = 1838, // WebAssemblyInstrFormats.td:61
1854 TABLE_GET_EXTERNREF = 1839, // WebAssemblyInstrFormats.td:59
1855 TABLE_GET_EXTERNREF_S = 1840, // WebAssemblyInstrFormats.td:61
1856 TABLE_GET_FUNCREF = 1841, // WebAssemblyInstrFormats.td:59
1857 TABLE_GET_FUNCREF_S = 1842, // WebAssemblyInstrFormats.td:61
1858 TABLE_GROW_EXNREF = 1843, // WebAssemblyInstrFormats.td:59
1859 TABLE_GROW_EXNREF_S = 1844, // WebAssemblyInstrFormats.td:61
1860 TABLE_GROW_EXTERNREF = 1845, // WebAssemblyInstrFormats.td:59
1861 TABLE_GROW_EXTERNREF_S = 1846, // WebAssemblyInstrFormats.td:61
1862 TABLE_GROW_FUNCREF = 1847, // WebAssemblyInstrFormats.td:59
1863 TABLE_GROW_FUNCREF_S = 1848, // WebAssemblyInstrFormats.td:61
1864 TABLE_SET_EXNREF = 1849, // WebAssemblyInstrFormats.td:59
1865 TABLE_SET_EXNREF_S = 1850, // WebAssemblyInstrFormats.td:61
1866 TABLE_SET_EXTERNREF = 1851, // WebAssemblyInstrFormats.td:59
1867 TABLE_SET_EXTERNREF_S = 1852, // WebAssemblyInstrFormats.td:61
1868 TABLE_SET_FUNCREF = 1853, // WebAssemblyInstrFormats.td:59
1869 TABLE_SET_FUNCREF_S = 1854, // WebAssemblyInstrFormats.td:61
1870 TABLE_SIZE = 1855, // WebAssemblyInstrFormats.td:59
1871 TABLE_SIZE_S = 1856, // WebAssemblyInstrFormats.td:61
1872 TEE_EXNREF = 1857, // WebAssemblyInstrFormats.td:59
1873 TEE_EXNREF_S = 1858, // WebAssemblyInstrFormats.td:61
1874 TEE_EXTERNREF = 1859, // WebAssemblyInstrFormats.td:59
1875 TEE_EXTERNREF_S = 1860, // WebAssemblyInstrFormats.td:61
1876 TEE_F32 = 1861, // WebAssemblyInstrFormats.td:59
1877 TEE_F32_S = 1862, // WebAssemblyInstrFormats.td:61
1878 TEE_F64 = 1863, // WebAssemblyInstrFormats.td:59
1879 TEE_F64_S = 1864, // WebAssemblyInstrFormats.td:61
1880 TEE_FUNCREF = 1865, // WebAssemblyInstrFormats.td:59
1881 TEE_FUNCREF_S = 1866, // WebAssemblyInstrFormats.td:61
1882 TEE_I32 = 1867, // WebAssemblyInstrFormats.td:59
1883 TEE_I32_S = 1868, // WebAssemblyInstrFormats.td:61
1884 TEE_I64 = 1869, // WebAssemblyInstrFormats.td:59
1885 TEE_I64_S = 1870, // WebAssemblyInstrFormats.td:61
1886 TEE_V128 = 1871, // WebAssemblyInstrFormats.td:59
1887 TEE_V128_S = 1872, // WebAssemblyInstrFormats.td:61
1888 THROW = 1873, // WebAssemblyInstrFormats.td:59
1889 THROW_REF = 1874, // WebAssemblyInstrFormats.td:59
1890 THROW_REF_S = 1875, // WebAssemblyInstrFormats.td:61
1891 THROW_S = 1876, // WebAssemblyInstrFormats.td:61
1892 TRUNC_F16x8 = 1877, // WebAssemblyInstrFormats.td:59
1893 TRUNC_F16x8_S = 1878, // WebAssemblyInstrFormats.td:61
1894 TRUNC_F32 = 1879, // WebAssemblyInstrFormats.td:59
1895 TRUNC_F32_S = 1880, // WebAssemblyInstrFormats.td:61
1896 TRUNC_F32x4 = 1881, // WebAssemblyInstrFormats.td:59
1897 TRUNC_F32x4_S = 1882, // WebAssemblyInstrFormats.td:61
1898 TRUNC_F64 = 1883, // WebAssemblyInstrFormats.td:59
1899 TRUNC_F64_S = 1884, // WebAssemblyInstrFormats.td:61
1900 TRUNC_F64x2 = 1885, // WebAssemblyInstrFormats.td:59
1901 TRUNC_F64x2_S = 1886, // WebAssemblyInstrFormats.td:61
1902 TRY = 1887, // WebAssemblyInstrFormats.td:59
1903 TRY_S = 1888, // WebAssemblyInstrFormats.td:61
1904 TRY_TABLE = 1889, // WebAssemblyInstrFormats.td:59
1905 TRY_TABLE_S = 1890, // WebAssemblyInstrFormats.td:61
1906 UNREACHABLE = 1891, // WebAssemblyInstrFormats.td:59
1907 UNREACHABLE_S = 1892, // WebAssemblyInstrFormats.td:61
1908 XOR = 1893, // WebAssemblyInstrFormats.td:59
1909 XOR_I32 = 1894, // WebAssemblyInstrFormats.td:59
1910 XOR_I32_S = 1895, // WebAssemblyInstrFormats.td:61
1911 XOR_I64 = 1896, // WebAssemblyInstrFormats.td:59
1912 XOR_I64_S = 1897, // WebAssemblyInstrFormats.td:61
1913 XOR_S = 1898, // WebAssemblyInstrFormats.td:61
1914 anonymous_14422MEMORY_GROW_A32 = 1899, // WebAssemblyInstrFormats.td:59
1915 anonymous_14422MEMORY_GROW_A32_S = 1900, // WebAssemblyInstrFormats.td:61
1916 anonymous_14422MEMORY_SIZE_A32 = 1901, // WebAssemblyInstrFormats.td:59
1917 anonymous_14422MEMORY_SIZE_A32_S = 1902, // WebAssemblyInstrFormats.td:61
1918 anonymous_14423MEMORY_GROW_A64 = 1903, // WebAssemblyInstrFormats.td:59
1919 anonymous_14423MEMORY_GROW_A64_S = 1904, // WebAssemblyInstrFormats.td:61
1920 anonymous_14423MEMORY_SIZE_A64 = 1905, // WebAssemblyInstrFormats.td:59
1921 anonymous_14423MEMORY_SIZE_A64_S = 1906, // WebAssemblyInstrFormats.td:61
1922 convert_low_s_F64x2 = 1907, // WebAssemblyInstrFormats.td:59
1923 convert_low_s_F64x2_S = 1908, // WebAssemblyInstrFormats.td:61
1924 convert_low_u_F64x2 = 1909, // WebAssemblyInstrFormats.td:59
1925 convert_low_u_F64x2_S = 1910, // WebAssemblyInstrFormats.td:61
1926 demote_zero_F16x8 = 1911, // WebAssemblyInstrFormats.td:59
1927 demote_zero_F16x8_S = 1912, // WebAssemblyInstrFormats.td:61
1928 demote_zero_F32x4 = 1913, // WebAssemblyInstrFormats.td:59
1929 demote_zero_F32x4_S = 1914, // WebAssemblyInstrFormats.td:61
1930 extadd_pairwise_s_I16x8 = 1915, // WebAssemblyInstrFormats.td:59
1931 extadd_pairwise_s_I16x8_S = 1916, // WebAssemblyInstrFormats.td:61
1932 extadd_pairwise_s_I32x4 = 1917, // WebAssemblyInstrFormats.td:59
1933 extadd_pairwise_s_I32x4_S = 1918, // WebAssemblyInstrFormats.td:61
1934 extadd_pairwise_u_I16x8 = 1919, // WebAssemblyInstrFormats.td:59
1935 extadd_pairwise_u_I16x8_S = 1920, // WebAssemblyInstrFormats.td:61
1936 extadd_pairwise_u_I32x4 = 1921, // WebAssemblyInstrFormats.td:59
1937 extadd_pairwise_u_I32x4_S = 1922, // WebAssemblyInstrFormats.td:61
1938 extend_high_s_I16x8 = 1923, // WebAssemblyInstrFormats.td:59
1939 extend_high_s_I16x8_S = 1924, // WebAssemblyInstrFormats.td:61
1940 extend_high_s_I32x4 = 1925, // WebAssemblyInstrFormats.td:59
1941 extend_high_s_I32x4_S = 1926, // WebAssemblyInstrFormats.td:61
1942 extend_high_s_I64x2 = 1927, // WebAssemblyInstrFormats.td:59
1943 extend_high_s_I64x2_S = 1928, // WebAssemblyInstrFormats.td:61
1944 extend_high_u_I16x8 = 1929, // WebAssemblyInstrFormats.td:59
1945 extend_high_u_I16x8_S = 1930, // WebAssemblyInstrFormats.td:61
1946 extend_high_u_I32x4 = 1931, // WebAssemblyInstrFormats.td:59
1947 extend_high_u_I32x4_S = 1932, // WebAssemblyInstrFormats.td:61
1948 extend_high_u_I64x2 = 1933, // WebAssemblyInstrFormats.td:59
1949 extend_high_u_I64x2_S = 1934, // WebAssemblyInstrFormats.td:61
1950 extend_low_s_I16x8 = 1935, // WebAssemblyInstrFormats.td:59
1951 extend_low_s_I16x8_S = 1936, // WebAssemblyInstrFormats.td:61
1952 extend_low_s_I32x4 = 1937, // WebAssemblyInstrFormats.td:59
1953 extend_low_s_I32x4_S = 1938, // WebAssemblyInstrFormats.td:61
1954 extend_low_s_I64x2 = 1939, // WebAssemblyInstrFormats.td:59
1955 extend_low_s_I64x2_S = 1940, // WebAssemblyInstrFormats.td:61
1956 extend_low_u_I16x8 = 1941, // WebAssemblyInstrFormats.td:59
1957 extend_low_u_I16x8_S = 1942, // WebAssemblyInstrFormats.td:61
1958 extend_low_u_I32x4 = 1943, // WebAssemblyInstrFormats.td:59
1959 extend_low_u_I32x4_S = 1944, // WebAssemblyInstrFormats.td:61
1960 extend_low_u_I64x2 = 1945, // WebAssemblyInstrFormats.td:59
1961 extend_low_u_I64x2_S = 1946, // WebAssemblyInstrFormats.td:61
1962 fp_to_sint_I16x8 = 1947, // WebAssemblyInstrFormats.td:59
1963 fp_to_sint_I16x8_S = 1948, // WebAssemblyInstrFormats.td:61
1964 fp_to_sint_I32x4 = 1949, // WebAssemblyInstrFormats.td:59
1965 fp_to_sint_I32x4_S = 1950, // WebAssemblyInstrFormats.td:61
1966 fp_to_uint_I16x8 = 1951, // WebAssemblyInstrFormats.td:59
1967 fp_to_uint_I16x8_S = 1952, // WebAssemblyInstrFormats.td:61
1968 fp_to_uint_I32x4 = 1953, // WebAssemblyInstrFormats.td:59
1969 fp_to_uint_I32x4_S = 1954, // WebAssemblyInstrFormats.td:61
1970 int_wasm_relaxed_trunc_signed_I32x4 = 1955, // WebAssemblyInstrFormats.td:59
1971 int_wasm_relaxed_trunc_signed_I32x4_S = 1956, // WebAssemblyInstrFormats.td:61
1972 int_wasm_relaxed_trunc_signed_zero_I32x4 = 1957, // WebAssemblyInstrFormats.td:59
1973 int_wasm_relaxed_trunc_signed_zero_I32x4_S = 1958, // WebAssemblyInstrFormats.td:61
1974 int_wasm_relaxed_trunc_unsigned_I32x4 = 1959, // WebAssemblyInstrFormats.td:59
1975 int_wasm_relaxed_trunc_unsigned_I32x4_S = 1960, // WebAssemblyInstrFormats.td:61
1976 int_wasm_relaxed_trunc_unsigned_zero_I32x4 = 1961, // WebAssemblyInstrFormats.td:59
1977 int_wasm_relaxed_trunc_unsigned_zero_I32x4_S = 1962, // WebAssemblyInstrFormats.td:61
1978 promote_low_F32x4 = 1963, // WebAssemblyInstrFormats.td:59
1979 promote_low_F32x4_S = 1964, // WebAssemblyInstrFormats.td:61
1980 promote_low_F64x2 = 1965, // WebAssemblyInstrFormats.td:59
1981 promote_low_F64x2_S = 1966, // WebAssemblyInstrFormats.td:61
1982 sint_to_fp_F16x8 = 1967, // WebAssemblyInstrFormats.td:59
1983 sint_to_fp_F16x8_S = 1968, // WebAssemblyInstrFormats.td:61
1984 sint_to_fp_F32x4 = 1969, // WebAssemblyInstrFormats.td:59
1985 sint_to_fp_F32x4_S = 1970, // WebAssemblyInstrFormats.td:61
1986 trunc_sat_zero_s_I32x4 = 1971, // WebAssemblyInstrFormats.td:59
1987 trunc_sat_zero_s_I32x4_S = 1972, // WebAssemblyInstrFormats.td:61
1988 trunc_sat_zero_u_I32x4 = 1973, // WebAssemblyInstrFormats.td:59
1989 trunc_sat_zero_u_I32x4_S = 1974, // WebAssemblyInstrFormats.td:61
1990 uint_to_fp_F16x8 = 1975, // WebAssemblyInstrFormats.td:59
1991 uint_to_fp_F16x8_S = 1976, // WebAssemblyInstrFormats.td:61
1992 uint_to_fp_F32x4 = 1977, // WebAssemblyInstrFormats.td:59
1993 uint_to_fp_F32x4_S = 1978, // WebAssemblyInstrFormats.td:61
1994 INSTRUCTION_LIST_END = 1979
1995 };
1996 enum RegClassByHwModeUses : uint16_t {
1997 wasm_ptr_rc,
1998 };
1999
2000} // namespace llvm::WebAssembly
2001
2002#endif // GET_INSTRINFO_ENUM
2003
2004#ifdef GET_INSTRINFO_SCHED_ENUM
2005#undef GET_INSTRINFO_SCHED_ENUM
2006
2007namespace llvm::WebAssembly::Sched {
2008
2009 enum {
2010 NoInstrModel = 0,
2011 SCHED_LIST_END = 1
2012 };
2013
2014} // namespace llvm::WebAssembly::Sched
2015
2016#endif // GET_INSTRINFO_SCHED_ENUM
2017
2018#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
2019
2020namespace llvm {
2021
2022struct WebAssemblyInstrTable {
2023 MCInstrDesc Insts[1979];
2024 static_assert(alignof(MCInstrDesc) >= alignof(MCPhysReg), "Unwanted padding between Insts and ImplicitOps");
2025 MCPhysReg ImplicitOps[10];
2026 char Padding[sizeof(MCOperandInfo) - sizeof ImplicitOps % sizeof(MCOperandInfo)];
2027 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
2028 MCOperandInfo OperandInfo[890];
2029};
2030} // namespace llvm
2031
2032#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
2033
2034#ifdef GET_INSTRINFO_MC_DESC
2035#undef GET_INSTRINFO_MC_DESC
2036
2037namespace llvm {
2038
2039static_assert((sizeof WebAssemblyInstrTable::ImplicitOps + sizeof WebAssemblyInstrTable::Padding) % sizeof(MCOperandInfo) == 0);
2040static constexpr unsigned WebAssemblyOpInfoBase = (sizeof WebAssemblyInstrTable::ImplicitOps + sizeof WebAssemblyInstrTable::Padding) / sizeof(MCOperandInfo);
2041
2042extern const WebAssemblyInstrTable WebAssemblyDescs = {
2043 {
2044 { 1978, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // uint_to_fp_F32x4_S
2045 { 1977, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // uint_to_fp_F32x4
2046 { 1976, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // uint_to_fp_F16x8_S
2047 { 1975, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // uint_to_fp_F16x8
2048 { 1974, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // trunc_sat_zero_u_I32x4_S
2049 { 1973, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // trunc_sat_zero_u_I32x4
2050 { 1972, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // trunc_sat_zero_s_I32x4_S
2051 { 1971, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // trunc_sat_zero_s_I32x4
2052 { 1970, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // sint_to_fp_F32x4_S
2053 { 1969, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // sint_to_fp_F32x4
2054 { 1968, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // sint_to_fp_F16x8_S
2055 { 1967, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // sint_to_fp_F16x8
2056 { 1966, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // promote_low_F64x2_S
2057 { 1965, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // promote_low_F64x2
2058 { 1964, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // promote_low_F32x4_S
2059 { 1963, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // promote_low_F32x4
2060 { 1962, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // int_wasm_relaxed_trunc_unsigned_zero_I32x4_S
2061 { 1961, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // int_wasm_relaxed_trunc_unsigned_zero_I32x4
2062 { 1960, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // int_wasm_relaxed_trunc_unsigned_I32x4_S
2063 { 1959, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // int_wasm_relaxed_trunc_unsigned_I32x4
2064 { 1958, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // int_wasm_relaxed_trunc_signed_zero_I32x4_S
2065 { 1957, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // int_wasm_relaxed_trunc_signed_zero_I32x4
2066 { 1956, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // int_wasm_relaxed_trunc_signed_I32x4_S
2067 { 1955, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // int_wasm_relaxed_trunc_signed_I32x4
2068 { 1954, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // fp_to_uint_I32x4_S
2069 { 1953, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // fp_to_uint_I32x4
2070 { 1952, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // fp_to_uint_I16x8_S
2071 { 1951, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // fp_to_uint_I16x8
2072 { 1950, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // fp_to_sint_I32x4_S
2073 { 1949, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // fp_to_sint_I32x4
2074 { 1948, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // fp_to_sint_I16x8_S
2075 { 1947, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // fp_to_sint_I16x8
2076 { 1946, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_low_u_I64x2_S
2077 { 1945, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_low_u_I64x2
2078 { 1944, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_low_u_I32x4_S
2079 { 1943, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_low_u_I32x4
2080 { 1942, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_low_u_I16x8_S
2081 { 1941, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_low_u_I16x8
2082 { 1940, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_low_s_I64x2_S
2083 { 1939, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_low_s_I64x2
2084 { 1938, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_low_s_I32x4_S
2085 { 1937, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_low_s_I32x4
2086 { 1936, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_low_s_I16x8_S
2087 { 1935, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_low_s_I16x8
2088 { 1934, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_high_u_I64x2_S
2089 { 1933, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_high_u_I64x2
2090 { 1932, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_high_u_I32x4_S
2091 { 1931, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_high_u_I32x4
2092 { 1930, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_high_u_I16x8_S
2093 { 1929, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_high_u_I16x8
2094 { 1928, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_high_s_I64x2_S
2095 { 1927, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_high_s_I64x2
2096 { 1926, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_high_s_I32x4_S
2097 { 1925, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_high_s_I32x4
2098 { 1924, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_high_s_I16x8_S
2099 { 1923, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_high_s_I16x8
2100 { 1922, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extadd_pairwise_u_I32x4_S
2101 { 1921, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extadd_pairwise_u_I32x4
2102 { 1920, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extadd_pairwise_u_I16x8_S
2103 { 1919, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extadd_pairwise_u_I16x8
2104 { 1918, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extadd_pairwise_s_I32x4_S
2105 { 1917, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extadd_pairwise_s_I32x4
2106 { 1916, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extadd_pairwise_s_I16x8_S
2107 { 1915, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extadd_pairwise_s_I16x8
2108 { 1914, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // demote_zero_F32x4_S
2109 { 1913, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // demote_zero_F32x4
2110 { 1912, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // demote_zero_F16x8_S
2111 { 1911, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // demote_zero_F16x8
2112 { 1910, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // convert_low_u_F64x2_S
2113 { 1909, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // convert_low_u_F64x2
2114 { 1908, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // convert_low_s_F64x2_S
2115 { 1907, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // convert_low_s_F64x2
2116 { 1906, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14423MEMORY_SIZE_A64_S
2117 { 1905, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 190, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14423MEMORY_SIZE_A64
2118 { 1904, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14423MEMORY_GROW_A64_S
2119 { 1903, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 887, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14423MEMORY_GROW_A64
2120 { 1902, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14422MEMORY_SIZE_A32_S
2121 { 1901, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 188, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14422MEMORY_SIZE_A32
2122 { 1900, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14422MEMORY_GROW_A32_S
2123 { 1899, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 884, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14422MEMORY_GROW_A32
2124 { 1898, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_S
2125 { 1897, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_I64_S
2126 { 1896, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_I64
2127 { 1895, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_I32_S
2128 { 1894, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_I32
2129 { 1893, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR
2130 { 1892, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Trap)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // UNREACHABLE_S
2131 { 1891, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Trap)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // UNREACHABLE
2132 { 1890, 2, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 882, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRY_TABLE_S
2133 { 1889, 1, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 297, 8, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRY_TABLE
2134 { 1888, 1, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 297, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRY_S
2135 { 1887, 1, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 297, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRY
2136 { 1886, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRUNC_F64x2_S
2137 { 1885, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRUNC_F64x2
2138 { 1884, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRUNC_F64_S
2139 { 1883, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRUNC_F64
2140 { 1882, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRUNC_F32x4_S
2141 { 1881, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRUNC_F32x4
2142 { 1880, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRUNC_F32_S
2143 { 1879, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 157, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRUNC_F32
2144 { 1878, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRUNC_F16x8_S
2145 { 1877, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRUNC_F16x8
2146 { 1876, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 308, 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // THROW_S
2147 { 1875, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // THROW_REF_S
2148 { 1874, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 309, 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // THROW_REF
2149 { 1873, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 308, 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // THROW
2150 { 1872, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_V128_S
2151 { 1871, 3, 2, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_V128
2152 { 1870, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_I64_S
2153 { 1869, 3, 2, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_I64
2154 { 1868, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_I32_S
2155 { 1867, 3, 2, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_I32
2156 { 1866, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_FUNCREF_S
2157 { 1865, 3, 2, 0, 0, 0, 1, WebAssemblyOpInfoBase + 879, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_FUNCREF
2158 { 1864, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_F64_S
2159 { 1863, 3, 2, 0, 0, 0, 1, WebAssemblyOpInfoBase + 167, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_F64
2160 { 1862, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_F32_S
2161 { 1861, 3, 2, 0, 0, 0, 1, WebAssemblyOpInfoBase + 164, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_F32
2162 { 1860, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_EXTERNREF_S
2163 { 1859, 3, 2, 0, 0, 0, 1, WebAssemblyOpInfoBase + 876, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_EXTERNREF
2164 { 1858, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_EXNREF_S
2165 { 1857, 3, 2, 0, 0, 0, 1, WebAssemblyOpInfoBase + 873, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_EXNREF
2166 { 1856, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 832, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_SIZE_S
2167 { 1855, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 871, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_SIZE
2168 { 1854, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 832, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_SET_FUNCREF_S
2169 { 1853, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 868, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_SET_FUNCREF
2170 { 1852, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 832, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_SET_EXTERNREF_S
2171 { 1851, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 865, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_SET_EXTERNREF
2172 { 1850, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 832, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_SET_EXNREF_S
2173 { 1849, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 862, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_SET_EXNREF
2174 { 1848, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 832, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_GROW_FUNCREF_S
2175 { 1847, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 858, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_GROW_FUNCREF
2176 { 1846, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 832, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_GROW_EXTERNREF_S
2177 { 1845, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 854, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_GROW_EXTERNREF
2178 { 1844, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 832, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_GROW_EXNREF_S
2179 { 1843, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 850, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_GROW_EXNREF
2180 { 1842, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 832, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_GET_FUNCREF_S
2181 { 1841, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 847, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_GET_FUNCREF
2182 { 1840, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 832, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_GET_EXTERNREF_S
2183 { 1839, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 844, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_GET_EXTERNREF
2184 { 1838, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 832, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_GET_EXNREF_S
2185 { 1837, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 841, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_GET_EXNREF
2186 { 1836, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 832, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_FILL_FUNCREF_S
2187 { 1835, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 837, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_FILL_FUNCREF
2188 { 1834, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 832, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_FILL_EXTERNREF_S
2189 { 1833, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 833, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_FILL_EXTERNREF
2190 { 1832, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 832, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_FILL_EXNREF_S
2191 { 1831, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 828, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_FILL_EXNREF
2192 { 1830, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 826, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_COPY_S
2193 { 1829, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 821, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_COPY
2194 { 1828, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SWIZZLE_S
2195 { 1827, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SWIZZLE
2196 { 1826, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_SAT_U_I8x16_S
2197 { 1825, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_SAT_U_I8x16
2198 { 1824, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_SAT_U_I16x8_S
2199 { 1823, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_SAT_U_I16x8
2200 { 1822, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_SAT_S_I8x16_S
2201 { 1821, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_SAT_S_I8x16
2202 { 1820, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_SAT_S_I16x8_S
2203 { 1819, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_SAT_S_I16x8
2204 { 1818, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I8x16_S
2205 { 1817, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I8x16
2206 { 1816, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I64x2_S
2207 { 1815, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I64x2
2208 { 1814, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I64_S
2209 { 1813, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I64
2210 { 1812, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I32x4_S
2211 { 1811, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I32x4
2212 { 1810, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I32_S
2213 { 1809, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I32
2214 { 1808, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I16x8_S
2215 { 1807, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I16x8
2216 { 1806, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F64x2_S
2217 { 1805, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F64x2
2218 { 1804, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F64_S
2219 { 1803, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 167, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F64
2220 { 1802, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F32x4_S
2221 { 1801, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F32x4
2222 { 1800, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F32_S
2223 { 1799, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 164, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F32
2224 { 1798, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F16x8_S
2225 { 1797, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F16x8
2226 { 1796, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_V128_A64_S
2227 { 1795, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 817, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_V128_A64
2228 { 1794, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_V128_A32_S
2229 { 1793, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 813, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_V128_A32
2230 { 1792, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 565, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I8x16_A64_S
2231 { 1791, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 808, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I8x16_A64
2232 { 1790, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 556, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I8x16_A32_S
2233 { 1789, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 803, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I8x16_A32
2234 { 1788, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 565, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I64x2_A64_S
2235 { 1787, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 808, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I64x2_A64
2236 { 1786, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 556, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I64x2_A32_S
2237 { 1785, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 803, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I64x2_A32
2238 { 1784, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 565, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I32x4_A64_S
2239 { 1783, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 808, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I32x4_A64
2240 { 1782, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 556, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I32x4_A32_S
2241 { 1781, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 803, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I32x4_A32
2242 { 1780, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 565, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I16x8_A64_S
2243 { 1779, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 808, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I16x8_A64
2244 { 1778, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 556, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I16x8_A32_S
2245 { 1777, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 803, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I16x8_A32
2246 { 1776, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_I64_A64_S
2247 { 1775, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 783, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_I64_A64
2248 { 1774, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_I64_A32_S
2249 { 1773, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 779, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_I64_A32
2250 { 1772, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_I32_A64_S
2251 { 1771, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 775, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_I32_A64
2252 { 1770, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_I32_A32_S
2253 { 1769, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 771, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_I32_A32
2254 { 1768, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_F64_A64_S
2255 { 1767, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 799, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_F64_A64
2256 { 1766, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_F64_A32_S
2257 { 1765, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 795, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_F64_A32
2258 { 1764, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_F32_A64_S
2259 { 1763, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 791, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_F32_A64
2260 { 1762, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_F32_A32_S
2261 { 1761, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 787, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_F32_A32
2262 { 1760, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_F16_F32_A64_S
2263 { 1759, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 791, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_F16_F32_A64
2264 { 1758, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_F16_F32_A32_S
2265 { 1757, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 787, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_F16_F32_A32
2266 { 1756, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE8_I64_A64_S
2267 { 1755, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 783, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE8_I64_A64
2268 { 1754, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE8_I64_A32_S
2269 { 1753, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 779, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE8_I64_A32
2270 { 1752, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE8_I32_A64_S
2271 { 1751, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 775, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE8_I32_A64
2272 { 1750, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE8_I32_A32_S
2273 { 1749, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 771, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE8_I32_A32
2274 { 1748, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE32_I64_A64_S
2275 { 1747, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 783, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE32_I64_A64
2276 { 1746, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE32_I64_A32_S
2277 { 1745, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 779, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE32_I64_A32
2278 { 1744, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE16_I64_A64_S
2279 { 1743, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 783, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE16_I64_A64
2280 { 1742, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE16_I64_A32_S
2281 { 1741, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 779, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE16_I64_A32
2282 { 1740, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE16_I32_A64_S
2283 { 1739, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 775, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE16_I32_A64
2284 { 1738, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE16_I32_A32_S
2285 { 1737, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 771, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE16_I32_A32
2286 { 1736, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SQRT_F64x2_S
2287 { 1735, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SQRT_F64x2
2288 { 1734, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SQRT_F64_S
2289 { 1733, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SQRT_F64
2290 { 1732, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SQRT_F32x4_S
2291 { 1731, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SQRT_F32x4
2292 { 1730, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SQRT_F32_S
2293 { 1729, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 157, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SQRT_F32
2294 { 1728, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SQRT_F16x8_S
2295 { 1727, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SQRT_F16x8
2296 { 1726, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_I8x16_S
2297 { 1725, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 767, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_I8x16
2298 { 1724, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_I64x2_S
2299 { 1723, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 769, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_I64x2
2300 { 1722, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_I32x4_S
2301 { 1721, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 767, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_I32x4
2302 { 1720, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_I16x8_S
2303 { 1719, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 767, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_I16x8
2304 { 1718, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_F64x2_S
2305 { 1717, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 765, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_F64x2
2306 { 1716, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_F32x4_S
2307 { 1715, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 763, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_F32x4
2308 { 1714, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_F16x8_S
2309 { 1713, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 763, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_F16x8
2310 { 1712, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SIMD_RELAXED_FMIN_F64x2_S
2311 { 1711, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SIMD_RELAXED_FMIN_F64x2
2312 { 1710, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SIMD_RELAXED_FMIN_F32x4_S
2313 { 1709, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SIMD_RELAXED_FMIN_F32x4
2314 { 1708, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SIMD_RELAXED_FMAX_F64x2_S
2315 { 1707, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SIMD_RELAXED_FMAX_F64x2
2316 { 1706, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SIMD_RELAXED_FMAX_F32x4_S
2317 { 1705, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SIMD_RELAXED_FMAX_F32x4
2318 { 1704, 16, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 388, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHUFFLE_S
2319 { 1703, 19, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 744, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHUFFLE
2320 { 1702, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_U_I8x16_S
2321 { 1701, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 741, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_U_I8x16
2322 { 1700, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_U_I64x2_S
2323 { 1699, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 741, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_U_I64x2
2324 { 1698, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_U_I64_S
2325 { 1697, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_U_I64
2326 { 1696, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_U_I32x4_S
2327 { 1695, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 741, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_U_I32x4
2328 { 1694, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_U_I32_S
2329 { 1693, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_U_I32
2330 { 1692, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_U_I16x8_S
2331 { 1691, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 741, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_U_I16x8
2332 { 1690, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_S_I8x16_S
2333 { 1689, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 741, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_S_I8x16
2334 { 1688, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_S_I64x2_S
2335 { 1687, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 741, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_S_I64x2
2336 { 1686, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_S_I64_S
2337 { 1685, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_S_I64
2338 { 1684, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_S_I32x4_S
2339 { 1683, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 741, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_S_I32x4
2340 { 1682, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_S_I32_S
2341 { 1681, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_S_I32
2342 { 1680, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_S_I16x8_S
2343 { 1679, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 741, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_S_I16x8
2344 { 1678, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_I8x16_S
2345 { 1677, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 741, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_I8x16
2346 { 1676, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_I64x2_S
2347 { 1675, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 741, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_I64x2
2348 { 1674, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_I64_S
2349 { 1673, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_I64
2350 { 1672, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_I32x4_S
2351 { 1671, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 741, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_I32x4
2352 { 1670, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_I32_S
2353 { 1669, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_I32
2354 { 1668, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_I16x8_S
2355 { 1667, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 741, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_I16x8
2356 { 1666, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_V128_S
2357 { 1665, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 737, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_V128
2358 { 1664, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 736, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_T_S
2359 { 1663, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 736, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_T
2360 { 1662, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_I64_S
2361 { 1661, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 732, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_I64
2362 { 1660, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_I32_S
2363 { 1659, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 728, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_I32
2364 { 1658, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_FUNCREF_S
2365 { 1657, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 724, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_FUNCREF
2366 { 1656, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_F64_S
2367 { 1655, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 720, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_F64
2368 { 1654, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_F32_S
2369 { 1653, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 716, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_F32
2370 { 1652, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_EXTERNREF_S
2371 { 1651, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 712, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_EXTERNREF
2372 { 1650, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_EXNREF_S
2373 { 1649, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 708, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_EXNREF
2374 { 1648, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ROTR_I64_S
2375 { 1647, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ROTR_I64
2376 { 1646, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ROTR_I32_S
2377 { 1645, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ROTR_I32
2378 { 1644, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ROTL_I64_S
2379 { 1643, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ROTL_I64
2380 { 1642, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ROTL_I32_S
2381 { 1641, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ROTL_I32
2382 { 1640, 1, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 151, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RET_CALL_S
2383 { 1639, 1, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 307, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RET_CALL_REF_S
2384 { 1638, 2, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 305, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RET_CALL_REF
2385 { 1637, 2, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 303, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RET_CALL_INDIRECT_S
2386 { 1636, 2, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 303, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RET_CALL_INDIRECT
2387 { 1635, 1, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 151, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RET_CALL
2388 { 1634, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RETURN_S
2389 { 1633, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RETURN
2390 { 1632, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 154, 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RETHROW_S
2391 { 1631, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 154, 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RETHROW
2392 { 1630, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 429, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_I8x16_S
2393 { 1629, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 700, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_I8x16
2394 { 1628, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 429, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_I64x2_S
2395 { 1627, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 704, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_I64x2
2396 { 1626, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 429, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_I32x4_S
2397 { 1625, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 700, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_I32x4
2398 { 1624, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 429, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_I16x8_S
2399 { 1623, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 700, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_I16x8
2400 { 1622, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 429, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_F64x2_S
2401 { 1621, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 696, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_F64x2
2402 { 1620, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 429, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_F32x4_S
2403 { 1619, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 692, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_F32x4
2404 { 1618, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 429, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_F16x8_S
2405 { 1617, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 692, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_F16x8
2406 { 1616, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REM_U_I64_S
2407 { 1615, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REM_U_I64
2408 { 1614, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REM_U_I32_S
2409 { 1613, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REM_U_I32
2410 { 1612, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REM_S_I64_S
2411 { 1611, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REM_S_I64
2412 { 1610, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REM_S_I32_S
2413 { 1609, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REM_S_I32
2414 { 1608, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELAXED_SWIZZLE_S
2415 { 1607, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELAXED_SWIZZLE
2416 { 1606, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELAXED_Q15MULR_S_I16x8_S
2417 { 1605, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELAXED_Q15MULR_S_I16x8
2418 { 1604, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELAXED_DOT_S
2419 { 1603, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELAXED_DOT_BFLOAT_S
2420 { 1602, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 293, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELAXED_DOT_BFLOAT
2421 { 1601, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELAXED_DOT_ADD_S
2422 { 1600, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 293, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELAXED_DOT_ADD
2423 { 1599, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELAXED_DOT
2424 { 1598, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 307, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_TEST_FUNCREF_S
2425 { 1597, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 689, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_TEST_FUNCREF
2426 { 1596, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_NULL_FUNCREF_S
2427 { 1595, 1, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 413, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_NULL_FUNCREF
2428 { 1594, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_NULL_EXTERNREF_S
2429 { 1593, 1, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 410, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_NULL_EXTERNREF
2430 { 1592, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_NULL_EXNREF_S
2431 { 1591, 1, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 309, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_NULL_EXNREF
2432 { 1590, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_IS_NULL_FUNCREF_S
2433 { 1589, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 687, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_IS_NULL_FUNCREF
2434 { 1588, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_IS_NULL_EXTERNREF_S
2435 { 1587, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 685, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_IS_NULL_EXTERNREF
2436 { 1586, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_IS_NULL_EXNREF_S
2437 { 1585, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 683, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_IS_NULL_EXNREF
2438 { 1584, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 151, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_FUNC_S
2439 { 1583, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 681, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_FUNC
2440 { 1582, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 307, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_CAST_FUNCREF_S
2441 { 1581, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 678, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_CAST_FUNCREF
2442 { 1580, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Q15MULR_SAT_S_I16x8_S
2443 { 1579, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Q15MULR_SAT_S_I16x8
2444 { 1578, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // POPCNT_I8x16_S
2445 { 1577, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // POPCNT_I8x16
2446 { 1576, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // POPCNT_I64_S
2447 { 1575, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 312, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // POPCNT_I64
2448 { 1574, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // POPCNT_I32_S
2449 { 1573, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 310, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // POPCNT_I32
2450 { 1572, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PMIN_F64x2_S
2451 { 1571, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PMIN_F64x2
2452 { 1570, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PMIN_F32x4_S
2453 { 1569, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PMIN_F32x4
2454 { 1568, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PMIN_F16x8_S
2455 { 1567, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PMIN_F16x8
2456 { 1566, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PMAX_F64x2_S
2457 { 1565, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PMAX_F64x2
2458 { 1564, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PMAX_F32x4_S
2459 { 1563, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PMAX_F32x4
2460 { 1562, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PMAX_F16x8_S
2461 { 1561, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PMAX_F16x8
2462 { 1560, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_S
2463 { 1559, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_I64_S
2464 { 1558, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_I64
2465 { 1557, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_I32_S
2466 { 1556, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_I32
2467 { 1555, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR
2468 { 1554, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NOT_S
2469 { 1553, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NOT
2470 { 1552, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NOP_S
2471 { 1551, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NOP
2472 { 1550, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NMADD_F64x2_S
2473 { 1549, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 293, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NMADD_F64x2
2474 { 1548, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NMADD_F32x4_S
2475 { 1547, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 293, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NMADD_F32x4
2476 { 1546, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NMADD_F16x8_S
2477 { 1545, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 293, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NMADD_F16x8
2478 { 1544, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_I8x16_S
2479 { 1543, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_I8x16
2480 { 1542, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_I64x2_S
2481 { 1541, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_I64x2
2482 { 1540, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_I64_S
2483 { 1539, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 423, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_I64
2484 { 1538, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_I32x4_S
2485 { 1537, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_I32x4
2486 { 1536, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_I32_S
2487 { 1535, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_I32
2488 { 1534, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_I16x8_S
2489 { 1533, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_I16x8
2490 { 1532, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_F64x2_S
2491 { 1531, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_F64x2
2492 { 1530, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_F64_S
2493 { 1529, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 420, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_F64
2494 { 1528, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_F32x4_S
2495 { 1527, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_F32x4
2496 { 1526, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_F32_S
2497 { 1525, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 417, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_F32
2498 { 1524, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_F16x8_S
2499 { 1523, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_F16x8
2500 { 1522, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_I8x16_S
2501 { 1521, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_I8x16
2502 { 1520, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_I64x2_S
2503 { 1519, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_I64x2
2504 { 1518, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_I32x4_S
2505 { 1517, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_I32x4
2506 { 1516, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_I16x8_S
2507 { 1515, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_I16x8
2508 { 1514, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_F64x2_S
2509 { 1513, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_F64x2
2510 { 1512, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_F64_S
2511 { 1511, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_F64
2512 { 1510, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_F32x4_S
2513 { 1509, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_F32x4
2514 { 1508, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_F32_S
2515 { 1507, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 157, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_F32
2516 { 1506, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_F16x8_S
2517 { 1505, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_F16x8
2518 { 1504, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEAREST_F64x2_S
2519 { 1503, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEAREST_F64x2
2520 { 1502, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEAREST_F64_S
2521 { 1501, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEAREST_F64
2522 { 1500, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEAREST_F32x4_S
2523 { 1499, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEAREST_F32x4
2524 { 1498, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEAREST_F32_S
2525 { 1497, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 157, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEAREST_F32
2526 { 1496, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEAREST_F16x8_S
2527 { 1495, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEAREST_F16x8
2528 { 1494, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NARROW_U_I8x16_S
2529 { 1493, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NARROW_U_I8x16
2530 { 1492, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NARROW_U_I16x8_S
2531 { 1491, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NARROW_U_I16x8
2532 { 1490, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NARROW_S_I8x16_S
2533 { 1489, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NARROW_S_I8x16
2534 { 1488, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NARROW_S_I16x8_S
2535 { 1487, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NARROW_S_I16x8
2536 { 1486, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_I64x2_S
2537 { 1485, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_I64x2
2538 { 1484, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_I64_S
2539 { 1483, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_I64
2540 { 1482, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_I32x4_S
2541 { 1481, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_I32x4
2542 { 1480, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_I32_S
2543 { 1479, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_I32
2544 { 1478, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_I16x8_S
2545 { 1477, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_I16x8
2546 { 1476, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_F64x2_S
2547 { 1475, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_F64x2
2548 { 1474, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_F64_S
2549 { 1473, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 167, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_F64
2550 { 1472, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_F32x4_S
2551 { 1471, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_F32x4
2552 { 1470, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_F32_S
2553 { 1469, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 164, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_F32
2554 { 1468, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_F16x8_S
2555 { 1467, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_F16x8
2556 { 1466, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_U_I8x16_S
2557 { 1465, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_U_I8x16
2558 { 1464, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_U_I32x4_S
2559 { 1463, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_U_I32x4
2560 { 1462, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_U_I16x8_S
2561 { 1461, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_U_I16x8
2562 { 1460, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_S_I8x16_S
2563 { 1459, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_S_I8x16
2564 { 1458, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_S_I32x4_S
2565 { 1457, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_S_I32x4
2566 { 1456, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_S_I16x8_S
2567 { 1455, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_S_I16x8
2568 { 1454, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_F64x2_S
2569 { 1453, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_F64x2
2570 { 1452, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_F64_S
2571 { 1451, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 167, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_F64
2572 { 1450, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_F32x4_S
2573 { 1449, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_F32x4
2574 { 1448, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_F32_S
2575 { 1447, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 164, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_F32
2576 { 1446, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_F16x8_S
2577 { 1445, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_F16x8
2578 { 1444, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 322, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMSET_A64_S
2579 { 1443, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 669, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMSET_A64
2580 { 1442, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 322, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMSET_A32_S
2581 { 1441, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 665, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMSET_A32
2582 { 1440, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 630, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_INIT_A64_S
2583 { 1439, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 673, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_INIT_A64
2584 { 1438, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 630, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_INIT_A32_S
2585 { 1437, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 625, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_INIT_A32
2586 { 1436, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 322, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_FILL_A64_S
2587 { 1435, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 669, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_FILL_A64
2588 { 1434, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 322, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_FILL_A32_S
2589 { 1433, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 665, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_FILL_A32
2590 { 1432, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 630, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_COPY_A64_S
2591 { 1431, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 632, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_COPY_A64
2592 { 1430, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 630, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_COPY_A32_S
2593 { 1429, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 625, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_COPY_A32
2594 { 1428, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_ATOMIC_WAIT64_A64_S
2595 { 1427, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 658, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_ATOMIC_WAIT64_A64
2596 { 1426, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_ATOMIC_WAIT64_A32_S
2597 { 1425, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 651, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_ATOMIC_WAIT64_A32
2598 { 1424, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_ATOMIC_WAIT32_A64_S
2599 { 1423, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 644, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_ATOMIC_WAIT32_A64
2600 { 1422, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_ATOMIC_WAIT32_A32_S
2601 { 1421, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 637, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_ATOMIC_WAIT32_A32
2602 { 1420, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_ATOMIC_NOTIFY_A64_S
2603 { 1419, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_ATOMIC_NOTIFY_A64
2604 { 1418, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_ATOMIC_NOTIFY_A32_S
2605 { 1417, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_ATOMIC_NOTIFY_A32
2606 { 1416, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 630, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMCPY_A64_S
2607 { 1415, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 632, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMCPY_A64
2608 { 1414, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 630, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMCPY_A32_S
2609 { 1413, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 625, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMCPY_A32
2610 { 1412, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_U_I8x16_S
2611 { 1411, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_U_I8x16
2612 { 1410, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_U_I32x4_S
2613 { 1409, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_U_I32x4
2614 { 1408, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_U_I16x8_S
2615 { 1407, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_U_I16x8
2616 { 1406, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_S_I8x16_S
2617 { 1405, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_S_I8x16
2618 { 1404, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_S_I32x4_S
2619 { 1403, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_S_I32x4
2620 { 1402, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_S_I16x8_S
2621 { 1401, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_S_I16x8
2622 { 1400, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_F64x2_S
2623 { 1399, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_F64x2
2624 { 1398, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_F64_S
2625 { 1397, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 167, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_F64
2626 { 1396, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_F32x4_S
2627 { 1395, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_F32x4
2628 { 1394, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_F32_S
2629 { 1393, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 164, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_F32
2630 { 1392, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_F16x8_S
2631 { 1391, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_F16x8
2632 { 1390, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MADD_F64x2_S
2633 { 1389, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 293, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MADD_F64x2
2634 { 1388, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MADD_F32x4_S
2635 { 1387, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 293, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MADD_F32x4
2636 { 1386, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MADD_F16x8_S
2637 { 1385, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 293, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MADD_F16x8
2638 { 1384, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_U_I8x16_S
2639 { 1383, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_U_I8x16
2640 { 1382, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_U_I64_S
2641 { 1381, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 423, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_U_I64
2642 { 1380, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_U_I32x4_S
2643 { 1379, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_U_I32x4
2644 { 1378, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_U_I32_S
2645 { 1377, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_U_I32
2646 { 1376, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_U_I16x8_S
2647 { 1375, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_U_I16x8
2648 { 1374, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_S_I8x16_S
2649 { 1373, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_S_I8x16
2650 { 1372, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_S_I64x2_S
2651 { 1371, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_S_I64x2
2652 { 1370, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_S_I64_S
2653 { 1369, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 423, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_S_I64
2654 { 1368, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_S_I32x4_S
2655 { 1367, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_S_I32x4
2656 { 1366, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_S_I32_S
2657 { 1365, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_S_I32
2658 { 1364, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_S_I16x8_S
2659 { 1363, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_S_I16x8
2660 { 1362, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_F64x2_S
2661 { 1361, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_F64x2
2662 { 1360, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_F64_S
2663 { 1359, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 420, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_F64
2664 { 1358, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_F32x4_S
2665 { 1357, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_F32x4
2666 { 1356, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_F32_S
2667 { 1355, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 417, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_F32
2668 { 1354, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_F16x8_S
2669 { 1353, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_F16x8
2670 { 1352, 1, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 297, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOOP_S
2671 { 1351, 1, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 297, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOOP
2672 { 1350, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_V128_S
2673 { 1349, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 622, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_V128
2674 { 1348, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_I64_S
2675 { 1347, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 619, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_I64
2676 { 1346, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_I32_S
2677 { 1345, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 616, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_I32
2678 { 1344, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_FUNCREF_S
2679 { 1343, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 613, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_FUNCREF
2680 { 1342, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_F64_S
2681 { 1341, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 610, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_F64
2682 { 1340, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_F32_S
2683 { 1339, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 607, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_F32
2684 { 1338, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_EXTERNREF_S
2685 { 1337, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 604, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_EXTERNREF
2686 { 1336, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_EXNREF_S
2687 { 1335, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 601, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_EXNREF
2688 { 1334, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_V128_S
2689 { 1333, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 599, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_V128
2690 { 1332, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_I64_S
2691 { 1331, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 597, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_I64
2692 { 1330, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_I32_S
2693 { 1329, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 595, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_I32
2694 { 1328, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_FUNCREF_S
2695 { 1327, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 593, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_FUNCREF
2696 { 1326, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_F64_S
2697 { 1325, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 591, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_F64
2698 { 1324, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_F32_S
2699 { 1323, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 589, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_F32
2700 { 1322, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_EXTERNREF_S
2701 { 1321, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 587, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_EXTERNREF
2702 { 1320, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_EXNREF_S
2703 { 1319, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 585, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_EXNREF
2704 { 1318, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_V128_S
2705 { 1317, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 583, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_V128
2706 { 1316, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_I64_S
2707 { 1315, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 581, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_I64
2708 { 1314, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_I32_S
2709 { 1313, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 579, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_I32
2710 { 1312, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_FUNCREF_S
2711 { 1311, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 577, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_FUNCREF
2712 { 1310, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_F64_S
2713 { 1309, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 575, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_F64
2714 { 1308, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_F32_S
2715 { 1307, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 573, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_F32
2716 { 1306, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_EXTERNREF_S
2717 { 1305, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 571, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_EXTERNREF
2718 { 1304, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_EXNREF_S
2719 { 1303, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 568, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_EXNREF
2720 { 1302, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_ZERO_64_A64_S
2721 { 1301, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 512, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_ZERO_64_A64
2722 { 1300, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_ZERO_64_A32_S
2723 { 1299, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 506, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_ZERO_64_A32
2724 { 1298, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_ZERO_32_A64_S
2725 { 1297, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 512, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_ZERO_32_A64
2726 { 1296, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_ZERO_32_A32_S
2727 { 1295, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 506, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_ZERO_32_A32
2728 { 1294, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_V128_A64_S
2729 { 1293, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 512, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_V128_A64
2730 { 1292, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_V128_A32_S
2731 { 1291, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 506, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_V128_A32
2732 { 1290, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 565, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_8_A64_S
2733 { 1289, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 559, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_8_A64
2734 { 1288, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 556, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_8_A32_S
2735 { 1287, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 550, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_8_A32
2736 { 1286, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 565, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_64_A64_S
2737 { 1285, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 559, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_64_A64
2738 { 1284, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 556, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_64_A32_S
2739 { 1283, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 550, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_64_A32
2740 { 1282, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 565, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_32_A64_S
2741 { 1281, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 559, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_32_A64
2742 { 1280, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 556, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_32_A32_S
2743 { 1279, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 550, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_32_A32
2744 { 1278, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 565, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_16_A64_S
2745 { 1277, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 559, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_16_A64
2746 { 1276, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 556, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_16_A32_S
2747 { 1275, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 550, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_16_A32
2748 { 1274, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_I64_A64_S
2749 { 1273, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 530, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_I64_A64
2750 { 1272, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_I64_A32_S
2751 { 1271, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 526, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_I64_A32
2752 { 1270, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_I32_A64_S
2753 { 1269, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 522, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_I32_A64
2754 { 1268, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_I32_A32_S
2755 { 1267, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 518, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_I32_A32
2756 { 1266, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_F64_A64_S
2757 { 1265, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 546, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_F64_A64
2758 { 1264, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_F64_A32_S
2759 { 1263, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 542, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_F64_A32
2760 { 1262, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_F32_A64_S
2761 { 1261, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 538, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_F32_A64
2762 { 1260, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_F32_A32_S
2763 { 1259, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 534, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_F32_A32
2764 { 1258, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_F16_F32_A64_S
2765 { 1257, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 538, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_F16_F32_A64
2766 { 1256, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_F16_F32_A32_S
2767 { 1255, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 534, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_F16_F32_A32
2768 { 1254, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_U_I64x2_A64_S
2769 { 1253, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 512, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_U_I64x2_A64
2770 { 1252, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_U_I64x2_A32_S
2771 { 1251, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 506, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_U_I64x2_A32
2772 { 1250, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_U_I32x4_A64_S
2773 { 1249, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 512, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_U_I32x4_A64
2774 { 1248, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_U_I32x4_A32_S
2775 { 1247, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 506, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_U_I32x4_A32
2776 { 1246, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_U_I16x8_A64_S
2777 { 1245, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 512, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_U_I16x8_A64
2778 { 1244, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_U_I16x8_A32_S
2779 { 1243, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 506, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_U_I16x8_A32
2780 { 1242, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_S_I64x2_A64_S
2781 { 1241, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 512, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_S_I64x2_A64
2782 { 1240, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_S_I64x2_A32_S
2783 { 1239, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 506, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_S_I64x2_A32
2784 { 1238, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_S_I32x4_A64_S
2785 { 1237, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 512, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_S_I32x4_A64
2786 { 1236, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_S_I32x4_A32_S
2787 { 1235, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 506, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_S_I32x4_A32
2788 { 1234, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_S_I16x8_A64_S
2789 { 1233, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 512, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_S_I16x8_A64
2790 { 1232, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_S_I16x8_A32_S
2791 { 1231, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 506, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_S_I16x8_A32
2792 { 1230, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_U_I64_A64_S
2793 { 1229, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 530, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_U_I64_A64
2794 { 1228, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_U_I64_A32_S
2795 { 1227, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 526, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_U_I64_A32
2796 { 1226, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_U_I32_A64_S
2797 { 1225, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 522, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_U_I32_A64
2798 { 1224, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_U_I32_A32_S
2799 { 1223, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 518, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_U_I32_A32
2800 { 1222, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_S_I64_A64_S
2801 { 1221, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 530, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_S_I64_A64
2802 { 1220, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_S_I64_A32_S
2803 { 1219, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 526, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_S_I64_A32
2804 { 1218, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_S_I32_A64_S
2805 { 1217, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 522, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_S_I32_A64
2806 { 1216, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_S_I32_A32_S
2807 { 1215, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 518, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_S_I32_A32
2808 { 1214, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_SPLAT_A64_S
2809 { 1213, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 512, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_SPLAT_A64
2810 { 1212, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_SPLAT_A32_S
2811 { 1211, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 506, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_SPLAT_A32
2812 { 1210, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD64_SPLAT_A64_S
2813 { 1209, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 512, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD64_SPLAT_A64
2814 { 1208, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD64_SPLAT_A32_S
2815 { 1207, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 506, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD64_SPLAT_A32
2816 { 1206, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD32_U_I64_A64_S
2817 { 1205, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 530, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD32_U_I64_A64
2818 { 1204, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD32_U_I64_A32_S
2819 { 1203, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 526, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD32_U_I64_A32
2820 { 1202, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD32_S_I64_A64_S
2821 { 1201, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 530, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD32_S_I64_A64
2822 { 1200, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD32_S_I64_A32_S
2823 { 1199, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 526, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD32_S_I64_A32
2824 { 1198, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD32_SPLAT_A64_S
2825 { 1197, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 512, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD32_SPLAT_A64
2826 { 1196, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD32_SPLAT_A32_S
2827 { 1195, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 506, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD32_SPLAT_A32
2828 { 1194, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_U_I64_A64_S
2829 { 1193, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 530, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_U_I64_A64
2830 { 1192, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_U_I64_A32_S
2831 { 1191, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 526, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_U_I64_A32
2832 { 1190, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_U_I32_A64_S
2833 { 1189, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 522, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_U_I32_A64
2834 { 1188, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_U_I32_A32_S
2835 { 1187, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 518, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_U_I32_A32
2836 { 1186, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_S_I64_A64_S
2837 { 1185, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 530, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_S_I64_A64
2838 { 1184, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_S_I64_A32_S
2839 { 1183, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 526, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_S_I64_A32
2840 { 1182, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_S_I32_A64_S
2841 { 1181, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 522, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_S_I32_A64
2842 { 1180, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_S_I32_A32_S
2843 { 1179, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 518, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_S_I32_A32
2844 { 1178, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_SPLAT_A64_S
2845 { 1177, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 512, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_SPLAT_A64
2846 { 1176, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_SPLAT_A32_S
2847 { 1175, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 506, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_SPLAT_A32
2848 { 1174, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_U_I8x16_S
2849 { 1173, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_U_I8x16
2850 { 1172, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_U_I64_S
2851 { 1171, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 423, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_U_I64
2852 { 1170, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_U_I32x4_S
2853 { 1169, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_U_I32x4
2854 { 1168, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_U_I32_S
2855 { 1167, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_U_I32
2856 { 1166, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_U_I16x8_S
2857 { 1165, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_U_I16x8
2858 { 1164, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_S_I8x16_S
2859 { 1163, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_S_I8x16
2860 { 1162, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_S_I64x2_S
2861 { 1161, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_S_I64x2
2862 { 1160, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_S_I64_S
2863 { 1159, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 423, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_S_I64
2864 { 1158, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_S_I32x4_S
2865 { 1157, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_S_I32x4
2866 { 1156, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_S_I32_S
2867 { 1155, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_S_I32
2868 { 1154, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_S_I16x8_S
2869 { 1153, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_S_I16x8
2870 { 1152, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_F64x2_S
2871 { 1151, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_F64x2
2872 { 1150, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_F64_S
2873 { 1149, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 420, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_F64
2874 { 1148, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_F32x4_S
2875 { 1147, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_F32x4
2876 { 1146, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_F32_S
2877 { 1145, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 417, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_F32
2878 { 1144, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_F16x8_S
2879 { 1143, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_F16x8
2880 { 1142, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LANESELECT_I8x16_S
2881 { 1141, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 293, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LANESELECT_I8x16
2882 { 1140, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LANESELECT_I64x2_S
2883 { 1139, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 293, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LANESELECT_I64x2
2884 { 1138, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LANESELECT_I32x4_S
2885 { 1137, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 293, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LANESELECT_I32x4
2886 { 1136, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LANESELECT_I16x8_S
2887 { 1135, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 293, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LANESELECT_I16x8
2888 { 1134, 1, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 297, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // IF_S
2889 { 1133, 2, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 504, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // IF
2890 { 1132, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_U_SAT_F64_S
2891 { 1131, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 457, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_U_SAT_F64
2892 { 1130, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_U_SAT_F32_S
2893 { 1129, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 455, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_U_SAT_F32
2894 { 1128, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_U_F64_S
2895 { 1127, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 457, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_U_F64
2896 { 1126, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_U_F32_S
2897 { 1125, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 455, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_U_F32
2898 { 1124, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_S_SAT_F64_S
2899 { 1123, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 457, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_S_SAT_F64
2900 { 1122, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_S_SAT_F32_S
2901 { 1121, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 455, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_S_SAT_F32
2902 { 1120, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_S_F64_S
2903 { 1119, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 457, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_S_F64
2904 { 1118, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_S_F32_S
2905 { 1117, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 455, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_S_F32
2906 { 1116, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_SUB128_S
2907 { 1115, 6, 2, 0, 0, 0, 1, WebAssemblyOpInfoBase + 492, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_SUB128
2908 { 1114, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_REINTERPRET_F64_S
2909 { 1113, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 457, 3, 0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_REINTERPRET_F64
2910 { 1112, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_MUL_WIDE_U_S
2911 { 1111, 4, 2, 0, 0, 0, 1, WebAssemblyOpInfoBase + 500, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_MUL_WIDE_U
2912 { 1110, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_MUL_WIDE_S_S
2913 { 1109, 4, 2, 0, 0, 0, 1, WebAssemblyOpInfoBase + 500, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_MUL_WIDE_S
2914 { 1108, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_EXTEND_U_I32_S
2915 { 1107, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 498, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_EXTEND_U_I32
2916 { 1106, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_EXTEND_S_I32_S
2917 { 1105, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 498, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_EXTEND_S_I32
2918 { 1104, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_EXTEND8_S_I64_S
2919 { 1103, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 312, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_EXTEND8_S_I64
2920 { 1102, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_EXTEND32_S_I64_S
2921 { 1101, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 312, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_EXTEND32_S_I64
2922 { 1100, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_EXTEND16_S_I64_S
2923 { 1099, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 312, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_EXTEND16_S_I64
2924 { 1098, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_ADD128_S
2925 { 1097, 6, 2, 0, 0, 0, 1, WebAssemblyOpInfoBase + 492, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_ADD128
2926 { 1096, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_WRAP_I64_S
2927 { 1095, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 415, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_WRAP_I64
2928 { 1094, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_U_SAT_F64_S
2929 { 1093, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 453, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_U_SAT_F64
2930 { 1092, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_U_SAT_F32_S
2931 { 1091, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 451, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_U_SAT_F32
2932 { 1090, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_U_F64_S
2933 { 1089, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 453, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_U_F64
2934 { 1088, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_U_F32_S
2935 { 1087, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 451, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_U_F32
2936 { 1086, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_S_SAT_F64_S
2937 { 1085, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 453, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_S_SAT_F64
2938 { 1084, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_S_SAT_F32_S
2939 { 1083, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 451, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_S_SAT_F32
2940 { 1082, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_S_F64_S
2941 { 1081, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 453, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_S_F64
2942 { 1080, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_S_F32_S
2943 { 1079, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 451, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_S_F32
2944 { 1078, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_REINTERPRET_F32_S
2945 { 1077, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 451, 3, 0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_REINTERPRET_F32
2946 { 1076, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_EXTEND8_S_I32_S
2947 { 1075, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 310, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_EXTEND8_S_I32
2948 { 1074, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_EXTEND16_S_I32_S
2949 { 1073, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 310, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_EXTEND16_S_I32
2950 { 1072, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_U_I8x16_S
2951 { 1071, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_U_I8x16
2952 { 1070, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_U_I64_S
2953 { 1069, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 423, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_U_I64
2954 { 1068, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_U_I32x4_S
2955 { 1067, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_U_I32x4
2956 { 1066, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_U_I32_S
2957 { 1065, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_U_I32
2958 { 1064, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_U_I16x8_S
2959 { 1063, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_U_I16x8
2960 { 1062, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_S_I8x16_S
2961 { 1061, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_S_I8x16
2962 { 1060, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_S_I64x2_S
2963 { 1059, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_S_I64x2
2964 { 1058, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_S_I64_S
2965 { 1057, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 423, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_S_I64
2966 { 1056, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_S_I32x4_S
2967 { 1055, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_S_I32x4
2968 { 1054, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_S_I32_S
2969 { 1053, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_S_I32
2970 { 1052, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_S_I16x8_S
2971 { 1051, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_S_I16x8
2972 { 1050, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_F64x2_S
2973 { 1049, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_F64x2
2974 { 1048, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_F64_S
2975 { 1047, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 420, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_F64
2976 { 1046, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_F32x4_S
2977 { 1045, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_F32x4
2978 { 1044, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_F32_S
2979 { 1043, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 417, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_F32
2980 { 1042, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_F16x8_S
2981 { 1041, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_F16x8
2982 { 1040, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 461, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_V128_S
2983 { 1039, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 490, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_V128
2984 { 1038, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 461, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_I64_S
2985 { 1037, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 488, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_I64
2986 { 1036, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 461, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_I32_S
2987 { 1035, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 486, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_I32
2988 { 1034, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 461, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_FUNCREF_S
2989 { 1033, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 484, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_FUNCREF
2990 { 1032, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 461, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_F64_S
2991 { 1031, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 482, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_F64
2992 { 1030, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 461, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_F32_S
2993 { 1029, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 480, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_F32
2994 { 1028, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 461, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_EXTERNREF_S
2995 { 1027, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 478, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_EXTERNREF
2996 { 1026, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 461, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_EXNREF_S
2997 { 1025, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 476, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_EXNREF
2998 { 1024, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 461, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_V128_S
2999 { 1023, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 474, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_V128
3000 { 1022, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 461, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_I64_S
3001 { 1021, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 472, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_I64
3002 { 1020, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 461, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_I32_S
3003 { 1019, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 470, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_I32
3004 { 1018, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 461, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_FUNCREF_S
3005 { 1017, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 468, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_FUNCREF
3006 { 1016, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 461, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_F64_S
3007 { 1015, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 466, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_F64
3008 { 1014, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 461, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_F32_S
3009 { 1013, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 464, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_F32
3010 { 1012, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 461, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_EXTERNREF_S
3011 { 1011, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 462, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_EXTERNREF
3012 { 1010, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 461, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_EXNREF_S
3013 { 1009, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 459, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_EXNREF
3014 { 1008, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_U_I8x16_S
3015 { 1007, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_U_I8x16
3016 { 1006, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_U_I64_S
3017 { 1005, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 423, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_U_I64
3018 { 1004, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_U_I32x4_S
3019 { 1003, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_U_I32x4
3020 { 1002, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_U_I32_S
3021 { 1001, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_U_I32
3022 { 1000, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_U_I16x8_S
3023 { 999, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_U_I16x8
3024 { 998, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_S_I8x16_S
3025 { 997, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_S_I8x16
3026 { 996, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_S_I64x2_S
3027 { 995, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_S_I64x2
3028 { 994, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_S_I64_S
3029 { 993, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 423, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_S_I64
3030 { 992, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_S_I32x4_S
3031 { 991, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_S_I32x4
3032 { 990, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_S_I32_S
3033 { 989, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_S_I32
3034 { 988, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_S_I16x8_S
3035 { 987, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_S_I16x8
3036 { 986, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_F64x2_S
3037 { 985, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_F64x2
3038 { 984, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_F64_S
3039 { 983, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 420, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_F64
3040 { 982, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_F32x4_S
3041 { 981, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_F32x4
3042 { 980, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_F32_S
3043 { 979, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 417, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_F32
3044 { 978, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_F16x8_S
3045 { 977, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_F16x8
3046 { 976, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_UINT_I64_F64_S
3047 { 975, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 457, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_UINT_I64_F64
3048 { 974, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_UINT_I64_F32_S
3049 { 973, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 455, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_UINT_I64_F32
3050 { 972, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_UINT_I32_F64_S
3051 { 971, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 453, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_UINT_I32_F64
3052 { 970, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_UINT_I32_F32_S
3053 { 969, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 451, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_UINT_I32_F32
3054 { 968, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_SINT_I64_F64_S
3055 { 967, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 457, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_SINT_I64_F64
3056 { 966, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_SINT_I64_F32_S
3057 { 965, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 455, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_SINT_I64_F32
3058 { 964, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_SINT_I32_F64_S
3059 { 963, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 453, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_SINT_I32_F64
3060 { 962, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_SINT_I32_F32_S
3061 { 961, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 451, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_SINT_I32_F32
3062 { 960, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FLOOR_F64x2_S
3063 { 959, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FLOOR_F64x2
3064 { 958, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FLOOR_F64_S
3065 { 957, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FLOOR_F64
3066 { 956, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FLOOR_F32x4_S
3067 { 955, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FLOOR_F32x4
3068 { 954, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FLOOR_F32_S
3069 { 953, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 157, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FLOOR_F32
3070 { 952, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FLOOR_F16x8_S
3071 { 951, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FLOOR_F16x8
3072 { 950, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FALLTHROUGH_RETURN_S
3073 { 949, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FALLTHROUGH_RETURN
3074 { 948, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F64_REINTERPRET_I64_S
3075 { 947, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 447, 3, 0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F64_REINTERPRET_I64
3076 { 946, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F64_PROMOTE_F32_S
3077 { 945, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 449, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F64_PROMOTE_F32
3078 { 944, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F64_CONVERT_U_I64_S
3079 { 943, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 447, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F64_CONVERT_U_I64
3080 { 942, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F64_CONVERT_U_I32_S
3081 { 941, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 445, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F64_CONVERT_U_I32
3082 { 940, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F64_CONVERT_S_I64_S
3083 { 939, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 447, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F64_CONVERT_S_I64
3084 { 938, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F64_CONVERT_S_I32_S
3085 { 937, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 445, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F64_CONVERT_S_I32
3086 { 936, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F32_REINTERPRET_I32_S
3087 { 935, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 439, 3, 0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F32_REINTERPRET_I32
3088 { 934, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F32_DEMOTE_F64_S
3089 { 933, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 443, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F32_DEMOTE_F64
3090 { 932, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F32_CONVERT_U_I64_S
3091 { 931, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 441, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F32_CONVERT_U_I64
3092 { 930, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F32_CONVERT_U_I32_S
3093 { 929, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 439, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F32_CONVERT_U_I32
3094 { 928, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F32_CONVERT_S_I64_S
3095 { 927, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 441, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F32_CONVERT_S_I64
3096 { 926, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F32_CONVERT_S_I32_S
3097 { 925, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 439, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F32_CONVERT_S_I32
3098 { 924, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 429, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_I8x16_u_S
3099 { 923, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 433, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_I8x16_u
3100 { 922, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 429, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_I8x16_s_S
3101 { 921, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 433, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_I8x16_s
3102 { 920, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 429, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_I64x2_S
3103 { 919, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 436, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_I64x2
3104 { 918, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 429, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_I32x4_S
3105 { 917, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 433, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_I32x4
3106 { 916, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 429, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_I16x8_u_S
3107 { 915, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 433, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_I16x8_u
3108 { 914, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 429, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_I16x8_s_S
3109 { 913, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 433, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_I16x8_s
3110 { 912, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 429, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_F64x2_S
3111 { 911, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 430, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_F64x2
3112 { 910, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 429, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_F32x4_S
3113 { 909, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 426, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_F32x4
3114 { 908, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 429, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_F16x8_S
3115 { 907, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 426, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_F16x8
3116 { 906, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_LOW_U_I64x2_S
3117 { 905, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_LOW_U_I64x2
3118 { 904, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_LOW_U_I32x4_S
3119 { 903, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_LOW_U_I32x4
3120 { 902, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_LOW_U_I16x8_S
3121 { 901, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_LOW_U_I16x8
3122 { 900, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_LOW_S_I64x2_S
3123 { 899, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_LOW_S_I64x2
3124 { 898, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_LOW_S_I32x4_S
3125 { 897, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_LOW_S_I32x4
3126 { 896, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_LOW_S_I16x8_S
3127 { 895, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_LOW_S_I16x8
3128 { 894, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_HIGH_U_I64x2_S
3129 { 893, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_HIGH_U_I64x2
3130 { 892, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_HIGH_U_I32x4_S
3131 { 891, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_HIGH_U_I32x4
3132 { 890, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_HIGH_U_I16x8_S
3133 { 889, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_HIGH_U_I16x8
3134 { 888, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_HIGH_S_I64x2_S
3135 { 887, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_HIGH_S_I64x2
3136 { 886, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_HIGH_S_I32x4_S
3137 { 885, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_HIGH_S_I32x4
3138 { 884, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_HIGH_S_I16x8_S
3139 { 883, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_HIGH_S_I16x8
3140 { 882, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_I8x16_S
3141 { 881, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_I8x16
3142 { 880, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_I64x2_S
3143 { 879, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_I64x2
3144 { 878, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_I64_S
3145 { 877, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 423, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_I64
3146 { 876, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_I32x4_S
3147 { 875, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_I32x4
3148 { 874, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_I32_S
3149 { 873, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_I32
3150 { 872, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_I16x8_S
3151 { 871, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_I16x8
3152 { 870, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_F64x2_S
3153 { 869, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_F64x2
3154 { 868, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_F64_S
3155 { 867, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 420, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_F64
3156 { 866, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_F32x4_S
3157 { 865, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_F32x4
3158 { 864, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_F32_S
3159 { 863, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 417, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_F32
3160 { 862, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_F16x8_S
3161 { 861, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_F16x8
3162 { 860, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQZ_I64_S
3163 { 859, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 415, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQZ_I64
3164 { 858, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQZ_I32_S
3165 { 857, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 310, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQZ_I32
3166 { 856, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_TRY_TABLE_S
3167 { 855, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_TRY_TABLE
3168 { 854, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_TRY_S
3169 { 853, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_TRY
3170 { 852, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_S
3171 { 851, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_LOOP_S
3172 { 850, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_LOOP
3173 { 849, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_IF_S
3174 { 848, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_IF
3175 { 847, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_FUNCTION_S
3176 { 846, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_FUNCTION
3177 { 845, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_BLOCK_S
3178 { 844, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_BLOCK
3179 { 843, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END
3180 { 842, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ELSE_S
3181 { 841, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ELSE
3182 { 840, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_V128_S
3183 { 839, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 414, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_V128
3184 { 838, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_I64_S
3185 { 837, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 302, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_I64
3186 { 836, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_I32_S
3187 { 835, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 300, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_I32
3188 { 834, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_FUNCREF_S
3189 { 833, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 413, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_FUNCREF
3190 { 832, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_F64_S
3191 { 831, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 412, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_F64
3192 { 830, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_F32_S
3193 { 829, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 411, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_F32
3194 { 828, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_EXTERNREF_S
3195 { 827, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 410, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_EXTERNREF
3196 { 826, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_EXNREF_S
3197 { 825, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 309, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_EXNREF
3198 { 824, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DOT_S
3199 { 823, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DOT
3200 { 822, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_U_I64_S
3201 { 821, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_U_I64
3202 { 820, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_U_I32_S
3203 { 819, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_U_I32
3204 { 818, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_S_I64_S
3205 { 817, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_S_I64
3206 { 816, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_S_I32_S
3207 { 815, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_S_I32
3208 { 814, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_F64x2_S
3209 { 813, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_F64x2
3210 { 812, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_F64_S
3211 { 811, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 167, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_F64
3212 { 810, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_F32x4_S
3213 { 809, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_F32x4
3214 { 808, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_F32_S
3215 { 807, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 164, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_F32
3216 { 806, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_F16x8_S
3217 { 805, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_F16x8
3218 { 804, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 154, 3, 0|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DELEGATE_S
3219 { 803, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 154, 3, 0|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DELEGATE
3220 { 802, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Trap)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DEBUG_UNREACHABLE_S
3221 { 801, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Trap)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DEBUG_UNREACHABLE
3222 { 800, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 322, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DATA_DROP_S
3223 { 799, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 322, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DATA_DROP
3224 { 798, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CTZ_I64_S
3225 { 797, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 312, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CTZ_I64
3226 { 796, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CTZ_I32_S
3227 { 795, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 310, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CTZ_I32
3228 { 794, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_V128_S
3229 { 793, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_V128
3230 { 792, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_I64_S
3231 { 791, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 312, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_I64
3232 { 790, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_I32_S
3233 { 789, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 310, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_I32
3234 { 788, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_FUNCREF_S
3235 { 787, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 408, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_FUNCREF
3236 { 786, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_F64_S
3237 { 785, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_F64
3238 { 784, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_F32_S
3239 { 783, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 157, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_F32
3240 { 782, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_EXTERNREF_S
3241 { 781, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 406, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_EXTERNREF
3242 { 780, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_EXNREF_S
3243 { 779, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 404, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_EXNREF
3244 { 778, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPYSIGN_F64_S
3245 { 777, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 167, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPYSIGN_F64
3246 { 776, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPYSIGN_F32_S
3247 { 775, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 164, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPYSIGN_F32
3248 { 774, 16, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 388, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_V128_I8x16_S
3249 { 773, 17, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 371, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_V128_I8x16
3250 { 772, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 369, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_V128_I64x2_S
3251 { 771, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 366, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_V128_I64x2
3252 { 770, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 362, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_V128_I32x4_S
3253 { 769, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 357, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_V128_I32x4
3254 { 768, 8, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 349, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_V128_I16x8_S
3255 { 767, 9, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 340, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_V128_I16x8
3256 { 766, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 338, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_V128_F64x2_S
3257 { 765, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 335, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_V128_F64x2
3258 { 764, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 331, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_V128_F32x4_S
3259 { 763, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 326, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_V128_F32x4
3260 { 762, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 325, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_I64_S
3261 { 761, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 323, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_I64
3262 { 760, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 322, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_I32_S
3263 { 759, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 320, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_I32
3264 { 758, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 319, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_F64_S
3265 { 757, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 317, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_F64
3266 { 756, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 316, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_F32_S
3267 { 755, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 314, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_F32
3268 { 754, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLZ_I64_S
3269 { 753, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 312, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLZ_I64
3270 { 752, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLZ_I32_S
3271 { 751, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 310, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLZ_I32
3272 { 750, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CEIL_F64x2_S
3273 { 749, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CEIL_F64x2
3274 { 748, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CEIL_F64_S
3275 { 747, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CEIL_F64
3276 { 746, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CEIL_F32x4_S
3277 { 745, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CEIL_F32x4
3278 { 744, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CEIL_F32_S
3279 { 743, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 157, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CEIL_F32
3280 { 742, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CEIL_F16x8_S
3281 { 741, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CEIL_F16x8
3282 { 740, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 308, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CATCH_S
3283 { 739, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 308, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CATCH_REF_S
3284 { 738, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 308, 3, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CATCH_REF
3285 { 737, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 308, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CATCH_LEGACY_S
3286 { 736, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 308, 3, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CATCH_LEGACY
3287 { 735, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CATCH_ALL_S
3288 { 734, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CATCH_ALL_REF_S
3289 { 733, 1, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 309, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CATCH_ALL_REF
3290 { 732, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CATCH_ALL_LEGACY_S
3291 { 731, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CATCH_ALL_LEGACY
3292 { 730, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CATCH_ALL
3293 { 729, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 308, 3, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CATCH
3294 { 728, 1, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 151, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CALL_S
3295 { 727, 1, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 307, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CALL_REF_S
3296 { 726, 2, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 305, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CALL_REF
3297 { 725, 2, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 303, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CALL_INDIRECT_S
3298 { 724, 2, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 303, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CALL_INDIRECT
3299 { 723, 1, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 151, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CALL
3300 { 722, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 154, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BR_UNLESS_S
3301 { 721, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 298, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BR_UNLESS
3302 { 720, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 301, 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BR_TABLE_I64_S
3303 { 719, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 302, 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BR_TABLE_I64
3304 { 718, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 301, 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BR_TABLE_I32_S
3305 { 717, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 300, 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BR_TABLE_I32
3306 { 716, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 154, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BR_S
3307 { 715, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 154, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BR_IF_S
3308 { 714, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 298, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BR_IF
3309 { 713, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 154, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BR
3310 { 712, 1, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 297, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLOCK_S
3311 { 711, 1, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 297, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLOCK
3312 { 710, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BITSELECT_S
3313 { 709, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 293, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BITSELECT
3314 { 708, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BITMASK_I8x16_S
3315 { 707, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 176, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BITMASK_I8x16
3316 { 706, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BITMASK_I64x2_S
3317 { 705, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 176, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BITMASK_I64x2
3318 { 704, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BITMASK_I32x4_S
3319 { 703, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 176, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BITMASK_I32x4
3320 { 702, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BITMASK_I16x8_S
3321 { 701, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 176, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BITMASK_I16x8
3322 { 700, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AVGR_U_I8x16_S
3323 { 699, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AVGR_U_I8x16
3324 { 698, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AVGR_U_I16x8_S
3325 { 697, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AVGR_U_I16x8
3326 { 696, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE_I64_A64_S
3327 { 695, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 288, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE_I64_A64
3328 { 694, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE_I64_A32_S
3329 { 693, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 283, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE_I64_A32
3330 { 692, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE_I32_A64_S
3331 { 691, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 278, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE_I32_A64
3332 { 690, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE_I32_A32_S
3333 { 689, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 273, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE_I32_A32
3334 { 688, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE8_I64_A64_S
3335 { 687, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 288, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE8_I64_A64
3336 { 686, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE8_I64_A32_S
3337 { 685, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 283, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE8_I64_A32
3338 { 684, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE8_I32_A64_S
3339 { 683, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 278, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE8_I32_A64
3340 { 682, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE8_I32_A32_S
3341 { 681, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 273, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE8_I32_A32
3342 { 680, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE32_I64_A64_S
3343 { 679, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 288, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE32_I64_A64
3344 { 678, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE32_I64_A32_S
3345 { 677, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 283, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE32_I64_A32
3346 { 676, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE16_I64_A64_S
3347 { 675, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 288, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE16_I64_A64
3348 { 674, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE16_I64_A32_S
3349 { 673, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 283, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE16_I64_A32
3350 { 672, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE16_I32_A64_S
3351 { 671, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 278, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE16_I32_A64
3352 { 670, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE16_I32_A32_S
3353 { 669, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 273, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE16_I32_A32
3354 { 668, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XOR_I64_A64_S
3355 { 667, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XOR_I64_A64
3356 { 666, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XOR_I64_A32_S
3357 { 665, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XOR_I64_A32
3358 { 664, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XOR_I32_A64_S
3359 { 663, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XOR_I32_A64
3360 { 662, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XOR_I32_A32_S
3361 { 661, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XOR_I32_A32
3362 { 660, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XCHG_I64_A64_S
3363 { 659, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XCHG_I64_A64
3364 { 658, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XCHG_I64_A32_S
3365 { 657, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XCHG_I64_A32
3366 { 656, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XCHG_I32_A64_S
3367 { 655, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XCHG_I32_A64
3368 { 654, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XCHG_I32_A32_S
3369 { 653, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XCHG_I32_A32
3370 { 652, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_SUB_I64_A64_S
3371 { 651, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_SUB_I64_A64
3372 { 650, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_SUB_I64_A32_S
3373 { 649, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_SUB_I64_A32
3374 { 648, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_SUB_I32_A64_S
3375 { 647, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_SUB_I32_A64
3376 { 646, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_SUB_I32_A32_S
3377 { 645, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_SUB_I32_A32
3378 { 644, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_OR_I64_A64_S
3379 { 643, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_OR_I64_A64
3380 { 642, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_OR_I64_A32_S
3381 { 641, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_OR_I64_A32
3382 { 640, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_OR_I32_A64_S
3383 { 639, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_OR_I32_A64
3384 { 638, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_OR_I32_A32_S
3385 { 637, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_OR_I32_A32
3386 { 636, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_CMPXCHG_I64_A64_S
3387 { 635, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 266, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_CMPXCHG_I64_A64
3388 { 634, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_CMPXCHG_I64_A32_S
3389 { 633, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 259, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_CMPXCHG_I64_A32
3390 { 632, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_CMPXCHG_I32_A64_S
3391 { 631, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 252, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_CMPXCHG_I32_A64
3392 { 630, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_CMPXCHG_I32_A32_S
3393 { 629, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 245, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_CMPXCHG_I32_A32
3394 { 628, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_AND_I64_A64_S
3395 { 627, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_AND_I64_A64
3396 { 626, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_AND_I64_A32_S
3397 { 625, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_AND_I64_A32
3398 { 624, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_AND_I32_A64_S
3399 { 623, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_AND_I32_A64
3400 { 622, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_AND_I32_A32_S
3401 { 621, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_AND_I32_A32
3402 { 620, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_ADD_I64_A64_S
3403 { 619, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_ADD_I64_A64
3404 { 618, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_ADD_I64_A32_S
3405 { 617, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_ADD_I64_A32
3406 { 616, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_ADD_I32_A64_S
3407 { 615, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_ADD_I32_A64
3408 { 614, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_ADD_I32_A32_S
3409 { 613, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_ADD_I32_A32
3410 { 612, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XOR_I64_A64_S
3411 { 611, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XOR_I64_A64
3412 { 610, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XOR_I64_A32_S
3413 { 609, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XOR_I64_A32
3414 { 608, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XOR_I32_A64_S
3415 { 607, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XOR_I32_A64
3416 { 606, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XOR_I32_A32_S
3417 { 605, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XOR_I32_A32
3418 { 604, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XCHG_I64_A64_S
3419 { 603, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XCHG_I64_A64
3420 { 602, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XCHG_I64_A32_S
3421 { 601, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XCHG_I64_A32
3422 { 600, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XCHG_I32_A64_S
3423 { 599, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XCHG_I32_A64
3424 { 598, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XCHG_I32_A32_S
3425 { 597, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XCHG_I32_A32
3426 { 596, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_SUB_I64_A64_S
3427 { 595, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_SUB_I64_A64
3428 { 594, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_SUB_I64_A32_S
3429 { 593, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_SUB_I64_A32
3430 { 592, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_SUB_I32_A64_S
3431 { 591, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_SUB_I32_A64
3432 { 590, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_SUB_I32_A32_S
3433 { 589, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_SUB_I32_A32
3434 { 588, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_OR_I64_A64_S
3435 { 587, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_OR_I64_A64
3436 { 586, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_OR_I64_A32_S
3437 { 585, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_OR_I64_A32
3438 { 584, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_OR_I32_A64_S
3439 { 583, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_OR_I32_A64
3440 { 582, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_OR_I32_A32_S
3441 { 581, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_OR_I32_A32
3442 { 580, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_CMPXCHG_I64_A64_S
3443 { 579, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 266, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_CMPXCHG_I64_A64
3444 { 578, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_CMPXCHG_I64_A32_S
3445 { 577, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 259, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_CMPXCHG_I64_A32
3446 { 576, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_CMPXCHG_I32_A64_S
3447 { 575, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 252, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_CMPXCHG_I32_A64
3448 { 574, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_CMPXCHG_I32_A32_S
3449 { 573, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 245, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_CMPXCHG_I32_A32
3450 { 572, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_AND_I64_A64_S
3451 { 571, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_AND_I64_A64
3452 { 570, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_AND_I64_A32_S
3453 { 569, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_AND_I64_A32
3454 { 568, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_AND_I32_A64_S
3455 { 567, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_AND_I32_A64
3456 { 566, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_AND_I32_A32_S
3457 { 565, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_AND_I32_A32
3458 { 564, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_ADD_I64_A64_S
3459 { 563, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_ADD_I64_A64
3460 { 562, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_ADD_I64_A32_S
3461 { 561, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_ADD_I64_A32
3462 { 560, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_ADD_I32_A64_S
3463 { 559, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_ADD_I32_A64
3464 { 558, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_ADD_I32_A32_S
3465 { 557, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_ADD_I32_A32
3466 { 556, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_XOR_I64_A64_S
3467 { 555, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_XOR_I64_A64
3468 { 554, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_XOR_I64_A32_S
3469 { 553, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_XOR_I64_A32
3470 { 552, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_XCHG_I64_A64_S
3471 { 551, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_XCHG_I64_A64
3472 { 550, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_XCHG_I64_A32_S
3473 { 549, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_XCHG_I64_A32
3474 { 548, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_SUB_I64_A64_S
3475 { 547, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_SUB_I64_A64
3476 { 546, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_SUB_I64_A32_S
3477 { 545, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_SUB_I64_A32
3478 { 544, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_OR_I64_A64_S
3479 { 543, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_OR_I64_A64
3480 { 542, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_OR_I64_A32_S
3481 { 541, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_OR_I64_A32
3482 { 540, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_CMPXCHG_I64_A64_S
3483 { 539, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 266, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_CMPXCHG_I64_A64
3484 { 538, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_CMPXCHG_I64_A32_S
3485 { 537, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 259, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_CMPXCHG_I64_A32
3486 { 536, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_AND_I64_A64_S
3487 { 535, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_AND_I64_A64
3488 { 534, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_AND_I64_A32_S
3489 { 533, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_AND_I64_A32
3490 { 532, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_ADD_I64_A64_S
3491 { 531, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_ADD_I64_A64
3492 { 530, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_ADD_I64_A32_S
3493 { 529, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_ADD_I64_A32
3494 { 528, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XOR_I64_A64_S
3495 { 527, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XOR_I64_A64
3496 { 526, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XOR_I64_A32_S
3497 { 525, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XOR_I64_A32
3498 { 524, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XOR_I32_A64_S
3499 { 523, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XOR_I32_A64
3500 { 522, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XOR_I32_A32_S
3501 { 521, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XOR_I32_A32
3502 { 520, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XCHG_I64_A64_S
3503 { 519, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XCHG_I64_A64
3504 { 518, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XCHG_I64_A32_S
3505 { 517, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XCHG_I64_A32
3506 { 516, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XCHG_I32_A64_S
3507 { 515, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XCHG_I32_A64
3508 { 514, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XCHG_I32_A32_S
3509 { 513, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XCHG_I32_A32
3510 { 512, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_SUB_I64_A64_S
3511 { 511, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_SUB_I64_A64
3512 { 510, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_SUB_I64_A32_S
3513 { 509, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_SUB_I64_A32
3514 { 508, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_SUB_I32_A64_S
3515 { 507, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_SUB_I32_A64
3516 { 506, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_SUB_I32_A32_S
3517 { 505, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_SUB_I32_A32
3518 { 504, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_OR_I64_A64_S
3519 { 503, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_OR_I64_A64
3520 { 502, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_OR_I64_A32_S
3521 { 501, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_OR_I64_A32
3522 { 500, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_OR_I32_A64_S
3523 { 499, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_OR_I32_A64
3524 { 498, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_OR_I32_A32_S
3525 { 497, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_OR_I32_A32
3526 { 496, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_CMPXCHG_I64_A64_S
3527 { 495, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 266, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_CMPXCHG_I64_A64
3528 { 494, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_CMPXCHG_I64_A32_S
3529 { 493, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 259, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_CMPXCHG_I64_A32
3530 { 492, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_CMPXCHG_I32_A64_S
3531 { 491, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 252, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_CMPXCHG_I32_A64
3532 { 490, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_CMPXCHG_I32_A32_S
3533 { 489, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 245, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_CMPXCHG_I32_A32
3534 { 488, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_AND_I64_A64_S
3535 { 487, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_AND_I64_A64
3536 { 486, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_AND_I64_A32_S
3537 { 485, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_AND_I64_A32
3538 { 484, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_AND_I32_A64_S
3539 { 483, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_AND_I32_A64
3540 { 482, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_AND_I32_A32_S
3541 { 481, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_AND_I32_A32
3542 { 480, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_ADD_I64_A64_S
3543 { 479, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_ADD_I64_A64
3544 { 478, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_ADD_I64_A32_S
3545 { 477, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_ADD_I64_A32
3546 { 476, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_ADD_I32_A64_S
3547 { 475, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_ADD_I32_A64
3548 { 474, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_ADD_I32_A32_S
3549 { 473, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_ADD_I32_A32
3550 { 472, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD_I64_A64_S
3551 { 471, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 216, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD_I64_A64
3552 { 470, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD_I64_A32_S
3553 { 469, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 211, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD_I64_A32
3554 { 468, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD_I32_A64_S
3555 { 467, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 203, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD_I32_A64
3556 { 466, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD_I32_A32_S
3557 { 465, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 195, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD_I32_A32
3558 { 464, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD8_U_I64_A64_S
3559 { 463, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 216, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD8_U_I64_A64
3560 { 462, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD8_U_I64_A32_S
3561 { 461, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 211, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD8_U_I64_A32
3562 { 460, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD8_U_I32_A64_S
3563 { 459, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 203, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD8_U_I32_A64
3564 { 458, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD8_U_I32_A32_S
3565 { 457, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 195, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD8_U_I32_A32
3566 { 456, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD32_U_I64_A64_S
3567 { 455, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 216, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD32_U_I64_A64
3568 { 454, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD32_U_I64_A32_S
3569 { 453, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 211, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD32_U_I64_A32
3570 { 452, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD16_U_I64_A64_S
3571 { 451, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 216, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD16_U_I64_A64
3572 { 450, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD16_U_I64_A32_S
3573 { 449, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 211, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD16_U_I64_A32
3574 { 448, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD16_U_I32_A64_S
3575 { 447, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 203, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD16_U_I32_A64
3576 { 446, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD16_U_I32_A32_S
3577 { 445, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 195, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD16_U_I32_A32
3578 { 444, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 194, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_FENCE_S
3579 { 443, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 194, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_FENCE
3580 { 442, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v8i16_S
3581 { 441, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 192, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v8i16
3582 { 440, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v8f16_S
3583 { 439, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 192, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v8f16
3584 { 438, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v4i32_S
3585 { 437, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 192, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v4i32
3586 { 436, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v4f32_S
3587 { 435, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 192, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v4f32
3588 { 434, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v2i64_S
3589 { 433, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 192, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v2i64
3590 { 432, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v2f64_S
3591 { 431, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 192, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v2f64
3592 { 430, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v16i8_S
3593 { 429, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 192, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v16i8
3594 { 428, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_i64_S
3595 { 427, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 190, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_i64
3596 { 426, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_i32_S
3597 { 425, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 188, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_i32
3598 { 424, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_funcref_S
3599 { 423, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 186, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_funcref
3600 { 422, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_f64_S
3601 { 421, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 184, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_f64
3602 { 420, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_f32_S
3603 { 419, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 182, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_f32
3604 { 418, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_externref_S
3605 { 417, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 180, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_externref
3606 { 416, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_exnref_S
3607 { 415, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 178, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_exnref
3608 { 414, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANYTRUE_S
3609 { 413, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 176, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANYTRUE
3610 { 412, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_S
3611 { 411, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_I64_S
3612 { 410, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_I64
3613 { 409, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_I32_S
3614 { 408, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_I32
3615 { 407, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANDNOT_S
3616 { 406, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANDNOT
3617 { 405, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND
3618 { 404, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ALLTRUE_I8x16_S
3619 { 403, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 176, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ALLTRUE_I8x16
3620 { 402, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ALLTRUE_I64x2_S
3621 { 401, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 176, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ALLTRUE_I64x2
3622 { 400, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ALLTRUE_I32x4_S
3623 { 399, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 176, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ALLTRUE_I32x4
3624 { 398, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ALLTRUE_I16x8_S
3625 { 397, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 176, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ALLTRUE_I16x8
3626 { 396, 2, 0, 0, 0, 2, 2, WebAssemblyOpInfoBase + 20, 4, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKUP_S
3627 { 395, 2, 0, 0, 0, 2, 2, WebAssemblyOpInfoBase + 20, 4, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKUP
3628 { 394, 2, 0, 0, 0, 2, 2, WebAssemblyOpInfoBase + 20, 4, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKDOWN_S
3629 { 393, 2, 0, 0, 0, 2, 2, WebAssemblyOpInfoBase + 20, 4, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKDOWN
3630 { 392, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_SAT_U_I8x16_S
3631 { 391, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_SAT_U_I8x16
3632 { 390, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_SAT_U_I16x8_S
3633 { 389, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_SAT_U_I16x8
3634 { 388, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_SAT_S_I8x16_S
3635 { 387, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_SAT_S_I8x16
3636 { 386, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_SAT_S_I16x8_S
3637 { 385, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_SAT_S_I16x8
3638 { 384, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I8x16_S
3639 { 383, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I8x16
3640 { 382, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I64x2_S
3641 { 381, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I64x2
3642 { 380, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I64_S
3643 { 379, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I64
3644 { 378, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I32x4_S
3645 { 377, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I32x4
3646 { 376, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I32_S
3647 { 375, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I32
3648 { 374, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I16x8_S
3649 { 373, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I16x8
3650 { 372, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F64x2_S
3651 { 371, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F64x2
3652 { 370, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F64_S
3653 { 369, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 167, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F64
3654 { 368, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F32x4_S
3655 { 367, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F32x4
3656 { 366, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F32_S
3657 { 365, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 164, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F32
3658 { 364, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F16x8_S
3659 { 363, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F16x8
3660 { 362, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_I8x16_S
3661 { 361, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_I8x16
3662 { 360, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_I64x2_S
3663 { 359, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_I64x2
3664 { 358, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_I32x4_S
3665 { 357, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_I32x4
3666 { 356, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_I16x8_S
3667 { 355, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_I16x8
3668 { 354, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_F64x2_S
3669 { 353, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_F64x2
3670 { 352, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_F64_S
3671 { 351, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_F64
3672 { 350, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_F32x4_S
3673 { 349, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_F32x4
3674 { 348, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_F32_S
3675 { 347, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 157, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_F32
3676 { 346, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_F16x8_S
3677 { 345, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_F16x8
3678 { 344, 0, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // RET_CALL_RESULTS_S
3679 { 343, 0, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // RET_CALL_RESULTS
3680 { 342, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COMPILER_FENCE_S
3681 { 341, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COMPILER_FENCE
3682 { 340, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 154, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLEANUPRET_S
3683 { 339, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 154, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLEANUPRET
3684 { 338, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 152, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CATCHRET_S
3685 { 337, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 152, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CATCHRET
3686 { 336, 0, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CALL_RESULTS_S
3687 { 335, 0, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CALL_RESULTS
3688 { 334, 1, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 151, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CALL_PARAMS_S
3689 { 333, 1, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 151, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CALL_PARAMS
3690 { 332, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBFX
3691 { 331, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SBFX
3692 { 330, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMIN
3693 { 329, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMAX
3694 { 328, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMIN
3695 { 327, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMAX
3696 { 326, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_XOR
3697 { 325, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_OR
3698 { 324, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_AND
3699 { 323, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_MUL
3700 { 322, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_ADD
3701 { 321, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMINIMUMNUM
3702 { 320, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAXIMUMNUM
3703 { 319, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMINIMUM
3704 { 318, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAXIMUM
3705 { 317, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMIN
3706 { 316, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAX
3707 { 315, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMUL
3708 { 314, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FADD
3709 { 313, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FMUL
3710 { 312, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FADD
3711 { 311, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBSANTRAP
3712 { 310, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DEBUGTRAP
3713 { 309, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRAP
3714 { 308, 3, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET_INLINE
3715 { 307, 3, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BZERO
3716 { 306, 4, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET
3717 { 305, 4, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMMOVE
3718 { 304, 3, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY_INLINE
3719 { 303, 4, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY
3720 { 302, 2, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 141, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_WRITE_REGISTER
3721 { 301, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_READ_REGISTER
3722 { 300, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FCMPS
3723 { 299, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FCMP
3724 { 298, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FLDEXP
3725 { 297, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSQRT
3726 { 296, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMA
3727 { 295, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FREM
3728 { 294, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FDIV
3729 { 293, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMUL
3730 { 292, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSUB
3731 { 291, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FADD
3732 { 290, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKRESTORE
3733 { 289, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKSAVE
3734 { 288, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DYN_STACKALLOC
3735 { 287, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_JUMP_TABLE
3736 { 286, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BLOCK_ADDR
3737 { 285, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADDRSPACE_CAST
3738 { 284, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEARBYINT
3739 { 283, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRINT
3740 { 282, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFLOOR
3741 { 281, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSQRT
3742 { 280, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTANH
3743 { 279, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINH
3744 { 278, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOSH
3745 { 277, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN2
3746 { 276, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN
3747 { 275, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FASIN
3748 { 274, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FACOS
3749 { 273, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTAN
3750 { 272, 3, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINCOS
3751 { 271, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSIN
3752 { 270, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOS
3753 { 269, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCEIL
3754 { 268, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CLMUL
3755 { 267, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITREVERSE
3756 { 266, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BSWAP
3757 { 265, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTPOP
3758 { 264, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLS
3759 { 263, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ_ZERO_POISON
3760 { 262, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ
3761 { 261, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ_ZERO_POISON
3762 { 260, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ
3763 { 259, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 137, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECTOR_COMPRESS
3764 { 258, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STEP_VECTOR
3765 { 257, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SPLAT_VECTOR
3766 { 256, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 133, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHUFFLE_VECTOR
3767 { 255, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_VECTOR_ELT
3768 { 254, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 126, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_VECTOR_ELT
3769 { 253, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_SUBVECTOR
3770 { 252, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_SUBVECTOR
3771 { 251, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VSCALE
3772 { 250, 3, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRJT
3773 { 249, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BR
3774 { 248, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LLROUND
3775 { 247, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LROUND
3776 { 246, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABS
3777 { 245, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMAX
3778 { 244, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMIN
3779 { 243, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMAX
3780 { 242, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMIN
3781 { 241, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRMASK
3782 { 240, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTR_ADD
3783 { 239, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_ROUNDING
3784 { 238, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_ROUNDING
3785 { 237, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPMODE
3786 { 236, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPMODE
3787 { 235, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPMODE
3788 { 234, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPENV
3789 { 233, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPENV
3790 { 232, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPENV
3791 { 231, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUMNUM
3792 { 230, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUMNUM
3793 { 229, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUM
3794 { 228, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUM
3795 { 227, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM_IEEE
3796 { 226, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM_IEEE
3797 { 225, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM
3798 { 224, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM
3799 { 223, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCANONICALIZE
3800 { 222, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IS_FPCLASS
3801 { 221, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOPYSIGN
3802 { 220, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FABS
3803 { 219, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI_SAT
3804 { 218, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI_SAT
3805 { 217, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UITOFP
3806 { 216, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SITOFP
3807 { 215, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI
3808 { 214, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI
3809 { 213, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNC
3810 { 212, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXT
3811 { 211, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEG
3812 { 210, 3, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFREXP
3813 { 209, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLDEXP
3814 { 208, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG10
3815 { 207, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG2
3816 { 206, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG
3817 { 205, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP10
3818 { 204, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP2
3819 { 203, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP
3820 { 202, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOWI
3821 { 201, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOW
3822 { 200, 3, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMODF
3823 { 199, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREM
3824 { 198, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FDIV
3825 { 197, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAD
3826 { 196, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMA
3827 { 195, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMUL
3828 { 194, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSUB
3829 { 193, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FADD
3830 { 192, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIXSAT
3831 { 191, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIXSAT
3832 { 190, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIX
3833 { 189, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIX
3834 { 188, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIXSAT
3835 { 187, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIXSAT
3836 { 186, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIX
3837 { 185, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIX
3838 { 184, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSHLSAT
3839 { 183, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USHLSAT
3840 { 182, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBSAT
3841 { 181, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBSAT
3842 { 180, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDSAT
3843 { 179, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDSAT
3844 { 178, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULH
3845 { 177, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULH
3846 { 176, 4, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULO
3847 { 175, 4, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULO
3848 { 174, 5, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBE
3849 { 173, 4, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBO
3850 { 172, 5, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDE
3851 { 171, 4, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDO
3852 { 170, 5, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBE
3853 { 169, 4, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBO
3854 { 168, 5, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDE
3855 { 167, 4, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDO
3856 { 166, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SELECT
3857 { 165, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UCMP
3858 { 164, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SCMP
3859 { 163, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCMP
3860 { 162, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ICMP
3861 { 161, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTL
3862 { 160, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTR
3863 { 159, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHR
3864 { 158, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHL
3865 { 157, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASHR
3866 { 156, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LSHR
3867 { 155, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHL
3868 { 154, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXT
3869 { 153, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT_INREG
3870 { 152, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT
3871 { 151, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VAARG
3872 { 150, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VASTART
3873 { 149, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCONSTANT
3874 { 148, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT
3875 { 147, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_USAT_U
3876 { 146, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_U
3877 { 145, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_S
3878 { 144, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC
3879 { 143, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ANYEXT
3880 { 142, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
3881 { 141, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT
3882 { 140, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_W_SIDE_EFFECTS
3883 { 139, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC
3884 { 138, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INVOKE_REGION_START
3885 { 137, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRINDIRECT
3886 { 136, 2, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRCOND
3887 { 135, 4, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 93, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PREFETCH
3888 { 134, 2, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 20, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FENCE
3889 { 133, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_SAT
3890 { 132, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_COND
3891 { 131, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UDEC_WRAP
3892 { 130, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UINC_WRAP
3893 { 129, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUMNUM
3894 { 128, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUMNUM
3895 { 127, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUM
3896 { 126, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUM
3897 { 125, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMIN
3898 { 124, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAX
3899 { 123, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FSUB
3900 { 122, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FADD
3901 { 121, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMIN
3902 { 120, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMAX
3903 { 119, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MIN
3904 { 118, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MAX
3905 { 117, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XOR
3906 { 116, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_OR
3907 { 115, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_NAND
3908 { 114, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_AND
3909 { 113, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_SUB
3910 { 112, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_ADD
3911 { 111, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XCHG
3912 { 110, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG
3913 { 109, 5, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 81, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
3914 { 108, 5, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 76, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_STORE
3915 { 107, 2, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNCSTORE
3916 { 106, 2, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STORE
3917 { 105, 5, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_ZEXTLOAD
3918 { 104, 5, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_SEXTLOAD
3919 { 103, 5, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_LOAD
3920 { 102, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXTLOAD
3921 { 101, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXTLOAD
3922 { 100, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXTLOAD
3923 { 99, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LOAD
3924 { 98, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READSTEADYCOUNTER
3925 { 97, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READCYCLECOUNTER
3926 { 96, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUNDEVEN
3927 { 95, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LLRINT
3928 { 94, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LRINT
3929 { 93, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUND
3930 { 92, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_TRUNC
3931 { 91, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_FPTRUNC_ROUND
3932 { 90, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_FOLD_BARRIER
3933 { 89, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREEZE
3934 { 88, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITCAST
3935 { 87, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTTOPTR
3936 { 86, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRTOINT
3937 { 85, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONCAT_VECTORS
3938 { 84, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR_TRUNC
3939 { 83, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR
3940 { 82, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MERGE_VALUES
3941 { 81, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT
3942 { 80, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UNMERGE_VALUES
3943 { 79, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT
3944 { 78, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_POOL
3945 { 77, 5, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 52, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRAUTH_GLOBAL_VALUE
3946 { 76, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GLOBAL_VALUE
3947 { 75, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRAME_INDEX
3948 { 74, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PHI
3949 { 73, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IMPLICIT_DEF
3950 { 72, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGCEIL
3951 { 71, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGFLOOR
3952 { 70, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGCEIL
3953 { 69, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGFLOOR
3954 { 68, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDU
3955 { 67, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDS
3956 { 66, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_XOR
3957 { 65, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_OR
3958 { 64, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_AND
3959 { 63, 4, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVREM
3960 { 62, 4, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVREM
3961 { 61, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UREM
3962 { 60, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SREM
3963 { 59, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIV
3964 { 58, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIV
3965 { 57, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MUL
3966 { 56, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SUB
3967 { 55, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADD
3968 { 54, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ALIGN
3969 { 53, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ZEXT
3970 { 52, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_SEXT
3971 { 51, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_GLUE
3972 { 50, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_LOOP
3973 { 49, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ANCHOR
3974 { 48, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ENTRY
3975 { 47, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELOC_NONE
3976 { 46, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUMP_TABLE_DEBUG_INFO
3977 { 45, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMBARRIER
3978 { 44, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAKE_USE
3979 { 43, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ICALL_BRANCH_FUNNEL
3980 { 42, 3, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 36, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_15278
3981 { 41, 2, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 34, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_15277
3982 { 40, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_TAIL_CALL
3983 { 39, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_EXIT
3984 { 38, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_RET
3985 { 37, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_ENTER
3986 { 36, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_OP
3987 { 35, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAULTING_OP
3988 { 34, 2, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 32, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_ESCAPE
3989 { 33, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STATEPOINT
3990 { 32, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 29, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_15276
3991 { 31, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PREALLOCATED_SETUP
3992 { 30, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 28, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_13978
3993 { 29, 6, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 22, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHPOINT
3994 { 28, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FENTRY_CALL
3995 { 27, 2, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STACKMAP
3996 { 26, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 18, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARITH_FENCE
3997 { 25, 4, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 14, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PSEUDO_PROBE
3998 { 24, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_END
3999 { 23, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_START
4000 { 22, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BUNDLE
4001 { 21, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 11, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_LANEMASK
4002 { 20, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY
4003 { 19, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REG_SEQUENCE
4004 { 18, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_LABEL
4005 { 17, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_PHI
4006 { 16, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_INSTR_REF
4007 { 15, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE_LIST
4008 { 14, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE
4009 { 13, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_TO_REGCLASS
4010 { 12, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBREG_TO_REG
4011 { 11, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INIT_UNDEF
4012 { 10, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // IMPLICIT_DEF
4013 { 9, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 5, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INSERT_SUBREG
4014 { 8, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_SUBREG
4015 { 7, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KILL
4016 { 6, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANNOTATION_LABEL
4017 { 5, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GC_LABEL
4018 { 4, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EH_LABEL
4019 { 3, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CFI_INSTRUCTION
4020 { 2, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM_BR
4021 { 1, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM
4022 { 0, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PHI
4023 }, {
4024 /* 0 */
4025 /* 0 */ WebAssembly::SP32, WebAssembly::SP64, WebAssembly::ARGUMENTS,
4026 /* 3 */ WebAssembly::ARGUMENTS,
4027 /* 4 */ WebAssembly::SP32, WebAssembly::SP64, WebAssembly::SP32, WebAssembly::SP64,
4028 /* 8 */ WebAssembly::VALUE_STACK, WebAssembly::VALUE_STACK,
4029 }, {
4030 0
4031 }, {
4032 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4033 /* 1 */
4034 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4035 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4036 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4037 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4038 /* 11 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4039 /* 14 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4040 /* 18 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
4041 /* 20 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4042 /* 22 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4043 /* 28 */ { WebAssembly::wasm_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 },
4044 /* 29 */ { WebAssembly::wasm_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4045 /* 32 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4046 /* 34 */ { WebAssembly::wasm_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4047 /* 36 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { WebAssembly::wasm_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4048 /* 39 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
4049 /* 42 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
4050 /* 45 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
4051 /* 49 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
4052 /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4053 /* 52 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4054 /* 57 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
4055 /* 60 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
4056 /* 62 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
4057 /* 66 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
4058 /* 68 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4059 /* 71 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4060 /* 76 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4061 /* 81 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
4062 /* 86 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
4063 /* 90 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
4064 /* 93 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_2, 0 },
4065 /* 97 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4066 /* 100 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
4067 /* 103 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
4068 /* 107 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
4069 /* 111 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
4070 /* 114 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
4071 /* 119 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
4072 /* 123 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
4073 /* 126 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
4074 /* 130 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
4075 /* 133 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4076 /* 137 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
4077 /* 141 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
4078 /* 143 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
4079 /* 147 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
4080 /* 151 */ { -1, 0, WebAssembly::OPERAND_FUNCTION32, 0 },
4081 /* 152 */ { -1, 0, WebAssembly::OPERAND_BASIC_BLOCK, 0 }, { -1, 0, WebAssembly::OPERAND_BASIC_BLOCK, 0 },
4082 /* 154 */ { -1, 0, WebAssembly::OPERAND_BASIC_BLOCK, 0 },
4083 /* 155 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4084 /* 157 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4085 /* 159 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4086 /* 161 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4087 /* 164 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4088 /* 167 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4089 /* 170 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4090 /* 173 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4091 /* 176 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4092 /* 178 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4093 /* 180 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4094 /* 182 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4095 /* 184 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4096 /* 186 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4097 /* 188 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4098 /* 190 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4099 /* 192 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4100 /* 194 */ { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 },
4101 /* 195 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4102 /* 200 */ { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 },
4103 /* 203 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4104 /* 208 */ { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 },
4105 /* 211 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4106 /* 216 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4107 /* 221 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4108 /* 227 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4109 /* 233 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4110 /* 239 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4111 /* 245 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4112 /* 252 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4113 /* 259 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4114 /* 266 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4115 /* 273 */ { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4116 /* 278 */ { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4117 /* 283 */ { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4118 /* 288 */ { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4119 /* 293 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4120 /* 297 */ { -1, 0, WebAssembly::OPERAND_SIGNATURE, 0 },
4121 /* 298 */ { -1, 0, WebAssembly::OPERAND_BASIC_BLOCK, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4122 /* 300 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4123 /* 301 */ { -1, 0, WebAssembly::OPERAND_BRLIST, 0 },
4124 /* 302 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4125 /* 303 */ { -1, 0, WebAssembly::OPERAND_TYPEINDEX, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 },
4126 /* 305 */ { -1, 0, WebAssembly::OPERAND_TYPEINDEX, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4127 /* 307 */ { -1, 0, WebAssembly::OPERAND_TYPEINDEX, 0 },
4128 /* 308 */ { -1, 0, WebAssembly::OPERAND_TAG, 0 },
4129 /* 309 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4130 /* 310 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4131 /* 312 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4132 /* 314 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 },
4133 /* 316 */ { -1, 0, WebAssembly::OPERAND_F32IMM, 0 },
4134 /* 317 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_F64IMM, 0 },
4135 /* 319 */ { -1, 0, WebAssembly::OPERAND_F64IMM, 0 },
4136 /* 320 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_I32IMM, 0 },
4137 /* 322 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 },
4138 /* 323 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_I64IMM, 0 },
4139 /* 325 */ { -1, 0, WebAssembly::OPERAND_I64IMM, 0 },
4140 /* 326 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 },
4141 /* 331 */ { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 },
4142 /* 335 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_F64IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F64IMM, 0 },
4143 /* 338 */ { -1, 0, WebAssembly::OPERAND_F64IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F64IMM, 0 },
4144 /* 340 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 },
4145 /* 349 */ { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 },
4146 /* 357 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 },
4147 /* 362 */ { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 },
4148 /* 366 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I64IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I64IMM, 0 },
4149 /* 369 */ { -1, 0, WebAssembly::OPERAND_VEC_I64IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I64IMM, 0 },
4150 /* 371 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 },
4151 /* 388 */ { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 },
4152 /* 404 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4153 /* 406 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4154 /* 408 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4155 /* 410 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4156 /* 411 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4157 /* 412 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4158 /* 413 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4159 /* 414 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4160 /* 415 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4161 /* 417 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4162 /* 420 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4163 /* 423 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4164 /* 426 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 },
4165 /* 429 */ { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 },
4166 /* 430 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 },
4167 /* 433 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 },
4168 /* 436 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 },
4169 /* 439 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4170 /* 441 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4171 /* 443 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4172 /* 445 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4173 /* 447 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4174 /* 449 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4175 /* 451 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4176 /* 453 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4177 /* 455 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4178 /* 457 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4179 /* 459 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 },
4180 /* 461 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 },
4181 /* 462 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 },
4182 /* 464 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 },
4183 /* 466 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 },
4184 /* 468 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 },
4185 /* 470 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 },
4186 /* 472 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 },
4187 /* 474 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 },
4188 /* 476 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4189 /* 478 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4190 /* 480 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4191 /* 482 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4192 /* 484 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4193 /* 486 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4194 /* 488 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4195 /* 490 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4196 /* 492 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4197 /* 498 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4198 /* 500 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4199 /* 504 */ { -1, 0, WebAssembly::OPERAND_SIGNATURE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4200 /* 506 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4201 /* 510 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 },
4202 /* 512 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4203 /* 516 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 },
4204 /* 518 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4205 /* 522 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4206 /* 526 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4207 /* 530 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4208 /* 534 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4209 /* 538 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4210 /* 542 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4211 /* 546 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4212 /* 550 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4213 /* 556 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 },
4214 /* 559 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4215 /* 565 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 },
4216 /* 568 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 },
4217 /* 570 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 },
4218 /* 571 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 },
4219 /* 573 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 },
4220 /* 575 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 },
4221 /* 577 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 },
4222 /* 579 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 },
4223 /* 581 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 },
4224 /* 583 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 },
4225 /* 585 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4226 /* 587 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4227 /* 589 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4228 /* 591 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4229 /* 593 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4230 /* 595 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4231 /* 597 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4232 /* 599 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4233 /* 601 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4234 /* 604 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4235 /* 607 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4236 /* 610 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4237 /* 613 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4238 /* 616 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4239 /* 619 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4240 /* 622 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4241 /* 625 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4242 /* 630 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_I32IMM, 0 },
4243 /* 632 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4244 /* 637 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4245 /* 644 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4246 /* 651 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4247 /* 658 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4248 /* 665 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4249 /* 669 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4250 /* 673 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4251 /* 678 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TYPEINDEX, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4252 /* 681 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_FUNCTION32, 0 },
4253 /* 683 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4254 /* 685 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4255 /* 687 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4256 /* 689 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TYPEINDEX, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4257 /* 692 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4258 /* 696 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4259 /* 700 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4260 /* 704 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4261 /* 708 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4262 /* 712 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4263 /* 716 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4264 /* 720 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4265 /* 724 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4266 /* 728 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4267 /* 732 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4268 /* 736 */ { -1, 0, WebAssembly::OPERAND_VALTYPE_LIST, 0 },
4269 /* 737 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4270 /* 741 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4271 /* 744 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 },
4272 /* 763 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4273 /* 765 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4274 /* 767 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4275 /* 769 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4276 /* 771 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4277 /* 775 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4278 /* 779 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4279 /* 783 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4280 /* 787 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4281 /* 791 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4282 /* 795 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4283 /* 799 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4284 /* 803 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4285 /* 808 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4286 /* 813 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4287 /* 817 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4288 /* 821 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4289 /* 826 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 },
4290 /* 828 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4291 /* 832 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 },
4292 /* 833 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4293 /* 837 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4294 /* 841 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4295 /* 844 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4296 /* 847 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4297 /* 850 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4298 /* 854 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4299 /* 858 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4300 /* 862 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4301 /* 865 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4302 /* 868 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4303 /* 871 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 },
4304 /* 873 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4305 /* 876 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4306 /* 879 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4307 /* 882 */ { -1, 0, WebAssembly::OPERAND_SIGNATURE, 0 }, { -1, 0, WebAssembly::OPERAND_CATCH_LIST, 0 },
4308 /* 884 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4309 /* 887 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4310 }
4311};
4312
4313
4314#ifdef __GNUC__
4315#pragma GCC diagnostic push
4316#pragma GCC diagnostic ignored "-Woverlength-strings"
4317#endif
4318extern const char WebAssemblyInstrNameData[] = {
4319 /* 0 */ "G_FLOG10\000"
4320 /* 9 */ "G_FEXP10\000"
4321 /* 18 */ "LOAD_F16_F32_A32\000"
4322 /* 35 */ "STORE_F16_F32_A32\000"
4323 /* 53 */ "LOAD_F32_A32\000"
4324 /* 66 */ "STORE_F32_A32\000"
4325 /* 80 */ "ATOMIC_STORE16_I32_A32\000"
4326 /* 103 */ "ATOMIC_STORE8_I32_A32\000"
4327 /* 125 */ "ATOMIC_RMW16_U_SUB_I32_A32\000"
4328 /* 152 */ "ATOMIC_RMW8_U_SUB_I32_A32\000"
4329 /* 178 */ "ATOMIC_RMW_SUB_I32_A32\000"
4330 /* 201 */ "ATOMIC_LOAD_I32_A32\000"
4331 /* 221 */ "ATOMIC_RMW16_U_ADD_I32_A32\000"
4332 /* 248 */ "ATOMIC_RMW8_U_ADD_I32_A32\000"
4333 /* 274 */ "ATOMIC_RMW_ADD_I32_A32\000"
4334 /* 297 */ "ATOMIC_RMW16_U_AND_I32_A32\000"
4335 /* 324 */ "ATOMIC_RMW8_U_AND_I32_A32\000"
4336 /* 350 */ "ATOMIC_RMW_AND_I32_A32\000"
4337 /* 373 */ "ATOMIC_STORE_I32_A32\000"
4338 /* 394 */ "ATOMIC_RMW16_U_CMPXCHG_I32_A32\000"
4339 /* 425 */ "ATOMIC_RMW8_U_CMPXCHG_I32_A32\000"
4340 /* 455 */ "ATOMIC_RMW_CMPXCHG_I32_A32\000"
4341 /* 482 */ "ATOMIC_RMW16_U_XCHG_I32_A32\000"
4342 /* 510 */ "ATOMIC_RMW8_U_XCHG_I32_A32\000"
4343 /* 537 */ "ATOMIC_RMW_XCHG_I32_A32\000"
4344 /* 561 */ "ATOMIC_RMW16_U_XOR_I32_A32\000"
4345 /* 588 */ "ATOMIC_RMW8_U_XOR_I32_A32\000"
4346 /* 614 */ "ATOMIC_RMW_XOR_I32_A32\000"
4347 /* 637 */ "ATOMIC_RMW16_U_OR_I32_A32\000"
4348 /* 663 */ "ATOMIC_RMW8_U_OR_I32_A32\000"
4349 /* 688 */ "ATOMIC_RMW_OR_I32_A32\000"
4350 /* 710 */ "LOAD16_S_I32_A32\000"
4351 /* 727 */ "LOAD8_S_I32_A32\000"
4352 /* 743 */ "ATOMIC_LOAD16_U_I32_A32\000"
4353 /* 767 */ "ATOMIC_LOAD8_U_I32_A32\000"
4354 /* 790 */ "MEMORY_ATOMIC_WAIT32_A32\000"
4355 /* 815 */ "LOAD_LANE_32_A32\000"
4356 /* 832 */ "LOAD_ZERO_32_A32\000"
4357 /* 849 */ "STORE_LANE_I64x2_A32\000"
4358 /* 870 */ "LOAD_EXTEND_S_I64x2_A32\000"
4359 /* 894 */ "LOAD_EXTEND_U_I64x2_A32\000"
4360 /* 918 */ "LOAD_F64_A32\000"
4361 /* 931 */ "STORE_F64_A32\000"
4362 /* 945 */ "ATOMIC_STORE32_I64_A32\000"
4363 /* 968 */ "ATOMIC_STORE16_I64_A32\000"
4364 /* 991 */ "ATOMIC_STORE8_I64_A32\000"
4365 /* 1013 */ "ATOMIC_RMW32_U_SUB_I64_A32\000"
4366 /* 1040 */ "ATOMIC_RMW16_U_SUB_I64_A32\000"
4367 /* 1067 */ "ATOMIC_RMW8_U_SUB_I64_A32\000"
4368 /* 1093 */ "ATOMIC_RMW_SUB_I64_A32\000"
4369 /* 1116 */ "ATOMIC_LOAD_I64_A32\000"
4370 /* 1136 */ "ATOMIC_RMW32_U_ADD_I64_A32\000"
4371 /* 1163 */ "ATOMIC_RMW16_U_ADD_I64_A32\000"
4372 /* 1190 */ "ATOMIC_RMW8_U_ADD_I64_A32\000"
4373 /* 1216 */ "ATOMIC_RMW_ADD_I64_A32\000"
4374 /* 1239 */ "ATOMIC_RMW32_U_AND_I64_A32\000"
4375 /* 1266 */ "ATOMIC_RMW16_U_AND_I64_A32\000"
4376 /* 1293 */ "ATOMIC_RMW8_U_AND_I64_A32\000"
4377 /* 1319 */ "ATOMIC_RMW_AND_I64_A32\000"
4378 /* 1342 */ "ATOMIC_STORE_I64_A32\000"
4379 /* 1363 */ "ATOMIC_RMW32_U_CMPXCHG_I64_A32\000"
4380 /* 1394 */ "ATOMIC_RMW16_U_CMPXCHG_I64_A32\000"
4381 /* 1425 */ "ATOMIC_RMW8_U_CMPXCHG_I64_A32\000"
4382 /* 1455 */ "ATOMIC_RMW_CMPXCHG_I64_A32\000"
4383 /* 1482 */ "ATOMIC_RMW32_U_XCHG_I64_A32\000"
4384 /* 1510 */ "ATOMIC_RMW16_U_XCHG_I64_A32\000"
4385 /* 1538 */ "ATOMIC_RMW8_U_XCHG_I64_A32\000"
4386 /* 1565 */ "ATOMIC_RMW_XCHG_I64_A32\000"
4387 /* 1589 */ "ATOMIC_RMW32_U_XOR_I64_A32\000"
4388 /* 1616 */ "ATOMIC_RMW16_U_XOR_I64_A32\000"
4389 /* 1643 */ "ATOMIC_RMW8_U_XOR_I64_A32\000"
4390 /* 1669 */ "ATOMIC_RMW_XOR_I64_A32\000"
4391 /* 1692 */ "ATOMIC_RMW32_U_OR_I64_A32\000"
4392 /* 1718 */ "ATOMIC_RMW16_U_OR_I64_A32\000"
4393 /* 1744 */ "ATOMIC_RMW8_U_OR_I64_A32\000"
4394 /* 1769 */ "ATOMIC_RMW_OR_I64_A32\000"
4395 /* 1791 */ "LOAD32_S_I64_A32\000"
4396 /* 1808 */ "LOAD16_S_I64_A32\000"
4397 /* 1825 */ "LOAD8_S_I64_A32\000"
4398 /* 1841 */ "ATOMIC_LOAD32_U_I64_A32\000"
4399 /* 1865 */ "ATOMIC_LOAD16_U_I64_A32\000"
4400 /* 1889 */ "ATOMIC_LOAD8_U_I64_A32\000"
4401 /* 1912 */ "MEMORY_ATOMIC_WAIT64_A32\000"
4402 /* 1937 */ "LOAD_LANE_64_A32\000"
4403 /* 1954 */ "LOAD_ZERO_64_A32\000"
4404 /* 1971 */ "STORE_LANE_I32x4_A32\000"
4405 /* 1992 */ "LOAD_EXTEND_S_I32x4_A32\000"
4406 /* 2016 */ "LOAD_EXTEND_U_I32x4_A32\000"
4407 /* 2040 */ "LOAD_LANE_16_A32\000"
4408 /* 2057 */ "STORE_LANE_I8x16_A32\000"
4409 /* 2078 */ "LOAD_V128_A32\000"
4410 /* 2092 */ "STORE_V128_A32\000"
4411 /* 2107 */ "LOAD_LANE_8_A32\000"
4412 /* 2123 */ "STORE_LANE_I16x8_A32\000"
4413 /* 2144 */ "LOAD_EXTEND_S_I16x8_A32\000"
4414 /* 2168 */ "LOAD_EXTEND_U_I16x8_A32\000"
4415 /* 2192 */ "anonymous_14422MEMORY_SIZE_A32\000"
4416 /* 2223 */ "MEMORY_FILL_A32\000"
4417 /* 2239 */ "LOAD32_SPLAT_A32\000"
4418 /* 2256 */ "LOAD64_SPLAT_A32\000"
4419 /* 2273 */ "LOAD16_SPLAT_A32\000"
4420 /* 2290 */ "LOAD8_SPLAT_A32\000"
4421 /* 2306 */ "MEMSET_A32\000"
4422 /* 2317 */ "MEMORY_INIT_A32\000"
4423 /* 2333 */ "anonymous_14422MEMORY_GROW_A32\000"
4424 /* 2364 */ "MEMORY_ATOMIC_NOTIFY_A32\000"
4425 /* 2389 */ "MEMCPY_A32\000"
4426 /* 2400 */ "MEMORY_COPY_A32\000"
4427 /* 2416 */ "FP_TO_SINT_I32_F32\000"
4428 /* 2435 */ "FP_TO_UINT_I32_F32\000"
4429 /* 2454 */ "FP_TO_SINT_I64_F32\000"
4430 /* 2473 */ "FP_TO_UINT_I64_F32\000"
4431 /* 2492 */ "SUB_F32\000"
4432 /* 2500 */ "TRUNC_F32\000"
4433 /* 2510 */ "ADD_F32\000"
4434 /* 2518 */ "LOCAL_TEE_F32\000"
4435 /* 2532 */ "GE_F32\000"
4436 /* 2539 */ "LE_F32\000"
4437 /* 2546 */ "NE_F32\000"
4438 /* 2553 */ "F64_PROMOTE_F32\000"
4439 /* 2569 */ "NEG_F32\000"
4440 /* 2577 */ "CEIL_F32\000"
4441 /* 2586 */ "MUL_F32\000"
4442 /* 2594 */ "COPYSIGN_F32\000"
4443 /* 2607 */ "MIN_F32\000"
4444 /* 2615 */ "DROP_F32\000"
4445 /* 2624 */ "EQ_F32\000"
4446 /* 2631 */ "FLOOR_F32\000"
4447 /* 2641 */ "ABS_F32\000"
4448 /* 2649 */ "I32_TRUNC_S_F32\000"
4449 /* 2665 */ "I64_TRUNC_S_F32\000"
4450 /* 2681 */ "I32_TRUNC_S_SAT_F32\000"
4451 /* 2701 */ "I64_TRUNC_S_SAT_F32\000"
4452 /* 2721 */ "I32_TRUNC_U_SAT_F32\000"
4453 /* 2741 */ "I64_TRUNC_U_SAT_F32\000"
4454 /* 2761 */ "SELECT_F32\000"
4455 /* 2772 */ "GLOBAL_GET_F32\000"
4456 /* 2787 */ "LOCAL_GET_F32\000"
4457 /* 2801 */ "I32_REINTERPRET_F32\000"
4458 /* 2821 */ "GLOBAL_SET_F32\000"
4459 /* 2836 */ "LOCAL_SET_F32\000"
4460 /* 2850 */ "GT_F32\000"
4461 /* 2857 */ "LT_F32\000"
4462 /* 2864 */ "SQRT_F32\000"
4463 /* 2873 */ "NEAREST_F32\000"
4464 /* 2885 */ "CONST_F32\000"
4465 /* 2895 */ "I32_TRUNC_U_F32\000"
4466 /* 2911 */ "I64_TRUNC_U_F32\000"
4467 /* 2927 */ "DIV_F32\000"
4468 /* 2935 */ "MAX_F32\000"
4469 /* 2943 */ "COPY_F32\000"
4470 /* 2952 */ "SUB_I32\000"
4471 /* 2960 */ "ADD_I32\000"
4472 /* 2968 */ "AND_I32\000"
4473 /* 2976 */ "LOCAL_TEE_I32\000"
4474 /* 2990 */ "BR_TABLE_I32\000"
4475 /* 3003 */ "NE_I32\000"
4476 /* 3010 */ "SHL_I32\000"
4477 /* 3018 */ "ROTL_I32\000"
4478 /* 3027 */ "MUL_I32\000"
4479 /* 3035 */ "DROP_I32\000"
4480 /* 3044 */ "EQ_I32\000"
4481 /* 3051 */ "XOR_I32\000"
4482 /* 3059 */ "ROTR_I32\000"
4483 /* 3068 */ "I32_EXTEND16_S_I32\000"
4484 /* 3087 */ "I32_EXTEND8_S_I32\000"
4485 /* 3105 */ "I64_EXTEND_S_I32\000"
4486 /* 3122 */ "GE_S_I32\000"
4487 /* 3131 */ "LE_S_I32\000"
4488 /* 3140 */ "REM_S_I32\000"
4489 /* 3150 */ "SHR_S_I32\000"
4490 /* 3160 */ "GT_S_I32\000"
4491 /* 3169 */ "LT_S_I32\000"
4492 /* 3178 */ "F32_CONVERT_S_I32\000"
4493 /* 3196 */ "F64_CONVERT_S_I32\000"
4494 /* 3214 */ "DIV_S_I32\000"
4495 /* 3224 */ "SELECT_I32\000"
4496 /* 3235 */ "GLOBAL_GET_I32\000"
4497 /* 3250 */ "LOCAL_GET_I32\000"
4498 /* 3264 */ "F32_REINTERPRET_I32\000"
4499 /* 3284 */ "GLOBAL_SET_I32\000"
4500 /* 3299 */ "LOCAL_SET_I32\000"
4501 /* 3313 */ "POPCNT_I32\000"
4502 /* 3324 */ "CONST_I32\000"
4503 /* 3334 */ "I64_EXTEND_U_I32\000"
4504 /* 3351 */ "GE_U_I32\000"
4505 /* 3360 */ "LE_U_I32\000"
4506 /* 3369 */ "REM_U_I32\000"
4507 /* 3379 */ "SHR_U_I32\000"
4508 /* 3389 */ "GT_U_I32\000"
4509 /* 3398 */ "LT_U_I32\000"
4510 /* 3407 */ "F32_CONVERT_U_I32\000"
4511 /* 3425 */ "F64_CONVERT_U_I32\000"
4512 /* 3443 */ "DIV_U_I32\000"
4513 /* 3453 */ "COPY_I32\000"
4514 /* 3462 */ "CLZ_I32\000"
4515 /* 3470 */ "EQZ_I32\000"
4516 /* 3478 */ "CTZ_I32\000"
4517 /* 3486 */ "ARGUMENT_v4f32\000"
4518 /* 3501 */ "ARGUMENT_f32\000"
4519 /* 3514 */ "ARGUMENT_v4i32\000"
4520 /* 3529 */ "ARGUMENT_i32\000"
4521 /* 3542 */ "G_FLOG2\000"
4522 /* 3550 */ "G_FATAN2\000"
4523 /* 3559 */ "G_FEXP2\000"
4524 /* 3567 */ "CONST_V128_F64x2\000"
4525 /* 3584 */ "SUB_F64x2\000"
4526 /* 3594 */ "TRUNC_F64x2\000"
4527 /* 3606 */ "NMADD_F64x2\000"
4528 /* 3618 */ "GE_F64x2\000"
4529 /* 3627 */ "LE_F64x2\000"
4530 /* 3636 */ "REPLACE_LANE_F64x2\000"
4531 /* 3655 */ "EXTRACT_LANE_F64x2\000"
4532 /* 3674 */ "NEG_F64x2\000"
4533 /* 3684 */ "CEIL_F64x2\000"
4534 /* 3695 */ "MUL_F64x2\000"
4535 /* 3705 */ "SIMD_RELAXED_FMIN_F64x2\000"
4536 /* 3729 */ "PMIN_F64x2\000"
4537 /* 3740 */ "EQ_F64x2\000"
4538 /* 3749 */ "FLOOR_F64x2\000"
4539 /* 3761 */ "ABS_F64x2\000"
4540 /* 3771 */ "SPLAT_F64x2\000"
4541 /* 3783 */ "GT_F64x2\000"
4542 /* 3792 */ "LT_F64x2\000"
4543 /* 3801 */ "SQRT_F64x2\000"
4544 /* 3812 */ "NEAREST_F64x2\000"
4545 /* 3826 */ "DIV_F64x2\000"
4546 /* 3836 */ "SIMD_RELAXED_FMAX_F64x2\000"
4547 /* 3860 */ "PMAX_F64x2\000"
4548 /* 3871 */ "convert_low_s_F64x2\000"
4549 /* 3891 */ "convert_low_u_F64x2\000"
4550 /* 3911 */ "promote_low_F64x2\000"
4551 /* 3929 */ "CONST_V128_I64x2\000"
4552 /* 3946 */ "SUB_I64x2\000"
4553 /* 3956 */ "ADD_I64x2\000"
4554 /* 3966 */ "REPLACE_LANE_I64x2\000"
4555 /* 3985 */ "EXTRACT_LANE_I64x2\000"
4556 /* 4004 */ "ALLTRUE_I64x2\000"
4557 /* 4018 */ "NEG_I64x2\000"
4558 /* 4028 */ "BITMASK_I64x2\000"
4559 /* 4042 */ "SHL_I64x2\000"
4560 /* 4052 */ "MUL_I64x2\000"
4561 /* 4062 */ "EQ_I64x2\000"
4562 /* 4071 */ "ABS_I64x2\000"
4563 /* 4081 */ "GE_S_I64x2\000"
4564 /* 4092 */ "LE_S_I64x2\000"
4565 /* 4103 */ "EXTMUL_HIGH_S_I64x2\000"
4566 /* 4123 */ "SHR_S_I64x2\000"
4567 /* 4135 */ "GT_S_I64x2\000"
4568 /* 4146 */ "LT_S_I64x2\000"
4569 /* 4157 */ "EXTMUL_LOW_S_I64x2\000"
4570 /* 4176 */ "SPLAT_I64x2\000"
4571 /* 4188 */ "LANESELECT_I64x2\000"
4572 /* 4205 */ "EXTMUL_HIGH_U_I64x2\000"
4573 /* 4225 */ "SHR_U_I64x2\000"
4574 /* 4237 */ "EXTMUL_LOW_U_I64x2\000"
4575 /* 4256 */ "extend_high_s_I64x2\000"
4576 /* 4276 */ "extend_low_s_I64x2\000"
4577 /* 4295 */ "extend_high_u_I64x2\000"
4578 /* 4315 */ "extend_low_u_I64x2\000"
4579 /* 4334 */ "LOAD_F16_F32_A64\000"
4580 /* 4351 */ "STORE_F16_F32_A64\000"
4581 /* 4369 */ "LOAD_F32_A64\000"
4582 /* 4382 */ "STORE_F32_A64\000"
4583 /* 4396 */ "ATOMIC_STORE16_I32_A64\000"
4584 /* 4419 */ "ATOMIC_STORE8_I32_A64\000"
4585 /* 4441 */ "ATOMIC_RMW16_U_SUB_I32_A64\000"
4586 /* 4468 */ "ATOMIC_RMW8_U_SUB_I32_A64\000"
4587 /* 4494 */ "ATOMIC_RMW_SUB_I32_A64\000"
4588 /* 4517 */ "ATOMIC_LOAD_I32_A64\000"
4589 /* 4537 */ "ATOMIC_RMW16_U_ADD_I32_A64\000"
4590 /* 4564 */ "ATOMIC_RMW8_U_ADD_I32_A64\000"
4591 /* 4590 */ "ATOMIC_RMW_ADD_I32_A64\000"
4592 /* 4613 */ "ATOMIC_RMW16_U_AND_I32_A64\000"
4593 /* 4640 */ "ATOMIC_RMW8_U_AND_I32_A64\000"
4594 /* 4666 */ "ATOMIC_RMW_AND_I32_A64\000"
4595 /* 4689 */ "ATOMIC_STORE_I32_A64\000"
4596 /* 4710 */ "ATOMIC_RMW16_U_CMPXCHG_I32_A64\000"
4597 /* 4741 */ "ATOMIC_RMW8_U_CMPXCHG_I32_A64\000"
4598 /* 4771 */ "ATOMIC_RMW_CMPXCHG_I32_A64\000"
4599 /* 4798 */ "ATOMIC_RMW16_U_XCHG_I32_A64\000"
4600 /* 4826 */ "ATOMIC_RMW8_U_XCHG_I32_A64\000"
4601 /* 4853 */ "ATOMIC_RMW_XCHG_I32_A64\000"
4602 /* 4877 */ "ATOMIC_RMW16_U_XOR_I32_A64\000"
4603 /* 4904 */ "ATOMIC_RMW8_U_XOR_I32_A64\000"
4604 /* 4930 */ "ATOMIC_RMW_XOR_I32_A64\000"
4605 /* 4953 */ "ATOMIC_RMW16_U_OR_I32_A64\000"
4606 /* 4979 */ "ATOMIC_RMW8_U_OR_I32_A64\000"
4607 /* 5004 */ "ATOMIC_RMW_OR_I32_A64\000"
4608 /* 5026 */ "LOAD16_S_I32_A64\000"
4609 /* 5043 */ "LOAD8_S_I32_A64\000"
4610 /* 5059 */ "ATOMIC_LOAD16_U_I32_A64\000"
4611 /* 5083 */ "ATOMIC_LOAD8_U_I32_A64\000"
4612 /* 5106 */ "MEMORY_ATOMIC_WAIT32_A64\000"
4613 /* 5131 */ "LOAD_LANE_32_A64\000"
4614 /* 5148 */ "LOAD_ZERO_32_A64\000"
4615 /* 5165 */ "STORE_LANE_I64x2_A64\000"
4616 /* 5186 */ "LOAD_EXTEND_S_I64x2_A64\000"
4617 /* 5210 */ "LOAD_EXTEND_U_I64x2_A64\000"
4618 /* 5234 */ "LOAD_F64_A64\000"
4619 /* 5247 */ "STORE_F64_A64\000"
4620 /* 5261 */ "ATOMIC_STORE32_I64_A64\000"
4621 /* 5284 */ "ATOMIC_STORE16_I64_A64\000"
4622 /* 5307 */ "ATOMIC_STORE8_I64_A64\000"
4623 /* 5329 */ "ATOMIC_RMW32_U_SUB_I64_A64\000"
4624 /* 5356 */ "ATOMIC_RMW16_U_SUB_I64_A64\000"
4625 /* 5383 */ "ATOMIC_RMW8_U_SUB_I64_A64\000"
4626 /* 5409 */ "ATOMIC_RMW_SUB_I64_A64\000"
4627 /* 5432 */ "ATOMIC_LOAD_I64_A64\000"
4628 /* 5452 */ "ATOMIC_RMW32_U_ADD_I64_A64\000"
4629 /* 5479 */ "ATOMIC_RMW16_U_ADD_I64_A64\000"
4630 /* 5506 */ "ATOMIC_RMW8_U_ADD_I64_A64\000"
4631 /* 5532 */ "ATOMIC_RMW_ADD_I64_A64\000"
4632 /* 5555 */ "ATOMIC_RMW32_U_AND_I64_A64\000"
4633 /* 5582 */ "ATOMIC_RMW16_U_AND_I64_A64\000"
4634 /* 5609 */ "ATOMIC_RMW8_U_AND_I64_A64\000"
4635 /* 5635 */ "ATOMIC_RMW_AND_I64_A64\000"
4636 /* 5658 */ "ATOMIC_STORE_I64_A64\000"
4637 /* 5679 */ "ATOMIC_RMW32_U_CMPXCHG_I64_A64\000"
4638 /* 5710 */ "ATOMIC_RMW16_U_CMPXCHG_I64_A64\000"
4639 /* 5741 */ "ATOMIC_RMW8_U_CMPXCHG_I64_A64\000"
4640 /* 5771 */ "ATOMIC_RMW_CMPXCHG_I64_A64\000"
4641 /* 5798 */ "ATOMIC_RMW32_U_XCHG_I64_A64\000"
4642 /* 5826 */ "ATOMIC_RMW16_U_XCHG_I64_A64\000"
4643 /* 5854 */ "ATOMIC_RMW8_U_XCHG_I64_A64\000"
4644 /* 5881 */ "ATOMIC_RMW_XCHG_I64_A64\000"
4645 /* 5905 */ "ATOMIC_RMW32_U_XOR_I64_A64\000"
4646 /* 5932 */ "ATOMIC_RMW16_U_XOR_I64_A64\000"
4647 /* 5959 */ "ATOMIC_RMW8_U_XOR_I64_A64\000"
4648 /* 5985 */ "ATOMIC_RMW_XOR_I64_A64\000"
4649 /* 6008 */ "ATOMIC_RMW32_U_OR_I64_A64\000"
4650 /* 6034 */ "ATOMIC_RMW16_U_OR_I64_A64\000"
4651 /* 6060 */ "ATOMIC_RMW8_U_OR_I64_A64\000"
4652 /* 6085 */ "ATOMIC_RMW_OR_I64_A64\000"
4653 /* 6107 */ "LOAD32_S_I64_A64\000"
4654 /* 6124 */ "LOAD16_S_I64_A64\000"
4655 /* 6141 */ "LOAD8_S_I64_A64\000"
4656 /* 6157 */ "ATOMIC_LOAD32_U_I64_A64\000"
4657 /* 6181 */ "ATOMIC_LOAD16_U_I64_A64\000"
4658 /* 6205 */ "ATOMIC_LOAD8_U_I64_A64\000"
4659 /* 6228 */ "MEMORY_ATOMIC_WAIT64_A64\000"
4660 /* 6253 */ "LOAD_LANE_64_A64\000"
4661 /* 6270 */ "LOAD_ZERO_64_A64\000"
4662 /* 6287 */ "STORE_LANE_I32x4_A64\000"
4663 /* 6308 */ "LOAD_EXTEND_S_I32x4_A64\000"
4664 /* 6332 */ "LOAD_EXTEND_U_I32x4_A64\000"
4665 /* 6356 */ "LOAD_LANE_16_A64\000"
4666 /* 6373 */ "STORE_LANE_I8x16_A64\000"
4667 /* 6394 */ "LOAD_V128_A64\000"
4668 /* 6408 */ "STORE_V128_A64\000"
4669 /* 6423 */ "LOAD_LANE_8_A64\000"
4670 /* 6439 */ "STORE_LANE_I16x8_A64\000"
4671 /* 6460 */ "LOAD_EXTEND_S_I16x8_A64\000"
4672 /* 6484 */ "LOAD_EXTEND_U_I16x8_A64\000"
4673 /* 6508 */ "anonymous_14423MEMORY_SIZE_A64\000"
4674 /* 6539 */ "MEMORY_FILL_A64\000"
4675 /* 6555 */ "LOAD32_SPLAT_A64\000"
4676 /* 6572 */ "LOAD64_SPLAT_A64\000"
4677 /* 6589 */ "LOAD16_SPLAT_A64\000"
4678 /* 6606 */ "LOAD8_SPLAT_A64\000"
4679 /* 6622 */ "MEMSET_A64\000"
4680 /* 6633 */ "MEMORY_INIT_A64\000"
4681 /* 6649 */ "anonymous_14423MEMORY_GROW_A64\000"
4682 /* 6680 */ "MEMORY_ATOMIC_NOTIFY_A64\000"
4683 /* 6705 */ "MEMCPY_A64\000"
4684 /* 6716 */ "MEMORY_COPY_A64\000"
4685 /* 6732 */ "FP_TO_SINT_I32_F64\000"
4686 /* 6751 */ "FP_TO_UINT_I32_F64\000"
4687 /* 6770 */ "FP_TO_SINT_I64_F64\000"
4688 /* 6789 */ "FP_TO_UINT_I64_F64\000"
4689 /* 6808 */ "SUB_F64\000"
4690 /* 6816 */ "TRUNC_F64\000"
4691 /* 6826 */ "ADD_F64\000"
4692 /* 6834 */ "LOCAL_TEE_F64\000"
4693 /* 6848 */ "GE_F64\000"
4694 /* 6855 */ "LE_F64\000"
4695 /* 6862 */ "NE_F64\000"
4696 /* 6869 */ "F32_DEMOTE_F64\000"
4697 /* 6884 */ "NEG_F64\000"
4698 /* 6892 */ "CEIL_F64\000"
4699 /* 6901 */ "MUL_F64\000"
4700 /* 6909 */ "COPYSIGN_F64\000"
4701 /* 6922 */ "MIN_F64\000"
4702 /* 6930 */ "DROP_F64\000"
4703 /* 6939 */ "EQ_F64\000"
4704 /* 6946 */ "FLOOR_F64\000"
4705 /* 6956 */ "ABS_F64\000"
4706 /* 6964 */ "I32_TRUNC_S_F64\000"
4707 /* 6980 */ "I64_TRUNC_S_F64\000"
4708 /* 6996 */ "I32_TRUNC_S_SAT_F64\000"
4709 /* 7016 */ "I64_TRUNC_S_SAT_F64\000"
4710 /* 7036 */ "I32_TRUNC_U_SAT_F64\000"
4711 /* 7056 */ "I64_TRUNC_U_SAT_F64\000"
4712 /* 7076 */ "SELECT_F64\000"
4713 /* 7087 */ "GLOBAL_GET_F64\000"
4714 /* 7102 */ "LOCAL_GET_F64\000"
4715 /* 7116 */ "I64_REINTERPRET_F64\000"
4716 /* 7136 */ "GLOBAL_SET_F64\000"
4717 /* 7151 */ "LOCAL_SET_F64\000"
4718 /* 7165 */ "GT_F64\000"
4719 /* 7172 */ "LT_F64\000"
4720 /* 7179 */ "SQRT_F64\000"
4721 /* 7188 */ "NEAREST_F64\000"
4722 /* 7200 */ "CONST_F64\000"
4723 /* 7210 */ "I32_TRUNC_U_F64\000"
4724 /* 7226 */ "I64_TRUNC_U_F64\000"
4725 /* 7242 */ "DIV_F64\000"
4726 /* 7250 */ "MAX_F64\000"
4727 /* 7258 */ "COPY_F64\000"
4728 /* 7267 */ "SUB_I64\000"
4729 /* 7275 */ "ADD_I64\000"
4730 /* 7283 */ "AND_I64\000"
4731 /* 7291 */ "LOCAL_TEE_I64\000"
4732 /* 7305 */ "BR_TABLE_I64\000"
4733 /* 7318 */ "NE_I64\000"
4734 /* 7325 */ "SHL_I64\000"
4735 /* 7333 */ "ROTL_I64\000"
4736 /* 7342 */ "MUL_I64\000"
4737 /* 7350 */ "I32_WRAP_I64\000"
4738 /* 7363 */ "DROP_I64\000"
4739 /* 7372 */ "EQ_I64\000"
4740 /* 7379 */ "XOR_I64\000"
4741 /* 7387 */ "ROTR_I64\000"
4742 /* 7396 */ "I64_EXTEND32_S_I64\000"
4743 /* 7415 */ "I64_EXTEND16_S_I64\000"
4744 /* 7434 */ "I64_EXTEND8_S_I64\000"
4745 /* 7452 */ "GE_S_I64\000"
4746 /* 7461 */ "LE_S_I64\000"
4747 /* 7470 */ "REM_S_I64\000"
4748 /* 7480 */ "SHR_S_I64\000"
4749 /* 7490 */ "GT_S_I64\000"
4750 /* 7499 */ "LT_S_I64\000"
4751 /* 7508 */ "F32_CONVERT_S_I64\000"
4752 /* 7526 */ "F64_CONVERT_S_I64\000"
4753 /* 7544 */ "DIV_S_I64\000"
4754 /* 7554 */ "SELECT_I64\000"
4755 /* 7565 */ "GLOBAL_GET_I64\000"
4756 /* 7580 */ "LOCAL_GET_I64\000"
4757 /* 7594 */ "F64_REINTERPRET_I64\000"
4758 /* 7614 */ "GLOBAL_SET_I64\000"
4759 /* 7629 */ "LOCAL_SET_I64\000"
4760 /* 7643 */ "POPCNT_I64\000"
4761 /* 7654 */ "CONST_I64\000"
4762 /* 7664 */ "GE_U_I64\000"
4763 /* 7673 */ "LE_U_I64\000"
4764 /* 7682 */ "REM_U_I64\000"
4765 /* 7692 */ "SHR_U_I64\000"
4766 /* 7702 */ "GT_U_I64\000"
4767 /* 7711 */ "LT_U_I64\000"
4768 /* 7720 */ "F32_CONVERT_U_I64\000"
4769 /* 7738 */ "F64_CONVERT_U_I64\000"
4770 /* 7756 */ "DIV_U_I64\000"
4771 /* 7766 */ "COPY_I64\000"
4772 /* 7775 */ "CLZ_I64\000"
4773 /* 7783 */ "EQZ_I64\000"
4774 /* 7791 */ "CTZ_I64\000"
4775 /* 7799 */ "ARGUMENT_v2f64\000"
4776 /* 7814 */ "ARGUMENT_f64\000"
4777 /* 7827 */ "ARGUMENT_v2i64\000"
4778 /* 7842 */ "ARGUMENT_i64\000"
4779 /* 7855 */ "CONST_V128_F32x4\000"
4780 /* 7872 */ "SUB_F32x4\000"
4781 /* 7882 */ "TRUNC_F32x4\000"
4782 /* 7894 */ "NMADD_F32x4\000"
4783 /* 7906 */ "GE_F32x4\000"
4784 /* 7915 */ "LE_F32x4\000"
4785 /* 7924 */ "REPLACE_LANE_F32x4\000"
4786 /* 7943 */ "EXTRACT_LANE_F32x4\000"
4787 /* 7962 */ "NEG_F32x4\000"
4788 /* 7972 */ "CEIL_F32x4\000"
4789 /* 7983 */ "MUL_F32x4\000"
4790 /* 7993 */ "SIMD_RELAXED_FMIN_F32x4\000"
4791 /* 8017 */ "PMIN_F32x4\000"
4792 /* 8028 */ "EQ_F32x4\000"
4793 /* 8037 */ "FLOOR_F32x4\000"
4794 /* 8049 */ "ABS_F32x4\000"
4795 /* 8059 */ "SPLAT_F32x4\000"
4796 /* 8071 */ "GT_F32x4\000"
4797 /* 8080 */ "LT_F32x4\000"
4798 /* 8089 */ "SQRT_F32x4\000"
4799 /* 8100 */ "NEAREST_F32x4\000"
4800 /* 8114 */ "DIV_F32x4\000"
4801 /* 8124 */ "SIMD_RELAXED_FMAX_F32x4\000"
4802 /* 8148 */ "PMAX_F32x4\000"
4803 /* 8159 */ "demote_zero_F32x4\000"
4804 /* 8177 */ "sint_to_fp_F32x4\000"
4805 /* 8194 */ "uint_to_fp_F32x4\000"
4806 /* 8211 */ "promote_low_F32x4\000"
4807 /* 8229 */ "CONST_V128_I32x4\000"
4808 /* 8246 */ "SUB_I32x4\000"
4809 /* 8256 */ "ADD_I32x4\000"
4810 /* 8266 */ "REPLACE_LANE_I32x4\000"
4811 /* 8285 */ "EXTRACT_LANE_I32x4\000"
4812 /* 8304 */ "ALLTRUE_I32x4\000"
4813 /* 8318 */ "NEG_I32x4\000"
4814 /* 8328 */ "BITMASK_I32x4\000"
4815 /* 8342 */ "SHL_I32x4\000"
4816 /* 8352 */ "MUL_I32x4\000"
4817 /* 8362 */ "EQ_I32x4\000"
4818 /* 8371 */ "ABS_I32x4\000"
4819 /* 8381 */ "GE_S_I32x4\000"
4820 /* 8392 */ "LE_S_I32x4\000"
4821 /* 8403 */ "EXTMUL_HIGH_S_I32x4\000"
4822 /* 8423 */ "MIN_S_I32x4\000"
4823 /* 8435 */ "SHR_S_I32x4\000"
4824 /* 8447 */ "GT_S_I32x4\000"
4825 /* 8458 */ "LT_S_I32x4\000"
4826 /* 8469 */ "EXTMUL_LOW_S_I32x4\000"
4827 /* 8488 */ "MAX_S_I32x4\000"
4828 /* 8500 */ "SPLAT_I32x4\000"
4829 /* 8512 */ "LANESELECT_I32x4\000"
4830 /* 8529 */ "GE_U_I32x4\000"
4831 /* 8540 */ "LE_U_I32x4\000"
4832 /* 8551 */ "EXTMUL_HIGH_U_I32x4\000"
4833 /* 8571 */ "MIN_U_I32x4\000"
4834 /* 8583 */ "SHR_U_I32x4\000"
4835 /* 8595 */ "GT_U_I32x4\000"
4836 /* 8606 */ "LT_U_I32x4\000"
4837 /* 8617 */ "EXTMUL_LOW_U_I32x4\000"
4838 /* 8636 */ "MAX_U_I32x4\000"
4839 /* 8648 */ "int_wasm_relaxed_trunc_signed_I32x4\000"
4840 /* 8684 */ "int_wasm_relaxed_trunc_unsigned_I32x4\000"
4841 /* 8722 */ "int_wasm_relaxed_trunc_signed_zero_I32x4\000"
4842 /* 8763 */ "int_wasm_relaxed_trunc_unsigned_zero_I32x4\000"
4843 /* 8806 */ "extadd_pairwise_s_I32x4\000"
4844 /* 8830 */ "extend_high_s_I32x4\000"
4845 /* 8850 */ "trunc_sat_zero_s_I32x4\000"
4846 /* 8873 */ "extend_low_s_I32x4\000"
4847 /* 8892 */ "fp_to_sint_I32x4\000"
4848 /* 8909 */ "fp_to_uint_I32x4\000"
4849 /* 8926 */ "extadd_pairwise_u_I32x4\000"
4850 /* 8950 */ "extend_high_u_I32x4\000"
4851 /* 8970 */ "trunc_sat_zero_u_I32x4\000"
4852 /* 8993 */ "extend_low_u_I32x4\000"
4853 /* 9012 */ "ARGUMENT_v8f16\000"
4854 /* 9027 */ "ARGUMENT_v8i16\000"
4855 /* 9042 */ "CONST_V128_I8x16\000"
4856 /* 9059 */ "SUB_I8x16\000"
4857 /* 9069 */ "ADD_I8x16\000"
4858 /* 9079 */ "REPLACE_LANE_I8x16\000"
4859 /* 9098 */ "ALLTRUE_I8x16\000"
4860 /* 9112 */ "NEG_I8x16\000"
4861 /* 9122 */ "BITMASK_I8x16\000"
4862 /* 9136 */ "SHL_I8x16\000"
4863 /* 9146 */ "EQ_I8x16\000"
4864 /* 9155 */ "ABS_I8x16\000"
4865 /* 9165 */ "GE_S_I8x16\000"
4866 /* 9176 */ "LE_S_I8x16\000"
4867 /* 9187 */ "MIN_S_I8x16\000"
4868 /* 9199 */ "SHR_S_I8x16\000"
4869 /* 9211 */ "SUB_SAT_S_I8x16\000"
4870 /* 9227 */ "ADD_SAT_S_I8x16\000"
4871 /* 9243 */ "GT_S_I8x16\000"
4872 /* 9254 */ "LT_S_I8x16\000"
4873 /* 9265 */ "NARROW_S_I8x16\000"
4874 /* 9280 */ "MAX_S_I8x16\000"
4875 /* 9292 */ "SPLAT_I8x16\000"
4876 /* 9304 */ "LANESELECT_I8x16\000"
4877 /* 9321 */ "POPCNT_I8x16\000"
4878 /* 9334 */ "GE_U_I8x16\000"
4879 /* 9345 */ "LE_U_I8x16\000"
4880 /* 9356 */ "MIN_U_I8x16\000"
4881 /* 9368 */ "AVGR_U_I8x16\000"
4882 /* 9381 */ "SHR_U_I8x16\000"
4883 /* 9393 */ "SUB_SAT_U_I8x16\000"
4884 /* 9409 */ "ADD_SAT_U_I8x16\000"
4885 /* 9425 */ "GT_U_I8x16\000"
4886 /* 9436 */ "LT_U_I8x16\000"
4887 /* 9447 */ "NARROW_U_I8x16\000"
4888 /* 9462 */ "MAX_U_I8x16\000"
4889 /* 9474 */ "I64_SUB128\000"
4890 /* 9485 */ "I64_ADD128\000"
4891 /* 9496 */ "LOCAL_TEE_V128\000"
4892 /* 9511 */ "DROP_V128\000"
4893 /* 9521 */ "SELECT_V128\000"
4894 /* 9533 */ "GLOBAL_GET_V128\000"
4895 /* 9549 */ "LOCAL_GET_V128\000"
4896 /* 9564 */ "GLOBAL_SET_V128\000"
4897 /* 9580 */ "LOCAL_SET_V128\000"
4898 /* 9595 */ "COPY_V128\000"
4899 /* 9605 */ "ARGUMENT_v16i8\000"
4900 /* 9620 */ "SUB_F16x8\000"
4901 /* 9630 */ "TRUNC_F16x8\000"
4902 /* 9642 */ "NMADD_F16x8\000"
4903 /* 9654 */ "GE_F16x8\000"
4904 /* 9663 */ "LE_F16x8\000"
4905 /* 9672 */ "REPLACE_LANE_F16x8\000"
4906 /* 9691 */ "EXTRACT_LANE_F16x8\000"
4907 /* 9710 */ "NEG_F16x8\000"
4908 /* 9720 */ "CEIL_F16x8\000"
4909 /* 9731 */ "MUL_F16x8\000"
4910 /* 9741 */ "PMIN_F16x8\000"
4911 /* 9752 */ "EQ_F16x8\000"
4912 /* 9761 */ "FLOOR_F16x8\000"
4913 /* 9773 */ "ABS_F16x8\000"
4914 /* 9783 */ "SPLAT_F16x8\000"
4915 /* 9795 */ "GT_F16x8\000"
4916 /* 9804 */ "LT_F16x8\000"
4917 /* 9813 */ "SQRT_F16x8\000"
4918 /* 9824 */ "NEAREST_F16x8\000"
4919 /* 9838 */ "DIV_F16x8\000"
4920 /* 9848 */ "PMAX_F16x8\000"
4921 /* 9859 */ "demote_zero_F16x8\000"
4922 /* 9877 */ "sint_to_fp_F16x8\000"
4923 /* 9894 */ "uint_to_fp_F16x8\000"
4924 /* 9911 */ "CONST_V128_I16x8\000"
4925 /* 9928 */ "SUB_I16x8\000"
4926 /* 9938 */ "ADD_I16x8\000"
4927 /* 9948 */ "REPLACE_LANE_I16x8\000"
4928 /* 9967 */ "ALLTRUE_I16x8\000"
4929 /* 9981 */ "NEG_I16x8\000"
4930 /* 9991 */ "BITMASK_I16x8\000"
4931 /* 10005 */ "SHL_I16x8\000"
4932 /* 10015 */ "MUL_I16x8\000"
4933 /* 10025 */ "EQ_I16x8\000"
4934 /* 10034 */ "ABS_I16x8\000"
4935 /* 10044 */ "GE_S_I16x8\000"
4936 /* 10055 */ "LE_S_I16x8\000"
4937 /* 10066 */ "EXTMUL_HIGH_S_I16x8\000"
4938 /* 10086 */ "MIN_S_I16x8\000"
4939 /* 10098 */ "SHR_S_I16x8\000"
4940 /* 10110 */ "RELAXED_Q15MULR_S_I16x8\000"
4941 /* 10134 */ "SUB_SAT_S_I16x8\000"
4942 /* 10150 */ "ADD_SAT_S_I16x8\000"
4943 /* 10166 */ "Q15MULR_SAT_S_I16x8\000"
4944 /* 10186 */ "GT_S_I16x8\000"
4945 /* 10197 */ "LT_S_I16x8\000"
4946 /* 10208 */ "EXTMUL_LOW_S_I16x8\000"
4947 /* 10227 */ "NARROW_S_I16x8\000"
4948 /* 10242 */ "MAX_S_I16x8\000"
4949 /* 10254 */ "SPLAT_I16x8\000"
4950 /* 10266 */ "LANESELECT_I16x8\000"
4951 /* 10283 */ "GE_U_I16x8\000"
4952 /* 10294 */ "LE_U_I16x8\000"
4953 /* 10305 */ "EXTMUL_HIGH_U_I16x8\000"
4954 /* 10325 */ "MIN_U_I16x8\000"
4955 /* 10337 */ "AVGR_U_I16x8\000"
4956 /* 10350 */ "SHR_U_I16x8\000"
4957 /* 10362 */ "SUB_SAT_U_I16x8\000"
4958 /* 10378 */ "ADD_SAT_U_I16x8\000"
4959 /* 10394 */ "GT_U_I16x8\000"
4960 /* 10405 */ "LT_U_I16x8\000"
4961 /* 10416 */ "EXTMUL_LOW_U_I16x8\000"
4962 /* 10435 */ "NARROW_U_I16x8\000"
4963 /* 10450 */ "MAX_U_I16x8\000"
4964 /* 10462 */ "extadd_pairwise_s_I16x8\000"
4965 /* 10486 */ "extend_high_s_I16x8\000"
4966 /* 10506 */ "extend_low_s_I16x8\000"
4967 /* 10525 */ "fp_to_sint_I16x8\000"
4968 /* 10542 */ "fp_to_uint_I16x8\000"
4969 /* 10559 */ "extadd_pairwise_u_I16x8\000"
4970 /* 10583 */ "extend_high_u_I16x8\000"
4971 /* 10603 */ "extend_low_u_I16x8\000"
4972 /* 10622 */ "G_FMA\000"
4973 /* 10628 */ "G_STRICT_FMA\000"
4974 /* 10641 */ "G_FSUB\000"
4975 /* 10648 */ "G_STRICT_FSUB\000"
4976 /* 10662 */ "G_ATOMICRMW_FSUB\000"
4977 /* 10679 */ "G_SUB\000"
4978 /* 10685 */ "G_ATOMICRMW_SUB\000"
4979 /* 10701 */ "G_INTRINSIC\000"
4980 /* 10713 */ "REF_FUNC\000"
4981 /* 10722 */ "G_FPTRUNC\000"
4982 /* 10732 */ "G_INTRINSIC_TRUNC\000"
4983 /* 10750 */ "G_TRUNC\000"
4984 /* 10758 */ "G_BUILD_VECTOR_TRUNC\000"
4985 /* 10779 */ "G_DYN_STACKALLOC\000"
4986 /* 10796 */ "G_FMAD\000"
4987 /* 10803 */ "G_FPEXTLOAD\000"
4988 /* 10815 */ "G_INDEXED_SEXTLOAD\000"
4989 /* 10834 */ "G_SEXTLOAD\000"
4990 /* 10845 */ "G_INDEXED_ZEXTLOAD\000"
4991 /* 10864 */ "G_ZEXTLOAD\000"
4992 /* 10875 */ "G_INDEXED_LOAD\000"
4993 /* 10890 */ "G_LOAD\000"
4994 /* 10897 */ "G_VECREDUCE_FADD\000"
4995 /* 10914 */ "G_FADD\000"
4996 /* 10921 */ "G_VECREDUCE_SEQ_FADD\000"
4997 /* 10942 */ "G_STRICT_FADD\000"
4998 /* 10956 */ "G_ATOMICRMW_FADD\000"
4999 /* 10973 */ "G_VECREDUCE_ADD\000"
5000 /* 10989 */ "G_ADD\000"
5001 /* 10995 */ "G_PTR_ADD\000"
5002 /* 11005 */ "RELAXED_DOT_ADD\000"
5003 /* 11021 */ "G_ATOMICRMW_ADD\000"
5004 /* 11037 */ "G_ATOMICRMW_NAND\000"
5005 /* 11054 */ "G_VECREDUCE_AND\000"
5006 /* 11070 */ "G_AND\000"
5007 /* 11076 */ "G_ATOMICRMW_AND\000"
5008 /* 11092 */ "LIFETIME_END\000"
5009 /* 11105 */ "G_BRCOND\000"
5010 /* 11114 */ "G_ATOMICRMW_USUB_COND\000"
5011 /* 11136 */ "G_LLROUND\000"
5012 /* 11146 */ "G_LROUND\000"
5013 /* 11155 */ "G_INTRINSIC_ROUND\000"
5014 /* 11173 */ "G_INTRINSIC_FPTRUNC_ROUND\000"
5015 /* 11199 */ "LOAD_STACK_GUARD\000"
5016 /* 11216 */ "PSEUDO_PROBE\000"
5017 /* 11229 */ "G_SSUBE\000"
5018 /* 11237 */ "G_USUBE\000"
5019 /* 11245 */ "ATOMIC_FENCE\000"
5020 /* 11258 */ "G_FENCE\000"
5021 /* 11266 */ "ARITH_FENCE\000"
5022 /* 11278 */ "COMPILER_FENCE\000"
5023 /* 11293 */ "REG_SEQUENCE\000"
5024 /* 11306 */ "G_SADDE\000"
5025 /* 11314 */ "G_UADDE\000"
5026 /* 11322 */ "G_GET_FPMODE\000"
5027 /* 11335 */ "G_RESET_FPMODE\000"
5028 /* 11350 */ "G_SET_FPMODE\000"
5029 /* 11363 */ "G_FMINNUM_IEEE\000"
5030 /* 11378 */ "G_FMAXNUM_IEEE\000"
5031 /* 11393 */ "G_VSCALE\000"
5032 /* 11402 */ "DEBUG_UNREACHABLE\000"
5033 /* 11420 */ "G_JUMP_TABLE\000"
5034 /* 11433 */ "END_TRY_TABLE\000"
5035 /* 11447 */ "BUNDLE\000"
5036 /* 11454 */ "SHUFFLE\000"
5037 /* 11462 */ "RELAXED_SWIZZLE\000"
5038 /* 11478 */ "G_MEMSET_INLINE\000"
5039 /* 11494 */ "G_MEMCPY_INLINE\000"
5040 /* 11510 */ "RELOC_NONE\000"
5041 /* 11521 */ "LOCAL_ESCAPE\000"
5042 /* 11534 */ "G_FPTRUNCSTORE\000"
5043 /* 11549 */ "G_STACKRESTORE\000"
5044 /* 11564 */ "G_INDEXED_STORE\000"
5045 /* 11580 */ "G_STORE\000"
5046 /* 11588 */ "ELSE\000"
5047 /* 11593 */ "G_BITREVERSE\000"
5048 /* 11606 */ "FAKE_USE\000"
5049 /* 11615 */ "DELEGATE\000"
5050 /* 11624 */ "DBG_VALUE\000"
5051 /* 11634 */ "G_GLOBAL_VALUE\000"
5052 /* 11649 */ "G_PTRAUTH_GLOBAL_VALUE\000"
5053 /* 11672 */ "CONVERGENCECTRL_GLUE\000"
5054 /* 11693 */ "ANYTRUE\000"
5055 /* 11701 */ "G_STACKSAVE\000"
5056 /* 11713 */ "G_MEMMOVE\000"
5057 /* 11723 */ "G_FREEZE\000"
5058 /* 11732 */ "G_FCANONICALIZE\000"
5059 /* 11748 */ "TABLE_SIZE\000"
5060 /* 11759 */ "G_FMODF\000"
5061 /* 11767 */ "INIT_UNDEF\000"
5062 /* 11778 */ "G_IMPLICIT_DEF\000"
5063 /* 11793 */ "LOCAL_TEE_FUNCREF\000"
5064 /* 11811 */ "TABLE_FILL_FUNCREF\000"
5065 /* 11830 */ "REF_NULL_FUNCREF\000"
5066 /* 11847 */ "REF_IS_NULL_FUNCREF\000"
5067 /* 11867 */ "DROP_FUNCREF\000"
5068 /* 11880 */ "SELECT_FUNCREF\000"
5069 /* 11895 */ "TABLE_GET_FUNCREF\000"
5070 /* 11913 */ "GLOBAL_GET_FUNCREF\000"
5071 /* 11932 */ "LOCAL_GET_FUNCREF\000"
5072 /* 11950 */ "TABLE_SET_FUNCREF\000"
5073 /* 11968 */ "GLOBAL_SET_FUNCREF\000"
5074 /* 11987 */ "LOCAL_SET_FUNCREF\000"
5075 /* 12005 */ "REF_CAST_FUNCREF\000"
5076 /* 12022 */ "REF_TEST_FUNCREF\000"
5077 /* 12039 */ "TABLE_GROW_FUNCREF\000"
5078 /* 12058 */ "COPY_FUNCREF\000"
5079 /* 12071 */ "LOCAL_TEE_EXTERNREF\000"
5080 /* 12091 */ "TABLE_FILL_EXTERNREF\000"
5081 /* 12112 */ "REF_NULL_EXTERNREF\000"
5082 /* 12131 */ "REF_IS_NULL_EXTERNREF\000"
5083 /* 12153 */ "DROP_EXTERNREF\000"
5084 /* 12168 */ "SELECT_EXTERNREF\000"
5085 /* 12185 */ "TABLE_GET_EXTERNREF\000"
5086 /* 12205 */ "GLOBAL_GET_EXTERNREF\000"
5087 /* 12226 */ "LOCAL_GET_EXTERNREF\000"
5088 /* 12246 */ "TABLE_SET_EXTERNREF\000"
5089 /* 12266 */ "GLOBAL_SET_EXTERNREF\000"
5090 /* 12287 */ "LOCAL_SET_EXTERNREF\000"
5091 /* 12307 */ "TABLE_GROW_EXTERNREF\000"
5092 /* 12328 */ "COPY_EXTERNREF\000"
5093 /* 12343 */ "LOCAL_TEE_EXNREF\000"
5094 /* 12360 */ "TABLE_FILL_EXNREF\000"
5095 /* 12378 */ "REF_NULL_EXNREF\000"
5096 /* 12394 */ "REF_IS_NULL_EXNREF\000"
5097 /* 12413 */ "DROP_EXNREF\000"
5098 /* 12425 */ "SELECT_EXNREF\000"
5099 /* 12439 */ "TABLE_GET_EXNREF\000"
5100 /* 12456 */ "GLOBAL_GET_EXNREF\000"
5101 /* 12474 */ "LOCAL_GET_EXNREF\000"
5102 /* 12491 */ "TABLE_SET_EXNREF\000"
5103 /* 12508 */ "GLOBAL_SET_EXNREF\000"
5104 /* 12526 */ "LOCAL_SET_EXNREF\000"
5105 /* 12543 */ "TABLE_GROW_EXNREF\000"
5106 /* 12561 */ "COPY_EXNREF\000"
5107 /* 12573 */ "CATCH_REF\000"
5108 /* 12583 */ "RET_CALL_REF\000"
5109 /* 12596 */ "CATCH_ALL_REF\000"
5110 /* 12610 */ "DBG_INSTR_REF\000"
5111 /* 12624 */ "THROW_REF\000"
5112 /* 12634 */ "END_IF\000"
5113 /* 12641 */ "BR_IF\000"
5114 /* 12647 */ "G_FNEG\000"
5115 /* 12654 */ "EXTRACT_SUBREG\000"
5116 /* 12669 */ "INSERT_SUBREG\000"
5117 /* 12683 */ "G_SEXT_INREG\000"
5118 /* 12696 */ "SUBREG_TO_REG\000"
5119 /* 12710 */ "G_ATOMIC_CMPXCHG\000"
5120 /* 12727 */ "G_ATOMICRMW_XCHG\000"
5121 /* 12744 */ "G_GET_ROUNDING\000"
5122 /* 12759 */ "G_SET_ROUNDING\000"
5123 /* 12774 */ "G_FLOG\000"
5124 /* 12781 */ "G_VAARG\000"
5125 /* 12789 */ "PREALLOCATED_ARG\000"
5126 /* 12806 */ "CATCH\000"
5127 /* 12812 */ "G_PREFETCH\000"
5128 /* 12823 */ "G_SMULH\000"
5129 /* 12831 */ "G_UMULH\000"
5130 /* 12839 */ "G_FTANH\000"
5131 /* 12847 */ "G_FSINH\000"
5132 /* 12855 */ "G_FCOSH\000"
5133 /* 12863 */ "DBG_PHI\000"
5134 /* 12871 */ "G_FPTOSI\000"
5135 /* 12880 */ "G_FPTOUI\000"
5136 /* 12889 */ "G_FPOWI\000"
5137 /* 12897 */ "END_BLOCK\000"
5138 /* 12907 */ "COPY_LANEMASK\000"
5139 /* 12921 */ "G_PTRMASK\000"
5140 /* 12931 */ "GC_LABEL\000"
5141 /* 12940 */ "DBG_LABEL\000"
5142 /* 12950 */ "EH_LABEL\000"
5143 /* 12959 */ "ANNOTATION_LABEL\000"
5144 /* 12976 */ "ICALL_BRANCH_FUNNEL\000"
5145 /* 12996 */ "G_FSHL\000"
5146 /* 13003 */ "G_SHL\000"
5147 /* 13009 */ "G_FCEIL\000"
5148 /* 13017 */ "G_SAVGCEIL\000"
5149 /* 13028 */ "G_UAVGCEIL\000"
5150 /* 13039 */ "PATCHABLE_TAIL_CALL\000"
5151 /* 13059 */ "RET_CALL\000"
5152 /* 13068 */ "PATCHABLE_TYPED_EVENT_CALL\000"
5153 /* 13095 */ "PATCHABLE_EVENT_CALL\000"
5154 /* 13116 */ "FENTRY_CALL\000"
5155 /* 13128 */ "CATCH_ALL\000"
5156 /* 13138 */ "KILL\000"
5157 /* 13143 */ "G_CONSTANT_POOL\000"
5158 /* 13159 */ "G_ROTL\000"
5159 /* 13166 */ "G_VECREDUCE_FMUL\000"
5160 /* 13183 */ "G_FMUL\000"
5161 /* 13190 */ "G_VECREDUCE_SEQ_FMUL\000"
5162 /* 13211 */ "G_STRICT_FMUL\000"
5163 /* 13225 */ "G_CLMUL\000"
5164 /* 13233 */ "G_VECREDUCE_MUL\000"
5165 /* 13249 */ "G_MUL\000"
5166 /* 13255 */ "G_FREM\000"
5167 /* 13262 */ "G_STRICT_FREM\000"
5168 /* 13276 */ "G_SREM\000"
5169 /* 13283 */ "G_UREM\000"
5170 /* 13290 */ "G_SDIVREM\000"
5171 /* 13300 */ "G_UDIVREM\000"
5172 /* 13310 */ "INLINEASM\000"
5173 /* 13320 */ "G_VECREDUCE_FMINIMUM\000"
5174 /* 13341 */ "G_FMINIMUM\000"
5175 /* 13352 */ "G_ATOMICRMW_FMINIMUM\000"
5176 /* 13373 */ "G_VECREDUCE_FMAXIMUM\000"
5177 /* 13394 */ "G_FMAXIMUM\000"
5178 /* 13405 */ "G_ATOMICRMW_FMAXIMUM\000"
5179 /* 13426 */ "G_VECREDUCE_FMINIMUMNUM\000"
5180 /* 13450 */ "G_FMINIMUMNUM\000"
5181 /* 13464 */ "G_ATOMICRMW_FMINIMUMNUM\000"
5182 /* 13488 */ "G_VECREDUCE_FMAXIMUMNUM\000"
5183 /* 13512 */ "G_FMAXIMUMNUM\000"
5184 /* 13526 */ "G_ATOMICRMW_FMAXIMUMNUM\000"
5185 /* 13550 */ "G_FMINNUM\000"
5186 /* 13560 */ "G_FMAXNUM\000"
5187 /* 13570 */ "G_FATAN\000"
5188 /* 13578 */ "G_FTAN\000"
5189 /* 13585 */ "G_INTRINSIC_ROUNDEVEN\000"
5190 /* 13607 */ "G_ASSERT_ALIGN\000"
5191 /* 13622 */ "G_FCOPYSIGN\000"
5192 /* 13634 */ "G_VECREDUCE_FMIN\000"
5193 /* 13651 */ "G_ATOMICRMW_FMIN\000"
5194 /* 13668 */ "G_VECREDUCE_SMIN\000"
5195 /* 13685 */ "G_SMIN\000"
5196 /* 13692 */ "G_VECREDUCE_UMIN\000"
5197 /* 13709 */ "G_UMIN\000"
5198 /* 13716 */ "G_ATOMICRMW_UMIN\000"
5199 /* 13733 */ "G_ATOMICRMW_MIN\000"
5200 /* 13749 */ "G_FASIN\000"
5201 /* 13757 */ "G_FSIN\000"
5202 /* 13764 */ "END_FUNCTION\000"
5203 /* 13777 */ "CFI_INSTRUCTION\000"
5204 /* 13793 */ "G_CTLZ_ZERO_POISON\000"
5205 /* 13812 */ "G_CTTZ_ZERO_POISON\000"
5206 /* 13831 */ "FALLTHROUGH_RETURN\000"
5207 /* 13850 */ "ADJCALLSTACKDOWN\000"
5208 /* 13867 */ "G_SSUBO\000"
5209 /* 13875 */ "G_USUBO\000"
5210 /* 13883 */ "G_SADDO\000"
5211 /* 13891 */ "G_UADDO\000"
5212 /* 13899 */ "JUMP_TABLE_DEBUG_INFO\000"
5213 /* 13921 */ "G_SMULO\000"
5214 /* 13929 */ "G_UMULO\000"
5215 /* 13937 */ "G_BZERO\000"
5216 /* 13945 */ "STACKMAP\000"
5217 /* 13954 */ "G_DEBUGTRAP\000"
5218 /* 13966 */ "G_UBSANTRAP\000"
5219 /* 13978 */ "G_TRAP\000"
5220 /* 13985 */ "G_ATOMICRMW_UDEC_WRAP\000"
5221 /* 14007 */ "G_ATOMICRMW_UINC_WRAP\000"
5222 /* 14029 */ "G_BSWAP\000"
5223 /* 14037 */ "G_SITOFP\000"
5224 /* 14046 */ "G_UITOFP\000"
5225 /* 14055 */ "G_FCMP\000"
5226 /* 14062 */ "G_STRICT_FCMP\000"
5227 /* 14076 */ "G_ICMP\000"
5228 /* 14083 */ "G_SCMP\000"
5229 /* 14090 */ "G_UCMP\000"
5230 /* 14097 */ "NOP\000"
5231 /* 14101 */ "END_LOOP\000"
5232 /* 14110 */ "CONVERGENCECTRL_LOOP\000"
5233 /* 14131 */ "G_CTPOP\000"
5234 /* 14139 */ "DATA_DROP\000"
5235 /* 14149 */ "PATCHABLE_OP\000"
5236 /* 14162 */ "FAULTING_OP\000"
5237 /* 14174 */ "ADJCALLSTACKUP\000"
5238 /* 14189 */ "PREALLOCATED_SETUP\000"
5239 /* 14208 */ "G_FLDEXP\000"
5240 /* 14217 */ "G_STRICT_FLDEXP\000"
5241 /* 14233 */ "G_FEXP\000"
5242 /* 14240 */ "G_FFREXP\000"
5243 /* 14249 */ "G_BR\000"
5244 /* 14254 */ "INLINEASM_BR\000"
5245 /* 14267 */ "G_BLOCK_ADDR\000"
5246 /* 14280 */ "MEMBARRIER\000"
5247 /* 14291 */ "G_CONSTANT_FOLD_BARRIER\000"
5248 /* 14315 */ "PATCHABLE_FUNCTION_ENTER\000"
5249 /* 14340 */ "G_READCYCLECOUNTER\000"
5250 /* 14359 */ "G_READSTEADYCOUNTER\000"
5251 /* 14379 */ "G_READ_REGISTER\000"
5252 /* 14395 */ "G_WRITE_REGISTER\000"
5253 /* 14412 */ "G_ASHR\000"
5254 /* 14419 */ "G_FSHR\000"
5255 /* 14426 */ "G_LSHR\000"
5256 /* 14433 */ "CONVERGENCECTRL_ANCHOR\000"
5257 /* 14456 */ "G_FFLOOR\000"
5258 /* 14465 */ "G_SAVGFLOOR\000"
5259 /* 14477 */ "G_UAVGFLOOR\000"
5260 /* 14489 */ "G_EXTRACT_SUBVECTOR\000"
5261 /* 14509 */ "G_INSERT_SUBVECTOR\000"
5262 /* 14528 */ "G_BUILD_VECTOR\000"
5263 /* 14543 */ "G_SHUFFLE_VECTOR\000"
5264 /* 14560 */ "G_STEP_VECTOR\000"
5265 /* 14574 */ "G_SPLAT_VECTOR\000"
5266 /* 14589 */ "G_VECREDUCE_XOR\000"
5267 /* 14605 */ "G_XOR\000"
5268 /* 14611 */ "G_ATOMICRMW_XOR\000"
5269 /* 14627 */ "G_VECREDUCE_OR\000"
5270 /* 14642 */ "G_OR\000"
5271 /* 14647 */ "G_ATOMICRMW_OR\000"
5272 /* 14662 */ "G_ROTR\000"
5273 /* 14669 */ "G_INTTOPTR\000"
5274 /* 14680 */ "G_FABS\000"
5275 /* 14687 */ "G_ABS\000"
5276 /* 14693 */ "G_ABDS\000"
5277 /* 14700 */ "G_UNMERGE_VALUES\000"
5278 /* 14717 */ "G_MERGE_VALUES\000"
5279 /* 14732 */ "G_CTLS\000"
5280 /* 14739 */ "CALL_PARAMS\000"
5281 /* 14751 */ "G_FACOS\000"
5282 /* 14759 */ "G_FCOS\000"
5283 /* 14766 */ "G_FSINCOS\000"
5284 /* 14776 */ "G_STRICT_FCMPS\000"
5285 /* 14791 */ "G_CONCAT_VECTORS\000"
5286 /* 14808 */ "COPY_TO_REGCLASS\000"
5287 /* 14825 */ "G_IS_FPCLASS\000"
5288 /* 14838 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000"
5289 /* 14868 */ "BR_UNLESS\000"
5290 /* 14878 */ "G_VECTOR_COMPRESS\000"
5291 /* 14896 */ "G_INTRINSIC_W_SIDE_EFFECTS\000"
5292 /* 14923 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000"
5293 /* 14961 */ "RET_CALL_RESULTS\000"
5294 /* 14978 */ "LOAD_F16_F32_A32_S\000"
5295 /* 14997 */ "STORE_F16_F32_A32_S\000"
5296 /* 15017 */ "LOAD_F32_A32_S\000"
5297 /* 15032 */ "STORE_F32_A32_S\000"
5298 /* 15048 */ "ATOMIC_STORE16_I32_A32_S\000"
5299 /* 15073 */ "ATOMIC_STORE8_I32_A32_S\000"
5300 /* 15097 */ "ATOMIC_RMW16_U_SUB_I32_A32_S\000"
5301 /* 15126 */ "ATOMIC_RMW8_U_SUB_I32_A32_S\000"
5302 /* 15154 */ "ATOMIC_RMW_SUB_I32_A32_S\000"
5303 /* 15179 */ "ATOMIC_LOAD_I32_A32_S\000"
5304 /* 15201 */ "ATOMIC_RMW16_U_ADD_I32_A32_S\000"
5305 /* 15230 */ "ATOMIC_RMW8_U_ADD_I32_A32_S\000"
5306 /* 15258 */ "ATOMIC_RMW_ADD_I32_A32_S\000"
5307 /* 15283 */ "ATOMIC_RMW16_U_AND_I32_A32_S\000"
5308 /* 15312 */ "ATOMIC_RMW8_U_AND_I32_A32_S\000"
5309 /* 15340 */ "ATOMIC_RMW_AND_I32_A32_S\000"
5310 /* 15365 */ "ATOMIC_STORE_I32_A32_S\000"
5311 /* 15388 */ "ATOMIC_RMW16_U_CMPXCHG_I32_A32_S\000"
5312 /* 15421 */ "ATOMIC_RMW8_U_CMPXCHG_I32_A32_S\000"
5313 /* 15453 */ "ATOMIC_RMW_CMPXCHG_I32_A32_S\000"
5314 /* 15482 */ "ATOMIC_RMW16_U_XCHG_I32_A32_S\000"
5315 /* 15512 */ "ATOMIC_RMW8_U_XCHG_I32_A32_S\000"
5316 /* 15541 */ "ATOMIC_RMW_XCHG_I32_A32_S\000"
5317 /* 15567 */ "ATOMIC_RMW16_U_XOR_I32_A32_S\000"
5318 /* 15596 */ "ATOMIC_RMW8_U_XOR_I32_A32_S\000"
5319 /* 15624 */ "ATOMIC_RMW_XOR_I32_A32_S\000"
5320 /* 15649 */ "ATOMIC_RMW16_U_OR_I32_A32_S\000"
5321 /* 15677 */ "ATOMIC_RMW8_U_OR_I32_A32_S\000"
5322 /* 15704 */ "ATOMIC_RMW_OR_I32_A32_S\000"
5323 /* 15728 */ "LOAD16_S_I32_A32_S\000"
5324 /* 15747 */ "LOAD8_S_I32_A32_S\000"
5325 /* 15765 */ "ATOMIC_LOAD16_U_I32_A32_S\000"
5326 /* 15791 */ "ATOMIC_LOAD8_U_I32_A32_S\000"
5327 /* 15816 */ "MEMORY_ATOMIC_WAIT32_A32_S\000"
5328 /* 15843 */ "LOAD_LANE_32_A32_S\000"
5329 /* 15862 */ "LOAD_ZERO_32_A32_S\000"
5330 /* 15881 */ "STORE_LANE_I64x2_A32_S\000"
5331 /* 15904 */ "LOAD_EXTEND_S_I64x2_A32_S\000"
5332 /* 15930 */ "LOAD_EXTEND_U_I64x2_A32_S\000"
5333 /* 15956 */ "LOAD_F64_A32_S\000"
5334 /* 15971 */ "STORE_F64_A32_S\000"
5335 /* 15987 */ "ATOMIC_STORE32_I64_A32_S\000"
5336 /* 16012 */ "ATOMIC_STORE16_I64_A32_S\000"
5337 /* 16037 */ "ATOMIC_STORE8_I64_A32_S\000"
5338 /* 16061 */ "ATOMIC_RMW32_U_SUB_I64_A32_S\000"
5339 /* 16090 */ "ATOMIC_RMW16_U_SUB_I64_A32_S\000"
5340 /* 16119 */ "ATOMIC_RMW8_U_SUB_I64_A32_S\000"
5341 /* 16147 */ "ATOMIC_RMW_SUB_I64_A32_S\000"
5342 /* 16172 */ "ATOMIC_LOAD_I64_A32_S\000"
5343 /* 16194 */ "ATOMIC_RMW32_U_ADD_I64_A32_S\000"
5344 /* 16223 */ "ATOMIC_RMW16_U_ADD_I64_A32_S\000"
5345 /* 16252 */ "ATOMIC_RMW8_U_ADD_I64_A32_S\000"
5346 /* 16280 */ "ATOMIC_RMW_ADD_I64_A32_S\000"
5347 /* 16305 */ "ATOMIC_RMW32_U_AND_I64_A32_S\000"
5348 /* 16334 */ "ATOMIC_RMW16_U_AND_I64_A32_S\000"
5349 /* 16363 */ "ATOMIC_RMW8_U_AND_I64_A32_S\000"
5350 /* 16391 */ "ATOMIC_RMW_AND_I64_A32_S\000"
5351 /* 16416 */ "ATOMIC_STORE_I64_A32_S\000"
5352 /* 16439 */ "ATOMIC_RMW32_U_CMPXCHG_I64_A32_S\000"
5353 /* 16472 */ "ATOMIC_RMW16_U_CMPXCHG_I64_A32_S\000"
5354 /* 16505 */ "ATOMIC_RMW8_U_CMPXCHG_I64_A32_S\000"
5355 /* 16537 */ "ATOMIC_RMW_CMPXCHG_I64_A32_S\000"
5356 /* 16566 */ "ATOMIC_RMW32_U_XCHG_I64_A32_S\000"
5357 /* 16596 */ "ATOMIC_RMW16_U_XCHG_I64_A32_S\000"
5358 /* 16626 */ "ATOMIC_RMW8_U_XCHG_I64_A32_S\000"
5359 /* 16655 */ "ATOMIC_RMW_XCHG_I64_A32_S\000"
5360 /* 16681 */ "ATOMIC_RMW32_U_XOR_I64_A32_S\000"
5361 /* 16710 */ "ATOMIC_RMW16_U_XOR_I64_A32_S\000"
5362 /* 16739 */ "ATOMIC_RMW8_U_XOR_I64_A32_S\000"
5363 /* 16767 */ "ATOMIC_RMW_XOR_I64_A32_S\000"
5364 /* 16792 */ "ATOMIC_RMW32_U_OR_I64_A32_S\000"
5365 /* 16820 */ "ATOMIC_RMW16_U_OR_I64_A32_S\000"
5366 /* 16848 */ "ATOMIC_RMW8_U_OR_I64_A32_S\000"
5367 /* 16875 */ "ATOMIC_RMW_OR_I64_A32_S\000"
5368 /* 16899 */ "LOAD32_S_I64_A32_S\000"
5369 /* 16918 */ "LOAD16_S_I64_A32_S\000"
5370 /* 16937 */ "LOAD8_S_I64_A32_S\000"
5371 /* 16955 */ "ATOMIC_LOAD32_U_I64_A32_S\000"
5372 /* 16981 */ "ATOMIC_LOAD16_U_I64_A32_S\000"
5373 /* 17007 */ "ATOMIC_LOAD8_U_I64_A32_S\000"
5374 /* 17032 */ "MEMORY_ATOMIC_WAIT64_A32_S\000"
5375 /* 17059 */ "LOAD_LANE_64_A32_S\000"
5376 /* 17078 */ "LOAD_ZERO_64_A32_S\000"
5377 /* 17097 */ "STORE_LANE_I32x4_A32_S\000"
5378 /* 17120 */ "LOAD_EXTEND_S_I32x4_A32_S\000"
5379 /* 17146 */ "LOAD_EXTEND_U_I32x4_A32_S\000"
5380 /* 17172 */ "LOAD_LANE_16_A32_S\000"
5381 /* 17191 */ "STORE_LANE_I8x16_A32_S\000"
5382 /* 17214 */ "LOAD_V128_A32_S\000"
5383 /* 17230 */ "STORE_V128_A32_S\000"
5384 /* 17247 */ "LOAD_LANE_8_A32_S\000"
5385 /* 17265 */ "STORE_LANE_I16x8_A32_S\000"
5386 /* 17288 */ "LOAD_EXTEND_S_I16x8_A32_S\000"
5387 /* 17314 */ "LOAD_EXTEND_U_I16x8_A32_S\000"
5388 /* 17340 */ "anonymous_14422MEMORY_SIZE_A32_S\000"
5389 /* 17373 */ "MEMORY_FILL_A32_S\000"
5390 /* 17391 */ "LOAD32_SPLAT_A32_S\000"
5391 /* 17410 */ "LOAD64_SPLAT_A32_S\000"
5392 /* 17429 */ "LOAD16_SPLAT_A32_S\000"
5393 /* 17448 */ "LOAD8_SPLAT_A32_S\000"
5394 /* 17466 */ "MEMSET_A32_S\000"
5395 /* 17479 */ "MEMORY_INIT_A32_S\000"
5396 /* 17497 */ "anonymous_14422MEMORY_GROW_A32_S\000"
5397 /* 17530 */ "MEMORY_ATOMIC_NOTIFY_A32_S\000"
5398 /* 17557 */ "MEMCPY_A32_S\000"
5399 /* 17570 */ "MEMORY_COPY_A32_S\000"
5400 /* 17588 */ "FP_TO_SINT_I32_F32_S\000"
5401 /* 17609 */ "FP_TO_UINT_I32_F32_S\000"
5402 /* 17630 */ "FP_TO_SINT_I64_F32_S\000"
5403 /* 17651 */ "FP_TO_UINT_I64_F32_S\000"
5404 /* 17672 */ "SUB_F32_S\000"
5405 /* 17682 */ "TRUNC_F32_S\000"
5406 /* 17694 */ "ADD_F32_S\000"
5407 /* 17704 */ "LOCAL_TEE_F32_S\000"
5408 /* 17720 */ "GE_F32_S\000"
5409 /* 17729 */ "LE_F32_S\000"
5410 /* 17738 */ "NE_F32_S\000"
5411 /* 17747 */ "F64_PROMOTE_F32_S\000"
5412 /* 17765 */ "NEG_F32_S\000"
5413 /* 17775 */ "CEIL_F32_S\000"
5414 /* 17786 */ "MUL_F32_S\000"
5415 /* 17796 */ "COPYSIGN_F32_S\000"
5416 /* 17811 */ "MIN_F32_S\000"
5417 /* 17821 */ "DROP_F32_S\000"
5418 /* 17832 */ "EQ_F32_S\000"
5419 /* 17841 */ "FLOOR_F32_S\000"
5420 /* 17853 */ "ABS_F32_S\000"
5421 /* 17863 */ "I32_TRUNC_S_F32_S\000"
5422 /* 17881 */ "I64_TRUNC_S_F32_S\000"
5423 /* 17899 */ "I32_TRUNC_S_SAT_F32_S\000"
5424 /* 17921 */ "I64_TRUNC_S_SAT_F32_S\000"
5425 /* 17943 */ "I32_TRUNC_U_SAT_F32_S\000"
5426 /* 17965 */ "I64_TRUNC_U_SAT_F32_S\000"
5427 /* 17987 */ "SELECT_F32_S\000"
5428 /* 18000 */ "GLOBAL_GET_F32_S\000"
5429 /* 18017 */ "LOCAL_GET_F32_S\000"
5430 /* 18033 */ "I32_REINTERPRET_F32_S\000"
5431 /* 18055 */ "GLOBAL_SET_F32_S\000"
5432 /* 18072 */ "LOCAL_SET_F32_S\000"
5433 /* 18088 */ "GT_F32_S\000"
5434 /* 18097 */ "LT_F32_S\000"
5435 /* 18106 */ "SQRT_F32_S\000"
5436 /* 18117 */ "NEAREST_F32_S\000"
5437 /* 18131 */ "CONST_F32_S\000"
5438 /* 18143 */ "I32_TRUNC_U_F32_S\000"
5439 /* 18161 */ "I64_TRUNC_U_F32_S\000"
5440 /* 18179 */ "DIV_F32_S\000"
5441 /* 18189 */ "MAX_F32_S\000"
5442 /* 18199 */ "COPY_F32_S\000"
5443 /* 18210 */ "SUB_I32_S\000"
5444 /* 18220 */ "ADD_I32_S\000"
5445 /* 18230 */ "AND_I32_S\000"
5446 /* 18240 */ "LOCAL_TEE_I32_S\000"
5447 /* 18256 */ "BR_TABLE_I32_S\000"
5448 /* 18271 */ "NE_I32_S\000"
5449 /* 18280 */ "SHL_I32_S\000"
5450 /* 18290 */ "ROTL_I32_S\000"
5451 /* 18301 */ "MUL_I32_S\000"
5452 /* 18311 */ "DROP_I32_S\000"
5453 /* 18322 */ "EQ_I32_S\000"
5454 /* 18331 */ "XOR_I32_S\000"
5455 /* 18341 */ "ROTR_I32_S\000"
5456 /* 18352 */ "I32_EXTEND16_S_I32_S\000"
5457 /* 18373 */ "I32_EXTEND8_S_I32_S\000"
5458 /* 18393 */ "I64_EXTEND_S_I32_S\000"
5459 /* 18412 */ "GE_S_I32_S\000"
5460 /* 18423 */ "LE_S_I32_S\000"
5461 /* 18434 */ "REM_S_I32_S\000"
5462 /* 18446 */ "SHR_S_I32_S\000"
5463 /* 18458 */ "GT_S_I32_S\000"
5464 /* 18469 */ "LT_S_I32_S\000"
5465 /* 18480 */ "F32_CONVERT_S_I32_S\000"
5466 /* 18500 */ "F64_CONVERT_S_I32_S\000"
5467 /* 18520 */ "DIV_S_I32_S\000"
5468 /* 18532 */ "SELECT_I32_S\000"
5469 /* 18545 */ "GLOBAL_GET_I32_S\000"
5470 /* 18562 */ "LOCAL_GET_I32_S\000"
5471 /* 18578 */ "F32_REINTERPRET_I32_S\000"
5472 /* 18600 */ "GLOBAL_SET_I32_S\000"
5473 /* 18617 */ "LOCAL_SET_I32_S\000"
5474 /* 18633 */ "POPCNT_I32_S\000"
5475 /* 18646 */ "CONST_I32_S\000"
5476 /* 18658 */ "I64_EXTEND_U_I32_S\000"
5477 /* 18677 */ "GE_U_I32_S\000"
5478 /* 18688 */ "LE_U_I32_S\000"
5479 /* 18699 */ "REM_U_I32_S\000"
5480 /* 18711 */ "SHR_U_I32_S\000"
5481 /* 18723 */ "GT_U_I32_S\000"
5482 /* 18734 */ "LT_U_I32_S\000"
5483 /* 18745 */ "F32_CONVERT_U_I32_S\000"
5484 /* 18765 */ "F64_CONVERT_U_I32_S\000"
5485 /* 18785 */ "DIV_U_I32_S\000"
5486 /* 18797 */ "COPY_I32_S\000"
5487 /* 18808 */ "CLZ_I32_S\000"
5488 /* 18818 */ "EQZ_I32_S\000"
5489 /* 18828 */ "CTZ_I32_S\000"
5490 /* 18838 */ "ARGUMENT_v4f32_S\000"
5491 /* 18855 */ "ARGUMENT_f32_S\000"
5492 /* 18870 */ "ARGUMENT_v4i32_S\000"
5493 /* 18887 */ "ARGUMENT_i32_S\000"
5494 /* 18902 */ "CONST_V128_F64x2_S\000"
5495 /* 18921 */ "SUB_F64x2_S\000"
5496 /* 18933 */ "TRUNC_F64x2_S\000"
5497 /* 18947 */ "NMADD_F64x2_S\000"
5498 /* 18961 */ "GE_F64x2_S\000"
5499 /* 18972 */ "LE_F64x2_S\000"
5500 /* 18983 */ "REPLACE_LANE_F64x2_S\000"
5501 /* 19004 */ "EXTRACT_LANE_F64x2_S\000"
5502 /* 19025 */ "NEG_F64x2_S\000"
5503 /* 19037 */ "CEIL_F64x2_S\000"
5504 /* 19050 */ "MUL_F64x2_S\000"
5505 /* 19062 */ "SIMD_RELAXED_FMIN_F64x2_S\000"
5506 /* 19088 */ "PMIN_F64x2_S\000"
5507 /* 19101 */ "EQ_F64x2_S\000"
5508 /* 19112 */ "FLOOR_F64x2_S\000"
5509 /* 19126 */ "ABS_F64x2_S\000"
5510 /* 19138 */ "SPLAT_F64x2_S\000"
5511 /* 19152 */ "GT_F64x2_S\000"
5512 /* 19163 */ "LT_F64x2_S\000"
5513 /* 19174 */ "SQRT_F64x2_S\000"
5514 /* 19187 */ "NEAREST_F64x2_S\000"
5515 /* 19203 */ "DIV_F64x2_S\000"
5516 /* 19215 */ "SIMD_RELAXED_FMAX_F64x2_S\000"
5517 /* 19241 */ "PMAX_F64x2_S\000"
5518 /* 19254 */ "convert_low_s_F64x2_S\000"
5519 /* 19276 */ "convert_low_u_F64x2_S\000"
5520 /* 19298 */ "promote_low_F64x2_S\000"
5521 /* 19318 */ "CONST_V128_I64x2_S\000"
5522 /* 19337 */ "SUB_I64x2_S\000"
5523 /* 19349 */ "ADD_I64x2_S\000"
5524 /* 19361 */ "REPLACE_LANE_I64x2_S\000"
5525 /* 19382 */ "EXTRACT_LANE_I64x2_S\000"
5526 /* 19403 */ "ALLTRUE_I64x2_S\000"
5527 /* 19419 */ "NEG_I64x2_S\000"
5528 /* 19431 */ "BITMASK_I64x2_S\000"
5529 /* 19447 */ "SHL_I64x2_S\000"
5530 /* 19459 */ "MUL_I64x2_S\000"
5531 /* 19471 */ "EQ_I64x2_S\000"
5532 /* 19482 */ "ABS_I64x2_S\000"
5533 /* 19494 */ "GE_S_I64x2_S\000"
5534 /* 19507 */ "LE_S_I64x2_S\000"
5535 /* 19520 */ "EXTMUL_HIGH_S_I64x2_S\000"
5536 /* 19542 */ "SHR_S_I64x2_S\000"
5537 /* 19556 */ "GT_S_I64x2_S\000"
5538 /* 19569 */ "LT_S_I64x2_S\000"
5539 /* 19582 */ "EXTMUL_LOW_S_I64x2_S\000"
5540 /* 19603 */ "SPLAT_I64x2_S\000"
5541 /* 19617 */ "LANESELECT_I64x2_S\000"
5542 /* 19636 */ "EXTMUL_HIGH_U_I64x2_S\000"
5543 /* 19658 */ "SHR_U_I64x2_S\000"
5544 /* 19672 */ "EXTMUL_LOW_U_I64x2_S\000"
5545 /* 19693 */ "extend_high_s_I64x2_S\000"
5546 /* 19715 */ "extend_low_s_I64x2_S\000"
5547 /* 19736 */ "extend_high_u_I64x2_S\000"
5548 /* 19758 */ "extend_low_u_I64x2_S\000"
5549 /* 19779 */ "LOAD_F16_F32_A64_S\000"
5550 /* 19798 */ "STORE_F16_F32_A64_S\000"
5551 /* 19818 */ "LOAD_F32_A64_S\000"
5552 /* 19833 */ "STORE_F32_A64_S\000"
5553 /* 19849 */ "ATOMIC_STORE16_I32_A64_S\000"
5554 /* 19874 */ "ATOMIC_STORE8_I32_A64_S\000"
5555 /* 19898 */ "ATOMIC_RMW16_U_SUB_I32_A64_S\000"
5556 /* 19927 */ "ATOMIC_RMW8_U_SUB_I32_A64_S\000"
5557 /* 19955 */ "ATOMIC_RMW_SUB_I32_A64_S\000"
5558 /* 19980 */ "ATOMIC_LOAD_I32_A64_S\000"
5559 /* 20002 */ "ATOMIC_RMW16_U_ADD_I32_A64_S\000"
5560 /* 20031 */ "ATOMIC_RMW8_U_ADD_I32_A64_S\000"
5561 /* 20059 */ "ATOMIC_RMW_ADD_I32_A64_S\000"
5562 /* 20084 */ "ATOMIC_RMW16_U_AND_I32_A64_S\000"
5563 /* 20113 */ "ATOMIC_RMW8_U_AND_I32_A64_S\000"
5564 /* 20141 */ "ATOMIC_RMW_AND_I32_A64_S\000"
5565 /* 20166 */ "ATOMIC_STORE_I32_A64_S\000"
5566 /* 20189 */ "ATOMIC_RMW16_U_CMPXCHG_I32_A64_S\000"
5567 /* 20222 */ "ATOMIC_RMW8_U_CMPXCHG_I32_A64_S\000"
5568 /* 20254 */ "ATOMIC_RMW_CMPXCHG_I32_A64_S\000"
5569 /* 20283 */ "ATOMIC_RMW16_U_XCHG_I32_A64_S\000"
5570 /* 20313 */ "ATOMIC_RMW8_U_XCHG_I32_A64_S\000"
5571 /* 20342 */ "ATOMIC_RMW_XCHG_I32_A64_S\000"
5572 /* 20368 */ "ATOMIC_RMW16_U_XOR_I32_A64_S\000"
5573 /* 20397 */ "ATOMIC_RMW8_U_XOR_I32_A64_S\000"
5574 /* 20425 */ "ATOMIC_RMW_XOR_I32_A64_S\000"
5575 /* 20450 */ "ATOMIC_RMW16_U_OR_I32_A64_S\000"
5576 /* 20478 */ "ATOMIC_RMW8_U_OR_I32_A64_S\000"
5577 /* 20505 */ "ATOMIC_RMW_OR_I32_A64_S\000"
5578 /* 20529 */ "LOAD16_S_I32_A64_S\000"
5579 /* 20548 */ "LOAD8_S_I32_A64_S\000"
5580 /* 20566 */ "ATOMIC_LOAD16_U_I32_A64_S\000"
5581 /* 20592 */ "ATOMIC_LOAD8_U_I32_A64_S\000"
5582 /* 20617 */ "MEMORY_ATOMIC_WAIT32_A64_S\000"
5583 /* 20644 */ "LOAD_LANE_32_A64_S\000"
5584 /* 20663 */ "LOAD_ZERO_32_A64_S\000"
5585 /* 20682 */ "STORE_LANE_I64x2_A64_S\000"
5586 /* 20705 */ "LOAD_EXTEND_S_I64x2_A64_S\000"
5587 /* 20731 */ "LOAD_EXTEND_U_I64x2_A64_S\000"
5588 /* 20757 */ "LOAD_F64_A64_S\000"
5589 /* 20772 */ "STORE_F64_A64_S\000"
5590 /* 20788 */ "ATOMIC_STORE32_I64_A64_S\000"
5591 /* 20813 */ "ATOMIC_STORE16_I64_A64_S\000"
5592 /* 20838 */ "ATOMIC_STORE8_I64_A64_S\000"
5593 /* 20862 */ "ATOMIC_RMW32_U_SUB_I64_A64_S\000"
5594 /* 20891 */ "ATOMIC_RMW16_U_SUB_I64_A64_S\000"
5595 /* 20920 */ "ATOMIC_RMW8_U_SUB_I64_A64_S\000"
5596 /* 20948 */ "ATOMIC_RMW_SUB_I64_A64_S\000"
5597 /* 20973 */ "ATOMIC_LOAD_I64_A64_S\000"
5598 /* 20995 */ "ATOMIC_RMW32_U_ADD_I64_A64_S\000"
5599 /* 21024 */ "ATOMIC_RMW16_U_ADD_I64_A64_S\000"
5600 /* 21053 */ "ATOMIC_RMW8_U_ADD_I64_A64_S\000"
5601 /* 21081 */ "ATOMIC_RMW_ADD_I64_A64_S\000"
5602 /* 21106 */ "ATOMIC_RMW32_U_AND_I64_A64_S\000"
5603 /* 21135 */ "ATOMIC_RMW16_U_AND_I64_A64_S\000"
5604 /* 21164 */ "ATOMIC_RMW8_U_AND_I64_A64_S\000"
5605 /* 21192 */ "ATOMIC_RMW_AND_I64_A64_S\000"
5606 /* 21217 */ "ATOMIC_STORE_I64_A64_S\000"
5607 /* 21240 */ "ATOMIC_RMW32_U_CMPXCHG_I64_A64_S\000"
5608 /* 21273 */ "ATOMIC_RMW16_U_CMPXCHG_I64_A64_S\000"
5609 /* 21306 */ "ATOMIC_RMW8_U_CMPXCHG_I64_A64_S\000"
5610 /* 21338 */ "ATOMIC_RMW_CMPXCHG_I64_A64_S\000"
5611 /* 21367 */ "ATOMIC_RMW32_U_XCHG_I64_A64_S\000"
5612 /* 21397 */ "ATOMIC_RMW16_U_XCHG_I64_A64_S\000"
5613 /* 21427 */ "ATOMIC_RMW8_U_XCHG_I64_A64_S\000"
5614 /* 21456 */ "ATOMIC_RMW_XCHG_I64_A64_S\000"
5615 /* 21482 */ "ATOMIC_RMW32_U_XOR_I64_A64_S\000"
5616 /* 21511 */ "ATOMIC_RMW16_U_XOR_I64_A64_S\000"
5617 /* 21540 */ "ATOMIC_RMW8_U_XOR_I64_A64_S\000"
5618 /* 21568 */ "ATOMIC_RMW_XOR_I64_A64_S\000"
5619 /* 21593 */ "ATOMIC_RMW32_U_OR_I64_A64_S\000"
5620 /* 21621 */ "ATOMIC_RMW16_U_OR_I64_A64_S\000"
5621 /* 21649 */ "ATOMIC_RMW8_U_OR_I64_A64_S\000"
5622 /* 21676 */ "ATOMIC_RMW_OR_I64_A64_S\000"
5623 /* 21700 */ "LOAD32_S_I64_A64_S\000"
5624 /* 21719 */ "LOAD16_S_I64_A64_S\000"
5625 /* 21738 */ "LOAD8_S_I64_A64_S\000"
5626 /* 21756 */ "ATOMIC_LOAD32_U_I64_A64_S\000"
5627 /* 21782 */ "ATOMIC_LOAD16_U_I64_A64_S\000"
5628 /* 21808 */ "ATOMIC_LOAD8_U_I64_A64_S\000"
5629 /* 21833 */ "MEMORY_ATOMIC_WAIT64_A64_S\000"
5630 /* 21860 */ "LOAD_LANE_64_A64_S\000"
5631 /* 21879 */ "LOAD_ZERO_64_A64_S\000"
5632 /* 21898 */ "STORE_LANE_I32x4_A64_S\000"
5633 /* 21921 */ "LOAD_EXTEND_S_I32x4_A64_S\000"
5634 /* 21947 */ "LOAD_EXTEND_U_I32x4_A64_S\000"
5635 /* 21973 */ "LOAD_LANE_16_A64_S\000"
5636 /* 21992 */ "STORE_LANE_I8x16_A64_S\000"
5637 /* 22015 */ "LOAD_V128_A64_S\000"
5638 /* 22031 */ "STORE_V128_A64_S\000"
5639 /* 22048 */ "LOAD_LANE_8_A64_S\000"
5640 /* 22066 */ "STORE_LANE_I16x8_A64_S\000"
5641 /* 22089 */ "LOAD_EXTEND_S_I16x8_A64_S\000"
5642 /* 22115 */ "LOAD_EXTEND_U_I16x8_A64_S\000"
5643 /* 22141 */ "anonymous_14423MEMORY_SIZE_A64_S\000"
5644 /* 22174 */ "MEMORY_FILL_A64_S\000"
5645 /* 22192 */ "LOAD32_SPLAT_A64_S\000"
5646 /* 22211 */ "LOAD64_SPLAT_A64_S\000"
5647 /* 22230 */ "LOAD16_SPLAT_A64_S\000"
5648 /* 22249 */ "LOAD8_SPLAT_A64_S\000"
5649 /* 22267 */ "MEMSET_A64_S\000"
5650 /* 22280 */ "MEMORY_INIT_A64_S\000"
5651 /* 22298 */ "anonymous_14423MEMORY_GROW_A64_S\000"
5652 /* 22331 */ "MEMORY_ATOMIC_NOTIFY_A64_S\000"
5653 /* 22358 */ "MEMCPY_A64_S\000"
5654 /* 22371 */ "MEMORY_COPY_A64_S\000"
5655 /* 22389 */ "FP_TO_SINT_I32_F64_S\000"
5656 /* 22410 */ "FP_TO_UINT_I32_F64_S\000"
5657 /* 22431 */ "FP_TO_SINT_I64_F64_S\000"
5658 /* 22452 */ "FP_TO_UINT_I64_F64_S\000"
5659 /* 22473 */ "SUB_F64_S\000"
5660 /* 22483 */ "TRUNC_F64_S\000"
5661 /* 22495 */ "ADD_F64_S\000"
5662 /* 22505 */ "LOCAL_TEE_F64_S\000"
5663 /* 22521 */ "GE_F64_S\000"
5664 /* 22530 */ "LE_F64_S\000"
5665 /* 22539 */ "NE_F64_S\000"
5666 /* 22548 */ "F32_DEMOTE_F64_S\000"
5667 /* 22565 */ "NEG_F64_S\000"
5668 /* 22575 */ "CEIL_F64_S\000"
5669 /* 22586 */ "MUL_F64_S\000"
5670 /* 22596 */ "COPYSIGN_F64_S\000"
5671 /* 22611 */ "MIN_F64_S\000"
5672 /* 22621 */ "DROP_F64_S\000"
5673 /* 22632 */ "EQ_F64_S\000"
5674 /* 22641 */ "FLOOR_F64_S\000"
5675 /* 22653 */ "ABS_F64_S\000"
5676 /* 22663 */ "I32_TRUNC_S_F64_S\000"
5677 /* 22681 */ "I64_TRUNC_S_F64_S\000"
5678 /* 22699 */ "I32_TRUNC_S_SAT_F64_S\000"
5679 /* 22721 */ "I64_TRUNC_S_SAT_F64_S\000"
5680 /* 22743 */ "I32_TRUNC_U_SAT_F64_S\000"
5681 /* 22765 */ "I64_TRUNC_U_SAT_F64_S\000"
5682 /* 22787 */ "SELECT_F64_S\000"
5683 /* 22800 */ "GLOBAL_GET_F64_S\000"
5684 /* 22817 */ "LOCAL_GET_F64_S\000"
5685 /* 22833 */ "I64_REINTERPRET_F64_S\000"
5686 /* 22855 */ "GLOBAL_SET_F64_S\000"
5687 /* 22872 */ "LOCAL_SET_F64_S\000"
5688 /* 22888 */ "GT_F64_S\000"
5689 /* 22897 */ "LT_F64_S\000"
5690 /* 22906 */ "SQRT_F64_S\000"
5691 /* 22917 */ "NEAREST_F64_S\000"
5692 /* 22931 */ "CONST_F64_S\000"
5693 /* 22943 */ "I32_TRUNC_U_F64_S\000"
5694 /* 22961 */ "I64_TRUNC_U_F64_S\000"
5695 /* 22979 */ "DIV_F64_S\000"
5696 /* 22989 */ "MAX_F64_S\000"
5697 /* 22999 */ "COPY_F64_S\000"
5698 /* 23010 */ "SUB_I64_S\000"
5699 /* 23020 */ "ADD_I64_S\000"
5700 /* 23030 */ "AND_I64_S\000"
5701 /* 23040 */ "LOCAL_TEE_I64_S\000"
5702 /* 23056 */ "BR_TABLE_I64_S\000"
5703 /* 23071 */ "NE_I64_S\000"
5704 /* 23080 */ "SHL_I64_S\000"
5705 /* 23090 */ "ROTL_I64_S\000"
5706 /* 23101 */ "MUL_I64_S\000"
5707 /* 23111 */ "I32_WRAP_I64_S\000"
5708 /* 23126 */ "DROP_I64_S\000"
5709 /* 23137 */ "EQ_I64_S\000"
5710 /* 23146 */ "XOR_I64_S\000"
5711 /* 23156 */ "ROTR_I64_S\000"
5712 /* 23167 */ "I64_EXTEND32_S_I64_S\000"
5713 /* 23188 */ "I64_EXTEND16_S_I64_S\000"
5714 /* 23209 */ "I64_EXTEND8_S_I64_S\000"
5715 /* 23229 */ "GE_S_I64_S\000"
5716 /* 23240 */ "LE_S_I64_S\000"
5717 /* 23251 */ "REM_S_I64_S\000"
5718 /* 23263 */ "SHR_S_I64_S\000"
5719 /* 23275 */ "GT_S_I64_S\000"
5720 /* 23286 */ "LT_S_I64_S\000"
5721 /* 23297 */ "F32_CONVERT_S_I64_S\000"
5722 /* 23317 */ "F64_CONVERT_S_I64_S\000"
5723 /* 23337 */ "DIV_S_I64_S\000"
5724 /* 23349 */ "SELECT_I64_S\000"
5725 /* 23362 */ "GLOBAL_GET_I64_S\000"
5726 /* 23379 */ "LOCAL_GET_I64_S\000"
5727 /* 23395 */ "F64_REINTERPRET_I64_S\000"
5728 /* 23417 */ "GLOBAL_SET_I64_S\000"
5729 /* 23434 */ "LOCAL_SET_I64_S\000"
5730 /* 23450 */ "POPCNT_I64_S\000"
5731 /* 23463 */ "CONST_I64_S\000"
5732 /* 23475 */ "GE_U_I64_S\000"
5733 /* 23486 */ "LE_U_I64_S\000"
5734 /* 23497 */ "REM_U_I64_S\000"
5735 /* 23509 */ "SHR_U_I64_S\000"
5736 /* 23521 */ "GT_U_I64_S\000"
5737 /* 23532 */ "LT_U_I64_S\000"
5738 /* 23543 */ "F32_CONVERT_U_I64_S\000"
5739 /* 23563 */ "F64_CONVERT_U_I64_S\000"
5740 /* 23583 */ "DIV_U_I64_S\000"
5741 /* 23595 */ "COPY_I64_S\000"
5742 /* 23606 */ "CLZ_I64_S\000"
5743 /* 23616 */ "EQZ_I64_S\000"
5744 /* 23626 */ "CTZ_I64_S\000"
5745 /* 23636 */ "ARGUMENT_v2f64_S\000"
5746 /* 23653 */ "ARGUMENT_f64_S\000"
5747 /* 23668 */ "ARGUMENT_v2i64_S\000"
5748 /* 23685 */ "ARGUMENT_i64_S\000"
5749 /* 23700 */ "CONST_V128_F32x4_S\000"
5750 /* 23719 */ "SUB_F32x4_S\000"
5751 /* 23731 */ "TRUNC_F32x4_S\000"
5752 /* 23745 */ "NMADD_F32x4_S\000"
5753 /* 23759 */ "GE_F32x4_S\000"
5754 /* 23770 */ "LE_F32x4_S\000"
5755 /* 23781 */ "REPLACE_LANE_F32x4_S\000"
5756 /* 23802 */ "EXTRACT_LANE_F32x4_S\000"
5757 /* 23823 */ "NEG_F32x4_S\000"
5758 /* 23835 */ "CEIL_F32x4_S\000"
5759 /* 23848 */ "MUL_F32x4_S\000"
5760 /* 23860 */ "SIMD_RELAXED_FMIN_F32x4_S\000"
5761 /* 23886 */ "PMIN_F32x4_S\000"
5762 /* 23899 */ "EQ_F32x4_S\000"
5763 /* 23910 */ "FLOOR_F32x4_S\000"
5764 /* 23924 */ "ABS_F32x4_S\000"
5765 /* 23936 */ "SPLAT_F32x4_S\000"
5766 /* 23950 */ "GT_F32x4_S\000"
5767 /* 23961 */ "LT_F32x4_S\000"
5768 /* 23972 */ "SQRT_F32x4_S\000"
5769 /* 23985 */ "NEAREST_F32x4_S\000"
5770 /* 24001 */ "DIV_F32x4_S\000"
5771 /* 24013 */ "SIMD_RELAXED_FMAX_F32x4_S\000"
5772 /* 24039 */ "PMAX_F32x4_S\000"
5773 /* 24052 */ "demote_zero_F32x4_S\000"
5774 /* 24072 */ "sint_to_fp_F32x4_S\000"
5775 /* 24091 */ "uint_to_fp_F32x4_S\000"
5776 /* 24110 */ "promote_low_F32x4_S\000"
5777 /* 24130 */ "CONST_V128_I32x4_S\000"
5778 /* 24149 */ "SUB_I32x4_S\000"
5779 /* 24161 */ "ADD_I32x4_S\000"
5780 /* 24173 */ "REPLACE_LANE_I32x4_S\000"
5781 /* 24194 */ "EXTRACT_LANE_I32x4_S\000"
5782 /* 24215 */ "ALLTRUE_I32x4_S\000"
5783 /* 24231 */ "NEG_I32x4_S\000"
5784 /* 24243 */ "BITMASK_I32x4_S\000"
5785 /* 24259 */ "SHL_I32x4_S\000"
5786 /* 24271 */ "MUL_I32x4_S\000"
5787 /* 24283 */ "EQ_I32x4_S\000"
5788 /* 24294 */ "ABS_I32x4_S\000"
5789 /* 24306 */ "GE_S_I32x4_S\000"
5790 /* 24319 */ "LE_S_I32x4_S\000"
5791 /* 24332 */ "EXTMUL_HIGH_S_I32x4_S\000"
5792 /* 24354 */ "MIN_S_I32x4_S\000"
5793 /* 24368 */ "SHR_S_I32x4_S\000"
5794 /* 24382 */ "GT_S_I32x4_S\000"
5795 /* 24395 */ "LT_S_I32x4_S\000"
5796 /* 24408 */ "EXTMUL_LOW_S_I32x4_S\000"
5797 /* 24429 */ "MAX_S_I32x4_S\000"
5798 /* 24443 */ "SPLAT_I32x4_S\000"
5799 /* 24457 */ "LANESELECT_I32x4_S\000"
5800 /* 24476 */ "GE_U_I32x4_S\000"
5801 /* 24489 */ "LE_U_I32x4_S\000"
5802 /* 24502 */ "EXTMUL_HIGH_U_I32x4_S\000"
5803 /* 24524 */ "MIN_U_I32x4_S\000"
5804 /* 24538 */ "SHR_U_I32x4_S\000"
5805 /* 24552 */ "GT_U_I32x4_S\000"
5806 /* 24565 */ "LT_U_I32x4_S\000"
5807 /* 24578 */ "EXTMUL_LOW_U_I32x4_S\000"
5808 /* 24599 */ "MAX_U_I32x4_S\000"
5809 /* 24613 */ "int_wasm_relaxed_trunc_signed_I32x4_S\000"
5810 /* 24651 */ "int_wasm_relaxed_trunc_unsigned_I32x4_S\000"
5811 /* 24691 */ "int_wasm_relaxed_trunc_signed_zero_I32x4_S\000"
5812 /* 24734 */ "int_wasm_relaxed_trunc_unsigned_zero_I32x4_S\000"
5813 /* 24779 */ "extadd_pairwise_s_I32x4_S\000"
5814 /* 24805 */ "extend_high_s_I32x4_S\000"
5815 /* 24827 */ "trunc_sat_zero_s_I32x4_S\000"
5816 /* 24852 */ "extend_low_s_I32x4_S\000"
5817 /* 24873 */ "fp_to_sint_I32x4_S\000"
5818 /* 24892 */ "fp_to_uint_I32x4_S\000"
5819 /* 24911 */ "extadd_pairwise_u_I32x4_S\000"
5820 /* 24937 */ "extend_high_u_I32x4_S\000"
5821 /* 24959 */ "trunc_sat_zero_u_I32x4_S\000"
5822 /* 24984 */ "extend_low_u_I32x4_S\000"
5823 /* 25005 */ "ARGUMENT_v8f16_S\000"
5824 /* 25022 */ "ARGUMENT_v8i16_S\000"
5825 /* 25039 */ "CONST_V128_I8x16_S\000"
5826 /* 25058 */ "SUB_I8x16_S\000"
5827 /* 25070 */ "ADD_I8x16_S\000"
5828 /* 25082 */ "REPLACE_LANE_I8x16_S\000"
5829 /* 25103 */ "ALLTRUE_I8x16_S\000"
5830 /* 25119 */ "NEG_I8x16_S\000"
5831 /* 25131 */ "BITMASK_I8x16_S\000"
5832 /* 25147 */ "SHL_I8x16_S\000"
5833 /* 25159 */ "EQ_I8x16_S\000"
5834 /* 25170 */ "ABS_I8x16_S\000"
5835 /* 25182 */ "GE_S_I8x16_S\000"
5836 /* 25195 */ "LE_S_I8x16_S\000"
5837 /* 25208 */ "MIN_S_I8x16_S\000"
5838 /* 25222 */ "SHR_S_I8x16_S\000"
5839 /* 25236 */ "SUB_SAT_S_I8x16_S\000"
5840 /* 25254 */ "ADD_SAT_S_I8x16_S\000"
5841 /* 25272 */ "GT_S_I8x16_S\000"
5842 /* 25285 */ "LT_S_I8x16_S\000"
5843 /* 25298 */ "NARROW_S_I8x16_S\000"
5844 /* 25315 */ "MAX_S_I8x16_S\000"
5845 /* 25329 */ "SPLAT_I8x16_S\000"
5846 /* 25343 */ "LANESELECT_I8x16_S\000"
5847 /* 25362 */ "POPCNT_I8x16_S\000"
5848 /* 25377 */ "GE_U_I8x16_S\000"
5849 /* 25390 */ "LE_U_I8x16_S\000"
5850 /* 25403 */ "MIN_U_I8x16_S\000"
5851 /* 25417 */ "AVGR_U_I8x16_S\000"
5852 /* 25432 */ "SHR_U_I8x16_S\000"
5853 /* 25446 */ "SUB_SAT_U_I8x16_S\000"
5854 /* 25464 */ "ADD_SAT_U_I8x16_S\000"
5855 /* 25482 */ "GT_U_I8x16_S\000"
5856 /* 25495 */ "LT_U_I8x16_S\000"
5857 /* 25508 */ "NARROW_U_I8x16_S\000"
5858 /* 25525 */ "MAX_U_I8x16_S\000"
5859 /* 25539 */ "I64_SUB128_S\000"
5860 /* 25552 */ "I64_ADD128_S\000"
5861 /* 25565 */ "LOCAL_TEE_V128_S\000"
5862 /* 25582 */ "DROP_V128_S\000"
5863 /* 25594 */ "SELECT_V128_S\000"
5864 /* 25608 */ "GLOBAL_GET_V128_S\000"
5865 /* 25626 */ "LOCAL_GET_V128_S\000"
5866 /* 25643 */ "GLOBAL_SET_V128_S\000"
5867 /* 25661 */ "LOCAL_SET_V128_S\000"
5868 /* 25678 */ "COPY_V128_S\000"
5869 /* 25690 */ "ARGUMENT_v16i8_S\000"
5870 /* 25707 */ "SUB_F16x8_S\000"
5871 /* 25719 */ "TRUNC_F16x8_S\000"
5872 /* 25733 */ "NMADD_F16x8_S\000"
5873 /* 25747 */ "GE_F16x8_S\000"
5874 /* 25758 */ "LE_F16x8_S\000"
5875 /* 25769 */ "REPLACE_LANE_F16x8_S\000"
5876 /* 25790 */ "EXTRACT_LANE_F16x8_S\000"
5877 /* 25811 */ "NEG_F16x8_S\000"
5878 /* 25823 */ "CEIL_F16x8_S\000"
5879 /* 25836 */ "MUL_F16x8_S\000"
5880 /* 25848 */ "PMIN_F16x8_S\000"
5881 /* 25861 */ "EQ_F16x8_S\000"
5882 /* 25872 */ "FLOOR_F16x8_S\000"
5883 /* 25886 */ "ABS_F16x8_S\000"
5884 /* 25898 */ "SPLAT_F16x8_S\000"
5885 /* 25912 */ "GT_F16x8_S\000"
5886 /* 25923 */ "LT_F16x8_S\000"
5887 /* 25934 */ "SQRT_F16x8_S\000"
5888 /* 25947 */ "NEAREST_F16x8_S\000"
5889 /* 25963 */ "DIV_F16x8_S\000"
5890 /* 25975 */ "PMAX_F16x8_S\000"
5891 /* 25988 */ "demote_zero_F16x8_S\000"
5892 /* 26008 */ "sint_to_fp_F16x8_S\000"
5893 /* 26027 */ "uint_to_fp_F16x8_S\000"
5894 /* 26046 */ "CONST_V128_I16x8_S\000"
5895 /* 26065 */ "SUB_I16x8_S\000"
5896 /* 26077 */ "ADD_I16x8_S\000"
5897 /* 26089 */ "REPLACE_LANE_I16x8_S\000"
5898 /* 26110 */ "ALLTRUE_I16x8_S\000"
5899 /* 26126 */ "NEG_I16x8_S\000"
5900 /* 26138 */ "BITMASK_I16x8_S\000"
5901 /* 26154 */ "SHL_I16x8_S\000"
5902 /* 26166 */ "MUL_I16x8_S\000"
5903 /* 26178 */ "EQ_I16x8_S\000"
5904 /* 26189 */ "ABS_I16x8_S\000"
5905 /* 26201 */ "GE_S_I16x8_S\000"
5906 /* 26214 */ "LE_S_I16x8_S\000"
5907 /* 26227 */ "EXTMUL_HIGH_S_I16x8_S\000"
5908 /* 26249 */ "MIN_S_I16x8_S\000"
5909 /* 26263 */ "SHR_S_I16x8_S\000"
5910 /* 26277 */ "RELAXED_Q15MULR_S_I16x8_S\000"
5911 /* 26303 */ "SUB_SAT_S_I16x8_S\000"
5912 /* 26321 */ "ADD_SAT_S_I16x8_S\000"
5913 /* 26339 */ "Q15MULR_SAT_S_I16x8_S\000"
5914 /* 26361 */ "GT_S_I16x8_S\000"
5915 /* 26374 */ "LT_S_I16x8_S\000"
5916 /* 26387 */ "EXTMUL_LOW_S_I16x8_S\000"
5917 /* 26408 */ "NARROW_S_I16x8_S\000"
5918 /* 26425 */ "MAX_S_I16x8_S\000"
5919 /* 26439 */ "SPLAT_I16x8_S\000"
5920 /* 26453 */ "LANESELECT_I16x8_S\000"
5921 /* 26472 */ "GE_U_I16x8_S\000"
5922 /* 26485 */ "LE_U_I16x8_S\000"
5923 /* 26498 */ "EXTMUL_HIGH_U_I16x8_S\000"
5924 /* 26520 */ "MIN_U_I16x8_S\000"
5925 /* 26534 */ "AVGR_U_I16x8_S\000"
5926 /* 26549 */ "SHR_U_I16x8_S\000"
5927 /* 26563 */ "SUB_SAT_U_I16x8_S\000"
5928 /* 26581 */ "ADD_SAT_U_I16x8_S\000"
5929 /* 26599 */ "GT_U_I16x8_S\000"
5930 /* 26612 */ "LT_U_I16x8_S\000"
5931 /* 26625 */ "EXTMUL_LOW_U_I16x8_S\000"
5932 /* 26646 */ "NARROW_U_I16x8_S\000"
5933 /* 26663 */ "MAX_U_I16x8_S\000"
5934 /* 26677 */ "extadd_pairwise_s_I16x8_S\000"
5935 /* 26703 */ "extend_high_s_I16x8_S\000"
5936 /* 26725 */ "extend_low_s_I16x8_S\000"
5937 /* 26746 */ "fp_to_sint_I16x8_S\000"
5938 /* 26765 */ "fp_to_uint_I16x8_S\000"
5939 /* 26784 */ "extadd_pairwise_u_I16x8_S\000"
5940 /* 26810 */ "extend_high_u_I16x8_S\000"
5941 /* 26832 */ "extend_low_u_I16x8_S\000"
5942 /* 26853 */ "REF_FUNC_S\000"
5943 /* 26864 */ "RELAXED_DOT_ADD_S\000"
5944 /* 26882 */ "AND_S\000"
5945 /* 26888 */ "END_S\000"
5946 /* 26894 */ "ATOMIC_FENCE_S\000"
5947 /* 26909 */ "COMPILER_FENCE_S\000"
5948 /* 26926 */ "I64_MUL_WIDE_S\000"
5949 /* 26941 */ "DEBUG_UNREACHABLE_S\000"
5950 /* 26961 */ "END_TRY_TABLE_S\000"
5951 /* 26977 */ "SHUFFLE_S\000"
5952 /* 26987 */ "RELAXED_SWIZZLE_S\000"
5953 /* 27005 */ "ELSE_S\000"
5954 /* 27012 */ "DELEGATE_S\000"
5955 /* 27023 */ "ANYTRUE_S\000"
5956 /* 27033 */ "TABLE_SIZE_S\000"
5957 /* 27046 */ "LOCAL_TEE_FUNCREF_S\000"
5958 /* 27066 */ "TABLE_FILL_FUNCREF_S\000"
5959 /* 27087 */ "REF_NULL_FUNCREF_S\000"
5960 /* 27106 */ "REF_IS_NULL_FUNCREF_S\000"
5961 /* 27128 */ "DROP_FUNCREF_S\000"
5962 /* 27143 */ "SELECT_FUNCREF_S\000"
5963 /* 27160 */ "TABLE_GET_FUNCREF_S\000"
5964 /* 27180 */ "GLOBAL_GET_FUNCREF_S\000"
5965 /* 27201 */ "LOCAL_GET_FUNCREF_S\000"
5966 /* 27221 */ "TABLE_SET_FUNCREF_S\000"
5967 /* 27241 */ "GLOBAL_SET_FUNCREF_S\000"
5968 /* 27262 */ "LOCAL_SET_FUNCREF_S\000"
5969 /* 27282 */ "REF_CAST_FUNCREF_S\000"
5970 /* 27301 */ "REF_TEST_FUNCREF_S\000"
5971 /* 27320 */ "TABLE_GROW_FUNCREF_S\000"
5972 /* 27341 */ "COPY_FUNCREF_S\000"
5973 /* 27356 */ "LOCAL_TEE_EXTERNREF_S\000"
5974 /* 27378 */ "TABLE_FILL_EXTERNREF_S\000"
5975 /* 27401 */ "REF_NULL_EXTERNREF_S\000"
5976 /* 27422 */ "REF_IS_NULL_EXTERNREF_S\000"
5977 /* 27446 */ "DROP_EXTERNREF_S\000"
5978 /* 27463 */ "SELECT_EXTERNREF_S\000"
5979 /* 27482 */ "TABLE_GET_EXTERNREF_S\000"
5980 /* 27504 */ "GLOBAL_GET_EXTERNREF_S\000"
5981 /* 27527 */ "LOCAL_GET_EXTERNREF_S\000"
5982 /* 27549 */ "TABLE_SET_EXTERNREF_S\000"
5983 /* 27571 */ "GLOBAL_SET_EXTERNREF_S\000"
5984 /* 27594 */ "LOCAL_SET_EXTERNREF_S\000"
5985 /* 27616 */ "TABLE_GROW_EXTERNREF_S\000"
5986 /* 27639 */ "COPY_EXTERNREF_S\000"
5987 /* 27656 */ "LOCAL_TEE_EXNREF_S\000"
5988 /* 27675 */ "TABLE_FILL_EXNREF_S\000"
5989 /* 27695 */ "REF_NULL_EXNREF_S\000"
5990 /* 27713 */ "REF_IS_NULL_EXNREF_S\000"
5991 /* 27734 */ "DROP_EXNREF_S\000"
5992 /* 27748 */ "SELECT_EXNREF_S\000"
5993 /* 27764 */ "TABLE_GET_EXNREF_S\000"
5994 /* 27783 */ "GLOBAL_GET_EXNREF_S\000"
5995 /* 27803 */ "LOCAL_GET_EXNREF_S\000"
5996 /* 27822 */ "TABLE_SET_EXNREF_S\000"
5997 /* 27841 */ "GLOBAL_SET_EXNREF_S\000"
5998 /* 27861 */ "LOCAL_SET_EXNREF_S\000"
5999 /* 27880 */ "TABLE_GROW_EXNREF_S\000"
6000 /* 27900 */ "COPY_EXNREF_S\000"
6001 /* 27914 */ "CATCH_REF_S\000"
6002 /* 27926 */ "RET_CALL_REF_S\000"
6003 /* 27941 */ "CATCH_ALL_REF_S\000"
6004 /* 27957 */ "THROW_REF_S\000"
6005 /* 27969 */ "END_IF_S\000"
6006 /* 27978 */ "BR_IF_S\000"
6007 /* 27986 */ "CATCH_S\000"
6008 /* 27994 */ "END_BLOCK_S\000"
6009 /* 28006 */ "RET_CALL_S\000"
6010 /* 28017 */ "CATCH_ALL_S\000"
6011 /* 28029 */ "END_FUNCTION_S\000"
6012 /* 28044 */ "FALLTHROUGH_RETURN_S\000"
6013 /* 28065 */ "ADJCALLSTACKDOWN_S\000"
6014 /* 28084 */ "NOP_S\000"
6015 /* 28090 */ "END_LOOP_S\000"
6016 /* 28101 */ "DATA_DROP_S\000"
6017 /* 28113 */ "ADJCALLSTACKUP_S\000"
6018 /* 28130 */ "BR_S\000"
6019 /* 28135 */ "XOR_S\000"
6020 /* 28141 */ "CALL_PARAMS_S\000"
6021 /* 28155 */ "BR_UNLESS_S\000"
6022 /* 28167 */ "RET_CALL_RESULTS_S\000"
6023 /* 28186 */ "I64_MUL_WIDE_S_S\000"
6024 /* 28203 */ "RELAXED_DOT_BFLOAT_S\000"
6025 /* 28224 */ "G_TRUNC_SSAT_S\000"
6026 /* 28239 */ "BITSELECT_S\000"
6027 /* 28251 */ "RET_CALL_INDIRECT_S\000"
6028 /* 28271 */ "CATCHRET_S\000"
6029 /* 28282 */ "CLEANUPRET_S\000"
6030 /* 28295 */ "RELAXED_DOT_S\000"
6031 /* 28309 */ "ANDNOT_S\000"
6032 /* 28318 */ "SELECT_T_S\000"
6033 /* 28329 */ "I64_MUL_WIDE_U_S\000"
6034 /* 28346 */ "RETHROW_S\000"
6035 /* 28356 */ "CATCH_LEGACY_S\000"
6036 /* 28371 */ "CATCH_ALL_LEGACY_S\000"
6037 /* 28390 */ "TABLE_COPY_S\000"
6038 /* 28403 */ "END_TRY_S\000"
6039 /* 28413 */ "ARGUMENT_funcref_S\000"
6040 /* 28432 */ "ARGUMENT_externref_S\000"
6041 /* 28453 */ "ARGUMENT_exnref_S\000"
6042 /* 28471 */ "EXTRACT_LANE_I8x16_s_S\000"
6043 /* 28494 */ "EXTRACT_LANE_I16x8_s_S\000"
6044 /* 28517 */ "EXTRACT_LANE_I8x16_u_S\000"
6045 /* 28540 */ "EXTRACT_LANE_I16x8_u_S\000"
6046 /* 28563 */ "RELAXED_DOT_BFLOAT\000"
6047 /* 28582 */ "G_SSUBSAT\000"
6048 /* 28592 */ "G_USUBSAT\000"
6049 /* 28602 */ "G_SADDSAT\000"
6050 /* 28612 */ "G_UADDSAT\000"
6051 /* 28622 */ "G_SSHLSAT\000"
6052 /* 28632 */ "G_USHLSAT\000"
6053 /* 28642 */ "G_SMULFIXSAT\000"
6054 /* 28655 */ "G_UMULFIXSAT\000"
6055 /* 28668 */ "G_SDIVFIXSAT\000"
6056 /* 28681 */ "G_UDIVFIXSAT\000"
6057 /* 28694 */ "G_ATOMICRMW_USUB_SAT\000"
6058 /* 28715 */ "G_FPTOSI_SAT\000"
6059 /* 28728 */ "G_FPTOUI_SAT\000"
6060 /* 28741 */ "G_EXTRACT\000"
6061 /* 28751 */ "BITSELECT\000"
6062 /* 28761 */ "G_SELECT\000"
6063 /* 28770 */ "G_BRINDIRECT\000"
6064 /* 28783 */ "RET_CALL_INDIRECT\000"
6065 /* 28801 */ "CATCHRET\000"
6066 /* 28810 */ "CLEANUPRET\000"
6067 /* 28821 */ "PATCHABLE_RET\000"
6068 /* 28835 */ "G_MEMSET\000"
6069 /* 28844 */ "PATCHABLE_FUNCTION_EXIT\000"
6070 /* 28868 */ "G_BRJT\000"
6071 /* 28875 */ "G_EXTRACT_VECTOR_ELT\000"
6072 /* 28896 */ "G_INSERT_VECTOR_ELT\000"
6073 /* 28916 */ "G_FCONSTANT\000"
6074 /* 28928 */ "G_CONSTANT\000"
6075 /* 28939 */ "G_INTRINSIC_CONVERGENT\000"
6076 /* 28962 */ "STATEPOINT\000"
6077 /* 28973 */ "PATCHPOINT\000"
6078 /* 28984 */ "G_PTRTOINT\000"
6079 /* 28995 */ "G_FRINT\000"
6080 /* 29003 */ "G_INTRINSIC_LLRINT\000"
6081 /* 29022 */ "G_INTRINSIC_LRINT\000"
6082 /* 29040 */ "G_FNEARBYINT\000"
6083 /* 29053 */ "RELAXED_DOT\000"
6084 /* 29065 */ "ANDNOT\000"
6085 /* 29072 */ "G_VASTART\000"
6086 /* 29082 */ "LIFETIME_START\000"
6087 /* 29097 */ "G_INVOKE_REGION_START\000"
6088 /* 29119 */ "G_INSERT\000"
6089 /* 29128 */ "G_FSQRT\000"
6090 /* 29136 */ "G_STRICT_FSQRT\000"
6091 /* 29151 */ "G_BITCAST\000"
6092 /* 29161 */ "G_ADDRSPACE_CAST\000"
6093 /* 29178 */ "DBG_VALUE_LIST\000"
6094 /* 29193 */ "G_FPEXT\000"
6095 /* 29201 */ "G_SEXT\000"
6096 /* 29208 */ "G_ASSERT_SEXT\000"
6097 /* 29222 */ "G_ANYEXT\000"
6098 /* 29231 */ "G_ZEXT\000"
6099 /* 29238 */ "G_ASSERT_ZEXT\000"
6100 /* 29252 */ "SELECT_T\000"
6101 /* 29261 */ "G_ABDU\000"
6102 /* 29268 */ "I64_MUL_WIDE_U\000"
6103 /* 29283 */ "G_TRUNC_SSAT_U\000"
6104 /* 29298 */ "G_TRUNC_USAT_U\000"
6105 /* 29313 */ "G_FDIV\000"
6106 /* 29320 */ "G_STRICT_FDIV\000"
6107 /* 29334 */ "G_SDIV\000"
6108 /* 29341 */ "G_UDIV\000"
6109 /* 29348 */ "G_GET_FPENV\000"
6110 /* 29360 */ "G_RESET_FPENV\000"
6111 /* 29374 */ "G_SET_FPENV\000"
6112 /* 29386 */ "G_FPOW\000"
6113 /* 29393 */ "RETHROW\000"
6114 /* 29401 */ "G_VECREDUCE_FMAX\000"
6115 /* 29418 */ "G_ATOMICRMW_FMAX\000"
6116 /* 29435 */ "G_VECREDUCE_SMAX\000"
6117 /* 29452 */ "G_SMAX\000"
6118 /* 29459 */ "G_VECREDUCE_UMAX\000"
6119 /* 29476 */ "G_UMAX\000"
6120 /* 29483 */ "G_ATOMICRMW_UMAX\000"
6121 /* 29500 */ "G_ATOMICRMW_MAX\000"
6122 /* 29516 */ "G_FRAME_INDEX\000"
6123 /* 29530 */ "G_SBFX\000"
6124 /* 29537 */ "G_UBFX\000"
6125 /* 29544 */ "G_SMULFIX\000"
6126 /* 29554 */ "G_UMULFIX\000"
6127 /* 29564 */ "G_SDIVFIX\000"
6128 /* 29574 */ "G_UDIVFIX\000"
6129 /* 29584 */ "CATCH_LEGACY\000"
6130 /* 29597 */ "CATCH_ALL_LEGACY\000"
6131 /* 29614 */ "G_MEMCPY\000"
6132 /* 29623 */ "TABLE_COPY\000"
6133 /* 29634 */ "CONVERGENCECTRL_ENTRY\000"
6134 /* 29656 */ "END_TRY\000"
6135 /* 29664 */ "G_CTLZ\000"
6136 /* 29671 */ "G_CTTZ\000"
6137 /* 29678 */ "ARGUMENT_funcref\000"
6138 /* 29695 */ "ARGUMENT_externref\000"
6139 /* 29714 */ "ARGUMENT_exnref\000"
6140 /* 29730 */ "EXTRACT_LANE_I8x16_s\000"
6141 /* 29751 */ "EXTRACT_LANE_I16x8_s\000"
6142 /* 29772 */ "EXTRACT_LANE_I8x16_u\000"
6143 /* 29793 */ "EXTRACT_LANE_I16x8_u\000"
6144};
6145#ifdef __GNUC__
6146#pragma GCC diagnostic pop
6147#endif
6148
6149extern const unsigned WebAssemblyInstrNameIndices[] = {
6150 12867U, 13310U, 14254U, 13777U, 12950U, 12931U, 12959U, 13138U,
6151 12654U, 12669U, 11780U, 11767U, 12696U, 14808U, 11624U, 29178U,
6152 12610U, 12863U, 12940U, 11293U, 29629U, 12907U, 11447U, 29082U,
6153 11092U, 11216U, 11266U, 13945U, 13116U, 28973U, 11199U, 14189U,
6154 12789U, 28962U, 11521U, 14162U, 14149U, 14315U, 28821U, 28844U,
6155 13039U, 13095U, 13068U, 12976U, 11606U, 14280U, 13899U, 11510U,
6156 29634U, 14433U, 14110U, 11672U, 29208U, 29238U, 13607U, 10989U,
6157 10679U, 13249U, 29334U, 29341U, 13276U, 13283U, 13290U, 13300U,
6158 11070U, 14642U, 14605U, 14693U, 29261U, 14477U, 13028U, 14465U,
6159 13017U, 11778U, 12865U, 29516U, 11634U, 11649U, 13143U, 28741U,
6160 14700U, 29119U, 14717U, 14528U, 10758U, 14791U, 28984U, 14669U,
6161 29151U, 11723U, 14291U, 11173U, 10732U, 11155U, 29022U, 29003U,
6162 13585U, 14340U, 14359U, 10890U, 10834U, 10864U, 10803U, 10875U,
6163 10815U, 10845U, 11580U, 11534U, 11564U, 14838U, 12710U, 12727U,
6164 11021U, 10685U, 11076U, 11037U, 14647U, 14611U, 29500U, 13733U,
6165 29483U, 13716U, 10956U, 10662U, 29418U, 13651U, 13405U, 13352U,
6166 13526U, 13464U, 14007U, 13985U, 11114U, 28694U, 11258U, 12812U,
6167 11105U, 28770U, 29097U, 10701U, 14896U, 28939U, 14923U, 29222U,
6168 10750U, 28224U, 29283U, 29298U, 28928U, 28916U, 29072U, 12781U,
6169 29201U, 12683U, 29231U, 13003U, 14426U, 14412U, 12996U, 14419U,
6170 14662U, 13159U, 14076U, 14055U, 14083U, 14090U, 28761U, 13891U,
6171 11314U, 13875U, 11237U, 13883U, 11306U, 13867U, 11229U, 13929U,
6172 13921U, 12831U, 12823U, 28612U, 28602U, 28592U, 28582U, 28632U,
6173 28622U, 29544U, 29554U, 28642U, 28655U, 29564U, 29574U, 28668U,
6174 28681U, 10914U, 10641U, 13183U, 10622U, 10796U, 29313U, 13255U,
6175 11759U, 29386U, 12889U, 14233U, 3559U, 9U, 12774U, 3542U,
6176 0U, 14208U, 14240U, 12647U, 29193U, 10722U, 12871U, 12880U,
6177 14037U, 14046U, 28715U, 28728U, 14680U, 13622U, 14825U, 11732U,
6178 13550U, 13560U, 11363U, 11378U, 13341U, 13394U, 13450U, 13512U,
6179 29348U, 29374U, 29360U, 11322U, 11350U, 11335U, 12744U, 12759U,
6180 10995U, 12921U, 13685U, 29452U, 13709U, 29476U, 14687U, 11146U,
6181 11136U, 14249U, 28868U, 11393U, 14509U, 14489U, 28896U, 28875U,
6182 14543U, 14574U, 14560U, 14878U, 29671U, 13812U, 29664U, 13793U,
6183 14732U, 14131U, 14029U, 11593U, 13225U, 13009U, 14759U, 13757U,
6184 14766U, 13578U, 14751U, 13749U, 13570U, 3550U, 12855U, 12847U,
6185 12839U, 29128U, 14456U, 28995U, 29040U, 29161U, 14267U, 11420U,
6186 10779U, 11701U, 11549U, 10942U, 10648U, 13211U, 29320U, 13262U,
6187 10628U, 29136U, 14217U, 14062U, 14776U, 14379U, 14395U, 29614U,
6188 11494U, 11713U, 28835U, 13937U, 11478U, 13978U, 13954U, 13966U,
6189 10921U, 13190U, 10897U, 13166U, 29401U, 13634U, 13373U, 13320U,
6190 13488U, 13426U, 10973U, 13233U, 11054U, 14627U, 14589U, 29435U,
6191 13668U, 29459U, 13692U, 29530U, 29537U, 14739U, 28141U, 14965U,
6192 28171U, 28801U, 28271U, 28810U, 28282U, 11278U, 26909U, 14961U,
6193 28167U, 9773U, 25886U, 2641U, 17853U, 8049U, 23924U, 6956U,
6194 22653U, 3761U, 19126U, 10034U, 26189U, 8371U, 24294U, 4071U,
6195 19482U, 9155U, 25170U, 9644U, 25735U, 2510U, 17694U, 7896U,
6196 23747U, 6826U, 22495U, 3608U, 18949U, 9938U, 26077U, 2960U,
6197 18220U, 8256U, 24161U, 7275U, 23020U, 3956U, 19349U, 9069U,
6198 25070U, 10150U, 26321U, 9227U, 25254U, 10378U, 26581U, 9409U,
6199 25464U, 13850U, 28065U, 14174U, 28113U, 9967U, 26110U, 8304U,
6200 24215U, 4004U, 19403U, 9098U, 25103U, 11050U, 29065U, 28309U,
6201 2968U, 18230U, 7283U, 23030U, 26882U, 11693U, 27023U, 29714U,
6202 28453U, 29695U, 28432U, 3501U, 18855U, 7814U, 23653U, 29678U,
6203 28413U, 3529U, 18887U, 7842U, 23685U, 9605U, 25690U, 7799U,
6204 23636U, 7827U, 23668U, 3486U, 18838U, 3514U, 18870U, 9012U,
6205 25005U, 9027U, 25022U, 11245U, 26894U, 743U, 15765U, 5059U,
6206 20566U, 1865U, 16981U, 6181U, 21782U, 1841U, 16955U, 6157U,
6207 21756U, 767U, 15791U, 5083U, 20592U, 1889U, 17007U, 6205U,
6208 21808U, 201U, 15179U, 4517U, 19980U, 1116U, 16172U, 5432U,
6209 20973U, 221U, 15201U, 4537U, 20002U, 1163U, 16223U, 5479U,
6210 21024U, 297U, 15283U, 4613U, 20084U, 1266U, 16334U, 5582U,
6211 21135U, 394U, 15388U, 4710U, 20189U, 1394U, 16472U, 5710U,
6212 21273U, 637U, 15649U, 4953U, 20450U, 1718U, 16820U, 6034U,
6213 21621U, 125U, 15097U, 4441U, 19898U, 1040U, 16090U, 5356U,
6214 20891U, 482U, 15482U, 4798U, 20283U, 1510U, 16596U, 5826U,
6215 21397U, 561U, 15567U, 4877U, 20368U, 1616U, 16710U, 5932U,
6216 21511U, 1136U, 16194U, 5452U, 20995U, 1239U, 16305U, 5555U,
6217 21106U, 1363U, 16439U, 5679U, 21240U, 1692U, 16792U, 6008U,
6218 21593U, 1013U, 16061U, 5329U, 20862U, 1482U, 16566U, 5798U,
6219 21367U, 1589U, 16681U, 5905U, 21482U, 248U, 15230U, 4564U,
6220 20031U, 1190U, 16252U, 5506U, 21053U, 324U, 15312U, 4640U,
6221 20113U, 1293U, 16363U, 5609U, 21164U, 425U, 15421U, 4741U,
6222 20222U, 1425U, 16505U, 5741U, 21306U, 663U, 15677U, 4979U,
6223 20478U, 1744U, 16848U, 6060U, 21649U, 152U, 15126U, 4468U,
6224 19927U, 1067U, 16119U, 5383U, 20920U, 510U, 15512U, 4826U,
6225 20313U, 1538U, 16626U, 5854U, 21427U, 588U, 15596U, 4904U,
6226 20397U, 1643U, 16739U, 5959U, 21540U, 274U, 15258U, 4590U,
6227 20059U, 1216U, 16280U, 5532U, 21081U, 350U, 15340U, 4666U,
6228 20141U, 1319U, 16391U, 5635U, 21192U, 455U, 15453U, 4771U,
6229 20254U, 1455U, 16537U, 5771U, 21338U, 688U, 15704U, 5004U,
6230 20505U, 1769U, 16875U, 6085U, 21676U, 178U, 15154U, 4494U,
6231 19955U, 1093U, 16147U, 5409U, 20948U, 537U, 15541U, 4853U,
6232 20342U, 1565U, 16655U, 5881U, 21456U, 614U, 15624U, 4930U,
6233 20425U, 1669U, 16767U, 5985U, 21568U, 80U, 15048U, 4396U,
6234 19849U, 968U, 16012U, 5284U, 20813U, 945U, 15987U, 5261U,
6235 20788U, 103U, 15073U, 4419U, 19874U, 991U, 16037U, 5307U,
6236 20838U, 373U, 15365U, 4689U, 20166U, 1342U, 16416U, 5658U,
6237 21217U, 10337U, 26534U, 9368U, 25417U, 9991U, 26138U, 8328U,
6238 24243U, 4028U, 19431U, 9122U, 25131U, 28751U, 28239U, 12901U,
6239 27998U, 14251U, 12641U, 27978U, 28130U, 2990U, 18256U, 7305U,
6240 23056U, 14868U, 28155U, 13054U, 28787U, 28255U, 12587U, 27930U,
6241 28010U, 12806U, 13128U, 29597U, 28371U, 12596U, 27941U, 28017U,
6242 29584U, 28356U, 12573U, 27914U, 27986U, 9720U, 25823U, 2577U,
6243 17775U, 7972U, 23835U, 6892U, 22575U, 3684U, 19037U, 3462U,
6244 18808U, 7775U, 23606U, 2885U, 18131U, 7200U, 22931U, 3324U,
6245 18646U, 7654U, 23463U, 7855U, 23700U, 3567U, 18902U, 9911U,
6246 26046U, 8229U, 24130U, 3929U, 19318U, 9042U, 25039U, 2594U,
6247 17796U, 6909U, 22596U, 12561U, 27900U, 12328U, 27639U, 2943U,
6248 18199U, 7258U, 22999U, 12058U, 27341U, 3453U, 18797U, 7766U,
6249 23595U, 9595U, 25678U, 3478U, 18828U, 7791U, 23626U, 14139U,
6250 28101U, 11402U, 26941U, 11615U, 27012U, 9838U, 25963U, 2927U,
6251 18179U, 8114U, 24001U, 7242U, 22979U, 3826U, 19203U, 3214U,
6252 18520U, 7544U, 23337U, 3443U, 18785U, 7756U, 23583U, 29061U,
6253 28303U, 12413U, 27734U, 12153U, 27446U, 2615U, 17821U, 6930U,
6254 22621U, 11867U, 27128U, 3035U, 18311U, 7363U, 23126U, 9511U,
6255 25582U, 11588U, 27005U, 11101U, 12897U, 27994U, 13764U, 28029U,
6256 12634U, 27969U, 14101U, 28090U, 26888U, 29656U, 28403U, 11433U,
6257 26961U, 3470U, 18818U, 7783U, 23616U, 9752U, 25861U, 2624U,
6258 17832U, 8028U, 23899U, 6939U, 22632U, 3740U, 19101U, 10025U,
6259 26178U, 3044U, 18322U, 8362U, 24283U, 7372U, 23137U, 4062U,
6260 19471U, 9146U, 25159U, 10066U, 26227U, 8403U, 24332U, 4103U,
6261 19520U, 10305U, 26498U, 8551U, 24502U, 4205U, 19636U, 10208U,
6262 26387U, 8469U, 24408U, 4157U, 19582U, 10416U, 26625U, 8617U,
6263 24578U, 4237U, 19672U, 9691U, 25790U, 7943U, 23802U, 3655U,
6264 19004U, 29751U, 28494U, 29793U, 28540U, 8285U, 24194U, 3985U,
6265 19382U, 29730U, 28471U, 29772U, 28517U, 3178U, 18480U, 7508U,
6266 23297U, 3407U, 18745U, 7720U, 23543U, 6869U, 22548U, 3264U,
6267 18578U, 3196U, 18500U, 7526U, 23317U, 3425U, 18765U, 7738U,
6268 23563U, 2553U, 17747U, 7594U, 23395U, 13831U, 28044U, 9761U,
6269 25872U, 2631U, 17841U, 8037U, 23910U, 6946U, 22641U, 3749U,
6270 19112U, 2416U, 17588U, 6732U, 22389U, 2454U, 17630U, 6770U,
6271 22431U, 2435U, 17609U, 6751U, 22410U, 2473U, 17651U, 6789U,
6272 22452U, 9654U, 25747U, 2532U, 17720U, 7906U, 23759U, 6848U,
6273 22521U, 3618U, 18961U, 10044U, 26201U, 3122U, 18412U, 8381U,
6274 24306U, 7452U, 23229U, 4081U, 19494U, 9165U, 25182U, 10283U,
6275 26472U, 3351U, 18677U, 8529U, 24476U, 7664U, 23475U, 9334U,
6276 25377U, 12456U, 27783U, 12205U, 27504U, 2772U, 18000U, 7087U,
6277 22800U, 11913U, 27180U, 3235U, 18545U, 7565U, 23362U, 9533U,
6278 25608U, 12508U, 27841U, 12266U, 27571U, 2821U, 18055U, 7136U,
6279 22855U, 11968U, 27241U, 3284U, 18600U, 7614U, 23417U, 9564U,
6280 25643U, 9795U, 25912U, 2850U, 18088U, 8071U, 23950U, 7165U,
6281 22888U, 3783U, 19152U, 10186U, 26361U, 3160U, 18458U, 8447U,
6282 24382U, 7490U, 23275U, 4135U, 19556U, 9243U, 25272U, 10394U,
6283 26599U, 3389U, 18723U, 8595U, 24552U, 7702U, 23521U, 9425U,
6284 25482U, 3068U, 18352U, 3087U, 18373U, 2801U, 18033U, 2649U,
6285 17863U, 6964U, 22663U, 2681U, 17899U, 6996U, 22699U, 2895U,
6286 18143U, 7210U, 22943U, 2721U, 17943U, 7036U, 22743U, 7350U,
6287 23111U, 9485U, 25552U, 7415U, 23188U, 7396U, 23167U, 7434U,
6288 23209U, 3105U, 18393U, 3334U, 18658U, 26926U, 28186U, 29268U,
6289 28329U, 7116U, 22833U, 9474U, 25539U, 2665U, 17881U, 6980U,
6290 22681U, 2701U, 17921U, 7016U, 22721U, 2911U, 18161U, 7226U,
6291 22961U, 2741U, 17965U, 7056U, 22765U, 12638U, 27973U, 10266U,
6292 26453U, 8512U, 24457U, 4188U, 19617U, 9304U, 25343U, 9663U,
6293 25758U, 2539U, 17729U, 7915U, 23770U, 6855U, 22530U, 3627U,
6294 18972U, 10055U, 26214U, 3131U, 18423U, 8392U, 24319U, 7461U,
6295 23240U, 4092U, 19507U, 9176U, 25195U, 10294U, 26485U, 3360U,
6296 18688U, 8540U, 24489U, 7673U, 23486U, 9345U, 25390U, 2273U,
6297 17429U, 6589U, 22230U, 710U, 15728U, 5026U, 20529U, 1808U,
6298 16918U, 6124U, 21719U, 750U, 15772U, 5066U, 20573U, 1872U,
6299 16988U, 6188U, 21789U, 2239U, 17391U, 6555U, 22192U, 1791U,
6300 16899U, 6107U, 21700U, 1848U, 16962U, 6164U, 21763U, 2256U,
6301 17410U, 6572U, 22211U, 2290U, 17448U, 6606U, 22249U, 727U,
6302 15747U, 5043U, 20548U, 1825U, 16937U, 6141U, 21738U, 774U,
6303 15798U, 5090U, 20599U, 1896U, 17014U, 6212U, 21815U, 2144U,
6304 17288U, 6460U, 22089U, 1992U, 17120U, 6308U, 21921U, 870U,
6305 15904U, 5186U, 20705U, 2168U, 17314U, 6484U, 22115U, 2016U,
6306 17146U, 6332U, 21947U, 894U, 15930U, 5210U, 20731U, 18U,
6307 14978U, 4334U, 19779U, 53U, 15017U, 4369U, 19818U, 918U,
6308 15956U, 5234U, 20757U, 208U, 15186U, 4524U, 19987U, 1123U,
6309 16179U, 5439U, 20980U, 2040U, 17172U, 6356U, 21973U, 815U,
6310 15843U, 5131U, 20644U, 1937U, 17059U, 6253U, 21860U, 2107U,
6311 17247U, 6423U, 22048U, 2078U, 17214U, 6394U, 22015U, 832U,
6312 15862U, 5148U, 20663U, 1954U, 17078U, 6270U, 21879U, 12474U,
6313 27803U, 12226U, 27527U, 2787U, 18017U, 7102U, 22817U, 11932U,
6314 27201U, 3250U, 18562U, 7580U, 23379U, 9549U, 25626U, 12526U,
6315 27861U, 12287U, 27594U, 2836U, 18072U, 7151U, 22872U, 11987U,
6316 27262U, 3299U, 18617U, 7629U, 23434U, 9580U, 25661U, 12343U,
6317 27656U, 12071U, 27356U, 2518U, 17704U, 6834U, 22505U, 11793U,
6318 27046U, 2976U, 18240U, 7291U, 23040U, 9496U, 25565U, 14105U,
6319 28094U, 9804U, 25923U, 2857U, 18097U, 8080U, 23961U, 7172U,
6320 22897U, 3792U, 19163U, 10197U, 26374U, 3169U, 18469U, 8458U,
6321 24395U, 7499U, 23286U, 4146U, 19569U, 9254U, 25285U, 10405U,
6322 26612U, 3398U, 18734U, 8606U, 24565U, 7711U, 23532U, 9436U,
6323 25495U, 9643U, 25734U, 7895U, 23746U, 3607U, 18948U, 9849U,
6324 25976U, 2935U, 18189U, 8138U, 24027U, 7250U, 22989U, 3850U,
6325 19229U, 10242U, 26425U, 8488U, 24429U, 9280U, 25315U, 10450U,
6326 26663U, 8636U, 24599U, 9462U, 25525U, 2389U, 17557U, 6705U,
6327 22358U, 2364U, 17530U, 6680U, 22331U, 790U, 15816U, 5106U,
6328 20617U, 1912U, 17032U, 6228U, 21833U, 2400U, 17570U, 6716U,
6329 22371U, 2223U, 17373U, 6539U, 22174U, 2317U, 17479U, 6633U,
6330 22280U, 2306U, 17466U, 6622U, 22267U, 9742U, 25849U, 2607U,
6331 17811U, 8007U, 23874U, 6922U, 22611U, 3719U, 19076U, 10086U,
6332 26249U, 8423U, 24354U, 9187U, 25208U, 10325U, 26520U, 8571U,
6333 24524U, 9356U, 25403U, 9731U, 25836U, 2586U, 17786U, 7983U,
6334 23848U, 6901U, 22586U, 3695U, 19050U, 10015U, 26166U, 3027U,
6335 18301U, 8352U, 24271U, 7342U, 23101U, 4052U, 19459U, 10227U,
6336 26408U, 9265U, 25298U, 10435U, 26646U, 9447U, 25508U, 9824U,
6337 25947U, 2873U, 18117U, 8100U, 23985U, 7188U, 22917U, 3812U,
6338 19187U, 9710U, 25811U, 2569U, 17765U, 7962U, 23823U, 6884U,
6339 22565U, 3674U, 19025U, 9981U, 26126U, 8318U, 24231U, 4018U,
6340 19419U, 9112U, 25119U, 9682U, 25779U, 2546U, 17738U, 7934U,
6341 23791U, 6862U, 22539U, 3646U, 18993U, 9958U, 26099U, 3003U,
6342 18271U, 8276U, 24183U, 7318U, 23071U, 3976U, 19371U, 9089U,
6343 25092U, 9642U, 25733U, 7894U, 23745U, 3606U, 18947U, 14097U,
6344 28084U, 29068U, 28312U, 14453U, 3052U, 18332U, 7380U, 23147U,
6345 28136U, 9848U, 25975U, 8148U, 24039U, 3860U, 19241U, 9741U,
6346 25848U, 8017U, 23886U, 3729U, 19088U, 3313U, 18633U, 7643U,
6347 23450U, 9321U, 25362U, 10166U, 26339U, 12005U, 27282U, 10713U,
6348 26853U, 12394U, 27713U, 12131U, 27422U, 11847U, 27106U, 12378U,
6349 27695U, 12112U, 27401U, 11830U, 27087U, 12022U, 27301U, 29053U,
6350 11005U, 26864U, 28563U, 28203U, 28295U, 10110U, 26277U, 11462U,
6351 26987U, 3140U, 18434U, 7470U, 23251U, 3369U, 18699U, 7682U,
6352 23497U, 9672U, 25769U, 7924U, 23781U, 3636U, 18983U, 9948U,
6353 26089U, 8266U, 24173U, 3966U, 19361U, 9079U, 25082U, 29393U,
6354 28346U, 13843U, 28056U, 13059U, 28783U, 28251U, 12583U, 27926U,
6355 28006U, 3018U, 18290U, 7333U, 23090U, 3059U, 18341U, 7387U,
6356 23156U, 12425U, 27748U, 12168U, 27463U, 2761U, 17987U, 7076U,
6357 22787U, 11880U, 27143U, 3224U, 18532U, 7554U, 23349U, 29252U,
6358 28318U, 9521U, 25594U, 10005U, 26154U, 3010U, 18280U, 8342U,
6359 24259U, 7325U, 23080U, 4042U, 19447U, 9136U, 25147U, 10098U,
6360 26263U, 3150U, 18446U, 8435U, 24368U, 7480U, 23263U, 4123U,
6361 19542U, 9199U, 25222U, 10350U, 26549U, 3379U, 18711U, 8583U,
6362 24538U, 7692U, 23509U, 4225U, 19658U, 9381U, 25432U, 11454U,
6363 26977U, 8124U, 24013U, 3836U, 19215U, 7993U, 23860U, 3705U,
6364 19062U, 9783U, 25898U, 8059U, 23936U, 3771U, 19138U, 10254U,
6365 26439U, 8500U, 24443U, 4176U, 19603U, 9292U, 25329U, 9813U,
6366 25934U, 2864U, 18106U, 8089U, 23972U, 7179U, 22906U, 3801U,
6367 19174U, 87U, 15055U, 4403U, 19856U, 975U, 16019U, 5291U,
6368 20820U, 952U, 15994U, 5268U, 20795U, 110U, 15080U, 4426U,
6369 19881U, 998U, 16044U, 5314U, 20845U, 35U, 14997U, 4351U,
6370 19798U, 66U, 15032U, 4382U, 19833U, 931U, 15971U, 5247U,
6371 20772U, 380U, 15372U, 4696U, 20173U, 1349U, 16423U, 5665U,
6372 21224U, 2123U, 17265U, 6439U, 22066U, 1971U, 17097U, 6287U,
6373 21898U, 849U, 15881U, 5165U, 20682U, 2057U, 17191U, 6373U,
6374 21992U, 2092U, 17230U, 6408U, 22031U, 9620U, 25707U, 2492U,
6375 17672U, 7872U, 23719U, 6808U, 22473U, 3584U, 18921U, 9928U,
6376 26065U, 2952U, 18210U, 8246U, 24149U, 7267U, 23010U, 3946U,
6377 19337U, 9059U, 25058U, 10134U, 26303U, 9211U, 25236U, 10362U,
6378 26563U, 9393U, 25446U, 11470U, 26995U, 29623U, 28390U, 12360U,
6379 27675U, 12091U, 27378U, 11811U, 27066U, 12439U, 27764U, 12185U,
6380 27482U, 11895U, 27160U, 12543U, 27880U, 12307U, 27616U, 12039U,
6381 27320U, 12491U, 27822U, 12246U, 27549U, 11950U, 27221U, 11748U,
6382 27033U, 12349U, 27662U, 12077U, 27362U, 2524U, 17710U, 6840U,
6383 22511U, 11799U, 27052U, 2982U, 18246U, 7297U, 23046U, 9502U,
6384 25571U, 29395U, 12624U, 27957U, 28348U, 9630U, 25719U, 2500U,
6385 17682U, 7882U, 23731U, 6816U, 22483U, 3594U, 18933U, 29652U,
6386 28407U, 11437U, 26965U, 11408U, 26947U, 14601U, 3051U, 18331U,
6387 7379U, 23146U, 28135U, 2333U, 17497U, 2192U, 17340U, 6649U,
6388 22298U, 6508U, 22141U, 3871U, 19254U, 3891U, 19276U, 9859U,
6389 25988U, 8159U, 24052U, 10462U, 26677U, 8806U, 24779U, 10559U,
6390 26784U, 8926U, 24911U, 10486U, 26703U, 8830U, 24805U, 4256U,
6391 19693U, 10583U, 26810U, 8950U, 24937U, 4295U, 19736U, 10506U,
6392 26725U, 8873U, 24852U, 4276U, 19715U, 10603U, 26832U, 8993U,
6393 24984U, 4315U, 19758U, 10525U, 26746U, 8892U, 24873U, 10542U,
6394 26765U, 8909U, 24892U, 8648U, 24613U, 8722U, 24691U, 8684U,
6395 24651U, 8763U, 24734U, 8211U, 24110U, 3911U, 19298U, 9877U,
6396 26008U, 8177U, 24072U, 8850U, 24827U, 8970U, 24959U, 9894U,
6397 26027U, 8194U, 24091U,
6398};
6399
6400extern const int16_t WebAssemblyRegClassByHwModeTables[2][1] = {
6401 { // DefaultMode
6402 WebAssembly::I32RegClassID, // wasm_ptr_rc
6403 },
6404 { // WASM64
6405 WebAssembly::I64RegClassID, // wasm_ptr_rc
6406 },
6407};
6408
6409static inline void InitWebAssemblyMCInstrInfo(MCInstrInfo *II) {
6410 II->InitMCInstrInfo(WebAssemblyDescs.Insts, WebAssemblyInstrNameIndices, WebAssemblyInstrNameData, nullptr, nullptr, 1979, &WebAssemblyRegClassByHwModeTables[0][0], 1);
6411}
6412
6413
6414} // namespace llvm
6415
6416#endif // GET_INSTRINFO_MC_DESC
6417
6418#ifdef GET_INSTRINFO_HEADER
6419#undef GET_INSTRINFO_HEADER
6420
6421namespace llvm {
6422
6423struct WebAssemblyGenInstrInfo : public TargetInstrInfo {
6424 explicit WebAssemblyGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
6425 ~WebAssemblyGenInstrInfo() override = default;
6426};
6427extern const int16_t WebAssemblyRegClassByHwModeTables[2][1];
6428
6429} // namespace llvm
6430
6431namespace llvm::WebAssembly {
6432
6433
6434} // namespace llvm::WebAssembly
6435
6436#endif // GET_INSTRINFO_HEADER
6437
6438#ifdef GET_INSTRINFO_HELPER_DECLS
6439#undef GET_INSTRINFO_HELPER_DECLS
6440
6441
6442#endif // GET_INSTRINFO_HELPER_DECLS
6443
6444#ifdef GET_INSTRINFO_HELPERS
6445#undef GET_INSTRINFO_HELPERS
6446
6447
6448#endif // GET_INSTRINFO_HELPERS
6449
6450#ifdef GET_INSTRINFO_CTOR_DTOR
6451#undef GET_INSTRINFO_CTOR_DTOR
6452
6453namespace llvm {
6454
6455extern const WebAssemblyInstrTable WebAssemblyDescs;
6456extern const unsigned WebAssemblyInstrNameIndices[];
6457extern const char WebAssemblyInstrNameData[];
6458WebAssemblyGenInstrInfo::WebAssemblyGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
6459 : TargetInstrInfo(TRI, CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode, WebAssemblyRegClassByHwModeTables[STI.getHwMode(MCSubtargetInfo::HwMode_RegInfo)]) {
6460 InitMCInstrInfo(WebAssemblyDescs.Insts, WebAssemblyInstrNameIndices, WebAssemblyInstrNameData, nullptr, nullptr, 1979, &WebAssemblyRegClassByHwModeTables[0][0], 1);
6461}
6462
6463} // namespace llvm
6464
6465#endif // GET_INSTRINFO_CTOR_DTOR
6466
6467#ifdef GET_INSTRINFO_OPERAND_ENUM
6468#undef GET_INSTRINFO_OPERAND_ENUM
6469
6470namespace llvm::WebAssembly {
6471
6472enum class OpName : uint8_t {
6473 dst = 0,
6474 order = 1,
6475 p2align = 2,
6476 off = 3,
6477 addr = 4,
6478 val = 5,
6479 exp = 6,
6480 new_ = 7,
6481 idx = 8,
6482 vec = 9,
6483 count = 10,
6484 timeout = 11,
6485 NUM_OPERAND_NAMES = 12,
6486}; // enum class OpName
6487
6488LLVM_READONLY int16_t getNamedOperandIdx(uint32_t Opcode, OpName Name);
6489LLVM_READONLY OpName getOperandIdxName(uint32_t Opcode, int16_t Idx);
6490
6491} // namespace llvm::WebAssembly
6492
6493#endif // GET_INSTRINFO_OPERAND_ENUM
6494
6495#ifdef GET_INSTRINFO_NAMED_OPS
6496#undef GET_INSTRINFO_NAMED_OPS
6497
6498namespace llvm::WebAssembly {
6499
6500LLVM_READONLY static uint8_t getInstructionIndexForOpLookup(uint32_t Opcode) {
6501 static constexpr uint8_t InstructionIndex[] = {
6502 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6503 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6504 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6505 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6506 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6507 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6508 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6509 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6510 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6511 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6512 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6513 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6514 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6515 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6516 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6517 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6518 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6519 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6520 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6521 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6522 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6523 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6524 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6525 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6526 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6527 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6528 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6529 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 1,
6530 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1,
6531 2, 1, 2, 1, 2, 1, 2, 1, 2, 3, 2, 3, 2, 3, 2, 3,
6532 2, 3, 2, 3, 2, 3, 2, 3, 2, 4, 2, 4, 2, 4, 2, 4,
6533 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3,
6534 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3,
6535 2, 3, 2, 3, 2, 3, 2, 3, 2, 4, 2, 4, 2, 3, 2, 3,
6536 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3,
6537 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 4, 2, 4,
6538 2, 4, 2, 4, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3,
6539 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3,
6540 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3,
6541 2, 3, 2, 3, 2, 4, 2, 4, 2, 4, 2, 4, 2, 3, 2, 3,
6542 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3,
6543 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 5, 2, 5,
6544 2, 5, 2, 5, 2, 5, 2, 5, 2, 5, 2, 5, 2, 5, 2, 5,
6545 2, 5, 2, 5, 2, 5, 2, 5, 2, 0, 0, 0, 0, 0, 0, 0,
6546 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6547 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6548 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6549 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6550 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6551 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6552 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6553 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6554 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6555 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6556 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6557 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6558 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6559 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6560 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6561 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6562 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6563 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6564 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6565 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6566 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6567 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6568 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6569 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6570 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6571 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6572 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6573 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6574 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6575 0, 0, 0, 0, 0, 0, 0, 6, 7, 6, 7, 6, 7, 6, 7, 6,
6576 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6,
6577 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6,
6578 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6,
6579 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6,
6580 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6,
6581 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 8, 9, 8, 9, 8,
6582 9, 8, 9, 8, 9, 8, 9, 8, 9, 8, 9, 6, 7, 6, 7, 6,
6583 7, 6, 7, 6, 7, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6584 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6585 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6586 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6587 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6588 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6589 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6590 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 2, 10, 2, 11, 2, 11,
6591 2, 11, 2, 11, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6592 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6593 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6594 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6595 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6596 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6597 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6598 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6599 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6600 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6601 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6602 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6603 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6604 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6605 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6606 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6607 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6608 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6609 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6610 0, 0, 0, 0, 0, 0, 0, 0, 0, 12, 7, 12, 7, 12, 7, 12,
6611 7, 12, 7, 12, 7, 12, 7, 12, 7, 12, 7, 12, 7, 12, 7, 12,
6612 7, 12, 7, 12, 7, 12, 7, 12, 7, 12, 7, 12, 7, 12, 7, 12,
6613 7, 13, 9, 13, 9, 13, 9, 13, 9, 13, 9, 13, 9, 13, 9, 13,
6614 9, 14, 7, 14, 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6615 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6616 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6617 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6618 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6619 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6620 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6621 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6622 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6623 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6624 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6625 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6626 };
6627 return InstructionIndex[Opcode];
6628}
6629LLVM_READONLY int16_t getNamedOperandIdx(uint32_t Opcode, OpName Name) {
6630 assert(Name != OpName::NUM_OPERAND_NAMES);
6631 static constexpr int8_t OperandMap[][12] = {
6632 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
6633 {0, 1, 2, 3, 4, -1, -1, -1, -1, -1, -1, -1, },
6634 {-1, 0, 1, 2, -1, -1, -1, -1, -1, -1, -1, -1, },
6635 {0, 1, 2, 3, 4, 5, -1, -1, -1, -1, -1, -1, },
6636 {0, 1, 2, 3, 4, -1, 5, 6, -1, -1, -1, -1, },
6637 {-1, 0, 1, 2, 3, 4, -1, -1, -1, -1, -1, -1, },
6638 {0, -1, 1, 2, 3, -1, -1, -1, -1, -1, -1, -1, },
6639 {-1, -1, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, },
6640 {0, -1, 1, 2, 4, -1, -1, -1, 3, 5, -1, -1, },
6641 {-1, -1, 0, 1, -1, -1, -1, -1, 2, -1, -1, -1, },
6642 {0, 1, 2, 3, 4, -1, -1, -1, -1, -1, 5, -1, },
6643 {0, 1, 2, 3, 4, -1, 5, -1, -1, -1, -1, 6, },
6644 {-1, -1, 0, 1, 2, 3, -1, -1, -1, -1, -1, -1, },
6645 {-1, -1, 0, 1, 3, -1, -1, -1, 2, 4, -1, -1, },
6646 {-1, -1, 0, 1, 2, -1, -1, -1, -1, 3, -1, -1, },
6647 };
6648 unsigned InstrIdx = getInstructionIndexForOpLookup(Opcode);
6649 return OperandMap[InstrIdx][(unsigned)Name];
6650}
6651LLVM_READONLY OpName getOperandIdxName(uint32_t Opcode, int16_t Idx) {
6652 assert(Idx >= 0 && Idx < 7);
6653 static constexpr OpName OperandMap[][7] = {
6654 {OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
6655 {OpName::dst, OpName::order, OpName::p2align, OpName::off, OpName::addr, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
6656 {OpName::order, OpName::p2align, OpName::off, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
6657 {OpName::dst, OpName::order, OpName::p2align, OpName::off, OpName::addr, OpName::val, OpName::NUM_OPERAND_NAMES, },
6658 {OpName::dst, OpName::order, OpName::p2align, OpName::off, OpName::addr, OpName::exp, OpName::new_, },
6659 {OpName::order, OpName::p2align, OpName::off, OpName::addr, OpName::val, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
6660 {OpName::dst, OpName::p2align, OpName::off, OpName::addr, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
6661 {OpName::p2align, OpName::off, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
6662 {OpName::dst, OpName::p2align, OpName::off, OpName::idx, OpName::addr, OpName::vec, OpName::NUM_OPERAND_NAMES, },
6663 {OpName::p2align, OpName::off, OpName::idx, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
6664 {OpName::dst, OpName::order, OpName::p2align, OpName::off, OpName::addr, OpName::count, OpName::NUM_OPERAND_NAMES, },
6665 {OpName::dst, OpName::order, OpName::p2align, OpName::off, OpName::addr, OpName::exp, OpName::timeout, },
6666 {OpName::p2align, OpName::off, OpName::addr, OpName::val, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
6667 {OpName::p2align, OpName::off, OpName::idx, OpName::addr, OpName::vec, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
6668 {OpName::p2align, OpName::off, OpName::addr, OpName::vec, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
6669 };
6670 unsigned InstrIdx = getInstructionIndexForOpLookup(Opcode);
6671 return OperandMap[InstrIdx][(unsigned)Idx];
6672}
6673
6674} // namespace llvm::WebAssembly
6675
6676#endif // GET_INSTRINFO_NAMED_OPS
6677
6678#ifdef GET_INSTRINFO_MC_HELPER_DECLS
6679#undef GET_INSTRINFO_MC_HELPER_DECLS
6680
6681namespace llvm {
6682
6683class MCInst;
6684class FeatureBitset;
6685
6686namespace WebAssembly_MC {
6687
6688void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
6689
6690} // namespace WebAssembly_MC
6691
6692} // namespace llvm
6693
6694#endif // GET_INSTRINFO_MC_HELPER_DECLS
6695
6696#ifdef GET_INSTRINFO_MC_HELPERS
6697#undef GET_INSTRINFO_MC_HELPERS
6698
6699namespace llvm::WebAssembly_MC {
6700
6701
6702} // namespace llvm::WebAssembly_MC
6703
6704#endif // GET_INSTRINFO_MC_HELPERS
6705
6706#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
6707 defined(GET_AVAILABLE_OPCODE_CHECKER)
6708#define GET_COMPUTE_FEATURES
6709#endif
6710#ifdef GET_COMPUTE_FEATURES
6711#undef GET_COMPUTE_FEATURES
6712
6713namespace llvm::WebAssembly_MC {
6714
6715// Bits for subtarget features that participate in instruction matching.
6716enum SubtargetFeatureBits : uint8_t {
6717 Feature_HasAtomicsBit = 0,
6718 Feature_HasBulkMemoryBit = 1,
6719 Feature_HasBulkMemoryOptBit = 2,
6720 Feature_HasCallIndirectOverlongBit = 3,
6721 Feature_HasExceptionHandlingBit = 4,
6722 Feature_HasExtendedConstBit = 5,
6723 Feature_HasFP16Bit = 6,
6724 Feature_HasGCBit = 7,
6725 Feature_HasMultiMemoryBit = 8,
6726 Feature_HasMultivalueBit = 9,
6727 Feature_HasMutableGlobalsBit = 10,
6728 Feature_HasNontrappingFPToIntBit = 11,
6729 Feature_NotHasNontrappingFPToIntBit = 19,
6730 Feature_HasReferenceTypesBit = 12,
6731 Feature_HasRelaxedAtomicsBit = 13,
6732 Feature_HasRelaxedSIMDBit = 14,
6733 Feature_HasSignExtBit = 16,
6734 Feature_HasSIMD128Bit = 15,
6735 Feature_HasTailCallBit = 17,
6736 Feature_HasWideArithmeticBit = 18,
6737};
6738
6739inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
6740 FeatureBitset Features;
6741 if (FB[WebAssembly::FeatureAtomics])
6742 Features.set(Feature_HasAtomicsBit);
6743 if (FB[WebAssembly::FeatureBulkMemory])
6744 Features.set(Feature_HasBulkMemoryBit);
6745 if (FB[WebAssembly::FeatureBulkMemoryOpt])
6746 Features.set(Feature_HasBulkMemoryOptBit);
6747 if (FB[WebAssembly::FeatureCallIndirectOverlong])
6748 Features.set(Feature_HasCallIndirectOverlongBit);
6749 if (FB[WebAssembly::FeatureExceptionHandling])
6750 Features.set(Feature_HasExceptionHandlingBit);
6751 if (FB[WebAssembly::FeatureExtendedConst])
6752 Features.set(Feature_HasExtendedConstBit);
6753 if (FB[WebAssembly::FeatureFP16])
6754 Features.set(Feature_HasFP16Bit);
6755 if (FB[WebAssembly::FeatureGC])
6756 Features.set(Feature_HasGCBit);
6757 if (FB[WebAssembly::FeatureMultiMemory])
6758 Features.set(Feature_HasMultiMemoryBit);
6759 if (FB[WebAssembly::FeatureMultivalue])
6760 Features.set(Feature_HasMultivalueBit);
6761 if (FB[WebAssembly::FeatureMutableGlobals])
6762 Features.set(Feature_HasMutableGlobalsBit);
6763 if (FB[WebAssembly::FeatureNontrappingFPToInt])
6764 Features.set(Feature_HasNontrappingFPToIntBit);
6765 if (!(FB[WebAssembly::FeatureNontrappingFPToInt]))
6766 Features.set(Feature_NotHasNontrappingFPToIntBit);
6767 if (FB[WebAssembly::FeatureReferenceTypes])
6768 Features.set(Feature_HasReferenceTypesBit);
6769 if (FB[WebAssembly::FeatureRelaxedAtomics])
6770 Features.set(Feature_HasRelaxedAtomicsBit);
6771 if (FB[WebAssembly::FeatureRelaxedSIMD])
6772 Features.set(Feature_HasRelaxedSIMDBit);
6773 if (FB[WebAssembly::FeatureSignExt])
6774 Features.set(Feature_HasSignExtBit);
6775 if (FB[WebAssembly::FeatureSIMD128] || FB[WebAssembly::FeatureRelaxedSIMD])
6776 Features.set(Feature_HasSIMD128Bit);
6777 if (FB[WebAssembly::FeatureTailCall])
6778 Features.set(Feature_HasTailCallBit);
6779 if (FB[WebAssembly::FeatureWideArithmetic])
6780 Features.set(Feature_HasWideArithmeticBit);
6781 return Features;
6782}
6783
6784inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
6785 enum : uint8_t {
6786 CEFBS_None,
6787 CEFBS_HasAtomics,
6788 CEFBS_HasBulkMemoryOpt,
6789 CEFBS_HasExceptionHandling,
6790 CEFBS_HasFP16,
6791 CEFBS_HasGC,
6792 CEFBS_HasNontrappingFPToInt,
6793 CEFBS_HasReferenceTypes,
6794 CEFBS_HasRelaxedSIMD,
6795 CEFBS_HasSIMD128,
6796 CEFBS_HasSignExt,
6797 CEFBS_HasTailCall,
6798 CEFBS_HasWideArithmetic,
6799 CEFBS_NotHasNontrappingFPToInt,
6800 CEFBS_HasReferenceTypes_HasExceptionHandling,
6801 CEFBS_HasSIMD128_HasFP16,
6802 CEFBS_HasSIMD128_HasRelaxedSIMD,
6803 CEFBS_HasTailCall_HasGC,
6804 };
6805
6806 static constexpr FeatureBitset FeatureBitsets[] = {
6807 {}, // CEFBS_None
6808 {Feature_HasAtomicsBit, },
6809 {Feature_HasBulkMemoryOptBit, },
6810 {Feature_HasExceptionHandlingBit, },
6811 {Feature_HasFP16Bit, },
6812 {Feature_HasGCBit, },
6813 {Feature_HasNontrappingFPToIntBit, },
6814 {Feature_HasReferenceTypesBit, },
6815 {Feature_HasRelaxedSIMDBit, },
6816 {Feature_HasSIMD128Bit, },
6817 {Feature_HasSignExtBit, },
6818 {Feature_HasTailCallBit, },
6819 {Feature_HasWideArithmeticBit, },
6820 {Feature_NotHasNontrappingFPToIntBit, },
6821 {Feature_HasReferenceTypesBit, Feature_HasExceptionHandlingBit, },
6822 {Feature_HasSIMD128Bit, Feature_HasFP16Bit, },
6823 {Feature_HasSIMD128Bit, Feature_HasRelaxedSIMDBit, },
6824 {Feature_HasTailCallBit, Feature_HasGCBit, },
6825 };
6826 static constexpr uint8_t RequiredFeaturesRefs[] = {
6827 CEFBS_None, // PHI
6828 CEFBS_None, // INLINEASM
6829 CEFBS_None, // INLINEASM_BR
6830 CEFBS_None, // CFI_INSTRUCTION
6831 CEFBS_None, // EH_LABEL
6832 CEFBS_None, // GC_LABEL
6833 CEFBS_None, // ANNOTATION_LABEL
6834 CEFBS_None, // KILL
6835 CEFBS_None, // EXTRACT_SUBREG
6836 CEFBS_None, // INSERT_SUBREG
6837 CEFBS_None, // IMPLICIT_DEF
6838 CEFBS_None, // INIT_UNDEF
6839 CEFBS_None, // SUBREG_TO_REG
6840 CEFBS_None, // COPY_TO_REGCLASS
6841 CEFBS_None, // DBG_VALUE
6842 CEFBS_None, // DBG_VALUE_LIST
6843 CEFBS_None, // DBG_INSTR_REF
6844 CEFBS_None, // DBG_PHI
6845 CEFBS_None, // DBG_LABEL
6846 CEFBS_None, // REG_SEQUENCE
6847 CEFBS_None, // COPY
6848 CEFBS_None, // COPY_LANEMASK
6849 CEFBS_None, // BUNDLE
6850 CEFBS_None, // LIFETIME_START
6851 CEFBS_None, // LIFETIME_END
6852 CEFBS_None, // PSEUDO_PROBE
6853 CEFBS_None, // ARITH_FENCE
6854 CEFBS_None, // STACKMAP
6855 CEFBS_None, // FENTRY_CALL
6856 CEFBS_None, // PATCHPOINT
6857 CEFBS_None, // LOAD_STACK_GUARD
6858 CEFBS_None, // PREALLOCATED_SETUP
6859 CEFBS_None, // PREALLOCATED_ARG
6860 CEFBS_None, // STATEPOINT
6861 CEFBS_None, // LOCAL_ESCAPE
6862 CEFBS_None, // FAULTING_OP
6863 CEFBS_None, // PATCHABLE_OP
6864 CEFBS_None, // PATCHABLE_FUNCTION_ENTER
6865 CEFBS_None, // PATCHABLE_RET
6866 CEFBS_None, // PATCHABLE_FUNCTION_EXIT
6867 CEFBS_None, // PATCHABLE_TAIL_CALL
6868 CEFBS_None, // PATCHABLE_EVENT_CALL
6869 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL
6870 CEFBS_None, // ICALL_BRANCH_FUNNEL
6871 CEFBS_None, // FAKE_USE
6872 CEFBS_None, // MEMBARRIER
6873 CEFBS_None, // JUMP_TABLE_DEBUG_INFO
6874 CEFBS_None, // RELOC_NONE
6875 CEFBS_None, // CONVERGENCECTRL_ENTRY
6876 CEFBS_None, // CONVERGENCECTRL_ANCHOR
6877 CEFBS_None, // CONVERGENCECTRL_LOOP
6878 CEFBS_None, // CONVERGENCECTRL_GLUE
6879 CEFBS_None, // G_ASSERT_SEXT
6880 CEFBS_None, // G_ASSERT_ZEXT
6881 CEFBS_None, // G_ASSERT_ALIGN
6882 CEFBS_None, // G_ADD
6883 CEFBS_None, // G_SUB
6884 CEFBS_None, // G_MUL
6885 CEFBS_None, // G_SDIV
6886 CEFBS_None, // G_UDIV
6887 CEFBS_None, // G_SREM
6888 CEFBS_None, // G_UREM
6889 CEFBS_None, // G_SDIVREM
6890 CEFBS_None, // G_UDIVREM
6891 CEFBS_None, // G_AND
6892 CEFBS_None, // G_OR
6893 CEFBS_None, // G_XOR
6894 CEFBS_None, // G_ABDS
6895 CEFBS_None, // G_ABDU
6896 CEFBS_None, // G_UAVGFLOOR
6897 CEFBS_None, // G_UAVGCEIL
6898 CEFBS_None, // G_SAVGFLOOR
6899 CEFBS_None, // G_SAVGCEIL
6900 CEFBS_None, // G_IMPLICIT_DEF
6901 CEFBS_None, // G_PHI
6902 CEFBS_None, // G_FRAME_INDEX
6903 CEFBS_None, // G_GLOBAL_VALUE
6904 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE
6905 CEFBS_None, // G_CONSTANT_POOL
6906 CEFBS_None, // G_EXTRACT
6907 CEFBS_None, // G_UNMERGE_VALUES
6908 CEFBS_None, // G_INSERT
6909 CEFBS_None, // G_MERGE_VALUES
6910 CEFBS_None, // G_BUILD_VECTOR
6911 CEFBS_None, // G_BUILD_VECTOR_TRUNC
6912 CEFBS_None, // G_CONCAT_VECTORS
6913 CEFBS_None, // G_PTRTOINT
6914 CEFBS_None, // G_INTTOPTR
6915 CEFBS_None, // G_BITCAST
6916 CEFBS_None, // G_FREEZE
6917 CEFBS_None, // G_CONSTANT_FOLD_BARRIER
6918 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND
6919 CEFBS_None, // G_INTRINSIC_TRUNC
6920 CEFBS_None, // G_INTRINSIC_ROUND
6921 CEFBS_None, // G_INTRINSIC_LRINT
6922 CEFBS_None, // G_INTRINSIC_LLRINT
6923 CEFBS_None, // G_INTRINSIC_ROUNDEVEN
6924 CEFBS_None, // G_READCYCLECOUNTER
6925 CEFBS_None, // G_READSTEADYCOUNTER
6926 CEFBS_None, // G_LOAD
6927 CEFBS_None, // G_SEXTLOAD
6928 CEFBS_None, // G_ZEXTLOAD
6929 CEFBS_None, // G_FPEXTLOAD
6930 CEFBS_None, // G_INDEXED_LOAD
6931 CEFBS_None, // G_INDEXED_SEXTLOAD
6932 CEFBS_None, // G_INDEXED_ZEXTLOAD
6933 CEFBS_None, // G_STORE
6934 CEFBS_None, // G_FPTRUNCSTORE
6935 CEFBS_None, // G_INDEXED_STORE
6936 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
6937 CEFBS_None, // G_ATOMIC_CMPXCHG
6938 CEFBS_None, // G_ATOMICRMW_XCHG
6939 CEFBS_None, // G_ATOMICRMW_ADD
6940 CEFBS_None, // G_ATOMICRMW_SUB
6941 CEFBS_None, // G_ATOMICRMW_AND
6942 CEFBS_None, // G_ATOMICRMW_NAND
6943 CEFBS_None, // G_ATOMICRMW_OR
6944 CEFBS_None, // G_ATOMICRMW_XOR
6945 CEFBS_None, // G_ATOMICRMW_MAX
6946 CEFBS_None, // G_ATOMICRMW_MIN
6947 CEFBS_None, // G_ATOMICRMW_UMAX
6948 CEFBS_None, // G_ATOMICRMW_UMIN
6949 CEFBS_None, // G_ATOMICRMW_FADD
6950 CEFBS_None, // G_ATOMICRMW_FSUB
6951 CEFBS_None, // G_ATOMICRMW_FMAX
6952 CEFBS_None, // G_ATOMICRMW_FMIN
6953 CEFBS_None, // G_ATOMICRMW_FMAXIMUM
6954 CEFBS_None, // G_ATOMICRMW_FMINIMUM
6955 CEFBS_None, // G_ATOMICRMW_FMAXIMUMNUM
6956 CEFBS_None, // G_ATOMICRMW_FMINIMUMNUM
6957 CEFBS_None, // G_ATOMICRMW_UINC_WRAP
6958 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP
6959 CEFBS_None, // G_ATOMICRMW_USUB_COND
6960 CEFBS_None, // G_ATOMICRMW_USUB_SAT
6961 CEFBS_None, // G_FENCE
6962 CEFBS_None, // G_PREFETCH
6963 CEFBS_None, // G_BRCOND
6964 CEFBS_None, // G_BRINDIRECT
6965 CEFBS_None, // G_INVOKE_REGION_START
6966 CEFBS_None, // G_INTRINSIC
6967 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS
6968 CEFBS_None, // G_INTRINSIC_CONVERGENT
6969 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
6970 CEFBS_None, // G_ANYEXT
6971 CEFBS_None, // G_TRUNC
6972 CEFBS_None, // G_TRUNC_SSAT_S
6973 CEFBS_None, // G_TRUNC_SSAT_U
6974 CEFBS_None, // G_TRUNC_USAT_U
6975 CEFBS_None, // G_CONSTANT
6976 CEFBS_None, // G_FCONSTANT
6977 CEFBS_None, // G_VASTART
6978 CEFBS_None, // G_VAARG
6979 CEFBS_None, // G_SEXT
6980 CEFBS_None, // G_SEXT_INREG
6981 CEFBS_None, // G_ZEXT
6982 CEFBS_None, // G_SHL
6983 CEFBS_None, // G_LSHR
6984 CEFBS_None, // G_ASHR
6985 CEFBS_None, // G_FSHL
6986 CEFBS_None, // G_FSHR
6987 CEFBS_None, // G_ROTR
6988 CEFBS_None, // G_ROTL
6989 CEFBS_None, // G_ICMP
6990 CEFBS_None, // G_FCMP
6991 CEFBS_None, // G_SCMP
6992 CEFBS_None, // G_UCMP
6993 CEFBS_None, // G_SELECT
6994 CEFBS_None, // G_UADDO
6995 CEFBS_None, // G_UADDE
6996 CEFBS_None, // G_USUBO
6997 CEFBS_None, // G_USUBE
6998 CEFBS_None, // G_SADDO
6999 CEFBS_None, // G_SADDE
7000 CEFBS_None, // G_SSUBO
7001 CEFBS_None, // G_SSUBE
7002 CEFBS_None, // G_UMULO
7003 CEFBS_None, // G_SMULO
7004 CEFBS_None, // G_UMULH
7005 CEFBS_None, // G_SMULH
7006 CEFBS_None, // G_UADDSAT
7007 CEFBS_None, // G_SADDSAT
7008 CEFBS_None, // G_USUBSAT
7009 CEFBS_None, // G_SSUBSAT
7010 CEFBS_None, // G_USHLSAT
7011 CEFBS_None, // G_SSHLSAT
7012 CEFBS_None, // G_SMULFIX
7013 CEFBS_None, // G_UMULFIX
7014 CEFBS_None, // G_SMULFIXSAT
7015 CEFBS_None, // G_UMULFIXSAT
7016 CEFBS_None, // G_SDIVFIX
7017 CEFBS_None, // G_UDIVFIX
7018 CEFBS_None, // G_SDIVFIXSAT
7019 CEFBS_None, // G_UDIVFIXSAT
7020 CEFBS_None, // G_FADD
7021 CEFBS_None, // G_FSUB
7022 CEFBS_None, // G_FMUL
7023 CEFBS_None, // G_FMA
7024 CEFBS_None, // G_FMAD
7025 CEFBS_None, // G_FDIV
7026 CEFBS_None, // G_FREM
7027 CEFBS_None, // G_FMODF
7028 CEFBS_None, // G_FPOW
7029 CEFBS_None, // G_FPOWI
7030 CEFBS_None, // G_FEXP
7031 CEFBS_None, // G_FEXP2
7032 CEFBS_None, // G_FEXP10
7033 CEFBS_None, // G_FLOG
7034 CEFBS_None, // G_FLOG2
7035 CEFBS_None, // G_FLOG10
7036 CEFBS_None, // G_FLDEXP
7037 CEFBS_None, // G_FFREXP
7038 CEFBS_None, // G_FNEG
7039 CEFBS_None, // G_FPEXT
7040 CEFBS_None, // G_FPTRUNC
7041 CEFBS_None, // G_FPTOSI
7042 CEFBS_None, // G_FPTOUI
7043 CEFBS_None, // G_SITOFP
7044 CEFBS_None, // G_UITOFP
7045 CEFBS_None, // G_FPTOSI_SAT
7046 CEFBS_None, // G_FPTOUI_SAT
7047 CEFBS_None, // G_FABS
7048 CEFBS_None, // G_FCOPYSIGN
7049 CEFBS_None, // G_IS_FPCLASS
7050 CEFBS_None, // G_FCANONICALIZE
7051 CEFBS_None, // G_FMINNUM
7052 CEFBS_None, // G_FMAXNUM
7053 CEFBS_None, // G_FMINNUM_IEEE
7054 CEFBS_None, // G_FMAXNUM_IEEE
7055 CEFBS_None, // G_FMINIMUM
7056 CEFBS_None, // G_FMAXIMUM
7057 CEFBS_None, // G_FMINIMUMNUM
7058 CEFBS_None, // G_FMAXIMUMNUM
7059 CEFBS_None, // G_GET_FPENV
7060 CEFBS_None, // G_SET_FPENV
7061 CEFBS_None, // G_RESET_FPENV
7062 CEFBS_None, // G_GET_FPMODE
7063 CEFBS_None, // G_SET_FPMODE
7064 CEFBS_None, // G_RESET_FPMODE
7065 CEFBS_None, // G_GET_ROUNDING
7066 CEFBS_None, // G_SET_ROUNDING
7067 CEFBS_None, // G_PTR_ADD
7068 CEFBS_None, // G_PTRMASK
7069 CEFBS_None, // G_SMIN
7070 CEFBS_None, // G_SMAX
7071 CEFBS_None, // G_UMIN
7072 CEFBS_None, // G_UMAX
7073 CEFBS_None, // G_ABS
7074 CEFBS_None, // G_LROUND
7075 CEFBS_None, // G_LLROUND
7076 CEFBS_None, // G_BR
7077 CEFBS_None, // G_BRJT
7078 CEFBS_None, // G_VSCALE
7079 CEFBS_None, // G_INSERT_SUBVECTOR
7080 CEFBS_None, // G_EXTRACT_SUBVECTOR
7081 CEFBS_None, // G_INSERT_VECTOR_ELT
7082 CEFBS_None, // G_EXTRACT_VECTOR_ELT
7083 CEFBS_None, // G_SHUFFLE_VECTOR
7084 CEFBS_None, // G_SPLAT_VECTOR
7085 CEFBS_None, // G_STEP_VECTOR
7086 CEFBS_None, // G_VECTOR_COMPRESS
7087 CEFBS_None, // G_CTTZ
7088 CEFBS_None, // G_CTTZ_ZERO_POISON
7089 CEFBS_None, // G_CTLZ
7090 CEFBS_None, // G_CTLZ_ZERO_POISON
7091 CEFBS_None, // G_CTLS
7092 CEFBS_None, // G_CTPOP
7093 CEFBS_None, // G_BSWAP
7094 CEFBS_None, // G_BITREVERSE
7095 CEFBS_None, // G_CLMUL
7096 CEFBS_None, // G_FCEIL
7097 CEFBS_None, // G_FCOS
7098 CEFBS_None, // G_FSIN
7099 CEFBS_None, // G_FSINCOS
7100 CEFBS_None, // G_FTAN
7101 CEFBS_None, // G_FACOS
7102 CEFBS_None, // G_FASIN
7103 CEFBS_None, // G_FATAN
7104 CEFBS_None, // G_FATAN2
7105 CEFBS_None, // G_FCOSH
7106 CEFBS_None, // G_FSINH
7107 CEFBS_None, // G_FTANH
7108 CEFBS_None, // G_FSQRT
7109 CEFBS_None, // G_FFLOOR
7110 CEFBS_None, // G_FRINT
7111 CEFBS_None, // G_FNEARBYINT
7112 CEFBS_None, // G_ADDRSPACE_CAST
7113 CEFBS_None, // G_BLOCK_ADDR
7114 CEFBS_None, // G_JUMP_TABLE
7115 CEFBS_None, // G_DYN_STACKALLOC
7116 CEFBS_None, // G_STACKSAVE
7117 CEFBS_None, // G_STACKRESTORE
7118 CEFBS_None, // G_STRICT_FADD
7119 CEFBS_None, // G_STRICT_FSUB
7120 CEFBS_None, // G_STRICT_FMUL
7121 CEFBS_None, // G_STRICT_FDIV
7122 CEFBS_None, // G_STRICT_FREM
7123 CEFBS_None, // G_STRICT_FMA
7124 CEFBS_None, // G_STRICT_FSQRT
7125 CEFBS_None, // G_STRICT_FLDEXP
7126 CEFBS_None, // G_STRICT_FCMP
7127 CEFBS_None, // G_STRICT_FCMPS
7128 CEFBS_None, // G_READ_REGISTER
7129 CEFBS_None, // G_WRITE_REGISTER
7130 CEFBS_None, // G_MEMCPY
7131 CEFBS_None, // G_MEMCPY_INLINE
7132 CEFBS_None, // G_MEMMOVE
7133 CEFBS_None, // G_MEMSET
7134 CEFBS_None, // G_BZERO
7135 CEFBS_None, // G_MEMSET_INLINE
7136 CEFBS_None, // G_TRAP
7137 CEFBS_None, // G_DEBUGTRAP
7138 CEFBS_None, // G_UBSANTRAP
7139 CEFBS_None, // G_VECREDUCE_SEQ_FADD
7140 CEFBS_None, // G_VECREDUCE_SEQ_FMUL
7141 CEFBS_None, // G_VECREDUCE_FADD
7142 CEFBS_None, // G_VECREDUCE_FMUL
7143 CEFBS_None, // G_VECREDUCE_FMAX
7144 CEFBS_None, // G_VECREDUCE_FMIN
7145 CEFBS_None, // G_VECREDUCE_FMAXIMUM
7146 CEFBS_None, // G_VECREDUCE_FMINIMUM
7147 CEFBS_None, // G_VECREDUCE_FMAXIMUMNUM
7148 CEFBS_None, // G_VECREDUCE_FMINIMUMNUM
7149 CEFBS_None, // G_VECREDUCE_ADD
7150 CEFBS_None, // G_VECREDUCE_MUL
7151 CEFBS_None, // G_VECREDUCE_AND
7152 CEFBS_None, // G_VECREDUCE_OR
7153 CEFBS_None, // G_VECREDUCE_XOR
7154 CEFBS_None, // G_VECREDUCE_SMAX
7155 CEFBS_None, // G_VECREDUCE_SMIN
7156 CEFBS_None, // G_VECREDUCE_UMAX
7157 CEFBS_None, // G_VECREDUCE_UMIN
7158 CEFBS_None, // G_SBFX
7159 CEFBS_None, // G_UBFX
7160 CEFBS_None, // CALL_PARAMS
7161 CEFBS_None, // CALL_PARAMS_S
7162 CEFBS_None, // CALL_RESULTS
7163 CEFBS_None, // CALL_RESULTS_S
7164 CEFBS_HasExceptionHandling, // CATCHRET
7165 CEFBS_HasExceptionHandling, // CATCHRET_S
7166 CEFBS_HasExceptionHandling, // CLEANUPRET
7167 CEFBS_HasExceptionHandling, // CLEANUPRET_S
7168 CEFBS_HasAtomics, // COMPILER_FENCE
7169 CEFBS_HasAtomics, // COMPILER_FENCE_S
7170 CEFBS_None, // RET_CALL_RESULTS
7171 CEFBS_None, // RET_CALL_RESULTS_S
7172 CEFBS_HasSIMD128_HasFP16, // ABS_F16x8
7173 CEFBS_HasSIMD128_HasFP16, // ABS_F16x8_S
7174 CEFBS_None, // ABS_F32
7175 CEFBS_None, // ABS_F32_S
7176 CEFBS_HasSIMD128, // ABS_F32x4
7177 CEFBS_HasSIMD128, // ABS_F32x4_S
7178 CEFBS_None, // ABS_F64
7179 CEFBS_None, // ABS_F64_S
7180 CEFBS_HasSIMD128, // ABS_F64x2
7181 CEFBS_HasSIMD128, // ABS_F64x2_S
7182 CEFBS_HasSIMD128, // ABS_I16x8
7183 CEFBS_HasSIMD128, // ABS_I16x8_S
7184 CEFBS_HasSIMD128, // ABS_I32x4
7185 CEFBS_HasSIMD128, // ABS_I32x4_S
7186 CEFBS_HasSIMD128, // ABS_I64x2
7187 CEFBS_HasSIMD128, // ABS_I64x2_S
7188 CEFBS_HasSIMD128, // ABS_I8x16
7189 CEFBS_HasSIMD128, // ABS_I8x16_S
7190 CEFBS_HasSIMD128_HasFP16, // ADD_F16x8
7191 CEFBS_HasSIMD128_HasFP16, // ADD_F16x8_S
7192 CEFBS_None, // ADD_F32
7193 CEFBS_None, // ADD_F32_S
7194 CEFBS_HasSIMD128, // ADD_F32x4
7195 CEFBS_HasSIMD128, // ADD_F32x4_S
7196 CEFBS_None, // ADD_F64
7197 CEFBS_None, // ADD_F64_S
7198 CEFBS_HasSIMD128, // ADD_F64x2
7199 CEFBS_HasSIMD128, // ADD_F64x2_S
7200 CEFBS_HasSIMD128, // ADD_I16x8
7201 CEFBS_HasSIMD128, // ADD_I16x8_S
7202 CEFBS_None, // ADD_I32
7203 CEFBS_None, // ADD_I32_S
7204 CEFBS_HasSIMD128, // ADD_I32x4
7205 CEFBS_HasSIMD128, // ADD_I32x4_S
7206 CEFBS_None, // ADD_I64
7207 CEFBS_None, // ADD_I64_S
7208 CEFBS_HasSIMD128, // ADD_I64x2
7209 CEFBS_HasSIMD128, // ADD_I64x2_S
7210 CEFBS_HasSIMD128, // ADD_I8x16
7211 CEFBS_HasSIMD128, // ADD_I8x16_S
7212 CEFBS_HasSIMD128, // ADD_SAT_S_I16x8
7213 CEFBS_HasSIMD128, // ADD_SAT_S_I16x8_S
7214 CEFBS_HasSIMD128, // ADD_SAT_S_I8x16
7215 CEFBS_HasSIMD128, // ADD_SAT_S_I8x16_S
7216 CEFBS_HasSIMD128, // ADD_SAT_U_I16x8
7217 CEFBS_HasSIMD128, // ADD_SAT_U_I16x8_S
7218 CEFBS_HasSIMD128, // ADD_SAT_U_I8x16
7219 CEFBS_HasSIMD128, // ADD_SAT_U_I8x16_S
7220 CEFBS_None, // ADJCALLSTACKDOWN
7221 CEFBS_None, // ADJCALLSTACKDOWN_S
7222 CEFBS_None, // ADJCALLSTACKUP
7223 CEFBS_None, // ADJCALLSTACKUP_S
7224 CEFBS_HasSIMD128, // ALLTRUE_I16x8
7225 CEFBS_HasSIMD128, // ALLTRUE_I16x8_S
7226 CEFBS_HasSIMD128, // ALLTRUE_I32x4
7227 CEFBS_HasSIMD128, // ALLTRUE_I32x4_S
7228 CEFBS_HasSIMD128, // ALLTRUE_I64x2
7229 CEFBS_HasSIMD128, // ALLTRUE_I64x2_S
7230 CEFBS_HasSIMD128, // ALLTRUE_I8x16
7231 CEFBS_HasSIMD128, // ALLTRUE_I8x16_S
7232 CEFBS_HasSIMD128, // AND
7233 CEFBS_HasSIMD128, // ANDNOT
7234 CEFBS_HasSIMD128, // ANDNOT_S
7235 CEFBS_None, // AND_I32
7236 CEFBS_None, // AND_I32_S
7237 CEFBS_None, // AND_I64
7238 CEFBS_None, // AND_I64_S
7239 CEFBS_HasSIMD128, // AND_S
7240 CEFBS_HasSIMD128, // ANYTRUE
7241 CEFBS_HasSIMD128, // ANYTRUE_S
7242 CEFBS_None, // ARGUMENT_exnref
7243 CEFBS_None, // ARGUMENT_exnref_S
7244 CEFBS_None, // ARGUMENT_externref
7245 CEFBS_None, // ARGUMENT_externref_S
7246 CEFBS_None, // ARGUMENT_f32
7247 CEFBS_None, // ARGUMENT_f32_S
7248 CEFBS_None, // ARGUMENT_f64
7249 CEFBS_None, // ARGUMENT_f64_S
7250 CEFBS_None, // ARGUMENT_funcref
7251 CEFBS_None, // ARGUMENT_funcref_S
7252 CEFBS_None, // ARGUMENT_i32
7253 CEFBS_None, // ARGUMENT_i32_S
7254 CEFBS_None, // ARGUMENT_i64
7255 CEFBS_None, // ARGUMENT_i64_S
7256 CEFBS_None, // ARGUMENT_v16i8
7257 CEFBS_None, // ARGUMENT_v16i8_S
7258 CEFBS_None, // ARGUMENT_v2f64
7259 CEFBS_None, // ARGUMENT_v2f64_S
7260 CEFBS_None, // ARGUMENT_v2i64
7261 CEFBS_None, // ARGUMENT_v2i64_S
7262 CEFBS_None, // ARGUMENT_v4f32
7263 CEFBS_None, // ARGUMENT_v4f32_S
7264 CEFBS_None, // ARGUMENT_v4i32
7265 CEFBS_None, // ARGUMENT_v4i32_S
7266 CEFBS_None, // ARGUMENT_v8f16
7267 CEFBS_None, // ARGUMENT_v8f16_S
7268 CEFBS_None, // ARGUMENT_v8i16
7269 CEFBS_None, // ARGUMENT_v8i16_S
7270 CEFBS_HasAtomics, // ATOMIC_FENCE
7271 CEFBS_HasAtomics, // ATOMIC_FENCE_S
7272 CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I32_A32
7273 CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I32_A32_S
7274 CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I32_A64
7275 CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I32_A64_S
7276 CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I64_A32
7277 CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I64_A32_S
7278 CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I64_A64
7279 CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I64_A64_S
7280 CEFBS_HasAtomics, // ATOMIC_LOAD32_U_I64_A32
7281 CEFBS_HasAtomics, // ATOMIC_LOAD32_U_I64_A32_S
7282 CEFBS_HasAtomics, // ATOMIC_LOAD32_U_I64_A64
7283 CEFBS_HasAtomics, // ATOMIC_LOAD32_U_I64_A64_S
7284 CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I32_A32
7285 CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I32_A32_S
7286 CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I32_A64
7287 CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I32_A64_S
7288 CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I64_A32
7289 CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I64_A32_S
7290 CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I64_A64
7291 CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I64_A64_S
7292 CEFBS_HasAtomics, // ATOMIC_LOAD_I32_A32
7293 CEFBS_HasAtomics, // ATOMIC_LOAD_I32_A32_S
7294 CEFBS_HasAtomics, // ATOMIC_LOAD_I32_A64
7295 CEFBS_HasAtomics, // ATOMIC_LOAD_I32_A64_S
7296 CEFBS_HasAtomics, // ATOMIC_LOAD_I64_A32
7297 CEFBS_HasAtomics, // ATOMIC_LOAD_I64_A32_S
7298 CEFBS_HasAtomics, // ATOMIC_LOAD_I64_A64
7299 CEFBS_HasAtomics, // ATOMIC_LOAD_I64_A64_S
7300 CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I32_A32
7301 CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I32_A32_S
7302 CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I32_A64
7303 CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I32_A64_S
7304 CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I64_A32
7305 CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I64_A32_S
7306 CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I64_A64
7307 CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I64_A64_S
7308 CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I32_A32
7309 CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I32_A32_S
7310 CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I32_A64
7311 CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I32_A64_S
7312 CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I64_A32
7313 CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I64_A32_S
7314 CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I64_A64
7315 CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I64_A64_S
7316 CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I32_A32
7317 CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I32_A32_S
7318 CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I32_A64
7319 CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I32_A64_S
7320 CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I64_A32
7321 CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I64_A32_S
7322 CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I64_A64
7323 CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I64_A64_S
7324 CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I32_A32
7325 CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I32_A32_S
7326 CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I32_A64
7327 CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I32_A64_S
7328 CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I64_A32
7329 CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I64_A32_S
7330 CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I64_A64
7331 CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I64_A64_S
7332 CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I32_A32
7333 CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I32_A32_S
7334 CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I32_A64
7335 CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I32_A64_S
7336 CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I64_A32
7337 CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I64_A32_S
7338 CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I64_A64
7339 CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I64_A64_S
7340 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I32_A32
7341 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I32_A32_S
7342 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I32_A64
7343 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I32_A64_S
7344 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I64_A32
7345 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I64_A32_S
7346 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I64_A64
7347 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I64_A64_S
7348 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I32_A32
7349 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I32_A32_S
7350 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I32_A64
7351 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I32_A64_S
7352 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I64_A32
7353 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I64_A32_S
7354 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I64_A64
7355 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I64_A64_S
7356 CEFBS_HasAtomics, // ATOMIC_RMW32_U_ADD_I64_A32
7357 CEFBS_HasAtomics, // ATOMIC_RMW32_U_ADD_I64_A32_S
7358 CEFBS_HasAtomics, // ATOMIC_RMW32_U_ADD_I64_A64
7359 CEFBS_HasAtomics, // ATOMIC_RMW32_U_ADD_I64_A64_S
7360 CEFBS_HasAtomics, // ATOMIC_RMW32_U_AND_I64_A32
7361 CEFBS_HasAtomics, // ATOMIC_RMW32_U_AND_I64_A32_S
7362 CEFBS_HasAtomics, // ATOMIC_RMW32_U_AND_I64_A64
7363 CEFBS_HasAtomics, // ATOMIC_RMW32_U_AND_I64_A64_S
7364 CEFBS_HasAtomics, // ATOMIC_RMW32_U_CMPXCHG_I64_A32
7365 CEFBS_HasAtomics, // ATOMIC_RMW32_U_CMPXCHG_I64_A32_S
7366 CEFBS_HasAtomics, // ATOMIC_RMW32_U_CMPXCHG_I64_A64
7367 CEFBS_HasAtomics, // ATOMIC_RMW32_U_CMPXCHG_I64_A64_S
7368 CEFBS_HasAtomics, // ATOMIC_RMW32_U_OR_I64_A32
7369 CEFBS_HasAtomics, // ATOMIC_RMW32_U_OR_I64_A32_S
7370 CEFBS_HasAtomics, // ATOMIC_RMW32_U_OR_I64_A64
7371 CEFBS_HasAtomics, // ATOMIC_RMW32_U_OR_I64_A64_S
7372 CEFBS_HasAtomics, // ATOMIC_RMW32_U_SUB_I64_A32
7373 CEFBS_HasAtomics, // ATOMIC_RMW32_U_SUB_I64_A32_S
7374 CEFBS_HasAtomics, // ATOMIC_RMW32_U_SUB_I64_A64
7375 CEFBS_HasAtomics, // ATOMIC_RMW32_U_SUB_I64_A64_S
7376 CEFBS_HasAtomics, // ATOMIC_RMW32_U_XCHG_I64_A32
7377 CEFBS_HasAtomics, // ATOMIC_RMW32_U_XCHG_I64_A32_S
7378 CEFBS_HasAtomics, // ATOMIC_RMW32_U_XCHG_I64_A64
7379 CEFBS_HasAtomics, // ATOMIC_RMW32_U_XCHG_I64_A64_S
7380 CEFBS_HasAtomics, // ATOMIC_RMW32_U_XOR_I64_A32
7381 CEFBS_HasAtomics, // ATOMIC_RMW32_U_XOR_I64_A32_S
7382 CEFBS_HasAtomics, // ATOMIC_RMW32_U_XOR_I64_A64
7383 CEFBS_HasAtomics, // ATOMIC_RMW32_U_XOR_I64_A64_S
7384 CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I32_A32
7385 CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I32_A32_S
7386 CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I32_A64
7387 CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I32_A64_S
7388 CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I64_A32
7389 CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I64_A32_S
7390 CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I64_A64
7391 CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I64_A64_S
7392 CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I32_A32
7393 CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I32_A32_S
7394 CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I32_A64
7395 CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I32_A64_S
7396 CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I64_A32
7397 CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I64_A32_S
7398 CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I64_A64
7399 CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I64_A64_S
7400 CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I32_A32
7401 CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I32_A32_S
7402 CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I32_A64
7403 CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I32_A64_S
7404 CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I64_A32
7405 CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I64_A32_S
7406 CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I64_A64
7407 CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I64_A64_S
7408 CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I32_A32
7409 CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I32_A32_S
7410 CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I32_A64
7411 CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I32_A64_S
7412 CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I64_A32
7413 CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I64_A32_S
7414 CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I64_A64
7415 CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I64_A64_S
7416 CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I32_A32
7417 CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I32_A32_S
7418 CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I32_A64
7419 CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I32_A64_S
7420 CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I64_A32
7421 CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I64_A32_S
7422 CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I64_A64
7423 CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I64_A64_S
7424 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I32_A32
7425 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I32_A32_S
7426 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I32_A64
7427 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I32_A64_S
7428 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I64_A32
7429 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I64_A32_S
7430 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I64_A64
7431 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I64_A64_S
7432 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I32_A32
7433 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I32_A32_S
7434 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I32_A64
7435 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I32_A64_S
7436 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I64_A32
7437 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I64_A32_S
7438 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I64_A64
7439 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I64_A64_S
7440 CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I32_A32
7441 CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I32_A32_S
7442 CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I32_A64
7443 CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I32_A64_S
7444 CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I64_A32
7445 CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I64_A32_S
7446 CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I64_A64
7447 CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I64_A64_S
7448 CEFBS_HasAtomics, // ATOMIC_RMW_AND_I32_A32
7449 CEFBS_HasAtomics, // ATOMIC_RMW_AND_I32_A32_S
7450 CEFBS_HasAtomics, // ATOMIC_RMW_AND_I32_A64
7451 CEFBS_HasAtomics, // ATOMIC_RMW_AND_I32_A64_S
7452 CEFBS_HasAtomics, // ATOMIC_RMW_AND_I64_A32
7453 CEFBS_HasAtomics, // ATOMIC_RMW_AND_I64_A32_S
7454 CEFBS_HasAtomics, // ATOMIC_RMW_AND_I64_A64
7455 CEFBS_HasAtomics, // ATOMIC_RMW_AND_I64_A64_S
7456 CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I32_A32
7457 CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I32_A32_S
7458 CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I32_A64
7459 CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I32_A64_S
7460 CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I64_A32
7461 CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I64_A32_S
7462 CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I64_A64
7463 CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I64_A64_S
7464 CEFBS_HasAtomics, // ATOMIC_RMW_OR_I32_A32
7465 CEFBS_HasAtomics, // ATOMIC_RMW_OR_I32_A32_S
7466 CEFBS_HasAtomics, // ATOMIC_RMW_OR_I32_A64
7467 CEFBS_HasAtomics, // ATOMIC_RMW_OR_I32_A64_S
7468 CEFBS_HasAtomics, // ATOMIC_RMW_OR_I64_A32
7469 CEFBS_HasAtomics, // ATOMIC_RMW_OR_I64_A32_S
7470 CEFBS_HasAtomics, // ATOMIC_RMW_OR_I64_A64
7471 CEFBS_HasAtomics, // ATOMIC_RMW_OR_I64_A64_S
7472 CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I32_A32
7473 CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I32_A32_S
7474 CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I32_A64
7475 CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I32_A64_S
7476 CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I64_A32
7477 CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I64_A32_S
7478 CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I64_A64
7479 CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I64_A64_S
7480 CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I32_A32
7481 CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I32_A32_S
7482 CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I32_A64
7483 CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I32_A64_S
7484 CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I64_A32
7485 CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I64_A32_S
7486 CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I64_A64
7487 CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I64_A64_S
7488 CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I32_A32
7489 CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I32_A32_S
7490 CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I32_A64
7491 CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I32_A64_S
7492 CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I64_A32
7493 CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I64_A32_S
7494 CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I64_A64
7495 CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I64_A64_S
7496 CEFBS_HasAtomics, // ATOMIC_STORE16_I32_A32
7497 CEFBS_HasAtomics, // ATOMIC_STORE16_I32_A32_S
7498 CEFBS_HasAtomics, // ATOMIC_STORE16_I32_A64
7499 CEFBS_HasAtomics, // ATOMIC_STORE16_I32_A64_S
7500 CEFBS_HasAtomics, // ATOMIC_STORE16_I64_A32
7501 CEFBS_HasAtomics, // ATOMIC_STORE16_I64_A32_S
7502 CEFBS_HasAtomics, // ATOMIC_STORE16_I64_A64
7503 CEFBS_HasAtomics, // ATOMIC_STORE16_I64_A64_S
7504 CEFBS_HasAtomics, // ATOMIC_STORE32_I64_A32
7505 CEFBS_HasAtomics, // ATOMIC_STORE32_I64_A32_S
7506 CEFBS_HasAtomics, // ATOMIC_STORE32_I64_A64
7507 CEFBS_HasAtomics, // ATOMIC_STORE32_I64_A64_S
7508 CEFBS_HasAtomics, // ATOMIC_STORE8_I32_A32
7509 CEFBS_HasAtomics, // ATOMIC_STORE8_I32_A32_S
7510 CEFBS_HasAtomics, // ATOMIC_STORE8_I32_A64
7511 CEFBS_HasAtomics, // ATOMIC_STORE8_I32_A64_S
7512 CEFBS_HasAtomics, // ATOMIC_STORE8_I64_A32
7513 CEFBS_HasAtomics, // ATOMIC_STORE8_I64_A32_S
7514 CEFBS_HasAtomics, // ATOMIC_STORE8_I64_A64
7515 CEFBS_HasAtomics, // ATOMIC_STORE8_I64_A64_S
7516 CEFBS_HasAtomics, // ATOMIC_STORE_I32_A32
7517 CEFBS_HasAtomics, // ATOMIC_STORE_I32_A32_S
7518 CEFBS_HasAtomics, // ATOMIC_STORE_I32_A64
7519 CEFBS_HasAtomics, // ATOMIC_STORE_I32_A64_S
7520 CEFBS_HasAtomics, // ATOMIC_STORE_I64_A32
7521 CEFBS_HasAtomics, // ATOMIC_STORE_I64_A32_S
7522 CEFBS_HasAtomics, // ATOMIC_STORE_I64_A64
7523 CEFBS_HasAtomics, // ATOMIC_STORE_I64_A64_S
7524 CEFBS_HasSIMD128, // AVGR_U_I16x8
7525 CEFBS_HasSIMD128, // AVGR_U_I16x8_S
7526 CEFBS_HasSIMD128, // AVGR_U_I8x16
7527 CEFBS_HasSIMD128, // AVGR_U_I8x16_S
7528 CEFBS_HasSIMD128, // BITMASK_I16x8
7529 CEFBS_HasSIMD128, // BITMASK_I16x8_S
7530 CEFBS_HasSIMD128, // BITMASK_I32x4
7531 CEFBS_HasSIMD128, // BITMASK_I32x4_S
7532 CEFBS_HasSIMD128, // BITMASK_I64x2
7533 CEFBS_HasSIMD128, // BITMASK_I64x2_S
7534 CEFBS_HasSIMD128, // BITMASK_I8x16
7535 CEFBS_HasSIMD128, // BITMASK_I8x16_S
7536 CEFBS_HasSIMD128, // BITSELECT
7537 CEFBS_HasSIMD128, // BITSELECT_S
7538 CEFBS_None, // BLOCK
7539 CEFBS_None, // BLOCK_S
7540 CEFBS_None, // BR
7541 CEFBS_None, // BR_IF
7542 CEFBS_None, // BR_IF_S
7543 CEFBS_None, // BR_S
7544 CEFBS_None, // BR_TABLE_I32
7545 CEFBS_None, // BR_TABLE_I32_S
7546 CEFBS_None, // BR_TABLE_I64
7547 CEFBS_None, // BR_TABLE_I64_S
7548 CEFBS_None, // BR_UNLESS
7549 CEFBS_None, // BR_UNLESS_S
7550 CEFBS_None, // CALL
7551 CEFBS_None, // CALL_INDIRECT
7552 CEFBS_None, // CALL_INDIRECT_S
7553 CEFBS_HasGC, // CALL_REF
7554 CEFBS_HasGC, // CALL_REF_S
7555 CEFBS_None, // CALL_S
7556 CEFBS_HasExceptionHandling, // CATCH
7557 CEFBS_HasExceptionHandling, // CATCH_ALL
7558 CEFBS_HasExceptionHandling, // CATCH_ALL_LEGACY
7559 CEFBS_HasExceptionHandling, // CATCH_ALL_LEGACY_S
7560 CEFBS_HasExceptionHandling, // CATCH_ALL_REF
7561 CEFBS_HasExceptionHandling, // CATCH_ALL_REF_S
7562 CEFBS_HasExceptionHandling, // CATCH_ALL_S
7563 CEFBS_HasExceptionHandling, // CATCH_LEGACY
7564 CEFBS_HasExceptionHandling, // CATCH_LEGACY_S
7565 CEFBS_HasExceptionHandling, // CATCH_REF
7566 CEFBS_HasExceptionHandling, // CATCH_REF_S
7567 CEFBS_HasExceptionHandling, // CATCH_S
7568 CEFBS_HasSIMD128_HasFP16, // CEIL_F16x8
7569 CEFBS_HasSIMD128_HasFP16, // CEIL_F16x8_S
7570 CEFBS_None, // CEIL_F32
7571 CEFBS_None, // CEIL_F32_S
7572 CEFBS_HasSIMD128, // CEIL_F32x4
7573 CEFBS_HasSIMD128, // CEIL_F32x4_S
7574 CEFBS_None, // CEIL_F64
7575 CEFBS_None, // CEIL_F64_S
7576 CEFBS_HasSIMD128, // CEIL_F64x2
7577 CEFBS_HasSIMD128, // CEIL_F64x2_S
7578 CEFBS_None, // CLZ_I32
7579 CEFBS_None, // CLZ_I32_S
7580 CEFBS_None, // CLZ_I64
7581 CEFBS_None, // CLZ_I64_S
7582 CEFBS_None, // CONST_F32
7583 CEFBS_None, // CONST_F32_S
7584 CEFBS_None, // CONST_F64
7585 CEFBS_None, // CONST_F64_S
7586 CEFBS_None, // CONST_I32
7587 CEFBS_None, // CONST_I32_S
7588 CEFBS_None, // CONST_I64
7589 CEFBS_None, // CONST_I64_S
7590 CEFBS_HasSIMD128, // CONST_V128_F32x4
7591 CEFBS_HasSIMD128, // CONST_V128_F32x4_S
7592 CEFBS_HasSIMD128, // CONST_V128_F64x2
7593 CEFBS_HasSIMD128, // CONST_V128_F64x2_S
7594 CEFBS_HasSIMD128, // CONST_V128_I16x8
7595 CEFBS_HasSIMD128, // CONST_V128_I16x8_S
7596 CEFBS_HasSIMD128, // CONST_V128_I32x4
7597 CEFBS_HasSIMD128, // CONST_V128_I32x4_S
7598 CEFBS_HasSIMD128, // CONST_V128_I64x2
7599 CEFBS_HasSIMD128, // CONST_V128_I64x2_S
7600 CEFBS_HasSIMD128, // CONST_V128_I8x16
7601 CEFBS_HasSIMD128, // CONST_V128_I8x16_S
7602 CEFBS_None, // COPYSIGN_F32
7603 CEFBS_None, // COPYSIGN_F32_S
7604 CEFBS_None, // COPYSIGN_F64
7605 CEFBS_None, // COPYSIGN_F64_S
7606 CEFBS_HasReferenceTypes_HasExceptionHandling, // COPY_EXNREF
7607 CEFBS_HasReferenceTypes_HasExceptionHandling, // COPY_EXNREF_S
7608 CEFBS_HasReferenceTypes, // COPY_EXTERNREF
7609 CEFBS_HasReferenceTypes, // COPY_EXTERNREF_S
7610 CEFBS_None, // COPY_F32
7611 CEFBS_None, // COPY_F32_S
7612 CEFBS_None, // COPY_F64
7613 CEFBS_None, // COPY_F64_S
7614 CEFBS_HasReferenceTypes, // COPY_FUNCREF
7615 CEFBS_HasReferenceTypes, // COPY_FUNCREF_S
7616 CEFBS_None, // COPY_I32
7617 CEFBS_None, // COPY_I32_S
7618 CEFBS_None, // COPY_I64
7619 CEFBS_None, // COPY_I64_S
7620 CEFBS_HasSIMD128, // COPY_V128
7621 CEFBS_HasSIMD128, // COPY_V128_S
7622 CEFBS_None, // CTZ_I32
7623 CEFBS_None, // CTZ_I32_S
7624 CEFBS_None, // CTZ_I64
7625 CEFBS_None, // CTZ_I64_S
7626 CEFBS_HasBulkMemoryOpt, // DATA_DROP
7627 CEFBS_HasBulkMemoryOpt, // DATA_DROP_S
7628 CEFBS_None, // DEBUG_UNREACHABLE
7629 CEFBS_None, // DEBUG_UNREACHABLE_S
7630 CEFBS_HasExceptionHandling, // DELEGATE
7631 CEFBS_HasExceptionHandling, // DELEGATE_S
7632 CEFBS_HasSIMD128_HasFP16, // DIV_F16x8
7633 CEFBS_HasSIMD128_HasFP16, // DIV_F16x8_S
7634 CEFBS_None, // DIV_F32
7635 CEFBS_None, // DIV_F32_S
7636 CEFBS_HasSIMD128, // DIV_F32x4
7637 CEFBS_HasSIMD128, // DIV_F32x4_S
7638 CEFBS_None, // DIV_F64
7639 CEFBS_None, // DIV_F64_S
7640 CEFBS_HasSIMD128, // DIV_F64x2
7641 CEFBS_HasSIMD128, // DIV_F64x2_S
7642 CEFBS_None, // DIV_S_I32
7643 CEFBS_None, // DIV_S_I32_S
7644 CEFBS_None, // DIV_S_I64
7645 CEFBS_None, // DIV_S_I64_S
7646 CEFBS_None, // DIV_U_I32
7647 CEFBS_None, // DIV_U_I32_S
7648 CEFBS_None, // DIV_U_I64
7649 CEFBS_None, // DIV_U_I64_S
7650 CEFBS_HasSIMD128, // DOT
7651 CEFBS_HasSIMD128, // DOT_S
7652 CEFBS_HasReferenceTypes_HasExceptionHandling, // DROP_EXNREF
7653 CEFBS_HasReferenceTypes_HasExceptionHandling, // DROP_EXNREF_S
7654 CEFBS_HasReferenceTypes, // DROP_EXTERNREF
7655 CEFBS_HasReferenceTypes, // DROP_EXTERNREF_S
7656 CEFBS_None, // DROP_F32
7657 CEFBS_None, // DROP_F32_S
7658 CEFBS_None, // DROP_F64
7659 CEFBS_None, // DROP_F64_S
7660 CEFBS_HasReferenceTypes, // DROP_FUNCREF
7661 CEFBS_HasReferenceTypes, // DROP_FUNCREF_S
7662 CEFBS_None, // DROP_I32
7663 CEFBS_None, // DROP_I32_S
7664 CEFBS_None, // DROP_I64
7665 CEFBS_None, // DROP_I64_S
7666 CEFBS_HasSIMD128, // DROP_V128
7667 CEFBS_HasSIMD128, // DROP_V128_S
7668 CEFBS_None, // ELSE
7669 CEFBS_None, // ELSE_S
7670 CEFBS_None, // END
7671 CEFBS_None, // END_BLOCK
7672 CEFBS_None, // END_BLOCK_S
7673 CEFBS_None, // END_FUNCTION
7674 CEFBS_None, // END_FUNCTION_S
7675 CEFBS_None, // END_IF
7676 CEFBS_None, // END_IF_S
7677 CEFBS_None, // END_LOOP
7678 CEFBS_None, // END_LOOP_S
7679 CEFBS_None, // END_S
7680 CEFBS_HasExceptionHandling, // END_TRY
7681 CEFBS_HasExceptionHandling, // END_TRY_S
7682 CEFBS_HasExceptionHandling, // END_TRY_TABLE
7683 CEFBS_HasExceptionHandling, // END_TRY_TABLE_S
7684 CEFBS_None, // EQZ_I32
7685 CEFBS_None, // EQZ_I32_S
7686 CEFBS_None, // EQZ_I64
7687 CEFBS_None, // EQZ_I64_S
7688 CEFBS_HasSIMD128_HasFP16, // EQ_F16x8
7689 CEFBS_HasSIMD128_HasFP16, // EQ_F16x8_S
7690 CEFBS_None, // EQ_F32
7691 CEFBS_None, // EQ_F32_S
7692 CEFBS_HasSIMD128, // EQ_F32x4
7693 CEFBS_HasSIMD128, // EQ_F32x4_S
7694 CEFBS_None, // EQ_F64
7695 CEFBS_None, // EQ_F64_S
7696 CEFBS_HasSIMD128, // EQ_F64x2
7697 CEFBS_HasSIMD128, // EQ_F64x2_S
7698 CEFBS_HasSIMD128, // EQ_I16x8
7699 CEFBS_HasSIMD128, // EQ_I16x8_S
7700 CEFBS_None, // EQ_I32
7701 CEFBS_None, // EQ_I32_S
7702 CEFBS_HasSIMD128, // EQ_I32x4
7703 CEFBS_HasSIMD128, // EQ_I32x4_S
7704 CEFBS_None, // EQ_I64
7705 CEFBS_None, // EQ_I64_S
7706 CEFBS_HasSIMD128, // EQ_I64x2
7707 CEFBS_HasSIMD128, // EQ_I64x2_S
7708 CEFBS_HasSIMD128, // EQ_I8x16
7709 CEFBS_HasSIMD128, // EQ_I8x16_S
7710 CEFBS_HasSIMD128, // EXTMUL_HIGH_S_I16x8
7711 CEFBS_HasSIMD128, // EXTMUL_HIGH_S_I16x8_S
7712 CEFBS_HasSIMD128, // EXTMUL_HIGH_S_I32x4
7713 CEFBS_HasSIMD128, // EXTMUL_HIGH_S_I32x4_S
7714 CEFBS_HasSIMD128, // EXTMUL_HIGH_S_I64x2
7715 CEFBS_HasSIMD128, // EXTMUL_HIGH_S_I64x2_S
7716 CEFBS_HasSIMD128, // EXTMUL_HIGH_U_I16x8
7717 CEFBS_HasSIMD128, // EXTMUL_HIGH_U_I16x8_S
7718 CEFBS_HasSIMD128, // EXTMUL_HIGH_U_I32x4
7719 CEFBS_HasSIMD128, // EXTMUL_HIGH_U_I32x4_S
7720 CEFBS_HasSIMD128, // EXTMUL_HIGH_U_I64x2
7721 CEFBS_HasSIMD128, // EXTMUL_HIGH_U_I64x2_S
7722 CEFBS_HasSIMD128, // EXTMUL_LOW_S_I16x8
7723 CEFBS_HasSIMD128, // EXTMUL_LOW_S_I16x8_S
7724 CEFBS_HasSIMD128, // EXTMUL_LOW_S_I32x4
7725 CEFBS_HasSIMD128, // EXTMUL_LOW_S_I32x4_S
7726 CEFBS_HasSIMD128, // EXTMUL_LOW_S_I64x2
7727 CEFBS_HasSIMD128, // EXTMUL_LOW_S_I64x2_S
7728 CEFBS_HasSIMD128, // EXTMUL_LOW_U_I16x8
7729 CEFBS_HasSIMD128, // EXTMUL_LOW_U_I16x8_S
7730 CEFBS_HasSIMD128, // EXTMUL_LOW_U_I32x4
7731 CEFBS_HasSIMD128, // EXTMUL_LOW_U_I32x4_S
7732 CEFBS_HasSIMD128, // EXTMUL_LOW_U_I64x2
7733 CEFBS_HasSIMD128, // EXTMUL_LOW_U_I64x2_S
7734 CEFBS_HasFP16, // EXTRACT_LANE_F16x8
7735 CEFBS_HasFP16, // EXTRACT_LANE_F16x8_S
7736 CEFBS_HasSIMD128, // EXTRACT_LANE_F32x4
7737 CEFBS_HasSIMD128, // EXTRACT_LANE_F32x4_S
7738 CEFBS_HasSIMD128, // EXTRACT_LANE_F64x2
7739 CEFBS_HasSIMD128, // EXTRACT_LANE_F64x2_S
7740 CEFBS_HasSIMD128, // EXTRACT_LANE_I16x8_s
7741 CEFBS_HasSIMD128, // EXTRACT_LANE_I16x8_s_S
7742 CEFBS_HasSIMD128, // EXTRACT_LANE_I16x8_u
7743 CEFBS_HasSIMD128, // EXTRACT_LANE_I16x8_u_S
7744 CEFBS_HasSIMD128, // EXTRACT_LANE_I32x4
7745 CEFBS_HasSIMD128, // EXTRACT_LANE_I32x4_S
7746 CEFBS_HasSIMD128, // EXTRACT_LANE_I64x2
7747 CEFBS_HasSIMD128, // EXTRACT_LANE_I64x2_S
7748 CEFBS_HasSIMD128, // EXTRACT_LANE_I8x16_s
7749 CEFBS_HasSIMD128, // EXTRACT_LANE_I8x16_s_S
7750 CEFBS_HasSIMD128, // EXTRACT_LANE_I8x16_u
7751 CEFBS_HasSIMD128, // EXTRACT_LANE_I8x16_u_S
7752 CEFBS_None, // F32_CONVERT_S_I32
7753 CEFBS_None, // F32_CONVERT_S_I32_S
7754 CEFBS_None, // F32_CONVERT_S_I64
7755 CEFBS_None, // F32_CONVERT_S_I64_S
7756 CEFBS_None, // F32_CONVERT_U_I32
7757 CEFBS_None, // F32_CONVERT_U_I32_S
7758 CEFBS_None, // F32_CONVERT_U_I64
7759 CEFBS_None, // F32_CONVERT_U_I64_S
7760 CEFBS_None, // F32_DEMOTE_F64
7761 CEFBS_None, // F32_DEMOTE_F64_S
7762 CEFBS_None, // F32_REINTERPRET_I32
7763 CEFBS_None, // F32_REINTERPRET_I32_S
7764 CEFBS_None, // F64_CONVERT_S_I32
7765 CEFBS_None, // F64_CONVERT_S_I32_S
7766 CEFBS_None, // F64_CONVERT_S_I64
7767 CEFBS_None, // F64_CONVERT_S_I64_S
7768 CEFBS_None, // F64_CONVERT_U_I32
7769 CEFBS_None, // F64_CONVERT_U_I32_S
7770 CEFBS_None, // F64_CONVERT_U_I64
7771 CEFBS_None, // F64_CONVERT_U_I64_S
7772 CEFBS_None, // F64_PROMOTE_F32
7773 CEFBS_None, // F64_PROMOTE_F32_S
7774 CEFBS_None, // F64_REINTERPRET_I64
7775 CEFBS_None, // F64_REINTERPRET_I64_S
7776 CEFBS_None, // FALLTHROUGH_RETURN
7777 CEFBS_None, // FALLTHROUGH_RETURN_S
7778 CEFBS_HasSIMD128_HasFP16, // FLOOR_F16x8
7779 CEFBS_HasSIMD128_HasFP16, // FLOOR_F16x8_S
7780 CEFBS_None, // FLOOR_F32
7781 CEFBS_None, // FLOOR_F32_S
7782 CEFBS_HasSIMD128, // FLOOR_F32x4
7783 CEFBS_HasSIMD128, // FLOOR_F32x4_S
7784 CEFBS_None, // FLOOR_F64
7785 CEFBS_None, // FLOOR_F64_S
7786 CEFBS_HasSIMD128, // FLOOR_F64x2
7787 CEFBS_HasSIMD128, // FLOOR_F64x2_S
7788 CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I32_F32
7789 CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I32_F32_S
7790 CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I32_F64
7791 CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I32_F64_S
7792 CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I64_F32
7793 CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I64_F32_S
7794 CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I64_F64
7795 CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I64_F64_S
7796 CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I32_F32
7797 CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I32_F32_S
7798 CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I32_F64
7799 CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I32_F64_S
7800 CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I64_F32
7801 CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I64_F32_S
7802 CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I64_F64
7803 CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I64_F64_S
7804 CEFBS_HasSIMD128_HasFP16, // GE_F16x8
7805 CEFBS_HasSIMD128_HasFP16, // GE_F16x8_S
7806 CEFBS_None, // GE_F32
7807 CEFBS_None, // GE_F32_S
7808 CEFBS_HasSIMD128, // GE_F32x4
7809 CEFBS_HasSIMD128, // GE_F32x4_S
7810 CEFBS_None, // GE_F64
7811 CEFBS_None, // GE_F64_S
7812 CEFBS_HasSIMD128, // GE_F64x2
7813 CEFBS_HasSIMD128, // GE_F64x2_S
7814 CEFBS_HasSIMD128, // GE_S_I16x8
7815 CEFBS_HasSIMD128, // GE_S_I16x8_S
7816 CEFBS_None, // GE_S_I32
7817 CEFBS_None, // GE_S_I32_S
7818 CEFBS_HasSIMD128, // GE_S_I32x4
7819 CEFBS_HasSIMD128, // GE_S_I32x4_S
7820 CEFBS_None, // GE_S_I64
7821 CEFBS_None, // GE_S_I64_S
7822 CEFBS_HasSIMD128, // GE_S_I64x2
7823 CEFBS_HasSIMD128, // GE_S_I64x2_S
7824 CEFBS_HasSIMD128, // GE_S_I8x16
7825 CEFBS_HasSIMD128, // GE_S_I8x16_S
7826 CEFBS_HasSIMD128, // GE_U_I16x8
7827 CEFBS_HasSIMD128, // GE_U_I16x8_S
7828 CEFBS_None, // GE_U_I32
7829 CEFBS_None, // GE_U_I32_S
7830 CEFBS_HasSIMD128, // GE_U_I32x4
7831 CEFBS_HasSIMD128, // GE_U_I32x4_S
7832 CEFBS_None, // GE_U_I64
7833 CEFBS_None, // GE_U_I64_S
7834 CEFBS_HasSIMD128, // GE_U_I8x16
7835 CEFBS_HasSIMD128, // GE_U_I8x16_S
7836 CEFBS_HasReferenceTypes_HasExceptionHandling, // GLOBAL_GET_EXNREF
7837 CEFBS_HasReferenceTypes_HasExceptionHandling, // GLOBAL_GET_EXNREF_S
7838 CEFBS_HasReferenceTypes, // GLOBAL_GET_EXTERNREF
7839 CEFBS_HasReferenceTypes, // GLOBAL_GET_EXTERNREF_S
7840 CEFBS_None, // GLOBAL_GET_F32
7841 CEFBS_None, // GLOBAL_GET_F32_S
7842 CEFBS_None, // GLOBAL_GET_F64
7843 CEFBS_None, // GLOBAL_GET_F64_S
7844 CEFBS_HasReferenceTypes, // GLOBAL_GET_FUNCREF
7845 CEFBS_HasReferenceTypes, // GLOBAL_GET_FUNCREF_S
7846 CEFBS_None, // GLOBAL_GET_I32
7847 CEFBS_None, // GLOBAL_GET_I32_S
7848 CEFBS_None, // GLOBAL_GET_I64
7849 CEFBS_None, // GLOBAL_GET_I64_S
7850 CEFBS_HasSIMD128, // GLOBAL_GET_V128
7851 CEFBS_HasSIMD128, // GLOBAL_GET_V128_S
7852 CEFBS_HasReferenceTypes_HasExceptionHandling, // GLOBAL_SET_EXNREF
7853 CEFBS_HasReferenceTypes_HasExceptionHandling, // GLOBAL_SET_EXNREF_S
7854 CEFBS_HasReferenceTypes, // GLOBAL_SET_EXTERNREF
7855 CEFBS_HasReferenceTypes, // GLOBAL_SET_EXTERNREF_S
7856 CEFBS_None, // GLOBAL_SET_F32
7857 CEFBS_None, // GLOBAL_SET_F32_S
7858 CEFBS_None, // GLOBAL_SET_F64
7859 CEFBS_None, // GLOBAL_SET_F64_S
7860 CEFBS_HasReferenceTypes, // GLOBAL_SET_FUNCREF
7861 CEFBS_HasReferenceTypes, // GLOBAL_SET_FUNCREF_S
7862 CEFBS_None, // GLOBAL_SET_I32
7863 CEFBS_None, // GLOBAL_SET_I32_S
7864 CEFBS_None, // GLOBAL_SET_I64
7865 CEFBS_None, // GLOBAL_SET_I64_S
7866 CEFBS_HasSIMD128, // GLOBAL_SET_V128
7867 CEFBS_HasSIMD128, // GLOBAL_SET_V128_S
7868 CEFBS_HasSIMD128_HasFP16, // GT_F16x8
7869 CEFBS_HasSIMD128_HasFP16, // GT_F16x8_S
7870 CEFBS_None, // GT_F32
7871 CEFBS_None, // GT_F32_S
7872 CEFBS_HasSIMD128, // GT_F32x4
7873 CEFBS_HasSIMD128, // GT_F32x4_S
7874 CEFBS_None, // GT_F64
7875 CEFBS_None, // GT_F64_S
7876 CEFBS_HasSIMD128, // GT_F64x2
7877 CEFBS_HasSIMD128, // GT_F64x2_S
7878 CEFBS_HasSIMD128, // GT_S_I16x8
7879 CEFBS_HasSIMD128, // GT_S_I16x8_S
7880 CEFBS_None, // GT_S_I32
7881 CEFBS_None, // GT_S_I32_S
7882 CEFBS_HasSIMD128, // GT_S_I32x4
7883 CEFBS_HasSIMD128, // GT_S_I32x4_S
7884 CEFBS_None, // GT_S_I64
7885 CEFBS_None, // GT_S_I64_S
7886 CEFBS_HasSIMD128, // GT_S_I64x2
7887 CEFBS_HasSIMD128, // GT_S_I64x2_S
7888 CEFBS_HasSIMD128, // GT_S_I8x16
7889 CEFBS_HasSIMD128, // GT_S_I8x16_S
7890 CEFBS_HasSIMD128, // GT_U_I16x8
7891 CEFBS_HasSIMD128, // GT_U_I16x8_S
7892 CEFBS_None, // GT_U_I32
7893 CEFBS_None, // GT_U_I32_S
7894 CEFBS_HasSIMD128, // GT_U_I32x4
7895 CEFBS_HasSIMD128, // GT_U_I32x4_S
7896 CEFBS_None, // GT_U_I64
7897 CEFBS_None, // GT_U_I64_S
7898 CEFBS_HasSIMD128, // GT_U_I8x16
7899 CEFBS_HasSIMD128, // GT_U_I8x16_S
7900 CEFBS_HasSignExt, // I32_EXTEND16_S_I32
7901 CEFBS_HasSignExt, // I32_EXTEND16_S_I32_S
7902 CEFBS_HasSignExt, // I32_EXTEND8_S_I32
7903 CEFBS_HasSignExt, // I32_EXTEND8_S_I32_S
7904 CEFBS_None, // I32_REINTERPRET_F32
7905 CEFBS_None, // I32_REINTERPRET_F32_S
7906 CEFBS_None, // I32_TRUNC_S_F32
7907 CEFBS_None, // I32_TRUNC_S_F32_S
7908 CEFBS_None, // I32_TRUNC_S_F64
7909 CEFBS_None, // I32_TRUNC_S_F64_S
7910 CEFBS_HasNontrappingFPToInt, // I32_TRUNC_S_SAT_F32
7911 CEFBS_HasNontrappingFPToInt, // I32_TRUNC_S_SAT_F32_S
7912 CEFBS_HasNontrappingFPToInt, // I32_TRUNC_S_SAT_F64
7913 CEFBS_HasNontrappingFPToInt, // I32_TRUNC_S_SAT_F64_S
7914 CEFBS_None, // I32_TRUNC_U_F32
7915 CEFBS_None, // I32_TRUNC_U_F32_S
7916 CEFBS_None, // I32_TRUNC_U_F64
7917 CEFBS_None, // I32_TRUNC_U_F64_S
7918 CEFBS_HasNontrappingFPToInt, // I32_TRUNC_U_SAT_F32
7919 CEFBS_HasNontrappingFPToInt, // I32_TRUNC_U_SAT_F32_S
7920 CEFBS_HasNontrappingFPToInt, // I32_TRUNC_U_SAT_F64
7921 CEFBS_HasNontrappingFPToInt, // I32_TRUNC_U_SAT_F64_S
7922 CEFBS_None, // I32_WRAP_I64
7923 CEFBS_None, // I32_WRAP_I64_S
7924 CEFBS_HasWideArithmetic, // I64_ADD128
7925 CEFBS_HasWideArithmetic, // I64_ADD128_S
7926 CEFBS_HasSignExt, // I64_EXTEND16_S_I64
7927 CEFBS_HasSignExt, // I64_EXTEND16_S_I64_S
7928 CEFBS_HasSignExt, // I64_EXTEND32_S_I64
7929 CEFBS_HasSignExt, // I64_EXTEND32_S_I64_S
7930 CEFBS_HasSignExt, // I64_EXTEND8_S_I64
7931 CEFBS_HasSignExt, // I64_EXTEND8_S_I64_S
7932 CEFBS_None, // I64_EXTEND_S_I32
7933 CEFBS_None, // I64_EXTEND_S_I32_S
7934 CEFBS_None, // I64_EXTEND_U_I32
7935 CEFBS_None, // I64_EXTEND_U_I32_S
7936 CEFBS_HasWideArithmetic, // I64_MUL_WIDE_S
7937 CEFBS_HasWideArithmetic, // I64_MUL_WIDE_S_S
7938 CEFBS_HasWideArithmetic, // I64_MUL_WIDE_U
7939 CEFBS_HasWideArithmetic, // I64_MUL_WIDE_U_S
7940 CEFBS_None, // I64_REINTERPRET_F64
7941 CEFBS_None, // I64_REINTERPRET_F64_S
7942 CEFBS_HasWideArithmetic, // I64_SUB128
7943 CEFBS_HasWideArithmetic, // I64_SUB128_S
7944 CEFBS_None, // I64_TRUNC_S_F32
7945 CEFBS_None, // I64_TRUNC_S_F32_S
7946 CEFBS_None, // I64_TRUNC_S_F64
7947 CEFBS_None, // I64_TRUNC_S_F64_S
7948 CEFBS_HasNontrappingFPToInt, // I64_TRUNC_S_SAT_F32
7949 CEFBS_HasNontrappingFPToInt, // I64_TRUNC_S_SAT_F32_S
7950 CEFBS_HasNontrappingFPToInt, // I64_TRUNC_S_SAT_F64
7951 CEFBS_HasNontrappingFPToInt, // I64_TRUNC_S_SAT_F64_S
7952 CEFBS_None, // I64_TRUNC_U_F32
7953 CEFBS_None, // I64_TRUNC_U_F32_S
7954 CEFBS_None, // I64_TRUNC_U_F64
7955 CEFBS_None, // I64_TRUNC_U_F64_S
7956 CEFBS_HasNontrappingFPToInt, // I64_TRUNC_U_SAT_F32
7957 CEFBS_HasNontrappingFPToInt, // I64_TRUNC_U_SAT_F32_S
7958 CEFBS_HasNontrappingFPToInt, // I64_TRUNC_U_SAT_F64
7959 CEFBS_HasNontrappingFPToInt, // I64_TRUNC_U_SAT_F64_S
7960 CEFBS_None, // IF
7961 CEFBS_None, // IF_S
7962 CEFBS_HasRelaxedSIMD, // LANESELECT_I16x8
7963 CEFBS_HasRelaxedSIMD, // LANESELECT_I16x8_S
7964 CEFBS_HasRelaxedSIMD, // LANESELECT_I32x4
7965 CEFBS_HasRelaxedSIMD, // LANESELECT_I32x4_S
7966 CEFBS_HasRelaxedSIMD, // LANESELECT_I64x2
7967 CEFBS_HasRelaxedSIMD, // LANESELECT_I64x2_S
7968 CEFBS_HasRelaxedSIMD, // LANESELECT_I8x16
7969 CEFBS_HasRelaxedSIMD, // LANESELECT_I8x16_S
7970 CEFBS_HasSIMD128_HasFP16, // LE_F16x8
7971 CEFBS_HasSIMD128_HasFP16, // LE_F16x8_S
7972 CEFBS_None, // LE_F32
7973 CEFBS_None, // LE_F32_S
7974 CEFBS_HasSIMD128, // LE_F32x4
7975 CEFBS_HasSIMD128, // LE_F32x4_S
7976 CEFBS_None, // LE_F64
7977 CEFBS_None, // LE_F64_S
7978 CEFBS_HasSIMD128, // LE_F64x2
7979 CEFBS_HasSIMD128, // LE_F64x2_S
7980 CEFBS_HasSIMD128, // LE_S_I16x8
7981 CEFBS_HasSIMD128, // LE_S_I16x8_S
7982 CEFBS_None, // LE_S_I32
7983 CEFBS_None, // LE_S_I32_S
7984 CEFBS_HasSIMD128, // LE_S_I32x4
7985 CEFBS_HasSIMD128, // LE_S_I32x4_S
7986 CEFBS_None, // LE_S_I64
7987 CEFBS_None, // LE_S_I64_S
7988 CEFBS_HasSIMD128, // LE_S_I64x2
7989 CEFBS_HasSIMD128, // LE_S_I64x2_S
7990 CEFBS_HasSIMD128, // LE_S_I8x16
7991 CEFBS_HasSIMD128, // LE_S_I8x16_S
7992 CEFBS_HasSIMD128, // LE_U_I16x8
7993 CEFBS_HasSIMD128, // LE_U_I16x8_S
7994 CEFBS_None, // LE_U_I32
7995 CEFBS_None, // LE_U_I32_S
7996 CEFBS_HasSIMD128, // LE_U_I32x4
7997 CEFBS_HasSIMD128, // LE_U_I32x4_S
7998 CEFBS_None, // LE_U_I64
7999 CEFBS_None, // LE_U_I64_S
8000 CEFBS_HasSIMD128, // LE_U_I8x16
8001 CEFBS_HasSIMD128, // LE_U_I8x16_S
8002 CEFBS_HasSIMD128, // LOAD16_SPLAT_A32
8003 CEFBS_HasSIMD128, // LOAD16_SPLAT_A32_S
8004 CEFBS_HasSIMD128, // LOAD16_SPLAT_A64
8005 CEFBS_HasSIMD128, // LOAD16_SPLAT_A64_S
8006 CEFBS_None, // LOAD16_S_I32_A32
8007 CEFBS_None, // LOAD16_S_I32_A32_S
8008 CEFBS_None, // LOAD16_S_I32_A64
8009 CEFBS_None, // LOAD16_S_I32_A64_S
8010 CEFBS_None, // LOAD16_S_I64_A32
8011 CEFBS_None, // LOAD16_S_I64_A32_S
8012 CEFBS_None, // LOAD16_S_I64_A64
8013 CEFBS_None, // LOAD16_S_I64_A64_S
8014 CEFBS_None, // LOAD16_U_I32_A32
8015 CEFBS_None, // LOAD16_U_I32_A32_S
8016 CEFBS_None, // LOAD16_U_I32_A64
8017 CEFBS_None, // LOAD16_U_I32_A64_S
8018 CEFBS_None, // LOAD16_U_I64_A32
8019 CEFBS_None, // LOAD16_U_I64_A32_S
8020 CEFBS_None, // LOAD16_U_I64_A64
8021 CEFBS_None, // LOAD16_U_I64_A64_S
8022 CEFBS_HasSIMD128, // LOAD32_SPLAT_A32
8023 CEFBS_HasSIMD128, // LOAD32_SPLAT_A32_S
8024 CEFBS_HasSIMD128, // LOAD32_SPLAT_A64
8025 CEFBS_HasSIMD128, // LOAD32_SPLAT_A64_S
8026 CEFBS_None, // LOAD32_S_I64_A32
8027 CEFBS_None, // LOAD32_S_I64_A32_S
8028 CEFBS_None, // LOAD32_S_I64_A64
8029 CEFBS_None, // LOAD32_S_I64_A64_S
8030 CEFBS_None, // LOAD32_U_I64_A32
8031 CEFBS_None, // LOAD32_U_I64_A32_S
8032 CEFBS_None, // LOAD32_U_I64_A64
8033 CEFBS_None, // LOAD32_U_I64_A64_S
8034 CEFBS_HasSIMD128, // LOAD64_SPLAT_A32
8035 CEFBS_HasSIMD128, // LOAD64_SPLAT_A32_S
8036 CEFBS_HasSIMD128, // LOAD64_SPLAT_A64
8037 CEFBS_HasSIMD128, // LOAD64_SPLAT_A64_S
8038 CEFBS_HasSIMD128, // LOAD8_SPLAT_A32
8039 CEFBS_HasSIMD128, // LOAD8_SPLAT_A32_S
8040 CEFBS_HasSIMD128, // LOAD8_SPLAT_A64
8041 CEFBS_HasSIMD128, // LOAD8_SPLAT_A64_S
8042 CEFBS_None, // LOAD8_S_I32_A32
8043 CEFBS_None, // LOAD8_S_I32_A32_S
8044 CEFBS_None, // LOAD8_S_I32_A64
8045 CEFBS_None, // LOAD8_S_I32_A64_S
8046 CEFBS_None, // LOAD8_S_I64_A32
8047 CEFBS_None, // LOAD8_S_I64_A32_S
8048 CEFBS_None, // LOAD8_S_I64_A64
8049 CEFBS_None, // LOAD8_S_I64_A64_S
8050 CEFBS_None, // LOAD8_U_I32_A32
8051 CEFBS_None, // LOAD8_U_I32_A32_S
8052 CEFBS_None, // LOAD8_U_I32_A64
8053 CEFBS_None, // LOAD8_U_I32_A64_S
8054 CEFBS_None, // LOAD8_U_I64_A32
8055 CEFBS_None, // LOAD8_U_I64_A32_S
8056 CEFBS_None, // LOAD8_U_I64_A64
8057 CEFBS_None, // LOAD8_U_I64_A64_S
8058 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I16x8_A32
8059 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I16x8_A32_S
8060 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I16x8_A64
8061 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I16x8_A64_S
8062 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I32x4_A32
8063 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I32x4_A32_S
8064 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I32x4_A64
8065 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I32x4_A64_S
8066 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I64x2_A32
8067 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I64x2_A32_S
8068 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I64x2_A64
8069 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I64x2_A64_S
8070 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I16x8_A32
8071 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I16x8_A32_S
8072 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I16x8_A64
8073 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I16x8_A64_S
8074 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I32x4_A32
8075 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I32x4_A32_S
8076 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I32x4_A64
8077 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I32x4_A64_S
8078 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I64x2_A32
8079 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I64x2_A32_S
8080 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I64x2_A64
8081 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I64x2_A64_S
8082 CEFBS_HasFP16, // LOAD_F16_F32_A32
8083 CEFBS_HasFP16, // LOAD_F16_F32_A32_S
8084 CEFBS_HasFP16, // LOAD_F16_F32_A64
8085 CEFBS_HasFP16, // LOAD_F16_F32_A64_S
8086 CEFBS_None, // LOAD_F32_A32
8087 CEFBS_None, // LOAD_F32_A32_S
8088 CEFBS_None, // LOAD_F32_A64
8089 CEFBS_None, // LOAD_F32_A64_S
8090 CEFBS_None, // LOAD_F64_A32
8091 CEFBS_None, // LOAD_F64_A32_S
8092 CEFBS_None, // LOAD_F64_A64
8093 CEFBS_None, // LOAD_F64_A64_S
8094 CEFBS_None, // LOAD_I32_A32
8095 CEFBS_None, // LOAD_I32_A32_S
8096 CEFBS_None, // LOAD_I32_A64
8097 CEFBS_None, // LOAD_I32_A64_S
8098 CEFBS_None, // LOAD_I64_A32
8099 CEFBS_None, // LOAD_I64_A32_S
8100 CEFBS_None, // LOAD_I64_A64
8101 CEFBS_None, // LOAD_I64_A64_S
8102 CEFBS_HasSIMD128, // LOAD_LANE_16_A32
8103 CEFBS_HasSIMD128, // LOAD_LANE_16_A32_S
8104 CEFBS_HasSIMD128, // LOAD_LANE_16_A64
8105 CEFBS_HasSIMD128, // LOAD_LANE_16_A64_S
8106 CEFBS_HasSIMD128, // LOAD_LANE_32_A32
8107 CEFBS_HasSIMD128, // LOAD_LANE_32_A32_S
8108 CEFBS_HasSIMD128, // LOAD_LANE_32_A64
8109 CEFBS_HasSIMD128, // LOAD_LANE_32_A64_S
8110 CEFBS_HasSIMD128, // LOAD_LANE_64_A32
8111 CEFBS_HasSIMD128, // LOAD_LANE_64_A32_S
8112 CEFBS_HasSIMD128, // LOAD_LANE_64_A64
8113 CEFBS_HasSIMD128, // LOAD_LANE_64_A64_S
8114 CEFBS_HasSIMD128, // LOAD_LANE_8_A32
8115 CEFBS_HasSIMD128, // LOAD_LANE_8_A32_S
8116 CEFBS_HasSIMD128, // LOAD_LANE_8_A64
8117 CEFBS_HasSIMD128, // LOAD_LANE_8_A64_S
8118 CEFBS_HasSIMD128, // LOAD_V128_A32
8119 CEFBS_HasSIMD128, // LOAD_V128_A32_S
8120 CEFBS_HasSIMD128, // LOAD_V128_A64
8121 CEFBS_HasSIMD128, // LOAD_V128_A64_S
8122 CEFBS_HasSIMD128, // LOAD_ZERO_32_A32
8123 CEFBS_HasSIMD128, // LOAD_ZERO_32_A32_S
8124 CEFBS_HasSIMD128, // LOAD_ZERO_32_A64
8125 CEFBS_HasSIMD128, // LOAD_ZERO_32_A64_S
8126 CEFBS_HasSIMD128, // LOAD_ZERO_64_A32
8127 CEFBS_HasSIMD128, // LOAD_ZERO_64_A32_S
8128 CEFBS_HasSIMD128, // LOAD_ZERO_64_A64
8129 CEFBS_HasSIMD128, // LOAD_ZERO_64_A64_S
8130 CEFBS_HasReferenceTypes_HasExceptionHandling, // LOCAL_GET_EXNREF
8131 CEFBS_HasReferenceTypes_HasExceptionHandling, // LOCAL_GET_EXNREF_S
8132 CEFBS_HasReferenceTypes, // LOCAL_GET_EXTERNREF
8133 CEFBS_HasReferenceTypes, // LOCAL_GET_EXTERNREF_S
8134 CEFBS_None, // LOCAL_GET_F32
8135 CEFBS_None, // LOCAL_GET_F32_S
8136 CEFBS_None, // LOCAL_GET_F64
8137 CEFBS_None, // LOCAL_GET_F64_S
8138 CEFBS_HasReferenceTypes, // LOCAL_GET_FUNCREF
8139 CEFBS_HasReferenceTypes, // LOCAL_GET_FUNCREF_S
8140 CEFBS_None, // LOCAL_GET_I32
8141 CEFBS_None, // LOCAL_GET_I32_S
8142 CEFBS_None, // LOCAL_GET_I64
8143 CEFBS_None, // LOCAL_GET_I64_S
8144 CEFBS_HasSIMD128, // LOCAL_GET_V128
8145 CEFBS_HasSIMD128, // LOCAL_GET_V128_S
8146 CEFBS_HasReferenceTypes_HasExceptionHandling, // LOCAL_SET_EXNREF
8147 CEFBS_HasReferenceTypes_HasExceptionHandling, // LOCAL_SET_EXNREF_S
8148 CEFBS_HasReferenceTypes, // LOCAL_SET_EXTERNREF
8149 CEFBS_HasReferenceTypes, // LOCAL_SET_EXTERNREF_S
8150 CEFBS_None, // LOCAL_SET_F32
8151 CEFBS_None, // LOCAL_SET_F32_S
8152 CEFBS_None, // LOCAL_SET_F64
8153 CEFBS_None, // LOCAL_SET_F64_S
8154 CEFBS_HasReferenceTypes, // LOCAL_SET_FUNCREF
8155 CEFBS_HasReferenceTypes, // LOCAL_SET_FUNCREF_S
8156 CEFBS_None, // LOCAL_SET_I32
8157 CEFBS_None, // LOCAL_SET_I32_S
8158 CEFBS_None, // LOCAL_SET_I64
8159 CEFBS_None, // LOCAL_SET_I64_S
8160 CEFBS_HasSIMD128, // LOCAL_SET_V128
8161 CEFBS_HasSIMD128, // LOCAL_SET_V128_S
8162 CEFBS_HasReferenceTypes_HasExceptionHandling, // LOCAL_TEE_EXNREF
8163 CEFBS_HasReferenceTypes_HasExceptionHandling, // LOCAL_TEE_EXNREF_S
8164 CEFBS_HasReferenceTypes, // LOCAL_TEE_EXTERNREF
8165 CEFBS_HasReferenceTypes, // LOCAL_TEE_EXTERNREF_S
8166 CEFBS_None, // LOCAL_TEE_F32
8167 CEFBS_None, // LOCAL_TEE_F32_S
8168 CEFBS_None, // LOCAL_TEE_F64
8169 CEFBS_None, // LOCAL_TEE_F64_S
8170 CEFBS_HasReferenceTypes, // LOCAL_TEE_FUNCREF
8171 CEFBS_HasReferenceTypes, // LOCAL_TEE_FUNCREF_S
8172 CEFBS_None, // LOCAL_TEE_I32
8173 CEFBS_None, // LOCAL_TEE_I32_S
8174 CEFBS_None, // LOCAL_TEE_I64
8175 CEFBS_None, // LOCAL_TEE_I64_S
8176 CEFBS_HasSIMD128, // LOCAL_TEE_V128
8177 CEFBS_HasSIMD128, // LOCAL_TEE_V128_S
8178 CEFBS_None, // LOOP
8179 CEFBS_None, // LOOP_S
8180 CEFBS_HasSIMD128_HasFP16, // LT_F16x8
8181 CEFBS_HasSIMD128_HasFP16, // LT_F16x8_S
8182 CEFBS_None, // LT_F32
8183 CEFBS_None, // LT_F32_S
8184 CEFBS_HasSIMD128, // LT_F32x4
8185 CEFBS_HasSIMD128, // LT_F32x4_S
8186 CEFBS_None, // LT_F64
8187 CEFBS_None, // LT_F64_S
8188 CEFBS_HasSIMD128, // LT_F64x2
8189 CEFBS_HasSIMD128, // LT_F64x2_S
8190 CEFBS_HasSIMD128, // LT_S_I16x8
8191 CEFBS_HasSIMD128, // LT_S_I16x8_S
8192 CEFBS_None, // LT_S_I32
8193 CEFBS_None, // LT_S_I32_S
8194 CEFBS_HasSIMD128, // LT_S_I32x4
8195 CEFBS_HasSIMD128, // LT_S_I32x4_S
8196 CEFBS_None, // LT_S_I64
8197 CEFBS_None, // LT_S_I64_S
8198 CEFBS_HasSIMD128, // LT_S_I64x2
8199 CEFBS_HasSIMD128, // LT_S_I64x2_S
8200 CEFBS_HasSIMD128, // LT_S_I8x16
8201 CEFBS_HasSIMD128, // LT_S_I8x16_S
8202 CEFBS_HasSIMD128, // LT_U_I16x8
8203 CEFBS_HasSIMD128, // LT_U_I16x8_S
8204 CEFBS_None, // LT_U_I32
8205 CEFBS_None, // LT_U_I32_S
8206 CEFBS_HasSIMD128, // LT_U_I32x4
8207 CEFBS_HasSIMD128, // LT_U_I32x4_S
8208 CEFBS_None, // LT_U_I64
8209 CEFBS_None, // LT_U_I64_S
8210 CEFBS_HasSIMD128, // LT_U_I8x16
8211 CEFBS_HasSIMD128, // LT_U_I8x16_S
8212 CEFBS_HasSIMD128_HasFP16, // MADD_F16x8
8213 CEFBS_HasSIMD128_HasFP16, // MADD_F16x8_S
8214 CEFBS_HasSIMD128_HasRelaxedSIMD, // MADD_F32x4
8215 CEFBS_HasSIMD128_HasRelaxedSIMD, // MADD_F32x4_S
8216 CEFBS_HasSIMD128_HasRelaxedSIMD, // MADD_F64x2
8217 CEFBS_HasSIMD128_HasRelaxedSIMD, // MADD_F64x2_S
8218 CEFBS_HasSIMD128_HasFP16, // MAX_F16x8
8219 CEFBS_HasSIMD128_HasFP16, // MAX_F16x8_S
8220 CEFBS_None, // MAX_F32
8221 CEFBS_None, // MAX_F32_S
8222 CEFBS_HasSIMD128, // MAX_F32x4
8223 CEFBS_HasSIMD128, // MAX_F32x4_S
8224 CEFBS_None, // MAX_F64
8225 CEFBS_None, // MAX_F64_S
8226 CEFBS_HasSIMD128, // MAX_F64x2
8227 CEFBS_HasSIMD128, // MAX_F64x2_S
8228 CEFBS_HasSIMD128, // MAX_S_I16x8
8229 CEFBS_HasSIMD128, // MAX_S_I16x8_S
8230 CEFBS_HasSIMD128, // MAX_S_I32x4
8231 CEFBS_HasSIMD128, // MAX_S_I32x4_S
8232 CEFBS_HasSIMD128, // MAX_S_I8x16
8233 CEFBS_HasSIMD128, // MAX_S_I8x16_S
8234 CEFBS_HasSIMD128, // MAX_U_I16x8
8235 CEFBS_HasSIMD128, // MAX_U_I16x8_S
8236 CEFBS_HasSIMD128, // MAX_U_I32x4
8237 CEFBS_HasSIMD128, // MAX_U_I32x4_S
8238 CEFBS_HasSIMD128, // MAX_U_I8x16
8239 CEFBS_HasSIMD128, // MAX_U_I8x16_S
8240 CEFBS_HasBulkMemoryOpt, // MEMCPY_A32
8241 CEFBS_HasBulkMemoryOpt, // MEMCPY_A32_S
8242 CEFBS_HasBulkMemoryOpt, // MEMCPY_A64
8243 CEFBS_HasBulkMemoryOpt, // MEMCPY_A64_S
8244 CEFBS_HasAtomics, // MEMORY_ATOMIC_NOTIFY_A32
8245 CEFBS_HasAtomics, // MEMORY_ATOMIC_NOTIFY_A32_S
8246 CEFBS_HasAtomics, // MEMORY_ATOMIC_NOTIFY_A64
8247 CEFBS_HasAtomics, // MEMORY_ATOMIC_NOTIFY_A64_S
8248 CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT32_A32
8249 CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT32_A32_S
8250 CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT32_A64
8251 CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT32_A64_S
8252 CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT64_A32
8253 CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT64_A32_S
8254 CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT64_A64
8255 CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT64_A64_S
8256 CEFBS_HasBulkMemoryOpt, // MEMORY_COPY_A32
8257 CEFBS_HasBulkMemoryOpt, // MEMORY_COPY_A32_S
8258 CEFBS_HasBulkMemoryOpt, // MEMORY_COPY_A64
8259 CEFBS_HasBulkMemoryOpt, // MEMORY_COPY_A64_S
8260 CEFBS_HasBulkMemoryOpt, // MEMORY_FILL_A32
8261 CEFBS_HasBulkMemoryOpt, // MEMORY_FILL_A32_S
8262 CEFBS_HasBulkMemoryOpt, // MEMORY_FILL_A64
8263 CEFBS_HasBulkMemoryOpt, // MEMORY_FILL_A64_S
8264 CEFBS_HasBulkMemoryOpt, // MEMORY_INIT_A32
8265 CEFBS_HasBulkMemoryOpt, // MEMORY_INIT_A32_S
8266 CEFBS_HasBulkMemoryOpt, // MEMORY_INIT_A64
8267 CEFBS_HasBulkMemoryOpt, // MEMORY_INIT_A64_S
8268 CEFBS_HasBulkMemoryOpt, // MEMSET_A32
8269 CEFBS_HasBulkMemoryOpt, // MEMSET_A32_S
8270 CEFBS_HasBulkMemoryOpt, // MEMSET_A64
8271 CEFBS_HasBulkMemoryOpt, // MEMSET_A64_S
8272 CEFBS_HasSIMD128_HasFP16, // MIN_F16x8
8273 CEFBS_HasSIMD128_HasFP16, // MIN_F16x8_S
8274 CEFBS_None, // MIN_F32
8275 CEFBS_None, // MIN_F32_S
8276 CEFBS_HasSIMD128, // MIN_F32x4
8277 CEFBS_HasSIMD128, // MIN_F32x4_S
8278 CEFBS_None, // MIN_F64
8279 CEFBS_None, // MIN_F64_S
8280 CEFBS_HasSIMD128, // MIN_F64x2
8281 CEFBS_HasSIMD128, // MIN_F64x2_S
8282 CEFBS_HasSIMD128, // MIN_S_I16x8
8283 CEFBS_HasSIMD128, // MIN_S_I16x8_S
8284 CEFBS_HasSIMD128, // MIN_S_I32x4
8285 CEFBS_HasSIMD128, // MIN_S_I32x4_S
8286 CEFBS_HasSIMD128, // MIN_S_I8x16
8287 CEFBS_HasSIMD128, // MIN_S_I8x16_S
8288 CEFBS_HasSIMD128, // MIN_U_I16x8
8289 CEFBS_HasSIMD128, // MIN_U_I16x8_S
8290 CEFBS_HasSIMD128, // MIN_U_I32x4
8291 CEFBS_HasSIMD128, // MIN_U_I32x4_S
8292 CEFBS_HasSIMD128, // MIN_U_I8x16
8293 CEFBS_HasSIMD128, // MIN_U_I8x16_S
8294 CEFBS_HasSIMD128_HasFP16, // MUL_F16x8
8295 CEFBS_HasSIMD128_HasFP16, // MUL_F16x8_S
8296 CEFBS_None, // MUL_F32
8297 CEFBS_None, // MUL_F32_S
8298 CEFBS_HasSIMD128, // MUL_F32x4
8299 CEFBS_HasSIMD128, // MUL_F32x4_S
8300 CEFBS_None, // MUL_F64
8301 CEFBS_None, // MUL_F64_S
8302 CEFBS_HasSIMD128, // MUL_F64x2
8303 CEFBS_HasSIMD128, // MUL_F64x2_S
8304 CEFBS_HasSIMD128, // MUL_I16x8
8305 CEFBS_HasSIMD128, // MUL_I16x8_S
8306 CEFBS_None, // MUL_I32
8307 CEFBS_None, // MUL_I32_S
8308 CEFBS_HasSIMD128, // MUL_I32x4
8309 CEFBS_HasSIMD128, // MUL_I32x4_S
8310 CEFBS_None, // MUL_I64
8311 CEFBS_None, // MUL_I64_S
8312 CEFBS_HasSIMD128, // MUL_I64x2
8313 CEFBS_HasSIMD128, // MUL_I64x2_S
8314 CEFBS_HasSIMD128, // NARROW_S_I16x8
8315 CEFBS_HasSIMD128, // NARROW_S_I16x8_S
8316 CEFBS_HasSIMD128, // NARROW_S_I8x16
8317 CEFBS_HasSIMD128, // NARROW_S_I8x16_S
8318 CEFBS_HasSIMD128, // NARROW_U_I16x8
8319 CEFBS_HasSIMD128, // NARROW_U_I16x8_S
8320 CEFBS_HasSIMD128, // NARROW_U_I8x16
8321 CEFBS_HasSIMD128, // NARROW_U_I8x16_S
8322 CEFBS_HasSIMD128_HasFP16, // NEAREST_F16x8
8323 CEFBS_HasSIMD128_HasFP16, // NEAREST_F16x8_S
8324 CEFBS_None, // NEAREST_F32
8325 CEFBS_None, // NEAREST_F32_S
8326 CEFBS_HasSIMD128, // NEAREST_F32x4
8327 CEFBS_HasSIMD128, // NEAREST_F32x4_S
8328 CEFBS_None, // NEAREST_F64
8329 CEFBS_None, // NEAREST_F64_S
8330 CEFBS_HasSIMD128, // NEAREST_F64x2
8331 CEFBS_HasSIMD128, // NEAREST_F64x2_S
8332 CEFBS_HasSIMD128_HasFP16, // NEG_F16x8
8333 CEFBS_HasSIMD128_HasFP16, // NEG_F16x8_S
8334 CEFBS_None, // NEG_F32
8335 CEFBS_None, // NEG_F32_S
8336 CEFBS_HasSIMD128, // NEG_F32x4
8337 CEFBS_HasSIMD128, // NEG_F32x4_S
8338 CEFBS_None, // NEG_F64
8339 CEFBS_None, // NEG_F64_S
8340 CEFBS_HasSIMD128, // NEG_F64x2
8341 CEFBS_HasSIMD128, // NEG_F64x2_S
8342 CEFBS_HasSIMD128, // NEG_I16x8
8343 CEFBS_HasSIMD128, // NEG_I16x8_S
8344 CEFBS_HasSIMD128, // NEG_I32x4
8345 CEFBS_HasSIMD128, // NEG_I32x4_S
8346 CEFBS_HasSIMD128, // NEG_I64x2
8347 CEFBS_HasSIMD128, // NEG_I64x2_S
8348 CEFBS_HasSIMD128, // NEG_I8x16
8349 CEFBS_HasSIMD128, // NEG_I8x16_S
8350 CEFBS_HasSIMD128_HasFP16, // NE_F16x8
8351 CEFBS_HasSIMD128_HasFP16, // NE_F16x8_S
8352 CEFBS_None, // NE_F32
8353 CEFBS_None, // NE_F32_S
8354 CEFBS_HasSIMD128, // NE_F32x4
8355 CEFBS_HasSIMD128, // NE_F32x4_S
8356 CEFBS_None, // NE_F64
8357 CEFBS_None, // NE_F64_S
8358 CEFBS_HasSIMD128, // NE_F64x2
8359 CEFBS_HasSIMD128, // NE_F64x2_S
8360 CEFBS_HasSIMD128, // NE_I16x8
8361 CEFBS_HasSIMD128, // NE_I16x8_S
8362 CEFBS_None, // NE_I32
8363 CEFBS_None, // NE_I32_S
8364 CEFBS_HasSIMD128, // NE_I32x4
8365 CEFBS_HasSIMD128, // NE_I32x4_S
8366 CEFBS_None, // NE_I64
8367 CEFBS_None, // NE_I64_S
8368 CEFBS_HasSIMD128, // NE_I64x2
8369 CEFBS_HasSIMD128, // NE_I64x2_S
8370 CEFBS_HasSIMD128, // NE_I8x16
8371 CEFBS_HasSIMD128, // NE_I8x16_S
8372 CEFBS_HasSIMD128_HasFP16, // NMADD_F16x8
8373 CEFBS_HasSIMD128_HasFP16, // NMADD_F16x8_S
8374 CEFBS_HasSIMD128_HasRelaxedSIMD, // NMADD_F32x4
8375 CEFBS_HasSIMD128_HasRelaxedSIMD, // NMADD_F32x4_S
8376 CEFBS_HasSIMD128_HasRelaxedSIMD, // NMADD_F64x2
8377 CEFBS_HasSIMD128_HasRelaxedSIMD, // NMADD_F64x2_S
8378 CEFBS_None, // NOP
8379 CEFBS_None, // NOP_S
8380 CEFBS_HasSIMD128, // NOT
8381 CEFBS_HasSIMD128, // NOT_S
8382 CEFBS_HasSIMD128, // OR
8383 CEFBS_None, // OR_I32
8384 CEFBS_None, // OR_I32_S
8385 CEFBS_None, // OR_I64
8386 CEFBS_None, // OR_I64_S
8387 CEFBS_HasSIMD128, // OR_S
8388 CEFBS_HasSIMD128_HasFP16, // PMAX_F16x8
8389 CEFBS_HasSIMD128_HasFP16, // PMAX_F16x8_S
8390 CEFBS_HasSIMD128, // PMAX_F32x4
8391 CEFBS_HasSIMD128, // PMAX_F32x4_S
8392 CEFBS_HasSIMD128, // PMAX_F64x2
8393 CEFBS_HasSIMD128, // PMAX_F64x2_S
8394 CEFBS_HasSIMD128_HasFP16, // PMIN_F16x8
8395 CEFBS_HasSIMD128_HasFP16, // PMIN_F16x8_S
8396 CEFBS_HasSIMD128, // PMIN_F32x4
8397 CEFBS_HasSIMD128, // PMIN_F32x4_S
8398 CEFBS_HasSIMD128, // PMIN_F64x2
8399 CEFBS_HasSIMD128, // PMIN_F64x2_S
8400 CEFBS_None, // POPCNT_I32
8401 CEFBS_None, // POPCNT_I32_S
8402 CEFBS_None, // POPCNT_I64
8403 CEFBS_None, // POPCNT_I64_S
8404 CEFBS_HasSIMD128, // POPCNT_I8x16
8405 CEFBS_HasSIMD128, // POPCNT_I8x16_S
8406 CEFBS_HasSIMD128, // Q15MULR_SAT_S_I16x8
8407 CEFBS_HasSIMD128, // Q15MULR_SAT_S_I16x8_S
8408 CEFBS_HasGC, // REF_CAST_FUNCREF
8409 CEFBS_HasGC, // REF_CAST_FUNCREF_S
8410 CEFBS_HasReferenceTypes, // REF_FUNC
8411 CEFBS_HasReferenceTypes, // REF_FUNC_S
8412 CEFBS_HasReferenceTypes, // REF_IS_NULL_EXNREF
8413 CEFBS_HasReferenceTypes, // REF_IS_NULL_EXNREF_S
8414 CEFBS_HasReferenceTypes, // REF_IS_NULL_EXTERNREF
8415 CEFBS_HasReferenceTypes, // REF_IS_NULL_EXTERNREF_S
8416 CEFBS_HasReferenceTypes, // REF_IS_NULL_FUNCREF
8417 CEFBS_HasReferenceTypes, // REF_IS_NULL_FUNCREF_S
8418 CEFBS_HasReferenceTypes, // REF_NULL_EXNREF
8419 CEFBS_HasReferenceTypes, // REF_NULL_EXNREF_S
8420 CEFBS_HasReferenceTypes, // REF_NULL_EXTERNREF
8421 CEFBS_HasReferenceTypes, // REF_NULL_EXTERNREF_S
8422 CEFBS_HasReferenceTypes, // REF_NULL_FUNCREF
8423 CEFBS_HasReferenceTypes, // REF_NULL_FUNCREF_S
8424 CEFBS_HasGC, // REF_TEST_FUNCREF
8425 CEFBS_HasGC, // REF_TEST_FUNCREF_S
8426 CEFBS_HasRelaxedSIMD, // RELAXED_DOT
8427 CEFBS_HasRelaxedSIMD, // RELAXED_DOT_ADD
8428 CEFBS_HasRelaxedSIMD, // RELAXED_DOT_ADD_S
8429 CEFBS_HasRelaxedSIMD, // RELAXED_DOT_BFLOAT
8430 CEFBS_HasRelaxedSIMD, // RELAXED_DOT_BFLOAT_S
8431 CEFBS_HasRelaxedSIMD, // RELAXED_DOT_S
8432 CEFBS_HasRelaxedSIMD, // RELAXED_Q15MULR_S_I16x8
8433 CEFBS_HasRelaxedSIMD, // RELAXED_Q15MULR_S_I16x8_S
8434 CEFBS_HasRelaxedSIMD, // RELAXED_SWIZZLE
8435 CEFBS_HasRelaxedSIMD, // RELAXED_SWIZZLE_S
8436 CEFBS_None, // REM_S_I32
8437 CEFBS_None, // REM_S_I32_S
8438 CEFBS_None, // REM_S_I64
8439 CEFBS_None, // REM_S_I64_S
8440 CEFBS_None, // REM_U_I32
8441 CEFBS_None, // REM_U_I32_S
8442 CEFBS_None, // REM_U_I64
8443 CEFBS_None, // REM_U_I64_S
8444 CEFBS_HasFP16, // REPLACE_LANE_F16x8
8445 CEFBS_HasFP16, // REPLACE_LANE_F16x8_S
8446 CEFBS_HasSIMD128, // REPLACE_LANE_F32x4
8447 CEFBS_HasSIMD128, // REPLACE_LANE_F32x4_S
8448 CEFBS_HasSIMD128, // REPLACE_LANE_F64x2
8449 CEFBS_HasSIMD128, // REPLACE_LANE_F64x2_S
8450 CEFBS_HasSIMD128, // REPLACE_LANE_I16x8
8451 CEFBS_HasSIMD128, // REPLACE_LANE_I16x8_S
8452 CEFBS_HasSIMD128, // REPLACE_LANE_I32x4
8453 CEFBS_HasSIMD128, // REPLACE_LANE_I32x4_S
8454 CEFBS_HasSIMD128, // REPLACE_LANE_I64x2
8455 CEFBS_HasSIMD128, // REPLACE_LANE_I64x2_S
8456 CEFBS_HasSIMD128, // REPLACE_LANE_I8x16
8457 CEFBS_HasSIMD128, // REPLACE_LANE_I8x16_S
8458 CEFBS_HasExceptionHandling, // RETHROW
8459 CEFBS_HasExceptionHandling, // RETHROW_S
8460 CEFBS_None, // RETURN
8461 CEFBS_None, // RETURN_S
8462 CEFBS_HasTailCall, // RET_CALL
8463 CEFBS_HasTailCall, // RET_CALL_INDIRECT
8464 CEFBS_HasTailCall, // RET_CALL_INDIRECT_S
8465 CEFBS_HasTailCall_HasGC, // RET_CALL_REF
8466 CEFBS_HasTailCall_HasGC, // RET_CALL_REF_S
8467 CEFBS_HasTailCall, // RET_CALL_S
8468 CEFBS_None, // ROTL_I32
8469 CEFBS_None, // ROTL_I32_S
8470 CEFBS_None, // ROTL_I64
8471 CEFBS_None, // ROTL_I64_S
8472 CEFBS_None, // ROTR_I32
8473 CEFBS_None, // ROTR_I32_S
8474 CEFBS_None, // ROTR_I64
8475 CEFBS_None, // ROTR_I64_S
8476 CEFBS_HasReferenceTypes, // SELECT_EXNREF
8477 CEFBS_HasReferenceTypes, // SELECT_EXNREF_S
8478 CEFBS_HasReferenceTypes, // SELECT_EXTERNREF
8479 CEFBS_HasReferenceTypes, // SELECT_EXTERNREF_S
8480 CEFBS_None, // SELECT_F32
8481 CEFBS_None, // SELECT_F32_S
8482 CEFBS_None, // SELECT_F64
8483 CEFBS_None, // SELECT_F64_S
8484 CEFBS_HasReferenceTypes, // SELECT_FUNCREF
8485 CEFBS_HasReferenceTypes, // SELECT_FUNCREF_S
8486 CEFBS_None, // SELECT_I32
8487 CEFBS_None, // SELECT_I32_S
8488 CEFBS_None, // SELECT_I64
8489 CEFBS_None, // SELECT_I64_S
8490 CEFBS_HasReferenceTypes, // SELECT_T
8491 CEFBS_HasReferenceTypes, // SELECT_T_S
8492 CEFBS_None, // SELECT_V128
8493 CEFBS_None, // SELECT_V128_S
8494 CEFBS_HasSIMD128, // SHL_I16x8
8495 CEFBS_HasSIMD128, // SHL_I16x8_S
8496 CEFBS_None, // SHL_I32
8497 CEFBS_None, // SHL_I32_S
8498 CEFBS_HasSIMD128, // SHL_I32x4
8499 CEFBS_HasSIMD128, // SHL_I32x4_S
8500 CEFBS_None, // SHL_I64
8501 CEFBS_None, // SHL_I64_S
8502 CEFBS_HasSIMD128, // SHL_I64x2
8503 CEFBS_HasSIMD128, // SHL_I64x2_S
8504 CEFBS_HasSIMD128, // SHL_I8x16
8505 CEFBS_HasSIMD128, // SHL_I8x16_S
8506 CEFBS_HasSIMD128, // SHR_S_I16x8
8507 CEFBS_HasSIMD128, // SHR_S_I16x8_S
8508 CEFBS_None, // SHR_S_I32
8509 CEFBS_None, // SHR_S_I32_S
8510 CEFBS_HasSIMD128, // SHR_S_I32x4
8511 CEFBS_HasSIMD128, // SHR_S_I32x4_S
8512 CEFBS_None, // SHR_S_I64
8513 CEFBS_None, // SHR_S_I64_S
8514 CEFBS_HasSIMD128, // SHR_S_I64x2
8515 CEFBS_HasSIMD128, // SHR_S_I64x2_S
8516 CEFBS_HasSIMD128, // SHR_S_I8x16
8517 CEFBS_HasSIMD128, // SHR_S_I8x16_S
8518 CEFBS_HasSIMD128, // SHR_U_I16x8
8519 CEFBS_HasSIMD128, // SHR_U_I16x8_S
8520 CEFBS_None, // SHR_U_I32
8521 CEFBS_None, // SHR_U_I32_S
8522 CEFBS_HasSIMD128, // SHR_U_I32x4
8523 CEFBS_HasSIMD128, // SHR_U_I32x4_S
8524 CEFBS_None, // SHR_U_I64
8525 CEFBS_None, // SHR_U_I64_S
8526 CEFBS_HasSIMD128, // SHR_U_I64x2
8527 CEFBS_HasSIMD128, // SHR_U_I64x2_S
8528 CEFBS_HasSIMD128, // SHR_U_I8x16
8529 CEFBS_HasSIMD128, // SHR_U_I8x16_S
8530 CEFBS_HasSIMD128, // SHUFFLE
8531 CEFBS_HasSIMD128, // SHUFFLE_S
8532 CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMAX_F32x4
8533 CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMAX_F32x4_S
8534 CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMAX_F64x2
8535 CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMAX_F64x2_S
8536 CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMIN_F32x4
8537 CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMIN_F32x4_S
8538 CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMIN_F64x2
8539 CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMIN_F64x2_S
8540 CEFBS_HasFP16, // SPLAT_F16x8
8541 CEFBS_HasFP16, // SPLAT_F16x8_S
8542 CEFBS_HasSIMD128, // SPLAT_F32x4
8543 CEFBS_HasSIMD128, // SPLAT_F32x4_S
8544 CEFBS_HasSIMD128, // SPLAT_F64x2
8545 CEFBS_HasSIMD128, // SPLAT_F64x2_S
8546 CEFBS_HasSIMD128, // SPLAT_I16x8
8547 CEFBS_HasSIMD128, // SPLAT_I16x8_S
8548 CEFBS_HasSIMD128, // SPLAT_I32x4
8549 CEFBS_HasSIMD128, // SPLAT_I32x4_S
8550 CEFBS_HasSIMD128, // SPLAT_I64x2
8551 CEFBS_HasSIMD128, // SPLAT_I64x2_S
8552 CEFBS_HasSIMD128, // SPLAT_I8x16
8553 CEFBS_HasSIMD128, // SPLAT_I8x16_S
8554 CEFBS_HasSIMD128_HasFP16, // SQRT_F16x8
8555 CEFBS_HasSIMD128_HasFP16, // SQRT_F16x8_S
8556 CEFBS_None, // SQRT_F32
8557 CEFBS_None, // SQRT_F32_S
8558 CEFBS_HasSIMD128, // SQRT_F32x4
8559 CEFBS_HasSIMD128, // SQRT_F32x4_S
8560 CEFBS_None, // SQRT_F64
8561 CEFBS_None, // SQRT_F64_S
8562 CEFBS_HasSIMD128, // SQRT_F64x2
8563 CEFBS_HasSIMD128, // SQRT_F64x2_S
8564 CEFBS_None, // STORE16_I32_A32
8565 CEFBS_None, // STORE16_I32_A32_S
8566 CEFBS_None, // STORE16_I32_A64
8567 CEFBS_None, // STORE16_I32_A64_S
8568 CEFBS_None, // STORE16_I64_A32
8569 CEFBS_None, // STORE16_I64_A32_S
8570 CEFBS_None, // STORE16_I64_A64
8571 CEFBS_None, // STORE16_I64_A64_S
8572 CEFBS_None, // STORE32_I64_A32
8573 CEFBS_None, // STORE32_I64_A32_S
8574 CEFBS_None, // STORE32_I64_A64
8575 CEFBS_None, // STORE32_I64_A64_S
8576 CEFBS_None, // STORE8_I32_A32
8577 CEFBS_None, // STORE8_I32_A32_S
8578 CEFBS_None, // STORE8_I32_A64
8579 CEFBS_None, // STORE8_I32_A64_S
8580 CEFBS_None, // STORE8_I64_A32
8581 CEFBS_None, // STORE8_I64_A32_S
8582 CEFBS_None, // STORE8_I64_A64
8583 CEFBS_None, // STORE8_I64_A64_S
8584 CEFBS_HasFP16, // STORE_F16_F32_A32
8585 CEFBS_HasFP16, // STORE_F16_F32_A32_S
8586 CEFBS_HasFP16, // STORE_F16_F32_A64
8587 CEFBS_HasFP16, // STORE_F16_F32_A64_S
8588 CEFBS_None, // STORE_F32_A32
8589 CEFBS_None, // STORE_F32_A32_S
8590 CEFBS_None, // STORE_F32_A64
8591 CEFBS_None, // STORE_F32_A64_S
8592 CEFBS_None, // STORE_F64_A32
8593 CEFBS_None, // STORE_F64_A32_S
8594 CEFBS_None, // STORE_F64_A64
8595 CEFBS_None, // STORE_F64_A64_S
8596 CEFBS_None, // STORE_I32_A32
8597 CEFBS_None, // STORE_I32_A32_S
8598 CEFBS_None, // STORE_I32_A64
8599 CEFBS_None, // STORE_I32_A64_S
8600 CEFBS_None, // STORE_I64_A32
8601 CEFBS_None, // STORE_I64_A32_S
8602 CEFBS_None, // STORE_I64_A64
8603 CEFBS_None, // STORE_I64_A64_S
8604 CEFBS_HasSIMD128, // STORE_LANE_I16x8_A32
8605 CEFBS_HasSIMD128, // STORE_LANE_I16x8_A32_S
8606 CEFBS_HasSIMD128, // STORE_LANE_I16x8_A64
8607 CEFBS_HasSIMD128, // STORE_LANE_I16x8_A64_S
8608 CEFBS_HasSIMD128, // STORE_LANE_I32x4_A32
8609 CEFBS_HasSIMD128, // STORE_LANE_I32x4_A32_S
8610 CEFBS_HasSIMD128, // STORE_LANE_I32x4_A64
8611 CEFBS_HasSIMD128, // STORE_LANE_I32x4_A64_S
8612 CEFBS_HasSIMD128, // STORE_LANE_I64x2_A32
8613 CEFBS_HasSIMD128, // STORE_LANE_I64x2_A32_S
8614 CEFBS_HasSIMD128, // STORE_LANE_I64x2_A64
8615 CEFBS_HasSIMD128, // STORE_LANE_I64x2_A64_S
8616 CEFBS_HasSIMD128, // STORE_LANE_I8x16_A32
8617 CEFBS_HasSIMD128, // STORE_LANE_I8x16_A32_S
8618 CEFBS_HasSIMD128, // STORE_LANE_I8x16_A64
8619 CEFBS_HasSIMD128, // STORE_LANE_I8x16_A64_S
8620 CEFBS_HasSIMD128, // STORE_V128_A32
8621 CEFBS_HasSIMD128, // STORE_V128_A32_S
8622 CEFBS_HasSIMD128, // STORE_V128_A64
8623 CEFBS_HasSIMD128, // STORE_V128_A64_S
8624 CEFBS_HasSIMD128_HasFP16, // SUB_F16x8
8625 CEFBS_HasSIMD128_HasFP16, // SUB_F16x8_S
8626 CEFBS_None, // SUB_F32
8627 CEFBS_None, // SUB_F32_S
8628 CEFBS_HasSIMD128, // SUB_F32x4
8629 CEFBS_HasSIMD128, // SUB_F32x4_S
8630 CEFBS_None, // SUB_F64
8631 CEFBS_None, // SUB_F64_S
8632 CEFBS_HasSIMD128, // SUB_F64x2
8633 CEFBS_HasSIMD128, // SUB_F64x2_S
8634 CEFBS_HasSIMD128, // SUB_I16x8
8635 CEFBS_HasSIMD128, // SUB_I16x8_S
8636 CEFBS_None, // SUB_I32
8637 CEFBS_None, // SUB_I32_S
8638 CEFBS_HasSIMD128, // SUB_I32x4
8639 CEFBS_HasSIMD128, // SUB_I32x4_S
8640 CEFBS_None, // SUB_I64
8641 CEFBS_None, // SUB_I64_S
8642 CEFBS_HasSIMD128, // SUB_I64x2
8643 CEFBS_HasSIMD128, // SUB_I64x2_S
8644 CEFBS_HasSIMD128, // SUB_I8x16
8645 CEFBS_HasSIMD128, // SUB_I8x16_S
8646 CEFBS_HasSIMD128, // SUB_SAT_S_I16x8
8647 CEFBS_HasSIMD128, // SUB_SAT_S_I16x8_S
8648 CEFBS_HasSIMD128, // SUB_SAT_S_I8x16
8649 CEFBS_HasSIMD128, // SUB_SAT_S_I8x16_S
8650 CEFBS_HasSIMD128, // SUB_SAT_U_I16x8
8651 CEFBS_HasSIMD128, // SUB_SAT_U_I16x8_S
8652 CEFBS_HasSIMD128, // SUB_SAT_U_I8x16
8653 CEFBS_HasSIMD128, // SUB_SAT_U_I8x16_S
8654 CEFBS_HasSIMD128, // SWIZZLE
8655 CEFBS_HasSIMD128, // SWIZZLE_S
8656 CEFBS_HasReferenceTypes, // TABLE_COPY
8657 CEFBS_HasReferenceTypes, // TABLE_COPY_S
8658 CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_FILL_EXNREF
8659 CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_FILL_EXNREF_S
8660 CEFBS_HasReferenceTypes, // TABLE_FILL_EXTERNREF
8661 CEFBS_HasReferenceTypes, // TABLE_FILL_EXTERNREF_S
8662 CEFBS_HasReferenceTypes, // TABLE_FILL_FUNCREF
8663 CEFBS_HasReferenceTypes, // TABLE_FILL_FUNCREF_S
8664 CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_GET_EXNREF
8665 CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_GET_EXNREF_S
8666 CEFBS_HasReferenceTypes, // TABLE_GET_EXTERNREF
8667 CEFBS_HasReferenceTypes, // TABLE_GET_EXTERNREF_S
8668 CEFBS_HasReferenceTypes, // TABLE_GET_FUNCREF
8669 CEFBS_HasReferenceTypes, // TABLE_GET_FUNCREF_S
8670 CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_GROW_EXNREF
8671 CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_GROW_EXNREF_S
8672 CEFBS_HasReferenceTypes, // TABLE_GROW_EXTERNREF
8673 CEFBS_HasReferenceTypes, // TABLE_GROW_EXTERNREF_S
8674 CEFBS_HasReferenceTypes, // TABLE_GROW_FUNCREF
8675 CEFBS_HasReferenceTypes, // TABLE_GROW_FUNCREF_S
8676 CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_SET_EXNREF
8677 CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_SET_EXNREF_S
8678 CEFBS_HasReferenceTypes, // TABLE_SET_EXTERNREF
8679 CEFBS_HasReferenceTypes, // TABLE_SET_EXTERNREF_S
8680 CEFBS_HasReferenceTypes, // TABLE_SET_FUNCREF
8681 CEFBS_HasReferenceTypes, // TABLE_SET_FUNCREF_S
8682 CEFBS_HasReferenceTypes, // TABLE_SIZE
8683 CEFBS_HasReferenceTypes, // TABLE_SIZE_S
8684 CEFBS_HasReferenceTypes_HasExceptionHandling, // TEE_EXNREF
8685 CEFBS_HasReferenceTypes_HasExceptionHandling, // TEE_EXNREF_S
8686 CEFBS_HasReferenceTypes, // TEE_EXTERNREF
8687 CEFBS_HasReferenceTypes, // TEE_EXTERNREF_S
8688 CEFBS_None, // TEE_F32
8689 CEFBS_None, // TEE_F32_S
8690 CEFBS_None, // TEE_F64
8691 CEFBS_None, // TEE_F64_S
8692 CEFBS_HasReferenceTypes, // TEE_FUNCREF
8693 CEFBS_HasReferenceTypes, // TEE_FUNCREF_S
8694 CEFBS_None, // TEE_I32
8695 CEFBS_None, // TEE_I32_S
8696 CEFBS_None, // TEE_I64
8697 CEFBS_None, // TEE_I64_S
8698 CEFBS_HasSIMD128, // TEE_V128
8699 CEFBS_HasSIMD128, // TEE_V128_S
8700 CEFBS_HasExceptionHandling, // THROW
8701 CEFBS_HasExceptionHandling, // THROW_REF
8702 CEFBS_HasExceptionHandling, // THROW_REF_S
8703 CEFBS_HasExceptionHandling, // THROW_S
8704 CEFBS_HasSIMD128_HasFP16, // TRUNC_F16x8
8705 CEFBS_HasSIMD128_HasFP16, // TRUNC_F16x8_S
8706 CEFBS_None, // TRUNC_F32
8707 CEFBS_None, // TRUNC_F32_S
8708 CEFBS_HasSIMD128, // TRUNC_F32x4
8709 CEFBS_HasSIMD128, // TRUNC_F32x4_S
8710 CEFBS_None, // TRUNC_F64
8711 CEFBS_None, // TRUNC_F64_S
8712 CEFBS_HasSIMD128, // TRUNC_F64x2
8713 CEFBS_HasSIMD128, // TRUNC_F64x2_S
8714 CEFBS_HasExceptionHandling, // TRY
8715 CEFBS_HasExceptionHandling, // TRY_S
8716 CEFBS_HasExceptionHandling, // TRY_TABLE
8717 CEFBS_HasExceptionHandling, // TRY_TABLE_S
8718 CEFBS_None, // UNREACHABLE
8719 CEFBS_None, // UNREACHABLE_S
8720 CEFBS_HasSIMD128, // XOR
8721 CEFBS_None, // XOR_I32
8722 CEFBS_None, // XOR_I32_S
8723 CEFBS_None, // XOR_I64
8724 CEFBS_None, // XOR_I64_S
8725 CEFBS_HasSIMD128, // XOR_S
8726 CEFBS_None, // anonymous_14422MEMORY_GROW_A32
8727 CEFBS_None, // anonymous_14422MEMORY_GROW_A32_S
8728 CEFBS_None, // anonymous_14422MEMORY_SIZE_A32
8729 CEFBS_None, // anonymous_14422MEMORY_SIZE_A32_S
8730 CEFBS_None, // anonymous_14423MEMORY_GROW_A64
8731 CEFBS_None, // anonymous_14423MEMORY_GROW_A64_S
8732 CEFBS_None, // anonymous_14423MEMORY_SIZE_A64
8733 CEFBS_None, // anonymous_14423MEMORY_SIZE_A64_S
8734 CEFBS_HasSIMD128, // convert_low_s_F64x2
8735 CEFBS_HasSIMD128, // convert_low_s_F64x2_S
8736 CEFBS_HasSIMD128, // convert_low_u_F64x2
8737 CEFBS_HasSIMD128, // convert_low_u_F64x2_S
8738 CEFBS_HasSIMD128_HasFP16, // demote_zero_F16x8
8739 CEFBS_HasSIMD128_HasFP16, // demote_zero_F16x8_S
8740 CEFBS_HasSIMD128, // demote_zero_F32x4
8741 CEFBS_HasSIMD128, // demote_zero_F32x4_S
8742 CEFBS_HasSIMD128, // extadd_pairwise_s_I16x8
8743 CEFBS_HasSIMD128, // extadd_pairwise_s_I16x8_S
8744 CEFBS_HasSIMD128, // extadd_pairwise_s_I32x4
8745 CEFBS_HasSIMD128, // extadd_pairwise_s_I32x4_S
8746 CEFBS_HasSIMD128, // extadd_pairwise_u_I16x8
8747 CEFBS_HasSIMD128, // extadd_pairwise_u_I16x8_S
8748 CEFBS_HasSIMD128, // extadd_pairwise_u_I32x4
8749 CEFBS_HasSIMD128, // extadd_pairwise_u_I32x4_S
8750 CEFBS_HasSIMD128, // extend_high_s_I16x8
8751 CEFBS_HasSIMD128, // extend_high_s_I16x8_S
8752 CEFBS_HasSIMD128, // extend_high_s_I32x4
8753 CEFBS_HasSIMD128, // extend_high_s_I32x4_S
8754 CEFBS_HasSIMD128, // extend_high_s_I64x2
8755 CEFBS_HasSIMD128, // extend_high_s_I64x2_S
8756 CEFBS_HasSIMD128, // extend_high_u_I16x8
8757 CEFBS_HasSIMD128, // extend_high_u_I16x8_S
8758 CEFBS_HasSIMD128, // extend_high_u_I32x4
8759 CEFBS_HasSIMD128, // extend_high_u_I32x4_S
8760 CEFBS_HasSIMD128, // extend_high_u_I64x2
8761 CEFBS_HasSIMD128, // extend_high_u_I64x2_S
8762 CEFBS_HasSIMD128, // extend_low_s_I16x8
8763 CEFBS_HasSIMD128, // extend_low_s_I16x8_S
8764 CEFBS_HasSIMD128, // extend_low_s_I32x4
8765 CEFBS_HasSIMD128, // extend_low_s_I32x4_S
8766 CEFBS_HasSIMD128, // extend_low_s_I64x2
8767 CEFBS_HasSIMD128, // extend_low_s_I64x2_S
8768 CEFBS_HasSIMD128, // extend_low_u_I16x8
8769 CEFBS_HasSIMD128, // extend_low_u_I16x8_S
8770 CEFBS_HasSIMD128, // extend_low_u_I32x4
8771 CEFBS_HasSIMD128, // extend_low_u_I32x4_S
8772 CEFBS_HasSIMD128, // extend_low_u_I64x2
8773 CEFBS_HasSIMD128, // extend_low_u_I64x2_S
8774 CEFBS_HasSIMD128_HasFP16, // fp_to_sint_I16x8
8775 CEFBS_HasSIMD128_HasFP16, // fp_to_sint_I16x8_S
8776 CEFBS_HasSIMD128, // fp_to_sint_I32x4
8777 CEFBS_HasSIMD128, // fp_to_sint_I32x4_S
8778 CEFBS_HasSIMD128_HasFP16, // fp_to_uint_I16x8
8779 CEFBS_HasSIMD128_HasFP16, // fp_to_uint_I16x8_S
8780 CEFBS_HasSIMD128, // fp_to_uint_I32x4
8781 CEFBS_HasSIMD128, // fp_to_uint_I32x4_S
8782 CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_signed_I32x4
8783 CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_signed_I32x4_S
8784 CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_signed_zero_I32x4
8785 CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_signed_zero_I32x4_S
8786 CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_unsigned_I32x4
8787 CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_unsigned_I32x4_S
8788 CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_unsigned_zero_I32x4
8789 CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_unsigned_zero_I32x4_S
8790 CEFBS_HasSIMD128_HasFP16, // promote_low_F32x4
8791 CEFBS_HasSIMD128_HasFP16, // promote_low_F32x4_S
8792 CEFBS_HasSIMD128, // promote_low_F64x2
8793 CEFBS_HasSIMD128, // promote_low_F64x2_S
8794 CEFBS_HasSIMD128_HasFP16, // sint_to_fp_F16x8
8795 CEFBS_HasSIMD128_HasFP16, // sint_to_fp_F16x8_S
8796 CEFBS_HasSIMD128, // sint_to_fp_F32x4
8797 CEFBS_HasSIMD128, // sint_to_fp_F32x4_S
8798 CEFBS_HasSIMD128, // trunc_sat_zero_s_I32x4
8799 CEFBS_HasSIMD128, // trunc_sat_zero_s_I32x4_S
8800 CEFBS_HasSIMD128, // trunc_sat_zero_u_I32x4
8801 CEFBS_HasSIMD128, // trunc_sat_zero_u_I32x4_S
8802 CEFBS_HasSIMD128_HasFP16, // uint_to_fp_F16x8
8803 CEFBS_HasSIMD128_HasFP16, // uint_to_fp_F16x8_S
8804 CEFBS_HasSIMD128, // uint_to_fp_F32x4
8805 CEFBS_HasSIMD128, // uint_to_fp_F32x4_S
8806 };
8807
8808 assert(Opcode < 1979);
8809 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
8810}
8811
8812
8813} // namespace llvm::WebAssembly_MC
8814
8815#endif // GET_COMPUTE_FEATURES
8816
8817#ifdef GET_AVAILABLE_OPCODE_CHECKER
8818#undef GET_AVAILABLE_OPCODE_CHECKER
8819
8820namespace llvm::WebAssembly_MC {
8821
8822bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
8823 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
8824 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
8825 FeatureBitset MissingFeatures =
8826 (AvailableFeatures & RequiredFeatures) ^
8827 RequiredFeatures;
8828 return !MissingFeatures.any();
8829}
8830
8831} // namespace llvm::WebAssembly_MC
8832
8833#endif // GET_AVAILABLE_OPCODE_CHECKER
8834
8835#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
8836#undef ENABLE_INSTR_PREDICATE_VERIFIER
8837
8838#include <sstream>
8839
8840namespace llvm::WebAssembly_MC {
8841
8842#ifndef NDEBUG
8843static const char *SubtargetFeatureNames[] = {
8844 "Feature_HasAtomics",
8845 "Feature_HasBulkMemory",
8846 "Feature_HasBulkMemoryOpt",
8847 "Feature_HasCallIndirectOverlong",
8848 "Feature_HasExceptionHandling",
8849 "Feature_HasExtendedConst",
8850 "Feature_HasFP16",
8851 "Feature_HasGC",
8852 "Feature_HasMultiMemory",
8853 "Feature_HasMultivalue",
8854 "Feature_HasMutableGlobals",
8855 "Feature_HasNontrappingFPToInt",
8856 "Feature_HasReferenceTypes",
8857 "Feature_HasRelaxedAtomics",
8858 "Feature_HasRelaxedSIMD",
8859 "Feature_HasSIMD128",
8860 "Feature_HasSignExt",
8861 "Feature_HasTailCall",
8862 "Feature_HasWideArithmetic",
8863 "Feature_NotHasNontrappingFPToInt",
8864 nullptr
8865};
8866
8867#endif // NDEBUG
8868
8869void verifyInstructionPredicates(
8870 unsigned Opcode, const FeatureBitset &Features) {
8871#ifndef NDEBUG
8872 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
8873 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
8874 FeatureBitset MissingFeatures =
8875 (AvailableFeatures & RequiredFeatures) ^
8876 RequiredFeatures;
8877 if (MissingFeatures.any()) {
8878 std::ostringstream Msg;
8879 Msg << "Attempting to emit " << &WebAssemblyInstrNameData[WebAssemblyInstrNameIndices[Opcode]]
8880 << " instruction but the ";
8881 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
8882 if (MissingFeatures.test(i))
8883 Msg << SubtargetFeatureNames[i] << " ";
8884 Msg << "predicate(s) are not met";
8885 report_fatal_error(Msg.str().c_str());
8886 }
8887#endif // NDEBUG
8888}
8889
8890} // namespace llvm::WebAssembly_MC
8891
8892#endif // ENABLE_INSTR_PREDICATE_VERIFIER
8893
8894#ifdef GET_INSTRMAP_INFO
8895#undef GET_INSTRMAP_INFO
8896
8897namespace llvm::WebAssembly {
8898
8899enum IsWasm64 {
8900 IsWasm64_1
8901};
8902
8903enum StackBased {
8904 StackBased_0,
8905 StackBased_1
8906};
8907
8908// getRegisterOpcode
8909LLVM_READONLY
8910int32_t getRegisterOpcode(uint32_t Opcode) {
8911 using namespace WebAssembly;
8912 static constexpr uint32_t Table[][2] = {
8913 { CALL_PARAMS_S, CALL_PARAMS },
8914 { CALL_RESULTS_S, CALL_RESULTS },
8915 { CATCHRET_S, CATCHRET },
8916 { CLEANUPRET_S, CLEANUPRET },
8917 { COMPILER_FENCE_S, COMPILER_FENCE },
8918 { RET_CALL_RESULTS_S, RET_CALL_RESULTS },
8919 { ABS_F16x8_S, ABS_F16x8 },
8920 { ABS_F32_S, ABS_F32 },
8921 { ABS_F32x4_S, ABS_F32x4 },
8922 { ABS_F64_S, ABS_F64 },
8923 { ABS_F64x2_S, ABS_F64x2 },
8924 { ABS_I16x8_S, ABS_I16x8 },
8925 { ABS_I32x4_S, ABS_I32x4 },
8926 { ABS_I64x2_S, ABS_I64x2 },
8927 { ABS_I8x16_S, ABS_I8x16 },
8928 { ADD_F16x8_S, ADD_F16x8 },
8929 { ADD_F32_S, ADD_F32 },
8930 { ADD_F32x4_S, ADD_F32x4 },
8931 { ADD_F64_S, ADD_F64 },
8932 { ADD_F64x2_S, ADD_F64x2 },
8933 { ADD_I16x8_S, ADD_I16x8 },
8934 { ADD_I32_S, ADD_I32 },
8935 { ADD_I32x4_S, ADD_I32x4 },
8936 { ADD_I64_S, ADD_I64 },
8937 { ADD_I64x2_S, ADD_I64x2 },
8938 { ADD_I8x16_S, ADD_I8x16 },
8939 { ADD_SAT_S_I16x8_S, ADD_SAT_S_I16x8 },
8940 { ADD_SAT_S_I8x16_S, ADD_SAT_S_I8x16 },
8941 { ADD_SAT_U_I16x8_S, ADD_SAT_U_I16x8 },
8942 { ADD_SAT_U_I8x16_S, ADD_SAT_U_I8x16 },
8943 { ADJCALLSTACKDOWN_S, ADJCALLSTACKDOWN },
8944 { ADJCALLSTACKUP_S, ADJCALLSTACKUP },
8945 { ALLTRUE_I16x8_S, ALLTRUE_I16x8 },
8946 { ALLTRUE_I32x4_S, ALLTRUE_I32x4 },
8947 { ALLTRUE_I64x2_S, ALLTRUE_I64x2 },
8948 { ALLTRUE_I8x16_S, ALLTRUE_I8x16 },
8949 { ANDNOT_S, ANDNOT },
8950 { AND_I32_S, AND_I32 },
8951 { AND_I64_S, AND_I64 },
8952 { AND_S, AND },
8953 { ANYTRUE_S, ANYTRUE },
8954 { ARGUMENT_exnref_S, ARGUMENT_exnref },
8955 { ARGUMENT_externref_S, ARGUMENT_externref },
8956 { ARGUMENT_f32_S, ARGUMENT_f32 },
8957 { ARGUMENT_f64_S, ARGUMENT_f64 },
8958 { ARGUMENT_funcref_S, ARGUMENT_funcref },
8959 { ARGUMENT_i32_S, ARGUMENT_i32 },
8960 { ARGUMENT_i64_S, ARGUMENT_i64 },
8961 { ARGUMENT_v16i8_S, ARGUMENT_v16i8 },
8962 { ARGUMENT_v2f64_S, ARGUMENT_v2f64 },
8963 { ARGUMENT_v2i64_S, ARGUMENT_v2i64 },
8964 { ARGUMENT_v4f32_S, ARGUMENT_v4f32 },
8965 { ARGUMENT_v4i32_S, ARGUMENT_v4i32 },
8966 { ARGUMENT_v8f16_S, ARGUMENT_v8f16 },
8967 { ARGUMENT_v8i16_S, ARGUMENT_v8i16 },
8968 { ATOMIC_FENCE_S, ATOMIC_FENCE },
8969 { ATOMIC_LOAD16_U_I32_A32_S, ATOMIC_LOAD16_U_I32_A32 },
8970 { ATOMIC_LOAD16_U_I32_A64_S, ATOMIC_LOAD16_U_I32_A64 },
8971 { ATOMIC_LOAD16_U_I64_A32_S, ATOMIC_LOAD16_U_I64_A32 },
8972 { ATOMIC_LOAD16_U_I64_A64_S, ATOMIC_LOAD16_U_I64_A64 },
8973 { ATOMIC_LOAD32_U_I64_A32_S, ATOMIC_LOAD32_U_I64_A32 },
8974 { ATOMIC_LOAD32_U_I64_A64_S, ATOMIC_LOAD32_U_I64_A64 },
8975 { ATOMIC_LOAD8_U_I32_A32_S, ATOMIC_LOAD8_U_I32_A32 },
8976 { ATOMIC_LOAD8_U_I32_A64_S, ATOMIC_LOAD8_U_I32_A64 },
8977 { ATOMIC_LOAD8_U_I64_A32_S, ATOMIC_LOAD8_U_I64_A32 },
8978 { ATOMIC_LOAD8_U_I64_A64_S, ATOMIC_LOAD8_U_I64_A64 },
8979 { ATOMIC_LOAD_I32_A32_S, ATOMIC_LOAD_I32_A32 },
8980 { ATOMIC_LOAD_I32_A64_S, ATOMIC_LOAD_I32_A64 },
8981 { ATOMIC_LOAD_I64_A32_S, ATOMIC_LOAD_I64_A32 },
8982 { ATOMIC_LOAD_I64_A64_S, ATOMIC_LOAD_I64_A64 },
8983 { ATOMIC_RMW16_U_ADD_I32_A32_S, ATOMIC_RMW16_U_ADD_I32_A32 },
8984 { ATOMIC_RMW16_U_ADD_I32_A64_S, ATOMIC_RMW16_U_ADD_I32_A64 },
8985 { ATOMIC_RMW16_U_ADD_I64_A32_S, ATOMIC_RMW16_U_ADD_I64_A32 },
8986 { ATOMIC_RMW16_U_ADD_I64_A64_S, ATOMIC_RMW16_U_ADD_I64_A64 },
8987 { ATOMIC_RMW16_U_AND_I32_A32_S, ATOMIC_RMW16_U_AND_I32_A32 },
8988 { ATOMIC_RMW16_U_AND_I32_A64_S, ATOMIC_RMW16_U_AND_I32_A64 },
8989 { ATOMIC_RMW16_U_AND_I64_A32_S, ATOMIC_RMW16_U_AND_I64_A32 },
8990 { ATOMIC_RMW16_U_AND_I64_A64_S, ATOMIC_RMW16_U_AND_I64_A64 },
8991 { ATOMIC_RMW16_U_CMPXCHG_I32_A32_S, ATOMIC_RMW16_U_CMPXCHG_I32_A32 },
8992 { ATOMIC_RMW16_U_CMPXCHG_I32_A64_S, ATOMIC_RMW16_U_CMPXCHG_I32_A64 },
8993 { ATOMIC_RMW16_U_CMPXCHG_I64_A32_S, ATOMIC_RMW16_U_CMPXCHG_I64_A32 },
8994 { ATOMIC_RMW16_U_CMPXCHG_I64_A64_S, ATOMIC_RMW16_U_CMPXCHG_I64_A64 },
8995 { ATOMIC_RMW16_U_OR_I32_A32_S, ATOMIC_RMW16_U_OR_I32_A32 },
8996 { ATOMIC_RMW16_U_OR_I32_A64_S, ATOMIC_RMW16_U_OR_I32_A64 },
8997 { ATOMIC_RMW16_U_OR_I64_A32_S, ATOMIC_RMW16_U_OR_I64_A32 },
8998 { ATOMIC_RMW16_U_OR_I64_A64_S, ATOMIC_RMW16_U_OR_I64_A64 },
8999 { ATOMIC_RMW16_U_SUB_I32_A32_S, ATOMIC_RMW16_U_SUB_I32_A32 },
9000 { ATOMIC_RMW16_U_SUB_I32_A64_S, ATOMIC_RMW16_U_SUB_I32_A64 },
9001 { ATOMIC_RMW16_U_SUB_I64_A32_S, ATOMIC_RMW16_U_SUB_I64_A32 },
9002 { ATOMIC_RMW16_U_SUB_I64_A64_S, ATOMIC_RMW16_U_SUB_I64_A64 },
9003 { ATOMIC_RMW16_U_XCHG_I32_A32_S, ATOMIC_RMW16_U_XCHG_I32_A32 },
9004 { ATOMIC_RMW16_U_XCHG_I32_A64_S, ATOMIC_RMW16_U_XCHG_I32_A64 },
9005 { ATOMIC_RMW16_U_XCHG_I64_A32_S, ATOMIC_RMW16_U_XCHG_I64_A32 },
9006 { ATOMIC_RMW16_U_XCHG_I64_A64_S, ATOMIC_RMW16_U_XCHG_I64_A64 },
9007 { ATOMIC_RMW16_U_XOR_I32_A32_S, ATOMIC_RMW16_U_XOR_I32_A32 },
9008 { ATOMIC_RMW16_U_XOR_I32_A64_S, ATOMIC_RMW16_U_XOR_I32_A64 },
9009 { ATOMIC_RMW16_U_XOR_I64_A32_S, ATOMIC_RMW16_U_XOR_I64_A32 },
9010 { ATOMIC_RMW16_U_XOR_I64_A64_S, ATOMIC_RMW16_U_XOR_I64_A64 },
9011 { ATOMIC_RMW32_U_ADD_I64_A32_S, ATOMIC_RMW32_U_ADD_I64_A32 },
9012 { ATOMIC_RMW32_U_ADD_I64_A64_S, ATOMIC_RMW32_U_ADD_I64_A64 },
9013 { ATOMIC_RMW32_U_AND_I64_A32_S, ATOMIC_RMW32_U_AND_I64_A32 },
9014 { ATOMIC_RMW32_U_AND_I64_A64_S, ATOMIC_RMW32_U_AND_I64_A64 },
9015 { ATOMIC_RMW32_U_CMPXCHG_I64_A32_S, ATOMIC_RMW32_U_CMPXCHG_I64_A32 },
9016 { ATOMIC_RMW32_U_CMPXCHG_I64_A64_S, ATOMIC_RMW32_U_CMPXCHG_I64_A64 },
9017 { ATOMIC_RMW32_U_OR_I64_A32_S, ATOMIC_RMW32_U_OR_I64_A32 },
9018 { ATOMIC_RMW32_U_OR_I64_A64_S, ATOMIC_RMW32_U_OR_I64_A64 },
9019 { ATOMIC_RMW32_U_SUB_I64_A32_S, ATOMIC_RMW32_U_SUB_I64_A32 },
9020 { ATOMIC_RMW32_U_SUB_I64_A64_S, ATOMIC_RMW32_U_SUB_I64_A64 },
9021 { ATOMIC_RMW32_U_XCHG_I64_A32_S, ATOMIC_RMW32_U_XCHG_I64_A32 },
9022 { ATOMIC_RMW32_U_XCHG_I64_A64_S, ATOMIC_RMW32_U_XCHG_I64_A64 },
9023 { ATOMIC_RMW32_U_XOR_I64_A32_S, ATOMIC_RMW32_U_XOR_I64_A32 },
9024 { ATOMIC_RMW32_U_XOR_I64_A64_S, ATOMIC_RMW32_U_XOR_I64_A64 },
9025 { ATOMIC_RMW8_U_ADD_I32_A32_S, ATOMIC_RMW8_U_ADD_I32_A32 },
9026 { ATOMIC_RMW8_U_ADD_I32_A64_S, ATOMIC_RMW8_U_ADD_I32_A64 },
9027 { ATOMIC_RMW8_U_ADD_I64_A32_S, ATOMIC_RMW8_U_ADD_I64_A32 },
9028 { ATOMIC_RMW8_U_ADD_I64_A64_S, ATOMIC_RMW8_U_ADD_I64_A64 },
9029 { ATOMIC_RMW8_U_AND_I32_A32_S, ATOMIC_RMW8_U_AND_I32_A32 },
9030 { ATOMIC_RMW8_U_AND_I32_A64_S, ATOMIC_RMW8_U_AND_I32_A64 },
9031 { ATOMIC_RMW8_U_AND_I64_A32_S, ATOMIC_RMW8_U_AND_I64_A32 },
9032 { ATOMIC_RMW8_U_AND_I64_A64_S, ATOMIC_RMW8_U_AND_I64_A64 },
9033 { ATOMIC_RMW8_U_CMPXCHG_I32_A32_S, ATOMIC_RMW8_U_CMPXCHG_I32_A32 },
9034 { ATOMIC_RMW8_U_CMPXCHG_I32_A64_S, ATOMIC_RMW8_U_CMPXCHG_I32_A64 },
9035 { ATOMIC_RMW8_U_CMPXCHG_I64_A32_S, ATOMIC_RMW8_U_CMPXCHG_I64_A32 },
9036 { ATOMIC_RMW8_U_CMPXCHG_I64_A64_S, ATOMIC_RMW8_U_CMPXCHG_I64_A64 },
9037 { ATOMIC_RMW8_U_OR_I32_A32_S, ATOMIC_RMW8_U_OR_I32_A32 },
9038 { ATOMIC_RMW8_U_OR_I32_A64_S, ATOMIC_RMW8_U_OR_I32_A64 },
9039 { ATOMIC_RMW8_U_OR_I64_A32_S, ATOMIC_RMW8_U_OR_I64_A32 },
9040 { ATOMIC_RMW8_U_OR_I64_A64_S, ATOMIC_RMW8_U_OR_I64_A64 },
9041 { ATOMIC_RMW8_U_SUB_I32_A32_S, ATOMIC_RMW8_U_SUB_I32_A32 },
9042 { ATOMIC_RMW8_U_SUB_I32_A64_S, ATOMIC_RMW8_U_SUB_I32_A64 },
9043 { ATOMIC_RMW8_U_SUB_I64_A32_S, ATOMIC_RMW8_U_SUB_I64_A32 },
9044 { ATOMIC_RMW8_U_SUB_I64_A64_S, ATOMIC_RMW8_U_SUB_I64_A64 },
9045 { ATOMIC_RMW8_U_XCHG_I32_A32_S, ATOMIC_RMW8_U_XCHG_I32_A32 },
9046 { ATOMIC_RMW8_U_XCHG_I32_A64_S, ATOMIC_RMW8_U_XCHG_I32_A64 },
9047 { ATOMIC_RMW8_U_XCHG_I64_A32_S, ATOMIC_RMW8_U_XCHG_I64_A32 },
9048 { ATOMIC_RMW8_U_XCHG_I64_A64_S, ATOMIC_RMW8_U_XCHG_I64_A64 },
9049 { ATOMIC_RMW8_U_XOR_I32_A32_S, ATOMIC_RMW8_U_XOR_I32_A32 },
9050 { ATOMIC_RMW8_U_XOR_I32_A64_S, ATOMIC_RMW8_U_XOR_I32_A64 },
9051 { ATOMIC_RMW8_U_XOR_I64_A32_S, ATOMIC_RMW8_U_XOR_I64_A32 },
9052 { ATOMIC_RMW8_U_XOR_I64_A64_S, ATOMIC_RMW8_U_XOR_I64_A64 },
9053 { ATOMIC_RMW_ADD_I32_A32_S, ATOMIC_RMW_ADD_I32_A32 },
9054 { ATOMIC_RMW_ADD_I32_A64_S, ATOMIC_RMW_ADD_I32_A64 },
9055 { ATOMIC_RMW_ADD_I64_A32_S, ATOMIC_RMW_ADD_I64_A32 },
9056 { ATOMIC_RMW_ADD_I64_A64_S, ATOMIC_RMW_ADD_I64_A64 },
9057 { ATOMIC_RMW_AND_I32_A32_S, ATOMIC_RMW_AND_I32_A32 },
9058 { ATOMIC_RMW_AND_I32_A64_S, ATOMIC_RMW_AND_I32_A64 },
9059 { ATOMIC_RMW_AND_I64_A32_S, ATOMIC_RMW_AND_I64_A32 },
9060 { ATOMIC_RMW_AND_I64_A64_S, ATOMIC_RMW_AND_I64_A64 },
9061 { ATOMIC_RMW_CMPXCHG_I32_A32_S, ATOMIC_RMW_CMPXCHG_I32_A32 },
9062 { ATOMIC_RMW_CMPXCHG_I32_A64_S, ATOMIC_RMW_CMPXCHG_I32_A64 },
9063 { ATOMIC_RMW_CMPXCHG_I64_A32_S, ATOMIC_RMW_CMPXCHG_I64_A32 },
9064 { ATOMIC_RMW_CMPXCHG_I64_A64_S, ATOMIC_RMW_CMPXCHG_I64_A64 },
9065 { ATOMIC_RMW_OR_I32_A32_S, ATOMIC_RMW_OR_I32_A32 },
9066 { ATOMIC_RMW_OR_I32_A64_S, ATOMIC_RMW_OR_I32_A64 },
9067 { ATOMIC_RMW_OR_I64_A32_S, ATOMIC_RMW_OR_I64_A32 },
9068 { ATOMIC_RMW_OR_I64_A64_S, ATOMIC_RMW_OR_I64_A64 },
9069 { ATOMIC_RMW_SUB_I32_A32_S, ATOMIC_RMW_SUB_I32_A32 },
9070 { ATOMIC_RMW_SUB_I32_A64_S, ATOMIC_RMW_SUB_I32_A64 },
9071 { ATOMIC_RMW_SUB_I64_A32_S, ATOMIC_RMW_SUB_I64_A32 },
9072 { ATOMIC_RMW_SUB_I64_A64_S, ATOMIC_RMW_SUB_I64_A64 },
9073 { ATOMIC_RMW_XCHG_I32_A32_S, ATOMIC_RMW_XCHG_I32_A32 },
9074 { ATOMIC_RMW_XCHG_I32_A64_S, ATOMIC_RMW_XCHG_I32_A64 },
9075 { ATOMIC_RMW_XCHG_I64_A32_S, ATOMIC_RMW_XCHG_I64_A32 },
9076 { ATOMIC_RMW_XCHG_I64_A64_S, ATOMIC_RMW_XCHG_I64_A64 },
9077 { ATOMIC_RMW_XOR_I32_A32_S, ATOMIC_RMW_XOR_I32_A32 },
9078 { ATOMIC_RMW_XOR_I32_A64_S, ATOMIC_RMW_XOR_I32_A64 },
9079 { ATOMIC_RMW_XOR_I64_A32_S, ATOMIC_RMW_XOR_I64_A32 },
9080 { ATOMIC_RMW_XOR_I64_A64_S, ATOMIC_RMW_XOR_I64_A64 },
9081 { ATOMIC_STORE16_I32_A32_S, ATOMIC_STORE16_I32_A32 },
9082 { ATOMIC_STORE16_I32_A64_S, ATOMIC_STORE16_I32_A64 },
9083 { ATOMIC_STORE16_I64_A32_S, ATOMIC_STORE16_I64_A32 },
9084 { ATOMIC_STORE16_I64_A64_S, ATOMIC_STORE16_I64_A64 },
9085 { ATOMIC_STORE32_I64_A32_S, ATOMIC_STORE32_I64_A32 },
9086 { ATOMIC_STORE32_I64_A64_S, ATOMIC_STORE32_I64_A64 },
9087 { ATOMIC_STORE8_I32_A32_S, ATOMIC_STORE8_I32_A32 },
9088 { ATOMIC_STORE8_I32_A64_S, ATOMIC_STORE8_I32_A64 },
9089 { ATOMIC_STORE8_I64_A32_S, ATOMIC_STORE8_I64_A32 },
9090 { ATOMIC_STORE8_I64_A64_S, ATOMIC_STORE8_I64_A64 },
9091 { ATOMIC_STORE_I32_A32_S, ATOMIC_STORE_I32_A32 },
9092 { ATOMIC_STORE_I32_A64_S, ATOMIC_STORE_I32_A64 },
9093 { ATOMIC_STORE_I64_A32_S, ATOMIC_STORE_I64_A32 },
9094 { ATOMIC_STORE_I64_A64_S, ATOMIC_STORE_I64_A64 },
9095 { AVGR_U_I16x8_S, AVGR_U_I16x8 },
9096 { AVGR_U_I8x16_S, AVGR_U_I8x16 },
9097 { BITMASK_I16x8_S, BITMASK_I16x8 },
9098 { BITMASK_I32x4_S, BITMASK_I32x4 },
9099 { BITMASK_I64x2_S, BITMASK_I64x2 },
9100 { BITMASK_I8x16_S, BITMASK_I8x16 },
9101 { BITSELECT_S, BITSELECT },
9102 { BLOCK_S, BLOCK },
9103 { BR_IF_S, BR_IF },
9104 { BR_S, BR },
9105 { BR_TABLE_I32_S, BR_TABLE_I32 },
9106 { BR_TABLE_I64_S, BR_TABLE_I64 },
9107 { BR_UNLESS_S, BR_UNLESS },
9108 { CALL_INDIRECT_S, CALL_INDIRECT },
9109 { CALL_REF_S, CALL_REF },
9110 { CALL_S, CALL },
9111 { CATCH_ALL_LEGACY_S, CATCH_ALL_LEGACY },
9112 { CATCH_ALL_REF_S, CATCH_ALL_REF },
9113 { CATCH_ALL_S, CATCH_ALL },
9114 { CATCH_LEGACY_S, CATCH_LEGACY },
9115 { CATCH_REF_S, CATCH_REF },
9116 { CATCH_S, CATCH },
9117 { CEIL_F16x8_S, CEIL_F16x8 },
9118 { CEIL_F32_S, CEIL_F32 },
9119 { CEIL_F32x4_S, CEIL_F32x4 },
9120 { CEIL_F64_S, CEIL_F64 },
9121 { CEIL_F64x2_S, CEIL_F64x2 },
9122 { CLZ_I32_S, CLZ_I32 },
9123 { CLZ_I64_S, CLZ_I64 },
9124 { CONST_F32_S, CONST_F32 },
9125 { CONST_F64_S, CONST_F64 },
9126 { CONST_I32_S, CONST_I32 },
9127 { CONST_I64_S, CONST_I64 },
9128 { CONST_V128_F32x4_S, CONST_V128_F32x4 },
9129 { CONST_V128_F64x2_S, CONST_V128_F64x2 },
9130 { CONST_V128_I16x8_S, CONST_V128_I16x8 },
9131 { CONST_V128_I32x4_S, CONST_V128_I32x4 },
9132 { CONST_V128_I64x2_S, CONST_V128_I64x2 },
9133 { CONST_V128_I8x16_S, CONST_V128_I8x16 },
9134 { COPYSIGN_F32_S, COPYSIGN_F32 },
9135 { COPYSIGN_F64_S, COPYSIGN_F64 },
9136 { COPY_EXNREF_S, COPY_EXNREF },
9137 { COPY_EXTERNREF_S, COPY_EXTERNREF },
9138 { COPY_F32_S, COPY_F32 },
9139 { COPY_F64_S, COPY_F64 },
9140 { COPY_FUNCREF_S, COPY_FUNCREF },
9141 { COPY_I32_S, COPY_I32 },
9142 { COPY_I64_S, COPY_I64 },
9143 { COPY_V128_S, COPY_V128 },
9144 { CTZ_I32_S, CTZ_I32 },
9145 { CTZ_I64_S, CTZ_I64 },
9146 { DATA_DROP_S, DATA_DROP },
9147 { DEBUG_UNREACHABLE_S, DEBUG_UNREACHABLE },
9148 { DELEGATE_S, DELEGATE },
9149 { DIV_F16x8_S, DIV_F16x8 },
9150 { DIV_F32_S, DIV_F32 },
9151 { DIV_F32x4_S, DIV_F32x4 },
9152 { DIV_F64_S, DIV_F64 },
9153 { DIV_F64x2_S, DIV_F64x2 },
9154 { DIV_S_I32_S, DIV_S_I32 },
9155 { DIV_S_I64_S, DIV_S_I64 },
9156 { DIV_U_I32_S, DIV_U_I32 },
9157 { DIV_U_I64_S, DIV_U_I64 },
9158 { DOT_S, DOT },
9159 { DROP_EXNREF_S, DROP_EXNREF },
9160 { DROP_EXTERNREF_S, DROP_EXTERNREF },
9161 { DROP_F32_S, DROP_F32 },
9162 { DROP_F64_S, DROP_F64 },
9163 { DROP_FUNCREF_S, DROP_FUNCREF },
9164 { DROP_I32_S, DROP_I32 },
9165 { DROP_I64_S, DROP_I64 },
9166 { DROP_V128_S, DROP_V128 },
9167 { ELSE_S, ELSE },
9168 { END_BLOCK_S, END_BLOCK },
9169 { END_FUNCTION_S, END_FUNCTION },
9170 { END_IF_S, END_IF },
9171 { END_LOOP_S, END_LOOP },
9172 { END_S, END },
9173 { END_TRY_S, END_TRY },
9174 { END_TRY_TABLE_S, END_TRY_TABLE },
9175 { EQZ_I32_S, EQZ_I32 },
9176 { EQZ_I64_S, EQZ_I64 },
9177 { EQ_F16x8_S, EQ_F16x8 },
9178 { EQ_F32_S, EQ_F32 },
9179 { EQ_F32x4_S, EQ_F32x4 },
9180 { EQ_F64_S, EQ_F64 },
9181 { EQ_F64x2_S, EQ_F64x2 },
9182 { EQ_I16x8_S, EQ_I16x8 },
9183 { EQ_I32_S, EQ_I32 },
9184 { EQ_I32x4_S, EQ_I32x4 },
9185 { EQ_I64_S, EQ_I64 },
9186 { EQ_I64x2_S, EQ_I64x2 },
9187 { EQ_I8x16_S, EQ_I8x16 },
9188 { EXTMUL_HIGH_S_I16x8_S, EXTMUL_HIGH_S_I16x8 },
9189 { EXTMUL_HIGH_S_I32x4_S, EXTMUL_HIGH_S_I32x4 },
9190 { EXTMUL_HIGH_S_I64x2_S, EXTMUL_HIGH_S_I64x2 },
9191 { EXTMUL_HIGH_U_I16x8_S, EXTMUL_HIGH_U_I16x8 },
9192 { EXTMUL_HIGH_U_I32x4_S, EXTMUL_HIGH_U_I32x4 },
9193 { EXTMUL_HIGH_U_I64x2_S, EXTMUL_HIGH_U_I64x2 },
9194 { EXTMUL_LOW_S_I16x8_S, EXTMUL_LOW_S_I16x8 },
9195 { EXTMUL_LOW_S_I32x4_S, EXTMUL_LOW_S_I32x4 },
9196 { EXTMUL_LOW_S_I64x2_S, EXTMUL_LOW_S_I64x2 },
9197 { EXTMUL_LOW_U_I16x8_S, EXTMUL_LOW_U_I16x8 },
9198 { EXTMUL_LOW_U_I32x4_S, EXTMUL_LOW_U_I32x4 },
9199 { EXTMUL_LOW_U_I64x2_S, EXTMUL_LOW_U_I64x2 },
9200 { EXTRACT_LANE_F16x8_S, EXTRACT_LANE_F16x8 },
9201 { EXTRACT_LANE_F32x4_S, EXTRACT_LANE_F32x4 },
9202 { EXTRACT_LANE_F64x2_S, EXTRACT_LANE_F64x2 },
9203 { EXTRACT_LANE_I16x8_s_S, EXTRACT_LANE_I16x8_s },
9204 { EXTRACT_LANE_I16x8_u_S, EXTRACT_LANE_I16x8_u },
9205 { EXTRACT_LANE_I32x4_S, EXTRACT_LANE_I32x4 },
9206 { EXTRACT_LANE_I64x2_S, EXTRACT_LANE_I64x2 },
9207 { EXTRACT_LANE_I8x16_s_S, EXTRACT_LANE_I8x16_s },
9208 { EXTRACT_LANE_I8x16_u_S, EXTRACT_LANE_I8x16_u },
9209 { F32_CONVERT_S_I32_S, F32_CONVERT_S_I32 },
9210 { F32_CONVERT_S_I64_S, F32_CONVERT_S_I64 },
9211 { F32_CONVERT_U_I32_S, F32_CONVERT_U_I32 },
9212 { F32_CONVERT_U_I64_S, F32_CONVERT_U_I64 },
9213 { F32_DEMOTE_F64_S, F32_DEMOTE_F64 },
9214 { F32_REINTERPRET_I32_S, F32_REINTERPRET_I32 },
9215 { F64_CONVERT_S_I32_S, F64_CONVERT_S_I32 },
9216 { F64_CONVERT_S_I64_S, F64_CONVERT_S_I64 },
9217 { F64_CONVERT_U_I32_S, F64_CONVERT_U_I32 },
9218 { F64_CONVERT_U_I64_S, F64_CONVERT_U_I64 },
9219 { F64_PROMOTE_F32_S, F64_PROMOTE_F32 },
9220 { F64_REINTERPRET_I64_S, F64_REINTERPRET_I64 },
9221 { FALLTHROUGH_RETURN_S, FALLTHROUGH_RETURN },
9222 { FLOOR_F16x8_S, FLOOR_F16x8 },
9223 { FLOOR_F32_S, FLOOR_F32 },
9224 { FLOOR_F32x4_S, FLOOR_F32x4 },
9225 { FLOOR_F64_S, FLOOR_F64 },
9226 { FLOOR_F64x2_S, FLOOR_F64x2 },
9227 { FP_TO_SINT_I32_F32_S, FP_TO_SINT_I32_F32 },
9228 { FP_TO_SINT_I32_F64_S, FP_TO_SINT_I32_F64 },
9229 { FP_TO_SINT_I64_F32_S, FP_TO_SINT_I64_F32 },
9230 { FP_TO_SINT_I64_F64_S, FP_TO_SINT_I64_F64 },
9231 { FP_TO_UINT_I32_F32_S, FP_TO_UINT_I32_F32 },
9232 { FP_TO_UINT_I32_F64_S, FP_TO_UINT_I32_F64 },
9233 { FP_TO_UINT_I64_F32_S, FP_TO_UINT_I64_F32 },
9234 { FP_TO_UINT_I64_F64_S, FP_TO_UINT_I64_F64 },
9235 { GE_F16x8_S, GE_F16x8 },
9236 { GE_F32_S, GE_F32 },
9237 { GE_F32x4_S, GE_F32x4 },
9238 { GE_F64_S, GE_F64 },
9239 { GE_F64x2_S, GE_F64x2 },
9240 { GE_S_I16x8_S, GE_S_I16x8 },
9241 { GE_S_I32_S, GE_S_I32 },
9242 { GE_S_I32x4_S, GE_S_I32x4 },
9243 { GE_S_I64_S, GE_S_I64 },
9244 { GE_S_I64x2_S, GE_S_I64x2 },
9245 { GE_S_I8x16_S, GE_S_I8x16 },
9246 { GE_U_I16x8_S, GE_U_I16x8 },
9247 { GE_U_I32_S, GE_U_I32 },
9248 { GE_U_I32x4_S, GE_U_I32x4 },
9249 { GE_U_I64_S, GE_U_I64 },
9250 { GE_U_I8x16_S, GE_U_I8x16 },
9251 { GLOBAL_GET_EXNREF_S, GLOBAL_GET_EXNREF },
9252 { GLOBAL_GET_EXTERNREF_S, GLOBAL_GET_EXTERNREF },
9253 { GLOBAL_GET_F32_S, GLOBAL_GET_F32 },
9254 { GLOBAL_GET_F64_S, GLOBAL_GET_F64 },
9255 { GLOBAL_GET_FUNCREF_S, GLOBAL_GET_FUNCREF },
9256 { GLOBAL_GET_I32_S, GLOBAL_GET_I32 },
9257 { GLOBAL_GET_I64_S, GLOBAL_GET_I64 },
9258 { GLOBAL_GET_V128_S, GLOBAL_GET_V128 },
9259 { GLOBAL_SET_EXNREF_S, GLOBAL_SET_EXNREF },
9260 { GLOBAL_SET_EXTERNREF_S, GLOBAL_SET_EXTERNREF },
9261 { GLOBAL_SET_F32_S, GLOBAL_SET_F32 },
9262 { GLOBAL_SET_F64_S, GLOBAL_SET_F64 },
9263 { GLOBAL_SET_FUNCREF_S, GLOBAL_SET_FUNCREF },
9264 { GLOBAL_SET_I32_S, GLOBAL_SET_I32 },
9265 { GLOBAL_SET_I64_S, GLOBAL_SET_I64 },
9266 { GLOBAL_SET_V128_S, GLOBAL_SET_V128 },
9267 { GT_F16x8_S, GT_F16x8 },
9268 { GT_F32_S, GT_F32 },
9269 { GT_F32x4_S, GT_F32x4 },
9270 { GT_F64_S, GT_F64 },
9271 { GT_F64x2_S, GT_F64x2 },
9272 { GT_S_I16x8_S, GT_S_I16x8 },
9273 { GT_S_I32_S, GT_S_I32 },
9274 { GT_S_I32x4_S, GT_S_I32x4 },
9275 { GT_S_I64_S, GT_S_I64 },
9276 { GT_S_I64x2_S, GT_S_I64x2 },
9277 { GT_S_I8x16_S, GT_S_I8x16 },
9278 { GT_U_I16x8_S, GT_U_I16x8 },
9279 { GT_U_I32_S, GT_U_I32 },
9280 { GT_U_I32x4_S, GT_U_I32x4 },
9281 { GT_U_I64_S, GT_U_I64 },
9282 { GT_U_I8x16_S, GT_U_I8x16 },
9283 { I32_EXTEND16_S_I32_S, I32_EXTEND16_S_I32 },
9284 { I32_EXTEND8_S_I32_S, I32_EXTEND8_S_I32 },
9285 { I32_REINTERPRET_F32_S, I32_REINTERPRET_F32 },
9286 { I32_TRUNC_S_F32_S, I32_TRUNC_S_F32 },
9287 { I32_TRUNC_S_F64_S, I32_TRUNC_S_F64 },
9288 { I32_TRUNC_S_SAT_F32_S, I32_TRUNC_S_SAT_F32 },
9289 { I32_TRUNC_S_SAT_F64_S, I32_TRUNC_S_SAT_F64 },
9290 { I32_TRUNC_U_F32_S, I32_TRUNC_U_F32 },
9291 { I32_TRUNC_U_F64_S, I32_TRUNC_U_F64 },
9292 { I32_TRUNC_U_SAT_F32_S, I32_TRUNC_U_SAT_F32 },
9293 { I32_TRUNC_U_SAT_F64_S, I32_TRUNC_U_SAT_F64 },
9294 { I32_WRAP_I64_S, I32_WRAP_I64 },
9295 { I64_ADD128_S, I64_ADD128 },
9296 { I64_EXTEND16_S_I64_S, I64_EXTEND16_S_I64 },
9297 { I64_EXTEND32_S_I64_S, I64_EXTEND32_S_I64 },
9298 { I64_EXTEND8_S_I64_S, I64_EXTEND8_S_I64 },
9299 { I64_EXTEND_S_I32_S, I64_EXTEND_S_I32 },
9300 { I64_EXTEND_U_I32_S, I64_EXTEND_U_I32 },
9301 { I64_MUL_WIDE_S_S, I64_MUL_WIDE_S },
9302 { I64_MUL_WIDE_U_S, I64_MUL_WIDE_U },
9303 { I64_REINTERPRET_F64_S, I64_REINTERPRET_F64 },
9304 { I64_SUB128_S, I64_SUB128 },
9305 { I64_TRUNC_S_F32_S, I64_TRUNC_S_F32 },
9306 { I64_TRUNC_S_F64_S, I64_TRUNC_S_F64 },
9307 { I64_TRUNC_S_SAT_F32_S, I64_TRUNC_S_SAT_F32 },
9308 { I64_TRUNC_S_SAT_F64_S, I64_TRUNC_S_SAT_F64 },
9309 { I64_TRUNC_U_F32_S, I64_TRUNC_U_F32 },
9310 { I64_TRUNC_U_F64_S, I64_TRUNC_U_F64 },
9311 { I64_TRUNC_U_SAT_F32_S, I64_TRUNC_U_SAT_F32 },
9312 { I64_TRUNC_U_SAT_F64_S, I64_TRUNC_U_SAT_F64 },
9313 { IF_S, IF },
9314 { LANESELECT_I16x8_S, LANESELECT_I16x8 },
9315 { LANESELECT_I32x4_S, LANESELECT_I32x4 },
9316 { LANESELECT_I64x2_S, LANESELECT_I64x2 },
9317 { LANESELECT_I8x16_S, LANESELECT_I8x16 },
9318 { LE_F16x8_S, LE_F16x8 },
9319 { LE_F32_S, LE_F32 },
9320 { LE_F32x4_S, LE_F32x4 },
9321 { LE_F64_S, LE_F64 },
9322 { LE_F64x2_S, LE_F64x2 },
9323 { LE_S_I16x8_S, LE_S_I16x8 },
9324 { LE_S_I32_S, LE_S_I32 },
9325 { LE_S_I32x4_S, LE_S_I32x4 },
9326 { LE_S_I64_S, LE_S_I64 },
9327 { LE_S_I64x2_S, LE_S_I64x2 },
9328 { LE_S_I8x16_S, LE_S_I8x16 },
9329 { LE_U_I16x8_S, LE_U_I16x8 },
9330 { LE_U_I32_S, LE_U_I32 },
9331 { LE_U_I32x4_S, LE_U_I32x4 },
9332 { LE_U_I64_S, LE_U_I64 },
9333 { LE_U_I8x16_S, LE_U_I8x16 },
9334 { LOAD16_SPLAT_A32_S, LOAD16_SPLAT_A32 },
9335 { LOAD16_SPLAT_A64_S, LOAD16_SPLAT_A64 },
9336 { LOAD16_S_I32_A32_S, LOAD16_S_I32_A32 },
9337 { LOAD16_S_I32_A64_S, LOAD16_S_I32_A64 },
9338 { LOAD16_S_I64_A32_S, LOAD16_S_I64_A32 },
9339 { LOAD16_S_I64_A64_S, LOAD16_S_I64_A64 },
9340 { LOAD16_U_I32_A32_S, LOAD16_U_I32_A32 },
9341 { LOAD16_U_I32_A64_S, LOAD16_U_I32_A64 },
9342 { LOAD16_U_I64_A32_S, LOAD16_U_I64_A32 },
9343 { LOAD16_U_I64_A64_S, LOAD16_U_I64_A64 },
9344 { LOAD32_SPLAT_A32_S, LOAD32_SPLAT_A32 },
9345 { LOAD32_SPLAT_A64_S, LOAD32_SPLAT_A64 },
9346 { LOAD32_S_I64_A32_S, LOAD32_S_I64_A32 },
9347 { LOAD32_S_I64_A64_S, LOAD32_S_I64_A64 },
9348 { LOAD32_U_I64_A32_S, LOAD32_U_I64_A32 },
9349 { LOAD32_U_I64_A64_S, LOAD32_U_I64_A64 },
9350 { LOAD64_SPLAT_A32_S, LOAD64_SPLAT_A32 },
9351 { LOAD64_SPLAT_A64_S, LOAD64_SPLAT_A64 },
9352 { LOAD8_SPLAT_A32_S, LOAD8_SPLAT_A32 },
9353 { LOAD8_SPLAT_A64_S, LOAD8_SPLAT_A64 },
9354 { LOAD8_S_I32_A32_S, LOAD8_S_I32_A32 },
9355 { LOAD8_S_I32_A64_S, LOAD8_S_I32_A64 },
9356 { LOAD8_S_I64_A32_S, LOAD8_S_I64_A32 },
9357 { LOAD8_S_I64_A64_S, LOAD8_S_I64_A64 },
9358 { LOAD8_U_I32_A32_S, LOAD8_U_I32_A32 },
9359 { LOAD8_U_I32_A64_S, LOAD8_U_I32_A64 },
9360 { LOAD8_U_I64_A32_S, LOAD8_U_I64_A32 },
9361 { LOAD8_U_I64_A64_S, LOAD8_U_I64_A64 },
9362 { LOAD_EXTEND_S_I16x8_A32_S, LOAD_EXTEND_S_I16x8_A32 },
9363 { LOAD_EXTEND_S_I16x8_A64_S, LOAD_EXTEND_S_I16x8_A64 },
9364 { LOAD_EXTEND_S_I32x4_A32_S, LOAD_EXTEND_S_I32x4_A32 },
9365 { LOAD_EXTEND_S_I32x4_A64_S, LOAD_EXTEND_S_I32x4_A64 },
9366 { LOAD_EXTEND_S_I64x2_A32_S, LOAD_EXTEND_S_I64x2_A32 },
9367 { LOAD_EXTEND_S_I64x2_A64_S, LOAD_EXTEND_S_I64x2_A64 },
9368 { LOAD_EXTEND_U_I16x8_A32_S, LOAD_EXTEND_U_I16x8_A32 },
9369 { LOAD_EXTEND_U_I16x8_A64_S, LOAD_EXTEND_U_I16x8_A64 },
9370 { LOAD_EXTEND_U_I32x4_A32_S, LOAD_EXTEND_U_I32x4_A32 },
9371 { LOAD_EXTEND_U_I32x4_A64_S, LOAD_EXTEND_U_I32x4_A64 },
9372 { LOAD_EXTEND_U_I64x2_A32_S, LOAD_EXTEND_U_I64x2_A32 },
9373 { LOAD_EXTEND_U_I64x2_A64_S, LOAD_EXTEND_U_I64x2_A64 },
9374 { LOAD_F16_F32_A32_S, LOAD_F16_F32_A32 },
9375 { LOAD_F16_F32_A64_S, LOAD_F16_F32_A64 },
9376 { LOAD_F32_A32_S, LOAD_F32_A32 },
9377 { LOAD_F32_A64_S, LOAD_F32_A64 },
9378 { LOAD_F64_A32_S, LOAD_F64_A32 },
9379 { LOAD_F64_A64_S, LOAD_F64_A64 },
9380 { LOAD_I32_A32_S, LOAD_I32_A32 },
9381 { LOAD_I32_A64_S, LOAD_I32_A64 },
9382 { LOAD_I64_A32_S, LOAD_I64_A32 },
9383 { LOAD_I64_A64_S, LOAD_I64_A64 },
9384 { LOAD_LANE_16_A32_S, LOAD_LANE_16_A32 },
9385 { LOAD_LANE_16_A64_S, LOAD_LANE_16_A64 },
9386 { LOAD_LANE_32_A32_S, LOAD_LANE_32_A32 },
9387 { LOAD_LANE_32_A64_S, LOAD_LANE_32_A64 },
9388 { LOAD_LANE_64_A32_S, LOAD_LANE_64_A32 },
9389 { LOAD_LANE_64_A64_S, LOAD_LANE_64_A64 },
9390 { LOAD_LANE_8_A32_S, LOAD_LANE_8_A32 },
9391 { LOAD_LANE_8_A64_S, LOAD_LANE_8_A64 },
9392 { LOAD_V128_A32_S, LOAD_V128_A32 },
9393 { LOAD_V128_A64_S, LOAD_V128_A64 },
9394 { LOAD_ZERO_32_A32_S, LOAD_ZERO_32_A32 },
9395 { LOAD_ZERO_32_A64_S, LOAD_ZERO_32_A64 },
9396 { LOAD_ZERO_64_A32_S, LOAD_ZERO_64_A32 },
9397 { LOAD_ZERO_64_A64_S, LOAD_ZERO_64_A64 },
9398 { LOCAL_GET_EXNREF_S, LOCAL_GET_EXNREF },
9399 { LOCAL_GET_EXTERNREF_S, LOCAL_GET_EXTERNREF },
9400 { LOCAL_GET_F32_S, LOCAL_GET_F32 },
9401 { LOCAL_GET_F64_S, LOCAL_GET_F64 },
9402 { LOCAL_GET_FUNCREF_S, LOCAL_GET_FUNCREF },
9403 { LOCAL_GET_I32_S, LOCAL_GET_I32 },
9404 { LOCAL_GET_I64_S, LOCAL_GET_I64 },
9405 { LOCAL_GET_V128_S, LOCAL_GET_V128 },
9406 { LOCAL_SET_EXNREF_S, LOCAL_SET_EXNREF },
9407 { LOCAL_SET_EXTERNREF_S, LOCAL_SET_EXTERNREF },
9408 { LOCAL_SET_F32_S, LOCAL_SET_F32 },
9409 { LOCAL_SET_F64_S, LOCAL_SET_F64 },
9410 { LOCAL_SET_FUNCREF_S, LOCAL_SET_FUNCREF },
9411 { LOCAL_SET_I32_S, LOCAL_SET_I32 },
9412 { LOCAL_SET_I64_S, LOCAL_SET_I64 },
9413 { LOCAL_SET_V128_S, LOCAL_SET_V128 },
9414 { LOCAL_TEE_EXNREF_S, LOCAL_TEE_EXNREF },
9415 { LOCAL_TEE_EXTERNREF_S, LOCAL_TEE_EXTERNREF },
9416 { LOCAL_TEE_F32_S, LOCAL_TEE_F32 },
9417 { LOCAL_TEE_F64_S, LOCAL_TEE_F64 },
9418 { LOCAL_TEE_FUNCREF_S, LOCAL_TEE_FUNCREF },
9419 { LOCAL_TEE_I32_S, LOCAL_TEE_I32 },
9420 { LOCAL_TEE_I64_S, LOCAL_TEE_I64 },
9421 { LOCAL_TEE_V128_S, LOCAL_TEE_V128 },
9422 { LOOP_S, LOOP },
9423 { LT_F16x8_S, LT_F16x8 },
9424 { LT_F32_S, LT_F32 },
9425 { LT_F32x4_S, LT_F32x4 },
9426 { LT_F64_S, LT_F64 },
9427 { LT_F64x2_S, LT_F64x2 },
9428 { LT_S_I16x8_S, LT_S_I16x8 },
9429 { LT_S_I32_S, LT_S_I32 },
9430 { LT_S_I32x4_S, LT_S_I32x4 },
9431 { LT_S_I64_S, LT_S_I64 },
9432 { LT_S_I64x2_S, LT_S_I64x2 },
9433 { LT_S_I8x16_S, LT_S_I8x16 },
9434 { LT_U_I16x8_S, LT_U_I16x8 },
9435 { LT_U_I32_S, LT_U_I32 },
9436 { LT_U_I32x4_S, LT_U_I32x4 },
9437 { LT_U_I64_S, LT_U_I64 },
9438 { LT_U_I8x16_S, LT_U_I8x16 },
9439 { MADD_F16x8_S, MADD_F16x8 },
9440 { MADD_F32x4_S, MADD_F32x4 },
9441 { MADD_F64x2_S, MADD_F64x2 },
9442 { MAX_F16x8_S, MAX_F16x8 },
9443 { MAX_F32_S, MAX_F32 },
9444 { MAX_F32x4_S, MAX_F32x4 },
9445 { MAX_F64_S, MAX_F64 },
9446 { MAX_F64x2_S, MAX_F64x2 },
9447 { MAX_S_I16x8_S, MAX_S_I16x8 },
9448 { MAX_S_I32x4_S, MAX_S_I32x4 },
9449 { MAX_S_I8x16_S, MAX_S_I8x16 },
9450 { MAX_U_I16x8_S, MAX_U_I16x8 },
9451 { MAX_U_I32x4_S, MAX_U_I32x4 },
9452 { MAX_U_I8x16_S, MAX_U_I8x16 },
9453 { MEMCPY_A32_S, MEMCPY_A32 },
9454 { MEMCPY_A64_S, MEMCPY_A64 },
9455 { MEMORY_ATOMIC_NOTIFY_A32_S, MEMORY_ATOMIC_NOTIFY_A32 },
9456 { MEMORY_ATOMIC_NOTIFY_A64_S, MEMORY_ATOMIC_NOTIFY_A64 },
9457 { MEMORY_ATOMIC_WAIT32_A32_S, MEMORY_ATOMIC_WAIT32_A32 },
9458 { MEMORY_ATOMIC_WAIT32_A64_S, MEMORY_ATOMIC_WAIT32_A64 },
9459 { MEMORY_ATOMIC_WAIT64_A32_S, MEMORY_ATOMIC_WAIT64_A32 },
9460 { MEMORY_ATOMIC_WAIT64_A64_S, MEMORY_ATOMIC_WAIT64_A64 },
9461 { MEMORY_COPY_A32_S, MEMORY_COPY_A32 },
9462 { MEMORY_COPY_A64_S, MEMORY_COPY_A64 },
9463 { MEMORY_FILL_A32_S, MEMORY_FILL_A32 },
9464 { MEMORY_FILL_A64_S, MEMORY_FILL_A64 },
9465 { MEMORY_INIT_A32_S, MEMORY_INIT_A32 },
9466 { MEMORY_INIT_A64_S, MEMORY_INIT_A64 },
9467 { MEMSET_A32_S, MEMSET_A32 },
9468 { MEMSET_A64_S, MEMSET_A64 },
9469 { MIN_F16x8_S, MIN_F16x8 },
9470 { MIN_F32_S, MIN_F32 },
9471 { MIN_F32x4_S, MIN_F32x4 },
9472 { MIN_F64_S, MIN_F64 },
9473 { MIN_F64x2_S, MIN_F64x2 },
9474 { MIN_S_I16x8_S, MIN_S_I16x8 },
9475 { MIN_S_I32x4_S, MIN_S_I32x4 },
9476 { MIN_S_I8x16_S, MIN_S_I8x16 },
9477 { MIN_U_I16x8_S, MIN_U_I16x8 },
9478 { MIN_U_I32x4_S, MIN_U_I32x4 },
9479 { MIN_U_I8x16_S, MIN_U_I8x16 },
9480 { MUL_F16x8_S, MUL_F16x8 },
9481 { MUL_F32_S, MUL_F32 },
9482 { MUL_F32x4_S, MUL_F32x4 },
9483 { MUL_F64_S, MUL_F64 },
9484 { MUL_F64x2_S, MUL_F64x2 },
9485 { MUL_I16x8_S, MUL_I16x8 },
9486 { MUL_I32_S, MUL_I32 },
9487 { MUL_I32x4_S, MUL_I32x4 },
9488 { MUL_I64_S, MUL_I64 },
9489 { MUL_I64x2_S, MUL_I64x2 },
9490 { NARROW_S_I16x8_S, NARROW_S_I16x8 },
9491 { NARROW_S_I8x16_S, NARROW_S_I8x16 },
9492 { NARROW_U_I16x8_S, NARROW_U_I16x8 },
9493 { NARROW_U_I8x16_S, NARROW_U_I8x16 },
9494 { NEAREST_F16x8_S, NEAREST_F16x8 },
9495 { NEAREST_F32_S, NEAREST_F32 },
9496 { NEAREST_F32x4_S, NEAREST_F32x4 },
9497 { NEAREST_F64_S, NEAREST_F64 },
9498 { NEAREST_F64x2_S, NEAREST_F64x2 },
9499 { NEG_F16x8_S, NEG_F16x8 },
9500 { NEG_F32_S, NEG_F32 },
9501 { NEG_F32x4_S, NEG_F32x4 },
9502 { NEG_F64_S, NEG_F64 },
9503 { NEG_F64x2_S, NEG_F64x2 },
9504 { NEG_I16x8_S, NEG_I16x8 },
9505 { NEG_I32x4_S, NEG_I32x4 },
9506 { NEG_I64x2_S, NEG_I64x2 },
9507 { NEG_I8x16_S, NEG_I8x16 },
9508 { NE_F16x8_S, NE_F16x8 },
9509 { NE_F32_S, NE_F32 },
9510 { NE_F32x4_S, NE_F32x4 },
9511 { NE_F64_S, NE_F64 },
9512 { NE_F64x2_S, NE_F64x2 },
9513 { NE_I16x8_S, NE_I16x8 },
9514 { NE_I32_S, NE_I32 },
9515 { NE_I32x4_S, NE_I32x4 },
9516 { NE_I64_S, NE_I64 },
9517 { NE_I64x2_S, NE_I64x2 },
9518 { NE_I8x16_S, NE_I8x16 },
9519 { NMADD_F16x8_S, NMADD_F16x8 },
9520 { NMADD_F32x4_S, NMADD_F32x4 },
9521 { NMADD_F64x2_S, NMADD_F64x2 },
9522 { NOP_S, NOP },
9523 { NOT_S, NOT },
9524 { OR_I32_S, OR_I32 },
9525 { OR_I64_S, OR_I64 },
9526 { OR_S, OR },
9527 { PMAX_F16x8_S, PMAX_F16x8 },
9528 { PMAX_F32x4_S, PMAX_F32x4 },
9529 { PMAX_F64x2_S, PMAX_F64x2 },
9530 { PMIN_F16x8_S, PMIN_F16x8 },
9531 { PMIN_F32x4_S, PMIN_F32x4 },
9532 { PMIN_F64x2_S, PMIN_F64x2 },
9533 { POPCNT_I32_S, POPCNT_I32 },
9534 { POPCNT_I64_S, POPCNT_I64 },
9535 { POPCNT_I8x16_S, POPCNT_I8x16 },
9536 { Q15MULR_SAT_S_I16x8_S, Q15MULR_SAT_S_I16x8 },
9537 { REF_CAST_FUNCREF_S, REF_CAST_FUNCREF },
9538 { REF_FUNC_S, REF_FUNC },
9539 { REF_IS_NULL_EXNREF_S, REF_IS_NULL_EXNREF },
9540 { REF_IS_NULL_EXTERNREF_S, REF_IS_NULL_EXTERNREF },
9541 { REF_IS_NULL_FUNCREF_S, REF_IS_NULL_FUNCREF },
9542 { REF_NULL_EXNREF_S, REF_NULL_EXNREF },
9543 { REF_NULL_EXTERNREF_S, REF_NULL_EXTERNREF },
9544 { REF_NULL_FUNCREF_S, REF_NULL_FUNCREF },
9545 { REF_TEST_FUNCREF_S, REF_TEST_FUNCREF },
9546 { RELAXED_DOT_ADD_S, RELAXED_DOT_ADD },
9547 { RELAXED_DOT_BFLOAT_S, RELAXED_DOT_BFLOAT },
9548 { RELAXED_DOT_S, RELAXED_DOT },
9549 { RELAXED_Q15MULR_S_I16x8_S, RELAXED_Q15MULR_S_I16x8 },
9550 { RELAXED_SWIZZLE_S, RELAXED_SWIZZLE },
9551 { REM_S_I32_S, REM_S_I32 },
9552 { REM_S_I64_S, REM_S_I64 },
9553 { REM_U_I32_S, REM_U_I32 },
9554 { REM_U_I64_S, REM_U_I64 },
9555 { REPLACE_LANE_F16x8_S, REPLACE_LANE_F16x8 },
9556 { REPLACE_LANE_F32x4_S, REPLACE_LANE_F32x4 },
9557 { REPLACE_LANE_F64x2_S, REPLACE_LANE_F64x2 },
9558 { REPLACE_LANE_I16x8_S, REPLACE_LANE_I16x8 },
9559 { REPLACE_LANE_I32x4_S, REPLACE_LANE_I32x4 },
9560 { REPLACE_LANE_I64x2_S, REPLACE_LANE_I64x2 },
9561 { REPLACE_LANE_I8x16_S, REPLACE_LANE_I8x16 },
9562 { RETHROW_S, RETHROW },
9563 { RETURN_S, RETURN },
9564 { RET_CALL_INDIRECT_S, RET_CALL_INDIRECT },
9565 { RET_CALL_REF_S, RET_CALL_REF },
9566 { RET_CALL_S, RET_CALL },
9567 { ROTL_I32_S, ROTL_I32 },
9568 { ROTL_I64_S, ROTL_I64 },
9569 { ROTR_I32_S, ROTR_I32 },
9570 { ROTR_I64_S, ROTR_I64 },
9571 { SELECT_EXNREF_S, SELECT_EXNREF },
9572 { SELECT_EXTERNREF_S, SELECT_EXTERNREF },
9573 { SELECT_F32_S, SELECT_F32 },
9574 { SELECT_F64_S, SELECT_F64 },
9575 { SELECT_FUNCREF_S, SELECT_FUNCREF },
9576 { SELECT_I32_S, SELECT_I32 },
9577 { SELECT_I64_S, SELECT_I64 },
9578 { SELECT_T_S, SELECT_T },
9579 { SELECT_V128_S, SELECT_V128 },
9580 { SHL_I16x8_S, SHL_I16x8 },
9581 { SHL_I32_S, SHL_I32 },
9582 { SHL_I32x4_S, SHL_I32x4 },
9583 { SHL_I64_S, SHL_I64 },
9584 { SHL_I64x2_S, SHL_I64x2 },
9585 { SHL_I8x16_S, SHL_I8x16 },
9586 { SHR_S_I16x8_S, SHR_S_I16x8 },
9587 { SHR_S_I32_S, SHR_S_I32 },
9588 { SHR_S_I32x4_S, SHR_S_I32x4 },
9589 { SHR_S_I64_S, SHR_S_I64 },
9590 { SHR_S_I64x2_S, SHR_S_I64x2 },
9591 { SHR_S_I8x16_S, SHR_S_I8x16 },
9592 { SHR_U_I16x8_S, SHR_U_I16x8 },
9593 { SHR_U_I32_S, SHR_U_I32 },
9594 { SHR_U_I32x4_S, SHR_U_I32x4 },
9595 { SHR_U_I64_S, SHR_U_I64 },
9596 { SHR_U_I64x2_S, SHR_U_I64x2 },
9597 { SHR_U_I8x16_S, SHR_U_I8x16 },
9598 { SHUFFLE_S, SHUFFLE },
9599 { SIMD_RELAXED_FMAX_F32x4_S, SIMD_RELAXED_FMAX_F32x4 },
9600 { SIMD_RELAXED_FMAX_F64x2_S, SIMD_RELAXED_FMAX_F64x2 },
9601 { SIMD_RELAXED_FMIN_F32x4_S, SIMD_RELAXED_FMIN_F32x4 },
9602 { SIMD_RELAXED_FMIN_F64x2_S, SIMD_RELAXED_FMIN_F64x2 },
9603 { SPLAT_F16x8_S, SPLAT_F16x8 },
9604 { SPLAT_F32x4_S, SPLAT_F32x4 },
9605 { SPLAT_F64x2_S, SPLAT_F64x2 },
9606 { SPLAT_I16x8_S, SPLAT_I16x8 },
9607 { SPLAT_I32x4_S, SPLAT_I32x4 },
9608 { SPLAT_I64x2_S, SPLAT_I64x2 },
9609 { SPLAT_I8x16_S, SPLAT_I8x16 },
9610 { SQRT_F16x8_S, SQRT_F16x8 },
9611 { SQRT_F32_S, SQRT_F32 },
9612 { SQRT_F32x4_S, SQRT_F32x4 },
9613 { SQRT_F64_S, SQRT_F64 },
9614 { SQRT_F64x2_S, SQRT_F64x2 },
9615 { STORE16_I32_A32_S, STORE16_I32_A32 },
9616 { STORE16_I32_A64_S, STORE16_I32_A64 },
9617 { STORE16_I64_A32_S, STORE16_I64_A32 },
9618 { STORE16_I64_A64_S, STORE16_I64_A64 },
9619 { STORE32_I64_A32_S, STORE32_I64_A32 },
9620 { STORE32_I64_A64_S, STORE32_I64_A64 },
9621 { STORE8_I32_A32_S, STORE8_I32_A32 },
9622 { STORE8_I32_A64_S, STORE8_I32_A64 },
9623 { STORE8_I64_A32_S, STORE8_I64_A32 },
9624 { STORE8_I64_A64_S, STORE8_I64_A64 },
9625 { STORE_F16_F32_A32_S, STORE_F16_F32_A32 },
9626 { STORE_F16_F32_A64_S, STORE_F16_F32_A64 },
9627 { STORE_F32_A32_S, STORE_F32_A32 },
9628 { STORE_F32_A64_S, STORE_F32_A64 },
9629 { STORE_F64_A32_S, STORE_F64_A32 },
9630 { STORE_F64_A64_S, STORE_F64_A64 },
9631 { STORE_I32_A32_S, STORE_I32_A32 },
9632 { STORE_I32_A64_S, STORE_I32_A64 },
9633 { STORE_I64_A32_S, STORE_I64_A32 },
9634 { STORE_I64_A64_S, STORE_I64_A64 },
9635 { STORE_LANE_I16x8_A32_S, STORE_LANE_I16x8_A32 },
9636 { STORE_LANE_I16x8_A64_S, STORE_LANE_I16x8_A64 },
9637 { STORE_LANE_I32x4_A32_S, STORE_LANE_I32x4_A32 },
9638 { STORE_LANE_I32x4_A64_S, STORE_LANE_I32x4_A64 },
9639 { STORE_LANE_I64x2_A32_S, STORE_LANE_I64x2_A32 },
9640 { STORE_LANE_I64x2_A64_S, STORE_LANE_I64x2_A64 },
9641 { STORE_LANE_I8x16_A32_S, STORE_LANE_I8x16_A32 },
9642 { STORE_LANE_I8x16_A64_S, STORE_LANE_I8x16_A64 },
9643 { STORE_V128_A32_S, STORE_V128_A32 },
9644 { STORE_V128_A64_S, STORE_V128_A64 },
9645 { SUB_F16x8_S, SUB_F16x8 },
9646 { SUB_F32_S, SUB_F32 },
9647 { SUB_F32x4_S, SUB_F32x4 },
9648 { SUB_F64_S, SUB_F64 },
9649 { SUB_F64x2_S, SUB_F64x2 },
9650 { SUB_I16x8_S, SUB_I16x8 },
9651 { SUB_I32_S, SUB_I32 },
9652 { SUB_I32x4_S, SUB_I32x4 },
9653 { SUB_I64_S, SUB_I64 },
9654 { SUB_I64x2_S, SUB_I64x2 },
9655 { SUB_I8x16_S, SUB_I8x16 },
9656 { SUB_SAT_S_I16x8_S, SUB_SAT_S_I16x8 },
9657 { SUB_SAT_S_I8x16_S, SUB_SAT_S_I8x16 },
9658 { SUB_SAT_U_I16x8_S, SUB_SAT_U_I16x8 },
9659 { SUB_SAT_U_I8x16_S, SUB_SAT_U_I8x16 },
9660 { SWIZZLE_S, SWIZZLE },
9661 { TABLE_COPY_S, TABLE_COPY },
9662 { TABLE_FILL_EXNREF_S, TABLE_FILL_EXNREF },
9663 { TABLE_FILL_EXTERNREF_S, TABLE_FILL_EXTERNREF },
9664 { TABLE_FILL_FUNCREF_S, TABLE_FILL_FUNCREF },
9665 { TABLE_GET_EXNREF_S, TABLE_GET_EXNREF },
9666 { TABLE_GET_EXTERNREF_S, TABLE_GET_EXTERNREF },
9667 { TABLE_GET_FUNCREF_S, TABLE_GET_FUNCREF },
9668 { TABLE_GROW_EXNREF_S, TABLE_GROW_EXNREF },
9669 { TABLE_GROW_EXTERNREF_S, TABLE_GROW_EXTERNREF },
9670 { TABLE_GROW_FUNCREF_S, TABLE_GROW_FUNCREF },
9671 { TABLE_SET_EXNREF_S, TABLE_SET_EXNREF },
9672 { TABLE_SET_EXTERNREF_S, TABLE_SET_EXTERNREF },
9673 { TABLE_SET_FUNCREF_S, TABLE_SET_FUNCREF },
9674 { TABLE_SIZE_S, TABLE_SIZE },
9675 { TEE_EXNREF_S, TEE_EXNREF },
9676 { TEE_EXTERNREF_S, TEE_EXTERNREF },
9677 { TEE_F32_S, TEE_F32 },
9678 { TEE_F64_S, TEE_F64 },
9679 { TEE_FUNCREF_S, TEE_FUNCREF },
9680 { TEE_I32_S, TEE_I32 },
9681 { TEE_I64_S, TEE_I64 },
9682 { TEE_V128_S, TEE_V128 },
9683 { THROW_REF_S, THROW_REF },
9684 { THROW_S, THROW },
9685 { TRUNC_F16x8_S, TRUNC_F16x8 },
9686 { TRUNC_F32_S, TRUNC_F32 },
9687 { TRUNC_F32x4_S, TRUNC_F32x4 },
9688 { TRUNC_F64_S, TRUNC_F64 },
9689 { TRUNC_F64x2_S, TRUNC_F64x2 },
9690 { TRY_S, TRY },
9691 { TRY_TABLE_S, TRY_TABLE },
9692 { UNREACHABLE_S, UNREACHABLE },
9693 { XOR_I32_S, XOR_I32 },
9694 { XOR_I64_S, XOR_I64 },
9695 { XOR_S, XOR },
9696 { anonymous_14422MEMORY_GROW_A32_S, anonymous_14422MEMORY_GROW_A32 },
9697 { anonymous_14422MEMORY_SIZE_A32_S, anonymous_14422MEMORY_SIZE_A32 },
9698 { anonymous_14423MEMORY_GROW_A64_S, anonymous_14423MEMORY_GROW_A64 },
9699 { anonymous_14423MEMORY_SIZE_A64_S, anonymous_14423MEMORY_SIZE_A64 },
9700 { convert_low_s_F64x2_S, convert_low_s_F64x2 },
9701 { convert_low_u_F64x2_S, convert_low_u_F64x2 },
9702 { demote_zero_F16x8_S, demote_zero_F16x8 },
9703 { demote_zero_F32x4_S, demote_zero_F32x4 },
9704 { extadd_pairwise_s_I16x8_S, extadd_pairwise_s_I16x8 },
9705 { extadd_pairwise_s_I32x4_S, extadd_pairwise_s_I32x4 },
9706 { extadd_pairwise_u_I16x8_S, extadd_pairwise_u_I16x8 },
9707 { extadd_pairwise_u_I32x4_S, extadd_pairwise_u_I32x4 },
9708 { extend_high_s_I16x8_S, extend_high_s_I16x8 },
9709 { extend_high_s_I32x4_S, extend_high_s_I32x4 },
9710 { extend_high_s_I64x2_S, extend_high_s_I64x2 },
9711 { extend_high_u_I16x8_S, extend_high_u_I16x8 },
9712 { extend_high_u_I32x4_S, extend_high_u_I32x4 },
9713 { extend_high_u_I64x2_S, extend_high_u_I64x2 },
9714 { extend_low_s_I16x8_S, extend_low_s_I16x8 },
9715 { extend_low_s_I32x4_S, extend_low_s_I32x4 },
9716 { extend_low_s_I64x2_S, extend_low_s_I64x2 },
9717 { extend_low_u_I16x8_S, extend_low_u_I16x8 },
9718 { extend_low_u_I32x4_S, extend_low_u_I32x4 },
9719 { extend_low_u_I64x2_S, extend_low_u_I64x2 },
9720 { fp_to_sint_I16x8_S, fp_to_sint_I16x8 },
9721 { fp_to_sint_I32x4_S, fp_to_sint_I32x4 },
9722 { fp_to_uint_I16x8_S, fp_to_uint_I16x8 },
9723 { fp_to_uint_I32x4_S, fp_to_uint_I32x4 },
9724 { int_wasm_relaxed_trunc_signed_I32x4_S, int_wasm_relaxed_trunc_signed_I32x4 },
9725 { int_wasm_relaxed_trunc_signed_zero_I32x4_S, int_wasm_relaxed_trunc_signed_zero_I32x4 },
9726 { int_wasm_relaxed_trunc_unsigned_I32x4_S, int_wasm_relaxed_trunc_unsigned_I32x4 },
9727 { int_wasm_relaxed_trunc_unsigned_zero_I32x4_S, int_wasm_relaxed_trunc_unsigned_zero_I32x4 },
9728 { promote_low_F32x4_S, promote_low_F32x4 },
9729 { promote_low_F64x2_S, promote_low_F64x2 },
9730 { sint_to_fp_F16x8_S, sint_to_fp_F16x8 },
9731 { sint_to_fp_F32x4_S, sint_to_fp_F32x4 },
9732 { trunc_sat_zero_s_I32x4_S, trunc_sat_zero_s_I32x4 },
9733 { trunc_sat_zero_u_I32x4_S, trunc_sat_zero_u_I32x4 },
9734 { uint_to_fp_F16x8_S, uint_to_fp_F16x8 },
9735 { uint_to_fp_F32x4_S, uint_to_fp_F32x4 },
9736 }; // End of Table
9737
9738 unsigned mid;
9739 unsigned start = 0;
9740 unsigned end = 823;
9741 while (start < end) {
9742 mid = start + (end - start) / 2;
9743 if (Opcode == Table[mid][0])
9744 break;
9745 if (Opcode < Table[mid][0])
9746 end = mid;
9747 else
9748 start = mid + 1;
9749 }
9750 if (start == end)
9751 return -1; // Instruction doesn't exist in this table.
9752
9753 return Table[mid][1];
9754}
9755
9756// getStackOpcode
9757LLVM_READONLY
9758int32_t getStackOpcode(uint32_t Opcode) {
9759 using namespace WebAssembly;
9760 static constexpr uint32_t Table[][2] = {
9761 { CALL_PARAMS, CALL_PARAMS_S },
9762 { CALL_RESULTS, CALL_RESULTS_S },
9763 { CATCHRET, CATCHRET_S },
9764 { CLEANUPRET, CLEANUPRET_S },
9765 { COMPILER_FENCE, COMPILER_FENCE_S },
9766 { RET_CALL_RESULTS, RET_CALL_RESULTS_S },
9767 { ABS_F16x8, ABS_F16x8_S },
9768 { ABS_F32, ABS_F32_S },
9769 { ABS_F32x4, ABS_F32x4_S },
9770 { ABS_F64, ABS_F64_S },
9771 { ABS_F64x2, ABS_F64x2_S },
9772 { ABS_I16x8, ABS_I16x8_S },
9773 { ABS_I32x4, ABS_I32x4_S },
9774 { ABS_I64x2, ABS_I64x2_S },
9775 { ABS_I8x16, ABS_I8x16_S },
9776 { ADD_F16x8, ADD_F16x8_S },
9777 { ADD_F32, ADD_F32_S },
9778 { ADD_F32x4, ADD_F32x4_S },
9779 { ADD_F64, ADD_F64_S },
9780 { ADD_F64x2, ADD_F64x2_S },
9781 { ADD_I16x8, ADD_I16x8_S },
9782 { ADD_I32, ADD_I32_S },
9783 { ADD_I32x4, ADD_I32x4_S },
9784 { ADD_I64, ADD_I64_S },
9785 { ADD_I64x2, ADD_I64x2_S },
9786 { ADD_I8x16, ADD_I8x16_S },
9787 { ADD_SAT_S_I16x8, ADD_SAT_S_I16x8_S },
9788 { ADD_SAT_S_I8x16, ADD_SAT_S_I8x16_S },
9789 { ADD_SAT_U_I16x8, ADD_SAT_U_I16x8_S },
9790 { ADD_SAT_U_I8x16, ADD_SAT_U_I8x16_S },
9791 { ADJCALLSTACKDOWN, ADJCALLSTACKDOWN_S },
9792 { ADJCALLSTACKUP, ADJCALLSTACKUP_S },
9793 { ALLTRUE_I16x8, ALLTRUE_I16x8_S },
9794 { ALLTRUE_I32x4, ALLTRUE_I32x4_S },
9795 { ALLTRUE_I64x2, ALLTRUE_I64x2_S },
9796 { ALLTRUE_I8x16, ALLTRUE_I8x16_S },
9797 { AND, AND_S },
9798 { ANDNOT, ANDNOT_S },
9799 { AND_I32, AND_I32_S },
9800 { AND_I64, AND_I64_S },
9801 { ANYTRUE, ANYTRUE_S },
9802 { ARGUMENT_exnref, ARGUMENT_exnref_S },
9803 { ARGUMENT_externref, ARGUMENT_externref_S },
9804 { ARGUMENT_f32, ARGUMENT_f32_S },
9805 { ARGUMENT_f64, ARGUMENT_f64_S },
9806 { ARGUMENT_funcref, ARGUMENT_funcref_S },
9807 { ARGUMENT_i32, ARGUMENT_i32_S },
9808 { ARGUMENT_i64, ARGUMENT_i64_S },
9809 { ARGUMENT_v16i8, ARGUMENT_v16i8_S },
9810 { ARGUMENT_v2f64, ARGUMENT_v2f64_S },
9811 { ARGUMENT_v2i64, ARGUMENT_v2i64_S },
9812 { ARGUMENT_v4f32, ARGUMENT_v4f32_S },
9813 { ARGUMENT_v4i32, ARGUMENT_v4i32_S },
9814 { ARGUMENT_v8f16, ARGUMENT_v8f16_S },
9815 { ARGUMENT_v8i16, ARGUMENT_v8i16_S },
9816 { ATOMIC_FENCE, ATOMIC_FENCE_S },
9817 { ATOMIC_LOAD16_U_I32_A32, ATOMIC_LOAD16_U_I32_A32_S },
9818 { ATOMIC_LOAD16_U_I32_A64, ATOMIC_LOAD16_U_I32_A64_S },
9819 { ATOMIC_LOAD16_U_I64_A32, ATOMIC_LOAD16_U_I64_A32_S },
9820 { ATOMIC_LOAD16_U_I64_A64, ATOMIC_LOAD16_U_I64_A64_S },
9821 { ATOMIC_LOAD32_U_I64_A32, ATOMIC_LOAD32_U_I64_A32_S },
9822 { ATOMIC_LOAD32_U_I64_A64, ATOMIC_LOAD32_U_I64_A64_S },
9823 { ATOMIC_LOAD8_U_I32_A32, ATOMIC_LOAD8_U_I32_A32_S },
9824 { ATOMIC_LOAD8_U_I32_A64, ATOMIC_LOAD8_U_I32_A64_S },
9825 { ATOMIC_LOAD8_U_I64_A32, ATOMIC_LOAD8_U_I64_A32_S },
9826 { ATOMIC_LOAD8_U_I64_A64, ATOMIC_LOAD8_U_I64_A64_S },
9827 { ATOMIC_LOAD_I32_A32, ATOMIC_LOAD_I32_A32_S },
9828 { ATOMIC_LOAD_I32_A64, ATOMIC_LOAD_I32_A64_S },
9829 { ATOMIC_LOAD_I64_A32, ATOMIC_LOAD_I64_A32_S },
9830 { ATOMIC_LOAD_I64_A64, ATOMIC_LOAD_I64_A64_S },
9831 { ATOMIC_RMW16_U_ADD_I32_A32, ATOMIC_RMW16_U_ADD_I32_A32_S },
9832 { ATOMIC_RMW16_U_ADD_I32_A64, ATOMIC_RMW16_U_ADD_I32_A64_S },
9833 { ATOMIC_RMW16_U_ADD_I64_A32, ATOMIC_RMW16_U_ADD_I64_A32_S },
9834 { ATOMIC_RMW16_U_ADD_I64_A64, ATOMIC_RMW16_U_ADD_I64_A64_S },
9835 { ATOMIC_RMW16_U_AND_I32_A32, ATOMIC_RMW16_U_AND_I32_A32_S },
9836 { ATOMIC_RMW16_U_AND_I32_A64, ATOMIC_RMW16_U_AND_I32_A64_S },
9837 { ATOMIC_RMW16_U_AND_I64_A32, ATOMIC_RMW16_U_AND_I64_A32_S },
9838 { ATOMIC_RMW16_U_AND_I64_A64, ATOMIC_RMW16_U_AND_I64_A64_S },
9839 { ATOMIC_RMW16_U_CMPXCHG_I32_A32, ATOMIC_RMW16_U_CMPXCHG_I32_A32_S },
9840 { ATOMIC_RMW16_U_CMPXCHG_I32_A64, ATOMIC_RMW16_U_CMPXCHG_I32_A64_S },
9841 { ATOMIC_RMW16_U_CMPXCHG_I64_A32, ATOMIC_RMW16_U_CMPXCHG_I64_A32_S },
9842 { ATOMIC_RMW16_U_CMPXCHG_I64_A64, ATOMIC_RMW16_U_CMPXCHG_I64_A64_S },
9843 { ATOMIC_RMW16_U_OR_I32_A32, ATOMIC_RMW16_U_OR_I32_A32_S },
9844 { ATOMIC_RMW16_U_OR_I32_A64, ATOMIC_RMW16_U_OR_I32_A64_S },
9845 { ATOMIC_RMW16_U_OR_I64_A32, ATOMIC_RMW16_U_OR_I64_A32_S },
9846 { ATOMIC_RMW16_U_OR_I64_A64, ATOMIC_RMW16_U_OR_I64_A64_S },
9847 { ATOMIC_RMW16_U_SUB_I32_A32, ATOMIC_RMW16_U_SUB_I32_A32_S },
9848 { ATOMIC_RMW16_U_SUB_I32_A64, ATOMIC_RMW16_U_SUB_I32_A64_S },
9849 { ATOMIC_RMW16_U_SUB_I64_A32, ATOMIC_RMW16_U_SUB_I64_A32_S },
9850 { ATOMIC_RMW16_U_SUB_I64_A64, ATOMIC_RMW16_U_SUB_I64_A64_S },
9851 { ATOMIC_RMW16_U_XCHG_I32_A32, ATOMIC_RMW16_U_XCHG_I32_A32_S },
9852 { ATOMIC_RMW16_U_XCHG_I32_A64, ATOMIC_RMW16_U_XCHG_I32_A64_S },
9853 { ATOMIC_RMW16_U_XCHG_I64_A32, ATOMIC_RMW16_U_XCHG_I64_A32_S },
9854 { ATOMIC_RMW16_U_XCHG_I64_A64, ATOMIC_RMW16_U_XCHG_I64_A64_S },
9855 { ATOMIC_RMW16_U_XOR_I32_A32, ATOMIC_RMW16_U_XOR_I32_A32_S },
9856 { ATOMIC_RMW16_U_XOR_I32_A64, ATOMIC_RMW16_U_XOR_I32_A64_S },
9857 { ATOMIC_RMW16_U_XOR_I64_A32, ATOMIC_RMW16_U_XOR_I64_A32_S },
9858 { ATOMIC_RMW16_U_XOR_I64_A64, ATOMIC_RMW16_U_XOR_I64_A64_S },
9859 { ATOMIC_RMW32_U_ADD_I64_A32, ATOMIC_RMW32_U_ADD_I64_A32_S },
9860 { ATOMIC_RMW32_U_ADD_I64_A64, ATOMIC_RMW32_U_ADD_I64_A64_S },
9861 { ATOMIC_RMW32_U_AND_I64_A32, ATOMIC_RMW32_U_AND_I64_A32_S },
9862 { ATOMIC_RMW32_U_AND_I64_A64, ATOMIC_RMW32_U_AND_I64_A64_S },
9863 { ATOMIC_RMW32_U_CMPXCHG_I64_A32, ATOMIC_RMW32_U_CMPXCHG_I64_A32_S },
9864 { ATOMIC_RMW32_U_CMPXCHG_I64_A64, ATOMIC_RMW32_U_CMPXCHG_I64_A64_S },
9865 { ATOMIC_RMW32_U_OR_I64_A32, ATOMIC_RMW32_U_OR_I64_A32_S },
9866 { ATOMIC_RMW32_U_OR_I64_A64, ATOMIC_RMW32_U_OR_I64_A64_S },
9867 { ATOMIC_RMW32_U_SUB_I64_A32, ATOMIC_RMW32_U_SUB_I64_A32_S },
9868 { ATOMIC_RMW32_U_SUB_I64_A64, ATOMIC_RMW32_U_SUB_I64_A64_S },
9869 { ATOMIC_RMW32_U_XCHG_I64_A32, ATOMIC_RMW32_U_XCHG_I64_A32_S },
9870 { ATOMIC_RMW32_U_XCHG_I64_A64, ATOMIC_RMW32_U_XCHG_I64_A64_S },
9871 { ATOMIC_RMW32_U_XOR_I64_A32, ATOMIC_RMW32_U_XOR_I64_A32_S },
9872 { ATOMIC_RMW32_U_XOR_I64_A64, ATOMIC_RMW32_U_XOR_I64_A64_S },
9873 { ATOMIC_RMW8_U_ADD_I32_A32, ATOMIC_RMW8_U_ADD_I32_A32_S },
9874 { ATOMIC_RMW8_U_ADD_I32_A64, ATOMIC_RMW8_U_ADD_I32_A64_S },
9875 { ATOMIC_RMW8_U_ADD_I64_A32, ATOMIC_RMW8_U_ADD_I64_A32_S },
9876 { ATOMIC_RMW8_U_ADD_I64_A64, ATOMIC_RMW8_U_ADD_I64_A64_S },
9877 { ATOMIC_RMW8_U_AND_I32_A32, ATOMIC_RMW8_U_AND_I32_A32_S },
9878 { ATOMIC_RMW8_U_AND_I32_A64, ATOMIC_RMW8_U_AND_I32_A64_S },
9879 { ATOMIC_RMW8_U_AND_I64_A32, ATOMIC_RMW8_U_AND_I64_A32_S },
9880 { ATOMIC_RMW8_U_AND_I64_A64, ATOMIC_RMW8_U_AND_I64_A64_S },
9881 { ATOMIC_RMW8_U_CMPXCHG_I32_A32, ATOMIC_RMW8_U_CMPXCHG_I32_A32_S },
9882 { ATOMIC_RMW8_U_CMPXCHG_I32_A64, ATOMIC_RMW8_U_CMPXCHG_I32_A64_S },
9883 { ATOMIC_RMW8_U_CMPXCHG_I64_A32, ATOMIC_RMW8_U_CMPXCHG_I64_A32_S },
9884 { ATOMIC_RMW8_U_CMPXCHG_I64_A64, ATOMIC_RMW8_U_CMPXCHG_I64_A64_S },
9885 { ATOMIC_RMW8_U_OR_I32_A32, ATOMIC_RMW8_U_OR_I32_A32_S },
9886 { ATOMIC_RMW8_U_OR_I32_A64, ATOMIC_RMW8_U_OR_I32_A64_S },
9887 { ATOMIC_RMW8_U_OR_I64_A32, ATOMIC_RMW8_U_OR_I64_A32_S },
9888 { ATOMIC_RMW8_U_OR_I64_A64, ATOMIC_RMW8_U_OR_I64_A64_S },
9889 { ATOMIC_RMW8_U_SUB_I32_A32, ATOMIC_RMW8_U_SUB_I32_A32_S },
9890 { ATOMIC_RMW8_U_SUB_I32_A64, ATOMIC_RMW8_U_SUB_I32_A64_S },
9891 { ATOMIC_RMW8_U_SUB_I64_A32, ATOMIC_RMW8_U_SUB_I64_A32_S },
9892 { ATOMIC_RMW8_U_SUB_I64_A64, ATOMIC_RMW8_U_SUB_I64_A64_S },
9893 { ATOMIC_RMW8_U_XCHG_I32_A32, ATOMIC_RMW8_U_XCHG_I32_A32_S },
9894 { ATOMIC_RMW8_U_XCHG_I32_A64, ATOMIC_RMW8_U_XCHG_I32_A64_S },
9895 { ATOMIC_RMW8_U_XCHG_I64_A32, ATOMIC_RMW8_U_XCHG_I64_A32_S },
9896 { ATOMIC_RMW8_U_XCHG_I64_A64, ATOMIC_RMW8_U_XCHG_I64_A64_S },
9897 { ATOMIC_RMW8_U_XOR_I32_A32, ATOMIC_RMW8_U_XOR_I32_A32_S },
9898 { ATOMIC_RMW8_U_XOR_I32_A64, ATOMIC_RMW8_U_XOR_I32_A64_S },
9899 { ATOMIC_RMW8_U_XOR_I64_A32, ATOMIC_RMW8_U_XOR_I64_A32_S },
9900 { ATOMIC_RMW8_U_XOR_I64_A64, ATOMIC_RMW8_U_XOR_I64_A64_S },
9901 { ATOMIC_RMW_ADD_I32_A32, ATOMIC_RMW_ADD_I32_A32_S },
9902 { ATOMIC_RMW_ADD_I32_A64, ATOMIC_RMW_ADD_I32_A64_S },
9903 { ATOMIC_RMW_ADD_I64_A32, ATOMIC_RMW_ADD_I64_A32_S },
9904 { ATOMIC_RMW_ADD_I64_A64, ATOMIC_RMW_ADD_I64_A64_S },
9905 { ATOMIC_RMW_AND_I32_A32, ATOMIC_RMW_AND_I32_A32_S },
9906 { ATOMIC_RMW_AND_I32_A64, ATOMIC_RMW_AND_I32_A64_S },
9907 { ATOMIC_RMW_AND_I64_A32, ATOMIC_RMW_AND_I64_A32_S },
9908 { ATOMIC_RMW_AND_I64_A64, ATOMIC_RMW_AND_I64_A64_S },
9909 { ATOMIC_RMW_CMPXCHG_I32_A32, ATOMIC_RMW_CMPXCHG_I32_A32_S },
9910 { ATOMIC_RMW_CMPXCHG_I32_A64, ATOMIC_RMW_CMPXCHG_I32_A64_S },
9911 { ATOMIC_RMW_CMPXCHG_I64_A32, ATOMIC_RMW_CMPXCHG_I64_A32_S },
9912 { ATOMIC_RMW_CMPXCHG_I64_A64, ATOMIC_RMW_CMPXCHG_I64_A64_S },
9913 { ATOMIC_RMW_OR_I32_A32, ATOMIC_RMW_OR_I32_A32_S },
9914 { ATOMIC_RMW_OR_I32_A64, ATOMIC_RMW_OR_I32_A64_S },
9915 { ATOMIC_RMW_OR_I64_A32, ATOMIC_RMW_OR_I64_A32_S },
9916 { ATOMIC_RMW_OR_I64_A64, ATOMIC_RMW_OR_I64_A64_S },
9917 { ATOMIC_RMW_SUB_I32_A32, ATOMIC_RMW_SUB_I32_A32_S },
9918 { ATOMIC_RMW_SUB_I32_A64, ATOMIC_RMW_SUB_I32_A64_S },
9919 { ATOMIC_RMW_SUB_I64_A32, ATOMIC_RMW_SUB_I64_A32_S },
9920 { ATOMIC_RMW_SUB_I64_A64, ATOMIC_RMW_SUB_I64_A64_S },
9921 { ATOMIC_RMW_XCHG_I32_A32, ATOMIC_RMW_XCHG_I32_A32_S },
9922 { ATOMIC_RMW_XCHG_I32_A64, ATOMIC_RMW_XCHG_I32_A64_S },
9923 { ATOMIC_RMW_XCHG_I64_A32, ATOMIC_RMW_XCHG_I64_A32_S },
9924 { ATOMIC_RMW_XCHG_I64_A64, ATOMIC_RMW_XCHG_I64_A64_S },
9925 { ATOMIC_RMW_XOR_I32_A32, ATOMIC_RMW_XOR_I32_A32_S },
9926 { ATOMIC_RMW_XOR_I32_A64, ATOMIC_RMW_XOR_I32_A64_S },
9927 { ATOMIC_RMW_XOR_I64_A32, ATOMIC_RMW_XOR_I64_A32_S },
9928 { ATOMIC_RMW_XOR_I64_A64, ATOMIC_RMW_XOR_I64_A64_S },
9929 { ATOMIC_STORE16_I32_A32, ATOMIC_STORE16_I32_A32_S },
9930 { ATOMIC_STORE16_I32_A64, ATOMIC_STORE16_I32_A64_S },
9931 { ATOMIC_STORE16_I64_A32, ATOMIC_STORE16_I64_A32_S },
9932 { ATOMIC_STORE16_I64_A64, ATOMIC_STORE16_I64_A64_S },
9933 { ATOMIC_STORE32_I64_A32, ATOMIC_STORE32_I64_A32_S },
9934 { ATOMIC_STORE32_I64_A64, ATOMIC_STORE32_I64_A64_S },
9935 { ATOMIC_STORE8_I32_A32, ATOMIC_STORE8_I32_A32_S },
9936 { ATOMIC_STORE8_I32_A64, ATOMIC_STORE8_I32_A64_S },
9937 { ATOMIC_STORE8_I64_A32, ATOMIC_STORE8_I64_A32_S },
9938 { ATOMIC_STORE8_I64_A64, ATOMIC_STORE8_I64_A64_S },
9939 { ATOMIC_STORE_I32_A32, ATOMIC_STORE_I32_A32_S },
9940 { ATOMIC_STORE_I32_A64, ATOMIC_STORE_I32_A64_S },
9941 { ATOMIC_STORE_I64_A32, ATOMIC_STORE_I64_A32_S },
9942 { ATOMIC_STORE_I64_A64, ATOMIC_STORE_I64_A64_S },
9943 { AVGR_U_I16x8, AVGR_U_I16x8_S },
9944 { AVGR_U_I8x16, AVGR_U_I8x16_S },
9945 { BITMASK_I16x8, BITMASK_I16x8_S },
9946 { BITMASK_I32x4, BITMASK_I32x4_S },
9947 { BITMASK_I64x2, BITMASK_I64x2_S },
9948 { BITMASK_I8x16, BITMASK_I8x16_S },
9949 { BITSELECT, BITSELECT_S },
9950 { BLOCK, BLOCK_S },
9951 { BR, BR_S },
9952 { BR_IF, BR_IF_S },
9953 { BR_TABLE_I32, BR_TABLE_I32_S },
9954 { BR_TABLE_I64, BR_TABLE_I64_S },
9955 { BR_UNLESS, BR_UNLESS_S },
9956 { CALL, CALL_S },
9957 { CALL_INDIRECT, CALL_INDIRECT_S },
9958 { CALL_REF, CALL_REF_S },
9959 { CATCH, CATCH_S },
9960 { CATCH_ALL, CATCH_ALL_S },
9961 { CATCH_ALL_LEGACY, CATCH_ALL_LEGACY_S },
9962 { CATCH_ALL_REF, CATCH_ALL_REF_S },
9963 { CATCH_LEGACY, CATCH_LEGACY_S },
9964 { CATCH_REF, CATCH_REF_S },
9965 { CEIL_F16x8, CEIL_F16x8_S },
9966 { CEIL_F32, CEIL_F32_S },
9967 { CEIL_F32x4, CEIL_F32x4_S },
9968 { CEIL_F64, CEIL_F64_S },
9969 { CEIL_F64x2, CEIL_F64x2_S },
9970 { CLZ_I32, CLZ_I32_S },
9971 { CLZ_I64, CLZ_I64_S },
9972 { CONST_F32, CONST_F32_S },
9973 { CONST_F64, CONST_F64_S },
9974 { CONST_I32, CONST_I32_S },
9975 { CONST_I64, CONST_I64_S },
9976 { CONST_V128_F32x4, CONST_V128_F32x4_S },
9977 { CONST_V128_F64x2, CONST_V128_F64x2_S },
9978 { CONST_V128_I16x8, CONST_V128_I16x8_S },
9979 { CONST_V128_I32x4, CONST_V128_I32x4_S },
9980 { CONST_V128_I64x2, CONST_V128_I64x2_S },
9981 { CONST_V128_I8x16, CONST_V128_I8x16_S },
9982 { COPYSIGN_F32, COPYSIGN_F32_S },
9983 { COPYSIGN_F64, COPYSIGN_F64_S },
9984 { COPY_EXNREF, COPY_EXNREF_S },
9985 { COPY_EXTERNREF, COPY_EXTERNREF_S },
9986 { COPY_F32, COPY_F32_S },
9987 { COPY_F64, COPY_F64_S },
9988 { COPY_FUNCREF, COPY_FUNCREF_S },
9989 { COPY_I32, COPY_I32_S },
9990 { COPY_I64, COPY_I64_S },
9991 { COPY_V128, COPY_V128_S },
9992 { CTZ_I32, CTZ_I32_S },
9993 { CTZ_I64, CTZ_I64_S },
9994 { DATA_DROP, DATA_DROP_S },
9995 { DEBUG_UNREACHABLE, DEBUG_UNREACHABLE_S },
9996 { DELEGATE, DELEGATE_S },
9997 { DIV_F16x8, DIV_F16x8_S },
9998 { DIV_F32, DIV_F32_S },
9999 { DIV_F32x4, DIV_F32x4_S },
10000 { DIV_F64, DIV_F64_S },
10001 { DIV_F64x2, DIV_F64x2_S },
10002 { DIV_S_I32, DIV_S_I32_S },
10003 { DIV_S_I64, DIV_S_I64_S },
10004 { DIV_U_I32, DIV_U_I32_S },
10005 { DIV_U_I64, DIV_U_I64_S },
10006 { DOT, DOT_S },
10007 { DROP_EXNREF, DROP_EXNREF_S },
10008 { DROP_EXTERNREF, DROP_EXTERNREF_S },
10009 { DROP_F32, DROP_F32_S },
10010 { DROP_F64, DROP_F64_S },
10011 { DROP_FUNCREF, DROP_FUNCREF_S },
10012 { DROP_I32, DROP_I32_S },
10013 { DROP_I64, DROP_I64_S },
10014 { DROP_V128, DROP_V128_S },
10015 { ELSE, ELSE_S },
10016 { END, END_S },
10017 { END_BLOCK, END_BLOCK_S },
10018 { END_FUNCTION, END_FUNCTION_S },
10019 { END_IF, END_IF_S },
10020 { END_LOOP, END_LOOP_S },
10021 { END_TRY, END_TRY_S },
10022 { END_TRY_TABLE, END_TRY_TABLE_S },
10023 { EQZ_I32, EQZ_I32_S },
10024 { EQZ_I64, EQZ_I64_S },
10025 { EQ_F16x8, EQ_F16x8_S },
10026 { EQ_F32, EQ_F32_S },
10027 { EQ_F32x4, EQ_F32x4_S },
10028 { EQ_F64, EQ_F64_S },
10029 { EQ_F64x2, EQ_F64x2_S },
10030 { EQ_I16x8, EQ_I16x8_S },
10031 { EQ_I32, EQ_I32_S },
10032 { EQ_I32x4, EQ_I32x4_S },
10033 { EQ_I64, EQ_I64_S },
10034 { EQ_I64x2, EQ_I64x2_S },
10035 { EQ_I8x16, EQ_I8x16_S },
10036 { EXTMUL_HIGH_S_I16x8, EXTMUL_HIGH_S_I16x8_S },
10037 { EXTMUL_HIGH_S_I32x4, EXTMUL_HIGH_S_I32x4_S },
10038 { EXTMUL_HIGH_S_I64x2, EXTMUL_HIGH_S_I64x2_S },
10039 { EXTMUL_HIGH_U_I16x8, EXTMUL_HIGH_U_I16x8_S },
10040 { EXTMUL_HIGH_U_I32x4, EXTMUL_HIGH_U_I32x4_S },
10041 { EXTMUL_HIGH_U_I64x2, EXTMUL_HIGH_U_I64x2_S },
10042 { EXTMUL_LOW_S_I16x8, EXTMUL_LOW_S_I16x8_S },
10043 { EXTMUL_LOW_S_I32x4, EXTMUL_LOW_S_I32x4_S },
10044 { EXTMUL_LOW_S_I64x2, EXTMUL_LOW_S_I64x2_S },
10045 { EXTMUL_LOW_U_I16x8, EXTMUL_LOW_U_I16x8_S },
10046 { EXTMUL_LOW_U_I32x4, EXTMUL_LOW_U_I32x4_S },
10047 { EXTMUL_LOW_U_I64x2, EXTMUL_LOW_U_I64x2_S },
10048 { EXTRACT_LANE_F16x8, EXTRACT_LANE_F16x8_S },
10049 { EXTRACT_LANE_F32x4, EXTRACT_LANE_F32x4_S },
10050 { EXTRACT_LANE_F64x2, EXTRACT_LANE_F64x2_S },
10051 { EXTRACT_LANE_I16x8_s, EXTRACT_LANE_I16x8_s_S },
10052 { EXTRACT_LANE_I16x8_u, EXTRACT_LANE_I16x8_u_S },
10053 { EXTRACT_LANE_I32x4, EXTRACT_LANE_I32x4_S },
10054 { EXTRACT_LANE_I64x2, EXTRACT_LANE_I64x2_S },
10055 { EXTRACT_LANE_I8x16_s, EXTRACT_LANE_I8x16_s_S },
10056 { EXTRACT_LANE_I8x16_u, EXTRACT_LANE_I8x16_u_S },
10057 { F32_CONVERT_S_I32, F32_CONVERT_S_I32_S },
10058 { F32_CONVERT_S_I64, F32_CONVERT_S_I64_S },
10059 { F32_CONVERT_U_I32, F32_CONVERT_U_I32_S },
10060 { F32_CONVERT_U_I64, F32_CONVERT_U_I64_S },
10061 { F32_DEMOTE_F64, F32_DEMOTE_F64_S },
10062 { F32_REINTERPRET_I32, F32_REINTERPRET_I32_S },
10063 { F64_CONVERT_S_I32, F64_CONVERT_S_I32_S },
10064 { F64_CONVERT_S_I64, F64_CONVERT_S_I64_S },
10065 { F64_CONVERT_U_I32, F64_CONVERT_U_I32_S },
10066 { F64_CONVERT_U_I64, F64_CONVERT_U_I64_S },
10067 { F64_PROMOTE_F32, F64_PROMOTE_F32_S },
10068 { F64_REINTERPRET_I64, F64_REINTERPRET_I64_S },
10069 { FALLTHROUGH_RETURN, FALLTHROUGH_RETURN_S },
10070 { FLOOR_F16x8, FLOOR_F16x8_S },
10071 { FLOOR_F32, FLOOR_F32_S },
10072 { FLOOR_F32x4, FLOOR_F32x4_S },
10073 { FLOOR_F64, FLOOR_F64_S },
10074 { FLOOR_F64x2, FLOOR_F64x2_S },
10075 { FP_TO_SINT_I32_F32, FP_TO_SINT_I32_F32_S },
10076 { FP_TO_SINT_I32_F64, FP_TO_SINT_I32_F64_S },
10077 { FP_TO_SINT_I64_F32, FP_TO_SINT_I64_F32_S },
10078 { FP_TO_SINT_I64_F64, FP_TO_SINT_I64_F64_S },
10079 { FP_TO_UINT_I32_F32, FP_TO_UINT_I32_F32_S },
10080 { FP_TO_UINT_I32_F64, FP_TO_UINT_I32_F64_S },
10081 { FP_TO_UINT_I64_F32, FP_TO_UINT_I64_F32_S },
10082 { FP_TO_UINT_I64_F64, FP_TO_UINT_I64_F64_S },
10083 { GE_F16x8, GE_F16x8_S },
10084 { GE_F32, GE_F32_S },
10085 { GE_F32x4, GE_F32x4_S },
10086 { GE_F64, GE_F64_S },
10087 { GE_F64x2, GE_F64x2_S },
10088 { GE_S_I16x8, GE_S_I16x8_S },
10089 { GE_S_I32, GE_S_I32_S },
10090 { GE_S_I32x4, GE_S_I32x4_S },
10091 { GE_S_I64, GE_S_I64_S },
10092 { GE_S_I64x2, GE_S_I64x2_S },
10093 { GE_S_I8x16, GE_S_I8x16_S },
10094 { GE_U_I16x8, GE_U_I16x8_S },
10095 { GE_U_I32, GE_U_I32_S },
10096 { GE_U_I32x4, GE_U_I32x4_S },
10097 { GE_U_I64, GE_U_I64_S },
10098 { GE_U_I8x16, GE_U_I8x16_S },
10099 { GLOBAL_GET_EXNREF, GLOBAL_GET_EXNREF_S },
10100 { GLOBAL_GET_EXTERNREF, GLOBAL_GET_EXTERNREF_S },
10101 { GLOBAL_GET_F32, GLOBAL_GET_F32_S },
10102 { GLOBAL_GET_F64, GLOBAL_GET_F64_S },
10103 { GLOBAL_GET_FUNCREF, GLOBAL_GET_FUNCREF_S },
10104 { GLOBAL_GET_I32, GLOBAL_GET_I32_S },
10105 { GLOBAL_GET_I64, GLOBAL_GET_I64_S },
10106 { GLOBAL_GET_V128, GLOBAL_GET_V128_S },
10107 { GLOBAL_SET_EXNREF, GLOBAL_SET_EXNREF_S },
10108 { GLOBAL_SET_EXTERNREF, GLOBAL_SET_EXTERNREF_S },
10109 { GLOBAL_SET_F32, GLOBAL_SET_F32_S },
10110 { GLOBAL_SET_F64, GLOBAL_SET_F64_S },
10111 { GLOBAL_SET_FUNCREF, GLOBAL_SET_FUNCREF_S },
10112 { GLOBAL_SET_I32, GLOBAL_SET_I32_S },
10113 { GLOBAL_SET_I64, GLOBAL_SET_I64_S },
10114 { GLOBAL_SET_V128, GLOBAL_SET_V128_S },
10115 { GT_F16x8, GT_F16x8_S },
10116 { GT_F32, GT_F32_S },
10117 { GT_F32x4, GT_F32x4_S },
10118 { GT_F64, GT_F64_S },
10119 { GT_F64x2, GT_F64x2_S },
10120 { GT_S_I16x8, GT_S_I16x8_S },
10121 { GT_S_I32, GT_S_I32_S },
10122 { GT_S_I32x4, GT_S_I32x4_S },
10123 { GT_S_I64, GT_S_I64_S },
10124 { GT_S_I64x2, GT_S_I64x2_S },
10125 { GT_S_I8x16, GT_S_I8x16_S },
10126 { GT_U_I16x8, GT_U_I16x8_S },
10127 { GT_U_I32, GT_U_I32_S },
10128 { GT_U_I32x4, GT_U_I32x4_S },
10129 { GT_U_I64, GT_U_I64_S },
10130 { GT_U_I8x16, GT_U_I8x16_S },
10131 { I32_EXTEND16_S_I32, I32_EXTEND16_S_I32_S },
10132 { I32_EXTEND8_S_I32, I32_EXTEND8_S_I32_S },
10133 { I32_REINTERPRET_F32, I32_REINTERPRET_F32_S },
10134 { I32_TRUNC_S_F32, I32_TRUNC_S_F32_S },
10135 { I32_TRUNC_S_F64, I32_TRUNC_S_F64_S },
10136 { I32_TRUNC_S_SAT_F32, I32_TRUNC_S_SAT_F32_S },
10137 { I32_TRUNC_S_SAT_F64, I32_TRUNC_S_SAT_F64_S },
10138 { I32_TRUNC_U_F32, I32_TRUNC_U_F32_S },
10139 { I32_TRUNC_U_F64, I32_TRUNC_U_F64_S },
10140 { I32_TRUNC_U_SAT_F32, I32_TRUNC_U_SAT_F32_S },
10141 { I32_TRUNC_U_SAT_F64, I32_TRUNC_U_SAT_F64_S },
10142 { I32_WRAP_I64, I32_WRAP_I64_S },
10143 { I64_ADD128, I64_ADD128_S },
10144 { I64_EXTEND16_S_I64, I64_EXTEND16_S_I64_S },
10145 { I64_EXTEND32_S_I64, I64_EXTEND32_S_I64_S },
10146 { I64_EXTEND8_S_I64, I64_EXTEND8_S_I64_S },
10147 { I64_EXTEND_S_I32, I64_EXTEND_S_I32_S },
10148 { I64_EXTEND_U_I32, I64_EXTEND_U_I32_S },
10149 { I64_MUL_WIDE_S, I64_MUL_WIDE_S_S },
10150 { I64_MUL_WIDE_U, I64_MUL_WIDE_U_S },
10151 { I64_REINTERPRET_F64, I64_REINTERPRET_F64_S },
10152 { I64_SUB128, I64_SUB128_S },
10153 { I64_TRUNC_S_F32, I64_TRUNC_S_F32_S },
10154 { I64_TRUNC_S_F64, I64_TRUNC_S_F64_S },
10155 { I64_TRUNC_S_SAT_F32, I64_TRUNC_S_SAT_F32_S },
10156 { I64_TRUNC_S_SAT_F64, I64_TRUNC_S_SAT_F64_S },
10157 { I64_TRUNC_U_F32, I64_TRUNC_U_F32_S },
10158 { I64_TRUNC_U_F64, I64_TRUNC_U_F64_S },
10159 { I64_TRUNC_U_SAT_F32, I64_TRUNC_U_SAT_F32_S },
10160 { I64_TRUNC_U_SAT_F64, I64_TRUNC_U_SAT_F64_S },
10161 { IF, IF_S },
10162 { LANESELECT_I16x8, LANESELECT_I16x8_S },
10163 { LANESELECT_I32x4, LANESELECT_I32x4_S },
10164 { LANESELECT_I64x2, LANESELECT_I64x2_S },
10165 { LANESELECT_I8x16, LANESELECT_I8x16_S },
10166 { LE_F16x8, LE_F16x8_S },
10167 { LE_F32, LE_F32_S },
10168 { LE_F32x4, LE_F32x4_S },
10169 { LE_F64, LE_F64_S },
10170 { LE_F64x2, LE_F64x2_S },
10171 { LE_S_I16x8, LE_S_I16x8_S },
10172 { LE_S_I32, LE_S_I32_S },
10173 { LE_S_I32x4, LE_S_I32x4_S },
10174 { LE_S_I64, LE_S_I64_S },
10175 { LE_S_I64x2, LE_S_I64x2_S },
10176 { LE_S_I8x16, LE_S_I8x16_S },
10177 { LE_U_I16x8, LE_U_I16x8_S },
10178 { LE_U_I32, LE_U_I32_S },
10179 { LE_U_I32x4, LE_U_I32x4_S },
10180 { LE_U_I64, LE_U_I64_S },
10181 { LE_U_I8x16, LE_U_I8x16_S },
10182 { LOAD16_SPLAT_A32, LOAD16_SPLAT_A32_S },
10183 { LOAD16_SPLAT_A64, LOAD16_SPLAT_A64_S },
10184 { LOAD16_S_I32_A32, LOAD16_S_I32_A32_S },
10185 { LOAD16_S_I32_A64, LOAD16_S_I32_A64_S },
10186 { LOAD16_S_I64_A32, LOAD16_S_I64_A32_S },
10187 { LOAD16_S_I64_A64, LOAD16_S_I64_A64_S },
10188 { LOAD16_U_I32_A32, LOAD16_U_I32_A32_S },
10189 { LOAD16_U_I32_A64, LOAD16_U_I32_A64_S },
10190 { LOAD16_U_I64_A32, LOAD16_U_I64_A32_S },
10191 { LOAD16_U_I64_A64, LOAD16_U_I64_A64_S },
10192 { LOAD32_SPLAT_A32, LOAD32_SPLAT_A32_S },
10193 { LOAD32_SPLAT_A64, LOAD32_SPLAT_A64_S },
10194 { LOAD32_S_I64_A32, LOAD32_S_I64_A32_S },
10195 { LOAD32_S_I64_A64, LOAD32_S_I64_A64_S },
10196 { LOAD32_U_I64_A32, LOAD32_U_I64_A32_S },
10197 { LOAD32_U_I64_A64, LOAD32_U_I64_A64_S },
10198 { LOAD64_SPLAT_A32, LOAD64_SPLAT_A32_S },
10199 { LOAD64_SPLAT_A64, LOAD64_SPLAT_A64_S },
10200 { LOAD8_SPLAT_A32, LOAD8_SPLAT_A32_S },
10201 { LOAD8_SPLAT_A64, LOAD8_SPLAT_A64_S },
10202 { LOAD8_S_I32_A32, LOAD8_S_I32_A32_S },
10203 { LOAD8_S_I32_A64, LOAD8_S_I32_A64_S },
10204 { LOAD8_S_I64_A32, LOAD8_S_I64_A32_S },
10205 { LOAD8_S_I64_A64, LOAD8_S_I64_A64_S },
10206 { LOAD8_U_I32_A32, LOAD8_U_I32_A32_S },
10207 { LOAD8_U_I32_A64, LOAD8_U_I32_A64_S },
10208 { LOAD8_U_I64_A32, LOAD8_U_I64_A32_S },
10209 { LOAD8_U_I64_A64, LOAD8_U_I64_A64_S },
10210 { LOAD_EXTEND_S_I16x8_A32, LOAD_EXTEND_S_I16x8_A32_S },
10211 { LOAD_EXTEND_S_I16x8_A64, LOAD_EXTEND_S_I16x8_A64_S },
10212 { LOAD_EXTEND_S_I32x4_A32, LOAD_EXTEND_S_I32x4_A32_S },
10213 { LOAD_EXTEND_S_I32x4_A64, LOAD_EXTEND_S_I32x4_A64_S },
10214 { LOAD_EXTEND_S_I64x2_A32, LOAD_EXTEND_S_I64x2_A32_S },
10215 { LOAD_EXTEND_S_I64x2_A64, LOAD_EXTEND_S_I64x2_A64_S },
10216 { LOAD_EXTEND_U_I16x8_A32, LOAD_EXTEND_U_I16x8_A32_S },
10217 { LOAD_EXTEND_U_I16x8_A64, LOAD_EXTEND_U_I16x8_A64_S },
10218 { LOAD_EXTEND_U_I32x4_A32, LOAD_EXTEND_U_I32x4_A32_S },
10219 { LOAD_EXTEND_U_I32x4_A64, LOAD_EXTEND_U_I32x4_A64_S },
10220 { LOAD_EXTEND_U_I64x2_A32, LOAD_EXTEND_U_I64x2_A32_S },
10221 { LOAD_EXTEND_U_I64x2_A64, LOAD_EXTEND_U_I64x2_A64_S },
10222 { LOAD_F16_F32_A32, LOAD_F16_F32_A32_S },
10223 { LOAD_F16_F32_A64, LOAD_F16_F32_A64_S },
10224 { LOAD_F32_A32, LOAD_F32_A32_S },
10225 { LOAD_F32_A64, LOAD_F32_A64_S },
10226 { LOAD_F64_A32, LOAD_F64_A32_S },
10227 { LOAD_F64_A64, LOAD_F64_A64_S },
10228 { LOAD_I32_A32, LOAD_I32_A32_S },
10229 { LOAD_I32_A64, LOAD_I32_A64_S },
10230 { LOAD_I64_A32, LOAD_I64_A32_S },
10231 { LOAD_I64_A64, LOAD_I64_A64_S },
10232 { LOAD_LANE_16_A32, LOAD_LANE_16_A32_S },
10233 { LOAD_LANE_16_A64, LOAD_LANE_16_A64_S },
10234 { LOAD_LANE_32_A32, LOAD_LANE_32_A32_S },
10235 { LOAD_LANE_32_A64, LOAD_LANE_32_A64_S },
10236 { LOAD_LANE_64_A32, LOAD_LANE_64_A32_S },
10237 { LOAD_LANE_64_A64, LOAD_LANE_64_A64_S },
10238 { LOAD_LANE_8_A32, LOAD_LANE_8_A32_S },
10239 { LOAD_LANE_8_A64, LOAD_LANE_8_A64_S },
10240 { LOAD_V128_A32, LOAD_V128_A32_S },
10241 { LOAD_V128_A64, LOAD_V128_A64_S },
10242 { LOAD_ZERO_32_A32, LOAD_ZERO_32_A32_S },
10243 { LOAD_ZERO_32_A64, LOAD_ZERO_32_A64_S },
10244 { LOAD_ZERO_64_A32, LOAD_ZERO_64_A32_S },
10245 { LOAD_ZERO_64_A64, LOAD_ZERO_64_A64_S },
10246 { LOCAL_GET_EXNREF, LOCAL_GET_EXNREF_S },
10247 { LOCAL_GET_EXTERNREF, LOCAL_GET_EXTERNREF_S },
10248 { LOCAL_GET_F32, LOCAL_GET_F32_S },
10249 { LOCAL_GET_F64, LOCAL_GET_F64_S },
10250 { LOCAL_GET_FUNCREF, LOCAL_GET_FUNCREF_S },
10251 { LOCAL_GET_I32, LOCAL_GET_I32_S },
10252 { LOCAL_GET_I64, LOCAL_GET_I64_S },
10253 { LOCAL_GET_V128, LOCAL_GET_V128_S },
10254 { LOCAL_SET_EXNREF, LOCAL_SET_EXNREF_S },
10255 { LOCAL_SET_EXTERNREF, LOCAL_SET_EXTERNREF_S },
10256 { LOCAL_SET_F32, LOCAL_SET_F32_S },
10257 { LOCAL_SET_F64, LOCAL_SET_F64_S },
10258 { LOCAL_SET_FUNCREF, LOCAL_SET_FUNCREF_S },
10259 { LOCAL_SET_I32, LOCAL_SET_I32_S },
10260 { LOCAL_SET_I64, LOCAL_SET_I64_S },
10261 { LOCAL_SET_V128, LOCAL_SET_V128_S },
10262 { LOCAL_TEE_EXNREF, LOCAL_TEE_EXNREF_S },
10263 { LOCAL_TEE_EXTERNREF, LOCAL_TEE_EXTERNREF_S },
10264 { LOCAL_TEE_F32, LOCAL_TEE_F32_S },
10265 { LOCAL_TEE_F64, LOCAL_TEE_F64_S },
10266 { LOCAL_TEE_FUNCREF, LOCAL_TEE_FUNCREF_S },
10267 { LOCAL_TEE_I32, LOCAL_TEE_I32_S },
10268 { LOCAL_TEE_I64, LOCAL_TEE_I64_S },
10269 { LOCAL_TEE_V128, LOCAL_TEE_V128_S },
10270 { LOOP, LOOP_S },
10271 { LT_F16x8, LT_F16x8_S },
10272 { LT_F32, LT_F32_S },
10273 { LT_F32x4, LT_F32x4_S },
10274 { LT_F64, LT_F64_S },
10275 { LT_F64x2, LT_F64x2_S },
10276 { LT_S_I16x8, LT_S_I16x8_S },
10277 { LT_S_I32, LT_S_I32_S },
10278 { LT_S_I32x4, LT_S_I32x4_S },
10279 { LT_S_I64, LT_S_I64_S },
10280 { LT_S_I64x2, LT_S_I64x2_S },
10281 { LT_S_I8x16, LT_S_I8x16_S },
10282 { LT_U_I16x8, LT_U_I16x8_S },
10283 { LT_U_I32, LT_U_I32_S },
10284 { LT_U_I32x4, LT_U_I32x4_S },
10285 { LT_U_I64, LT_U_I64_S },
10286 { LT_U_I8x16, LT_U_I8x16_S },
10287 { MADD_F16x8, MADD_F16x8_S },
10288 { MADD_F32x4, MADD_F32x4_S },
10289 { MADD_F64x2, MADD_F64x2_S },
10290 { MAX_F16x8, MAX_F16x8_S },
10291 { MAX_F32, MAX_F32_S },
10292 { MAX_F32x4, MAX_F32x4_S },
10293 { MAX_F64, MAX_F64_S },
10294 { MAX_F64x2, MAX_F64x2_S },
10295 { MAX_S_I16x8, MAX_S_I16x8_S },
10296 { MAX_S_I32x4, MAX_S_I32x4_S },
10297 { MAX_S_I8x16, MAX_S_I8x16_S },
10298 { MAX_U_I16x8, MAX_U_I16x8_S },
10299 { MAX_U_I32x4, MAX_U_I32x4_S },
10300 { MAX_U_I8x16, MAX_U_I8x16_S },
10301 { MEMCPY_A32, MEMCPY_A32_S },
10302 { MEMCPY_A64, MEMCPY_A64_S },
10303 { MEMORY_ATOMIC_NOTIFY_A32, MEMORY_ATOMIC_NOTIFY_A32_S },
10304 { MEMORY_ATOMIC_NOTIFY_A64, MEMORY_ATOMIC_NOTIFY_A64_S },
10305 { MEMORY_ATOMIC_WAIT32_A32, MEMORY_ATOMIC_WAIT32_A32_S },
10306 { MEMORY_ATOMIC_WAIT32_A64, MEMORY_ATOMIC_WAIT32_A64_S },
10307 { MEMORY_ATOMIC_WAIT64_A32, MEMORY_ATOMIC_WAIT64_A32_S },
10308 { MEMORY_ATOMIC_WAIT64_A64, MEMORY_ATOMIC_WAIT64_A64_S },
10309 { MEMORY_COPY_A32, MEMORY_COPY_A32_S },
10310 { MEMORY_COPY_A64, MEMORY_COPY_A64_S },
10311 { MEMORY_FILL_A32, MEMORY_FILL_A32_S },
10312 { MEMORY_FILL_A64, MEMORY_FILL_A64_S },
10313 { MEMORY_INIT_A32, MEMORY_INIT_A32_S },
10314 { MEMORY_INIT_A64, MEMORY_INIT_A64_S },
10315 { MEMSET_A32, MEMSET_A32_S },
10316 { MEMSET_A64, MEMSET_A64_S },
10317 { MIN_F16x8, MIN_F16x8_S },
10318 { MIN_F32, MIN_F32_S },
10319 { MIN_F32x4, MIN_F32x4_S },
10320 { MIN_F64, MIN_F64_S },
10321 { MIN_F64x2, MIN_F64x2_S },
10322 { MIN_S_I16x8, MIN_S_I16x8_S },
10323 { MIN_S_I32x4, MIN_S_I32x4_S },
10324 { MIN_S_I8x16, MIN_S_I8x16_S },
10325 { MIN_U_I16x8, MIN_U_I16x8_S },
10326 { MIN_U_I32x4, MIN_U_I32x4_S },
10327 { MIN_U_I8x16, MIN_U_I8x16_S },
10328 { MUL_F16x8, MUL_F16x8_S },
10329 { MUL_F32, MUL_F32_S },
10330 { MUL_F32x4, MUL_F32x4_S },
10331 { MUL_F64, MUL_F64_S },
10332 { MUL_F64x2, MUL_F64x2_S },
10333 { MUL_I16x8, MUL_I16x8_S },
10334 { MUL_I32, MUL_I32_S },
10335 { MUL_I32x4, MUL_I32x4_S },
10336 { MUL_I64, MUL_I64_S },
10337 { MUL_I64x2, MUL_I64x2_S },
10338 { NARROW_S_I16x8, NARROW_S_I16x8_S },
10339 { NARROW_S_I8x16, NARROW_S_I8x16_S },
10340 { NARROW_U_I16x8, NARROW_U_I16x8_S },
10341 { NARROW_U_I8x16, NARROW_U_I8x16_S },
10342 { NEAREST_F16x8, NEAREST_F16x8_S },
10343 { NEAREST_F32, NEAREST_F32_S },
10344 { NEAREST_F32x4, NEAREST_F32x4_S },
10345 { NEAREST_F64, NEAREST_F64_S },
10346 { NEAREST_F64x2, NEAREST_F64x2_S },
10347 { NEG_F16x8, NEG_F16x8_S },
10348 { NEG_F32, NEG_F32_S },
10349 { NEG_F32x4, NEG_F32x4_S },
10350 { NEG_F64, NEG_F64_S },
10351 { NEG_F64x2, NEG_F64x2_S },
10352 { NEG_I16x8, NEG_I16x8_S },
10353 { NEG_I32x4, NEG_I32x4_S },
10354 { NEG_I64x2, NEG_I64x2_S },
10355 { NEG_I8x16, NEG_I8x16_S },
10356 { NE_F16x8, NE_F16x8_S },
10357 { NE_F32, NE_F32_S },
10358 { NE_F32x4, NE_F32x4_S },
10359 { NE_F64, NE_F64_S },
10360 { NE_F64x2, NE_F64x2_S },
10361 { NE_I16x8, NE_I16x8_S },
10362 { NE_I32, NE_I32_S },
10363 { NE_I32x4, NE_I32x4_S },
10364 { NE_I64, NE_I64_S },
10365 { NE_I64x2, NE_I64x2_S },
10366 { NE_I8x16, NE_I8x16_S },
10367 { NMADD_F16x8, NMADD_F16x8_S },
10368 { NMADD_F32x4, NMADD_F32x4_S },
10369 { NMADD_F64x2, NMADD_F64x2_S },
10370 { NOP, NOP_S },
10371 { NOT, NOT_S },
10372 { OR, OR_S },
10373 { OR_I32, OR_I32_S },
10374 { OR_I64, OR_I64_S },
10375 { PMAX_F16x8, PMAX_F16x8_S },
10376 { PMAX_F32x4, PMAX_F32x4_S },
10377 { PMAX_F64x2, PMAX_F64x2_S },
10378 { PMIN_F16x8, PMIN_F16x8_S },
10379 { PMIN_F32x4, PMIN_F32x4_S },
10380 { PMIN_F64x2, PMIN_F64x2_S },
10381 { POPCNT_I32, POPCNT_I32_S },
10382 { POPCNT_I64, POPCNT_I64_S },
10383 { POPCNT_I8x16, POPCNT_I8x16_S },
10384 { Q15MULR_SAT_S_I16x8, Q15MULR_SAT_S_I16x8_S },
10385 { REF_CAST_FUNCREF, REF_CAST_FUNCREF_S },
10386 { REF_FUNC, REF_FUNC_S },
10387 { REF_IS_NULL_EXNREF, REF_IS_NULL_EXNREF_S },
10388 { REF_IS_NULL_EXTERNREF, REF_IS_NULL_EXTERNREF_S },
10389 { REF_IS_NULL_FUNCREF, REF_IS_NULL_FUNCREF_S },
10390 { REF_NULL_EXNREF, REF_NULL_EXNREF_S },
10391 { REF_NULL_EXTERNREF, REF_NULL_EXTERNREF_S },
10392 { REF_NULL_FUNCREF, REF_NULL_FUNCREF_S },
10393 { REF_TEST_FUNCREF, REF_TEST_FUNCREF_S },
10394 { RELAXED_DOT, RELAXED_DOT_S },
10395 { RELAXED_DOT_ADD, RELAXED_DOT_ADD_S },
10396 { RELAXED_DOT_BFLOAT, RELAXED_DOT_BFLOAT_S },
10397 { RELAXED_Q15MULR_S_I16x8, RELAXED_Q15MULR_S_I16x8_S },
10398 { RELAXED_SWIZZLE, RELAXED_SWIZZLE_S },
10399 { REM_S_I32, REM_S_I32_S },
10400 { REM_S_I64, REM_S_I64_S },
10401 { REM_U_I32, REM_U_I32_S },
10402 { REM_U_I64, REM_U_I64_S },
10403 { REPLACE_LANE_F16x8, REPLACE_LANE_F16x8_S },
10404 { REPLACE_LANE_F32x4, REPLACE_LANE_F32x4_S },
10405 { REPLACE_LANE_F64x2, REPLACE_LANE_F64x2_S },
10406 { REPLACE_LANE_I16x8, REPLACE_LANE_I16x8_S },
10407 { REPLACE_LANE_I32x4, REPLACE_LANE_I32x4_S },
10408 { REPLACE_LANE_I64x2, REPLACE_LANE_I64x2_S },
10409 { REPLACE_LANE_I8x16, REPLACE_LANE_I8x16_S },
10410 { RETHROW, RETHROW_S },
10411 { RETURN, RETURN_S },
10412 { RET_CALL, RET_CALL_S },
10413 { RET_CALL_INDIRECT, RET_CALL_INDIRECT_S },
10414 { RET_CALL_REF, RET_CALL_REF_S },
10415 { ROTL_I32, ROTL_I32_S },
10416 { ROTL_I64, ROTL_I64_S },
10417 { ROTR_I32, ROTR_I32_S },
10418 { ROTR_I64, ROTR_I64_S },
10419 { SELECT_EXNREF, SELECT_EXNREF_S },
10420 { SELECT_EXTERNREF, SELECT_EXTERNREF_S },
10421 { SELECT_F32, SELECT_F32_S },
10422 { SELECT_F64, SELECT_F64_S },
10423 { SELECT_FUNCREF, SELECT_FUNCREF_S },
10424 { SELECT_I32, SELECT_I32_S },
10425 { SELECT_I64, SELECT_I64_S },
10426 { SELECT_T, SELECT_T_S },
10427 { SELECT_V128, SELECT_V128_S },
10428 { SHL_I16x8, SHL_I16x8_S },
10429 { SHL_I32, SHL_I32_S },
10430 { SHL_I32x4, SHL_I32x4_S },
10431 { SHL_I64, SHL_I64_S },
10432 { SHL_I64x2, SHL_I64x2_S },
10433 { SHL_I8x16, SHL_I8x16_S },
10434 { SHR_S_I16x8, SHR_S_I16x8_S },
10435 { SHR_S_I32, SHR_S_I32_S },
10436 { SHR_S_I32x4, SHR_S_I32x4_S },
10437 { SHR_S_I64, SHR_S_I64_S },
10438 { SHR_S_I64x2, SHR_S_I64x2_S },
10439 { SHR_S_I8x16, SHR_S_I8x16_S },
10440 { SHR_U_I16x8, SHR_U_I16x8_S },
10441 { SHR_U_I32, SHR_U_I32_S },
10442 { SHR_U_I32x4, SHR_U_I32x4_S },
10443 { SHR_U_I64, SHR_U_I64_S },
10444 { SHR_U_I64x2, SHR_U_I64x2_S },
10445 { SHR_U_I8x16, SHR_U_I8x16_S },
10446 { SHUFFLE, SHUFFLE_S },
10447 { SIMD_RELAXED_FMAX_F32x4, SIMD_RELAXED_FMAX_F32x4_S },
10448 { SIMD_RELAXED_FMAX_F64x2, SIMD_RELAXED_FMAX_F64x2_S },
10449 { SIMD_RELAXED_FMIN_F32x4, SIMD_RELAXED_FMIN_F32x4_S },
10450 { SIMD_RELAXED_FMIN_F64x2, SIMD_RELAXED_FMIN_F64x2_S },
10451 { SPLAT_F16x8, SPLAT_F16x8_S },
10452 { SPLAT_F32x4, SPLAT_F32x4_S },
10453 { SPLAT_F64x2, SPLAT_F64x2_S },
10454 { SPLAT_I16x8, SPLAT_I16x8_S },
10455 { SPLAT_I32x4, SPLAT_I32x4_S },
10456 { SPLAT_I64x2, SPLAT_I64x2_S },
10457 { SPLAT_I8x16, SPLAT_I8x16_S },
10458 { SQRT_F16x8, SQRT_F16x8_S },
10459 { SQRT_F32, SQRT_F32_S },
10460 { SQRT_F32x4, SQRT_F32x4_S },
10461 { SQRT_F64, SQRT_F64_S },
10462 { SQRT_F64x2, SQRT_F64x2_S },
10463 { STORE16_I32_A32, STORE16_I32_A32_S },
10464 { STORE16_I32_A64, STORE16_I32_A64_S },
10465 { STORE16_I64_A32, STORE16_I64_A32_S },
10466 { STORE16_I64_A64, STORE16_I64_A64_S },
10467 { STORE32_I64_A32, STORE32_I64_A32_S },
10468 { STORE32_I64_A64, STORE32_I64_A64_S },
10469 { STORE8_I32_A32, STORE8_I32_A32_S },
10470 { STORE8_I32_A64, STORE8_I32_A64_S },
10471 { STORE8_I64_A32, STORE8_I64_A32_S },
10472 { STORE8_I64_A64, STORE8_I64_A64_S },
10473 { STORE_F16_F32_A32, STORE_F16_F32_A32_S },
10474 { STORE_F16_F32_A64, STORE_F16_F32_A64_S },
10475 { STORE_F32_A32, STORE_F32_A32_S },
10476 { STORE_F32_A64, STORE_F32_A64_S },
10477 { STORE_F64_A32, STORE_F64_A32_S },
10478 { STORE_F64_A64, STORE_F64_A64_S },
10479 { STORE_I32_A32, STORE_I32_A32_S },
10480 { STORE_I32_A64, STORE_I32_A64_S },
10481 { STORE_I64_A32, STORE_I64_A32_S },
10482 { STORE_I64_A64, STORE_I64_A64_S },
10483 { STORE_LANE_I16x8_A32, STORE_LANE_I16x8_A32_S },
10484 { STORE_LANE_I16x8_A64, STORE_LANE_I16x8_A64_S },
10485 { STORE_LANE_I32x4_A32, STORE_LANE_I32x4_A32_S },
10486 { STORE_LANE_I32x4_A64, STORE_LANE_I32x4_A64_S },
10487 { STORE_LANE_I64x2_A32, STORE_LANE_I64x2_A32_S },
10488 { STORE_LANE_I64x2_A64, STORE_LANE_I64x2_A64_S },
10489 { STORE_LANE_I8x16_A32, STORE_LANE_I8x16_A32_S },
10490 { STORE_LANE_I8x16_A64, STORE_LANE_I8x16_A64_S },
10491 { STORE_V128_A32, STORE_V128_A32_S },
10492 { STORE_V128_A64, STORE_V128_A64_S },
10493 { SUB_F16x8, SUB_F16x8_S },
10494 { SUB_F32, SUB_F32_S },
10495 { SUB_F32x4, SUB_F32x4_S },
10496 { SUB_F64, SUB_F64_S },
10497 { SUB_F64x2, SUB_F64x2_S },
10498 { SUB_I16x8, SUB_I16x8_S },
10499 { SUB_I32, SUB_I32_S },
10500 { SUB_I32x4, SUB_I32x4_S },
10501 { SUB_I64, SUB_I64_S },
10502 { SUB_I64x2, SUB_I64x2_S },
10503 { SUB_I8x16, SUB_I8x16_S },
10504 { SUB_SAT_S_I16x8, SUB_SAT_S_I16x8_S },
10505 { SUB_SAT_S_I8x16, SUB_SAT_S_I8x16_S },
10506 { SUB_SAT_U_I16x8, SUB_SAT_U_I16x8_S },
10507 { SUB_SAT_U_I8x16, SUB_SAT_U_I8x16_S },
10508 { SWIZZLE, SWIZZLE_S },
10509 { TABLE_COPY, TABLE_COPY_S },
10510 { TABLE_FILL_EXNREF, TABLE_FILL_EXNREF_S },
10511 { TABLE_FILL_EXTERNREF, TABLE_FILL_EXTERNREF_S },
10512 { TABLE_FILL_FUNCREF, TABLE_FILL_FUNCREF_S },
10513 { TABLE_GET_EXNREF, TABLE_GET_EXNREF_S },
10514 { TABLE_GET_EXTERNREF, TABLE_GET_EXTERNREF_S },
10515 { TABLE_GET_FUNCREF, TABLE_GET_FUNCREF_S },
10516 { TABLE_GROW_EXNREF, TABLE_GROW_EXNREF_S },
10517 { TABLE_GROW_EXTERNREF, TABLE_GROW_EXTERNREF_S },
10518 { TABLE_GROW_FUNCREF, TABLE_GROW_FUNCREF_S },
10519 { TABLE_SET_EXNREF, TABLE_SET_EXNREF_S },
10520 { TABLE_SET_EXTERNREF, TABLE_SET_EXTERNREF_S },
10521 { TABLE_SET_FUNCREF, TABLE_SET_FUNCREF_S },
10522 { TABLE_SIZE, TABLE_SIZE_S },
10523 { TEE_EXNREF, TEE_EXNREF_S },
10524 { TEE_EXTERNREF, TEE_EXTERNREF_S },
10525 { TEE_F32, TEE_F32_S },
10526 { TEE_F64, TEE_F64_S },
10527 { TEE_FUNCREF, TEE_FUNCREF_S },
10528 { TEE_I32, TEE_I32_S },
10529 { TEE_I64, TEE_I64_S },
10530 { TEE_V128, TEE_V128_S },
10531 { THROW, THROW_S },
10532 { THROW_REF, THROW_REF_S },
10533 { TRUNC_F16x8, TRUNC_F16x8_S },
10534 { TRUNC_F32, TRUNC_F32_S },
10535 { TRUNC_F32x4, TRUNC_F32x4_S },
10536 { TRUNC_F64, TRUNC_F64_S },
10537 { TRUNC_F64x2, TRUNC_F64x2_S },
10538 { TRY, TRY_S },
10539 { TRY_TABLE, TRY_TABLE_S },
10540 { UNREACHABLE, UNREACHABLE_S },
10541 { XOR, XOR_S },
10542 { XOR_I32, XOR_I32_S },
10543 { XOR_I64, XOR_I64_S },
10544 { anonymous_14422MEMORY_GROW_A32, anonymous_14422MEMORY_GROW_A32_S },
10545 { anonymous_14422MEMORY_SIZE_A32, anonymous_14422MEMORY_SIZE_A32_S },
10546 { anonymous_14423MEMORY_GROW_A64, anonymous_14423MEMORY_GROW_A64_S },
10547 { anonymous_14423MEMORY_SIZE_A64, anonymous_14423MEMORY_SIZE_A64_S },
10548 { convert_low_s_F64x2, convert_low_s_F64x2_S },
10549 { convert_low_u_F64x2, convert_low_u_F64x2_S },
10550 { demote_zero_F16x8, demote_zero_F16x8_S },
10551 { demote_zero_F32x4, demote_zero_F32x4_S },
10552 { extadd_pairwise_s_I16x8, extadd_pairwise_s_I16x8_S },
10553 { extadd_pairwise_s_I32x4, extadd_pairwise_s_I32x4_S },
10554 { extadd_pairwise_u_I16x8, extadd_pairwise_u_I16x8_S },
10555 { extadd_pairwise_u_I32x4, extadd_pairwise_u_I32x4_S },
10556 { extend_high_s_I16x8, extend_high_s_I16x8_S },
10557 { extend_high_s_I32x4, extend_high_s_I32x4_S },
10558 { extend_high_s_I64x2, extend_high_s_I64x2_S },
10559 { extend_high_u_I16x8, extend_high_u_I16x8_S },
10560 { extend_high_u_I32x4, extend_high_u_I32x4_S },
10561 { extend_high_u_I64x2, extend_high_u_I64x2_S },
10562 { extend_low_s_I16x8, extend_low_s_I16x8_S },
10563 { extend_low_s_I32x4, extend_low_s_I32x4_S },
10564 { extend_low_s_I64x2, extend_low_s_I64x2_S },
10565 { extend_low_u_I16x8, extend_low_u_I16x8_S },
10566 { extend_low_u_I32x4, extend_low_u_I32x4_S },
10567 { extend_low_u_I64x2, extend_low_u_I64x2_S },
10568 { fp_to_sint_I16x8, fp_to_sint_I16x8_S },
10569 { fp_to_sint_I32x4, fp_to_sint_I32x4_S },
10570 { fp_to_uint_I16x8, fp_to_uint_I16x8_S },
10571 { fp_to_uint_I32x4, fp_to_uint_I32x4_S },
10572 { int_wasm_relaxed_trunc_signed_I32x4, int_wasm_relaxed_trunc_signed_I32x4_S },
10573 { int_wasm_relaxed_trunc_signed_zero_I32x4, int_wasm_relaxed_trunc_signed_zero_I32x4_S },
10574 { int_wasm_relaxed_trunc_unsigned_I32x4, int_wasm_relaxed_trunc_unsigned_I32x4_S },
10575 { int_wasm_relaxed_trunc_unsigned_zero_I32x4, int_wasm_relaxed_trunc_unsigned_zero_I32x4_S },
10576 { promote_low_F32x4, promote_low_F32x4_S },
10577 { promote_low_F64x2, promote_low_F64x2_S },
10578 { sint_to_fp_F16x8, sint_to_fp_F16x8_S },
10579 { sint_to_fp_F32x4, sint_to_fp_F32x4_S },
10580 { trunc_sat_zero_s_I32x4, trunc_sat_zero_s_I32x4_S },
10581 { trunc_sat_zero_u_I32x4, trunc_sat_zero_u_I32x4_S },
10582 { uint_to_fp_F16x8, uint_to_fp_F16x8_S },
10583 { uint_to_fp_F32x4, uint_to_fp_F32x4_S },
10584 }; // End of Table
10585
10586 unsigned mid;
10587 unsigned start = 0;
10588 unsigned end = 823;
10589 while (start < end) {
10590 mid = start + (end - start) / 2;
10591 if (Opcode == Table[mid][0])
10592 break;
10593 if (Opcode < Table[mid][0])
10594 end = mid;
10595 else
10596 start = mid + 1;
10597 }
10598 if (start == end)
10599 return -1; // Instruction doesn't exist in this table.
10600
10601 return Table[mid][1];
10602}
10603
10604// getWasm64Opcode
10605LLVM_READONLY
10606int32_t getWasm64Opcode(uint32_t Opcode) {
10607 using namespace WebAssembly;
10608 static constexpr uint32_t Table[][2] = {
10609 { ATOMIC_LOAD16_U_I32_A32, ATOMIC_LOAD16_U_I32_A64 },
10610 { ATOMIC_LOAD16_U_I32_A32_S, ATOMIC_LOAD16_U_I32_A64_S },
10611 { ATOMIC_LOAD16_U_I64_A32, ATOMIC_LOAD16_U_I64_A64 },
10612 { ATOMIC_LOAD16_U_I64_A32_S, ATOMIC_LOAD16_U_I64_A64_S },
10613 { ATOMIC_LOAD32_U_I64_A32, ATOMIC_LOAD32_U_I64_A64 },
10614 { ATOMIC_LOAD32_U_I64_A32_S, ATOMIC_LOAD32_U_I64_A64_S },
10615 { ATOMIC_LOAD8_U_I32_A32, ATOMIC_LOAD8_U_I32_A64 },
10616 { ATOMIC_LOAD8_U_I32_A32_S, ATOMIC_LOAD8_U_I32_A64_S },
10617 { ATOMIC_LOAD8_U_I64_A32, ATOMIC_LOAD8_U_I64_A64 },
10618 { ATOMIC_LOAD8_U_I64_A32_S, ATOMIC_LOAD8_U_I64_A64_S },
10619 { ATOMIC_LOAD_I32_A32, ATOMIC_LOAD_I32_A64 },
10620 { ATOMIC_LOAD_I32_A32_S, ATOMIC_LOAD_I32_A64_S },
10621 { ATOMIC_LOAD_I64_A32, ATOMIC_LOAD_I64_A64 },
10622 { ATOMIC_LOAD_I64_A32_S, ATOMIC_LOAD_I64_A64_S },
10623 { ATOMIC_RMW16_U_ADD_I32_A32, ATOMIC_RMW16_U_ADD_I32_A64 },
10624 { ATOMIC_RMW16_U_ADD_I32_A32_S, ATOMIC_RMW16_U_ADD_I32_A64_S },
10625 { ATOMIC_RMW16_U_ADD_I64_A32, ATOMIC_RMW16_U_ADD_I64_A64 },
10626 { ATOMIC_RMW16_U_ADD_I64_A32_S, ATOMIC_RMW16_U_ADD_I64_A64_S },
10627 { ATOMIC_RMW16_U_AND_I32_A32, ATOMIC_RMW16_U_AND_I32_A64 },
10628 { ATOMIC_RMW16_U_AND_I32_A32_S, ATOMIC_RMW16_U_AND_I32_A64_S },
10629 { ATOMIC_RMW16_U_AND_I64_A32, ATOMIC_RMW16_U_AND_I64_A64 },
10630 { ATOMIC_RMW16_U_AND_I64_A32_S, ATOMIC_RMW16_U_AND_I64_A64_S },
10631 { ATOMIC_RMW16_U_CMPXCHG_I32_A32, ATOMIC_RMW16_U_CMPXCHG_I32_A64 },
10632 { ATOMIC_RMW16_U_CMPXCHG_I32_A32_S, ATOMIC_RMW16_U_CMPXCHG_I32_A64_S },
10633 { ATOMIC_RMW16_U_CMPXCHG_I64_A32, ATOMIC_RMW16_U_CMPXCHG_I64_A64 },
10634 { ATOMIC_RMW16_U_CMPXCHG_I64_A32_S, ATOMIC_RMW16_U_CMPXCHG_I64_A64_S },
10635 { ATOMIC_RMW16_U_OR_I32_A32, ATOMIC_RMW16_U_OR_I32_A64 },
10636 { ATOMIC_RMW16_U_OR_I32_A32_S, ATOMIC_RMW16_U_OR_I32_A64_S },
10637 { ATOMIC_RMW16_U_OR_I64_A32, ATOMIC_RMW16_U_OR_I64_A64 },
10638 { ATOMIC_RMW16_U_OR_I64_A32_S, ATOMIC_RMW16_U_OR_I64_A64_S },
10639 { ATOMIC_RMW16_U_SUB_I32_A32, ATOMIC_RMW16_U_SUB_I32_A64 },
10640 { ATOMIC_RMW16_U_SUB_I32_A32_S, ATOMIC_RMW16_U_SUB_I32_A64_S },
10641 { ATOMIC_RMW16_U_SUB_I64_A32, ATOMIC_RMW16_U_SUB_I64_A64 },
10642 { ATOMIC_RMW16_U_SUB_I64_A32_S, ATOMIC_RMW16_U_SUB_I64_A64_S },
10643 { ATOMIC_RMW16_U_XCHG_I32_A32, ATOMIC_RMW16_U_XCHG_I32_A64 },
10644 { ATOMIC_RMW16_U_XCHG_I32_A32_S, ATOMIC_RMW16_U_XCHG_I32_A64_S },
10645 { ATOMIC_RMW16_U_XCHG_I64_A32, ATOMIC_RMW16_U_XCHG_I64_A64 },
10646 { ATOMIC_RMW16_U_XCHG_I64_A32_S, ATOMIC_RMW16_U_XCHG_I64_A64_S },
10647 { ATOMIC_RMW16_U_XOR_I32_A32, ATOMIC_RMW16_U_XOR_I32_A64 },
10648 { ATOMIC_RMW16_U_XOR_I32_A32_S, ATOMIC_RMW16_U_XOR_I32_A64_S },
10649 { ATOMIC_RMW16_U_XOR_I64_A32, ATOMIC_RMW16_U_XOR_I64_A64 },
10650 { ATOMIC_RMW16_U_XOR_I64_A32_S, ATOMIC_RMW16_U_XOR_I64_A64_S },
10651 { ATOMIC_RMW32_U_ADD_I64_A32, ATOMIC_RMW32_U_ADD_I64_A64 },
10652 { ATOMIC_RMW32_U_ADD_I64_A32_S, ATOMIC_RMW32_U_ADD_I64_A64_S },
10653 { ATOMIC_RMW32_U_AND_I64_A32, ATOMIC_RMW32_U_AND_I64_A64 },
10654 { ATOMIC_RMW32_U_AND_I64_A32_S, ATOMIC_RMW32_U_AND_I64_A64_S },
10655 { ATOMIC_RMW32_U_CMPXCHG_I64_A32, ATOMIC_RMW32_U_CMPXCHG_I64_A64 },
10656 { ATOMIC_RMW32_U_CMPXCHG_I64_A32_S, ATOMIC_RMW32_U_CMPXCHG_I64_A64_S },
10657 { ATOMIC_RMW32_U_OR_I64_A32, ATOMIC_RMW32_U_OR_I64_A64 },
10658 { ATOMIC_RMW32_U_OR_I64_A32_S, ATOMIC_RMW32_U_OR_I64_A64_S },
10659 { ATOMIC_RMW32_U_SUB_I64_A32, ATOMIC_RMW32_U_SUB_I64_A64 },
10660 { ATOMIC_RMW32_U_SUB_I64_A32_S, ATOMIC_RMW32_U_SUB_I64_A64_S },
10661 { ATOMIC_RMW32_U_XCHG_I64_A32, ATOMIC_RMW32_U_XCHG_I64_A64 },
10662 { ATOMIC_RMW32_U_XCHG_I64_A32_S, ATOMIC_RMW32_U_XCHG_I64_A64_S },
10663 { ATOMIC_RMW32_U_XOR_I64_A32, ATOMIC_RMW32_U_XOR_I64_A64 },
10664 { ATOMIC_RMW32_U_XOR_I64_A32_S, ATOMIC_RMW32_U_XOR_I64_A64_S },
10665 { ATOMIC_RMW8_U_ADD_I32_A32, ATOMIC_RMW8_U_ADD_I32_A64 },
10666 { ATOMIC_RMW8_U_ADD_I32_A32_S, ATOMIC_RMW8_U_ADD_I32_A64_S },
10667 { ATOMIC_RMW8_U_ADD_I64_A32, ATOMIC_RMW8_U_ADD_I64_A64 },
10668 { ATOMIC_RMW8_U_ADD_I64_A32_S, ATOMIC_RMW8_U_ADD_I64_A64_S },
10669 { ATOMIC_RMW8_U_AND_I32_A32, ATOMIC_RMW8_U_AND_I32_A64 },
10670 { ATOMIC_RMW8_U_AND_I32_A32_S, ATOMIC_RMW8_U_AND_I32_A64_S },
10671 { ATOMIC_RMW8_U_AND_I64_A32, ATOMIC_RMW8_U_AND_I64_A64 },
10672 { ATOMIC_RMW8_U_AND_I64_A32_S, ATOMIC_RMW8_U_AND_I64_A64_S },
10673 { ATOMIC_RMW8_U_CMPXCHG_I32_A32, ATOMIC_RMW8_U_CMPXCHG_I32_A64 },
10674 { ATOMIC_RMW8_U_CMPXCHG_I32_A32_S, ATOMIC_RMW8_U_CMPXCHG_I32_A64_S },
10675 { ATOMIC_RMW8_U_CMPXCHG_I64_A32, ATOMIC_RMW8_U_CMPXCHG_I64_A64 },
10676 { ATOMIC_RMW8_U_CMPXCHG_I64_A32_S, ATOMIC_RMW8_U_CMPXCHG_I64_A64_S },
10677 { ATOMIC_RMW8_U_OR_I32_A32, ATOMIC_RMW8_U_OR_I32_A64 },
10678 { ATOMIC_RMW8_U_OR_I32_A32_S, ATOMIC_RMW8_U_OR_I32_A64_S },
10679 { ATOMIC_RMW8_U_OR_I64_A32, ATOMIC_RMW8_U_OR_I64_A64 },
10680 { ATOMIC_RMW8_U_OR_I64_A32_S, ATOMIC_RMW8_U_OR_I64_A64_S },
10681 { ATOMIC_RMW8_U_SUB_I32_A32, ATOMIC_RMW8_U_SUB_I32_A64 },
10682 { ATOMIC_RMW8_U_SUB_I32_A32_S, ATOMIC_RMW8_U_SUB_I32_A64_S },
10683 { ATOMIC_RMW8_U_SUB_I64_A32, ATOMIC_RMW8_U_SUB_I64_A64 },
10684 { ATOMIC_RMW8_U_SUB_I64_A32_S, ATOMIC_RMW8_U_SUB_I64_A64_S },
10685 { ATOMIC_RMW8_U_XCHG_I32_A32, ATOMIC_RMW8_U_XCHG_I32_A64 },
10686 { ATOMIC_RMW8_U_XCHG_I32_A32_S, ATOMIC_RMW8_U_XCHG_I32_A64_S },
10687 { ATOMIC_RMW8_U_XCHG_I64_A32, ATOMIC_RMW8_U_XCHG_I64_A64 },
10688 { ATOMIC_RMW8_U_XCHG_I64_A32_S, ATOMIC_RMW8_U_XCHG_I64_A64_S },
10689 { ATOMIC_RMW8_U_XOR_I32_A32, ATOMIC_RMW8_U_XOR_I32_A64 },
10690 { ATOMIC_RMW8_U_XOR_I32_A32_S, ATOMIC_RMW8_U_XOR_I32_A64_S },
10691 { ATOMIC_RMW8_U_XOR_I64_A32, ATOMIC_RMW8_U_XOR_I64_A64 },
10692 { ATOMIC_RMW8_U_XOR_I64_A32_S, ATOMIC_RMW8_U_XOR_I64_A64_S },
10693 { ATOMIC_RMW_ADD_I32_A32, ATOMIC_RMW_ADD_I32_A64 },
10694 { ATOMIC_RMW_ADD_I32_A32_S, ATOMIC_RMW_ADD_I32_A64_S },
10695 { ATOMIC_RMW_ADD_I64_A32, ATOMIC_RMW_ADD_I64_A64 },
10696 { ATOMIC_RMW_ADD_I64_A32_S, ATOMIC_RMW_ADD_I64_A64_S },
10697 { ATOMIC_RMW_AND_I32_A32, ATOMIC_RMW_AND_I32_A64 },
10698 { ATOMIC_RMW_AND_I32_A32_S, ATOMIC_RMW_AND_I32_A64_S },
10699 { ATOMIC_RMW_AND_I64_A32, ATOMIC_RMW_AND_I64_A64 },
10700 { ATOMIC_RMW_AND_I64_A32_S, ATOMIC_RMW_AND_I64_A64_S },
10701 { ATOMIC_RMW_CMPXCHG_I32_A32, ATOMIC_RMW_CMPXCHG_I32_A64 },
10702 { ATOMIC_RMW_CMPXCHG_I32_A32_S, ATOMIC_RMW_CMPXCHG_I32_A64_S },
10703 { ATOMIC_RMW_CMPXCHG_I64_A32, ATOMIC_RMW_CMPXCHG_I64_A64 },
10704 { ATOMIC_RMW_CMPXCHG_I64_A32_S, ATOMIC_RMW_CMPXCHG_I64_A64_S },
10705 { ATOMIC_RMW_OR_I32_A32, ATOMIC_RMW_OR_I32_A64 },
10706 { ATOMIC_RMW_OR_I32_A32_S, ATOMIC_RMW_OR_I32_A64_S },
10707 { ATOMIC_RMW_OR_I64_A32, ATOMIC_RMW_OR_I64_A64 },
10708 { ATOMIC_RMW_OR_I64_A32_S, ATOMIC_RMW_OR_I64_A64_S },
10709 { ATOMIC_RMW_SUB_I32_A32, ATOMIC_RMW_SUB_I32_A64 },
10710 { ATOMIC_RMW_SUB_I32_A32_S, ATOMIC_RMW_SUB_I32_A64_S },
10711 { ATOMIC_RMW_SUB_I64_A32, ATOMIC_RMW_SUB_I64_A64 },
10712 { ATOMIC_RMW_SUB_I64_A32_S, ATOMIC_RMW_SUB_I64_A64_S },
10713 { ATOMIC_RMW_XCHG_I32_A32, ATOMIC_RMW_XCHG_I32_A64 },
10714 { ATOMIC_RMW_XCHG_I32_A32_S, ATOMIC_RMW_XCHG_I32_A64_S },
10715 { ATOMIC_RMW_XCHG_I64_A32, ATOMIC_RMW_XCHG_I64_A64 },
10716 { ATOMIC_RMW_XCHG_I64_A32_S, ATOMIC_RMW_XCHG_I64_A64_S },
10717 { ATOMIC_RMW_XOR_I32_A32, ATOMIC_RMW_XOR_I32_A64 },
10718 { ATOMIC_RMW_XOR_I32_A32_S, ATOMIC_RMW_XOR_I32_A64_S },
10719 { ATOMIC_RMW_XOR_I64_A32, ATOMIC_RMW_XOR_I64_A64 },
10720 { ATOMIC_RMW_XOR_I64_A32_S, ATOMIC_RMW_XOR_I64_A64_S },
10721 { ATOMIC_STORE16_I32_A32, ATOMIC_STORE16_I32_A64 },
10722 { ATOMIC_STORE16_I32_A32_S, ATOMIC_STORE16_I32_A64_S },
10723 { ATOMIC_STORE16_I64_A32, ATOMIC_STORE16_I64_A64 },
10724 { ATOMIC_STORE16_I64_A32_S, ATOMIC_STORE16_I64_A64_S },
10725 { ATOMIC_STORE32_I64_A32, ATOMIC_STORE32_I64_A64 },
10726 { ATOMIC_STORE32_I64_A32_S, ATOMIC_STORE32_I64_A64_S },
10727 { ATOMIC_STORE8_I32_A32, ATOMIC_STORE8_I32_A64 },
10728 { ATOMIC_STORE8_I32_A32_S, ATOMIC_STORE8_I32_A64_S },
10729 { ATOMIC_STORE8_I64_A32, ATOMIC_STORE8_I64_A64 },
10730 { ATOMIC_STORE8_I64_A32_S, ATOMIC_STORE8_I64_A64_S },
10731 { ATOMIC_STORE_I32_A32, ATOMIC_STORE_I32_A64 },
10732 { ATOMIC_STORE_I32_A32_S, ATOMIC_STORE_I32_A64_S },
10733 { ATOMIC_STORE_I64_A32, ATOMIC_STORE_I64_A64 },
10734 { ATOMIC_STORE_I64_A32_S, ATOMIC_STORE_I64_A64_S },
10735 { LOAD16_S_I32_A32, LOAD16_S_I32_A64 },
10736 { LOAD16_S_I32_A32_S, LOAD16_S_I32_A64_S },
10737 { LOAD16_S_I64_A32, LOAD16_S_I64_A64 },
10738 { LOAD16_S_I64_A32_S, LOAD16_S_I64_A64_S },
10739 { LOAD16_U_I32_A32, LOAD16_U_I32_A64 },
10740 { LOAD16_U_I32_A32_S, LOAD16_U_I32_A64_S },
10741 { LOAD16_U_I64_A32, LOAD16_U_I64_A64 },
10742 { LOAD16_U_I64_A32_S, LOAD16_U_I64_A64_S },
10743 { LOAD32_S_I64_A32, LOAD32_S_I64_A64 },
10744 { LOAD32_S_I64_A32_S, LOAD32_S_I64_A64_S },
10745 { LOAD32_U_I64_A32, LOAD32_U_I64_A64 },
10746 { LOAD32_U_I64_A32_S, LOAD32_U_I64_A64_S },
10747 { LOAD8_S_I32_A32, LOAD8_S_I32_A64 },
10748 { LOAD8_S_I32_A32_S, LOAD8_S_I32_A64_S },
10749 { LOAD8_S_I64_A32, LOAD8_S_I64_A64 },
10750 { LOAD8_S_I64_A32_S, LOAD8_S_I64_A64_S },
10751 { LOAD8_U_I32_A32, LOAD8_U_I32_A64 },
10752 { LOAD8_U_I32_A32_S, LOAD8_U_I32_A64_S },
10753 { LOAD8_U_I64_A32, LOAD8_U_I64_A64 },
10754 { LOAD8_U_I64_A32_S, LOAD8_U_I64_A64_S },
10755 { LOAD_F16_F32_A32, LOAD_F16_F32_A64 },
10756 { LOAD_F16_F32_A32_S, LOAD_F16_F32_A64_S },
10757 { LOAD_F32_A32, LOAD_F32_A64 },
10758 { LOAD_F32_A32_S, LOAD_F32_A64_S },
10759 { LOAD_F64_A32, LOAD_F64_A64 },
10760 { LOAD_F64_A32_S, LOAD_F64_A64_S },
10761 { LOAD_I32_A32, LOAD_I32_A64 },
10762 { LOAD_I32_A32_S, LOAD_I32_A64_S },
10763 { LOAD_I64_A32, LOAD_I64_A64 },
10764 { LOAD_I64_A32_S, LOAD_I64_A64_S },
10765 { MEMORY_ATOMIC_NOTIFY_A32, MEMORY_ATOMIC_NOTIFY_A64 },
10766 { MEMORY_ATOMIC_NOTIFY_A32_S, MEMORY_ATOMIC_NOTIFY_A64_S },
10767 { MEMORY_ATOMIC_WAIT32_A32, MEMORY_ATOMIC_WAIT32_A64 },
10768 { MEMORY_ATOMIC_WAIT32_A32_S, MEMORY_ATOMIC_WAIT32_A64_S },
10769 { MEMORY_ATOMIC_WAIT64_A32, MEMORY_ATOMIC_WAIT64_A64 },
10770 { MEMORY_ATOMIC_WAIT64_A32_S, MEMORY_ATOMIC_WAIT64_A64_S },
10771 { STORE16_I32_A32, STORE16_I32_A64 },
10772 { STORE16_I32_A32_S, STORE16_I32_A64_S },
10773 { STORE16_I64_A32, STORE16_I64_A64 },
10774 { STORE16_I64_A32_S, STORE16_I64_A64_S },
10775 { STORE32_I64_A32, STORE32_I64_A64 },
10776 { STORE32_I64_A32_S, STORE32_I64_A64_S },
10777 { STORE8_I32_A32, STORE8_I32_A64 },
10778 { STORE8_I32_A32_S, STORE8_I32_A64_S },
10779 { STORE8_I64_A32, STORE8_I64_A64 },
10780 { STORE8_I64_A32_S, STORE8_I64_A64_S },
10781 { STORE_F16_F32_A32, STORE_F16_F32_A64 },
10782 { STORE_F16_F32_A32_S, STORE_F16_F32_A64_S },
10783 { STORE_F32_A32, STORE_F32_A64 },
10784 { STORE_F32_A32_S, STORE_F32_A64_S },
10785 { STORE_F64_A32, STORE_F64_A64 },
10786 { STORE_F64_A32_S, STORE_F64_A64_S },
10787 { STORE_I32_A32, STORE_I32_A64 },
10788 { STORE_I32_A32_S, STORE_I32_A64_S },
10789 { STORE_I64_A32, STORE_I64_A64 },
10790 { STORE_I64_A32_S, STORE_I64_A64_S },
10791 }; // End of Table
10792
10793 unsigned mid;
10794 unsigned start = 0;
10795 unsigned end = 182;
10796 while (start < end) {
10797 mid = start + (end - start) / 2;
10798 if (Opcode == Table[mid][0])
10799 break;
10800 if (Opcode < Table[mid][0])
10801 end = mid;
10802 else
10803 start = mid + 1;
10804 }
10805 if (start == end)
10806 return -1; // Instruction doesn't exist in this table.
10807
10808 return Table[mid][1];
10809}
10810
10811
10812} // namespace llvm::WebAssembly
10813
10814#endif // GET_INSTRMAP_INFO
10815
10816