1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11
12namespace llvm::WebAssembly {
13
14 enum {
15 PHI = 0, // Target.td:1301
16 INLINEASM = 1, // Target.td:1307
17 INLINEASM_BR = 2, // Target.td:1313
18 CFI_INSTRUCTION = 3, // Target.td:1322
19 EH_LABEL = 4, // Target.td:1331
20 GC_LABEL = 5, // Target.td:1340
21 ANNOTATION_LABEL = 6, // Target.td:1349
22 KILL = 7, // Target.td:1357
23 EXTRACT_SUBREG = 8, // Target.td:1364
24 INSERT_SUBREG = 9, // Target.td:1370
25 IMPLICIT_DEF = 10, // Target.td:1377
26 INIT_UNDEF = 11, // Target.td:1386
27 SUBREG_TO_REG = 12, // Target.td:1393
28 COPY_TO_REGCLASS = 13, // Target.td:1399
29 DBG_VALUE = 14, // Target.td:1406
30 DBG_VALUE_LIST = 15, // Target.td:1413
31 DBG_INSTR_REF = 16, // Target.td:1420
32 DBG_PHI = 17, // Target.td:1427
33 DBG_LABEL = 18, // Target.td:1434
34 REG_SEQUENCE = 19, // Target.td:1441
35 COPY = 20, // Target.td:1448
36 COPY_LANEMASK = 21, // Target.td:1456
37 BUNDLE = 22, // Target.td:1463
38 LIFETIME_START = 23, // Target.td:1469
39 LIFETIME_END = 24, // Target.td:1476
40 PSEUDO_PROBE = 25, // Target.td:1483
41 ARITH_FENCE = 26, // Target.td:1490
42 STACKMAP = 27, // Target.td:1499
43 FENTRY_CALL = 28, // Target.td:1634
44 PATCHPOINT = 29, // Target.td:1507
45 LOAD_STACK_GUARD = 30, // Target.td:1525
46 PREALLOCATED_SETUP = 31, // Target.td:1533
47 PREALLOCATED_ARG = 32, // Target.td:1539
48 STATEPOINT = 33, // Target.td:1516
49 LOCAL_ESCAPE = 34, // Target.td:1545
50 FAULTING_OP = 35, // Target.td:1554
51 PATCHABLE_OP = 36, // Target.td:1574
52 PATCHABLE_FUNCTION_ENTER = 37, // Target.td:1582
53 PATCHABLE_RET = 38, // Target.td:1589
54 PATCHABLE_FUNCTION_EXIT = 39, // Target.td:1598
55 PATCHABLE_TAIL_CALL = 40, // Target.td:1606
56 PATCHABLE_EVENT_CALL = 41, // Target.td:1614
57 PATCHABLE_TYPED_EVENT_CALL = 42, // Target.td:1624
58 ICALL_BRANCH_FUNNEL = 43, // Target.td:1644
59 FAKE_USE = 44, // Target.td:1564
60 MEMBARRIER = 45, // Target.td:1650
61 JUMP_TABLE_DEBUG_INFO = 46, // Target.td:1658
62 RELOC_NONE = 47, // Target.td:1666
63 CONVERGENCECTRL_ENTRY = 48, // Target.td:1678
64 CONVERGENCECTRL_ANCHOR = 49, // Target.td:1674
65 CONVERGENCECTRL_LOOP = 50, // Target.td:1682
66 CONVERGENCECTRL_GLUE = 51, // Target.td:1686
67 G_ASSERT_SEXT = 52, // GenericOpcodes.td:1867
68 G_ASSERT_ZEXT = 53, // GenericOpcodes.td:1859
69 G_ASSERT_ALIGN = 54, // GenericOpcodes.td:1874
70 G_ADD = 55, // GenericOpcodes.td:300
71 G_SUB = 56, // GenericOpcodes.td:308
72 G_MUL = 57, // GenericOpcodes.td:316
73 G_SDIV = 58, // GenericOpcodes.td:324
74 G_UDIV = 59, // GenericOpcodes.td:332
75 G_SREM = 60, // GenericOpcodes.td:340
76 G_UREM = 61, // GenericOpcodes.td:348
77 G_SDIVREM = 62, // GenericOpcodes.td:356
78 G_UDIVREM = 63, // GenericOpcodes.td:364
79 G_AND = 64, // GenericOpcodes.td:372
80 G_OR = 65, // GenericOpcodes.td:380
81 G_XOR = 66, // GenericOpcodes.td:388
82 G_ABDS = 67, // GenericOpcodes.td:417
83 G_ABDU = 68, // GenericOpcodes.td:425
84 G_UAVGFLOOR = 69, // GenericOpcodes.td:433
85 G_UAVGCEIL = 70, // GenericOpcodes.td:440
86 G_SAVGFLOOR = 71, // GenericOpcodes.td:447
87 G_SAVGCEIL = 72, // GenericOpcodes.td:454
88 G_IMPLICIT_DEF = 73, // GenericOpcodes.td:110
89 G_PHI = 74, // GenericOpcodes.td:116
90 G_FRAME_INDEX = 75, // GenericOpcodes.td:122
91 G_GLOBAL_VALUE = 76, // GenericOpcodes.td:128
92 G_PTRAUTH_GLOBAL_VALUE = 77, // GenericOpcodes.td:134
93 G_CONSTANT_POOL = 78, // GenericOpcodes.td:140
94 G_EXTRACT = 79, // GenericOpcodes.td:1474
95 G_UNMERGE_VALUES = 80, // GenericOpcodes.td:1486
96 G_INSERT = 81, // GenericOpcodes.td:1494
97 G_MERGE_VALUES = 82, // GenericOpcodes.td:1504
98 G_BUILD_VECTOR = 83, // GenericOpcodes.td:1523
99 G_BUILD_VECTOR_TRUNC = 84, // GenericOpcodes.td:1532
100 G_CONCAT_VECTORS = 85, // GenericOpcodes.td:1539
101 G_PTRTOINT = 86, // GenericOpcodes.td:152
102 G_INTTOPTR = 87, // GenericOpcodes.td:146
103 G_BITCAST = 88, // GenericOpcodes.td:158
104 G_FREEZE = 89, // GenericOpcodes.td:277
105 G_CONSTANT_FOLD_BARRIER = 90, // GenericOpcodes.td:1881
106 G_INTRINSIC_FPTRUNC_ROUND = 91, // GenericOpcodes.td:1263
107 G_INTRINSIC_TRUNC = 92, // GenericOpcodes.td:1269
108 G_INTRINSIC_ROUND = 93, // GenericOpcodes.td:1275
109 G_INTRINSIC_LRINT = 94, // GenericOpcodes.td:1281
110 G_INTRINSIC_LLRINT = 95, // GenericOpcodes.td:1287
111 G_INTRINSIC_ROUNDEVEN = 96, // GenericOpcodes.td:1293
112 G_READCYCLECOUNTER = 97, // GenericOpcodes.td:1299
113 G_READSTEADYCOUNTER = 98, // GenericOpcodes.td:1305
114 G_LOAD = 99, // GenericOpcodes.td:1332
115 G_SEXTLOAD = 100, // GenericOpcodes.td:1340
116 G_ZEXTLOAD = 101, // GenericOpcodes.td:1348
117 G_INDEXED_LOAD = 102, // GenericOpcodes.td:1358
118 G_INDEXED_SEXTLOAD = 103, // GenericOpcodes.td:1366
119 G_INDEXED_ZEXTLOAD = 104, // GenericOpcodes.td:1374
120 G_STORE = 105, // GenericOpcodes.td:1382
121 G_INDEXED_STORE = 106, // GenericOpcodes.td:1390
122 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 107, // GenericOpcodes.td:1400
123 G_ATOMIC_CMPXCHG = 108, // GenericOpcodes.td:1410
124 G_ATOMICRMW_XCHG = 109, // GenericOpcodes.td:1428
125 G_ATOMICRMW_ADD = 110, // GenericOpcodes.td:1429
126 G_ATOMICRMW_SUB = 111, // GenericOpcodes.td:1430
127 G_ATOMICRMW_AND = 112, // GenericOpcodes.td:1431
128 G_ATOMICRMW_NAND = 113, // GenericOpcodes.td:1432
129 G_ATOMICRMW_OR = 114, // GenericOpcodes.td:1433
130 G_ATOMICRMW_XOR = 115, // GenericOpcodes.td:1434
131 G_ATOMICRMW_MAX = 116, // GenericOpcodes.td:1435
132 G_ATOMICRMW_MIN = 117, // GenericOpcodes.td:1436
133 G_ATOMICRMW_UMAX = 118, // GenericOpcodes.td:1437
134 G_ATOMICRMW_UMIN = 119, // GenericOpcodes.td:1438
135 G_ATOMICRMW_FADD = 120, // GenericOpcodes.td:1439
136 G_ATOMICRMW_FSUB = 121, // GenericOpcodes.td:1440
137 G_ATOMICRMW_FMAX = 122, // GenericOpcodes.td:1441
138 G_ATOMICRMW_FMIN = 123, // GenericOpcodes.td:1442
139 G_ATOMICRMW_FMAXIMUM = 124, // GenericOpcodes.td:1443
140 G_ATOMICRMW_FMINIMUM = 125, // GenericOpcodes.td:1444
141 G_ATOMICRMW_FMAXIMUMNUM = 126, // GenericOpcodes.td:1445
142 G_ATOMICRMW_FMINIMUMNUM = 127, // GenericOpcodes.td:1446
143 G_ATOMICRMW_UINC_WRAP = 128, // GenericOpcodes.td:1447
144 G_ATOMICRMW_UDEC_WRAP = 129, // GenericOpcodes.td:1448
145 G_ATOMICRMW_USUB_COND = 130, // GenericOpcodes.td:1449
146 G_ATOMICRMW_USUB_SAT = 131, // GenericOpcodes.td:1450
147 G_FENCE = 132, // GenericOpcodes.td:1452
148 G_PREFETCH = 133, // GenericOpcodes.td:1459
149 G_BRCOND = 134, // GenericOpcodes.td:1594
150 G_BRINDIRECT = 135, // GenericOpcodes.td:1603
151 G_INVOKE_REGION_START = 136, // GenericOpcodes.td:1626
152 G_INTRINSIC = 137, // GenericOpcodes.td:1546
153 G_INTRINSIC_W_SIDE_EFFECTS = 138, // GenericOpcodes.td:1553
154 G_INTRINSIC_CONVERGENT = 139, // GenericOpcodes.td:1562
155 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 140, // GenericOpcodes.td:1570
156 G_ANYEXT = 141, // GenericOpcodes.td:44
157 G_TRUNC = 142, // GenericOpcodes.td:83
158 G_TRUNC_SSAT_S = 143, // GenericOpcodes.td:90
159 G_TRUNC_SSAT_U = 144, // GenericOpcodes.td:97
160 G_TRUNC_USAT_U = 145, // GenericOpcodes.td:104
161 G_CONSTANT = 146, // GenericOpcodes.td:165
162 G_FCONSTANT = 147, // GenericOpcodes.td:172
163 G_VASTART = 148, // GenericOpcodes.td:178
164 G_VAARG = 149, // GenericOpcodes.td:185
165 G_SEXT = 150, // GenericOpcodes.td:52
166 G_SEXT_INREG = 151, // GenericOpcodes.td:66
167 G_ZEXT = 152, // GenericOpcodes.td:74
168 G_SHL = 153, // GenericOpcodes.td:396
169 G_LSHR = 154, // GenericOpcodes.td:403
170 G_ASHR = 155, // GenericOpcodes.td:410
171 G_FSHL = 156, // GenericOpcodes.td:462
172 G_FSHR = 157, // GenericOpcodes.td:470
173 G_ROTR = 158, // GenericOpcodes.td:477
174 G_ROTL = 159, // GenericOpcodes.td:484
175 G_ICMP = 160, // GenericOpcodes.td:491
176 G_FCMP = 161, // GenericOpcodes.td:498
177 G_SCMP = 162, // GenericOpcodes.td:505
178 G_UCMP = 163, // GenericOpcodes.td:512
179 G_SELECT = 164, // GenericOpcodes.td:519
180 G_UADDO = 165, // GenericOpcodes.td:584
181 G_UADDE = 166, // GenericOpcodes.td:592
182 G_USUBO = 167, // GenericOpcodes.td:614
183 G_USUBE = 168, // GenericOpcodes.td:620
184 G_SADDO = 169, // GenericOpcodes.td:599
185 G_SADDE = 170, // GenericOpcodes.td:607
186 G_SSUBO = 171, // GenericOpcodes.td:627
187 G_SSUBE = 172, // GenericOpcodes.td:634
188 G_UMULO = 173, // GenericOpcodes.td:641
189 G_SMULO = 174, // GenericOpcodes.td:649
190 G_UMULH = 175, // GenericOpcodes.td:658
191 G_SMULH = 176, // GenericOpcodes.td:667
192 G_UADDSAT = 177, // GenericOpcodes.td:679
193 G_SADDSAT = 178, // GenericOpcodes.td:687
194 G_USUBSAT = 179, // GenericOpcodes.td:695
195 G_SSUBSAT = 180, // GenericOpcodes.td:703
196 G_USHLSAT = 181, // GenericOpcodes.td:711
197 G_SSHLSAT = 182, // GenericOpcodes.td:719
198 G_SMULFIX = 183, // GenericOpcodes.td:731
199 G_UMULFIX = 184, // GenericOpcodes.td:738
200 G_SMULFIXSAT = 185, // GenericOpcodes.td:748
201 G_UMULFIXSAT = 186, // GenericOpcodes.td:755
202 G_SDIVFIX = 187, // GenericOpcodes.td:766
203 G_UDIVFIX = 188, // GenericOpcodes.td:773
204 G_SDIVFIXSAT = 189, // GenericOpcodes.td:783
205 G_UDIVFIXSAT = 190, // GenericOpcodes.td:790
206 G_FADD = 191, // GenericOpcodes.td:963
207 G_FSUB = 192, // GenericOpcodes.td:971
208 G_FMUL = 193, // GenericOpcodes.td:979
209 G_FMA = 194, // GenericOpcodes.td:988
210 G_FMAD = 195, // GenericOpcodes.td:997
211 G_FDIV = 196, // GenericOpcodes.td:1005
212 G_FREM = 197, // GenericOpcodes.td:1012
213 G_FMODF = 198, // GenericOpcodes.td:1019
214 G_FPOW = 199, // GenericOpcodes.td:1026
215 G_FPOWI = 200, // GenericOpcodes.td:1033
216 G_FEXP = 201, // GenericOpcodes.td:1040
217 G_FEXP2 = 202, // GenericOpcodes.td:1047
218 G_FEXP10 = 203, // GenericOpcodes.td:1054
219 G_FLOG = 204, // GenericOpcodes.td:1061
220 G_FLOG2 = 205, // GenericOpcodes.td:1068
221 G_FLOG10 = 206, // GenericOpcodes.td:1075
222 G_FLDEXP = 207, // GenericOpcodes.td:1082
223 G_FFREXP = 208, // GenericOpcodes.td:1089
224 G_FNEG = 209, // GenericOpcodes.td:801
225 G_FPEXT = 210, // GenericOpcodes.td:807
226 G_FPTRUNC = 211, // GenericOpcodes.td:813
227 G_FPTOSI = 212, // GenericOpcodes.td:819
228 G_FPTOUI = 213, // GenericOpcodes.td:825
229 G_SITOFP = 214, // GenericOpcodes.td:831
230 G_UITOFP = 215, // GenericOpcodes.td:837
231 G_FPTOSI_SAT = 216, // GenericOpcodes.td:843
232 G_FPTOUI_SAT = 217, // GenericOpcodes.td:849
233 G_FABS = 218, // GenericOpcodes.td:855
234 G_FCOPYSIGN = 219, // GenericOpcodes.td:861
235 G_IS_FPCLASS = 220, // GenericOpcodes.td:874
236 G_FCANONICALIZE = 221, // GenericOpcodes.td:867
237 G_FMINNUM = 222, // GenericOpcodes.td:887
238 G_FMAXNUM = 223, // GenericOpcodes.td:894
239 G_FMINNUM_IEEE = 224, // GenericOpcodes.td:912
240 G_FMAXNUM_IEEE = 225, // GenericOpcodes.td:919
241 G_FMINIMUM = 226, // GenericOpcodes.td:929
242 G_FMAXIMUM = 227, // GenericOpcodes.td:936
243 G_FMINIMUMNUM = 228, // GenericOpcodes.td:944
244 G_FMAXIMUMNUM = 229, // GenericOpcodes.td:951
245 G_GET_FPENV = 230, // GenericOpcodes.td:1219
246 G_SET_FPENV = 231, // GenericOpcodes.td:1226
247 G_RESET_FPENV = 232, // GenericOpcodes.td:1233
248 G_GET_FPMODE = 233, // GenericOpcodes.td:1240
249 G_SET_FPMODE = 234, // GenericOpcodes.td:1247
250 G_RESET_FPMODE = 235, // GenericOpcodes.td:1254
251 G_GET_ROUNDING = 236, // GenericOpcodes.td:1311
252 G_SET_ROUNDING = 237, // GenericOpcodes.td:1317
253 G_PTR_ADD = 238, // GenericOpcodes.td:526
254 G_PTRMASK = 239, // GenericOpcodes.td:534
255 G_SMIN = 240, // GenericOpcodes.td:541
256 G_SMAX = 241, // GenericOpcodes.td:549
257 G_UMIN = 242, // GenericOpcodes.td:557
258 G_UMAX = 243, // GenericOpcodes.td:565
259 G_ABS = 244, // GenericOpcodes.td:573
260 G_LROUND = 245, // GenericOpcodes.td:283
261 G_LLROUND = 246, // GenericOpcodes.td:289
262 G_BR = 247, // GenericOpcodes.td:1584
263 G_BRJT = 248, // GenericOpcodes.td:1614
264 G_VSCALE = 249, // GenericOpcodes.td:1514
265 G_INSERT_SUBVECTOR = 250, // GenericOpcodes.td:1658
266 G_EXTRACT_SUBVECTOR = 251, // GenericOpcodes.td:1665
267 G_INSERT_VECTOR_ELT = 252, // GenericOpcodes.td:1672
268 G_EXTRACT_VECTOR_ELT = 253, // GenericOpcodes.td:1679
269 G_SHUFFLE_VECTOR = 254, // GenericOpcodes.td:1689
270 G_SPLAT_VECTOR = 255, // GenericOpcodes.td:1696
271 G_STEP_VECTOR = 256, // GenericOpcodes.td:1703
272 G_VECTOR_COMPRESS = 257, // GenericOpcodes.td:1710
273 G_CTTZ = 258, // GenericOpcodes.td:205
274 G_CTTZ_ZERO_UNDEF = 259, // GenericOpcodes.td:211
275 G_CTLZ = 260, // GenericOpcodes.td:193
276 G_CTLZ_ZERO_UNDEF = 261, // GenericOpcodes.td:199
277 G_CTLS = 262, // GenericOpcodes.td:217
278 G_CTPOP = 263, // GenericOpcodes.td:223
279 G_BSWAP = 264, // GenericOpcodes.td:229
280 G_BITREVERSE = 265, // GenericOpcodes.td:235
281 G_FCEIL = 266, // GenericOpcodes.td:1096
282 G_FCOS = 267, // GenericOpcodes.td:1103
283 G_FSIN = 268, // GenericOpcodes.td:1110
284 G_FSINCOS = 269, // GenericOpcodes.td:1117
285 G_FTAN = 270, // GenericOpcodes.td:1124
286 G_FACOS = 271, // GenericOpcodes.td:1131
287 G_FASIN = 272, // GenericOpcodes.td:1138
288 G_FATAN = 273, // GenericOpcodes.td:1145
289 G_FATAN2 = 274, // GenericOpcodes.td:1152
290 G_FCOSH = 275, // GenericOpcodes.td:1159
291 G_FSINH = 276, // GenericOpcodes.td:1166
292 G_FTANH = 277, // GenericOpcodes.td:1173
293 G_FSQRT = 278, // GenericOpcodes.td:1183
294 G_FFLOOR = 279, // GenericOpcodes.td:1190
295 G_FRINT = 280, // GenericOpcodes.td:1197
296 G_FNEARBYINT = 281, // GenericOpcodes.td:1204
297 G_ADDRSPACE_CAST = 282, // GenericOpcodes.td:241
298 G_BLOCK_ADDR = 283, // GenericOpcodes.td:247
299 G_JUMP_TABLE = 284, // GenericOpcodes.td:253
300 G_DYN_STACKALLOC = 285, // GenericOpcodes.td:259
301 G_STACKSAVE = 286, // GenericOpcodes.td:265
302 G_STACKRESTORE = 287, // GenericOpcodes.td:271
303 G_STRICT_FADD = 288, // GenericOpcodes.td:1760
304 G_STRICT_FSUB = 289, // GenericOpcodes.td:1761
305 G_STRICT_FMUL = 290, // GenericOpcodes.td:1762
306 G_STRICT_FDIV = 291, // GenericOpcodes.td:1763
307 G_STRICT_FREM = 292, // GenericOpcodes.td:1764
308 G_STRICT_FMA = 293, // GenericOpcodes.td:1765
309 G_STRICT_FSQRT = 294, // GenericOpcodes.td:1766
310 G_STRICT_FLDEXP = 295, // GenericOpcodes.td:1767
311 G_READ_REGISTER = 296, // GenericOpcodes.td:1633
312 G_WRITE_REGISTER = 297, // GenericOpcodes.td:1643
313 G_MEMCPY = 298, // GenericOpcodes.td:1773
314 G_MEMCPY_INLINE = 299, // GenericOpcodes.td:1781
315 G_MEMMOVE = 300, // GenericOpcodes.td:1789
316 G_MEMSET = 301, // GenericOpcodes.td:1797
317 G_BZERO = 302, // GenericOpcodes.td:1804
318 G_TRAP = 303, // GenericOpcodes.td:1814
319 G_DEBUGTRAP = 304, // GenericOpcodes.td:1821
320 G_UBSANTRAP = 305, // GenericOpcodes.td:1827
321 G_VECREDUCE_SEQ_FADD = 306, // GenericOpcodes.td:1726
322 G_VECREDUCE_SEQ_FMUL = 307, // GenericOpcodes.td:1732
323 G_VECREDUCE_FADD = 308, // GenericOpcodes.td:1738
324 G_VECREDUCE_FMUL = 309, // GenericOpcodes.td:1739
325 G_VECREDUCE_FMAX = 310, // GenericOpcodes.td:1741
326 G_VECREDUCE_FMIN = 311, // GenericOpcodes.td:1742
327 G_VECREDUCE_FMAXIMUM = 312, // GenericOpcodes.td:1743
328 G_VECREDUCE_FMINIMUM = 313, // GenericOpcodes.td:1744
329 G_VECREDUCE_ADD = 314, // GenericOpcodes.td:1746
330 G_VECREDUCE_MUL = 315, // GenericOpcodes.td:1747
331 G_VECREDUCE_AND = 316, // GenericOpcodes.td:1748
332 G_VECREDUCE_OR = 317, // GenericOpcodes.td:1749
333 G_VECREDUCE_XOR = 318, // GenericOpcodes.td:1750
334 G_VECREDUCE_SMAX = 319, // GenericOpcodes.td:1751
335 G_VECREDUCE_SMIN = 320, // GenericOpcodes.td:1752
336 G_VECREDUCE_UMAX = 321, // GenericOpcodes.td:1753
337 G_VECREDUCE_UMIN = 322, // GenericOpcodes.td:1754
338 G_SBFX = 323, // GenericOpcodes.td:1839
339 G_UBFX = 324, // GenericOpcodes.td:1847
340 CALL_PARAMS = 325, // WebAssemblyInstrFormats.td:59
341 CALL_PARAMS_S = 326, // WebAssemblyInstrFormats.td:61
342 CALL_RESULTS = 327, // WebAssemblyInstrFormats.td:59
343 CALL_RESULTS_S = 328, // WebAssemblyInstrFormats.td:61
344 CATCHRET = 329, // WebAssemblyInstrFormats.td:59
345 CATCHRET_S = 330, // WebAssemblyInstrFormats.td:61
346 CLEANUPRET = 331, // WebAssemblyInstrFormats.td:59
347 CLEANUPRET_S = 332, // WebAssemblyInstrFormats.td:61
348 COMPILER_FENCE = 333, // WebAssemblyInstrFormats.td:59
349 COMPILER_FENCE_S = 334, // WebAssemblyInstrFormats.td:61
350 RET_CALL_RESULTS = 335, // WebAssemblyInstrFormats.td:59
351 RET_CALL_RESULTS_S = 336, // WebAssemblyInstrFormats.td:61
352 ABS_F16x8 = 337, // WebAssemblyInstrFormats.td:59
353 ABS_F16x8_S = 338, // WebAssemblyInstrFormats.td:61
354 ABS_F32 = 339, // WebAssemblyInstrFormats.td:59
355 ABS_F32_S = 340, // WebAssemblyInstrFormats.td:61
356 ABS_F32x4 = 341, // WebAssemblyInstrFormats.td:59
357 ABS_F32x4_S = 342, // WebAssemblyInstrFormats.td:61
358 ABS_F64 = 343, // WebAssemblyInstrFormats.td:59
359 ABS_F64_S = 344, // WebAssemblyInstrFormats.td:61
360 ABS_F64x2 = 345, // WebAssemblyInstrFormats.td:59
361 ABS_F64x2_S = 346, // WebAssemblyInstrFormats.td:61
362 ABS_I16x8 = 347, // WebAssemblyInstrFormats.td:59
363 ABS_I16x8_S = 348, // WebAssemblyInstrFormats.td:61
364 ABS_I32x4 = 349, // WebAssemblyInstrFormats.td:59
365 ABS_I32x4_S = 350, // WebAssemblyInstrFormats.td:61
366 ABS_I64x2 = 351, // WebAssemblyInstrFormats.td:59
367 ABS_I64x2_S = 352, // WebAssemblyInstrFormats.td:61
368 ABS_I8x16 = 353, // WebAssemblyInstrFormats.td:59
369 ABS_I8x16_S = 354, // WebAssemblyInstrFormats.td:61
370 ADD_F16x8 = 355, // WebAssemblyInstrFormats.td:59
371 ADD_F16x8_S = 356, // WebAssemblyInstrFormats.td:61
372 ADD_F32 = 357, // WebAssemblyInstrFormats.td:59
373 ADD_F32_S = 358, // WebAssemblyInstrFormats.td:61
374 ADD_F32x4 = 359, // WebAssemblyInstrFormats.td:59
375 ADD_F32x4_S = 360, // WebAssemblyInstrFormats.td:61
376 ADD_F64 = 361, // WebAssemblyInstrFormats.td:59
377 ADD_F64_S = 362, // WebAssemblyInstrFormats.td:61
378 ADD_F64x2 = 363, // WebAssemblyInstrFormats.td:59
379 ADD_F64x2_S = 364, // WebAssemblyInstrFormats.td:61
380 ADD_I16x8 = 365, // WebAssemblyInstrFormats.td:59
381 ADD_I16x8_S = 366, // WebAssemblyInstrFormats.td:61
382 ADD_I32 = 367, // WebAssemblyInstrFormats.td:59
383 ADD_I32_S = 368, // WebAssemblyInstrFormats.td:61
384 ADD_I32x4 = 369, // WebAssemblyInstrFormats.td:59
385 ADD_I32x4_S = 370, // WebAssemblyInstrFormats.td:61
386 ADD_I64 = 371, // WebAssemblyInstrFormats.td:59
387 ADD_I64_S = 372, // WebAssemblyInstrFormats.td:61
388 ADD_I64x2 = 373, // WebAssemblyInstrFormats.td:59
389 ADD_I64x2_S = 374, // WebAssemblyInstrFormats.td:61
390 ADD_I8x16 = 375, // WebAssemblyInstrFormats.td:59
391 ADD_I8x16_S = 376, // WebAssemblyInstrFormats.td:61
392 ADD_SAT_S_I16x8 = 377, // WebAssemblyInstrFormats.td:59
393 ADD_SAT_S_I16x8_S = 378, // WebAssemblyInstrFormats.td:61
394 ADD_SAT_S_I8x16 = 379, // WebAssemblyInstrFormats.td:59
395 ADD_SAT_S_I8x16_S = 380, // WebAssemblyInstrFormats.td:61
396 ADD_SAT_U_I16x8 = 381, // WebAssemblyInstrFormats.td:59
397 ADD_SAT_U_I16x8_S = 382, // WebAssemblyInstrFormats.td:61
398 ADD_SAT_U_I8x16 = 383, // WebAssemblyInstrFormats.td:59
399 ADD_SAT_U_I8x16_S = 384, // WebAssemblyInstrFormats.td:61
400 ADJCALLSTACKDOWN = 385, // WebAssemblyInstrFormats.td:59
401 ADJCALLSTACKDOWN_S = 386, // WebAssemblyInstrFormats.td:61
402 ADJCALLSTACKUP = 387, // WebAssemblyInstrFormats.td:59
403 ADJCALLSTACKUP_S = 388, // WebAssemblyInstrFormats.td:61
404 ALLTRUE_I16x8 = 389, // WebAssemblyInstrFormats.td:59
405 ALLTRUE_I16x8_S = 390, // WebAssemblyInstrFormats.td:61
406 ALLTRUE_I32x4 = 391, // WebAssemblyInstrFormats.td:59
407 ALLTRUE_I32x4_S = 392, // WebAssemblyInstrFormats.td:61
408 ALLTRUE_I64x2 = 393, // WebAssemblyInstrFormats.td:59
409 ALLTRUE_I64x2_S = 394, // WebAssemblyInstrFormats.td:61
410 ALLTRUE_I8x16 = 395, // WebAssemblyInstrFormats.td:59
411 ALLTRUE_I8x16_S = 396, // WebAssemblyInstrFormats.td:61
412 AND = 397, // WebAssemblyInstrFormats.td:59
413 ANDNOT = 398, // WebAssemblyInstrFormats.td:59
414 ANDNOT_S = 399, // WebAssemblyInstrFormats.td:61
415 AND_I32 = 400, // WebAssemblyInstrFormats.td:59
416 AND_I32_S = 401, // WebAssemblyInstrFormats.td:61
417 AND_I64 = 402, // WebAssemblyInstrFormats.td:59
418 AND_I64_S = 403, // WebAssemblyInstrFormats.td:61
419 AND_S = 404, // WebAssemblyInstrFormats.td:61
420 ANYTRUE = 405, // WebAssemblyInstrFormats.td:59
421 ANYTRUE_S = 406, // WebAssemblyInstrFormats.td:61
422 ARGUMENT_exnref = 407, // WebAssemblyInstrFormats.td:59
423 ARGUMENT_exnref_S = 408, // WebAssemblyInstrFormats.td:61
424 ARGUMENT_externref = 409, // WebAssemblyInstrFormats.td:59
425 ARGUMENT_externref_S = 410, // WebAssemblyInstrFormats.td:61
426 ARGUMENT_f32 = 411, // WebAssemblyInstrFormats.td:59
427 ARGUMENT_f32_S = 412, // WebAssemblyInstrFormats.td:61
428 ARGUMENT_f64 = 413, // WebAssemblyInstrFormats.td:59
429 ARGUMENT_f64_S = 414, // WebAssemblyInstrFormats.td:61
430 ARGUMENT_funcref = 415, // WebAssemblyInstrFormats.td:59
431 ARGUMENT_funcref_S = 416, // WebAssemblyInstrFormats.td:61
432 ARGUMENT_i32 = 417, // WebAssemblyInstrFormats.td:59
433 ARGUMENT_i32_S = 418, // WebAssemblyInstrFormats.td:61
434 ARGUMENT_i64 = 419, // WebAssemblyInstrFormats.td:59
435 ARGUMENT_i64_S = 420, // WebAssemblyInstrFormats.td:61
436 ARGUMENT_v16i8 = 421, // WebAssemblyInstrFormats.td:59
437 ARGUMENT_v16i8_S = 422, // WebAssemblyInstrFormats.td:61
438 ARGUMENT_v2f64 = 423, // WebAssemblyInstrFormats.td:59
439 ARGUMENT_v2f64_S = 424, // WebAssemblyInstrFormats.td:61
440 ARGUMENT_v2i64 = 425, // WebAssemblyInstrFormats.td:59
441 ARGUMENT_v2i64_S = 426, // WebAssemblyInstrFormats.td:61
442 ARGUMENT_v4f32 = 427, // WebAssemblyInstrFormats.td:59
443 ARGUMENT_v4f32_S = 428, // WebAssemblyInstrFormats.td:61
444 ARGUMENT_v4i32 = 429, // WebAssemblyInstrFormats.td:59
445 ARGUMENT_v4i32_S = 430, // WebAssemblyInstrFormats.td:61
446 ARGUMENT_v8f16 = 431, // WebAssemblyInstrFormats.td:59
447 ARGUMENT_v8f16_S = 432, // WebAssemblyInstrFormats.td:61
448 ARGUMENT_v8i16 = 433, // WebAssemblyInstrFormats.td:59
449 ARGUMENT_v8i16_S = 434, // WebAssemblyInstrFormats.td:61
450 ATOMIC_FENCE = 435, // WebAssemblyInstrFormats.td:59
451 ATOMIC_FENCE_S = 436, // WebAssemblyInstrFormats.td:61
452 ATOMIC_LOAD16_U_I32_A32 = 437, // WebAssemblyInstrFormats.td:59
453 ATOMIC_LOAD16_U_I32_A32_S = 438, // WebAssemblyInstrFormats.td:61
454 ATOMIC_LOAD16_U_I32_A64 = 439, // WebAssemblyInstrFormats.td:59
455 ATOMIC_LOAD16_U_I32_A64_S = 440, // WebAssemblyInstrFormats.td:61
456 ATOMIC_LOAD16_U_I64_A32 = 441, // WebAssemblyInstrFormats.td:59
457 ATOMIC_LOAD16_U_I64_A32_S = 442, // WebAssemblyInstrFormats.td:61
458 ATOMIC_LOAD16_U_I64_A64 = 443, // WebAssemblyInstrFormats.td:59
459 ATOMIC_LOAD16_U_I64_A64_S = 444, // WebAssemblyInstrFormats.td:61
460 ATOMIC_LOAD32_U_I64_A32 = 445, // WebAssemblyInstrFormats.td:59
461 ATOMIC_LOAD32_U_I64_A32_S = 446, // WebAssemblyInstrFormats.td:61
462 ATOMIC_LOAD32_U_I64_A64 = 447, // WebAssemblyInstrFormats.td:59
463 ATOMIC_LOAD32_U_I64_A64_S = 448, // WebAssemblyInstrFormats.td:61
464 ATOMIC_LOAD8_U_I32_A32 = 449, // WebAssemblyInstrFormats.td:59
465 ATOMIC_LOAD8_U_I32_A32_S = 450, // WebAssemblyInstrFormats.td:61
466 ATOMIC_LOAD8_U_I32_A64 = 451, // WebAssemblyInstrFormats.td:59
467 ATOMIC_LOAD8_U_I32_A64_S = 452, // WebAssemblyInstrFormats.td:61
468 ATOMIC_LOAD8_U_I64_A32 = 453, // WebAssemblyInstrFormats.td:59
469 ATOMIC_LOAD8_U_I64_A32_S = 454, // WebAssemblyInstrFormats.td:61
470 ATOMIC_LOAD8_U_I64_A64 = 455, // WebAssemblyInstrFormats.td:59
471 ATOMIC_LOAD8_U_I64_A64_S = 456, // WebAssemblyInstrFormats.td:61
472 ATOMIC_LOAD_I32_A32 = 457, // WebAssemblyInstrFormats.td:59
473 ATOMIC_LOAD_I32_A32_S = 458, // WebAssemblyInstrFormats.td:61
474 ATOMIC_LOAD_I32_A64 = 459, // WebAssemblyInstrFormats.td:59
475 ATOMIC_LOAD_I32_A64_S = 460, // WebAssemblyInstrFormats.td:61
476 ATOMIC_LOAD_I64_A32 = 461, // WebAssemblyInstrFormats.td:59
477 ATOMIC_LOAD_I64_A32_S = 462, // WebAssemblyInstrFormats.td:61
478 ATOMIC_LOAD_I64_A64 = 463, // WebAssemblyInstrFormats.td:59
479 ATOMIC_LOAD_I64_A64_S = 464, // WebAssemblyInstrFormats.td:61
480 ATOMIC_RMW16_U_ADD_I32_A32 = 465, // WebAssemblyInstrFormats.td:59
481 ATOMIC_RMW16_U_ADD_I32_A32_S = 466, // WebAssemblyInstrFormats.td:61
482 ATOMIC_RMW16_U_ADD_I32_A64 = 467, // WebAssemblyInstrFormats.td:59
483 ATOMIC_RMW16_U_ADD_I32_A64_S = 468, // WebAssemblyInstrFormats.td:61
484 ATOMIC_RMW16_U_ADD_I64_A32 = 469, // WebAssemblyInstrFormats.td:59
485 ATOMIC_RMW16_U_ADD_I64_A32_S = 470, // WebAssemblyInstrFormats.td:61
486 ATOMIC_RMW16_U_ADD_I64_A64 = 471, // WebAssemblyInstrFormats.td:59
487 ATOMIC_RMW16_U_ADD_I64_A64_S = 472, // WebAssemblyInstrFormats.td:61
488 ATOMIC_RMW16_U_AND_I32_A32 = 473, // WebAssemblyInstrFormats.td:59
489 ATOMIC_RMW16_U_AND_I32_A32_S = 474, // WebAssemblyInstrFormats.td:61
490 ATOMIC_RMW16_U_AND_I32_A64 = 475, // WebAssemblyInstrFormats.td:59
491 ATOMIC_RMW16_U_AND_I32_A64_S = 476, // WebAssemblyInstrFormats.td:61
492 ATOMIC_RMW16_U_AND_I64_A32 = 477, // WebAssemblyInstrFormats.td:59
493 ATOMIC_RMW16_U_AND_I64_A32_S = 478, // WebAssemblyInstrFormats.td:61
494 ATOMIC_RMW16_U_AND_I64_A64 = 479, // WebAssemblyInstrFormats.td:59
495 ATOMIC_RMW16_U_AND_I64_A64_S = 480, // WebAssemblyInstrFormats.td:61
496 ATOMIC_RMW16_U_CMPXCHG_I32_A32 = 481, // WebAssemblyInstrFormats.td:59
497 ATOMIC_RMW16_U_CMPXCHG_I32_A32_S = 482, // WebAssemblyInstrFormats.td:61
498 ATOMIC_RMW16_U_CMPXCHG_I32_A64 = 483, // WebAssemblyInstrFormats.td:59
499 ATOMIC_RMW16_U_CMPXCHG_I32_A64_S = 484, // WebAssemblyInstrFormats.td:61
500 ATOMIC_RMW16_U_CMPXCHG_I64_A32 = 485, // WebAssemblyInstrFormats.td:59
501 ATOMIC_RMW16_U_CMPXCHG_I64_A32_S = 486, // WebAssemblyInstrFormats.td:61
502 ATOMIC_RMW16_U_CMPXCHG_I64_A64 = 487, // WebAssemblyInstrFormats.td:59
503 ATOMIC_RMW16_U_CMPXCHG_I64_A64_S = 488, // WebAssemblyInstrFormats.td:61
504 ATOMIC_RMW16_U_OR_I32_A32 = 489, // WebAssemblyInstrFormats.td:59
505 ATOMIC_RMW16_U_OR_I32_A32_S = 490, // WebAssemblyInstrFormats.td:61
506 ATOMIC_RMW16_U_OR_I32_A64 = 491, // WebAssemblyInstrFormats.td:59
507 ATOMIC_RMW16_U_OR_I32_A64_S = 492, // WebAssemblyInstrFormats.td:61
508 ATOMIC_RMW16_U_OR_I64_A32 = 493, // WebAssemblyInstrFormats.td:59
509 ATOMIC_RMW16_U_OR_I64_A32_S = 494, // WebAssemblyInstrFormats.td:61
510 ATOMIC_RMW16_U_OR_I64_A64 = 495, // WebAssemblyInstrFormats.td:59
511 ATOMIC_RMW16_U_OR_I64_A64_S = 496, // WebAssemblyInstrFormats.td:61
512 ATOMIC_RMW16_U_SUB_I32_A32 = 497, // WebAssemblyInstrFormats.td:59
513 ATOMIC_RMW16_U_SUB_I32_A32_S = 498, // WebAssemblyInstrFormats.td:61
514 ATOMIC_RMW16_U_SUB_I32_A64 = 499, // WebAssemblyInstrFormats.td:59
515 ATOMIC_RMW16_U_SUB_I32_A64_S = 500, // WebAssemblyInstrFormats.td:61
516 ATOMIC_RMW16_U_SUB_I64_A32 = 501, // WebAssemblyInstrFormats.td:59
517 ATOMIC_RMW16_U_SUB_I64_A32_S = 502, // WebAssemblyInstrFormats.td:61
518 ATOMIC_RMW16_U_SUB_I64_A64 = 503, // WebAssemblyInstrFormats.td:59
519 ATOMIC_RMW16_U_SUB_I64_A64_S = 504, // WebAssemblyInstrFormats.td:61
520 ATOMIC_RMW16_U_XCHG_I32_A32 = 505, // WebAssemblyInstrFormats.td:59
521 ATOMIC_RMW16_U_XCHG_I32_A32_S = 506, // WebAssemblyInstrFormats.td:61
522 ATOMIC_RMW16_U_XCHG_I32_A64 = 507, // WebAssemblyInstrFormats.td:59
523 ATOMIC_RMW16_U_XCHG_I32_A64_S = 508, // WebAssemblyInstrFormats.td:61
524 ATOMIC_RMW16_U_XCHG_I64_A32 = 509, // WebAssemblyInstrFormats.td:59
525 ATOMIC_RMW16_U_XCHG_I64_A32_S = 510, // WebAssemblyInstrFormats.td:61
526 ATOMIC_RMW16_U_XCHG_I64_A64 = 511, // WebAssemblyInstrFormats.td:59
527 ATOMIC_RMW16_U_XCHG_I64_A64_S = 512, // WebAssemblyInstrFormats.td:61
528 ATOMIC_RMW16_U_XOR_I32_A32 = 513, // WebAssemblyInstrFormats.td:59
529 ATOMIC_RMW16_U_XOR_I32_A32_S = 514, // WebAssemblyInstrFormats.td:61
530 ATOMIC_RMW16_U_XOR_I32_A64 = 515, // WebAssemblyInstrFormats.td:59
531 ATOMIC_RMW16_U_XOR_I32_A64_S = 516, // WebAssemblyInstrFormats.td:61
532 ATOMIC_RMW16_U_XOR_I64_A32 = 517, // WebAssemblyInstrFormats.td:59
533 ATOMIC_RMW16_U_XOR_I64_A32_S = 518, // WebAssemblyInstrFormats.td:61
534 ATOMIC_RMW16_U_XOR_I64_A64 = 519, // WebAssemblyInstrFormats.td:59
535 ATOMIC_RMW16_U_XOR_I64_A64_S = 520, // WebAssemblyInstrFormats.td:61
536 ATOMIC_RMW32_U_ADD_I64_A32 = 521, // WebAssemblyInstrFormats.td:59
537 ATOMIC_RMW32_U_ADD_I64_A32_S = 522, // WebAssemblyInstrFormats.td:61
538 ATOMIC_RMW32_U_ADD_I64_A64 = 523, // WebAssemblyInstrFormats.td:59
539 ATOMIC_RMW32_U_ADD_I64_A64_S = 524, // WebAssemblyInstrFormats.td:61
540 ATOMIC_RMW32_U_AND_I64_A32 = 525, // WebAssemblyInstrFormats.td:59
541 ATOMIC_RMW32_U_AND_I64_A32_S = 526, // WebAssemblyInstrFormats.td:61
542 ATOMIC_RMW32_U_AND_I64_A64 = 527, // WebAssemblyInstrFormats.td:59
543 ATOMIC_RMW32_U_AND_I64_A64_S = 528, // WebAssemblyInstrFormats.td:61
544 ATOMIC_RMW32_U_CMPXCHG_I64_A32 = 529, // WebAssemblyInstrFormats.td:59
545 ATOMIC_RMW32_U_CMPXCHG_I64_A32_S = 530, // WebAssemblyInstrFormats.td:61
546 ATOMIC_RMW32_U_CMPXCHG_I64_A64 = 531, // WebAssemblyInstrFormats.td:59
547 ATOMIC_RMW32_U_CMPXCHG_I64_A64_S = 532, // WebAssemblyInstrFormats.td:61
548 ATOMIC_RMW32_U_OR_I64_A32 = 533, // WebAssemblyInstrFormats.td:59
549 ATOMIC_RMW32_U_OR_I64_A32_S = 534, // WebAssemblyInstrFormats.td:61
550 ATOMIC_RMW32_U_OR_I64_A64 = 535, // WebAssemblyInstrFormats.td:59
551 ATOMIC_RMW32_U_OR_I64_A64_S = 536, // WebAssemblyInstrFormats.td:61
552 ATOMIC_RMW32_U_SUB_I64_A32 = 537, // WebAssemblyInstrFormats.td:59
553 ATOMIC_RMW32_U_SUB_I64_A32_S = 538, // WebAssemblyInstrFormats.td:61
554 ATOMIC_RMW32_U_SUB_I64_A64 = 539, // WebAssemblyInstrFormats.td:59
555 ATOMIC_RMW32_U_SUB_I64_A64_S = 540, // WebAssemblyInstrFormats.td:61
556 ATOMIC_RMW32_U_XCHG_I64_A32 = 541, // WebAssemblyInstrFormats.td:59
557 ATOMIC_RMW32_U_XCHG_I64_A32_S = 542, // WebAssemblyInstrFormats.td:61
558 ATOMIC_RMW32_U_XCHG_I64_A64 = 543, // WebAssemblyInstrFormats.td:59
559 ATOMIC_RMW32_U_XCHG_I64_A64_S = 544, // WebAssemblyInstrFormats.td:61
560 ATOMIC_RMW32_U_XOR_I64_A32 = 545, // WebAssemblyInstrFormats.td:59
561 ATOMIC_RMW32_U_XOR_I64_A32_S = 546, // WebAssemblyInstrFormats.td:61
562 ATOMIC_RMW32_U_XOR_I64_A64 = 547, // WebAssemblyInstrFormats.td:59
563 ATOMIC_RMW32_U_XOR_I64_A64_S = 548, // WebAssemblyInstrFormats.td:61
564 ATOMIC_RMW8_U_ADD_I32_A32 = 549, // WebAssemblyInstrFormats.td:59
565 ATOMIC_RMW8_U_ADD_I32_A32_S = 550, // WebAssemblyInstrFormats.td:61
566 ATOMIC_RMW8_U_ADD_I32_A64 = 551, // WebAssemblyInstrFormats.td:59
567 ATOMIC_RMW8_U_ADD_I32_A64_S = 552, // WebAssemblyInstrFormats.td:61
568 ATOMIC_RMW8_U_ADD_I64_A32 = 553, // WebAssemblyInstrFormats.td:59
569 ATOMIC_RMW8_U_ADD_I64_A32_S = 554, // WebAssemblyInstrFormats.td:61
570 ATOMIC_RMW8_U_ADD_I64_A64 = 555, // WebAssemblyInstrFormats.td:59
571 ATOMIC_RMW8_U_ADD_I64_A64_S = 556, // WebAssemblyInstrFormats.td:61
572 ATOMIC_RMW8_U_AND_I32_A32 = 557, // WebAssemblyInstrFormats.td:59
573 ATOMIC_RMW8_U_AND_I32_A32_S = 558, // WebAssemblyInstrFormats.td:61
574 ATOMIC_RMW8_U_AND_I32_A64 = 559, // WebAssemblyInstrFormats.td:59
575 ATOMIC_RMW8_U_AND_I32_A64_S = 560, // WebAssemblyInstrFormats.td:61
576 ATOMIC_RMW8_U_AND_I64_A32 = 561, // WebAssemblyInstrFormats.td:59
577 ATOMIC_RMW8_U_AND_I64_A32_S = 562, // WebAssemblyInstrFormats.td:61
578 ATOMIC_RMW8_U_AND_I64_A64 = 563, // WebAssemblyInstrFormats.td:59
579 ATOMIC_RMW8_U_AND_I64_A64_S = 564, // WebAssemblyInstrFormats.td:61
580 ATOMIC_RMW8_U_CMPXCHG_I32_A32 = 565, // WebAssemblyInstrFormats.td:59
581 ATOMIC_RMW8_U_CMPXCHG_I32_A32_S = 566, // WebAssemblyInstrFormats.td:61
582 ATOMIC_RMW8_U_CMPXCHG_I32_A64 = 567, // WebAssemblyInstrFormats.td:59
583 ATOMIC_RMW8_U_CMPXCHG_I32_A64_S = 568, // WebAssemblyInstrFormats.td:61
584 ATOMIC_RMW8_U_CMPXCHG_I64_A32 = 569, // WebAssemblyInstrFormats.td:59
585 ATOMIC_RMW8_U_CMPXCHG_I64_A32_S = 570, // WebAssemblyInstrFormats.td:61
586 ATOMIC_RMW8_U_CMPXCHG_I64_A64 = 571, // WebAssemblyInstrFormats.td:59
587 ATOMIC_RMW8_U_CMPXCHG_I64_A64_S = 572, // WebAssemblyInstrFormats.td:61
588 ATOMIC_RMW8_U_OR_I32_A32 = 573, // WebAssemblyInstrFormats.td:59
589 ATOMIC_RMW8_U_OR_I32_A32_S = 574, // WebAssemblyInstrFormats.td:61
590 ATOMIC_RMW8_U_OR_I32_A64 = 575, // WebAssemblyInstrFormats.td:59
591 ATOMIC_RMW8_U_OR_I32_A64_S = 576, // WebAssemblyInstrFormats.td:61
592 ATOMIC_RMW8_U_OR_I64_A32 = 577, // WebAssemblyInstrFormats.td:59
593 ATOMIC_RMW8_U_OR_I64_A32_S = 578, // WebAssemblyInstrFormats.td:61
594 ATOMIC_RMW8_U_OR_I64_A64 = 579, // WebAssemblyInstrFormats.td:59
595 ATOMIC_RMW8_U_OR_I64_A64_S = 580, // WebAssemblyInstrFormats.td:61
596 ATOMIC_RMW8_U_SUB_I32_A32 = 581, // WebAssemblyInstrFormats.td:59
597 ATOMIC_RMW8_U_SUB_I32_A32_S = 582, // WebAssemblyInstrFormats.td:61
598 ATOMIC_RMW8_U_SUB_I32_A64 = 583, // WebAssemblyInstrFormats.td:59
599 ATOMIC_RMW8_U_SUB_I32_A64_S = 584, // WebAssemblyInstrFormats.td:61
600 ATOMIC_RMW8_U_SUB_I64_A32 = 585, // WebAssemblyInstrFormats.td:59
601 ATOMIC_RMW8_U_SUB_I64_A32_S = 586, // WebAssemblyInstrFormats.td:61
602 ATOMIC_RMW8_U_SUB_I64_A64 = 587, // WebAssemblyInstrFormats.td:59
603 ATOMIC_RMW8_U_SUB_I64_A64_S = 588, // WebAssemblyInstrFormats.td:61
604 ATOMIC_RMW8_U_XCHG_I32_A32 = 589, // WebAssemblyInstrFormats.td:59
605 ATOMIC_RMW8_U_XCHG_I32_A32_S = 590, // WebAssemblyInstrFormats.td:61
606 ATOMIC_RMW8_U_XCHG_I32_A64 = 591, // WebAssemblyInstrFormats.td:59
607 ATOMIC_RMW8_U_XCHG_I32_A64_S = 592, // WebAssemblyInstrFormats.td:61
608 ATOMIC_RMW8_U_XCHG_I64_A32 = 593, // WebAssemblyInstrFormats.td:59
609 ATOMIC_RMW8_U_XCHG_I64_A32_S = 594, // WebAssemblyInstrFormats.td:61
610 ATOMIC_RMW8_U_XCHG_I64_A64 = 595, // WebAssemblyInstrFormats.td:59
611 ATOMIC_RMW8_U_XCHG_I64_A64_S = 596, // WebAssemblyInstrFormats.td:61
612 ATOMIC_RMW8_U_XOR_I32_A32 = 597, // WebAssemblyInstrFormats.td:59
613 ATOMIC_RMW8_U_XOR_I32_A32_S = 598, // WebAssemblyInstrFormats.td:61
614 ATOMIC_RMW8_U_XOR_I32_A64 = 599, // WebAssemblyInstrFormats.td:59
615 ATOMIC_RMW8_U_XOR_I32_A64_S = 600, // WebAssemblyInstrFormats.td:61
616 ATOMIC_RMW8_U_XOR_I64_A32 = 601, // WebAssemblyInstrFormats.td:59
617 ATOMIC_RMW8_U_XOR_I64_A32_S = 602, // WebAssemblyInstrFormats.td:61
618 ATOMIC_RMW8_U_XOR_I64_A64 = 603, // WebAssemblyInstrFormats.td:59
619 ATOMIC_RMW8_U_XOR_I64_A64_S = 604, // WebAssemblyInstrFormats.td:61
620 ATOMIC_RMW_ADD_I32_A32 = 605, // WebAssemblyInstrFormats.td:59
621 ATOMIC_RMW_ADD_I32_A32_S = 606, // WebAssemblyInstrFormats.td:61
622 ATOMIC_RMW_ADD_I32_A64 = 607, // WebAssemblyInstrFormats.td:59
623 ATOMIC_RMW_ADD_I32_A64_S = 608, // WebAssemblyInstrFormats.td:61
624 ATOMIC_RMW_ADD_I64_A32 = 609, // WebAssemblyInstrFormats.td:59
625 ATOMIC_RMW_ADD_I64_A32_S = 610, // WebAssemblyInstrFormats.td:61
626 ATOMIC_RMW_ADD_I64_A64 = 611, // WebAssemblyInstrFormats.td:59
627 ATOMIC_RMW_ADD_I64_A64_S = 612, // WebAssemblyInstrFormats.td:61
628 ATOMIC_RMW_AND_I32_A32 = 613, // WebAssemblyInstrFormats.td:59
629 ATOMIC_RMW_AND_I32_A32_S = 614, // WebAssemblyInstrFormats.td:61
630 ATOMIC_RMW_AND_I32_A64 = 615, // WebAssemblyInstrFormats.td:59
631 ATOMIC_RMW_AND_I32_A64_S = 616, // WebAssemblyInstrFormats.td:61
632 ATOMIC_RMW_AND_I64_A32 = 617, // WebAssemblyInstrFormats.td:59
633 ATOMIC_RMW_AND_I64_A32_S = 618, // WebAssemblyInstrFormats.td:61
634 ATOMIC_RMW_AND_I64_A64 = 619, // WebAssemblyInstrFormats.td:59
635 ATOMIC_RMW_AND_I64_A64_S = 620, // WebAssemblyInstrFormats.td:61
636 ATOMIC_RMW_CMPXCHG_I32_A32 = 621, // WebAssemblyInstrFormats.td:59
637 ATOMIC_RMW_CMPXCHG_I32_A32_S = 622, // WebAssemblyInstrFormats.td:61
638 ATOMIC_RMW_CMPXCHG_I32_A64 = 623, // WebAssemblyInstrFormats.td:59
639 ATOMIC_RMW_CMPXCHG_I32_A64_S = 624, // WebAssemblyInstrFormats.td:61
640 ATOMIC_RMW_CMPXCHG_I64_A32 = 625, // WebAssemblyInstrFormats.td:59
641 ATOMIC_RMW_CMPXCHG_I64_A32_S = 626, // WebAssemblyInstrFormats.td:61
642 ATOMIC_RMW_CMPXCHG_I64_A64 = 627, // WebAssemblyInstrFormats.td:59
643 ATOMIC_RMW_CMPXCHG_I64_A64_S = 628, // WebAssemblyInstrFormats.td:61
644 ATOMIC_RMW_OR_I32_A32 = 629, // WebAssemblyInstrFormats.td:59
645 ATOMIC_RMW_OR_I32_A32_S = 630, // WebAssemblyInstrFormats.td:61
646 ATOMIC_RMW_OR_I32_A64 = 631, // WebAssemblyInstrFormats.td:59
647 ATOMIC_RMW_OR_I32_A64_S = 632, // WebAssemblyInstrFormats.td:61
648 ATOMIC_RMW_OR_I64_A32 = 633, // WebAssemblyInstrFormats.td:59
649 ATOMIC_RMW_OR_I64_A32_S = 634, // WebAssemblyInstrFormats.td:61
650 ATOMIC_RMW_OR_I64_A64 = 635, // WebAssemblyInstrFormats.td:59
651 ATOMIC_RMW_OR_I64_A64_S = 636, // WebAssemblyInstrFormats.td:61
652 ATOMIC_RMW_SUB_I32_A32 = 637, // WebAssemblyInstrFormats.td:59
653 ATOMIC_RMW_SUB_I32_A32_S = 638, // WebAssemblyInstrFormats.td:61
654 ATOMIC_RMW_SUB_I32_A64 = 639, // WebAssemblyInstrFormats.td:59
655 ATOMIC_RMW_SUB_I32_A64_S = 640, // WebAssemblyInstrFormats.td:61
656 ATOMIC_RMW_SUB_I64_A32 = 641, // WebAssemblyInstrFormats.td:59
657 ATOMIC_RMW_SUB_I64_A32_S = 642, // WebAssemblyInstrFormats.td:61
658 ATOMIC_RMW_SUB_I64_A64 = 643, // WebAssemblyInstrFormats.td:59
659 ATOMIC_RMW_SUB_I64_A64_S = 644, // WebAssemblyInstrFormats.td:61
660 ATOMIC_RMW_XCHG_I32_A32 = 645, // WebAssemblyInstrFormats.td:59
661 ATOMIC_RMW_XCHG_I32_A32_S = 646, // WebAssemblyInstrFormats.td:61
662 ATOMIC_RMW_XCHG_I32_A64 = 647, // WebAssemblyInstrFormats.td:59
663 ATOMIC_RMW_XCHG_I32_A64_S = 648, // WebAssemblyInstrFormats.td:61
664 ATOMIC_RMW_XCHG_I64_A32 = 649, // WebAssemblyInstrFormats.td:59
665 ATOMIC_RMW_XCHG_I64_A32_S = 650, // WebAssemblyInstrFormats.td:61
666 ATOMIC_RMW_XCHG_I64_A64 = 651, // WebAssemblyInstrFormats.td:59
667 ATOMIC_RMW_XCHG_I64_A64_S = 652, // WebAssemblyInstrFormats.td:61
668 ATOMIC_RMW_XOR_I32_A32 = 653, // WebAssemblyInstrFormats.td:59
669 ATOMIC_RMW_XOR_I32_A32_S = 654, // WebAssemblyInstrFormats.td:61
670 ATOMIC_RMW_XOR_I32_A64 = 655, // WebAssemblyInstrFormats.td:59
671 ATOMIC_RMW_XOR_I32_A64_S = 656, // WebAssemblyInstrFormats.td:61
672 ATOMIC_RMW_XOR_I64_A32 = 657, // WebAssemblyInstrFormats.td:59
673 ATOMIC_RMW_XOR_I64_A32_S = 658, // WebAssemblyInstrFormats.td:61
674 ATOMIC_RMW_XOR_I64_A64 = 659, // WebAssemblyInstrFormats.td:59
675 ATOMIC_RMW_XOR_I64_A64_S = 660, // WebAssemblyInstrFormats.td:61
676 ATOMIC_STORE16_I32_A32 = 661, // WebAssemblyInstrFormats.td:59
677 ATOMIC_STORE16_I32_A32_S = 662, // WebAssemblyInstrFormats.td:61
678 ATOMIC_STORE16_I32_A64 = 663, // WebAssemblyInstrFormats.td:59
679 ATOMIC_STORE16_I32_A64_S = 664, // WebAssemblyInstrFormats.td:61
680 ATOMIC_STORE16_I64_A32 = 665, // WebAssemblyInstrFormats.td:59
681 ATOMIC_STORE16_I64_A32_S = 666, // WebAssemblyInstrFormats.td:61
682 ATOMIC_STORE16_I64_A64 = 667, // WebAssemblyInstrFormats.td:59
683 ATOMIC_STORE16_I64_A64_S = 668, // WebAssemblyInstrFormats.td:61
684 ATOMIC_STORE32_I64_A32 = 669, // WebAssemblyInstrFormats.td:59
685 ATOMIC_STORE32_I64_A32_S = 670, // WebAssemblyInstrFormats.td:61
686 ATOMIC_STORE32_I64_A64 = 671, // WebAssemblyInstrFormats.td:59
687 ATOMIC_STORE32_I64_A64_S = 672, // WebAssemblyInstrFormats.td:61
688 ATOMIC_STORE8_I32_A32 = 673, // WebAssemblyInstrFormats.td:59
689 ATOMIC_STORE8_I32_A32_S = 674, // WebAssemblyInstrFormats.td:61
690 ATOMIC_STORE8_I32_A64 = 675, // WebAssemblyInstrFormats.td:59
691 ATOMIC_STORE8_I32_A64_S = 676, // WebAssemblyInstrFormats.td:61
692 ATOMIC_STORE8_I64_A32 = 677, // WebAssemblyInstrFormats.td:59
693 ATOMIC_STORE8_I64_A32_S = 678, // WebAssemblyInstrFormats.td:61
694 ATOMIC_STORE8_I64_A64 = 679, // WebAssemblyInstrFormats.td:59
695 ATOMIC_STORE8_I64_A64_S = 680, // WebAssemblyInstrFormats.td:61
696 ATOMIC_STORE_I32_A32 = 681, // WebAssemblyInstrFormats.td:59
697 ATOMIC_STORE_I32_A32_S = 682, // WebAssemblyInstrFormats.td:61
698 ATOMIC_STORE_I32_A64 = 683, // WebAssemblyInstrFormats.td:59
699 ATOMIC_STORE_I32_A64_S = 684, // WebAssemblyInstrFormats.td:61
700 ATOMIC_STORE_I64_A32 = 685, // WebAssemblyInstrFormats.td:59
701 ATOMIC_STORE_I64_A32_S = 686, // WebAssemblyInstrFormats.td:61
702 ATOMIC_STORE_I64_A64 = 687, // WebAssemblyInstrFormats.td:59
703 ATOMIC_STORE_I64_A64_S = 688, // WebAssemblyInstrFormats.td:61
704 AVGR_U_I16x8 = 689, // WebAssemblyInstrFormats.td:59
705 AVGR_U_I16x8_S = 690, // WebAssemblyInstrFormats.td:61
706 AVGR_U_I8x16 = 691, // WebAssemblyInstrFormats.td:59
707 AVGR_U_I8x16_S = 692, // WebAssemblyInstrFormats.td:61
708 BITMASK_I16x8 = 693, // WebAssemblyInstrFormats.td:59
709 BITMASK_I16x8_S = 694, // WebAssemblyInstrFormats.td:61
710 BITMASK_I32x4 = 695, // WebAssemblyInstrFormats.td:59
711 BITMASK_I32x4_S = 696, // WebAssemblyInstrFormats.td:61
712 BITMASK_I64x2 = 697, // WebAssemblyInstrFormats.td:59
713 BITMASK_I64x2_S = 698, // WebAssemblyInstrFormats.td:61
714 BITMASK_I8x16 = 699, // WebAssemblyInstrFormats.td:59
715 BITMASK_I8x16_S = 700, // WebAssemblyInstrFormats.td:61
716 BITSELECT = 701, // WebAssemblyInstrFormats.td:59
717 BITSELECT_S = 702, // WebAssemblyInstrFormats.td:61
718 BLOCK = 703, // WebAssemblyInstrFormats.td:59
719 BLOCK_S = 704, // WebAssemblyInstrFormats.td:61
720 BR = 705, // WebAssemblyInstrFormats.td:59
721 BR_IF = 706, // WebAssemblyInstrFormats.td:59
722 BR_IF_S = 707, // WebAssemblyInstrFormats.td:61
723 BR_S = 708, // WebAssemblyInstrFormats.td:61
724 BR_TABLE_I32 = 709, // WebAssemblyInstrFormats.td:59
725 BR_TABLE_I32_S = 710, // WebAssemblyInstrFormats.td:61
726 BR_TABLE_I64 = 711, // WebAssemblyInstrFormats.td:59
727 BR_TABLE_I64_S = 712, // WebAssemblyInstrFormats.td:61
728 BR_UNLESS = 713, // WebAssemblyInstrFormats.td:59
729 BR_UNLESS_S = 714, // WebAssemblyInstrFormats.td:61
730 CALL = 715, // WebAssemblyInstrFormats.td:59
731 CALL_INDIRECT = 716, // WebAssemblyInstrFormats.td:59
732 CALL_INDIRECT_S = 717, // WebAssemblyInstrFormats.td:61
733 CALL_S = 718, // WebAssemblyInstrFormats.td:61
734 CATCH = 719, // WebAssemblyInstrFormats.td:59
735 CATCH_ALL = 720, // WebAssemblyInstrFormats.td:59
736 CATCH_ALL_LEGACY = 721, // WebAssemblyInstrFormats.td:59
737 CATCH_ALL_LEGACY_S = 722, // WebAssemblyInstrFormats.td:61
738 CATCH_ALL_REF = 723, // WebAssemblyInstrFormats.td:59
739 CATCH_ALL_REF_S = 724, // WebAssemblyInstrFormats.td:61
740 CATCH_ALL_S = 725, // WebAssemblyInstrFormats.td:61
741 CATCH_LEGACY = 726, // WebAssemblyInstrFormats.td:59
742 CATCH_LEGACY_S = 727, // WebAssemblyInstrFormats.td:61
743 CATCH_REF = 728, // WebAssemblyInstrFormats.td:59
744 CATCH_REF_S = 729, // WebAssemblyInstrFormats.td:61
745 CATCH_S = 730, // WebAssemblyInstrFormats.td:61
746 CEIL_F16x8 = 731, // WebAssemblyInstrFormats.td:59
747 CEIL_F16x8_S = 732, // WebAssemblyInstrFormats.td:61
748 CEIL_F32 = 733, // WebAssemblyInstrFormats.td:59
749 CEIL_F32_S = 734, // WebAssemblyInstrFormats.td:61
750 CEIL_F32x4 = 735, // WebAssemblyInstrFormats.td:59
751 CEIL_F32x4_S = 736, // WebAssemblyInstrFormats.td:61
752 CEIL_F64 = 737, // WebAssemblyInstrFormats.td:59
753 CEIL_F64_S = 738, // WebAssemblyInstrFormats.td:61
754 CEIL_F64x2 = 739, // WebAssemblyInstrFormats.td:59
755 CEIL_F64x2_S = 740, // WebAssemblyInstrFormats.td:61
756 CLZ_I32 = 741, // WebAssemblyInstrFormats.td:59
757 CLZ_I32_S = 742, // WebAssemblyInstrFormats.td:61
758 CLZ_I64 = 743, // WebAssemblyInstrFormats.td:59
759 CLZ_I64_S = 744, // WebAssemblyInstrFormats.td:61
760 CONST_F32 = 745, // WebAssemblyInstrFormats.td:59
761 CONST_F32_S = 746, // WebAssemblyInstrFormats.td:61
762 CONST_F64 = 747, // WebAssemblyInstrFormats.td:59
763 CONST_F64_S = 748, // WebAssemblyInstrFormats.td:61
764 CONST_I32 = 749, // WebAssemblyInstrFormats.td:59
765 CONST_I32_S = 750, // WebAssemblyInstrFormats.td:61
766 CONST_I64 = 751, // WebAssemblyInstrFormats.td:59
767 CONST_I64_S = 752, // WebAssemblyInstrFormats.td:61
768 CONST_V128_F32x4 = 753, // WebAssemblyInstrFormats.td:59
769 CONST_V128_F32x4_S = 754, // WebAssemblyInstrFormats.td:61
770 CONST_V128_F64x2 = 755, // WebAssemblyInstrFormats.td:59
771 CONST_V128_F64x2_S = 756, // WebAssemblyInstrFormats.td:61
772 CONST_V128_I16x8 = 757, // WebAssemblyInstrFormats.td:59
773 CONST_V128_I16x8_S = 758, // WebAssemblyInstrFormats.td:61
774 CONST_V128_I32x4 = 759, // WebAssemblyInstrFormats.td:59
775 CONST_V128_I32x4_S = 760, // WebAssemblyInstrFormats.td:61
776 CONST_V128_I64x2 = 761, // WebAssemblyInstrFormats.td:59
777 CONST_V128_I64x2_S = 762, // WebAssemblyInstrFormats.td:61
778 CONST_V128_I8x16 = 763, // WebAssemblyInstrFormats.td:59
779 CONST_V128_I8x16_S = 764, // WebAssemblyInstrFormats.td:61
780 COPYSIGN_F32 = 765, // WebAssemblyInstrFormats.td:59
781 COPYSIGN_F32_S = 766, // WebAssemblyInstrFormats.td:61
782 COPYSIGN_F64 = 767, // WebAssemblyInstrFormats.td:59
783 COPYSIGN_F64_S = 768, // WebAssemblyInstrFormats.td:61
784 COPY_EXNREF = 769, // WebAssemblyInstrFormats.td:59
785 COPY_EXNREF_S = 770, // WebAssemblyInstrFormats.td:61
786 COPY_EXTERNREF = 771, // WebAssemblyInstrFormats.td:59
787 COPY_EXTERNREF_S = 772, // WebAssemblyInstrFormats.td:61
788 COPY_F32 = 773, // WebAssemblyInstrFormats.td:59
789 COPY_F32_S = 774, // WebAssemblyInstrFormats.td:61
790 COPY_F64 = 775, // WebAssemblyInstrFormats.td:59
791 COPY_F64_S = 776, // WebAssemblyInstrFormats.td:61
792 COPY_FUNCREF = 777, // WebAssemblyInstrFormats.td:59
793 COPY_FUNCREF_S = 778, // WebAssemblyInstrFormats.td:61
794 COPY_I32 = 779, // WebAssemblyInstrFormats.td:59
795 COPY_I32_S = 780, // WebAssemblyInstrFormats.td:61
796 COPY_I64 = 781, // WebAssemblyInstrFormats.td:59
797 COPY_I64_S = 782, // WebAssemblyInstrFormats.td:61
798 COPY_V128 = 783, // WebAssemblyInstrFormats.td:59
799 COPY_V128_S = 784, // WebAssemblyInstrFormats.td:61
800 CTZ_I32 = 785, // WebAssemblyInstrFormats.td:59
801 CTZ_I32_S = 786, // WebAssemblyInstrFormats.td:61
802 CTZ_I64 = 787, // WebAssemblyInstrFormats.td:59
803 CTZ_I64_S = 788, // WebAssemblyInstrFormats.td:61
804 DATA_DROP = 789, // WebAssemblyInstrFormats.td:59
805 DATA_DROP_S = 790, // WebAssemblyInstrFormats.td:61
806 DEBUG_UNREACHABLE = 791, // WebAssemblyInstrFormats.td:59
807 DEBUG_UNREACHABLE_S = 792, // WebAssemblyInstrFormats.td:61
808 DELEGATE = 793, // WebAssemblyInstrFormats.td:59
809 DELEGATE_S = 794, // WebAssemblyInstrFormats.td:61
810 DIV_F16x8 = 795, // WebAssemblyInstrFormats.td:59
811 DIV_F16x8_S = 796, // WebAssemblyInstrFormats.td:61
812 DIV_F32 = 797, // WebAssemblyInstrFormats.td:59
813 DIV_F32_S = 798, // WebAssemblyInstrFormats.td:61
814 DIV_F32x4 = 799, // WebAssemblyInstrFormats.td:59
815 DIV_F32x4_S = 800, // WebAssemblyInstrFormats.td:61
816 DIV_F64 = 801, // WebAssemblyInstrFormats.td:59
817 DIV_F64_S = 802, // WebAssemblyInstrFormats.td:61
818 DIV_F64x2 = 803, // WebAssemblyInstrFormats.td:59
819 DIV_F64x2_S = 804, // WebAssemblyInstrFormats.td:61
820 DIV_S_I32 = 805, // WebAssemblyInstrFormats.td:59
821 DIV_S_I32_S = 806, // WebAssemblyInstrFormats.td:61
822 DIV_S_I64 = 807, // WebAssemblyInstrFormats.td:59
823 DIV_S_I64_S = 808, // WebAssemblyInstrFormats.td:61
824 DIV_U_I32 = 809, // WebAssemblyInstrFormats.td:59
825 DIV_U_I32_S = 810, // WebAssemblyInstrFormats.td:61
826 DIV_U_I64 = 811, // WebAssemblyInstrFormats.td:59
827 DIV_U_I64_S = 812, // WebAssemblyInstrFormats.td:61
828 DOT = 813, // WebAssemblyInstrFormats.td:59
829 DOT_S = 814, // WebAssemblyInstrFormats.td:61
830 DROP_EXNREF = 815, // WebAssemblyInstrFormats.td:59
831 DROP_EXNREF_S = 816, // WebAssemblyInstrFormats.td:61
832 DROP_EXTERNREF = 817, // WebAssemblyInstrFormats.td:59
833 DROP_EXTERNREF_S = 818, // WebAssemblyInstrFormats.td:61
834 DROP_F32 = 819, // WebAssemblyInstrFormats.td:59
835 DROP_F32_S = 820, // WebAssemblyInstrFormats.td:61
836 DROP_F64 = 821, // WebAssemblyInstrFormats.td:59
837 DROP_F64_S = 822, // WebAssemblyInstrFormats.td:61
838 DROP_FUNCREF = 823, // WebAssemblyInstrFormats.td:59
839 DROP_FUNCREF_S = 824, // WebAssemblyInstrFormats.td:61
840 DROP_I32 = 825, // WebAssemblyInstrFormats.td:59
841 DROP_I32_S = 826, // WebAssemblyInstrFormats.td:61
842 DROP_I64 = 827, // WebAssemblyInstrFormats.td:59
843 DROP_I64_S = 828, // WebAssemblyInstrFormats.td:61
844 DROP_V128 = 829, // WebAssemblyInstrFormats.td:59
845 DROP_V128_S = 830, // WebAssemblyInstrFormats.td:61
846 ELSE = 831, // WebAssemblyInstrFormats.td:59
847 ELSE_S = 832, // WebAssemblyInstrFormats.td:61
848 END = 833, // WebAssemblyInstrFormats.td:59
849 END_BLOCK = 834, // WebAssemblyInstrFormats.td:59
850 END_BLOCK_S = 835, // WebAssemblyInstrFormats.td:61
851 END_FUNCTION = 836, // WebAssemblyInstrFormats.td:59
852 END_FUNCTION_S = 837, // WebAssemblyInstrFormats.td:61
853 END_IF = 838, // WebAssemblyInstrFormats.td:59
854 END_IF_S = 839, // WebAssemblyInstrFormats.td:61
855 END_LOOP = 840, // WebAssemblyInstrFormats.td:59
856 END_LOOP_S = 841, // WebAssemblyInstrFormats.td:61
857 END_S = 842, // WebAssemblyInstrFormats.td:61
858 END_TRY = 843, // WebAssemblyInstrFormats.td:59
859 END_TRY_S = 844, // WebAssemblyInstrFormats.td:61
860 END_TRY_TABLE = 845, // WebAssemblyInstrFormats.td:59
861 END_TRY_TABLE_S = 846, // WebAssemblyInstrFormats.td:61
862 EQZ_I32 = 847, // WebAssemblyInstrFormats.td:59
863 EQZ_I32_S = 848, // WebAssemblyInstrFormats.td:61
864 EQZ_I64 = 849, // WebAssemblyInstrFormats.td:59
865 EQZ_I64_S = 850, // WebAssemblyInstrFormats.td:61
866 EQ_F16x8 = 851, // WebAssemblyInstrFormats.td:59
867 EQ_F16x8_S = 852, // WebAssemblyInstrFormats.td:61
868 EQ_F32 = 853, // WebAssemblyInstrFormats.td:59
869 EQ_F32_S = 854, // WebAssemblyInstrFormats.td:61
870 EQ_F32x4 = 855, // WebAssemblyInstrFormats.td:59
871 EQ_F32x4_S = 856, // WebAssemblyInstrFormats.td:61
872 EQ_F64 = 857, // WebAssemblyInstrFormats.td:59
873 EQ_F64_S = 858, // WebAssemblyInstrFormats.td:61
874 EQ_F64x2 = 859, // WebAssemblyInstrFormats.td:59
875 EQ_F64x2_S = 860, // WebAssemblyInstrFormats.td:61
876 EQ_I16x8 = 861, // WebAssemblyInstrFormats.td:59
877 EQ_I16x8_S = 862, // WebAssemblyInstrFormats.td:61
878 EQ_I32 = 863, // WebAssemblyInstrFormats.td:59
879 EQ_I32_S = 864, // WebAssemblyInstrFormats.td:61
880 EQ_I32x4 = 865, // WebAssemblyInstrFormats.td:59
881 EQ_I32x4_S = 866, // WebAssemblyInstrFormats.td:61
882 EQ_I64 = 867, // WebAssemblyInstrFormats.td:59
883 EQ_I64_S = 868, // WebAssemblyInstrFormats.td:61
884 EQ_I64x2 = 869, // WebAssemblyInstrFormats.td:59
885 EQ_I64x2_S = 870, // WebAssemblyInstrFormats.td:61
886 EQ_I8x16 = 871, // WebAssemblyInstrFormats.td:59
887 EQ_I8x16_S = 872, // WebAssemblyInstrFormats.td:61
888 EXTMUL_HIGH_S_I16x8 = 873, // WebAssemblyInstrFormats.td:59
889 EXTMUL_HIGH_S_I16x8_S = 874, // WebAssemblyInstrFormats.td:61
890 EXTMUL_HIGH_S_I32x4 = 875, // WebAssemblyInstrFormats.td:59
891 EXTMUL_HIGH_S_I32x4_S = 876, // WebAssemblyInstrFormats.td:61
892 EXTMUL_HIGH_S_I64x2 = 877, // WebAssemblyInstrFormats.td:59
893 EXTMUL_HIGH_S_I64x2_S = 878, // WebAssemblyInstrFormats.td:61
894 EXTMUL_HIGH_U_I16x8 = 879, // WebAssemblyInstrFormats.td:59
895 EXTMUL_HIGH_U_I16x8_S = 880, // WebAssemblyInstrFormats.td:61
896 EXTMUL_HIGH_U_I32x4 = 881, // WebAssemblyInstrFormats.td:59
897 EXTMUL_HIGH_U_I32x4_S = 882, // WebAssemblyInstrFormats.td:61
898 EXTMUL_HIGH_U_I64x2 = 883, // WebAssemblyInstrFormats.td:59
899 EXTMUL_HIGH_U_I64x2_S = 884, // WebAssemblyInstrFormats.td:61
900 EXTMUL_LOW_S_I16x8 = 885, // WebAssemblyInstrFormats.td:59
901 EXTMUL_LOW_S_I16x8_S = 886, // WebAssemblyInstrFormats.td:61
902 EXTMUL_LOW_S_I32x4 = 887, // WebAssemblyInstrFormats.td:59
903 EXTMUL_LOW_S_I32x4_S = 888, // WebAssemblyInstrFormats.td:61
904 EXTMUL_LOW_S_I64x2 = 889, // WebAssemblyInstrFormats.td:59
905 EXTMUL_LOW_S_I64x2_S = 890, // WebAssemblyInstrFormats.td:61
906 EXTMUL_LOW_U_I16x8 = 891, // WebAssemblyInstrFormats.td:59
907 EXTMUL_LOW_U_I16x8_S = 892, // WebAssemblyInstrFormats.td:61
908 EXTMUL_LOW_U_I32x4 = 893, // WebAssemblyInstrFormats.td:59
909 EXTMUL_LOW_U_I32x4_S = 894, // WebAssemblyInstrFormats.td:61
910 EXTMUL_LOW_U_I64x2 = 895, // WebAssemblyInstrFormats.td:59
911 EXTMUL_LOW_U_I64x2_S = 896, // WebAssemblyInstrFormats.td:61
912 EXTRACT_LANE_F16x8 = 897, // WebAssemblyInstrFormats.td:59
913 EXTRACT_LANE_F16x8_S = 898, // WebAssemblyInstrFormats.td:61
914 EXTRACT_LANE_F32x4 = 899, // WebAssemblyInstrFormats.td:59
915 EXTRACT_LANE_F32x4_S = 900, // WebAssemblyInstrFormats.td:61
916 EXTRACT_LANE_F64x2 = 901, // WebAssemblyInstrFormats.td:59
917 EXTRACT_LANE_F64x2_S = 902, // WebAssemblyInstrFormats.td:61
918 EXTRACT_LANE_I16x8_s = 903, // WebAssemblyInstrFormats.td:59
919 EXTRACT_LANE_I16x8_s_S = 904, // WebAssemblyInstrFormats.td:61
920 EXTRACT_LANE_I16x8_u = 905, // WebAssemblyInstrFormats.td:59
921 EXTRACT_LANE_I16x8_u_S = 906, // WebAssemblyInstrFormats.td:61
922 EXTRACT_LANE_I32x4 = 907, // WebAssemblyInstrFormats.td:59
923 EXTRACT_LANE_I32x4_S = 908, // WebAssemblyInstrFormats.td:61
924 EXTRACT_LANE_I64x2 = 909, // WebAssemblyInstrFormats.td:59
925 EXTRACT_LANE_I64x2_S = 910, // WebAssemblyInstrFormats.td:61
926 EXTRACT_LANE_I8x16_s = 911, // WebAssemblyInstrFormats.td:59
927 EXTRACT_LANE_I8x16_s_S = 912, // WebAssemblyInstrFormats.td:61
928 EXTRACT_LANE_I8x16_u = 913, // WebAssemblyInstrFormats.td:59
929 EXTRACT_LANE_I8x16_u_S = 914, // WebAssemblyInstrFormats.td:61
930 F32_CONVERT_S_I32 = 915, // WebAssemblyInstrFormats.td:59
931 F32_CONVERT_S_I32_S = 916, // WebAssemblyInstrFormats.td:61
932 F32_CONVERT_S_I64 = 917, // WebAssemblyInstrFormats.td:59
933 F32_CONVERT_S_I64_S = 918, // WebAssemblyInstrFormats.td:61
934 F32_CONVERT_U_I32 = 919, // WebAssemblyInstrFormats.td:59
935 F32_CONVERT_U_I32_S = 920, // WebAssemblyInstrFormats.td:61
936 F32_CONVERT_U_I64 = 921, // WebAssemblyInstrFormats.td:59
937 F32_CONVERT_U_I64_S = 922, // WebAssemblyInstrFormats.td:61
938 F32_DEMOTE_F64 = 923, // WebAssemblyInstrFormats.td:59
939 F32_DEMOTE_F64_S = 924, // WebAssemblyInstrFormats.td:61
940 F32_REINTERPRET_I32 = 925, // WebAssemblyInstrFormats.td:59
941 F32_REINTERPRET_I32_S = 926, // WebAssemblyInstrFormats.td:61
942 F64_CONVERT_S_I32 = 927, // WebAssemblyInstrFormats.td:59
943 F64_CONVERT_S_I32_S = 928, // WebAssemblyInstrFormats.td:61
944 F64_CONVERT_S_I64 = 929, // WebAssemblyInstrFormats.td:59
945 F64_CONVERT_S_I64_S = 930, // WebAssemblyInstrFormats.td:61
946 F64_CONVERT_U_I32 = 931, // WebAssemblyInstrFormats.td:59
947 F64_CONVERT_U_I32_S = 932, // WebAssemblyInstrFormats.td:61
948 F64_CONVERT_U_I64 = 933, // WebAssemblyInstrFormats.td:59
949 F64_CONVERT_U_I64_S = 934, // WebAssemblyInstrFormats.td:61
950 F64_PROMOTE_F32 = 935, // WebAssemblyInstrFormats.td:59
951 F64_PROMOTE_F32_S = 936, // WebAssemblyInstrFormats.td:61
952 F64_REINTERPRET_I64 = 937, // WebAssemblyInstrFormats.td:59
953 F64_REINTERPRET_I64_S = 938, // WebAssemblyInstrFormats.td:61
954 FALLTHROUGH_RETURN = 939, // WebAssemblyInstrFormats.td:59
955 FALLTHROUGH_RETURN_S = 940, // WebAssemblyInstrFormats.td:61
956 FLOOR_F16x8 = 941, // WebAssemblyInstrFormats.td:59
957 FLOOR_F16x8_S = 942, // WebAssemblyInstrFormats.td:61
958 FLOOR_F32 = 943, // WebAssemblyInstrFormats.td:59
959 FLOOR_F32_S = 944, // WebAssemblyInstrFormats.td:61
960 FLOOR_F32x4 = 945, // WebAssemblyInstrFormats.td:59
961 FLOOR_F32x4_S = 946, // WebAssemblyInstrFormats.td:61
962 FLOOR_F64 = 947, // WebAssemblyInstrFormats.td:59
963 FLOOR_F64_S = 948, // WebAssemblyInstrFormats.td:61
964 FLOOR_F64x2 = 949, // WebAssemblyInstrFormats.td:59
965 FLOOR_F64x2_S = 950, // WebAssemblyInstrFormats.td:61
966 FP_TO_SINT_I32_F32 = 951, // WebAssemblyInstrFormats.td:59
967 FP_TO_SINT_I32_F32_S = 952, // WebAssemblyInstrFormats.td:61
968 FP_TO_SINT_I32_F64 = 953, // WebAssemblyInstrFormats.td:59
969 FP_TO_SINT_I32_F64_S = 954, // WebAssemblyInstrFormats.td:61
970 FP_TO_SINT_I64_F32 = 955, // WebAssemblyInstrFormats.td:59
971 FP_TO_SINT_I64_F32_S = 956, // WebAssemblyInstrFormats.td:61
972 FP_TO_SINT_I64_F64 = 957, // WebAssemblyInstrFormats.td:59
973 FP_TO_SINT_I64_F64_S = 958, // WebAssemblyInstrFormats.td:61
974 FP_TO_UINT_I32_F32 = 959, // WebAssemblyInstrFormats.td:59
975 FP_TO_UINT_I32_F32_S = 960, // WebAssemblyInstrFormats.td:61
976 FP_TO_UINT_I32_F64 = 961, // WebAssemblyInstrFormats.td:59
977 FP_TO_UINT_I32_F64_S = 962, // WebAssemblyInstrFormats.td:61
978 FP_TO_UINT_I64_F32 = 963, // WebAssemblyInstrFormats.td:59
979 FP_TO_UINT_I64_F32_S = 964, // WebAssemblyInstrFormats.td:61
980 FP_TO_UINT_I64_F64 = 965, // WebAssemblyInstrFormats.td:59
981 FP_TO_UINT_I64_F64_S = 966, // WebAssemblyInstrFormats.td:61
982 GE_F16x8 = 967, // WebAssemblyInstrFormats.td:59
983 GE_F16x8_S = 968, // WebAssemblyInstrFormats.td:61
984 GE_F32 = 969, // WebAssemblyInstrFormats.td:59
985 GE_F32_S = 970, // WebAssemblyInstrFormats.td:61
986 GE_F32x4 = 971, // WebAssemblyInstrFormats.td:59
987 GE_F32x4_S = 972, // WebAssemblyInstrFormats.td:61
988 GE_F64 = 973, // WebAssemblyInstrFormats.td:59
989 GE_F64_S = 974, // WebAssemblyInstrFormats.td:61
990 GE_F64x2 = 975, // WebAssemblyInstrFormats.td:59
991 GE_F64x2_S = 976, // WebAssemblyInstrFormats.td:61
992 GE_S_I16x8 = 977, // WebAssemblyInstrFormats.td:59
993 GE_S_I16x8_S = 978, // WebAssemblyInstrFormats.td:61
994 GE_S_I32 = 979, // WebAssemblyInstrFormats.td:59
995 GE_S_I32_S = 980, // WebAssemblyInstrFormats.td:61
996 GE_S_I32x4 = 981, // WebAssemblyInstrFormats.td:59
997 GE_S_I32x4_S = 982, // WebAssemblyInstrFormats.td:61
998 GE_S_I64 = 983, // WebAssemblyInstrFormats.td:59
999 GE_S_I64_S = 984, // WebAssemblyInstrFormats.td:61
1000 GE_S_I64x2 = 985, // WebAssemblyInstrFormats.td:59
1001 GE_S_I64x2_S = 986, // WebAssemblyInstrFormats.td:61
1002 GE_S_I8x16 = 987, // WebAssemblyInstrFormats.td:59
1003 GE_S_I8x16_S = 988, // WebAssemblyInstrFormats.td:61
1004 GE_U_I16x8 = 989, // WebAssemblyInstrFormats.td:59
1005 GE_U_I16x8_S = 990, // WebAssemblyInstrFormats.td:61
1006 GE_U_I32 = 991, // WebAssemblyInstrFormats.td:59
1007 GE_U_I32_S = 992, // WebAssemblyInstrFormats.td:61
1008 GE_U_I32x4 = 993, // WebAssemblyInstrFormats.td:59
1009 GE_U_I32x4_S = 994, // WebAssemblyInstrFormats.td:61
1010 GE_U_I64 = 995, // WebAssemblyInstrFormats.td:59
1011 GE_U_I64_S = 996, // WebAssemblyInstrFormats.td:61
1012 GE_U_I8x16 = 997, // WebAssemblyInstrFormats.td:59
1013 GE_U_I8x16_S = 998, // WebAssemblyInstrFormats.td:61
1014 GLOBAL_GET_EXNREF = 999, // WebAssemblyInstrFormats.td:59
1015 GLOBAL_GET_EXNREF_S = 1000, // WebAssemblyInstrFormats.td:61
1016 GLOBAL_GET_EXTERNREF = 1001, // WebAssemblyInstrFormats.td:59
1017 GLOBAL_GET_EXTERNREF_S = 1002, // WebAssemblyInstrFormats.td:61
1018 GLOBAL_GET_F32 = 1003, // WebAssemblyInstrFormats.td:59
1019 GLOBAL_GET_F32_S = 1004, // WebAssemblyInstrFormats.td:61
1020 GLOBAL_GET_F64 = 1005, // WebAssemblyInstrFormats.td:59
1021 GLOBAL_GET_F64_S = 1006, // WebAssemblyInstrFormats.td:61
1022 GLOBAL_GET_FUNCREF = 1007, // WebAssemblyInstrFormats.td:59
1023 GLOBAL_GET_FUNCREF_S = 1008, // WebAssemblyInstrFormats.td:61
1024 GLOBAL_GET_I32 = 1009, // WebAssemblyInstrFormats.td:59
1025 GLOBAL_GET_I32_S = 1010, // WebAssemblyInstrFormats.td:61
1026 GLOBAL_GET_I64 = 1011, // WebAssemblyInstrFormats.td:59
1027 GLOBAL_GET_I64_S = 1012, // WebAssemblyInstrFormats.td:61
1028 GLOBAL_GET_V128 = 1013, // WebAssemblyInstrFormats.td:59
1029 GLOBAL_GET_V128_S = 1014, // WebAssemblyInstrFormats.td:61
1030 GLOBAL_SET_EXNREF = 1015, // WebAssemblyInstrFormats.td:59
1031 GLOBAL_SET_EXNREF_S = 1016, // WebAssemblyInstrFormats.td:61
1032 GLOBAL_SET_EXTERNREF = 1017, // WebAssemblyInstrFormats.td:59
1033 GLOBAL_SET_EXTERNREF_S = 1018, // WebAssemblyInstrFormats.td:61
1034 GLOBAL_SET_F32 = 1019, // WebAssemblyInstrFormats.td:59
1035 GLOBAL_SET_F32_S = 1020, // WebAssemblyInstrFormats.td:61
1036 GLOBAL_SET_F64 = 1021, // WebAssemblyInstrFormats.td:59
1037 GLOBAL_SET_F64_S = 1022, // WebAssemblyInstrFormats.td:61
1038 GLOBAL_SET_FUNCREF = 1023, // WebAssemblyInstrFormats.td:59
1039 GLOBAL_SET_FUNCREF_S = 1024, // WebAssemblyInstrFormats.td:61
1040 GLOBAL_SET_I32 = 1025, // WebAssemblyInstrFormats.td:59
1041 GLOBAL_SET_I32_S = 1026, // WebAssemblyInstrFormats.td:61
1042 GLOBAL_SET_I64 = 1027, // WebAssemblyInstrFormats.td:59
1043 GLOBAL_SET_I64_S = 1028, // WebAssemblyInstrFormats.td:61
1044 GLOBAL_SET_V128 = 1029, // WebAssemblyInstrFormats.td:59
1045 GLOBAL_SET_V128_S = 1030, // WebAssemblyInstrFormats.td:61
1046 GT_F16x8 = 1031, // WebAssemblyInstrFormats.td:59
1047 GT_F16x8_S = 1032, // WebAssemblyInstrFormats.td:61
1048 GT_F32 = 1033, // WebAssemblyInstrFormats.td:59
1049 GT_F32_S = 1034, // WebAssemblyInstrFormats.td:61
1050 GT_F32x4 = 1035, // WebAssemblyInstrFormats.td:59
1051 GT_F32x4_S = 1036, // WebAssemblyInstrFormats.td:61
1052 GT_F64 = 1037, // WebAssemblyInstrFormats.td:59
1053 GT_F64_S = 1038, // WebAssemblyInstrFormats.td:61
1054 GT_F64x2 = 1039, // WebAssemblyInstrFormats.td:59
1055 GT_F64x2_S = 1040, // WebAssemblyInstrFormats.td:61
1056 GT_S_I16x8 = 1041, // WebAssemblyInstrFormats.td:59
1057 GT_S_I16x8_S = 1042, // WebAssemblyInstrFormats.td:61
1058 GT_S_I32 = 1043, // WebAssemblyInstrFormats.td:59
1059 GT_S_I32_S = 1044, // WebAssemblyInstrFormats.td:61
1060 GT_S_I32x4 = 1045, // WebAssemblyInstrFormats.td:59
1061 GT_S_I32x4_S = 1046, // WebAssemblyInstrFormats.td:61
1062 GT_S_I64 = 1047, // WebAssemblyInstrFormats.td:59
1063 GT_S_I64_S = 1048, // WebAssemblyInstrFormats.td:61
1064 GT_S_I64x2 = 1049, // WebAssemblyInstrFormats.td:59
1065 GT_S_I64x2_S = 1050, // WebAssemblyInstrFormats.td:61
1066 GT_S_I8x16 = 1051, // WebAssemblyInstrFormats.td:59
1067 GT_S_I8x16_S = 1052, // WebAssemblyInstrFormats.td:61
1068 GT_U_I16x8 = 1053, // WebAssemblyInstrFormats.td:59
1069 GT_U_I16x8_S = 1054, // WebAssemblyInstrFormats.td:61
1070 GT_U_I32 = 1055, // WebAssemblyInstrFormats.td:59
1071 GT_U_I32_S = 1056, // WebAssemblyInstrFormats.td:61
1072 GT_U_I32x4 = 1057, // WebAssemblyInstrFormats.td:59
1073 GT_U_I32x4_S = 1058, // WebAssemblyInstrFormats.td:61
1074 GT_U_I64 = 1059, // WebAssemblyInstrFormats.td:59
1075 GT_U_I64_S = 1060, // WebAssemblyInstrFormats.td:61
1076 GT_U_I8x16 = 1061, // WebAssemblyInstrFormats.td:59
1077 GT_U_I8x16_S = 1062, // WebAssemblyInstrFormats.td:61
1078 I32_EXTEND16_S_I32 = 1063, // WebAssemblyInstrFormats.td:59
1079 I32_EXTEND16_S_I32_S = 1064, // WebAssemblyInstrFormats.td:61
1080 I32_EXTEND8_S_I32 = 1065, // WebAssemblyInstrFormats.td:59
1081 I32_EXTEND8_S_I32_S = 1066, // WebAssemblyInstrFormats.td:61
1082 I32_REINTERPRET_F32 = 1067, // WebAssemblyInstrFormats.td:59
1083 I32_REINTERPRET_F32_S = 1068, // WebAssemblyInstrFormats.td:61
1084 I32_TRUNC_S_F32 = 1069, // WebAssemblyInstrFormats.td:59
1085 I32_TRUNC_S_F32_S = 1070, // WebAssemblyInstrFormats.td:61
1086 I32_TRUNC_S_F64 = 1071, // WebAssemblyInstrFormats.td:59
1087 I32_TRUNC_S_F64_S = 1072, // WebAssemblyInstrFormats.td:61
1088 I32_TRUNC_S_SAT_F32 = 1073, // WebAssemblyInstrFormats.td:59
1089 I32_TRUNC_S_SAT_F32_S = 1074, // WebAssemblyInstrFormats.td:61
1090 I32_TRUNC_S_SAT_F64 = 1075, // WebAssemblyInstrFormats.td:59
1091 I32_TRUNC_S_SAT_F64_S = 1076, // WebAssemblyInstrFormats.td:61
1092 I32_TRUNC_U_F32 = 1077, // WebAssemblyInstrFormats.td:59
1093 I32_TRUNC_U_F32_S = 1078, // WebAssemblyInstrFormats.td:61
1094 I32_TRUNC_U_F64 = 1079, // WebAssemblyInstrFormats.td:59
1095 I32_TRUNC_U_F64_S = 1080, // WebAssemblyInstrFormats.td:61
1096 I32_TRUNC_U_SAT_F32 = 1081, // WebAssemblyInstrFormats.td:59
1097 I32_TRUNC_U_SAT_F32_S = 1082, // WebAssemblyInstrFormats.td:61
1098 I32_TRUNC_U_SAT_F64 = 1083, // WebAssemblyInstrFormats.td:59
1099 I32_TRUNC_U_SAT_F64_S = 1084, // WebAssemblyInstrFormats.td:61
1100 I32_WRAP_I64 = 1085, // WebAssemblyInstrFormats.td:59
1101 I32_WRAP_I64_S = 1086, // WebAssemblyInstrFormats.td:61
1102 I64_ADD128 = 1087, // WebAssemblyInstrFormats.td:59
1103 I64_ADD128_S = 1088, // WebAssemblyInstrFormats.td:61
1104 I64_EXTEND16_S_I64 = 1089, // WebAssemblyInstrFormats.td:59
1105 I64_EXTEND16_S_I64_S = 1090, // WebAssemblyInstrFormats.td:61
1106 I64_EXTEND32_S_I64 = 1091, // WebAssemblyInstrFormats.td:59
1107 I64_EXTEND32_S_I64_S = 1092, // WebAssemblyInstrFormats.td:61
1108 I64_EXTEND8_S_I64 = 1093, // WebAssemblyInstrFormats.td:59
1109 I64_EXTEND8_S_I64_S = 1094, // WebAssemblyInstrFormats.td:61
1110 I64_EXTEND_S_I32 = 1095, // WebAssemblyInstrFormats.td:59
1111 I64_EXTEND_S_I32_S = 1096, // WebAssemblyInstrFormats.td:61
1112 I64_EXTEND_U_I32 = 1097, // WebAssemblyInstrFormats.td:59
1113 I64_EXTEND_U_I32_S = 1098, // WebAssemblyInstrFormats.td:61
1114 I64_MUL_WIDE_S = 1099, // WebAssemblyInstrFormats.td:59
1115 I64_MUL_WIDE_S_S = 1100, // WebAssemblyInstrFormats.td:61
1116 I64_MUL_WIDE_U = 1101, // WebAssemblyInstrFormats.td:59
1117 I64_MUL_WIDE_U_S = 1102, // WebAssemblyInstrFormats.td:61
1118 I64_REINTERPRET_F64 = 1103, // WebAssemblyInstrFormats.td:59
1119 I64_REINTERPRET_F64_S = 1104, // WebAssemblyInstrFormats.td:61
1120 I64_SUB128 = 1105, // WebAssemblyInstrFormats.td:59
1121 I64_SUB128_S = 1106, // WebAssemblyInstrFormats.td:61
1122 I64_TRUNC_S_F32 = 1107, // WebAssemblyInstrFormats.td:59
1123 I64_TRUNC_S_F32_S = 1108, // WebAssemblyInstrFormats.td:61
1124 I64_TRUNC_S_F64 = 1109, // WebAssemblyInstrFormats.td:59
1125 I64_TRUNC_S_F64_S = 1110, // WebAssemblyInstrFormats.td:61
1126 I64_TRUNC_S_SAT_F32 = 1111, // WebAssemblyInstrFormats.td:59
1127 I64_TRUNC_S_SAT_F32_S = 1112, // WebAssemblyInstrFormats.td:61
1128 I64_TRUNC_S_SAT_F64 = 1113, // WebAssemblyInstrFormats.td:59
1129 I64_TRUNC_S_SAT_F64_S = 1114, // WebAssemblyInstrFormats.td:61
1130 I64_TRUNC_U_F32 = 1115, // WebAssemblyInstrFormats.td:59
1131 I64_TRUNC_U_F32_S = 1116, // WebAssemblyInstrFormats.td:61
1132 I64_TRUNC_U_F64 = 1117, // WebAssemblyInstrFormats.td:59
1133 I64_TRUNC_U_F64_S = 1118, // WebAssemblyInstrFormats.td:61
1134 I64_TRUNC_U_SAT_F32 = 1119, // WebAssemblyInstrFormats.td:59
1135 I64_TRUNC_U_SAT_F32_S = 1120, // WebAssemblyInstrFormats.td:61
1136 I64_TRUNC_U_SAT_F64 = 1121, // WebAssemblyInstrFormats.td:59
1137 I64_TRUNC_U_SAT_F64_S = 1122, // WebAssemblyInstrFormats.td:61
1138 IF = 1123, // WebAssemblyInstrFormats.td:59
1139 IF_S = 1124, // WebAssemblyInstrFormats.td:61
1140 LANESELECT_I16x8 = 1125, // WebAssemblyInstrFormats.td:59
1141 LANESELECT_I16x8_S = 1126, // WebAssemblyInstrFormats.td:61
1142 LANESELECT_I32x4 = 1127, // WebAssemblyInstrFormats.td:59
1143 LANESELECT_I32x4_S = 1128, // WebAssemblyInstrFormats.td:61
1144 LANESELECT_I64x2 = 1129, // WebAssemblyInstrFormats.td:59
1145 LANESELECT_I64x2_S = 1130, // WebAssemblyInstrFormats.td:61
1146 LANESELECT_I8x16 = 1131, // WebAssemblyInstrFormats.td:59
1147 LANESELECT_I8x16_S = 1132, // WebAssemblyInstrFormats.td:61
1148 LE_F16x8 = 1133, // WebAssemblyInstrFormats.td:59
1149 LE_F16x8_S = 1134, // WebAssemblyInstrFormats.td:61
1150 LE_F32 = 1135, // WebAssemblyInstrFormats.td:59
1151 LE_F32_S = 1136, // WebAssemblyInstrFormats.td:61
1152 LE_F32x4 = 1137, // WebAssemblyInstrFormats.td:59
1153 LE_F32x4_S = 1138, // WebAssemblyInstrFormats.td:61
1154 LE_F64 = 1139, // WebAssemblyInstrFormats.td:59
1155 LE_F64_S = 1140, // WebAssemblyInstrFormats.td:61
1156 LE_F64x2 = 1141, // WebAssemblyInstrFormats.td:59
1157 LE_F64x2_S = 1142, // WebAssemblyInstrFormats.td:61
1158 LE_S_I16x8 = 1143, // WebAssemblyInstrFormats.td:59
1159 LE_S_I16x8_S = 1144, // WebAssemblyInstrFormats.td:61
1160 LE_S_I32 = 1145, // WebAssemblyInstrFormats.td:59
1161 LE_S_I32_S = 1146, // WebAssemblyInstrFormats.td:61
1162 LE_S_I32x4 = 1147, // WebAssemblyInstrFormats.td:59
1163 LE_S_I32x4_S = 1148, // WebAssemblyInstrFormats.td:61
1164 LE_S_I64 = 1149, // WebAssemblyInstrFormats.td:59
1165 LE_S_I64_S = 1150, // WebAssemblyInstrFormats.td:61
1166 LE_S_I64x2 = 1151, // WebAssemblyInstrFormats.td:59
1167 LE_S_I64x2_S = 1152, // WebAssemblyInstrFormats.td:61
1168 LE_S_I8x16 = 1153, // WebAssemblyInstrFormats.td:59
1169 LE_S_I8x16_S = 1154, // WebAssemblyInstrFormats.td:61
1170 LE_U_I16x8 = 1155, // WebAssemblyInstrFormats.td:59
1171 LE_U_I16x8_S = 1156, // WebAssemblyInstrFormats.td:61
1172 LE_U_I32 = 1157, // WebAssemblyInstrFormats.td:59
1173 LE_U_I32_S = 1158, // WebAssemblyInstrFormats.td:61
1174 LE_U_I32x4 = 1159, // WebAssemblyInstrFormats.td:59
1175 LE_U_I32x4_S = 1160, // WebAssemblyInstrFormats.td:61
1176 LE_U_I64 = 1161, // WebAssemblyInstrFormats.td:59
1177 LE_U_I64_S = 1162, // WebAssemblyInstrFormats.td:61
1178 LE_U_I8x16 = 1163, // WebAssemblyInstrFormats.td:59
1179 LE_U_I8x16_S = 1164, // WebAssemblyInstrFormats.td:61
1180 LOAD16_SPLAT_A32 = 1165, // WebAssemblyInstrFormats.td:59
1181 LOAD16_SPLAT_A32_S = 1166, // WebAssemblyInstrFormats.td:61
1182 LOAD16_SPLAT_A64 = 1167, // WebAssemblyInstrFormats.td:59
1183 LOAD16_SPLAT_A64_S = 1168, // WebAssemblyInstrFormats.td:61
1184 LOAD16_S_I32_A32 = 1169, // WebAssemblyInstrFormats.td:59
1185 LOAD16_S_I32_A32_S = 1170, // WebAssemblyInstrFormats.td:61
1186 LOAD16_S_I32_A64 = 1171, // WebAssemblyInstrFormats.td:59
1187 LOAD16_S_I32_A64_S = 1172, // WebAssemblyInstrFormats.td:61
1188 LOAD16_S_I64_A32 = 1173, // WebAssemblyInstrFormats.td:59
1189 LOAD16_S_I64_A32_S = 1174, // WebAssemblyInstrFormats.td:61
1190 LOAD16_S_I64_A64 = 1175, // WebAssemblyInstrFormats.td:59
1191 LOAD16_S_I64_A64_S = 1176, // WebAssemblyInstrFormats.td:61
1192 LOAD16_U_I32_A32 = 1177, // WebAssemblyInstrFormats.td:59
1193 LOAD16_U_I32_A32_S = 1178, // WebAssemblyInstrFormats.td:61
1194 LOAD16_U_I32_A64 = 1179, // WebAssemblyInstrFormats.td:59
1195 LOAD16_U_I32_A64_S = 1180, // WebAssemblyInstrFormats.td:61
1196 LOAD16_U_I64_A32 = 1181, // WebAssemblyInstrFormats.td:59
1197 LOAD16_U_I64_A32_S = 1182, // WebAssemblyInstrFormats.td:61
1198 LOAD16_U_I64_A64 = 1183, // WebAssemblyInstrFormats.td:59
1199 LOAD16_U_I64_A64_S = 1184, // WebAssemblyInstrFormats.td:61
1200 LOAD32_SPLAT_A32 = 1185, // WebAssemblyInstrFormats.td:59
1201 LOAD32_SPLAT_A32_S = 1186, // WebAssemblyInstrFormats.td:61
1202 LOAD32_SPLAT_A64 = 1187, // WebAssemblyInstrFormats.td:59
1203 LOAD32_SPLAT_A64_S = 1188, // WebAssemblyInstrFormats.td:61
1204 LOAD32_S_I64_A32 = 1189, // WebAssemblyInstrFormats.td:59
1205 LOAD32_S_I64_A32_S = 1190, // WebAssemblyInstrFormats.td:61
1206 LOAD32_S_I64_A64 = 1191, // WebAssemblyInstrFormats.td:59
1207 LOAD32_S_I64_A64_S = 1192, // WebAssemblyInstrFormats.td:61
1208 LOAD32_U_I64_A32 = 1193, // WebAssemblyInstrFormats.td:59
1209 LOAD32_U_I64_A32_S = 1194, // WebAssemblyInstrFormats.td:61
1210 LOAD32_U_I64_A64 = 1195, // WebAssemblyInstrFormats.td:59
1211 LOAD32_U_I64_A64_S = 1196, // WebAssemblyInstrFormats.td:61
1212 LOAD64_SPLAT_A32 = 1197, // WebAssemblyInstrFormats.td:59
1213 LOAD64_SPLAT_A32_S = 1198, // WebAssemblyInstrFormats.td:61
1214 LOAD64_SPLAT_A64 = 1199, // WebAssemblyInstrFormats.td:59
1215 LOAD64_SPLAT_A64_S = 1200, // WebAssemblyInstrFormats.td:61
1216 LOAD8_SPLAT_A32 = 1201, // WebAssemblyInstrFormats.td:59
1217 LOAD8_SPLAT_A32_S = 1202, // WebAssemblyInstrFormats.td:61
1218 LOAD8_SPLAT_A64 = 1203, // WebAssemblyInstrFormats.td:59
1219 LOAD8_SPLAT_A64_S = 1204, // WebAssemblyInstrFormats.td:61
1220 LOAD8_S_I32_A32 = 1205, // WebAssemblyInstrFormats.td:59
1221 LOAD8_S_I32_A32_S = 1206, // WebAssemblyInstrFormats.td:61
1222 LOAD8_S_I32_A64 = 1207, // WebAssemblyInstrFormats.td:59
1223 LOAD8_S_I32_A64_S = 1208, // WebAssemblyInstrFormats.td:61
1224 LOAD8_S_I64_A32 = 1209, // WebAssemblyInstrFormats.td:59
1225 LOAD8_S_I64_A32_S = 1210, // WebAssemblyInstrFormats.td:61
1226 LOAD8_S_I64_A64 = 1211, // WebAssemblyInstrFormats.td:59
1227 LOAD8_S_I64_A64_S = 1212, // WebAssemblyInstrFormats.td:61
1228 LOAD8_U_I32_A32 = 1213, // WebAssemblyInstrFormats.td:59
1229 LOAD8_U_I32_A32_S = 1214, // WebAssemblyInstrFormats.td:61
1230 LOAD8_U_I32_A64 = 1215, // WebAssemblyInstrFormats.td:59
1231 LOAD8_U_I32_A64_S = 1216, // WebAssemblyInstrFormats.td:61
1232 LOAD8_U_I64_A32 = 1217, // WebAssemblyInstrFormats.td:59
1233 LOAD8_U_I64_A32_S = 1218, // WebAssemblyInstrFormats.td:61
1234 LOAD8_U_I64_A64 = 1219, // WebAssemblyInstrFormats.td:59
1235 LOAD8_U_I64_A64_S = 1220, // WebAssemblyInstrFormats.td:61
1236 LOAD_EXTEND_S_I16x8_A32 = 1221, // WebAssemblyInstrFormats.td:59
1237 LOAD_EXTEND_S_I16x8_A32_S = 1222, // WebAssemblyInstrFormats.td:61
1238 LOAD_EXTEND_S_I16x8_A64 = 1223, // WebAssemblyInstrFormats.td:59
1239 LOAD_EXTEND_S_I16x8_A64_S = 1224, // WebAssemblyInstrFormats.td:61
1240 LOAD_EXTEND_S_I32x4_A32 = 1225, // WebAssemblyInstrFormats.td:59
1241 LOAD_EXTEND_S_I32x4_A32_S = 1226, // WebAssemblyInstrFormats.td:61
1242 LOAD_EXTEND_S_I32x4_A64 = 1227, // WebAssemblyInstrFormats.td:59
1243 LOAD_EXTEND_S_I32x4_A64_S = 1228, // WebAssemblyInstrFormats.td:61
1244 LOAD_EXTEND_S_I64x2_A32 = 1229, // WebAssemblyInstrFormats.td:59
1245 LOAD_EXTEND_S_I64x2_A32_S = 1230, // WebAssemblyInstrFormats.td:61
1246 LOAD_EXTEND_S_I64x2_A64 = 1231, // WebAssemblyInstrFormats.td:59
1247 LOAD_EXTEND_S_I64x2_A64_S = 1232, // WebAssemblyInstrFormats.td:61
1248 LOAD_EXTEND_U_I16x8_A32 = 1233, // WebAssemblyInstrFormats.td:59
1249 LOAD_EXTEND_U_I16x8_A32_S = 1234, // WebAssemblyInstrFormats.td:61
1250 LOAD_EXTEND_U_I16x8_A64 = 1235, // WebAssemblyInstrFormats.td:59
1251 LOAD_EXTEND_U_I16x8_A64_S = 1236, // WebAssemblyInstrFormats.td:61
1252 LOAD_EXTEND_U_I32x4_A32 = 1237, // WebAssemblyInstrFormats.td:59
1253 LOAD_EXTEND_U_I32x4_A32_S = 1238, // WebAssemblyInstrFormats.td:61
1254 LOAD_EXTEND_U_I32x4_A64 = 1239, // WebAssemblyInstrFormats.td:59
1255 LOAD_EXTEND_U_I32x4_A64_S = 1240, // WebAssemblyInstrFormats.td:61
1256 LOAD_EXTEND_U_I64x2_A32 = 1241, // WebAssemblyInstrFormats.td:59
1257 LOAD_EXTEND_U_I64x2_A32_S = 1242, // WebAssemblyInstrFormats.td:61
1258 LOAD_EXTEND_U_I64x2_A64 = 1243, // WebAssemblyInstrFormats.td:59
1259 LOAD_EXTEND_U_I64x2_A64_S = 1244, // WebAssemblyInstrFormats.td:61
1260 LOAD_F16_F32_A32 = 1245, // WebAssemblyInstrFormats.td:59
1261 LOAD_F16_F32_A32_S = 1246, // WebAssemblyInstrFormats.td:61
1262 LOAD_F16_F32_A64 = 1247, // WebAssemblyInstrFormats.td:59
1263 LOAD_F16_F32_A64_S = 1248, // WebAssemblyInstrFormats.td:61
1264 LOAD_F32_A32 = 1249, // WebAssemblyInstrFormats.td:59
1265 LOAD_F32_A32_S = 1250, // WebAssemblyInstrFormats.td:61
1266 LOAD_F32_A64 = 1251, // WebAssemblyInstrFormats.td:59
1267 LOAD_F32_A64_S = 1252, // WebAssemblyInstrFormats.td:61
1268 LOAD_F64_A32 = 1253, // WebAssemblyInstrFormats.td:59
1269 LOAD_F64_A32_S = 1254, // WebAssemblyInstrFormats.td:61
1270 LOAD_F64_A64 = 1255, // WebAssemblyInstrFormats.td:59
1271 LOAD_F64_A64_S = 1256, // WebAssemblyInstrFormats.td:61
1272 LOAD_I32_A32 = 1257, // WebAssemblyInstrFormats.td:59
1273 LOAD_I32_A32_S = 1258, // WebAssemblyInstrFormats.td:61
1274 LOAD_I32_A64 = 1259, // WebAssemblyInstrFormats.td:59
1275 LOAD_I32_A64_S = 1260, // WebAssemblyInstrFormats.td:61
1276 LOAD_I64_A32 = 1261, // WebAssemblyInstrFormats.td:59
1277 LOAD_I64_A32_S = 1262, // WebAssemblyInstrFormats.td:61
1278 LOAD_I64_A64 = 1263, // WebAssemblyInstrFormats.td:59
1279 LOAD_I64_A64_S = 1264, // WebAssemblyInstrFormats.td:61
1280 LOAD_LANE_16_A32 = 1265, // WebAssemblyInstrFormats.td:59
1281 LOAD_LANE_16_A32_S = 1266, // WebAssemblyInstrFormats.td:61
1282 LOAD_LANE_16_A64 = 1267, // WebAssemblyInstrFormats.td:59
1283 LOAD_LANE_16_A64_S = 1268, // WebAssemblyInstrFormats.td:61
1284 LOAD_LANE_32_A32 = 1269, // WebAssemblyInstrFormats.td:59
1285 LOAD_LANE_32_A32_S = 1270, // WebAssemblyInstrFormats.td:61
1286 LOAD_LANE_32_A64 = 1271, // WebAssemblyInstrFormats.td:59
1287 LOAD_LANE_32_A64_S = 1272, // WebAssemblyInstrFormats.td:61
1288 LOAD_LANE_64_A32 = 1273, // WebAssemblyInstrFormats.td:59
1289 LOAD_LANE_64_A32_S = 1274, // WebAssemblyInstrFormats.td:61
1290 LOAD_LANE_64_A64 = 1275, // WebAssemblyInstrFormats.td:59
1291 LOAD_LANE_64_A64_S = 1276, // WebAssemblyInstrFormats.td:61
1292 LOAD_LANE_8_A32 = 1277, // WebAssemblyInstrFormats.td:59
1293 LOAD_LANE_8_A32_S = 1278, // WebAssemblyInstrFormats.td:61
1294 LOAD_LANE_8_A64 = 1279, // WebAssemblyInstrFormats.td:59
1295 LOAD_LANE_8_A64_S = 1280, // WebAssemblyInstrFormats.td:61
1296 LOAD_V128_A32 = 1281, // WebAssemblyInstrFormats.td:59
1297 LOAD_V128_A32_S = 1282, // WebAssemblyInstrFormats.td:61
1298 LOAD_V128_A64 = 1283, // WebAssemblyInstrFormats.td:59
1299 LOAD_V128_A64_S = 1284, // WebAssemblyInstrFormats.td:61
1300 LOAD_ZERO_32_A32 = 1285, // WebAssemblyInstrFormats.td:59
1301 LOAD_ZERO_32_A32_S = 1286, // WebAssemblyInstrFormats.td:61
1302 LOAD_ZERO_32_A64 = 1287, // WebAssemblyInstrFormats.td:59
1303 LOAD_ZERO_32_A64_S = 1288, // WebAssemblyInstrFormats.td:61
1304 LOAD_ZERO_64_A32 = 1289, // WebAssemblyInstrFormats.td:59
1305 LOAD_ZERO_64_A32_S = 1290, // WebAssemblyInstrFormats.td:61
1306 LOAD_ZERO_64_A64 = 1291, // WebAssemblyInstrFormats.td:59
1307 LOAD_ZERO_64_A64_S = 1292, // WebAssemblyInstrFormats.td:61
1308 LOCAL_GET_EXNREF = 1293, // WebAssemblyInstrFormats.td:59
1309 LOCAL_GET_EXNREF_S = 1294, // WebAssemblyInstrFormats.td:61
1310 LOCAL_GET_EXTERNREF = 1295, // WebAssemblyInstrFormats.td:59
1311 LOCAL_GET_EXTERNREF_S = 1296, // WebAssemblyInstrFormats.td:61
1312 LOCAL_GET_F32 = 1297, // WebAssemblyInstrFormats.td:59
1313 LOCAL_GET_F32_S = 1298, // WebAssemblyInstrFormats.td:61
1314 LOCAL_GET_F64 = 1299, // WebAssemblyInstrFormats.td:59
1315 LOCAL_GET_F64_S = 1300, // WebAssemblyInstrFormats.td:61
1316 LOCAL_GET_FUNCREF = 1301, // WebAssemblyInstrFormats.td:59
1317 LOCAL_GET_FUNCREF_S = 1302, // WebAssemblyInstrFormats.td:61
1318 LOCAL_GET_I32 = 1303, // WebAssemblyInstrFormats.td:59
1319 LOCAL_GET_I32_S = 1304, // WebAssemblyInstrFormats.td:61
1320 LOCAL_GET_I64 = 1305, // WebAssemblyInstrFormats.td:59
1321 LOCAL_GET_I64_S = 1306, // WebAssemblyInstrFormats.td:61
1322 LOCAL_GET_V128 = 1307, // WebAssemblyInstrFormats.td:59
1323 LOCAL_GET_V128_S = 1308, // WebAssemblyInstrFormats.td:61
1324 LOCAL_SET_EXNREF = 1309, // WebAssemblyInstrFormats.td:59
1325 LOCAL_SET_EXNREF_S = 1310, // WebAssemblyInstrFormats.td:61
1326 LOCAL_SET_EXTERNREF = 1311, // WebAssemblyInstrFormats.td:59
1327 LOCAL_SET_EXTERNREF_S = 1312, // WebAssemblyInstrFormats.td:61
1328 LOCAL_SET_F32 = 1313, // WebAssemblyInstrFormats.td:59
1329 LOCAL_SET_F32_S = 1314, // WebAssemblyInstrFormats.td:61
1330 LOCAL_SET_F64 = 1315, // WebAssemblyInstrFormats.td:59
1331 LOCAL_SET_F64_S = 1316, // WebAssemblyInstrFormats.td:61
1332 LOCAL_SET_FUNCREF = 1317, // WebAssemblyInstrFormats.td:59
1333 LOCAL_SET_FUNCREF_S = 1318, // WebAssemblyInstrFormats.td:61
1334 LOCAL_SET_I32 = 1319, // WebAssemblyInstrFormats.td:59
1335 LOCAL_SET_I32_S = 1320, // WebAssemblyInstrFormats.td:61
1336 LOCAL_SET_I64 = 1321, // WebAssemblyInstrFormats.td:59
1337 LOCAL_SET_I64_S = 1322, // WebAssemblyInstrFormats.td:61
1338 LOCAL_SET_V128 = 1323, // WebAssemblyInstrFormats.td:59
1339 LOCAL_SET_V128_S = 1324, // WebAssemblyInstrFormats.td:61
1340 LOCAL_TEE_EXNREF = 1325, // WebAssemblyInstrFormats.td:59
1341 LOCAL_TEE_EXNREF_S = 1326, // WebAssemblyInstrFormats.td:61
1342 LOCAL_TEE_EXTERNREF = 1327, // WebAssemblyInstrFormats.td:59
1343 LOCAL_TEE_EXTERNREF_S = 1328, // WebAssemblyInstrFormats.td:61
1344 LOCAL_TEE_F32 = 1329, // WebAssemblyInstrFormats.td:59
1345 LOCAL_TEE_F32_S = 1330, // WebAssemblyInstrFormats.td:61
1346 LOCAL_TEE_F64 = 1331, // WebAssemblyInstrFormats.td:59
1347 LOCAL_TEE_F64_S = 1332, // WebAssemblyInstrFormats.td:61
1348 LOCAL_TEE_FUNCREF = 1333, // WebAssemblyInstrFormats.td:59
1349 LOCAL_TEE_FUNCREF_S = 1334, // WebAssemblyInstrFormats.td:61
1350 LOCAL_TEE_I32 = 1335, // WebAssemblyInstrFormats.td:59
1351 LOCAL_TEE_I32_S = 1336, // WebAssemblyInstrFormats.td:61
1352 LOCAL_TEE_I64 = 1337, // WebAssemblyInstrFormats.td:59
1353 LOCAL_TEE_I64_S = 1338, // WebAssemblyInstrFormats.td:61
1354 LOCAL_TEE_V128 = 1339, // WebAssemblyInstrFormats.td:59
1355 LOCAL_TEE_V128_S = 1340, // WebAssemblyInstrFormats.td:61
1356 LOOP = 1341, // WebAssemblyInstrFormats.td:59
1357 LOOP_S = 1342, // WebAssemblyInstrFormats.td:61
1358 LT_F16x8 = 1343, // WebAssemblyInstrFormats.td:59
1359 LT_F16x8_S = 1344, // WebAssemblyInstrFormats.td:61
1360 LT_F32 = 1345, // WebAssemblyInstrFormats.td:59
1361 LT_F32_S = 1346, // WebAssemblyInstrFormats.td:61
1362 LT_F32x4 = 1347, // WebAssemblyInstrFormats.td:59
1363 LT_F32x4_S = 1348, // WebAssemblyInstrFormats.td:61
1364 LT_F64 = 1349, // WebAssemblyInstrFormats.td:59
1365 LT_F64_S = 1350, // WebAssemblyInstrFormats.td:61
1366 LT_F64x2 = 1351, // WebAssemblyInstrFormats.td:59
1367 LT_F64x2_S = 1352, // WebAssemblyInstrFormats.td:61
1368 LT_S_I16x8 = 1353, // WebAssemblyInstrFormats.td:59
1369 LT_S_I16x8_S = 1354, // WebAssemblyInstrFormats.td:61
1370 LT_S_I32 = 1355, // WebAssemblyInstrFormats.td:59
1371 LT_S_I32_S = 1356, // WebAssemblyInstrFormats.td:61
1372 LT_S_I32x4 = 1357, // WebAssemblyInstrFormats.td:59
1373 LT_S_I32x4_S = 1358, // WebAssemblyInstrFormats.td:61
1374 LT_S_I64 = 1359, // WebAssemblyInstrFormats.td:59
1375 LT_S_I64_S = 1360, // WebAssemblyInstrFormats.td:61
1376 LT_S_I64x2 = 1361, // WebAssemblyInstrFormats.td:59
1377 LT_S_I64x2_S = 1362, // WebAssemblyInstrFormats.td:61
1378 LT_S_I8x16 = 1363, // WebAssemblyInstrFormats.td:59
1379 LT_S_I8x16_S = 1364, // WebAssemblyInstrFormats.td:61
1380 LT_U_I16x8 = 1365, // WebAssemblyInstrFormats.td:59
1381 LT_U_I16x8_S = 1366, // WebAssemblyInstrFormats.td:61
1382 LT_U_I32 = 1367, // WebAssemblyInstrFormats.td:59
1383 LT_U_I32_S = 1368, // WebAssemblyInstrFormats.td:61
1384 LT_U_I32x4 = 1369, // WebAssemblyInstrFormats.td:59
1385 LT_U_I32x4_S = 1370, // WebAssemblyInstrFormats.td:61
1386 LT_U_I64 = 1371, // WebAssemblyInstrFormats.td:59
1387 LT_U_I64_S = 1372, // WebAssemblyInstrFormats.td:61
1388 LT_U_I8x16 = 1373, // WebAssemblyInstrFormats.td:59
1389 LT_U_I8x16_S = 1374, // WebAssemblyInstrFormats.td:61
1390 MADD_F16x8 = 1375, // WebAssemblyInstrFormats.td:59
1391 MADD_F16x8_S = 1376, // WebAssemblyInstrFormats.td:61
1392 MADD_F32x4 = 1377, // WebAssemblyInstrFormats.td:59
1393 MADD_F32x4_S = 1378, // WebAssemblyInstrFormats.td:61
1394 MADD_F64x2 = 1379, // WebAssemblyInstrFormats.td:59
1395 MADD_F64x2_S = 1380, // WebAssemblyInstrFormats.td:61
1396 MAX_F16x8 = 1381, // WebAssemblyInstrFormats.td:59
1397 MAX_F16x8_S = 1382, // WebAssemblyInstrFormats.td:61
1398 MAX_F32 = 1383, // WebAssemblyInstrFormats.td:59
1399 MAX_F32_S = 1384, // WebAssemblyInstrFormats.td:61
1400 MAX_F32x4 = 1385, // WebAssemblyInstrFormats.td:59
1401 MAX_F32x4_S = 1386, // WebAssemblyInstrFormats.td:61
1402 MAX_F64 = 1387, // WebAssemblyInstrFormats.td:59
1403 MAX_F64_S = 1388, // WebAssemblyInstrFormats.td:61
1404 MAX_F64x2 = 1389, // WebAssemblyInstrFormats.td:59
1405 MAX_F64x2_S = 1390, // WebAssemblyInstrFormats.td:61
1406 MAX_S_I16x8 = 1391, // WebAssemblyInstrFormats.td:59
1407 MAX_S_I16x8_S = 1392, // WebAssemblyInstrFormats.td:61
1408 MAX_S_I32x4 = 1393, // WebAssemblyInstrFormats.td:59
1409 MAX_S_I32x4_S = 1394, // WebAssemblyInstrFormats.td:61
1410 MAX_S_I8x16 = 1395, // WebAssemblyInstrFormats.td:59
1411 MAX_S_I8x16_S = 1396, // WebAssemblyInstrFormats.td:61
1412 MAX_U_I16x8 = 1397, // WebAssemblyInstrFormats.td:59
1413 MAX_U_I16x8_S = 1398, // WebAssemblyInstrFormats.td:61
1414 MAX_U_I32x4 = 1399, // WebAssemblyInstrFormats.td:59
1415 MAX_U_I32x4_S = 1400, // WebAssemblyInstrFormats.td:61
1416 MAX_U_I8x16 = 1401, // WebAssemblyInstrFormats.td:59
1417 MAX_U_I8x16_S = 1402, // WebAssemblyInstrFormats.td:61
1418 MEMCPY_A32 = 1403, // WebAssemblyInstrFormats.td:59
1419 MEMCPY_A32_S = 1404, // WebAssemblyInstrFormats.td:61
1420 MEMCPY_A64 = 1405, // WebAssemblyInstrFormats.td:59
1421 MEMCPY_A64_S = 1406, // WebAssemblyInstrFormats.td:61
1422 MEMORY_ATOMIC_NOTIFY_A32 = 1407, // WebAssemblyInstrFormats.td:59
1423 MEMORY_ATOMIC_NOTIFY_A32_S = 1408, // WebAssemblyInstrFormats.td:61
1424 MEMORY_ATOMIC_NOTIFY_A64 = 1409, // WebAssemblyInstrFormats.td:59
1425 MEMORY_ATOMIC_NOTIFY_A64_S = 1410, // WebAssemblyInstrFormats.td:61
1426 MEMORY_ATOMIC_WAIT32_A32 = 1411, // WebAssemblyInstrFormats.td:59
1427 MEMORY_ATOMIC_WAIT32_A32_S = 1412, // WebAssemblyInstrFormats.td:61
1428 MEMORY_ATOMIC_WAIT32_A64 = 1413, // WebAssemblyInstrFormats.td:59
1429 MEMORY_ATOMIC_WAIT32_A64_S = 1414, // WebAssemblyInstrFormats.td:61
1430 MEMORY_ATOMIC_WAIT64_A32 = 1415, // WebAssemblyInstrFormats.td:59
1431 MEMORY_ATOMIC_WAIT64_A32_S = 1416, // WebAssemblyInstrFormats.td:61
1432 MEMORY_ATOMIC_WAIT64_A64 = 1417, // WebAssemblyInstrFormats.td:59
1433 MEMORY_ATOMIC_WAIT64_A64_S = 1418, // WebAssemblyInstrFormats.td:61
1434 MEMORY_COPY_A32 = 1419, // WebAssemblyInstrFormats.td:59
1435 MEMORY_COPY_A32_S = 1420, // WebAssemblyInstrFormats.td:61
1436 MEMORY_COPY_A64 = 1421, // WebAssemblyInstrFormats.td:59
1437 MEMORY_COPY_A64_S = 1422, // WebAssemblyInstrFormats.td:61
1438 MEMORY_FILL_A32 = 1423, // WebAssemblyInstrFormats.td:59
1439 MEMORY_FILL_A32_S = 1424, // WebAssemblyInstrFormats.td:61
1440 MEMORY_FILL_A64 = 1425, // WebAssemblyInstrFormats.td:59
1441 MEMORY_FILL_A64_S = 1426, // WebAssemblyInstrFormats.td:61
1442 MEMORY_INIT_A32 = 1427, // WebAssemblyInstrFormats.td:59
1443 MEMORY_INIT_A32_S = 1428, // WebAssemblyInstrFormats.td:61
1444 MEMORY_INIT_A64 = 1429, // WebAssemblyInstrFormats.td:59
1445 MEMORY_INIT_A64_S = 1430, // WebAssemblyInstrFormats.td:61
1446 MEMSET_A32 = 1431, // WebAssemblyInstrFormats.td:59
1447 MEMSET_A32_S = 1432, // WebAssemblyInstrFormats.td:61
1448 MEMSET_A64 = 1433, // WebAssemblyInstrFormats.td:59
1449 MEMSET_A64_S = 1434, // WebAssemblyInstrFormats.td:61
1450 MIN_F16x8 = 1435, // WebAssemblyInstrFormats.td:59
1451 MIN_F16x8_S = 1436, // WebAssemblyInstrFormats.td:61
1452 MIN_F32 = 1437, // WebAssemblyInstrFormats.td:59
1453 MIN_F32_S = 1438, // WebAssemblyInstrFormats.td:61
1454 MIN_F32x4 = 1439, // WebAssemblyInstrFormats.td:59
1455 MIN_F32x4_S = 1440, // WebAssemblyInstrFormats.td:61
1456 MIN_F64 = 1441, // WebAssemblyInstrFormats.td:59
1457 MIN_F64_S = 1442, // WebAssemblyInstrFormats.td:61
1458 MIN_F64x2 = 1443, // WebAssemblyInstrFormats.td:59
1459 MIN_F64x2_S = 1444, // WebAssemblyInstrFormats.td:61
1460 MIN_S_I16x8 = 1445, // WebAssemblyInstrFormats.td:59
1461 MIN_S_I16x8_S = 1446, // WebAssemblyInstrFormats.td:61
1462 MIN_S_I32x4 = 1447, // WebAssemblyInstrFormats.td:59
1463 MIN_S_I32x4_S = 1448, // WebAssemblyInstrFormats.td:61
1464 MIN_S_I8x16 = 1449, // WebAssemblyInstrFormats.td:59
1465 MIN_S_I8x16_S = 1450, // WebAssemblyInstrFormats.td:61
1466 MIN_U_I16x8 = 1451, // WebAssemblyInstrFormats.td:59
1467 MIN_U_I16x8_S = 1452, // WebAssemblyInstrFormats.td:61
1468 MIN_U_I32x4 = 1453, // WebAssemblyInstrFormats.td:59
1469 MIN_U_I32x4_S = 1454, // WebAssemblyInstrFormats.td:61
1470 MIN_U_I8x16 = 1455, // WebAssemblyInstrFormats.td:59
1471 MIN_U_I8x16_S = 1456, // WebAssemblyInstrFormats.td:61
1472 MUL_F16x8 = 1457, // WebAssemblyInstrFormats.td:59
1473 MUL_F16x8_S = 1458, // WebAssemblyInstrFormats.td:61
1474 MUL_F32 = 1459, // WebAssemblyInstrFormats.td:59
1475 MUL_F32_S = 1460, // WebAssemblyInstrFormats.td:61
1476 MUL_F32x4 = 1461, // WebAssemblyInstrFormats.td:59
1477 MUL_F32x4_S = 1462, // WebAssemblyInstrFormats.td:61
1478 MUL_F64 = 1463, // WebAssemblyInstrFormats.td:59
1479 MUL_F64_S = 1464, // WebAssemblyInstrFormats.td:61
1480 MUL_F64x2 = 1465, // WebAssemblyInstrFormats.td:59
1481 MUL_F64x2_S = 1466, // WebAssemblyInstrFormats.td:61
1482 MUL_I16x8 = 1467, // WebAssemblyInstrFormats.td:59
1483 MUL_I16x8_S = 1468, // WebAssemblyInstrFormats.td:61
1484 MUL_I32 = 1469, // WebAssemblyInstrFormats.td:59
1485 MUL_I32_S = 1470, // WebAssemblyInstrFormats.td:61
1486 MUL_I32x4 = 1471, // WebAssemblyInstrFormats.td:59
1487 MUL_I32x4_S = 1472, // WebAssemblyInstrFormats.td:61
1488 MUL_I64 = 1473, // WebAssemblyInstrFormats.td:59
1489 MUL_I64_S = 1474, // WebAssemblyInstrFormats.td:61
1490 MUL_I64x2 = 1475, // WebAssemblyInstrFormats.td:59
1491 MUL_I64x2_S = 1476, // WebAssemblyInstrFormats.td:61
1492 NARROW_S_I16x8 = 1477, // WebAssemblyInstrFormats.td:59
1493 NARROW_S_I16x8_S = 1478, // WebAssemblyInstrFormats.td:61
1494 NARROW_S_I8x16 = 1479, // WebAssemblyInstrFormats.td:59
1495 NARROW_S_I8x16_S = 1480, // WebAssemblyInstrFormats.td:61
1496 NARROW_U_I16x8 = 1481, // WebAssemblyInstrFormats.td:59
1497 NARROW_U_I16x8_S = 1482, // WebAssemblyInstrFormats.td:61
1498 NARROW_U_I8x16 = 1483, // WebAssemblyInstrFormats.td:59
1499 NARROW_U_I8x16_S = 1484, // WebAssemblyInstrFormats.td:61
1500 NEAREST_F16x8 = 1485, // WebAssemblyInstrFormats.td:59
1501 NEAREST_F16x8_S = 1486, // WebAssemblyInstrFormats.td:61
1502 NEAREST_F32 = 1487, // WebAssemblyInstrFormats.td:59
1503 NEAREST_F32_S = 1488, // WebAssemblyInstrFormats.td:61
1504 NEAREST_F32x4 = 1489, // WebAssemblyInstrFormats.td:59
1505 NEAREST_F32x4_S = 1490, // WebAssemblyInstrFormats.td:61
1506 NEAREST_F64 = 1491, // WebAssemblyInstrFormats.td:59
1507 NEAREST_F64_S = 1492, // WebAssemblyInstrFormats.td:61
1508 NEAREST_F64x2 = 1493, // WebAssemblyInstrFormats.td:59
1509 NEAREST_F64x2_S = 1494, // WebAssemblyInstrFormats.td:61
1510 NEG_F16x8 = 1495, // WebAssemblyInstrFormats.td:59
1511 NEG_F16x8_S = 1496, // WebAssemblyInstrFormats.td:61
1512 NEG_F32 = 1497, // WebAssemblyInstrFormats.td:59
1513 NEG_F32_S = 1498, // WebAssemblyInstrFormats.td:61
1514 NEG_F32x4 = 1499, // WebAssemblyInstrFormats.td:59
1515 NEG_F32x4_S = 1500, // WebAssemblyInstrFormats.td:61
1516 NEG_F64 = 1501, // WebAssemblyInstrFormats.td:59
1517 NEG_F64_S = 1502, // WebAssemblyInstrFormats.td:61
1518 NEG_F64x2 = 1503, // WebAssemblyInstrFormats.td:59
1519 NEG_F64x2_S = 1504, // WebAssemblyInstrFormats.td:61
1520 NEG_I16x8 = 1505, // WebAssemblyInstrFormats.td:59
1521 NEG_I16x8_S = 1506, // WebAssemblyInstrFormats.td:61
1522 NEG_I32x4 = 1507, // WebAssemblyInstrFormats.td:59
1523 NEG_I32x4_S = 1508, // WebAssemblyInstrFormats.td:61
1524 NEG_I64x2 = 1509, // WebAssemblyInstrFormats.td:59
1525 NEG_I64x2_S = 1510, // WebAssemblyInstrFormats.td:61
1526 NEG_I8x16 = 1511, // WebAssemblyInstrFormats.td:59
1527 NEG_I8x16_S = 1512, // WebAssemblyInstrFormats.td:61
1528 NE_F16x8 = 1513, // WebAssemblyInstrFormats.td:59
1529 NE_F16x8_S = 1514, // WebAssemblyInstrFormats.td:61
1530 NE_F32 = 1515, // WebAssemblyInstrFormats.td:59
1531 NE_F32_S = 1516, // WebAssemblyInstrFormats.td:61
1532 NE_F32x4 = 1517, // WebAssemblyInstrFormats.td:59
1533 NE_F32x4_S = 1518, // WebAssemblyInstrFormats.td:61
1534 NE_F64 = 1519, // WebAssemblyInstrFormats.td:59
1535 NE_F64_S = 1520, // WebAssemblyInstrFormats.td:61
1536 NE_F64x2 = 1521, // WebAssemblyInstrFormats.td:59
1537 NE_F64x2_S = 1522, // WebAssemblyInstrFormats.td:61
1538 NE_I16x8 = 1523, // WebAssemblyInstrFormats.td:59
1539 NE_I16x8_S = 1524, // WebAssemblyInstrFormats.td:61
1540 NE_I32 = 1525, // WebAssemblyInstrFormats.td:59
1541 NE_I32_S = 1526, // WebAssemblyInstrFormats.td:61
1542 NE_I32x4 = 1527, // WebAssemblyInstrFormats.td:59
1543 NE_I32x4_S = 1528, // WebAssemblyInstrFormats.td:61
1544 NE_I64 = 1529, // WebAssemblyInstrFormats.td:59
1545 NE_I64_S = 1530, // WebAssemblyInstrFormats.td:61
1546 NE_I64x2 = 1531, // WebAssemblyInstrFormats.td:59
1547 NE_I64x2_S = 1532, // WebAssemblyInstrFormats.td:61
1548 NE_I8x16 = 1533, // WebAssemblyInstrFormats.td:59
1549 NE_I8x16_S = 1534, // WebAssemblyInstrFormats.td:61
1550 NMADD_F16x8 = 1535, // WebAssemblyInstrFormats.td:59
1551 NMADD_F16x8_S = 1536, // WebAssemblyInstrFormats.td:61
1552 NMADD_F32x4 = 1537, // WebAssemblyInstrFormats.td:59
1553 NMADD_F32x4_S = 1538, // WebAssemblyInstrFormats.td:61
1554 NMADD_F64x2 = 1539, // WebAssemblyInstrFormats.td:59
1555 NMADD_F64x2_S = 1540, // WebAssemblyInstrFormats.td:61
1556 NOP = 1541, // WebAssemblyInstrFormats.td:59
1557 NOP_S = 1542, // WebAssemblyInstrFormats.td:61
1558 NOT = 1543, // WebAssemblyInstrFormats.td:59
1559 NOT_S = 1544, // WebAssemblyInstrFormats.td:61
1560 OR = 1545, // WebAssemblyInstrFormats.td:59
1561 OR_I32 = 1546, // WebAssemblyInstrFormats.td:59
1562 OR_I32_S = 1547, // WebAssemblyInstrFormats.td:61
1563 OR_I64 = 1548, // WebAssemblyInstrFormats.td:59
1564 OR_I64_S = 1549, // WebAssemblyInstrFormats.td:61
1565 OR_S = 1550, // WebAssemblyInstrFormats.td:61
1566 PMAX_F16x8 = 1551, // WebAssemblyInstrFormats.td:59
1567 PMAX_F16x8_S = 1552, // WebAssemblyInstrFormats.td:61
1568 PMAX_F32x4 = 1553, // WebAssemblyInstrFormats.td:59
1569 PMAX_F32x4_S = 1554, // WebAssemblyInstrFormats.td:61
1570 PMAX_F64x2 = 1555, // WebAssemblyInstrFormats.td:59
1571 PMAX_F64x2_S = 1556, // WebAssemblyInstrFormats.td:61
1572 PMIN_F16x8 = 1557, // WebAssemblyInstrFormats.td:59
1573 PMIN_F16x8_S = 1558, // WebAssemblyInstrFormats.td:61
1574 PMIN_F32x4 = 1559, // WebAssemblyInstrFormats.td:59
1575 PMIN_F32x4_S = 1560, // WebAssemblyInstrFormats.td:61
1576 PMIN_F64x2 = 1561, // WebAssemblyInstrFormats.td:59
1577 PMIN_F64x2_S = 1562, // WebAssemblyInstrFormats.td:61
1578 POPCNT_I32 = 1563, // WebAssemblyInstrFormats.td:59
1579 POPCNT_I32_S = 1564, // WebAssemblyInstrFormats.td:61
1580 POPCNT_I64 = 1565, // WebAssemblyInstrFormats.td:59
1581 POPCNT_I64_S = 1566, // WebAssemblyInstrFormats.td:61
1582 POPCNT_I8x16 = 1567, // WebAssemblyInstrFormats.td:59
1583 POPCNT_I8x16_S = 1568, // WebAssemblyInstrFormats.td:61
1584 Q15MULR_SAT_S_I16x8 = 1569, // WebAssemblyInstrFormats.td:59
1585 Q15MULR_SAT_S_I16x8_S = 1570, // WebAssemblyInstrFormats.td:61
1586 REF_FUNC = 1571, // WebAssemblyInstrFormats.td:59
1587 REF_FUNC_S = 1572, // WebAssemblyInstrFormats.td:61
1588 REF_IS_NULL_EXNREF = 1573, // WebAssemblyInstrFormats.td:59
1589 REF_IS_NULL_EXNREF_S = 1574, // WebAssemblyInstrFormats.td:61
1590 REF_IS_NULL_EXTERNREF = 1575, // WebAssemblyInstrFormats.td:59
1591 REF_IS_NULL_EXTERNREF_S = 1576, // WebAssemblyInstrFormats.td:61
1592 REF_IS_NULL_FUNCREF = 1577, // WebAssemblyInstrFormats.td:59
1593 REF_IS_NULL_FUNCREF_S = 1578, // WebAssemblyInstrFormats.td:61
1594 REF_NULL_EXNREF = 1579, // WebAssemblyInstrFormats.td:59
1595 REF_NULL_EXNREF_S = 1580, // WebAssemblyInstrFormats.td:61
1596 REF_NULL_EXTERNREF = 1581, // WebAssemblyInstrFormats.td:59
1597 REF_NULL_EXTERNREF_S = 1582, // WebAssemblyInstrFormats.td:61
1598 REF_NULL_FUNCREF = 1583, // WebAssemblyInstrFormats.td:59
1599 REF_NULL_FUNCREF_S = 1584, // WebAssemblyInstrFormats.td:61
1600 REF_TEST_FUNCREF = 1585, // WebAssemblyInstrFormats.td:59
1601 REF_TEST_FUNCREF_S = 1586, // WebAssemblyInstrFormats.td:61
1602 RELAXED_DOT = 1587, // WebAssemblyInstrFormats.td:59
1603 RELAXED_DOT_ADD = 1588, // WebAssemblyInstrFormats.td:59
1604 RELAXED_DOT_ADD_S = 1589, // WebAssemblyInstrFormats.td:61
1605 RELAXED_DOT_BFLOAT = 1590, // WebAssemblyInstrFormats.td:59
1606 RELAXED_DOT_BFLOAT_S = 1591, // WebAssemblyInstrFormats.td:61
1607 RELAXED_DOT_S = 1592, // WebAssemblyInstrFormats.td:61
1608 RELAXED_Q15MULR_S_I16x8 = 1593, // WebAssemblyInstrFormats.td:59
1609 RELAXED_Q15MULR_S_I16x8_S = 1594, // WebAssemblyInstrFormats.td:61
1610 RELAXED_SWIZZLE = 1595, // WebAssemblyInstrFormats.td:59
1611 RELAXED_SWIZZLE_S = 1596, // WebAssemblyInstrFormats.td:61
1612 REM_S_I32 = 1597, // WebAssemblyInstrFormats.td:59
1613 REM_S_I32_S = 1598, // WebAssemblyInstrFormats.td:61
1614 REM_S_I64 = 1599, // WebAssemblyInstrFormats.td:59
1615 REM_S_I64_S = 1600, // WebAssemblyInstrFormats.td:61
1616 REM_U_I32 = 1601, // WebAssemblyInstrFormats.td:59
1617 REM_U_I32_S = 1602, // WebAssemblyInstrFormats.td:61
1618 REM_U_I64 = 1603, // WebAssemblyInstrFormats.td:59
1619 REM_U_I64_S = 1604, // WebAssemblyInstrFormats.td:61
1620 REPLACE_LANE_F16x8 = 1605, // WebAssemblyInstrFormats.td:59
1621 REPLACE_LANE_F16x8_S = 1606, // WebAssemblyInstrFormats.td:61
1622 REPLACE_LANE_F32x4 = 1607, // WebAssemblyInstrFormats.td:59
1623 REPLACE_LANE_F32x4_S = 1608, // WebAssemblyInstrFormats.td:61
1624 REPLACE_LANE_F64x2 = 1609, // WebAssemblyInstrFormats.td:59
1625 REPLACE_LANE_F64x2_S = 1610, // WebAssemblyInstrFormats.td:61
1626 REPLACE_LANE_I16x8 = 1611, // WebAssemblyInstrFormats.td:59
1627 REPLACE_LANE_I16x8_S = 1612, // WebAssemblyInstrFormats.td:61
1628 REPLACE_LANE_I32x4 = 1613, // WebAssemblyInstrFormats.td:59
1629 REPLACE_LANE_I32x4_S = 1614, // WebAssemblyInstrFormats.td:61
1630 REPLACE_LANE_I64x2 = 1615, // WebAssemblyInstrFormats.td:59
1631 REPLACE_LANE_I64x2_S = 1616, // WebAssemblyInstrFormats.td:61
1632 REPLACE_LANE_I8x16 = 1617, // WebAssemblyInstrFormats.td:59
1633 REPLACE_LANE_I8x16_S = 1618, // WebAssemblyInstrFormats.td:61
1634 RETHROW = 1619, // WebAssemblyInstrFormats.td:59
1635 RETHROW_S = 1620, // WebAssemblyInstrFormats.td:61
1636 RETURN = 1621, // WebAssemblyInstrFormats.td:59
1637 RETURN_S = 1622, // WebAssemblyInstrFormats.td:61
1638 RET_CALL = 1623, // WebAssemblyInstrFormats.td:59
1639 RET_CALL_INDIRECT = 1624, // WebAssemblyInstrFormats.td:59
1640 RET_CALL_INDIRECT_S = 1625, // WebAssemblyInstrFormats.td:61
1641 RET_CALL_S = 1626, // WebAssemblyInstrFormats.td:61
1642 ROTL_I32 = 1627, // WebAssemblyInstrFormats.td:59
1643 ROTL_I32_S = 1628, // WebAssemblyInstrFormats.td:61
1644 ROTL_I64 = 1629, // WebAssemblyInstrFormats.td:59
1645 ROTL_I64_S = 1630, // WebAssemblyInstrFormats.td:61
1646 ROTR_I32 = 1631, // WebAssemblyInstrFormats.td:59
1647 ROTR_I32_S = 1632, // WebAssemblyInstrFormats.td:61
1648 ROTR_I64 = 1633, // WebAssemblyInstrFormats.td:59
1649 ROTR_I64_S = 1634, // WebAssemblyInstrFormats.td:61
1650 SELECT_EXNREF = 1635, // WebAssemblyInstrFormats.td:59
1651 SELECT_EXNREF_S = 1636, // WebAssemblyInstrFormats.td:61
1652 SELECT_EXTERNREF = 1637, // WebAssemblyInstrFormats.td:59
1653 SELECT_EXTERNREF_S = 1638, // WebAssemblyInstrFormats.td:61
1654 SELECT_F32 = 1639, // WebAssemblyInstrFormats.td:59
1655 SELECT_F32_S = 1640, // WebAssemblyInstrFormats.td:61
1656 SELECT_F64 = 1641, // WebAssemblyInstrFormats.td:59
1657 SELECT_F64_S = 1642, // WebAssemblyInstrFormats.td:61
1658 SELECT_FUNCREF = 1643, // WebAssemblyInstrFormats.td:59
1659 SELECT_FUNCREF_S = 1644, // WebAssemblyInstrFormats.td:61
1660 SELECT_I32 = 1645, // WebAssemblyInstrFormats.td:59
1661 SELECT_I32_S = 1646, // WebAssemblyInstrFormats.td:61
1662 SELECT_I64 = 1647, // WebAssemblyInstrFormats.td:59
1663 SELECT_I64_S = 1648, // WebAssemblyInstrFormats.td:61
1664 SELECT_V128 = 1649, // WebAssemblyInstrFormats.td:59
1665 SELECT_V128_S = 1650, // WebAssemblyInstrFormats.td:61
1666 SHL_I16x8 = 1651, // WebAssemblyInstrFormats.td:59
1667 SHL_I16x8_S = 1652, // WebAssemblyInstrFormats.td:61
1668 SHL_I32 = 1653, // WebAssemblyInstrFormats.td:59
1669 SHL_I32_S = 1654, // WebAssemblyInstrFormats.td:61
1670 SHL_I32x4 = 1655, // WebAssemblyInstrFormats.td:59
1671 SHL_I32x4_S = 1656, // WebAssemblyInstrFormats.td:61
1672 SHL_I64 = 1657, // WebAssemblyInstrFormats.td:59
1673 SHL_I64_S = 1658, // WebAssemblyInstrFormats.td:61
1674 SHL_I64x2 = 1659, // WebAssemblyInstrFormats.td:59
1675 SHL_I64x2_S = 1660, // WebAssemblyInstrFormats.td:61
1676 SHL_I8x16 = 1661, // WebAssemblyInstrFormats.td:59
1677 SHL_I8x16_S = 1662, // WebAssemblyInstrFormats.td:61
1678 SHR_S_I16x8 = 1663, // WebAssemblyInstrFormats.td:59
1679 SHR_S_I16x8_S = 1664, // WebAssemblyInstrFormats.td:61
1680 SHR_S_I32 = 1665, // WebAssemblyInstrFormats.td:59
1681 SHR_S_I32_S = 1666, // WebAssemblyInstrFormats.td:61
1682 SHR_S_I32x4 = 1667, // WebAssemblyInstrFormats.td:59
1683 SHR_S_I32x4_S = 1668, // WebAssemblyInstrFormats.td:61
1684 SHR_S_I64 = 1669, // WebAssemblyInstrFormats.td:59
1685 SHR_S_I64_S = 1670, // WebAssemblyInstrFormats.td:61
1686 SHR_S_I64x2 = 1671, // WebAssemblyInstrFormats.td:59
1687 SHR_S_I64x2_S = 1672, // WebAssemblyInstrFormats.td:61
1688 SHR_S_I8x16 = 1673, // WebAssemblyInstrFormats.td:59
1689 SHR_S_I8x16_S = 1674, // WebAssemblyInstrFormats.td:61
1690 SHR_U_I16x8 = 1675, // WebAssemblyInstrFormats.td:59
1691 SHR_U_I16x8_S = 1676, // WebAssemblyInstrFormats.td:61
1692 SHR_U_I32 = 1677, // WebAssemblyInstrFormats.td:59
1693 SHR_U_I32_S = 1678, // WebAssemblyInstrFormats.td:61
1694 SHR_U_I32x4 = 1679, // WebAssemblyInstrFormats.td:59
1695 SHR_U_I32x4_S = 1680, // WebAssemblyInstrFormats.td:61
1696 SHR_U_I64 = 1681, // WebAssemblyInstrFormats.td:59
1697 SHR_U_I64_S = 1682, // WebAssemblyInstrFormats.td:61
1698 SHR_U_I64x2 = 1683, // WebAssemblyInstrFormats.td:59
1699 SHR_U_I64x2_S = 1684, // WebAssemblyInstrFormats.td:61
1700 SHR_U_I8x16 = 1685, // WebAssemblyInstrFormats.td:59
1701 SHR_U_I8x16_S = 1686, // WebAssemblyInstrFormats.td:61
1702 SHUFFLE = 1687, // WebAssemblyInstrFormats.td:59
1703 SHUFFLE_S = 1688, // WebAssemblyInstrFormats.td:61
1704 SIMD_RELAXED_FMAX_F32x4 = 1689, // WebAssemblyInstrFormats.td:59
1705 SIMD_RELAXED_FMAX_F32x4_S = 1690, // WebAssemblyInstrFormats.td:61
1706 SIMD_RELAXED_FMAX_F64x2 = 1691, // WebAssemblyInstrFormats.td:59
1707 SIMD_RELAXED_FMAX_F64x2_S = 1692, // WebAssemblyInstrFormats.td:61
1708 SIMD_RELAXED_FMIN_F32x4 = 1693, // WebAssemblyInstrFormats.td:59
1709 SIMD_RELAXED_FMIN_F32x4_S = 1694, // WebAssemblyInstrFormats.td:61
1710 SIMD_RELAXED_FMIN_F64x2 = 1695, // WebAssemblyInstrFormats.td:59
1711 SIMD_RELAXED_FMIN_F64x2_S = 1696, // WebAssemblyInstrFormats.td:61
1712 SPLAT_F16x8 = 1697, // WebAssemblyInstrFormats.td:59
1713 SPLAT_F16x8_S = 1698, // WebAssemblyInstrFormats.td:61
1714 SPLAT_F32x4 = 1699, // WebAssemblyInstrFormats.td:59
1715 SPLAT_F32x4_S = 1700, // WebAssemblyInstrFormats.td:61
1716 SPLAT_F64x2 = 1701, // WebAssemblyInstrFormats.td:59
1717 SPLAT_F64x2_S = 1702, // WebAssemblyInstrFormats.td:61
1718 SPLAT_I16x8 = 1703, // WebAssemblyInstrFormats.td:59
1719 SPLAT_I16x8_S = 1704, // WebAssemblyInstrFormats.td:61
1720 SPLAT_I32x4 = 1705, // WebAssemblyInstrFormats.td:59
1721 SPLAT_I32x4_S = 1706, // WebAssemblyInstrFormats.td:61
1722 SPLAT_I64x2 = 1707, // WebAssemblyInstrFormats.td:59
1723 SPLAT_I64x2_S = 1708, // WebAssemblyInstrFormats.td:61
1724 SPLAT_I8x16 = 1709, // WebAssemblyInstrFormats.td:59
1725 SPLAT_I8x16_S = 1710, // WebAssemblyInstrFormats.td:61
1726 SQRT_F16x8 = 1711, // WebAssemblyInstrFormats.td:59
1727 SQRT_F16x8_S = 1712, // WebAssemblyInstrFormats.td:61
1728 SQRT_F32 = 1713, // WebAssemblyInstrFormats.td:59
1729 SQRT_F32_S = 1714, // WebAssemblyInstrFormats.td:61
1730 SQRT_F32x4 = 1715, // WebAssemblyInstrFormats.td:59
1731 SQRT_F32x4_S = 1716, // WebAssemblyInstrFormats.td:61
1732 SQRT_F64 = 1717, // WebAssemblyInstrFormats.td:59
1733 SQRT_F64_S = 1718, // WebAssemblyInstrFormats.td:61
1734 SQRT_F64x2 = 1719, // WebAssemblyInstrFormats.td:59
1735 SQRT_F64x2_S = 1720, // WebAssemblyInstrFormats.td:61
1736 STORE16_I32_A32 = 1721, // WebAssemblyInstrFormats.td:59
1737 STORE16_I32_A32_S = 1722, // WebAssemblyInstrFormats.td:61
1738 STORE16_I32_A64 = 1723, // WebAssemblyInstrFormats.td:59
1739 STORE16_I32_A64_S = 1724, // WebAssemblyInstrFormats.td:61
1740 STORE16_I64_A32 = 1725, // WebAssemblyInstrFormats.td:59
1741 STORE16_I64_A32_S = 1726, // WebAssemblyInstrFormats.td:61
1742 STORE16_I64_A64 = 1727, // WebAssemblyInstrFormats.td:59
1743 STORE16_I64_A64_S = 1728, // WebAssemblyInstrFormats.td:61
1744 STORE32_I64_A32 = 1729, // WebAssemblyInstrFormats.td:59
1745 STORE32_I64_A32_S = 1730, // WebAssemblyInstrFormats.td:61
1746 STORE32_I64_A64 = 1731, // WebAssemblyInstrFormats.td:59
1747 STORE32_I64_A64_S = 1732, // WebAssemblyInstrFormats.td:61
1748 STORE8_I32_A32 = 1733, // WebAssemblyInstrFormats.td:59
1749 STORE8_I32_A32_S = 1734, // WebAssemblyInstrFormats.td:61
1750 STORE8_I32_A64 = 1735, // WebAssemblyInstrFormats.td:59
1751 STORE8_I32_A64_S = 1736, // WebAssemblyInstrFormats.td:61
1752 STORE8_I64_A32 = 1737, // WebAssemblyInstrFormats.td:59
1753 STORE8_I64_A32_S = 1738, // WebAssemblyInstrFormats.td:61
1754 STORE8_I64_A64 = 1739, // WebAssemblyInstrFormats.td:59
1755 STORE8_I64_A64_S = 1740, // WebAssemblyInstrFormats.td:61
1756 STORE_F16_F32_A32 = 1741, // WebAssemblyInstrFormats.td:59
1757 STORE_F16_F32_A32_S = 1742, // WebAssemblyInstrFormats.td:61
1758 STORE_F16_F32_A64 = 1743, // WebAssemblyInstrFormats.td:59
1759 STORE_F16_F32_A64_S = 1744, // WebAssemblyInstrFormats.td:61
1760 STORE_F32_A32 = 1745, // WebAssemblyInstrFormats.td:59
1761 STORE_F32_A32_S = 1746, // WebAssemblyInstrFormats.td:61
1762 STORE_F32_A64 = 1747, // WebAssemblyInstrFormats.td:59
1763 STORE_F32_A64_S = 1748, // WebAssemblyInstrFormats.td:61
1764 STORE_F64_A32 = 1749, // WebAssemblyInstrFormats.td:59
1765 STORE_F64_A32_S = 1750, // WebAssemblyInstrFormats.td:61
1766 STORE_F64_A64 = 1751, // WebAssemblyInstrFormats.td:59
1767 STORE_F64_A64_S = 1752, // WebAssemblyInstrFormats.td:61
1768 STORE_I32_A32 = 1753, // WebAssemblyInstrFormats.td:59
1769 STORE_I32_A32_S = 1754, // WebAssemblyInstrFormats.td:61
1770 STORE_I32_A64 = 1755, // WebAssemblyInstrFormats.td:59
1771 STORE_I32_A64_S = 1756, // WebAssemblyInstrFormats.td:61
1772 STORE_I64_A32 = 1757, // WebAssemblyInstrFormats.td:59
1773 STORE_I64_A32_S = 1758, // WebAssemblyInstrFormats.td:61
1774 STORE_I64_A64 = 1759, // WebAssemblyInstrFormats.td:59
1775 STORE_I64_A64_S = 1760, // WebAssemblyInstrFormats.td:61
1776 STORE_LANE_I16x8_A32 = 1761, // WebAssemblyInstrFormats.td:59
1777 STORE_LANE_I16x8_A32_S = 1762, // WebAssemblyInstrFormats.td:61
1778 STORE_LANE_I16x8_A64 = 1763, // WebAssemblyInstrFormats.td:59
1779 STORE_LANE_I16x8_A64_S = 1764, // WebAssemblyInstrFormats.td:61
1780 STORE_LANE_I32x4_A32 = 1765, // WebAssemblyInstrFormats.td:59
1781 STORE_LANE_I32x4_A32_S = 1766, // WebAssemblyInstrFormats.td:61
1782 STORE_LANE_I32x4_A64 = 1767, // WebAssemblyInstrFormats.td:59
1783 STORE_LANE_I32x4_A64_S = 1768, // WebAssemblyInstrFormats.td:61
1784 STORE_LANE_I64x2_A32 = 1769, // WebAssemblyInstrFormats.td:59
1785 STORE_LANE_I64x2_A32_S = 1770, // WebAssemblyInstrFormats.td:61
1786 STORE_LANE_I64x2_A64 = 1771, // WebAssemblyInstrFormats.td:59
1787 STORE_LANE_I64x2_A64_S = 1772, // WebAssemblyInstrFormats.td:61
1788 STORE_LANE_I8x16_A32 = 1773, // WebAssemblyInstrFormats.td:59
1789 STORE_LANE_I8x16_A32_S = 1774, // WebAssemblyInstrFormats.td:61
1790 STORE_LANE_I8x16_A64 = 1775, // WebAssemblyInstrFormats.td:59
1791 STORE_LANE_I8x16_A64_S = 1776, // WebAssemblyInstrFormats.td:61
1792 STORE_V128_A32 = 1777, // WebAssemblyInstrFormats.td:59
1793 STORE_V128_A32_S = 1778, // WebAssemblyInstrFormats.td:61
1794 STORE_V128_A64 = 1779, // WebAssemblyInstrFormats.td:59
1795 STORE_V128_A64_S = 1780, // WebAssemblyInstrFormats.td:61
1796 SUB_F16x8 = 1781, // WebAssemblyInstrFormats.td:59
1797 SUB_F16x8_S = 1782, // WebAssemblyInstrFormats.td:61
1798 SUB_F32 = 1783, // WebAssemblyInstrFormats.td:59
1799 SUB_F32_S = 1784, // WebAssemblyInstrFormats.td:61
1800 SUB_F32x4 = 1785, // WebAssemblyInstrFormats.td:59
1801 SUB_F32x4_S = 1786, // WebAssemblyInstrFormats.td:61
1802 SUB_F64 = 1787, // WebAssemblyInstrFormats.td:59
1803 SUB_F64_S = 1788, // WebAssemblyInstrFormats.td:61
1804 SUB_F64x2 = 1789, // WebAssemblyInstrFormats.td:59
1805 SUB_F64x2_S = 1790, // WebAssemblyInstrFormats.td:61
1806 SUB_I16x8 = 1791, // WebAssemblyInstrFormats.td:59
1807 SUB_I16x8_S = 1792, // WebAssemblyInstrFormats.td:61
1808 SUB_I32 = 1793, // WebAssemblyInstrFormats.td:59
1809 SUB_I32_S = 1794, // WebAssemblyInstrFormats.td:61
1810 SUB_I32x4 = 1795, // WebAssemblyInstrFormats.td:59
1811 SUB_I32x4_S = 1796, // WebAssemblyInstrFormats.td:61
1812 SUB_I64 = 1797, // WebAssemblyInstrFormats.td:59
1813 SUB_I64_S = 1798, // WebAssemblyInstrFormats.td:61
1814 SUB_I64x2 = 1799, // WebAssemblyInstrFormats.td:59
1815 SUB_I64x2_S = 1800, // WebAssemblyInstrFormats.td:61
1816 SUB_I8x16 = 1801, // WebAssemblyInstrFormats.td:59
1817 SUB_I8x16_S = 1802, // WebAssemblyInstrFormats.td:61
1818 SUB_SAT_S_I16x8 = 1803, // WebAssemblyInstrFormats.td:59
1819 SUB_SAT_S_I16x8_S = 1804, // WebAssemblyInstrFormats.td:61
1820 SUB_SAT_S_I8x16 = 1805, // WebAssemblyInstrFormats.td:59
1821 SUB_SAT_S_I8x16_S = 1806, // WebAssemblyInstrFormats.td:61
1822 SUB_SAT_U_I16x8 = 1807, // WebAssemblyInstrFormats.td:59
1823 SUB_SAT_U_I16x8_S = 1808, // WebAssemblyInstrFormats.td:61
1824 SUB_SAT_U_I8x16 = 1809, // WebAssemblyInstrFormats.td:59
1825 SUB_SAT_U_I8x16_S = 1810, // WebAssemblyInstrFormats.td:61
1826 SWIZZLE = 1811, // WebAssemblyInstrFormats.td:59
1827 SWIZZLE_S = 1812, // WebAssemblyInstrFormats.td:61
1828 TABLE_COPY = 1813, // WebAssemblyInstrFormats.td:59
1829 TABLE_COPY_S = 1814, // WebAssemblyInstrFormats.td:61
1830 TABLE_FILL_EXNREF = 1815, // WebAssemblyInstrFormats.td:59
1831 TABLE_FILL_EXNREF_S = 1816, // WebAssemblyInstrFormats.td:61
1832 TABLE_FILL_EXTERNREF = 1817, // WebAssemblyInstrFormats.td:59
1833 TABLE_FILL_EXTERNREF_S = 1818, // WebAssemblyInstrFormats.td:61
1834 TABLE_FILL_FUNCREF = 1819, // WebAssemblyInstrFormats.td:59
1835 TABLE_FILL_FUNCREF_S = 1820, // WebAssemblyInstrFormats.td:61
1836 TABLE_GET_EXNREF = 1821, // WebAssemblyInstrFormats.td:59
1837 TABLE_GET_EXNREF_S = 1822, // WebAssemblyInstrFormats.td:61
1838 TABLE_GET_EXTERNREF = 1823, // WebAssemblyInstrFormats.td:59
1839 TABLE_GET_EXTERNREF_S = 1824, // WebAssemblyInstrFormats.td:61
1840 TABLE_GET_FUNCREF = 1825, // WebAssemblyInstrFormats.td:59
1841 TABLE_GET_FUNCREF_S = 1826, // WebAssemblyInstrFormats.td:61
1842 TABLE_GROW_EXNREF = 1827, // WebAssemblyInstrFormats.td:59
1843 TABLE_GROW_EXNREF_S = 1828, // WebAssemblyInstrFormats.td:61
1844 TABLE_GROW_EXTERNREF = 1829, // WebAssemblyInstrFormats.td:59
1845 TABLE_GROW_EXTERNREF_S = 1830, // WebAssemblyInstrFormats.td:61
1846 TABLE_GROW_FUNCREF = 1831, // WebAssemblyInstrFormats.td:59
1847 TABLE_GROW_FUNCREF_S = 1832, // WebAssemblyInstrFormats.td:61
1848 TABLE_SET_EXNREF = 1833, // WebAssemblyInstrFormats.td:59
1849 TABLE_SET_EXNREF_S = 1834, // WebAssemblyInstrFormats.td:61
1850 TABLE_SET_EXTERNREF = 1835, // WebAssemblyInstrFormats.td:59
1851 TABLE_SET_EXTERNREF_S = 1836, // WebAssemblyInstrFormats.td:61
1852 TABLE_SET_FUNCREF = 1837, // WebAssemblyInstrFormats.td:59
1853 TABLE_SET_FUNCREF_S = 1838, // WebAssemblyInstrFormats.td:61
1854 TABLE_SIZE = 1839, // WebAssemblyInstrFormats.td:59
1855 TABLE_SIZE_S = 1840, // WebAssemblyInstrFormats.td:61
1856 TEE_EXNREF = 1841, // WebAssemblyInstrFormats.td:59
1857 TEE_EXNREF_S = 1842, // WebAssemblyInstrFormats.td:61
1858 TEE_EXTERNREF = 1843, // WebAssemblyInstrFormats.td:59
1859 TEE_EXTERNREF_S = 1844, // WebAssemblyInstrFormats.td:61
1860 TEE_F32 = 1845, // WebAssemblyInstrFormats.td:59
1861 TEE_F32_S = 1846, // WebAssemblyInstrFormats.td:61
1862 TEE_F64 = 1847, // WebAssemblyInstrFormats.td:59
1863 TEE_F64_S = 1848, // WebAssemblyInstrFormats.td:61
1864 TEE_FUNCREF = 1849, // WebAssemblyInstrFormats.td:59
1865 TEE_FUNCREF_S = 1850, // WebAssemblyInstrFormats.td:61
1866 TEE_I32 = 1851, // WebAssemblyInstrFormats.td:59
1867 TEE_I32_S = 1852, // WebAssemblyInstrFormats.td:61
1868 TEE_I64 = 1853, // WebAssemblyInstrFormats.td:59
1869 TEE_I64_S = 1854, // WebAssemblyInstrFormats.td:61
1870 TEE_V128 = 1855, // WebAssemblyInstrFormats.td:59
1871 TEE_V128_S = 1856, // WebAssemblyInstrFormats.td:61
1872 THROW = 1857, // WebAssemblyInstrFormats.td:59
1873 THROW_REF = 1858, // WebAssemblyInstrFormats.td:59
1874 THROW_REF_S = 1859, // WebAssemblyInstrFormats.td:61
1875 THROW_S = 1860, // WebAssemblyInstrFormats.td:61
1876 TRUNC_F16x8 = 1861, // WebAssemblyInstrFormats.td:59
1877 TRUNC_F16x8_S = 1862, // WebAssemblyInstrFormats.td:61
1878 TRUNC_F32 = 1863, // WebAssemblyInstrFormats.td:59
1879 TRUNC_F32_S = 1864, // WebAssemblyInstrFormats.td:61
1880 TRUNC_F32x4 = 1865, // WebAssemblyInstrFormats.td:59
1881 TRUNC_F32x4_S = 1866, // WebAssemblyInstrFormats.td:61
1882 TRUNC_F64 = 1867, // WebAssemblyInstrFormats.td:59
1883 TRUNC_F64_S = 1868, // WebAssemblyInstrFormats.td:61
1884 TRUNC_F64x2 = 1869, // WebAssemblyInstrFormats.td:59
1885 TRUNC_F64x2_S = 1870, // WebAssemblyInstrFormats.td:61
1886 TRY = 1871, // WebAssemblyInstrFormats.td:59
1887 TRY_S = 1872, // WebAssemblyInstrFormats.td:61
1888 TRY_TABLE = 1873, // WebAssemblyInstrFormats.td:59
1889 TRY_TABLE_S = 1874, // WebAssemblyInstrFormats.td:61
1890 UNREACHABLE = 1875, // WebAssemblyInstrFormats.td:59
1891 UNREACHABLE_S = 1876, // WebAssemblyInstrFormats.td:61
1892 XOR = 1877, // WebAssemblyInstrFormats.td:59
1893 XOR_I32 = 1878, // WebAssemblyInstrFormats.td:59
1894 XOR_I32_S = 1879, // WebAssemblyInstrFormats.td:61
1895 XOR_I64 = 1880, // WebAssemblyInstrFormats.td:59
1896 XOR_I64_S = 1881, // WebAssemblyInstrFormats.td:61
1897 XOR_S = 1882, // WebAssemblyInstrFormats.td:61
1898 anonymous_13975MEMORY_GROW_A32 = 1883, // WebAssemblyInstrFormats.td:59
1899 anonymous_13975MEMORY_GROW_A32_S = 1884, // WebAssemblyInstrFormats.td:61
1900 anonymous_13975MEMORY_SIZE_A32 = 1885, // WebAssemblyInstrFormats.td:59
1901 anonymous_13975MEMORY_SIZE_A32_S = 1886, // WebAssemblyInstrFormats.td:61
1902 anonymous_13976MEMORY_GROW_A64 = 1887, // WebAssemblyInstrFormats.td:59
1903 anonymous_13976MEMORY_GROW_A64_S = 1888, // WebAssemblyInstrFormats.td:61
1904 anonymous_13976MEMORY_SIZE_A64 = 1889, // WebAssemblyInstrFormats.td:59
1905 anonymous_13976MEMORY_SIZE_A64_S = 1890, // WebAssemblyInstrFormats.td:61
1906 convert_low_s_F64x2 = 1891, // WebAssemblyInstrFormats.td:59
1907 convert_low_s_F64x2_S = 1892, // WebAssemblyInstrFormats.td:61
1908 convert_low_u_F64x2 = 1893, // WebAssemblyInstrFormats.td:59
1909 convert_low_u_F64x2_S = 1894, // WebAssemblyInstrFormats.td:61
1910 demote_zero_F32x4 = 1895, // WebAssemblyInstrFormats.td:59
1911 demote_zero_F32x4_S = 1896, // WebAssemblyInstrFormats.td:61
1912 extadd_pairwise_s_I16x8 = 1897, // WebAssemblyInstrFormats.td:59
1913 extadd_pairwise_s_I16x8_S = 1898, // WebAssemblyInstrFormats.td:61
1914 extadd_pairwise_s_I32x4 = 1899, // WebAssemblyInstrFormats.td:59
1915 extadd_pairwise_s_I32x4_S = 1900, // WebAssemblyInstrFormats.td:61
1916 extadd_pairwise_u_I16x8 = 1901, // WebAssemblyInstrFormats.td:59
1917 extadd_pairwise_u_I16x8_S = 1902, // WebAssemblyInstrFormats.td:61
1918 extadd_pairwise_u_I32x4 = 1903, // WebAssemblyInstrFormats.td:59
1919 extadd_pairwise_u_I32x4_S = 1904, // WebAssemblyInstrFormats.td:61
1920 extend_high_s_I16x8 = 1905, // WebAssemblyInstrFormats.td:59
1921 extend_high_s_I16x8_S = 1906, // WebAssemblyInstrFormats.td:61
1922 extend_high_s_I32x4 = 1907, // WebAssemblyInstrFormats.td:59
1923 extend_high_s_I32x4_S = 1908, // WebAssemblyInstrFormats.td:61
1924 extend_high_s_I64x2 = 1909, // WebAssemblyInstrFormats.td:59
1925 extend_high_s_I64x2_S = 1910, // WebAssemblyInstrFormats.td:61
1926 extend_high_u_I16x8 = 1911, // WebAssemblyInstrFormats.td:59
1927 extend_high_u_I16x8_S = 1912, // WebAssemblyInstrFormats.td:61
1928 extend_high_u_I32x4 = 1913, // WebAssemblyInstrFormats.td:59
1929 extend_high_u_I32x4_S = 1914, // WebAssemblyInstrFormats.td:61
1930 extend_high_u_I64x2 = 1915, // WebAssemblyInstrFormats.td:59
1931 extend_high_u_I64x2_S = 1916, // WebAssemblyInstrFormats.td:61
1932 extend_low_s_I16x8 = 1917, // WebAssemblyInstrFormats.td:59
1933 extend_low_s_I16x8_S = 1918, // WebAssemblyInstrFormats.td:61
1934 extend_low_s_I32x4 = 1919, // WebAssemblyInstrFormats.td:59
1935 extend_low_s_I32x4_S = 1920, // WebAssemblyInstrFormats.td:61
1936 extend_low_s_I64x2 = 1921, // WebAssemblyInstrFormats.td:59
1937 extend_low_s_I64x2_S = 1922, // WebAssemblyInstrFormats.td:61
1938 extend_low_u_I16x8 = 1923, // WebAssemblyInstrFormats.td:59
1939 extend_low_u_I16x8_S = 1924, // WebAssemblyInstrFormats.td:61
1940 extend_low_u_I32x4 = 1925, // WebAssemblyInstrFormats.td:59
1941 extend_low_u_I32x4_S = 1926, // WebAssemblyInstrFormats.td:61
1942 extend_low_u_I64x2 = 1927, // WebAssemblyInstrFormats.td:59
1943 extend_low_u_I64x2_S = 1928, // WebAssemblyInstrFormats.td:61
1944 fp_to_sint_I16x8 = 1929, // WebAssemblyInstrFormats.td:59
1945 fp_to_sint_I16x8_S = 1930, // WebAssemblyInstrFormats.td:61
1946 fp_to_sint_I32x4 = 1931, // WebAssemblyInstrFormats.td:59
1947 fp_to_sint_I32x4_S = 1932, // WebAssemblyInstrFormats.td:61
1948 fp_to_uint_I16x8 = 1933, // WebAssemblyInstrFormats.td:59
1949 fp_to_uint_I16x8_S = 1934, // WebAssemblyInstrFormats.td:61
1950 fp_to_uint_I32x4 = 1935, // WebAssemblyInstrFormats.td:59
1951 fp_to_uint_I32x4_S = 1936, // WebAssemblyInstrFormats.td:61
1952 int_wasm_relaxed_trunc_signed_I32x4 = 1937, // WebAssemblyInstrFormats.td:59
1953 int_wasm_relaxed_trunc_signed_I32x4_S = 1938, // WebAssemblyInstrFormats.td:61
1954 int_wasm_relaxed_trunc_signed_zero_I32x4 = 1939, // WebAssemblyInstrFormats.td:59
1955 int_wasm_relaxed_trunc_signed_zero_I32x4_S = 1940, // WebAssemblyInstrFormats.td:61
1956 int_wasm_relaxed_trunc_unsigned_I32x4 = 1941, // WebAssemblyInstrFormats.td:59
1957 int_wasm_relaxed_trunc_unsigned_I32x4_S = 1942, // WebAssemblyInstrFormats.td:61
1958 int_wasm_relaxed_trunc_unsigned_zero_I32x4 = 1943, // WebAssemblyInstrFormats.td:59
1959 int_wasm_relaxed_trunc_unsigned_zero_I32x4_S = 1944, // WebAssemblyInstrFormats.td:61
1960 promote_low_F64x2 = 1945, // WebAssemblyInstrFormats.td:59
1961 promote_low_F64x2_S = 1946, // WebAssemblyInstrFormats.td:61
1962 sint_to_fp_F16x8 = 1947, // WebAssemblyInstrFormats.td:59
1963 sint_to_fp_F16x8_S = 1948, // WebAssemblyInstrFormats.td:61
1964 sint_to_fp_F32x4 = 1949, // WebAssemblyInstrFormats.td:59
1965 sint_to_fp_F32x4_S = 1950, // WebAssemblyInstrFormats.td:61
1966 trunc_sat_zero_s_I32x4 = 1951, // WebAssemblyInstrFormats.td:59
1967 trunc_sat_zero_s_I32x4_S = 1952, // WebAssemblyInstrFormats.td:61
1968 trunc_sat_zero_u_I32x4 = 1953, // WebAssemblyInstrFormats.td:59
1969 trunc_sat_zero_u_I32x4_S = 1954, // WebAssemblyInstrFormats.td:61
1970 uint_to_fp_F16x8 = 1955, // WebAssemblyInstrFormats.td:59
1971 uint_to_fp_F16x8_S = 1956, // WebAssemblyInstrFormats.td:61
1972 uint_to_fp_F32x4 = 1957, // WebAssemblyInstrFormats.td:59
1973 uint_to_fp_F32x4_S = 1958, // WebAssemblyInstrFormats.td:61
1974 INSTRUCTION_LIST_END = 1959
1975 };
1976 enum RegClassByHwModeUses : uint16_t {
1977 wasm_ptr_rc,
1978 };
1979
1980} // namespace llvm::WebAssembly
1981
1982#endif // GET_INSTRINFO_ENUM
1983
1984#ifdef GET_INSTRINFO_SCHED_ENUM
1985#undef GET_INSTRINFO_SCHED_ENUM
1986
1987namespace llvm::WebAssembly::Sched {
1988
1989 enum {
1990 NoInstrModel = 0,
1991 SCHED_LIST_END = 1
1992 };
1993
1994} // namespace llvm::WebAssembly::Sched
1995
1996#endif // GET_INSTRINFO_SCHED_ENUM
1997
1998#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
1999
2000namespace llvm {
2001
2002struct WebAssemblyInstrTable {
2003 MCInstrDesc Insts[1959];
2004 static_assert(alignof(MCInstrDesc) >= alignof(MCPhysReg), "Unwanted padding between Insts and ImplicitOps");
2005 MCPhysReg ImplicitOps[10];
2006 char Padding[sizeof(MCOperandInfo) - sizeof ImplicitOps % sizeof(MCOperandInfo)];
2007 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
2008 MCOperandInfo OperandInfo[884];
2009};
2010} // namespace llvm
2011
2012#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
2013
2014#ifdef GET_INSTRINFO_MC_DESC
2015#undef GET_INSTRINFO_MC_DESC
2016
2017namespace llvm {
2018
2019static_assert((sizeof WebAssemblyInstrTable::ImplicitOps + sizeof WebAssemblyInstrTable::Padding) % sizeof(MCOperandInfo) == 0);
2020static constexpr unsigned WebAssemblyOpInfoBase = (sizeof WebAssemblyInstrTable::ImplicitOps + sizeof WebAssemblyInstrTable::Padding) / sizeof(MCOperandInfo);
2021
2022extern const WebAssemblyInstrTable WebAssemblyDescs = {
2023 {
2024 { 1958, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // uint_to_fp_F32x4_S
2025 { 1957, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // uint_to_fp_F32x4
2026 { 1956, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // uint_to_fp_F16x8_S
2027 { 1955, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // uint_to_fp_F16x8
2028 { 1954, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // trunc_sat_zero_u_I32x4_S
2029 { 1953, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // trunc_sat_zero_u_I32x4
2030 { 1952, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // trunc_sat_zero_s_I32x4_S
2031 { 1951, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // trunc_sat_zero_s_I32x4
2032 { 1950, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // sint_to_fp_F32x4_S
2033 { 1949, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // sint_to_fp_F32x4
2034 { 1948, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // sint_to_fp_F16x8_S
2035 { 1947, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // sint_to_fp_F16x8
2036 { 1946, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // promote_low_F64x2_S
2037 { 1945, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // promote_low_F64x2
2038 { 1944, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // int_wasm_relaxed_trunc_unsigned_zero_I32x4_S
2039 { 1943, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // int_wasm_relaxed_trunc_unsigned_zero_I32x4
2040 { 1942, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // int_wasm_relaxed_trunc_unsigned_I32x4_S
2041 { 1941, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // int_wasm_relaxed_trunc_unsigned_I32x4
2042 { 1940, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // int_wasm_relaxed_trunc_signed_zero_I32x4_S
2043 { 1939, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // int_wasm_relaxed_trunc_signed_zero_I32x4
2044 { 1938, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // int_wasm_relaxed_trunc_signed_I32x4_S
2045 { 1937, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // int_wasm_relaxed_trunc_signed_I32x4
2046 { 1936, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // fp_to_uint_I32x4_S
2047 { 1935, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // fp_to_uint_I32x4
2048 { 1934, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // fp_to_uint_I16x8_S
2049 { 1933, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // fp_to_uint_I16x8
2050 { 1932, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // fp_to_sint_I32x4_S
2051 { 1931, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // fp_to_sint_I32x4
2052 { 1930, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // fp_to_sint_I16x8_S
2053 { 1929, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // fp_to_sint_I16x8
2054 { 1928, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_low_u_I64x2_S
2055 { 1927, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_low_u_I64x2
2056 { 1926, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_low_u_I32x4_S
2057 { 1925, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_low_u_I32x4
2058 { 1924, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_low_u_I16x8_S
2059 { 1923, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_low_u_I16x8
2060 { 1922, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_low_s_I64x2_S
2061 { 1921, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_low_s_I64x2
2062 { 1920, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_low_s_I32x4_S
2063 { 1919, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_low_s_I32x4
2064 { 1918, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_low_s_I16x8_S
2065 { 1917, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_low_s_I16x8
2066 { 1916, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_high_u_I64x2_S
2067 { 1915, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_high_u_I64x2
2068 { 1914, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_high_u_I32x4_S
2069 { 1913, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_high_u_I32x4
2070 { 1912, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_high_u_I16x8_S
2071 { 1911, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_high_u_I16x8
2072 { 1910, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_high_s_I64x2_S
2073 { 1909, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_high_s_I64x2
2074 { 1908, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_high_s_I32x4_S
2075 { 1907, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_high_s_I32x4
2076 { 1906, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_high_s_I16x8_S
2077 { 1905, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_high_s_I16x8
2078 { 1904, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extadd_pairwise_u_I32x4_S
2079 { 1903, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extadd_pairwise_u_I32x4
2080 { 1902, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extadd_pairwise_u_I16x8_S
2081 { 1901, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extadd_pairwise_u_I16x8
2082 { 1900, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extadd_pairwise_s_I32x4_S
2083 { 1899, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extadd_pairwise_s_I32x4
2084 { 1898, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extadd_pairwise_s_I16x8_S
2085 { 1897, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extadd_pairwise_s_I16x8
2086 { 1896, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // demote_zero_F32x4_S
2087 { 1895, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // demote_zero_F32x4
2088 { 1894, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // convert_low_u_F64x2_S
2089 { 1893, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // convert_low_u_F64x2
2090 { 1892, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // convert_low_s_F64x2_S
2091 { 1891, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // convert_low_s_F64x2
2092 { 1890, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_13976MEMORY_SIZE_A64_S
2093 { 1889, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 190, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_13976MEMORY_SIZE_A64
2094 { 1888, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_13976MEMORY_GROW_A64_S
2095 { 1887, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 881, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_13976MEMORY_GROW_A64
2096 { 1886, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_13975MEMORY_SIZE_A32_S
2097 { 1885, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 188, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_13975MEMORY_SIZE_A32
2098 { 1884, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_13975MEMORY_GROW_A32_S
2099 { 1883, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 878, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_13975MEMORY_GROW_A32
2100 { 1882, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_S
2101 { 1881, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_I64_S
2102 { 1880, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_I64
2103 { 1879, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_I32_S
2104 { 1878, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_I32
2105 { 1877, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR
2106 { 1876, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Trap)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // UNREACHABLE_S
2107 { 1875, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Trap)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // UNREACHABLE
2108 { 1874, 2, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 876, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRY_TABLE_S
2109 { 1873, 1, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 297, 8, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRY_TABLE
2110 { 1872, 1, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 297, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRY_S
2111 { 1871, 1, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 297, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRY
2112 { 1870, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRUNC_F64x2_S
2113 { 1869, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRUNC_F64x2
2114 { 1868, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRUNC_F64_S
2115 { 1867, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRUNC_F64
2116 { 1866, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRUNC_F32x4_S
2117 { 1865, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRUNC_F32x4
2118 { 1864, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRUNC_F32_S
2119 { 1863, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 157, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRUNC_F32
2120 { 1862, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRUNC_F16x8_S
2121 { 1861, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRUNC_F16x8
2122 { 1860, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 305, 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // THROW_S
2123 { 1859, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // THROW_REF_S
2124 { 1858, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 306, 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // THROW_REF
2125 { 1857, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 305, 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // THROW
2126 { 1856, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_V128_S
2127 { 1855, 3, 2, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_V128
2128 { 1854, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_I64_S
2129 { 1853, 3, 2, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_I64
2130 { 1852, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_I32_S
2131 { 1851, 3, 2, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_I32
2132 { 1850, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_FUNCREF_S
2133 { 1849, 3, 2, 0, 0, 0, 1, WebAssemblyOpInfoBase + 873, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_FUNCREF
2134 { 1848, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_F64_S
2135 { 1847, 3, 2, 0, 0, 0, 1, WebAssemblyOpInfoBase + 167, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_F64
2136 { 1846, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_F32_S
2137 { 1845, 3, 2, 0, 0, 0, 1, WebAssemblyOpInfoBase + 164, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_F32
2138 { 1844, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_EXTERNREF_S
2139 { 1843, 3, 2, 0, 0, 0, 1, WebAssemblyOpInfoBase + 870, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_EXTERNREF
2140 { 1842, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_EXNREF_S
2141 { 1841, 3, 2, 0, 0, 0, 1, WebAssemblyOpInfoBase + 867, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_EXNREF
2142 { 1840, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 826, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_SIZE_S
2143 { 1839, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 865, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_SIZE
2144 { 1838, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 826, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_SET_FUNCREF_S
2145 { 1837, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 862, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_SET_FUNCREF
2146 { 1836, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 826, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_SET_EXTERNREF_S
2147 { 1835, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 859, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_SET_EXTERNREF
2148 { 1834, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 826, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_SET_EXNREF_S
2149 { 1833, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 856, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_SET_EXNREF
2150 { 1832, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 826, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_GROW_FUNCREF_S
2151 { 1831, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 852, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_GROW_FUNCREF
2152 { 1830, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 826, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_GROW_EXTERNREF_S
2153 { 1829, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 848, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_GROW_EXTERNREF
2154 { 1828, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 826, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_GROW_EXNREF_S
2155 { 1827, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 844, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_GROW_EXNREF
2156 { 1826, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 826, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_GET_FUNCREF_S
2157 { 1825, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 841, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_GET_FUNCREF
2158 { 1824, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 826, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_GET_EXTERNREF_S
2159 { 1823, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 838, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_GET_EXTERNREF
2160 { 1822, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 826, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_GET_EXNREF_S
2161 { 1821, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 835, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_GET_EXNREF
2162 { 1820, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 826, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_FILL_FUNCREF_S
2163 { 1819, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 831, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_FILL_FUNCREF
2164 { 1818, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 826, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_FILL_EXTERNREF_S
2165 { 1817, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 827, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_FILL_EXTERNREF
2166 { 1816, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 826, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_FILL_EXNREF_S
2167 { 1815, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 822, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_FILL_EXNREF
2168 { 1814, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 820, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_COPY_S
2169 { 1813, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 815, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_COPY
2170 { 1812, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SWIZZLE_S
2171 { 1811, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SWIZZLE
2172 { 1810, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_SAT_U_I8x16_S
2173 { 1809, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_SAT_U_I8x16
2174 { 1808, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_SAT_U_I16x8_S
2175 { 1807, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_SAT_U_I16x8
2176 { 1806, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_SAT_S_I8x16_S
2177 { 1805, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_SAT_S_I8x16
2178 { 1804, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_SAT_S_I16x8_S
2179 { 1803, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_SAT_S_I16x8
2180 { 1802, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I8x16_S
2181 { 1801, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I8x16
2182 { 1800, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I64x2_S
2183 { 1799, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I64x2
2184 { 1798, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I64_S
2185 { 1797, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I64
2186 { 1796, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I32x4_S
2187 { 1795, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I32x4
2188 { 1794, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I32_S
2189 { 1793, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I32
2190 { 1792, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I16x8_S
2191 { 1791, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I16x8
2192 { 1790, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F64x2_S
2193 { 1789, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F64x2
2194 { 1788, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F64_S
2195 { 1787, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 167, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F64
2196 { 1786, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F32x4_S
2197 { 1785, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F32x4
2198 { 1784, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F32_S
2199 { 1783, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 164, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F32
2200 { 1782, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F16x8_S
2201 { 1781, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F16x8
2202 { 1780, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 513, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_V128_A64_S
2203 { 1779, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 811, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_V128_A64
2204 { 1778, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 507, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_V128_A32_S
2205 { 1777, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 807, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_V128_A32
2206 { 1776, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 562, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I8x16_A64_S
2207 { 1775, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 802, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I8x16_A64
2208 { 1774, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 553, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I8x16_A32_S
2209 { 1773, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 797, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I8x16_A32
2210 { 1772, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 562, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I64x2_A64_S
2211 { 1771, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 802, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I64x2_A64
2212 { 1770, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 553, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I64x2_A32_S
2213 { 1769, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 797, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I64x2_A32
2214 { 1768, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 562, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I32x4_A64_S
2215 { 1767, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 802, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I32x4_A64
2216 { 1766, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 553, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I32x4_A32_S
2217 { 1765, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 797, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I32x4_A32
2218 { 1764, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 562, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I16x8_A64_S
2219 { 1763, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 802, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I16x8_A64
2220 { 1762, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 553, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I16x8_A32_S
2221 { 1761, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 797, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I16x8_A32
2222 { 1760, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 513, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_I64_A64_S
2223 { 1759, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 777, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_I64_A64
2224 { 1758, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 507, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_I64_A32_S
2225 { 1757, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 773, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_I64_A32
2226 { 1756, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 513, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_I32_A64_S
2227 { 1755, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 769, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_I32_A64
2228 { 1754, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 507, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_I32_A32_S
2229 { 1753, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 765, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_I32_A32
2230 { 1752, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 513, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_F64_A64_S
2231 { 1751, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 793, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_F64_A64
2232 { 1750, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 507, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_F64_A32_S
2233 { 1749, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 789, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_F64_A32
2234 { 1748, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 513, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_F32_A64_S
2235 { 1747, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 785, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_F32_A64
2236 { 1746, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 507, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_F32_A32_S
2237 { 1745, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 781, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_F32_A32
2238 { 1744, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 513, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_F16_F32_A64_S
2239 { 1743, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 785, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_F16_F32_A64
2240 { 1742, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 507, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_F16_F32_A32_S
2241 { 1741, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 781, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_F16_F32_A32
2242 { 1740, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 513, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE8_I64_A64_S
2243 { 1739, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 777, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE8_I64_A64
2244 { 1738, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 507, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE8_I64_A32_S
2245 { 1737, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 773, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE8_I64_A32
2246 { 1736, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 513, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE8_I32_A64_S
2247 { 1735, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 769, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE8_I32_A64
2248 { 1734, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 507, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE8_I32_A32_S
2249 { 1733, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 765, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE8_I32_A32
2250 { 1732, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 513, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE32_I64_A64_S
2251 { 1731, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 777, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE32_I64_A64
2252 { 1730, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 507, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE32_I64_A32_S
2253 { 1729, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 773, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE32_I64_A32
2254 { 1728, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 513, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE16_I64_A64_S
2255 { 1727, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 777, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE16_I64_A64
2256 { 1726, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 507, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE16_I64_A32_S
2257 { 1725, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 773, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE16_I64_A32
2258 { 1724, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 513, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE16_I32_A64_S
2259 { 1723, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 769, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE16_I32_A64
2260 { 1722, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 507, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE16_I32_A32_S
2261 { 1721, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 765, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE16_I32_A32
2262 { 1720, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SQRT_F64x2_S
2263 { 1719, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SQRT_F64x2
2264 { 1718, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SQRT_F64_S
2265 { 1717, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SQRT_F64
2266 { 1716, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SQRT_F32x4_S
2267 { 1715, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SQRT_F32x4
2268 { 1714, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SQRT_F32_S
2269 { 1713, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 157, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SQRT_F32
2270 { 1712, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SQRT_F16x8_S
2271 { 1711, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SQRT_F16x8
2272 { 1710, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_I8x16_S
2273 { 1709, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 761, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_I8x16
2274 { 1708, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_I64x2_S
2275 { 1707, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 763, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_I64x2
2276 { 1706, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_I32x4_S
2277 { 1705, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 761, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_I32x4
2278 { 1704, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_I16x8_S
2279 { 1703, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 761, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_I16x8
2280 { 1702, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_F64x2_S
2281 { 1701, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 759, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_F64x2
2282 { 1700, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_F32x4_S
2283 { 1699, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 757, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_F32x4
2284 { 1698, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_F16x8_S
2285 { 1697, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 757, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_F16x8
2286 { 1696, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SIMD_RELAXED_FMIN_F64x2_S
2287 { 1695, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SIMD_RELAXED_FMIN_F64x2
2288 { 1694, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SIMD_RELAXED_FMIN_F32x4_S
2289 { 1693, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SIMD_RELAXED_FMIN_F32x4
2290 { 1692, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SIMD_RELAXED_FMAX_F64x2_S
2291 { 1691, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SIMD_RELAXED_FMAX_F64x2
2292 { 1690, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SIMD_RELAXED_FMAX_F32x4_S
2293 { 1689, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SIMD_RELAXED_FMAX_F32x4
2294 { 1688, 16, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 385, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHUFFLE_S
2295 { 1687, 19, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 738, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHUFFLE
2296 { 1686, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_U_I8x16_S
2297 { 1685, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 735, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_U_I8x16
2298 { 1684, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_U_I64x2_S
2299 { 1683, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 735, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_U_I64x2
2300 { 1682, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_U_I64_S
2301 { 1681, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_U_I64
2302 { 1680, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_U_I32x4_S
2303 { 1679, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 735, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_U_I32x4
2304 { 1678, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_U_I32_S
2305 { 1677, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_U_I32
2306 { 1676, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_U_I16x8_S
2307 { 1675, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 735, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_U_I16x8
2308 { 1674, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_S_I8x16_S
2309 { 1673, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 735, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_S_I8x16
2310 { 1672, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_S_I64x2_S
2311 { 1671, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 735, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_S_I64x2
2312 { 1670, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_S_I64_S
2313 { 1669, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_S_I64
2314 { 1668, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_S_I32x4_S
2315 { 1667, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 735, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_S_I32x4
2316 { 1666, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_S_I32_S
2317 { 1665, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_S_I32
2318 { 1664, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_S_I16x8_S
2319 { 1663, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 735, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_S_I16x8
2320 { 1662, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_I8x16_S
2321 { 1661, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 735, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_I8x16
2322 { 1660, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_I64x2_S
2323 { 1659, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 735, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_I64x2
2324 { 1658, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_I64_S
2325 { 1657, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_I64
2326 { 1656, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_I32x4_S
2327 { 1655, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 735, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_I32x4
2328 { 1654, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_I32_S
2329 { 1653, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_I32
2330 { 1652, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_I16x8_S
2331 { 1651, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 735, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_I16x8
2332 { 1650, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_V128_S
2333 { 1649, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 731, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_V128
2334 { 1648, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_I64_S
2335 { 1647, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 727, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_I64
2336 { 1646, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_I32_S
2337 { 1645, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 723, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_I32
2338 { 1644, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_FUNCREF_S
2339 { 1643, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 719, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_FUNCREF
2340 { 1642, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_F64_S
2341 { 1641, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 715, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_F64
2342 { 1640, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_F32_S
2343 { 1639, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 711, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_F32
2344 { 1638, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_EXTERNREF_S
2345 { 1637, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 707, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_EXTERNREF
2346 { 1636, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_EXNREF_S
2347 { 1635, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 703, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_EXNREF
2348 { 1634, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ROTR_I64_S
2349 { 1633, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ROTR_I64
2350 { 1632, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ROTR_I32_S
2351 { 1631, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ROTR_I32
2352 { 1630, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ROTL_I64_S
2353 { 1629, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ROTL_I64
2354 { 1628, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ROTL_I32_S
2355 { 1627, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ROTL_I32
2356 { 1626, 1, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 151, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RET_CALL_S
2357 { 1625, 2, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 303, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RET_CALL_INDIRECT_S
2358 { 1624, 2, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 303, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RET_CALL_INDIRECT
2359 { 1623, 1, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 151, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RET_CALL
2360 { 1622, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RETURN_S
2361 { 1621, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RETURN
2362 { 1620, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 154, 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RETHROW_S
2363 { 1619, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 154, 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RETHROW
2364 { 1618, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 426, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_I8x16_S
2365 { 1617, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 695, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_I8x16
2366 { 1616, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 426, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_I64x2_S
2367 { 1615, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 699, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_I64x2
2368 { 1614, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 426, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_I32x4_S
2369 { 1613, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 695, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_I32x4
2370 { 1612, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 426, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_I16x8_S
2371 { 1611, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 695, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_I16x8
2372 { 1610, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 426, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_F64x2_S
2373 { 1609, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 691, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_F64x2
2374 { 1608, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 426, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_F32x4_S
2375 { 1607, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 687, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_F32x4
2376 { 1606, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 426, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_F16x8_S
2377 { 1605, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 687, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_F16x8
2378 { 1604, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REM_U_I64_S
2379 { 1603, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REM_U_I64
2380 { 1602, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REM_U_I32_S
2381 { 1601, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REM_U_I32
2382 { 1600, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REM_S_I64_S
2383 { 1599, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REM_S_I64
2384 { 1598, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REM_S_I32_S
2385 { 1597, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REM_S_I32
2386 { 1596, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELAXED_SWIZZLE_S
2387 { 1595, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELAXED_SWIZZLE
2388 { 1594, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELAXED_Q15MULR_S_I16x8_S
2389 { 1593, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELAXED_Q15MULR_S_I16x8
2390 { 1592, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELAXED_DOT_S
2391 { 1591, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELAXED_DOT_BFLOAT_S
2392 { 1590, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 293, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELAXED_DOT_BFLOAT
2393 { 1589, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELAXED_DOT_ADD_S
2394 { 1588, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 293, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELAXED_DOT_ADD
2395 { 1587, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELAXED_DOT
2396 { 1586, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 686, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_TEST_FUNCREF_S
2397 { 1585, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 683, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_TEST_FUNCREF
2398 { 1584, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_NULL_FUNCREF_S
2399 { 1583, 1, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 410, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_NULL_FUNCREF
2400 { 1582, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_NULL_EXTERNREF_S
2401 { 1581, 1, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 407, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_NULL_EXTERNREF
2402 { 1580, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_NULL_EXNREF_S
2403 { 1579, 1, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 306, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_NULL_EXNREF
2404 { 1578, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_IS_NULL_FUNCREF_S
2405 { 1577, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 681, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_IS_NULL_FUNCREF
2406 { 1576, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_IS_NULL_EXTERNREF_S
2407 { 1575, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 679, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_IS_NULL_EXTERNREF
2408 { 1574, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_IS_NULL_EXNREF_S
2409 { 1573, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 677, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_IS_NULL_EXNREF
2410 { 1572, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 151, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_FUNC_S
2411 { 1571, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 675, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_FUNC
2412 { 1570, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Q15MULR_SAT_S_I16x8_S
2413 { 1569, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Q15MULR_SAT_S_I16x8
2414 { 1568, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // POPCNT_I8x16_S
2415 { 1567, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // POPCNT_I8x16
2416 { 1566, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // POPCNT_I64_S
2417 { 1565, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 309, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // POPCNT_I64
2418 { 1564, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // POPCNT_I32_S
2419 { 1563, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 307, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // POPCNT_I32
2420 { 1562, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PMIN_F64x2_S
2421 { 1561, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PMIN_F64x2
2422 { 1560, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PMIN_F32x4_S
2423 { 1559, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PMIN_F32x4
2424 { 1558, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PMIN_F16x8_S
2425 { 1557, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PMIN_F16x8
2426 { 1556, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PMAX_F64x2_S
2427 { 1555, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PMAX_F64x2
2428 { 1554, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PMAX_F32x4_S
2429 { 1553, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PMAX_F32x4
2430 { 1552, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PMAX_F16x8_S
2431 { 1551, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PMAX_F16x8
2432 { 1550, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_S
2433 { 1549, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_I64_S
2434 { 1548, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_I64
2435 { 1547, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_I32_S
2436 { 1546, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_I32
2437 { 1545, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR
2438 { 1544, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NOT_S
2439 { 1543, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NOT
2440 { 1542, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NOP_S
2441 { 1541, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NOP
2442 { 1540, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NMADD_F64x2_S
2443 { 1539, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 293, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NMADD_F64x2
2444 { 1538, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NMADD_F32x4_S
2445 { 1537, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 293, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NMADD_F32x4
2446 { 1536, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NMADD_F16x8_S
2447 { 1535, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 293, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NMADD_F16x8
2448 { 1534, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_I8x16_S
2449 { 1533, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_I8x16
2450 { 1532, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_I64x2_S
2451 { 1531, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_I64x2
2452 { 1530, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_I64_S
2453 { 1529, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 420, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_I64
2454 { 1528, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_I32x4_S
2455 { 1527, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_I32x4
2456 { 1526, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_I32_S
2457 { 1525, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_I32
2458 { 1524, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_I16x8_S
2459 { 1523, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_I16x8
2460 { 1522, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_F64x2_S
2461 { 1521, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_F64x2
2462 { 1520, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_F64_S
2463 { 1519, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 417, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_F64
2464 { 1518, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_F32x4_S
2465 { 1517, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_F32x4
2466 { 1516, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_F32_S
2467 { 1515, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 414, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_F32
2468 { 1514, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_F16x8_S
2469 { 1513, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_F16x8
2470 { 1512, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_I8x16_S
2471 { 1511, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_I8x16
2472 { 1510, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_I64x2_S
2473 { 1509, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_I64x2
2474 { 1508, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_I32x4_S
2475 { 1507, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_I32x4
2476 { 1506, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_I16x8_S
2477 { 1505, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_I16x8
2478 { 1504, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_F64x2_S
2479 { 1503, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_F64x2
2480 { 1502, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_F64_S
2481 { 1501, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_F64
2482 { 1500, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_F32x4_S
2483 { 1499, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_F32x4
2484 { 1498, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_F32_S
2485 { 1497, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 157, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_F32
2486 { 1496, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_F16x8_S
2487 { 1495, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_F16x8
2488 { 1494, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEAREST_F64x2_S
2489 { 1493, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEAREST_F64x2
2490 { 1492, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEAREST_F64_S
2491 { 1491, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEAREST_F64
2492 { 1490, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEAREST_F32x4_S
2493 { 1489, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEAREST_F32x4
2494 { 1488, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEAREST_F32_S
2495 { 1487, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 157, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEAREST_F32
2496 { 1486, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEAREST_F16x8_S
2497 { 1485, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEAREST_F16x8
2498 { 1484, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NARROW_U_I8x16_S
2499 { 1483, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NARROW_U_I8x16
2500 { 1482, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NARROW_U_I16x8_S
2501 { 1481, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NARROW_U_I16x8
2502 { 1480, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NARROW_S_I8x16_S
2503 { 1479, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NARROW_S_I8x16
2504 { 1478, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NARROW_S_I16x8_S
2505 { 1477, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NARROW_S_I16x8
2506 { 1476, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_I64x2_S
2507 { 1475, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_I64x2
2508 { 1474, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_I64_S
2509 { 1473, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_I64
2510 { 1472, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_I32x4_S
2511 { 1471, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_I32x4
2512 { 1470, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_I32_S
2513 { 1469, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_I32
2514 { 1468, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_I16x8_S
2515 { 1467, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_I16x8
2516 { 1466, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_F64x2_S
2517 { 1465, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_F64x2
2518 { 1464, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_F64_S
2519 { 1463, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 167, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_F64
2520 { 1462, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_F32x4_S
2521 { 1461, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_F32x4
2522 { 1460, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_F32_S
2523 { 1459, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 164, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_F32
2524 { 1458, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_F16x8_S
2525 { 1457, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_F16x8
2526 { 1456, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_U_I8x16_S
2527 { 1455, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_U_I8x16
2528 { 1454, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_U_I32x4_S
2529 { 1453, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_U_I32x4
2530 { 1452, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_U_I16x8_S
2531 { 1451, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_U_I16x8
2532 { 1450, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_S_I8x16_S
2533 { 1449, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_S_I8x16
2534 { 1448, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_S_I32x4_S
2535 { 1447, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_S_I32x4
2536 { 1446, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_S_I16x8_S
2537 { 1445, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_S_I16x8
2538 { 1444, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_F64x2_S
2539 { 1443, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_F64x2
2540 { 1442, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_F64_S
2541 { 1441, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 167, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_F64
2542 { 1440, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_F32x4_S
2543 { 1439, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_F32x4
2544 { 1438, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_F32_S
2545 { 1437, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 164, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_F32
2546 { 1436, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_F16x8_S
2547 { 1435, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_F16x8
2548 { 1434, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 319, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMSET_A64_S
2549 { 1433, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 666, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMSET_A64
2550 { 1432, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 319, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMSET_A32_S
2551 { 1431, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 662, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMSET_A32
2552 { 1430, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 627, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_INIT_A64_S
2553 { 1429, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 670, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_INIT_A64
2554 { 1428, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 627, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_INIT_A32_S
2555 { 1427, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 622, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_INIT_A32
2556 { 1426, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 319, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_FILL_A64_S
2557 { 1425, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 666, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_FILL_A64
2558 { 1424, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 319, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_FILL_A32_S
2559 { 1423, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 662, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_FILL_A32
2560 { 1422, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 627, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_COPY_A64_S
2561 { 1421, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 629, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_COPY_A64
2562 { 1420, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 627, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_COPY_A32_S
2563 { 1419, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 622, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_COPY_A32
2564 { 1418, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_ATOMIC_WAIT64_A64_S
2565 { 1417, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 655, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_ATOMIC_WAIT64_A64
2566 { 1416, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_ATOMIC_WAIT64_A32_S
2567 { 1415, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 648, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_ATOMIC_WAIT64_A32
2568 { 1414, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_ATOMIC_WAIT32_A64_S
2569 { 1413, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 641, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_ATOMIC_WAIT32_A64
2570 { 1412, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_ATOMIC_WAIT32_A32_S
2571 { 1411, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 634, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_ATOMIC_WAIT32_A32
2572 { 1410, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_ATOMIC_NOTIFY_A64_S
2573 { 1409, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_ATOMIC_NOTIFY_A64
2574 { 1408, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_ATOMIC_NOTIFY_A32_S
2575 { 1407, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_ATOMIC_NOTIFY_A32
2576 { 1406, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 627, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMCPY_A64_S
2577 { 1405, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 629, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMCPY_A64
2578 { 1404, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 627, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMCPY_A32_S
2579 { 1403, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 622, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMCPY_A32
2580 { 1402, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_U_I8x16_S
2581 { 1401, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_U_I8x16
2582 { 1400, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_U_I32x4_S
2583 { 1399, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_U_I32x4
2584 { 1398, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_U_I16x8_S
2585 { 1397, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_U_I16x8
2586 { 1396, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_S_I8x16_S
2587 { 1395, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_S_I8x16
2588 { 1394, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_S_I32x4_S
2589 { 1393, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_S_I32x4
2590 { 1392, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_S_I16x8_S
2591 { 1391, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_S_I16x8
2592 { 1390, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_F64x2_S
2593 { 1389, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_F64x2
2594 { 1388, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_F64_S
2595 { 1387, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 167, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_F64
2596 { 1386, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_F32x4_S
2597 { 1385, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_F32x4
2598 { 1384, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_F32_S
2599 { 1383, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 164, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_F32
2600 { 1382, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_F16x8_S
2601 { 1381, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_F16x8
2602 { 1380, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MADD_F64x2_S
2603 { 1379, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 293, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MADD_F64x2
2604 { 1378, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MADD_F32x4_S
2605 { 1377, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 293, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MADD_F32x4
2606 { 1376, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MADD_F16x8_S
2607 { 1375, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 293, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MADD_F16x8
2608 { 1374, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_U_I8x16_S
2609 { 1373, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_U_I8x16
2610 { 1372, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_U_I64_S
2611 { 1371, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 420, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_U_I64
2612 { 1370, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_U_I32x4_S
2613 { 1369, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_U_I32x4
2614 { 1368, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_U_I32_S
2615 { 1367, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_U_I32
2616 { 1366, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_U_I16x8_S
2617 { 1365, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_U_I16x8
2618 { 1364, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_S_I8x16_S
2619 { 1363, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_S_I8x16
2620 { 1362, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_S_I64x2_S
2621 { 1361, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_S_I64x2
2622 { 1360, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_S_I64_S
2623 { 1359, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 420, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_S_I64
2624 { 1358, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_S_I32x4_S
2625 { 1357, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_S_I32x4
2626 { 1356, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_S_I32_S
2627 { 1355, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_S_I32
2628 { 1354, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_S_I16x8_S
2629 { 1353, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_S_I16x8
2630 { 1352, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_F64x2_S
2631 { 1351, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_F64x2
2632 { 1350, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_F64_S
2633 { 1349, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 417, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_F64
2634 { 1348, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_F32x4_S
2635 { 1347, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_F32x4
2636 { 1346, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_F32_S
2637 { 1345, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 414, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_F32
2638 { 1344, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_F16x8_S
2639 { 1343, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_F16x8
2640 { 1342, 1, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 297, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOOP_S
2641 { 1341, 1, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 297, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOOP
2642 { 1340, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 567, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_V128_S
2643 { 1339, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 619, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_V128
2644 { 1338, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 567, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_I64_S
2645 { 1337, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 616, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_I64
2646 { 1336, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 567, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_I32_S
2647 { 1335, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 613, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_I32
2648 { 1334, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 567, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_FUNCREF_S
2649 { 1333, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 610, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_FUNCREF
2650 { 1332, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 567, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_F64_S
2651 { 1331, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 607, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_F64
2652 { 1330, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 567, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_F32_S
2653 { 1329, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 604, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_F32
2654 { 1328, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 567, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_EXTERNREF_S
2655 { 1327, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 601, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_EXTERNREF
2656 { 1326, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 567, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_EXNREF_S
2657 { 1325, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 598, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_EXNREF
2658 { 1324, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 567, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_V128_S
2659 { 1323, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 596, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_V128
2660 { 1322, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 567, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_I64_S
2661 { 1321, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 594, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_I64
2662 { 1320, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 567, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_I32_S
2663 { 1319, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 592, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_I32
2664 { 1318, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 567, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_FUNCREF_S
2665 { 1317, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 590, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_FUNCREF
2666 { 1316, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 567, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_F64_S
2667 { 1315, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 588, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_F64
2668 { 1314, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 567, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_F32_S
2669 { 1313, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 586, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_F32
2670 { 1312, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 567, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_EXTERNREF_S
2671 { 1311, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 584, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_EXTERNREF
2672 { 1310, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 567, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_EXNREF_S
2673 { 1309, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 582, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_EXNREF
2674 { 1308, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 567, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_V128_S
2675 { 1307, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 580, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_V128
2676 { 1306, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 567, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_I64_S
2677 { 1305, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 578, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_I64
2678 { 1304, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 567, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_I32_S
2679 { 1303, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 576, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_I32
2680 { 1302, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 567, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_FUNCREF_S
2681 { 1301, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 574, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_FUNCREF
2682 { 1300, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 567, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_F64_S
2683 { 1299, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 572, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_F64
2684 { 1298, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 567, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_F32_S
2685 { 1297, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_F32
2686 { 1296, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 567, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_EXTERNREF_S
2687 { 1295, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 568, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_EXTERNREF
2688 { 1294, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 567, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_EXNREF_S
2689 { 1293, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 565, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_EXNREF
2690 { 1292, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 513, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_ZERO_64_A64_S
2691 { 1291, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 509, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_ZERO_64_A64
2692 { 1290, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 507, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_ZERO_64_A32_S
2693 { 1289, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 503, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_ZERO_64_A32
2694 { 1288, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 513, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_ZERO_32_A64_S
2695 { 1287, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 509, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_ZERO_32_A64
2696 { 1286, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 507, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_ZERO_32_A32_S
2697 { 1285, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 503, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_ZERO_32_A32
2698 { 1284, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 513, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_V128_A64_S
2699 { 1283, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 509, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_V128_A64
2700 { 1282, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 507, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_V128_A32_S
2701 { 1281, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 503, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_V128_A32
2702 { 1280, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 562, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_8_A64_S
2703 { 1279, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 556, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_8_A64
2704 { 1278, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 553, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_8_A32_S
2705 { 1277, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 547, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_8_A32
2706 { 1276, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 562, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_64_A64_S
2707 { 1275, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 556, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_64_A64
2708 { 1274, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 553, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_64_A32_S
2709 { 1273, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 547, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_64_A32
2710 { 1272, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 562, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_32_A64_S
2711 { 1271, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 556, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_32_A64
2712 { 1270, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 553, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_32_A32_S
2713 { 1269, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 547, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_32_A32
2714 { 1268, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 562, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_16_A64_S
2715 { 1267, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 556, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_16_A64
2716 { 1266, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 553, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_16_A32_S
2717 { 1265, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 547, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_16_A32
2718 { 1264, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 513, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_I64_A64_S
2719 { 1263, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 527, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_I64_A64
2720 { 1262, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 507, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_I64_A32_S
2721 { 1261, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 523, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_I64_A32
2722 { 1260, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 513, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_I32_A64_S
2723 { 1259, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 519, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_I32_A64
2724 { 1258, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 507, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_I32_A32_S
2725 { 1257, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 515, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_I32_A32
2726 { 1256, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 513, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_F64_A64_S
2727 { 1255, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 543, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_F64_A64
2728 { 1254, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 507, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_F64_A32_S
2729 { 1253, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 539, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_F64_A32
2730 { 1252, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 513, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_F32_A64_S
2731 { 1251, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 535, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_F32_A64
2732 { 1250, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 507, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_F32_A32_S
2733 { 1249, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 531, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_F32_A32
2734 { 1248, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 513, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_F16_F32_A64_S
2735 { 1247, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 535, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_F16_F32_A64
2736 { 1246, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 507, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_F16_F32_A32_S
2737 { 1245, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 531, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_F16_F32_A32
2738 { 1244, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 513, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_U_I64x2_A64_S
2739 { 1243, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 509, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_U_I64x2_A64
2740 { 1242, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 507, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_U_I64x2_A32_S
2741 { 1241, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 503, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_U_I64x2_A32
2742 { 1240, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 513, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_U_I32x4_A64_S
2743 { 1239, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 509, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_U_I32x4_A64
2744 { 1238, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 507, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_U_I32x4_A32_S
2745 { 1237, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 503, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_U_I32x4_A32
2746 { 1236, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 513, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_U_I16x8_A64_S
2747 { 1235, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 509, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_U_I16x8_A64
2748 { 1234, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 507, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_U_I16x8_A32_S
2749 { 1233, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 503, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_U_I16x8_A32
2750 { 1232, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 513, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_S_I64x2_A64_S
2751 { 1231, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 509, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_S_I64x2_A64
2752 { 1230, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 507, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_S_I64x2_A32_S
2753 { 1229, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 503, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_S_I64x2_A32
2754 { 1228, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 513, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_S_I32x4_A64_S
2755 { 1227, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 509, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_S_I32x4_A64
2756 { 1226, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 507, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_S_I32x4_A32_S
2757 { 1225, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 503, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_S_I32x4_A32
2758 { 1224, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 513, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_S_I16x8_A64_S
2759 { 1223, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 509, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_S_I16x8_A64
2760 { 1222, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 507, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_S_I16x8_A32_S
2761 { 1221, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 503, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_S_I16x8_A32
2762 { 1220, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 513, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_U_I64_A64_S
2763 { 1219, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 527, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_U_I64_A64
2764 { 1218, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 507, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_U_I64_A32_S
2765 { 1217, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 523, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_U_I64_A32
2766 { 1216, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 513, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_U_I32_A64_S
2767 { 1215, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 519, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_U_I32_A64
2768 { 1214, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 507, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_U_I32_A32_S
2769 { 1213, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 515, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_U_I32_A32
2770 { 1212, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 513, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_S_I64_A64_S
2771 { 1211, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 527, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_S_I64_A64
2772 { 1210, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 507, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_S_I64_A32_S
2773 { 1209, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 523, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_S_I64_A32
2774 { 1208, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 513, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_S_I32_A64_S
2775 { 1207, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 519, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_S_I32_A64
2776 { 1206, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 507, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_S_I32_A32_S
2777 { 1205, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 515, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_S_I32_A32
2778 { 1204, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 513, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_SPLAT_A64_S
2779 { 1203, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 509, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_SPLAT_A64
2780 { 1202, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 507, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_SPLAT_A32_S
2781 { 1201, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 503, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_SPLAT_A32
2782 { 1200, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 513, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD64_SPLAT_A64_S
2783 { 1199, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 509, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD64_SPLAT_A64
2784 { 1198, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 507, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD64_SPLAT_A32_S
2785 { 1197, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 503, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD64_SPLAT_A32
2786 { 1196, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 513, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD32_U_I64_A64_S
2787 { 1195, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 527, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD32_U_I64_A64
2788 { 1194, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 507, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD32_U_I64_A32_S
2789 { 1193, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 523, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD32_U_I64_A32
2790 { 1192, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 513, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD32_S_I64_A64_S
2791 { 1191, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 527, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD32_S_I64_A64
2792 { 1190, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 507, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD32_S_I64_A32_S
2793 { 1189, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 523, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD32_S_I64_A32
2794 { 1188, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 513, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD32_SPLAT_A64_S
2795 { 1187, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 509, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD32_SPLAT_A64
2796 { 1186, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 507, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD32_SPLAT_A32_S
2797 { 1185, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 503, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD32_SPLAT_A32
2798 { 1184, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 513, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_U_I64_A64_S
2799 { 1183, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 527, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_U_I64_A64
2800 { 1182, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 507, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_U_I64_A32_S
2801 { 1181, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 523, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_U_I64_A32
2802 { 1180, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 513, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_U_I32_A64_S
2803 { 1179, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 519, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_U_I32_A64
2804 { 1178, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 507, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_U_I32_A32_S
2805 { 1177, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 515, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_U_I32_A32
2806 { 1176, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 513, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_S_I64_A64_S
2807 { 1175, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 527, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_S_I64_A64
2808 { 1174, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 507, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_S_I64_A32_S
2809 { 1173, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 523, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_S_I64_A32
2810 { 1172, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 513, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_S_I32_A64_S
2811 { 1171, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 519, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_S_I32_A64
2812 { 1170, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 507, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_S_I32_A32_S
2813 { 1169, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 515, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_S_I32_A32
2814 { 1168, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 513, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_SPLAT_A64_S
2815 { 1167, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 509, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_SPLAT_A64
2816 { 1166, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 507, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_SPLAT_A32_S
2817 { 1165, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 503, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_SPLAT_A32
2818 { 1164, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_U_I8x16_S
2819 { 1163, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_U_I8x16
2820 { 1162, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_U_I64_S
2821 { 1161, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 420, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_U_I64
2822 { 1160, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_U_I32x4_S
2823 { 1159, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_U_I32x4
2824 { 1158, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_U_I32_S
2825 { 1157, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_U_I32
2826 { 1156, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_U_I16x8_S
2827 { 1155, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_U_I16x8
2828 { 1154, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_S_I8x16_S
2829 { 1153, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_S_I8x16
2830 { 1152, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_S_I64x2_S
2831 { 1151, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_S_I64x2
2832 { 1150, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_S_I64_S
2833 { 1149, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 420, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_S_I64
2834 { 1148, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_S_I32x4_S
2835 { 1147, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_S_I32x4
2836 { 1146, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_S_I32_S
2837 { 1145, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_S_I32
2838 { 1144, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_S_I16x8_S
2839 { 1143, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_S_I16x8
2840 { 1142, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_F64x2_S
2841 { 1141, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_F64x2
2842 { 1140, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_F64_S
2843 { 1139, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 417, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_F64
2844 { 1138, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_F32x4_S
2845 { 1137, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_F32x4
2846 { 1136, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_F32_S
2847 { 1135, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 414, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_F32
2848 { 1134, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_F16x8_S
2849 { 1133, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_F16x8
2850 { 1132, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LANESELECT_I8x16_S
2851 { 1131, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 293, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LANESELECT_I8x16
2852 { 1130, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LANESELECT_I64x2_S
2853 { 1129, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 293, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LANESELECT_I64x2
2854 { 1128, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LANESELECT_I32x4_S
2855 { 1127, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 293, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LANESELECT_I32x4
2856 { 1126, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LANESELECT_I16x8_S
2857 { 1125, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 293, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LANESELECT_I16x8
2858 { 1124, 1, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 297, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // IF_S
2859 { 1123, 2, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 501, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // IF
2860 { 1122, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_U_SAT_F64_S
2861 { 1121, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 454, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_U_SAT_F64
2862 { 1120, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_U_SAT_F32_S
2863 { 1119, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 452, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_U_SAT_F32
2864 { 1118, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_U_F64_S
2865 { 1117, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 454, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_U_F64
2866 { 1116, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_U_F32_S
2867 { 1115, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 452, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_U_F32
2868 { 1114, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_S_SAT_F64_S
2869 { 1113, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 454, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_S_SAT_F64
2870 { 1112, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_S_SAT_F32_S
2871 { 1111, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 452, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_S_SAT_F32
2872 { 1110, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_S_F64_S
2873 { 1109, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 454, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_S_F64
2874 { 1108, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_S_F32_S
2875 { 1107, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 452, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_S_F32
2876 { 1106, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_SUB128_S
2877 { 1105, 6, 2, 0, 0, 0, 1, WebAssemblyOpInfoBase + 489, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_SUB128
2878 { 1104, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_REINTERPRET_F64_S
2879 { 1103, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 454, 3, 0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_REINTERPRET_F64
2880 { 1102, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_MUL_WIDE_U_S
2881 { 1101, 4, 2, 0, 0, 0, 1, WebAssemblyOpInfoBase + 497, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_MUL_WIDE_U
2882 { 1100, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_MUL_WIDE_S_S
2883 { 1099, 4, 2, 0, 0, 0, 1, WebAssemblyOpInfoBase + 497, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_MUL_WIDE_S
2884 { 1098, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_EXTEND_U_I32_S
2885 { 1097, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 495, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_EXTEND_U_I32
2886 { 1096, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_EXTEND_S_I32_S
2887 { 1095, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 495, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_EXTEND_S_I32
2888 { 1094, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_EXTEND8_S_I64_S
2889 { 1093, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 309, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_EXTEND8_S_I64
2890 { 1092, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_EXTEND32_S_I64_S
2891 { 1091, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 309, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_EXTEND32_S_I64
2892 { 1090, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_EXTEND16_S_I64_S
2893 { 1089, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 309, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_EXTEND16_S_I64
2894 { 1088, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_ADD128_S
2895 { 1087, 6, 2, 0, 0, 0, 1, WebAssemblyOpInfoBase + 489, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_ADD128
2896 { 1086, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_WRAP_I64_S
2897 { 1085, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 412, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_WRAP_I64
2898 { 1084, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_U_SAT_F64_S
2899 { 1083, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 450, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_U_SAT_F64
2900 { 1082, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_U_SAT_F32_S
2901 { 1081, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 448, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_U_SAT_F32
2902 { 1080, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_U_F64_S
2903 { 1079, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 450, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_U_F64
2904 { 1078, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_U_F32_S
2905 { 1077, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 448, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_U_F32
2906 { 1076, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_S_SAT_F64_S
2907 { 1075, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 450, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_S_SAT_F64
2908 { 1074, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_S_SAT_F32_S
2909 { 1073, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 448, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_S_SAT_F32
2910 { 1072, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_S_F64_S
2911 { 1071, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 450, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_S_F64
2912 { 1070, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_S_F32_S
2913 { 1069, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 448, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_S_F32
2914 { 1068, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_REINTERPRET_F32_S
2915 { 1067, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 448, 3, 0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_REINTERPRET_F32
2916 { 1066, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_EXTEND8_S_I32_S
2917 { 1065, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 307, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_EXTEND8_S_I32
2918 { 1064, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_EXTEND16_S_I32_S
2919 { 1063, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 307, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_EXTEND16_S_I32
2920 { 1062, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_U_I8x16_S
2921 { 1061, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_U_I8x16
2922 { 1060, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_U_I64_S
2923 { 1059, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 420, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_U_I64
2924 { 1058, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_U_I32x4_S
2925 { 1057, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_U_I32x4
2926 { 1056, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_U_I32_S
2927 { 1055, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_U_I32
2928 { 1054, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_U_I16x8_S
2929 { 1053, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_U_I16x8
2930 { 1052, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_S_I8x16_S
2931 { 1051, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_S_I8x16
2932 { 1050, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_S_I64x2_S
2933 { 1049, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_S_I64x2
2934 { 1048, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_S_I64_S
2935 { 1047, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 420, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_S_I64
2936 { 1046, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_S_I32x4_S
2937 { 1045, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_S_I32x4
2938 { 1044, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_S_I32_S
2939 { 1043, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_S_I32
2940 { 1042, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_S_I16x8_S
2941 { 1041, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_S_I16x8
2942 { 1040, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_F64x2_S
2943 { 1039, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_F64x2
2944 { 1038, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_F64_S
2945 { 1037, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 417, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_F64
2946 { 1036, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_F32x4_S
2947 { 1035, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_F32x4
2948 { 1034, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_F32_S
2949 { 1033, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 414, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_F32
2950 { 1032, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_F16x8_S
2951 { 1031, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_F16x8
2952 { 1030, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 458, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_V128_S
2953 { 1029, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 487, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_V128
2954 { 1028, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 458, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_I64_S
2955 { 1027, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 485, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_I64
2956 { 1026, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 458, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_I32_S
2957 { 1025, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 483, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_I32
2958 { 1024, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 458, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_FUNCREF_S
2959 { 1023, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 481, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_FUNCREF
2960 { 1022, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 458, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_F64_S
2961 { 1021, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 479, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_F64
2962 { 1020, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 458, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_F32_S
2963 { 1019, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 477, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_F32
2964 { 1018, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 458, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_EXTERNREF_S
2965 { 1017, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 475, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_EXTERNREF
2966 { 1016, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 458, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_EXNREF_S
2967 { 1015, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 473, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_EXNREF
2968 { 1014, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 458, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_V128_S
2969 { 1013, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 471, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_V128
2970 { 1012, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 458, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_I64_S
2971 { 1011, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 469, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_I64
2972 { 1010, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 458, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_I32_S
2973 { 1009, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 467, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_I32
2974 { 1008, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 458, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_FUNCREF_S
2975 { 1007, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 465, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_FUNCREF
2976 { 1006, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 458, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_F64_S
2977 { 1005, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 463, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_F64
2978 { 1004, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 458, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_F32_S
2979 { 1003, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 461, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_F32
2980 { 1002, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 458, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_EXTERNREF_S
2981 { 1001, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 459, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_EXTERNREF
2982 { 1000, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 458, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_EXNREF_S
2983 { 999, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 456, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_EXNREF
2984 { 998, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_U_I8x16_S
2985 { 997, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_U_I8x16
2986 { 996, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_U_I64_S
2987 { 995, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 420, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_U_I64
2988 { 994, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_U_I32x4_S
2989 { 993, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_U_I32x4
2990 { 992, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_U_I32_S
2991 { 991, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_U_I32
2992 { 990, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_U_I16x8_S
2993 { 989, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_U_I16x8
2994 { 988, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_S_I8x16_S
2995 { 987, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_S_I8x16
2996 { 986, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_S_I64x2_S
2997 { 985, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_S_I64x2
2998 { 984, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_S_I64_S
2999 { 983, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 420, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_S_I64
3000 { 982, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_S_I32x4_S
3001 { 981, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_S_I32x4
3002 { 980, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_S_I32_S
3003 { 979, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_S_I32
3004 { 978, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_S_I16x8_S
3005 { 977, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_S_I16x8
3006 { 976, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_F64x2_S
3007 { 975, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_F64x2
3008 { 974, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_F64_S
3009 { 973, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 417, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_F64
3010 { 972, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_F32x4_S
3011 { 971, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_F32x4
3012 { 970, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_F32_S
3013 { 969, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 414, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_F32
3014 { 968, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_F16x8_S
3015 { 967, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_F16x8
3016 { 966, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_UINT_I64_F64_S
3017 { 965, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 454, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_UINT_I64_F64
3018 { 964, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_UINT_I64_F32_S
3019 { 963, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 452, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_UINT_I64_F32
3020 { 962, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_UINT_I32_F64_S
3021 { 961, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 450, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_UINT_I32_F64
3022 { 960, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_UINT_I32_F32_S
3023 { 959, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 448, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_UINT_I32_F32
3024 { 958, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_SINT_I64_F64_S
3025 { 957, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 454, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_SINT_I64_F64
3026 { 956, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_SINT_I64_F32_S
3027 { 955, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 452, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_SINT_I64_F32
3028 { 954, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_SINT_I32_F64_S
3029 { 953, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 450, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_SINT_I32_F64
3030 { 952, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_SINT_I32_F32_S
3031 { 951, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 448, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_SINT_I32_F32
3032 { 950, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FLOOR_F64x2_S
3033 { 949, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FLOOR_F64x2
3034 { 948, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FLOOR_F64_S
3035 { 947, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FLOOR_F64
3036 { 946, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FLOOR_F32x4_S
3037 { 945, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FLOOR_F32x4
3038 { 944, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FLOOR_F32_S
3039 { 943, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 157, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FLOOR_F32
3040 { 942, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FLOOR_F16x8_S
3041 { 941, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FLOOR_F16x8
3042 { 940, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FALLTHROUGH_RETURN_S
3043 { 939, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FALLTHROUGH_RETURN
3044 { 938, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F64_REINTERPRET_I64_S
3045 { 937, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 444, 3, 0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F64_REINTERPRET_I64
3046 { 936, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F64_PROMOTE_F32_S
3047 { 935, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 446, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F64_PROMOTE_F32
3048 { 934, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F64_CONVERT_U_I64_S
3049 { 933, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 444, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F64_CONVERT_U_I64
3050 { 932, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F64_CONVERT_U_I32_S
3051 { 931, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 442, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F64_CONVERT_U_I32
3052 { 930, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F64_CONVERT_S_I64_S
3053 { 929, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 444, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F64_CONVERT_S_I64
3054 { 928, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F64_CONVERT_S_I32_S
3055 { 927, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 442, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F64_CONVERT_S_I32
3056 { 926, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F32_REINTERPRET_I32_S
3057 { 925, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 436, 3, 0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F32_REINTERPRET_I32
3058 { 924, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F32_DEMOTE_F64_S
3059 { 923, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 440, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F32_DEMOTE_F64
3060 { 922, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F32_CONVERT_U_I64_S
3061 { 921, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 438, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F32_CONVERT_U_I64
3062 { 920, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F32_CONVERT_U_I32_S
3063 { 919, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 436, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F32_CONVERT_U_I32
3064 { 918, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F32_CONVERT_S_I64_S
3065 { 917, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 438, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F32_CONVERT_S_I64
3066 { 916, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F32_CONVERT_S_I32_S
3067 { 915, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 436, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F32_CONVERT_S_I32
3068 { 914, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 426, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_I8x16_u_S
3069 { 913, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 430, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_I8x16_u
3070 { 912, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 426, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_I8x16_s_S
3071 { 911, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 430, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_I8x16_s
3072 { 910, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 426, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_I64x2_S
3073 { 909, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 433, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_I64x2
3074 { 908, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 426, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_I32x4_S
3075 { 907, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 430, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_I32x4
3076 { 906, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 426, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_I16x8_u_S
3077 { 905, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 430, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_I16x8_u
3078 { 904, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 426, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_I16x8_s_S
3079 { 903, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 430, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_I16x8_s
3080 { 902, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 426, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_F64x2_S
3081 { 901, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 427, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_F64x2
3082 { 900, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 426, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_F32x4_S
3083 { 899, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 423, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_F32x4
3084 { 898, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 426, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_F16x8_S
3085 { 897, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 423, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_F16x8
3086 { 896, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_LOW_U_I64x2_S
3087 { 895, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_LOW_U_I64x2
3088 { 894, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_LOW_U_I32x4_S
3089 { 893, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_LOW_U_I32x4
3090 { 892, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_LOW_U_I16x8_S
3091 { 891, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_LOW_U_I16x8
3092 { 890, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_LOW_S_I64x2_S
3093 { 889, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_LOW_S_I64x2
3094 { 888, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_LOW_S_I32x4_S
3095 { 887, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_LOW_S_I32x4
3096 { 886, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_LOW_S_I16x8_S
3097 { 885, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_LOW_S_I16x8
3098 { 884, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_HIGH_U_I64x2_S
3099 { 883, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_HIGH_U_I64x2
3100 { 882, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_HIGH_U_I32x4_S
3101 { 881, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_HIGH_U_I32x4
3102 { 880, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_HIGH_U_I16x8_S
3103 { 879, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_HIGH_U_I16x8
3104 { 878, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_HIGH_S_I64x2_S
3105 { 877, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_HIGH_S_I64x2
3106 { 876, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_HIGH_S_I32x4_S
3107 { 875, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_HIGH_S_I32x4
3108 { 874, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_HIGH_S_I16x8_S
3109 { 873, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_HIGH_S_I16x8
3110 { 872, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_I8x16_S
3111 { 871, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_I8x16
3112 { 870, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_I64x2_S
3113 { 869, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_I64x2
3114 { 868, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_I64_S
3115 { 867, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 420, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_I64
3116 { 866, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_I32x4_S
3117 { 865, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_I32x4
3118 { 864, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_I32_S
3119 { 863, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_I32
3120 { 862, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_I16x8_S
3121 { 861, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_I16x8
3122 { 860, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_F64x2_S
3123 { 859, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_F64x2
3124 { 858, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_F64_S
3125 { 857, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 417, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_F64
3126 { 856, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_F32x4_S
3127 { 855, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_F32x4
3128 { 854, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_F32_S
3129 { 853, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 414, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_F32
3130 { 852, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_F16x8_S
3131 { 851, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_F16x8
3132 { 850, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQZ_I64_S
3133 { 849, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 412, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQZ_I64
3134 { 848, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQZ_I32_S
3135 { 847, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 307, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQZ_I32
3136 { 846, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_TRY_TABLE_S
3137 { 845, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_TRY_TABLE
3138 { 844, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_TRY_S
3139 { 843, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_TRY
3140 { 842, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_S
3141 { 841, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_LOOP_S
3142 { 840, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_LOOP
3143 { 839, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_IF_S
3144 { 838, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_IF
3145 { 837, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_FUNCTION_S
3146 { 836, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_FUNCTION
3147 { 835, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_BLOCK_S
3148 { 834, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_BLOCK
3149 { 833, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END
3150 { 832, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ELSE_S
3151 { 831, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ELSE
3152 { 830, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_V128_S
3153 { 829, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 411, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_V128
3154 { 828, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_I64_S
3155 { 827, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 302, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_I64
3156 { 826, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_I32_S
3157 { 825, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 300, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_I32
3158 { 824, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_FUNCREF_S
3159 { 823, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 410, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_FUNCREF
3160 { 822, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_F64_S
3161 { 821, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 409, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_F64
3162 { 820, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_F32_S
3163 { 819, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 408, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_F32
3164 { 818, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_EXTERNREF_S
3165 { 817, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 407, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_EXTERNREF
3166 { 816, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_EXNREF_S
3167 { 815, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 306, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_EXNREF
3168 { 814, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DOT_S
3169 { 813, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DOT
3170 { 812, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_U_I64_S
3171 { 811, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_U_I64
3172 { 810, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_U_I32_S
3173 { 809, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_U_I32
3174 { 808, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_S_I64_S
3175 { 807, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_S_I64
3176 { 806, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_S_I32_S
3177 { 805, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_S_I32
3178 { 804, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_F64x2_S
3179 { 803, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_F64x2
3180 { 802, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_F64_S
3181 { 801, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 167, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_F64
3182 { 800, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_F32x4_S
3183 { 799, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_F32x4
3184 { 798, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_F32_S
3185 { 797, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 164, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_F32
3186 { 796, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_F16x8_S
3187 { 795, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_F16x8
3188 { 794, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 154, 3, 0|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DELEGATE_S
3189 { 793, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 154, 3, 0|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DELEGATE
3190 { 792, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Trap)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DEBUG_UNREACHABLE_S
3191 { 791, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Trap)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DEBUG_UNREACHABLE
3192 { 790, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 319, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DATA_DROP_S
3193 { 789, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 319, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DATA_DROP
3194 { 788, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CTZ_I64_S
3195 { 787, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 309, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CTZ_I64
3196 { 786, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CTZ_I32_S
3197 { 785, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 307, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CTZ_I32
3198 { 784, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_V128_S
3199 { 783, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_V128
3200 { 782, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_I64_S
3201 { 781, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 309, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_I64
3202 { 780, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_I32_S
3203 { 779, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 307, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_I32
3204 { 778, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_FUNCREF_S
3205 { 777, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 405, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_FUNCREF
3206 { 776, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_F64_S
3207 { 775, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_F64
3208 { 774, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_F32_S
3209 { 773, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 157, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_F32
3210 { 772, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_EXTERNREF_S
3211 { 771, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 403, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_EXTERNREF
3212 { 770, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_EXNREF_S
3213 { 769, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 401, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_EXNREF
3214 { 768, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPYSIGN_F64_S
3215 { 767, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 167, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPYSIGN_F64
3216 { 766, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPYSIGN_F32_S
3217 { 765, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 164, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPYSIGN_F32
3218 { 764, 16, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 385, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_V128_I8x16_S
3219 { 763, 17, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 368, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_V128_I8x16
3220 { 762, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 366, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_V128_I64x2_S
3221 { 761, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 363, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_V128_I64x2
3222 { 760, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 359, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_V128_I32x4_S
3223 { 759, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 354, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_V128_I32x4
3224 { 758, 8, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 346, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_V128_I16x8_S
3225 { 757, 9, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 337, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_V128_I16x8
3226 { 756, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 335, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_V128_F64x2_S
3227 { 755, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 332, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_V128_F64x2
3228 { 754, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 328, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_V128_F32x4_S
3229 { 753, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 323, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_V128_F32x4
3230 { 752, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 322, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_I64_S
3231 { 751, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 320, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_I64
3232 { 750, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 319, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_I32_S
3233 { 749, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 317, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_I32
3234 { 748, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 316, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_F64_S
3235 { 747, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 314, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_F64
3236 { 746, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 313, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_F32_S
3237 { 745, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 311, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_F32
3238 { 744, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLZ_I64_S
3239 { 743, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 309, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLZ_I64
3240 { 742, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLZ_I32_S
3241 { 741, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 307, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLZ_I32
3242 { 740, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CEIL_F64x2_S
3243 { 739, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CEIL_F64x2
3244 { 738, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CEIL_F64_S
3245 { 737, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CEIL_F64
3246 { 736, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CEIL_F32x4_S
3247 { 735, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CEIL_F32x4
3248 { 734, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CEIL_F32_S
3249 { 733, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 157, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CEIL_F32
3250 { 732, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CEIL_F16x8_S
3251 { 731, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CEIL_F16x8
3252 { 730, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 305, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CATCH_S
3253 { 729, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 305, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CATCH_REF_S
3254 { 728, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 305, 3, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CATCH_REF
3255 { 727, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 305, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CATCH_LEGACY_S
3256 { 726, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 305, 3, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CATCH_LEGACY
3257 { 725, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CATCH_ALL_S
3258 { 724, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CATCH_ALL_REF_S
3259 { 723, 1, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 306, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CATCH_ALL_REF
3260 { 722, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CATCH_ALL_LEGACY_S
3261 { 721, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CATCH_ALL_LEGACY
3262 { 720, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CATCH_ALL
3263 { 719, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 305, 3, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CATCH
3264 { 718, 1, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 151, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CALL_S
3265 { 717, 2, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 303, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CALL_INDIRECT_S
3266 { 716, 2, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 303, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CALL_INDIRECT
3267 { 715, 1, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 151, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CALL
3268 { 714, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 154, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BR_UNLESS_S
3269 { 713, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 298, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BR_UNLESS
3270 { 712, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 301, 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BR_TABLE_I64_S
3271 { 711, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 302, 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BR_TABLE_I64
3272 { 710, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 301, 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BR_TABLE_I32_S
3273 { 709, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 300, 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BR_TABLE_I32
3274 { 708, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 154, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BR_S
3275 { 707, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 154, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BR_IF_S
3276 { 706, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 298, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BR_IF
3277 { 705, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 154, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BR
3278 { 704, 1, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 297, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLOCK_S
3279 { 703, 1, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 297, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLOCK
3280 { 702, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BITSELECT_S
3281 { 701, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 293, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BITSELECT
3282 { 700, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BITMASK_I8x16_S
3283 { 699, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 176, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BITMASK_I8x16
3284 { 698, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BITMASK_I64x2_S
3285 { 697, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 176, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BITMASK_I64x2
3286 { 696, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BITMASK_I32x4_S
3287 { 695, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 176, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BITMASK_I32x4
3288 { 694, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BITMASK_I16x8_S
3289 { 693, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 176, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BITMASK_I16x8
3290 { 692, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AVGR_U_I8x16_S
3291 { 691, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AVGR_U_I8x16
3292 { 690, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AVGR_U_I16x8_S
3293 { 689, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AVGR_U_I16x8
3294 { 688, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE_I64_A64_S
3295 { 687, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 288, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE_I64_A64
3296 { 686, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE_I64_A32_S
3297 { 685, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 283, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE_I64_A32
3298 { 684, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE_I32_A64_S
3299 { 683, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 278, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE_I32_A64
3300 { 682, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE_I32_A32_S
3301 { 681, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 273, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE_I32_A32
3302 { 680, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE8_I64_A64_S
3303 { 679, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 288, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE8_I64_A64
3304 { 678, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE8_I64_A32_S
3305 { 677, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 283, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE8_I64_A32
3306 { 676, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE8_I32_A64_S
3307 { 675, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 278, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE8_I32_A64
3308 { 674, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE8_I32_A32_S
3309 { 673, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 273, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE8_I32_A32
3310 { 672, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE32_I64_A64_S
3311 { 671, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 288, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE32_I64_A64
3312 { 670, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE32_I64_A32_S
3313 { 669, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 283, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE32_I64_A32
3314 { 668, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE16_I64_A64_S
3315 { 667, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 288, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE16_I64_A64
3316 { 666, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE16_I64_A32_S
3317 { 665, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 283, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE16_I64_A32
3318 { 664, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE16_I32_A64_S
3319 { 663, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 278, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE16_I32_A64
3320 { 662, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE16_I32_A32_S
3321 { 661, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 273, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE16_I32_A32
3322 { 660, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XOR_I64_A64_S
3323 { 659, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XOR_I64_A64
3324 { 658, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XOR_I64_A32_S
3325 { 657, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XOR_I64_A32
3326 { 656, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XOR_I32_A64_S
3327 { 655, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XOR_I32_A64
3328 { 654, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XOR_I32_A32_S
3329 { 653, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XOR_I32_A32
3330 { 652, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XCHG_I64_A64_S
3331 { 651, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XCHG_I64_A64
3332 { 650, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XCHG_I64_A32_S
3333 { 649, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XCHG_I64_A32
3334 { 648, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XCHG_I32_A64_S
3335 { 647, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XCHG_I32_A64
3336 { 646, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XCHG_I32_A32_S
3337 { 645, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XCHG_I32_A32
3338 { 644, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_SUB_I64_A64_S
3339 { 643, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_SUB_I64_A64
3340 { 642, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_SUB_I64_A32_S
3341 { 641, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_SUB_I64_A32
3342 { 640, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_SUB_I32_A64_S
3343 { 639, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_SUB_I32_A64
3344 { 638, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_SUB_I32_A32_S
3345 { 637, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_SUB_I32_A32
3346 { 636, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_OR_I64_A64_S
3347 { 635, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_OR_I64_A64
3348 { 634, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_OR_I64_A32_S
3349 { 633, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_OR_I64_A32
3350 { 632, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_OR_I32_A64_S
3351 { 631, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_OR_I32_A64
3352 { 630, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_OR_I32_A32_S
3353 { 629, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_OR_I32_A32
3354 { 628, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_CMPXCHG_I64_A64_S
3355 { 627, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 266, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_CMPXCHG_I64_A64
3356 { 626, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_CMPXCHG_I64_A32_S
3357 { 625, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 259, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_CMPXCHG_I64_A32
3358 { 624, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_CMPXCHG_I32_A64_S
3359 { 623, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 252, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_CMPXCHG_I32_A64
3360 { 622, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_CMPXCHG_I32_A32_S
3361 { 621, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 245, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_CMPXCHG_I32_A32
3362 { 620, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_AND_I64_A64_S
3363 { 619, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_AND_I64_A64
3364 { 618, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_AND_I64_A32_S
3365 { 617, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_AND_I64_A32
3366 { 616, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_AND_I32_A64_S
3367 { 615, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_AND_I32_A64
3368 { 614, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_AND_I32_A32_S
3369 { 613, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_AND_I32_A32
3370 { 612, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_ADD_I64_A64_S
3371 { 611, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_ADD_I64_A64
3372 { 610, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_ADD_I64_A32_S
3373 { 609, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_ADD_I64_A32
3374 { 608, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_ADD_I32_A64_S
3375 { 607, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_ADD_I32_A64
3376 { 606, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_ADD_I32_A32_S
3377 { 605, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_ADD_I32_A32
3378 { 604, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XOR_I64_A64_S
3379 { 603, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XOR_I64_A64
3380 { 602, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XOR_I64_A32_S
3381 { 601, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XOR_I64_A32
3382 { 600, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XOR_I32_A64_S
3383 { 599, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XOR_I32_A64
3384 { 598, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XOR_I32_A32_S
3385 { 597, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XOR_I32_A32
3386 { 596, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XCHG_I64_A64_S
3387 { 595, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XCHG_I64_A64
3388 { 594, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XCHG_I64_A32_S
3389 { 593, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XCHG_I64_A32
3390 { 592, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XCHG_I32_A64_S
3391 { 591, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XCHG_I32_A64
3392 { 590, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XCHG_I32_A32_S
3393 { 589, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XCHG_I32_A32
3394 { 588, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_SUB_I64_A64_S
3395 { 587, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_SUB_I64_A64
3396 { 586, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_SUB_I64_A32_S
3397 { 585, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_SUB_I64_A32
3398 { 584, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_SUB_I32_A64_S
3399 { 583, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_SUB_I32_A64
3400 { 582, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_SUB_I32_A32_S
3401 { 581, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_SUB_I32_A32
3402 { 580, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_OR_I64_A64_S
3403 { 579, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_OR_I64_A64
3404 { 578, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_OR_I64_A32_S
3405 { 577, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_OR_I64_A32
3406 { 576, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_OR_I32_A64_S
3407 { 575, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_OR_I32_A64
3408 { 574, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_OR_I32_A32_S
3409 { 573, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_OR_I32_A32
3410 { 572, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_CMPXCHG_I64_A64_S
3411 { 571, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 266, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_CMPXCHG_I64_A64
3412 { 570, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_CMPXCHG_I64_A32_S
3413 { 569, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 259, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_CMPXCHG_I64_A32
3414 { 568, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_CMPXCHG_I32_A64_S
3415 { 567, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 252, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_CMPXCHG_I32_A64
3416 { 566, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_CMPXCHG_I32_A32_S
3417 { 565, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 245, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_CMPXCHG_I32_A32
3418 { 564, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_AND_I64_A64_S
3419 { 563, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_AND_I64_A64
3420 { 562, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_AND_I64_A32_S
3421 { 561, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_AND_I64_A32
3422 { 560, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_AND_I32_A64_S
3423 { 559, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_AND_I32_A64
3424 { 558, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_AND_I32_A32_S
3425 { 557, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_AND_I32_A32
3426 { 556, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_ADD_I64_A64_S
3427 { 555, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_ADD_I64_A64
3428 { 554, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_ADD_I64_A32_S
3429 { 553, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_ADD_I64_A32
3430 { 552, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_ADD_I32_A64_S
3431 { 551, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_ADD_I32_A64
3432 { 550, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_ADD_I32_A32_S
3433 { 549, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_ADD_I32_A32
3434 { 548, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_XOR_I64_A64_S
3435 { 547, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_XOR_I64_A64
3436 { 546, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_XOR_I64_A32_S
3437 { 545, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_XOR_I64_A32
3438 { 544, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_XCHG_I64_A64_S
3439 { 543, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_XCHG_I64_A64
3440 { 542, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_XCHG_I64_A32_S
3441 { 541, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_XCHG_I64_A32
3442 { 540, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_SUB_I64_A64_S
3443 { 539, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_SUB_I64_A64
3444 { 538, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_SUB_I64_A32_S
3445 { 537, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_SUB_I64_A32
3446 { 536, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_OR_I64_A64_S
3447 { 535, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_OR_I64_A64
3448 { 534, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_OR_I64_A32_S
3449 { 533, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_OR_I64_A32
3450 { 532, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_CMPXCHG_I64_A64_S
3451 { 531, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 266, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_CMPXCHG_I64_A64
3452 { 530, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_CMPXCHG_I64_A32_S
3453 { 529, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 259, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_CMPXCHG_I64_A32
3454 { 528, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_AND_I64_A64_S
3455 { 527, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_AND_I64_A64
3456 { 526, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_AND_I64_A32_S
3457 { 525, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_AND_I64_A32
3458 { 524, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_ADD_I64_A64_S
3459 { 523, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_ADD_I64_A64
3460 { 522, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_ADD_I64_A32_S
3461 { 521, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_ADD_I64_A32
3462 { 520, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XOR_I64_A64_S
3463 { 519, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XOR_I64_A64
3464 { 518, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XOR_I64_A32_S
3465 { 517, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XOR_I64_A32
3466 { 516, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XOR_I32_A64_S
3467 { 515, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XOR_I32_A64
3468 { 514, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XOR_I32_A32_S
3469 { 513, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XOR_I32_A32
3470 { 512, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XCHG_I64_A64_S
3471 { 511, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XCHG_I64_A64
3472 { 510, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XCHG_I64_A32_S
3473 { 509, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XCHG_I64_A32
3474 { 508, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XCHG_I32_A64_S
3475 { 507, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XCHG_I32_A64
3476 { 506, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XCHG_I32_A32_S
3477 { 505, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XCHG_I32_A32
3478 { 504, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_SUB_I64_A64_S
3479 { 503, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_SUB_I64_A64
3480 { 502, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_SUB_I64_A32_S
3481 { 501, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_SUB_I64_A32
3482 { 500, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_SUB_I32_A64_S
3483 { 499, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_SUB_I32_A64
3484 { 498, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_SUB_I32_A32_S
3485 { 497, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_SUB_I32_A32
3486 { 496, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_OR_I64_A64_S
3487 { 495, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_OR_I64_A64
3488 { 494, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_OR_I64_A32_S
3489 { 493, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_OR_I64_A32
3490 { 492, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_OR_I32_A64_S
3491 { 491, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_OR_I32_A64
3492 { 490, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_OR_I32_A32_S
3493 { 489, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_OR_I32_A32
3494 { 488, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_CMPXCHG_I64_A64_S
3495 { 487, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 266, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_CMPXCHG_I64_A64
3496 { 486, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_CMPXCHG_I64_A32_S
3497 { 485, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 259, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_CMPXCHG_I64_A32
3498 { 484, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_CMPXCHG_I32_A64_S
3499 { 483, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 252, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_CMPXCHG_I32_A64
3500 { 482, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_CMPXCHG_I32_A32_S
3501 { 481, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 245, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_CMPXCHG_I32_A32
3502 { 480, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_AND_I64_A64_S
3503 { 479, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_AND_I64_A64
3504 { 478, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_AND_I64_A32_S
3505 { 477, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_AND_I64_A32
3506 { 476, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_AND_I32_A64_S
3507 { 475, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_AND_I32_A64
3508 { 474, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_AND_I32_A32_S
3509 { 473, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_AND_I32_A32
3510 { 472, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_ADD_I64_A64_S
3511 { 471, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_ADD_I64_A64
3512 { 470, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_ADD_I64_A32_S
3513 { 469, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_ADD_I64_A32
3514 { 468, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_ADD_I32_A64_S
3515 { 467, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_ADD_I32_A64
3516 { 466, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_ADD_I32_A32_S
3517 { 465, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_ADD_I32_A32
3518 { 464, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD_I64_A64_S
3519 { 463, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 216, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD_I64_A64
3520 { 462, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD_I64_A32_S
3521 { 461, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 211, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD_I64_A32
3522 { 460, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD_I32_A64_S
3523 { 459, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 203, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD_I32_A64
3524 { 458, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD_I32_A32_S
3525 { 457, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 195, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD_I32_A32
3526 { 456, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD8_U_I64_A64_S
3527 { 455, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 216, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD8_U_I64_A64
3528 { 454, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD8_U_I64_A32_S
3529 { 453, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 211, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD8_U_I64_A32
3530 { 452, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD8_U_I32_A64_S
3531 { 451, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 203, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD8_U_I32_A64
3532 { 450, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD8_U_I32_A32_S
3533 { 449, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 195, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD8_U_I32_A32
3534 { 448, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD32_U_I64_A64_S
3535 { 447, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 216, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD32_U_I64_A64
3536 { 446, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD32_U_I64_A32_S
3537 { 445, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 211, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD32_U_I64_A32
3538 { 444, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD16_U_I64_A64_S
3539 { 443, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 216, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD16_U_I64_A64
3540 { 442, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD16_U_I64_A32_S
3541 { 441, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 211, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD16_U_I64_A32
3542 { 440, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD16_U_I32_A64_S
3543 { 439, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 203, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD16_U_I32_A64
3544 { 438, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD16_U_I32_A32_S
3545 { 437, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 195, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD16_U_I32_A32
3546 { 436, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 194, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_FENCE_S
3547 { 435, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 194, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_FENCE
3548 { 434, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v8i16_S
3549 { 433, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 192, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v8i16
3550 { 432, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v8f16_S
3551 { 431, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 192, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v8f16
3552 { 430, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v4i32_S
3553 { 429, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 192, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v4i32
3554 { 428, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v4f32_S
3555 { 427, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 192, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v4f32
3556 { 426, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v2i64_S
3557 { 425, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 192, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v2i64
3558 { 424, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v2f64_S
3559 { 423, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 192, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v2f64
3560 { 422, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v16i8_S
3561 { 421, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 192, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v16i8
3562 { 420, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_i64_S
3563 { 419, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 190, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_i64
3564 { 418, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_i32_S
3565 { 417, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 188, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_i32
3566 { 416, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_funcref_S
3567 { 415, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 186, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_funcref
3568 { 414, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_f64_S
3569 { 413, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 184, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_f64
3570 { 412, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_f32_S
3571 { 411, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 182, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_f32
3572 { 410, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_externref_S
3573 { 409, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 180, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_externref
3574 { 408, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_exnref_S
3575 { 407, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 178, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_exnref
3576 { 406, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANYTRUE_S
3577 { 405, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 176, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANYTRUE
3578 { 404, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_S
3579 { 403, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_I64_S
3580 { 402, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_I64
3581 { 401, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_I32_S
3582 { 400, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_I32
3583 { 399, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANDNOT_S
3584 { 398, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANDNOT
3585 { 397, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND
3586 { 396, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ALLTRUE_I8x16_S
3587 { 395, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 176, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ALLTRUE_I8x16
3588 { 394, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ALLTRUE_I64x2_S
3589 { 393, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 176, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ALLTRUE_I64x2
3590 { 392, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ALLTRUE_I32x4_S
3591 { 391, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 176, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ALLTRUE_I32x4
3592 { 390, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ALLTRUE_I16x8_S
3593 { 389, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 176, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ALLTRUE_I16x8
3594 { 388, 2, 0, 0, 0, 2, 2, WebAssemblyOpInfoBase + 20, 4, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKUP_S
3595 { 387, 2, 0, 0, 0, 2, 2, WebAssemblyOpInfoBase + 20, 4, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKUP
3596 { 386, 2, 0, 0, 0, 2, 2, WebAssemblyOpInfoBase + 20, 4, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKDOWN_S
3597 { 385, 2, 0, 0, 0, 2, 2, WebAssemblyOpInfoBase + 20, 4, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKDOWN
3598 { 384, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_SAT_U_I8x16_S
3599 { 383, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_SAT_U_I8x16
3600 { 382, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_SAT_U_I16x8_S
3601 { 381, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_SAT_U_I16x8
3602 { 380, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_SAT_S_I8x16_S
3603 { 379, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_SAT_S_I8x16
3604 { 378, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_SAT_S_I16x8_S
3605 { 377, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_SAT_S_I16x8
3606 { 376, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I8x16_S
3607 { 375, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I8x16
3608 { 374, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I64x2_S
3609 { 373, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I64x2
3610 { 372, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I64_S
3611 { 371, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I64
3612 { 370, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I32x4_S
3613 { 369, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I32x4
3614 { 368, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I32_S
3615 { 367, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I32
3616 { 366, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I16x8_S
3617 { 365, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I16x8
3618 { 364, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F64x2_S
3619 { 363, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F64x2
3620 { 362, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F64_S
3621 { 361, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 167, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F64
3622 { 360, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F32x4_S
3623 { 359, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F32x4
3624 { 358, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F32_S
3625 { 357, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 164, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F32
3626 { 356, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F16x8_S
3627 { 355, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F16x8
3628 { 354, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_I8x16_S
3629 { 353, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_I8x16
3630 { 352, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_I64x2_S
3631 { 351, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_I64x2
3632 { 350, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_I32x4_S
3633 { 349, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_I32x4
3634 { 348, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_I16x8_S
3635 { 347, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_I16x8
3636 { 346, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_F64x2_S
3637 { 345, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_F64x2
3638 { 344, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_F64_S
3639 { 343, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_F64
3640 { 342, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_F32x4_S
3641 { 341, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_F32x4
3642 { 340, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_F32_S
3643 { 339, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 157, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_F32
3644 { 338, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_F16x8_S
3645 { 337, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_F16x8
3646 { 336, 0, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // RET_CALL_RESULTS_S
3647 { 335, 0, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // RET_CALL_RESULTS
3648 { 334, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COMPILER_FENCE_S
3649 { 333, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COMPILER_FENCE
3650 { 332, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 154, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLEANUPRET_S
3651 { 331, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 154, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLEANUPRET
3652 { 330, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 152, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CATCHRET_S
3653 { 329, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 152, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CATCHRET
3654 { 328, 0, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CALL_RESULTS_S
3655 { 327, 0, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CALL_RESULTS
3656 { 326, 1, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 151, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CALL_PARAMS_S
3657 { 325, 1, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 151, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CALL_PARAMS
3658 { 324, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBFX
3659 { 323, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SBFX
3660 { 322, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMIN
3661 { 321, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMAX
3662 { 320, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMIN
3663 { 319, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMAX
3664 { 318, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_XOR
3665 { 317, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_OR
3666 { 316, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_AND
3667 { 315, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_MUL
3668 { 314, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_ADD
3669 { 313, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMINIMUM
3670 { 312, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAXIMUM
3671 { 311, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMIN
3672 { 310, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAX
3673 { 309, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMUL
3674 { 308, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FADD
3675 { 307, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FMUL
3676 { 306, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FADD
3677 { 305, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBSANTRAP
3678 { 304, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DEBUGTRAP
3679 { 303, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRAP
3680 { 302, 3, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BZERO
3681 { 301, 4, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET
3682 { 300, 4, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMMOVE
3683 { 299, 3, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY_INLINE
3684 { 298, 4, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY
3685 { 297, 2, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 141, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_WRITE_REGISTER
3686 { 296, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_READ_REGISTER
3687 { 295, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FLDEXP
3688 { 294, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSQRT
3689 { 293, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMA
3690 { 292, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FREM
3691 { 291, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FDIV
3692 { 290, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMUL
3693 { 289, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSUB
3694 { 288, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FADD
3695 { 287, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKRESTORE
3696 { 286, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKSAVE
3697 { 285, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DYN_STACKALLOC
3698 { 284, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_JUMP_TABLE
3699 { 283, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BLOCK_ADDR
3700 { 282, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADDRSPACE_CAST
3701 { 281, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEARBYINT
3702 { 280, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRINT
3703 { 279, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFLOOR
3704 { 278, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSQRT
3705 { 277, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTANH
3706 { 276, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINH
3707 { 275, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOSH
3708 { 274, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN2
3709 { 273, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN
3710 { 272, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FASIN
3711 { 271, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FACOS
3712 { 270, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTAN
3713 { 269, 3, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINCOS
3714 { 268, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSIN
3715 { 267, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOS
3716 { 266, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCEIL
3717 { 265, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITREVERSE
3718 { 264, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BSWAP
3719 { 263, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTPOP
3720 { 262, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLS
3721 { 261, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ_ZERO_UNDEF
3722 { 260, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ
3723 { 259, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ_ZERO_UNDEF
3724 { 258, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ
3725 { 257, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 137, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECTOR_COMPRESS
3726 { 256, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STEP_VECTOR
3727 { 255, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SPLAT_VECTOR
3728 { 254, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 133, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHUFFLE_VECTOR
3729 { 253, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_VECTOR_ELT
3730 { 252, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 126, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_VECTOR_ELT
3731 { 251, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_SUBVECTOR
3732 { 250, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_SUBVECTOR
3733 { 249, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VSCALE
3734 { 248, 3, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRJT
3735 { 247, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BR
3736 { 246, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LLROUND
3737 { 245, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LROUND
3738 { 244, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABS
3739 { 243, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMAX
3740 { 242, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMIN
3741 { 241, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMAX
3742 { 240, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMIN
3743 { 239, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRMASK
3744 { 238, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTR_ADD
3745 { 237, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_ROUNDING
3746 { 236, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_ROUNDING
3747 { 235, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPMODE
3748 { 234, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPMODE
3749 { 233, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPMODE
3750 { 232, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPENV
3751 { 231, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPENV
3752 { 230, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPENV
3753 { 229, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUMNUM
3754 { 228, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUMNUM
3755 { 227, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUM
3756 { 226, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUM
3757 { 225, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM_IEEE
3758 { 224, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM_IEEE
3759 { 223, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM
3760 { 222, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM
3761 { 221, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCANONICALIZE
3762 { 220, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IS_FPCLASS
3763 { 219, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOPYSIGN
3764 { 218, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FABS
3765 { 217, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI_SAT
3766 { 216, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI_SAT
3767 { 215, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UITOFP
3768 { 214, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SITOFP
3769 { 213, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI
3770 { 212, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI
3771 { 211, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNC
3772 { 210, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXT
3773 { 209, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEG
3774 { 208, 3, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFREXP
3775 { 207, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLDEXP
3776 { 206, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG10
3777 { 205, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG2
3778 { 204, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG
3779 { 203, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP10
3780 { 202, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP2
3781 { 201, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP
3782 { 200, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOWI
3783 { 199, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOW
3784 { 198, 3, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMODF
3785 { 197, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREM
3786 { 196, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FDIV
3787 { 195, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAD
3788 { 194, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMA
3789 { 193, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMUL
3790 { 192, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSUB
3791 { 191, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FADD
3792 { 190, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIXSAT
3793 { 189, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIXSAT
3794 { 188, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIX
3795 { 187, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIX
3796 { 186, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIXSAT
3797 { 185, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIXSAT
3798 { 184, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIX
3799 { 183, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIX
3800 { 182, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSHLSAT
3801 { 181, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USHLSAT
3802 { 180, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBSAT
3803 { 179, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBSAT
3804 { 178, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDSAT
3805 { 177, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDSAT
3806 { 176, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULH
3807 { 175, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULH
3808 { 174, 4, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULO
3809 { 173, 4, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULO
3810 { 172, 5, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBE
3811 { 171, 4, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBO
3812 { 170, 5, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDE
3813 { 169, 4, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDO
3814 { 168, 5, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBE
3815 { 167, 4, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBO
3816 { 166, 5, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDE
3817 { 165, 4, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDO
3818 { 164, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SELECT
3819 { 163, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UCMP
3820 { 162, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SCMP
3821 { 161, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCMP
3822 { 160, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ICMP
3823 { 159, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTL
3824 { 158, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTR
3825 { 157, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHR
3826 { 156, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHL
3827 { 155, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASHR
3828 { 154, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LSHR
3829 { 153, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHL
3830 { 152, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXT
3831 { 151, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT_INREG
3832 { 150, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT
3833 { 149, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VAARG
3834 { 148, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VASTART
3835 { 147, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCONSTANT
3836 { 146, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT
3837 { 145, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_USAT_U
3838 { 144, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_U
3839 { 143, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_S
3840 { 142, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC
3841 { 141, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ANYEXT
3842 { 140, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
3843 { 139, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT
3844 { 138, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_W_SIDE_EFFECTS
3845 { 137, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC
3846 { 136, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INVOKE_REGION_START
3847 { 135, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRINDIRECT
3848 { 134, 2, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRCOND
3849 { 133, 4, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 93, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PREFETCH
3850 { 132, 2, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 20, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FENCE
3851 { 131, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_SAT
3852 { 130, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_COND
3853 { 129, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UDEC_WRAP
3854 { 128, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UINC_WRAP
3855 { 127, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUMNUM
3856 { 126, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUMNUM
3857 { 125, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUM
3858 { 124, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUM
3859 { 123, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMIN
3860 { 122, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAX
3861 { 121, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FSUB
3862 { 120, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FADD
3863 { 119, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMIN
3864 { 118, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMAX
3865 { 117, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MIN
3866 { 116, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MAX
3867 { 115, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XOR
3868 { 114, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_OR
3869 { 113, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_NAND
3870 { 112, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_AND
3871 { 111, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_SUB
3872 { 110, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_ADD
3873 { 109, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XCHG
3874 { 108, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG
3875 { 107, 5, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 81, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
3876 { 106, 5, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 76, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_STORE
3877 { 105, 2, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STORE
3878 { 104, 5, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_ZEXTLOAD
3879 { 103, 5, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_SEXTLOAD
3880 { 102, 5, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_LOAD
3881 { 101, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXTLOAD
3882 { 100, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXTLOAD
3883 { 99, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LOAD
3884 { 98, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READSTEADYCOUNTER
3885 { 97, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READCYCLECOUNTER
3886 { 96, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUNDEVEN
3887 { 95, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LLRINT
3888 { 94, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LRINT
3889 { 93, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUND
3890 { 92, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_TRUNC
3891 { 91, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_FPTRUNC_ROUND
3892 { 90, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_FOLD_BARRIER
3893 { 89, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREEZE
3894 { 88, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITCAST
3895 { 87, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTTOPTR
3896 { 86, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRTOINT
3897 { 85, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONCAT_VECTORS
3898 { 84, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR_TRUNC
3899 { 83, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR
3900 { 82, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MERGE_VALUES
3901 { 81, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT
3902 { 80, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UNMERGE_VALUES
3903 { 79, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT
3904 { 78, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_POOL
3905 { 77, 5, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 52, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRAUTH_GLOBAL_VALUE
3906 { 76, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GLOBAL_VALUE
3907 { 75, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRAME_INDEX
3908 { 74, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PHI
3909 { 73, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IMPLICIT_DEF
3910 { 72, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGCEIL
3911 { 71, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGFLOOR
3912 { 70, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGCEIL
3913 { 69, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGFLOOR
3914 { 68, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDU
3915 { 67, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDS
3916 { 66, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_XOR
3917 { 65, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_OR
3918 { 64, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_AND
3919 { 63, 4, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVREM
3920 { 62, 4, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVREM
3921 { 61, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UREM
3922 { 60, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SREM
3923 { 59, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIV
3924 { 58, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIV
3925 { 57, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MUL
3926 { 56, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SUB
3927 { 55, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADD
3928 { 54, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ALIGN
3929 { 53, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ZEXT
3930 { 52, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_SEXT
3931 { 51, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_GLUE
3932 { 50, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_LOOP
3933 { 49, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ANCHOR
3934 { 48, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ENTRY
3935 { 47, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELOC_NONE
3936 { 46, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUMP_TABLE_DEBUG_INFO
3937 { 45, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMBARRIER
3938 { 44, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAKE_USE
3939 { 43, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ICALL_BRANCH_FUNNEL
3940 { 42, 3, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 36, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14815
3941 { 41, 2, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 34, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14814
3942 { 40, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_TAIL_CALL
3943 { 39, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_EXIT
3944 { 38, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_RET
3945 { 37, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_ENTER
3946 { 36, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_OP
3947 { 35, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAULTING_OP
3948 { 34, 2, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 32, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_ESCAPE
3949 { 33, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STATEPOINT
3950 { 32, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 29, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14813
3951 { 31, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PREALLOCATED_SETUP
3952 { 30, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 28, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_13542
3953 { 29, 6, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 22, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHPOINT
3954 { 28, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FENTRY_CALL
3955 { 27, 2, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STACKMAP
3956 { 26, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 18, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARITH_FENCE
3957 { 25, 4, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 14, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PSEUDO_PROBE
3958 { 24, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_END
3959 { 23, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_START
3960 { 22, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BUNDLE
3961 { 21, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 11, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_LANEMASK
3962 { 20, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY
3963 { 19, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REG_SEQUENCE
3964 { 18, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_LABEL
3965 { 17, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_PHI
3966 { 16, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_INSTR_REF
3967 { 15, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE_LIST
3968 { 14, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE
3969 { 13, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_TO_REGCLASS
3970 { 12, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBREG_TO_REG
3971 { 11, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INIT_UNDEF
3972 { 10, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // IMPLICIT_DEF
3973 { 9, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 5, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INSERT_SUBREG
3974 { 8, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_SUBREG
3975 { 7, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KILL
3976 { 6, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANNOTATION_LABEL
3977 { 5, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GC_LABEL
3978 { 4, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EH_LABEL
3979 { 3, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CFI_INSTRUCTION
3980 { 2, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM_BR
3981 { 1, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM
3982 { 0, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PHI
3983 }, {
3984 /* 0 */
3985 /* 0 */ WebAssembly::SP32, WebAssembly::SP64, WebAssembly::ARGUMENTS,
3986 /* 3 */ WebAssembly::ARGUMENTS,
3987 /* 4 */ WebAssembly::SP32, WebAssembly::SP64, WebAssembly::SP32, WebAssembly::SP64,
3988 /* 8 */ WebAssembly::VALUE_STACK, WebAssembly::VALUE_STACK,
3989 }, {
3990 0
3991 }, {
3992 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
3993 /* 1 */
3994 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3995 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3996 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3997 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
3998 /* 11 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
3999 /* 14 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4000 /* 18 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
4001 /* 20 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4002 /* 22 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4003 /* 28 */ { WebAssembly::wasm_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 },
4004 /* 29 */ { WebAssembly::wasm_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4005 /* 32 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4006 /* 34 */ { WebAssembly::wasm_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4007 /* 36 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { WebAssembly::wasm_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4008 /* 39 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
4009 /* 42 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
4010 /* 45 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
4011 /* 49 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
4012 /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4013 /* 52 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4014 /* 57 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
4015 /* 60 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
4016 /* 62 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
4017 /* 66 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
4018 /* 68 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4019 /* 71 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4020 /* 76 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4021 /* 81 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
4022 /* 86 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
4023 /* 90 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
4024 /* 93 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4025 /* 97 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4026 /* 100 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
4027 /* 103 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
4028 /* 107 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
4029 /* 111 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
4030 /* 114 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
4031 /* 119 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
4032 /* 123 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
4033 /* 126 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
4034 /* 130 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
4035 /* 133 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4036 /* 137 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
4037 /* 141 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
4038 /* 143 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
4039 /* 147 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
4040 /* 151 */ { -1, 0, WebAssembly::OPERAND_FUNCTION32, 0 },
4041 /* 152 */ { -1, 0, WebAssembly::OPERAND_BASIC_BLOCK, 0 }, { -1, 0, WebAssembly::OPERAND_BASIC_BLOCK, 0 },
4042 /* 154 */ { -1, 0, WebAssembly::OPERAND_BASIC_BLOCK, 0 },
4043 /* 155 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4044 /* 157 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4045 /* 159 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4046 /* 161 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4047 /* 164 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4048 /* 167 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4049 /* 170 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4050 /* 173 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4051 /* 176 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4052 /* 178 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4053 /* 180 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4054 /* 182 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4055 /* 184 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4056 /* 186 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4057 /* 188 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4058 /* 190 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4059 /* 192 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4060 /* 194 */ { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 },
4061 /* 195 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4062 /* 200 */ { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 },
4063 /* 203 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4064 /* 208 */ { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 },
4065 /* 211 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4066 /* 216 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4067 /* 221 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4068 /* 227 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4069 /* 233 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4070 /* 239 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4071 /* 245 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4072 /* 252 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4073 /* 259 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4074 /* 266 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4075 /* 273 */ { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4076 /* 278 */ { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4077 /* 283 */ { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4078 /* 288 */ { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4079 /* 293 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4080 /* 297 */ { -1, 0, WebAssembly::OPERAND_SIGNATURE, 0 },
4081 /* 298 */ { -1, 0, WebAssembly::OPERAND_BASIC_BLOCK, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4082 /* 300 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4083 /* 301 */ { -1, 0, WebAssembly::OPERAND_BRLIST, 0 },
4084 /* 302 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4085 /* 303 */ { -1, 0, WebAssembly::OPERAND_TYPEINDEX, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 },
4086 /* 305 */ { -1, 0, WebAssembly::OPERAND_TAG, 0 },
4087 /* 306 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4088 /* 307 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4089 /* 309 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4090 /* 311 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 },
4091 /* 313 */ { -1, 0, WebAssembly::OPERAND_F32IMM, 0 },
4092 /* 314 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_F64IMM, 0 },
4093 /* 316 */ { -1, 0, WebAssembly::OPERAND_F64IMM, 0 },
4094 /* 317 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_I32IMM, 0 },
4095 /* 319 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 },
4096 /* 320 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_I64IMM, 0 },
4097 /* 322 */ { -1, 0, WebAssembly::OPERAND_I64IMM, 0 },
4098 /* 323 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 },
4099 /* 328 */ { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 },
4100 /* 332 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_F64IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F64IMM, 0 },
4101 /* 335 */ { -1, 0, WebAssembly::OPERAND_F64IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F64IMM, 0 },
4102 /* 337 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 },
4103 /* 346 */ { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 },
4104 /* 354 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 },
4105 /* 359 */ { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 },
4106 /* 363 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I64IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I64IMM, 0 },
4107 /* 366 */ { -1, 0, WebAssembly::OPERAND_VEC_I64IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I64IMM, 0 },
4108 /* 368 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 },
4109 /* 385 */ { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 },
4110 /* 401 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4111 /* 403 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4112 /* 405 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4113 /* 407 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4114 /* 408 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4115 /* 409 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4116 /* 410 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4117 /* 411 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4118 /* 412 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4119 /* 414 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4120 /* 417 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4121 /* 420 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4122 /* 423 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 },
4123 /* 426 */ { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 },
4124 /* 427 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 },
4125 /* 430 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 },
4126 /* 433 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 },
4127 /* 436 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4128 /* 438 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4129 /* 440 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4130 /* 442 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4131 /* 444 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4132 /* 446 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4133 /* 448 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4134 /* 450 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4135 /* 452 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4136 /* 454 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4137 /* 456 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 },
4138 /* 458 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 },
4139 /* 459 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 },
4140 /* 461 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 },
4141 /* 463 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 },
4142 /* 465 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 },
4143 /* 467 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 },
4144 /* 469 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 },
4145 /* 471 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 },
4146 /* 473 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4147 /* 475 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4148 /* 477 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4149 /* 479 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4150 /* 481 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4151 /* 483 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4152 /* 485 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4153 /* 487 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4154 /* 489 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4155 /* 495 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4156 /* 497 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4157 /* 501 */ { -1, 0, WebAssembly::OPERAND_SIGNATURE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4158 /* 503 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4159 /* 507 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 },
4160 /* 509 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4161 /* 513 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 },
4162 /* 515 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4163 /* 519 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4164 /* 523 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4165 /* 527 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4166 /* 531 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4167 /* 535 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4168 /* 539 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4169 /* 543 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4170 /* 547 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4171 /* 553 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 },
4172 /* 556 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4173 /* 562 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 },
4174 /* 565 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 },
4175 /* 567 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 },
4176 /* 568 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 },
4177 /* 570 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 },
4178 /* 572 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 },
4179 /* 574 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 },
4180 /* 576 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 },
4181 /* 578 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 },
4182 /* 580 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 },
4183 /* 582 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4184 /* 584 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4185 /* 586 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4186 /* 588 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4187 /* 590 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4188 /* 592 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4189 /* 594 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4190 /* 596 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4191 /* 598 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4192 /* 601 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4193 /* 604 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4194 /* 607 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4195 /* 610 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4196 /* 613 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4197 /* 616 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4198 /* 619 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4199 /* 622 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4200 /* 627 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_I32IMM, 0 },
4201 /* 629 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4202 /* 634 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4203 /* 641 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4204 /* 648 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4205 /* 655 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4206 /* 662 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4207 /* 666 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4208 /* 670 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4209 /* 675 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_FUNCTION32, 0 },
4210 /* 677 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4211 /* 679 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4212 /* 681 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4213 /* 683 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TYPEINDEX, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4214 /* 686 */ { -1, 0, WebAssembly::OPERAND_TYPEINDEX, 0 },
4215 /* 687 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4216 /* 691 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4217 /* 695 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4218 /* 699 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4219 /* 703 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4220 /* 707 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4221 /* 711 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4222 /* 715 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4223 /* 719 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4224 /* 723 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4225 /* 727 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4226 /* 731 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4227 /* 735 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4228 /* 738 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 },
4229 /* 757 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4230 /* 759 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4231 /* 761 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4232 /* 763 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4233 /* 765 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4234 /* 769 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4235 /* 773 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4236 /* 777 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4237 /* 781 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4238 /* 785 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4239 /* 789 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4240 /* 793 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4241 /* 797 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4242 /* 802 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4243 /* 807 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4244 /* 811 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4245 /* 815 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4246 /* 820 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 },
4247 /* 822 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4248 /* 826 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 },
4249 /* 827 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4250 /* 831 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4251 /* 835 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4252 /* 838 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4253 /* 841 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4254 /* 844 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4255 /* 848 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4256 /* 852 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4257 /* 856 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4258 /* 859 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4259 /* 862 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4260 /* 865 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 },
4261 /* 867 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4262 /* 870 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4263 /* 873 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4264 /* 876 */ { -1, 0, WebAssembly::OPERAND_SIGNATURE, 0 }, { -1, 0, WebAssembly::OPERAND_CATCH_LIST, 0 },
4265 /* 878 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4266 /* 881 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4267 }
4268};
4269
4270
4271#ifdef __GNUC__
4272#pragma GCC diagnostic push
4273#pragma GCC diagnostic ignored "-Woverlength-strings"
4274#endif
4275extern const char WebAssemblyInstrNameData[] = {
4276 /* 0 */ "G_FLOG10\000"
4277 /* 9 */ "G_FEXP10\000"
4278 /* 18 */ "LOAD_F16_F32_A32\000"
4279 /* 35 */ "STORE_F16_F32_A32\000"
4280 /* 53 */ "LOAD_F32_A32\000"
4281 /* 66 */ "STORE_F32_A32\000"
4282 /* 80 */ "ATOMIC_STORE16_I32_A32\000"
4283 /* 103 */ "ATOMIC_STORE8_I32_A32\000"
4284 /* 125 */ "ATOMIC_RMW16_U_SUB_I32_A32\000"
4285 /* 152 */ "ATOMIC_RMW8_U_SUB_I32_A32\000"
4286 /* 178 */ "ATOMIC_RMW_SUB_I32_A32\000"
4287 /* 201 */ "ATOMIC_LOAD_I32_A32\000"
4288 /* 221 */ "ATOMIC_RMW16_U_ADD_I32_A32\000"
4289 /* 248 */ "ATOMIC_RMW8_U_ADD_I32_A32\000"
4290 /* 274 */ "ATOMIC_RMW_ADD_I32_A32\000"
4291 /* 297 */ "ATOMIC_RMW16_U_AND_I32_A32\000"
4292 /* 324 */ "ATOMIC_RMW8_U_AND_I32_A32\000"
4293 /* 350 */ "ATOMIC_RMW_AND_I32_A32\000"
4294 /* 373 */ "ATOMIC_STORE_I32_A32\000"
4295 /* 394 */ "ATOMIC_RMW16_U_CMPXCHG_I32_A32\000"
4296 /* 425 */ "ATOMIC_RMW8_U_CMPXCHG_I32_A32\000"
4297 /* 455 */ "ATOMIC_RMW_CMPXCHG_I32_A32\000"
4298 /* 482 */ "ATOMIC_RMW16_U_XCHG_I32_A32\000"
4299 /* 510 */ "ATOMIC_RMW8_U_XCHG_I32_A32\000"
4300 /* 537 */ "ATOMIC_RMW_XCHG_I32_A32\000"
4301 /* 561 */ "ATOMIC_RMW16_U_XOR_I32_A32\000"
4302 /* 588 */ "ATOMIC_RMW8_U_XOR_I32_A32\000"
4303 /* 614 */ "ATOMIC_RMW_XOR_I32_A32\000"
4304 /* 637 */ "ATOMIC_RMW16_U_OR_I32_A32\000"
4305 /* 663 */ "ATOMIC_RMW8_U_OR_I32_A32\000"
4306 /* 688 */ "ATOMIC_RMW_OR_I32_A32\000"
4307 /* 710 */ "LOAD16_S_I32_A32\000"
4308 /* 727 */ "LOAD8_S_I32_A32\000"
4309 /* 743 */ "ATOMIC_LOAD16_U_I32_A32\000"
4310 /* 767 */ "ATOMIC_LOAD8_U_I32_A32\000"
4311 /* 790 */ "MEMORY_ATOMIC_WAIT32_A32\000"
4312 /* 815 */ "LOAD_LANE_32_A32\000"
4313 /* 832 */ "LOAD_ZERO_32_A32\000"
4314 /* 849 */ "STORE_LANE_I64x2_A32\000"
4315 /* 870 */ "LOAD_EXTEND_S_I64x2_A32\000"
4316 /* 894 */ "LOAD_EXTEND_U_I64x2_A32\000"
4317 /* 918 */ "LOAD_F64_A32\000"
4318 /* 931 */ "STORE_F64_A32\000"
4319 /* 945 */ "ATOMIC_STORE32_I64_A32\000"
4320 /* 968 */ "ATOMIC_STORE16_I64_A32\000"
4321 /* 991 */ "ATOMIC_STORE8_I64_A32\000"
4322 /* 1013 */ "ATOMIC_RMW32_U_SUB_I64_A32\000"
4323 /* 1040 */ "ATOMIC_RMW16_U_SUB_I64_A32\000"
4324 /* 1067 */ "ATOMIC_RMW8_U_SUB_I64_A32\000"
4325 /* 1093 */ "ATOMIC_RMW_SUB_I64_A32\000"
4326 /* 1116 */ "ATOMIC_LOAD_I64_A32\000"
4327 /* 1136 */ "ATOMIC_RMW32_U_ADD_I64_A32\000"
4328 /* 1163 */ "ATOMIC_RMW16_U_ADD_I64_A32\000"
4329 /* 1190 */ "ATOMIC_RMW8_U_ADD_I64_A32\000"
4330 /* 1216 */ "ATOMIC_RMW_ADD_I64_A32\000"
4331 /* 1239 */ "ATOMIC_RMW32_U_AND_I64_A32\000"
4332 /* 1266 */ "ATOMIC_RMW16_U_AND_I64_A32\000"
4333 /* 1293 */ "ATOMIC_RMW8_U_AND_I64_A32\000"
4334 /* 1319 */ "ATOMIC_RMW_AND_I64_A32\000"
4335 /* 1342 */ "ATOMIC_STORE_I64_A32\000"
4336 /* 1363 */ "ATOMIC_RMW32_U_CMPXCHG_I64_A32\000"
4337 /* 1394 */ "ATOMIC_RMW16_U_CMPXCHG_I64_A32\000"
4338 /* 1425 */ "ATOMIC_RMW8_U_CMPXCHG_I64_A32\000"
4339 /* 1455 */ "ATOMIC_RMW_CMPXCHG_I64_A32\000"
4340 /* 1482 */ "ATOMIC_RMW32_U_XCHG_I64_A32\000"
4341 /* 1510 */ "ATOMIC_RMW16_U_XCHG_I64_A32\000"
4342 /* 1538 */ "ATOMIC_RMW8_U_XCHG_I64_A32\000"
4343 /* 1565 */ "ATOMIC_RMW_XCHG_I64_A32\000"
4344 /* 1589 */ "ATOMIC_RMW32_U_XOR_I64_A32\000"
4345 /* 1616 */ "ATOMIC_RMW16_U_XOR_I64_A32\000"
4346 /* 1643 */ "ATOMIC_RMW8_U_XOR_I64_A32\000"
4347 /* 1669 */ "ATOMIC_RMW_XOR_I64_A32\000"
4348 /* 1692 */ "ATOMIC_RMW32_U_OR_I64_A32\000"
4349 /* 1718 */ "ATOMIC_RMW16_U_OR_I64_A32\000"
4350 /* 1744 */ "ATOMIC_RMW8_U_OR_I64_A32\000"
4351 /* 1769 */ "ATOMIC_RMW_OR_I64_A32\000"
4352 /* 1791 */ "LOAD32_S_I64_A32\000"
4353 /* 1808 */ "LOAD16_S_I64_A32\000"
4354 /* 1825 */ "LOAD8_S_I64_A32\000"
4355 /* 1841 */ "ATOMIC_LOAD32_U_I64_A32\000"
4356 /* 1865 */ "ATOMIC_LOAD16_U_I64_A32\000"
4357 /* 1889 */ "ATOMIC_LOAD8_U_I64_A32\000"
4358 /* 1912 */ "MEMORY_ATOMIC_WAIT64_A32\000"
4359 /* 1937 */ "LOAD_LANE_64_A32\000"
4360 /* 1954 */ "LOAD_ZERO_64_A32\000"
4361 /* 1971 */ "STORE_LANE_I32x4_A32\000"
4362 /* 1992 */ "LOAD_EXTEND_S_I32x4_A32\000"
4363 /* 2016 */ "LOAD_EXTEND_U_I32x4_A32\000"
4364 /* 2040 */ "LOAD_LANE_16_A32\000"
4365 /* 2057 */ "STORE_LANE_I8x16_A32\000"
4366 /* 2078 */ "LOAD_V128_A32\000"
4367 /* 2092 */ "STORE_V128_A32\000"
4368 /* 2107 */ "LOAD_LANE_8_A32\000"
4369 /* 2123 */ "STORE_LANE_I16x8_A32\000"
4370 /* 2144 */ "LOAD_EXTEND_S_I16x8_A32\000"
4371 /* 2168 */ "LOAD_EXTEND_U_I16x8_A32\000"
4372 /* 2192 */ "anonymous_13975MEMORY_SIZE_A32\000"
4373 /* 2223 */ "MEMORY_FILL_A32\000"
4374 /* 2239 */ "LOAD32_SPLAT_A32\000"
4375 /* 2256 */ "LOAD64_SPLAT_A32\000"
4376 /* 2273 */ "LOAD16_SPLAT_A32\000"
4377 /* 2290 */ "LOAD8_SPLAT_A32\000"
4378 /* 2306 */ "MEMSET_A32\000"
4379 /* 2317 */ "MEMORY_INIT_A32\000"
4380 /* 2333 */ "anonymous_13975MEMORY_GROW_A32\000"
4381 /* 2364 */ "MEMORY_ATOMIC_NOTIFY_A32\000"
4382 /* 2389 */ "MEMCPY_A32\000"
4383 /* 2400 */ "MEMORY_COPY_A32\000"
4384 /* 2416 */ "FP_TO_SINT_I32_F32\000"
4385 /* 2435 */ "FP_TO_UINT_I32_F32\000"
4386 /* 2454 */ "FP_TO_SINT_I64_F32\000"
4387 /* 2473 */ "FP_TO_UINT_I64_F32\000"
4388 /* 2492 */ "SUB_F32\000"
4389 /* 2500 */ "TRUNC_F32\000"
4390 /* 2510 */ "ADD_F32\000"
4391 /* 2518 */ "LOCAL_TEE_F32\000"
4392 /* 2532 */ "GE_F32\000"
4393 /* 2539 */ "LE_F32\000"
4394 /* 2546 */ "NE_F32\000"
4395 /* 2553 */ "F64_PROMOTE_F32\000"
4396 /* 2569 */ "NEG_F32\000"
4397 /* 2577 */ "CEIL_F32\000"
4398 /* 2586 */ "MUL_F32\000"
4399 /* 2594 */ "COPYSIGN_F32\000"
4400 /* 2607 */ "MIN_F32\000"
4401 /* 2615 */ "DROP_F32\000"
4402 /* 2624 */ "EQ_F32\000"
4403 /* 2631 */ "FLOOR_F32\000"
4404 /* 2641 */ "ABS_F32\000"
4405 /* 2649 */ "I32_TRUNC_S_F32\000"
4406 /* 2665 */ "I64_TRUNC_S_F32\000"
4407 /* 2681 */ "I32_TRUNC_S_SAT_F32\000"
4408 /* 2701 */ "I64_TRUNC_S_SAT_F32\000"
4409 /* 2721 */ "I32_TRUNC_U_SAT_F32\000"
4410 /* 2741 */ "I64_TRUNC_U_SAT_F32\000"
4411 /* 2761 */ "SELECT_F32\000"
4412 /* 2772 */ "GLOBAL_GET_F32\000"
4413 /* 2787 */ "LOCAL_GET_F32\000"
4414 /* 2801 */ "I32_REINTERPRET_F32\000"
4415 /* 2821 */ "GLOBAL_SET_F32\000"
4416 /* 2836 */ "LOCAL_SET_F32\000"
4417 /* 2850 */ "GT_F32\000"
4418 /* 2857 */ "LT_F32\000"
4419 /* 2864 */ "SQRT_F32\000"
4420 /* 2873 */ "NEAREST_F32\000"
4421 /* 2885 */ "CONST_F32\000"
4422 /* 2895 */ "I32_TRUNC_U_F32\000"
4423 /* 2911 */ "I64_TRUNC_U_F32\000"
4424 /* 2927 */ "DIV_F32\000"
4425 /* 2935 */ "MAX_F32\000"
4426 /* 2943 */ "COPY_F32\000"
4427 /* 2952 */ "SUB_I32\000"
4428 /* 2960 */ "ADD_I32\000"
4429 /* 2968 */ "AND_I32\000"
4430 /* 2976 */ "LOCAL_TEE_I32\000"
4431 /* 2990 */ "BR_TABLE_I32\000"
4432 /* 3003 */ "NE_I32\000"
4433 /* 3010 */ "SHL_I32\000"
4434 /* 3018 */ "ROTL_I32\000"
4435 /* 3027 */ "MUL_I32\000"
4436 /* 3035 */ "DROP_I32\000"
4437 /* 3044 */ "EQ_I32\000"
4438 /* 3051 */ "XOR_I32\000"
4439 /* 3059 */ "ROTR_I32\000"
4440 /* 3068 */ "I32_EXTEND16_S_I32\000"
4441 /* 3087 */ "I32_EXTEND8_S_I32\000"
4442 /* 3105 */ "I64_EXTEND_S_I32\000"
4443 /* 3122 */ "GE_S_I32\000"
4444 /* 3131 */ "LE_S_I32\000"
4445 /* 3140 */ "REM_S_I32\000"
4446 /* 3150 */ "SHR_S_I32\000"
4447 /* 3160 */ "GT_S_I32\000"
4448 /* 3169 */ "LT_S_I32\000"
4449 /* 3178 */ "F32_CONVERT_S_I32\000"
4450 /* 3196 */ "F64_CONVERT_S_I32\000"
4451 /* 3214 */ "DIV_S_I32\000"
4452 /* 3224 */ "SELECT_I32\000"
4453 /* 3235 */ "GLOBAL_GET_I32\000"
4454 /* 3250 */ "LOCAL_GET_I32\000"
4455 /* 3264 */ "F32_REINTERPRET_I32\000"
4456 /* 3284 */ "GLOBAL_SET_I32\000"
4457 /* 3299 */ "LOCAL_SET_I32\000"
4458 /* 3313 */ "POPCNT_I32\000"
4459 /* 3324 */ "CONST_I32\000"
4460 /* 3334 */ "I64_EXTEND_U_I32\000"
4461 /* 3351 */ "GE_U_I32\000"
4462 /* 3360 */ "LE_U_I32\000"
4463 /* 3369 */ "REM_U_I32\000"
4464 /* 3379 */ "SHR_U_I32\000"
4465 /* 3389 */ "GT_U_I32\000"
4466 /* 3398 */ "LT_U_I32\000"
4467 /* 3407 */ "F32_CONVERT_U_I32\000"
4468 /* 3425 */ "F64_CONVERT_U_I32\000"
4469 /* 3443 */ "DIV_U_I32\000"
4470 /* 3453 */ "COPY_I32\000"
4471 /* 3462 */ "CLZ_I32\000"
4472 /* 3470 */ "EQZ_I32\000"
4473 /* 3478 */ "CTZ_I32\000"
4474 /* 3486 */ "ARGUMENT_v4f32\000"
4475 /* 3501 */ "ARGUMENT_f32\000"
4476 /* 3514 */ "ARGUMENT_v4i32\000"
4477 /* 3529 */ "ARGUMENT_i32\000"
4478 /* 3542 */ "G_FLOG2\000"
4479 /* 3550 */ "G_FATAN2\000"
4480 /* 3559 */ "G_FEXP2\000"
4481 /* 3567 */ "CONST_V128_F64x2\000"
4482 /* 3584 */ "SUB_F64x2\000"
4483 /* 3594 */ "TRUNC_F64x2\000"
4484 /* 3606 */ "NMADD_F64x2\000"
4485 /* 3618 */ "GE_F64x2\000"
4486 /* 3627 */ "LE_F64x2\000"
4487 /* 3636 */ "REPLACE_LANE_F64x2\000"
4488 /* 3655 */ "EXTRACT_LANE_F64x2\000"
4489 /* 3674 */ "NEG_F64x2\000"
4490 /* 3684 */ "CEIL_F64x2\000"
4491 /* 3695 */ "MUL_F64x2\000"
4492 /* 3705 */ "SIMD_RELAXED_FMIN_F64x2\000"
4493 /* 3729 */ "PMIN_F64x2\000"
4494 /* 3740 */ "EQ_F64x2\000"
4495 /* 3749 */ "FLOOR_F64x2\000"
4496 /* 3761 */ "ABS_F64x2\000"
4497 /* 3771 */ "SPLAT_F64x2\000"
4498 /* 3783 */ "GT_F64x2\000"
4499 /* 3792 */ "LT_F64x2\000"
4500 /* 3801 */ "SQRT_F64x2\000"
4501 /* 3812 */ "NEAREST_F64x2\000"
4502 /* 3826 */ "DIV_F64x2\000"
4503 /* 3836 */ "SIMD_RELAXED_FMAX_F64x2\000"
4504 /* 3860 */ "PMAX_F64x2\000"
4505 /* 3871 */ "convert_low_s_F64x2\000"
4506 /* 3891 */ "convert_low_u_F64x2\000"
4507 /* 3911 */ "promote_low_F64x2\000"
4508 /* 3929 */ "CONST_V128_I64x2\000"
4509 /* 3946 */ "SUB_I64x2\000"
4510 /* 3956 */ "ADD_I64x2\000"
4511 /* 3966 */ "REPLACE_LANE_I64x2\000"
4512 /* 3985 */ "EXTRACT_LANE_I64x2\000"
4513 /* 4004 */ "ALLTRUE_I64x2\000"
4514 /* 4018 */ "NEG_I64x2\000"
4515 /* 4028 */ "BITMASK_I64x2\000"
4516 /* 4042 */ "SHL_I64x2\000"
4517 /* 4052 */ "MUL_I64x2\000"
4518 /* 4062 */ "EQ_I64x2\000"
4519 /* 4071 */ "ABS_I64x2\000"
4520 /* 4081 */ "GE_S_I64x2\000"
4521 /* 4092 */ "LE_S_I64x2\000"
4522 /* 4103 */ "EXTMUL_HIGH_S_I64x2\000"
4523 /* 4123 */ "SHR_S_I64x2\000"
4524 /* 4135 */ "GT_S_I64x2\000"
4525 /* 4146 */ "LT_S_I64x2\000"
4526 /* 4157 */ "EXTMUL_LOW_S_I64x2\000"
4527 /* 4176 */ "SPLAT_I64x2\000"
4528 /* 4188 */ "LANESELECT_I64x2\000"
4529 /* 4205 */ "EXTMUL_HIGH_U_I64x2\000"
4530 /* 4225 */ "SHR_U_I64x2\000"
4531 /* 4237 */ "EXTMUL_LOW_U_I64x2\000"
4532 /* 4256 */ "extend_high_s_I64x2\000"
4533 /* 4276 */ "extend_low_s_I64x2\000"
4534 /* 4295 */ "extend_high_u_I64x2\000"
4535 /* 4315 */ "extend_low_u_I64x2\000"
4536 /* 4334 */ "LOAD_F16_F32_A64\000"
4537 /* 4351 */ "STORE_F16_F32_A64\000"
4538 /* 4369 */ "LOAD_F32_A64\000"
4539 /* 4382 */ "STORE_F32_A64\000"
4540 /* 4396 */ "ATOMIC_STORE16_I32_A64\000"
4541 /* 4419 */ "ATOMIC_STORE8_I32_A64\000"
4542 /* 4441 */ "ATOMIC_RMW16_U_SUB_I32_A64\000"
4543 /* 4468 */ "ATOMIC_RMW8_U_SUB_I32_A64\000"
4544 /* 4494 */ "ATOMIC_RMW_SUB_I32_A64\000"
4545 /* 4517 */ "ATOMIC_LOAD_I32_A64\000"
4546 /* 4537 */ "ATOMIC_RMW16_U_ADD_I32_A64\000"
4547 /* 4564 */ "ATOMIC_RMW8_U_ADD_I32_A64\000"
4548 /* 4590 */ "ATOMIC_RMW_ADD_I32_A64\000"
4549 /* 4613 */ "ATOMIC_RMW16_U_AND_I32_A64\000"
4550 /* 4640 */ "ATOMIC_RMW8_U_AND_I32_A64\000"
4551 /* 4666 */ "ATOMIC_RMW_AND_I32_A64\000"
4552 /* 4689 */ "ATOMIC_STORE_I32_A64\000"
4553 /* 4710 */ "ATOMIC_RMW16_U_CMPXCHG_I32_A64\000"
4554 /* 4741 */ "ATOMIC_RMW8_U_CMPXCHG_I32_A64\000"
4555 /* 4771 */ "ATOMIC_RMW_CMPXCHG_I32_A64\000"
4556 /* 4798 */ "ATOMIC_RMW16_U_XCHG_I32_A64\000"
4557 /* 4826 */ "ATOMIC_RMW8_U_XCHG_I32_A64\000"
4558 /* 4853 */ "ATOMIC_RMW_XCHG_I32_A64\000"
4559 /* 4877 */ "ATOMIC_RMW16_U_XOR_I32_A64\000"
4560 /* 4904 */ "ATOMIC_RMW8_U_XOR_I32_A64\000"
4561 /* 4930 */ "ATOMIC_RMW_XOR_I32_A64\000"
4562 /* 4953 */ "ATOMIC_RMW16_U_OR_I32_A64\000"
4563 /* 4979 */ "ATOMIC_RMW8_U_OR_I32_A64\000"
4564 /* 5004 */ "ATOMIC_RMW_OR_I32_A64\000"
4565 /* 5026 */ "LOAD16_S_I32_A64\000"
4566 /* 5043 */ "LOAD8_S_I32_A64\000"
4567 /* 5059 */ "ATOMIC_LOAD16_U_I32_A64\000"
4568 /* 5083 */ "ATOMIC_LOAD8_U_I32_A64\000"
4569 /* 5106 */ "MEMORY_ATOMIC_WAIT32_A64\000"
4570 /* 5131 */ "LOAD_LANE_32_A64\000"
4571 /* 5148 */ "LOAD_ZERO_32_A64\000"
4572 /* 5165 */ "STORE_LANE_I64x2_A64\000"
4573 /* 5186 */ "LOAD_EXTEND_S_I64x2_A64\000"
4574 /* 5210 */ "LOAD_EXTEND_U_I64x2_A64\000"
4575 /* 5234 */ "LOAD_F64_A64\000"
4576 /* 5247 */ "STORE_F64_A64\000"
4577 /* 5261 */ "ATOMIC_STORE32_I64_A64\000"
4578 /* 5284 */ "ATOMIC_STORE16_I64_A64\000"
4579 /* 5307 */ "ATOMIC_STORE8_I64_A64\000"
4580 /* 5329 */ "ATOMIC_RMW32_U_SUB_I64_A64\000"
4581 /* 5356 */ "ATOMIC_RMW16_U_SUB_I64_A64\000"
4582 /* 5383 */ "ATOMIC_RMW8_U_SUB_I64_A64\000"
4583 /* 5409 */ "ATOMIC_RMW_SUB_I64_A64\000"
4584 /* 5432 */ "ATOMIC_LOAD_I64_A64\000"
4585 /* 5452 */ "ATOMIC_RMW32_U_ADD_I64_A64\000"
4586 /* 5479 */ "ATOMIC_RMW16_U_ADD_I64_A64\000"
4587 /* 5506 */ "ATOMIC_RMW8_U_ADD_I64_A64\000"
4588 /* 5532 */ "ATOMIC_RMW_ADD_I64_A64\000"
4589 /* 5555 */ "ATOMIC_RMW32_U_AND_I64_A64\000"
4590 /* 5582 */ "ATOMIC_RMW16_U_AND_I64_A64\000"
4591 /* 5609 */ "ATOMIC_RMW8_U_AND_I64_A64\000"
4592 /* 5635 */ "ATOMIC_RMW_AND_I64_A64\000"
4593 /* 5658 */ "ATOMIC_STORE_I64_A64\000"
4594 /* 5679 */ "ATOMIC_RMW32_U_CMPXCHG_I64_A64\000"
4595 /* 5710 */ "ATOMIC_RMW16_U_CMPXCHG_I64_A64\000"
4596 /* 5741 */ "ATOMIC_RMW8_U_CMPXCHG_I64_A64\000"
4597 /* 5771 */ "ATOMIC_RMW_CMPXCHG_I64_A64\000"
4598 /* 5798 */ "ATOMIC_RMW32_U_XCHG_I64_A64\000"
4599 /* 5826 */ "ATOMIC_RMW16_U_XCHG_I64_A64\000"
4600 /* 5854 */ "ATOMIC_RMW8_U_XCHG_I64_A64\000"
4601 /* 5881 */ "ATOMIC_RMW_XCHG_I64_A64\000"
4602 /* 5905 */ "ATOMIC_RMW32_U_XOR_I64_A64\000"
4603 /* 5932 */ "ATOMIC_RMW16_U_XOR_I64_A64\000"
4604 /* 5959 */ "ATOMIC_RMW8_U_XOR_I64_A64\000"
4605 /* 5985 */ "ATOMIC_RMW_XOR_I64_A64\000"
4606 /* 6008 */ "ATOMIC_RMW32_U_OR_I64_A64\000"
4607 /* 6034 */ "ATOMIC_RMW16_U_OR_I64_A64\000"
4608 /* 6060 */ "ATOMIC_RMW8_U_OR_I64_A64\000"
4609 /* 6085 */ "ATOMIC_RMW_OR_I64_A64\000"
4610 /* 6107 */ "LOAD32_S_I64_A64\000"
4611 /* 6124 */ "LOAD16_S_I64_A64\000"
4612 /* 6141 */ "LOAD8_S_I64_A64\000"
4613 /* 6157 */ "ATOMIC_LOAD32_U_I64_A64\000"
4614 /* 6181 */ "ATOMIC_LOAD16_U_I64_A64\000"
4615 /* 6205 */ "ATOMIC_LOAD8_U_I64_A64\000"
4616 /* 6228 */ "MEMORY_ATOMIC_WAIT64_A64\000"
4617 /* 6253 */ "LOAD_LANE_64_A64\000"
4618 /* 6270 */ "LOAD_ZERO_64_A64\000"
4619 /* 6287 */ "STORE_LANE_I32x4_A64\000"
4620 /* 6308 */ "LOAD_EXTEND_S_I32x4_A64\000"
4621 /* 6332 */ "LOAD_EXTEND_U_I32x4_A64\000"
4622 /* 6356 */ "LOAD_LANE_16_A64\000"
4623 /* 6373 */ "STORE_LANE_I8x16_A64\000"
4624 /* 6394 */ "LOAD_V128_A64\000"
4625 /* 6408 */ "STORE_V128_A64\000"
4626 /* 6423 */ "LOAD_LANE_8_A64\000"
4627 /* 6439 */ "STORE_LANE_I16x8_A64\000"
4628 /* 6460 */ "LOAD_EXTEND_S_I16x8_A64\000"
4629 /* 6484 */ "LOAD_EXTEND_U_I16x8_A64\000"
4630 /* 6508 */ "anonymous_13976MEMORY_SIZE_A64\000"
4631 /* 6539 */ "MEMORY_FILL_A64\000"
4632 /* 6555 */ "LOAD32_SPLAT_A64\000"
4633 /* 6572 */ "LOAD64_SPLAT_A64\000"
4634 /* 6589 */ "LOAD16_SPLAT_A64\000"
4635 /* 6606 */ "LOAD8_SPLAT_A64\000"
4636 /* 6622 */ "MEMSET_A64\000"
4637 /* 6633 */ "MEMORY_INIT_A64\000"
4638 /* 6649 */ "anonymous_13976MEMORY_GROW_A64\000"
4639 /* 6680 */ "MEMORY_ATOMIC_NOTIFY_A64\000"
4640 /* 6705 */ "MEMCPY_A64\000"
4641 /* 6716 */ "MEMORY_COPY_A64\000"
4642 /* 6732 */ "FP_TO_SINT_I32_F64\000"
4643 /* 6751 */ "FP_TO_UINT_I32_F64\000"
4644 /* 6770 */ "FP_TO_SINT_I64_F64\000"
4645 /* 6789 */ "FP_TO_UINT_I64_F64\000"
4646 /* 6808 */ "SUB_F64\000"
4647 /* 6816 */ "TRUNC_F64\000"
4648 /* 6826 */ "ADD_F64\000"
4649 /* 6834 */ "LOCAL_TEE_F64\000"
4650 /* 6848 */ "GE_F64\000"
4651 /* 6855 */ "LE_F64\000"
4652 /* 6862 */ "NE_F64\000"
4653 /* 6869 */ "F32_DEMOTE_F64\000"
4654 /* 6884 */ "NEG_F64\000"
4655 /* 6892 */ "CEIL_F64\000"
4656 /* 6901 */ "MUL_F64\000"
4657 /* 6909 */ "COPYSIGN_F64\000"
4658 /* 6922 */ "MIN_F64\000"
4659 /* 6930 */ "DROP_F64\000"
4660 /* 6939 */ "EQ_F64\000"
4661 /* 6946 */ "FLOOR_F64\000"
4662 /* 6956 */ "ABS_F64\000"
4663 /* 6964 */ "I32_TRUNC_S_F64\000"
4664 /* 6980 */ "I64_TRUNC_S_F64\000"
4665 /* 6996 */ "I32_TRUNC_S_SAT_F64\000"
4666 /* 7016 */ "I64_TRUNC_S_SAT_F64\000"
4667 /* 7036 */ "I32_TRUNC_U_SAT_F64\000"
4668 /* 7056 */ "I64_TRUNC_U_SAT_F64\000"
4669 /* 7076 */ "SELECT_F64\000"
4670 /* 7087 */ "GLOBAL_GET_F64\000"
4671 /* 7102 */ "LOCAL_GET_F64\000"
4672 /* 7116 */ "I64_REINTERPRET_F64\000"
4673 /* 7136 */ "GLOBAL_SET_F64\000"
4674 /* 7151 */ "LOCAL_SET_F64\000"
4675 /* 7165 */ "GT_F64\000"
4676 /* 7172 */ "LT_F64\000"
4677 /* 7179 */ "SQRT_F64\000"
4678 /* 7188 */ "NEAREST_F64\000"
4679 /* 7200 */ "CONST_F64\000"
4680 /* 7210 */ "I32_TRUNC_U_F64\000"
4681 /* 7226 */ "I64_TRUNC_U_F64\000"
4682 /* 7242 */ "DIV_F64\000"
4683 /* 7250 */ "MAX_F64\000"
4684 /* 7258 */ "COPY_F64\000"
4685 /* 7267 */ "SUB_I64\000"
4686 /* 7275 */ "ADD_I64\000"
4687 /* 7283 */ "AND_I64\000"
4688 /* 7291 */ "LOCAL_TEE_I64\000"
4689 /* 7305 */ "BR_TABLE_I64\000"
4690 /* 7318 */ "NE_I64\000"
4691 /* 7325 */ "SHL_I64\000"
4692 /* 7333 */ "ROTL_I64\000"
4693 /* 7342 */ "MUL_I64\000"
4694 /* 7350 */ "I32_WRAP_I64\000"
4695 /* 7363 */ "DROP_I64\000"
4696 /* 7372 */ "EQ_I64\000"
4697 /* 7379 */ "XOR_I64\000"
4698 /* 7387 */ "ROTR_I64\000"
4699 /* 7396 */ "I64_EXTEND32_S_I64\000"
4700 /* 7415 */ "I64_EXTEND16_S_I64\000"
4701 /* 7434 */ "I64_EXTEND8_S_I64\000"
4702 /* 7452 */ "GE_S_I64\000"
4703 /* 7461 */ "LE_S_I64\000"
4704 /* 7470 */ "REM_S_I64\000"
4705 /* 7480 */ "SHR_S_I64\000"
4706 /* 7490 */ "GT_S_I64\000"
4707 /* 7499 */ "LT_S_I64\000"
4708 /* 7508 */ "F32_CONVERT_S_I64\000"
4709 /* 7526 */ "F64_CONVERT_S_I64\000"
4710 /* 7544 */ "DIV_S_I64\000"
4711 /* 7554 */ "SELECT_I64\000"
4712 /* 7565 */ "GLOBAL_GET_I64\000"
4713 /* 7580 */ "LOCAL_GET_I64\000"
4714 /* 7594 */ "F64_REINTERPRET_I64\000"
4715 /* 7614 */ "GLOBAL_SET_I64\000"
4716 /* 7629 */ "LOCAL_SET_I64\000"
4717 /* 7643 */ "POPCNT_I64\000"
4718 /* 7654 */ "CONST_I64\000"
4719 /* 7664 */ "GE_U_I64\000"
4720 /* 7673 */ "LE_U_I64\000"
4721 /* 7682 */ "REM_U_I64\000"
4722 /* 7692 */ "SHR_U_I64\000"
4723 /* 7702 */ "GT_U_I64\000"
4724 /* 7711 */ "LT_U_I64\000"
4725 /* 7720 */ "F32_CONVERT_U_I64\000"
4726 /* 7738 */ "F64_CONVERT_U_I64\000"
4727 /* 7756 */ "DIV_U_I64\000"
4728 /* 7766 */ "COPY_I64\000"
4729 /* 7775 */ "CLZ_I64\000"
4730 /* 7783 */ "EQZ_I64\000"
4731 /* 7791 */ "CTZ_I64\000"
4732 /* 7799 */ "ARGUMENT_v2f64\000"
4733 /* 7814 */ "ARGUMENT_f64\000"
4734 /* 7827 */ "ARGUMENT_v2i64\000"
4735 /* 7842 */ "ARGUMENT_i64\000"
4736 /* 7855 */ "CONST_V128_F32x4\000"
4737 /* 7872 */ "SUB_F32x4\000"
4738 /* 7882 */ "TRUNC_F32x4\000"
4739 /* 7894 */ "NMADD_F32x4\000"
4740 /* 7906 */ "GE_F32x4\000"
4741 /* 7915 */ "LE_F32x4\000"
4742 /* 7924 */ "REPLACE_LANE_F32x4\000"
4743 /* 7943 */ "EXTRACT_LANE_F32x4\000"
4744 /* 7962 */ "NEG_F32x4\000"
4745 /* 7972 */ "CEIL_F32x4\000"
4746 /* 7983 */ "MUL_F32x4\000"
4747 /* 7993 */ "SIMD_RELAXED_FMIN_F32x4\000"
4748 /* 8017 */ "PMIN_F32x4\000"
4749 /* 8028 */ "EQ_F32x4\000"
4750 /* 8037 */ "FLOOR_F32x4\000"
4751 /* 8049 */ "ABS_F32x4\000"
4752 /* 8059 */ "SPLAT_F32x4\000"
4753 /* 8071 */ "GT_F32x4\000"
4754 /* 8080 */ "LT_F32x4\000"
4755 /* 8089 */ "SQRT_F32x4\000"
4756 /* 8100 */ "NEAREST_F32x4\000"
4757 /* 8114 */ "DIV_F32x4\000"
4758 /* 8124 */ "SIMD_RELAXED_FMAX_F32x4\000"
4759 /* 8148 */ "PMAX_F32x4\000"
4760 /* 8159 */ "demote_zero_F32x4\000"
4761 /* 8177 */ "sint_to_fp_F32x4\000"
4762 /* 8194 */ "uint_to_fp_F32x4\000"
4763 /* 8211 */ "CONST_V128_I32x4\000"
4764 /* 8228 */ "SUB_I32x4\000"
4765 /* 8238 */ "ADD_I32x4\000"
4766 /* 8248 */ "REPLACE_LANE_I32x4\000"
4767 /* 8267 */ "EXTRACT_LANE_I32x4\000"
4768 /* 8286 */ "ALLTRUE_I32x4\000"
4769 /* 8300 */ "NEG_I32x4\000"
4770 /* 8310 */ "BITMASK_I32x4\000"
4771 /* 8324 */ "SHL_I32x4\000"
4772 /* 8334 */ "MUL_I32x4\000"
4773 /* 8344 */ "EQ_I32x4\000"
4774 /* 8353 */ "ABS_I32x4\000"
4775 /* 8363 */ "GE_S_I32x4\000"
4776 /* 8374 */ "LE_S_I32x4\000"
4777 /* 8385 */ "EXTMUL_HIGH_S_I32x4\000"
4778 /* 8405 */ "MIN_S_I32x4\000"
4779 /* 8417 */ "SHR_S_I32x4\000"
4780 /* 8429 */ "GT_S_I32x4\000"
4781 /* 8440 */ "LT_S_I32x4\000"
4782 /* 8451 */ "EXTMUL_LOW_S_I32x4\000"
4783 /* 8470 */ "MAX_S_I32x4\000"
4784 /* 8482 */ "SPLAT_I32x4\000"
4785 /* 8494 */ "LANESELECT_I32x4\000"
4786 /* 8511 */ "GE_U_I32x4\000"
4787 /* 8522 */ "LE_U_I32x4\000"
4788 /* 8533 */ "EXTMUL_HIGH_U_I32x4\000"
4789 /* 8553 */ "MIN_U_I32x4\000"
4790 /* 8565 */ "SHR_U_I32x4\000"
4791 /* 8577 */ "GT_U_I32x4\000"
4792 /* 8588 */ "LT_U_I32x4\000"
4793 /* 8599 */ "EXTMUL_LOW_U_I32x4\000"
4794 /* 8618 */ "MAX_U_I32x4\000"
4795 /* 8630 */ "int_wasm_relaxed_trunc_signed_I32x4\000"
4796 /* 8666 */ "int_wasm_relaxed_trunc_unsigned_I32x4\000"
4797 /* 8704 */ "int_wasm_relaxed_trunc_signed_zero_I32x4\000"
4798 /* 8745 */ "int_wasm_relaxed_trunc_unsigned_zero_I32x4\000"
4799 /* 8788 */ "extadd_pairwise_s_I32x4\000"
4800 /* 8812 */ "extend_high_s_I32x4\000"
4801 /* 8832 */ "trunc_sat_zero_s_I32x4\000"
4802 /* 8855 */ "extend_low_s_I32x4\000"
4803 /* 8874 */ "fp_to_sint_I32x4\000"
4804 /* 8891 */ "fp_to_uint_I32x4\000"
4805 /* 8908 */ "extadd_pairwise_u_I32x4\000"
4806 /* 8932 */ "extend_high_u_I32x4\000"
4807 /* 8952 */ "trunc_sat_zero_u_I32x4\000"
4808 /* 8975 */ "extend_low_u_I32x4\000"
4809 /* 8994 */ "ARGUMENT_v8f16\000"
4810 /* 9009 */ "ARGUMENT_v8i16\000"
4811 /* 9024 */ "CONST_V128_I8x16\000"
4812 /* 9041 */ "SUB_I8x16\000"
4813 /* 9051 */ "ADD_I8x16\000"
4814 /* 9061 */ "REPLACE_LANE_I8x16\000"
4815 /* 9080 */ "ALLTRUE_I8x16\000"
4816 /* 9094 */ "NEG_I8x16\000"
4817 /* 9104 */ "BITMASK_I8x16\000"
4818 /* 9118 */ "SHL_I8x16\000"
4819 /* 9128 */ "EQ_I8x16\000"
4820 /* 9137 */ "ABS_I8x16\000"
4821 /* 9147 */ "GE_S_I8x16\000"
4822 /* 9158 */ "LE_S_I8x16\000"
4823 /* 9169 */ "MIN_S_I8x16\000"
4824 /* 9181 */ "SHR_S_I8x16\000"
4825 /* 9193 */ "SUB_SAT_S_I8x16\000"
4826 /* 9209 */ "ADD_SAT_S_I8x16\000"
4827 /* 9225 */ "GT_S_I8x16\000"
4828 /* 9236 */ "LT_S_I8x16\000"
4829 /* 9247 */ "NARROW_S_I8x16\000"
4830 /* 9262 */ "MAX_S_I8x16\000"
4831 /* 9274 */ "SPLAT_I8x16\000"
4832 /* 9286 */ "LANESELECT_I8x16\000"
4833 /* 9303 */ "POPCNT_I8x16\000"
4834 /* 9316 */ "GE_U_I8x16\000"
4835 /* 9327 */ "LE_U_I8x16\000"
4836 /* 9338 */ "MIN_U_I8x16\000"
4837 /* 9350 */ "AVGR_U_I8x16\000"
4838 /* 9363 */ "SHR_U_I8x16\000"
4839 /* 9375 */ "SUB_SAT_U_I8x16\000"
4840 /* 9391 */ "ADD_SAT_U_I8x16\000"
4841 /* 9407 */ "GT_U_I8x16\000"
4842 /* 9418 */ "LT_U_I8x16\000"
4843 /* 9429 */ "NARROW_U_I8x16\000"
4844 /* 9444 */ "MAX_U_I8x16\000"
4845 /* 9456 */ "I64_SUB128\000"
4846 /* 9467 */ "I64_ADD128\000"
4847 /* 9478 */ "LOCAL_TEE_V128\000"
4848 /* 9493 */ "DROP_V128\000"
4849 /* 9503 */ "SELECT_V128\000"
4850 /* 9515 */ "GLOBAL_GET_V128\000"
4851 /* 9531 */ "LOCAL_GET_V128\000"
4852 /* 9546 */ "GLOBAL_SET_V128\000"
4853 /* 9562 */ "LOCAL_SET_V128\000"
4854 /* 9577 */ "COPY_V128\000"
4855 /* 9587 */ "ARGUMENT_v16i8\000"
4856 /* 9602 */ "SUB_F16x8\000"
4857 /* 9612 */ "TRUNC_F16x8\000"
4858 /* 9624 */ "NMADD_F16x8\000"
4859 /* 9636 */ "GE_F16x8\000"
4860 /* 9645 */ "LE_F16x8\000"
4861 /* 9654 */ "REPLACE_LANE_F16x8\000"
4862 /* 9673 */ "EXTRACT_LANE_F16x8\000"
4863 /* 9692 */ "NEG_F16x8\000"
4864 /* 9702 */ "CEIL_F16x8\000"
4865 /* 9713 */ "MUL_F16x8\000"
4866 /* 9723 */ "PMIN_F16x8\000"
4867 /* 9734 */ "EQ_F16x8\000"
4868 /* 9743 */ "FLOOR_F16x8\000"
4869 /* 9755 */ "ABS_F16x8\000"
4870 /* 9765 */ "SPLAT_F16x8\000"
4871 /* 9777 */ "GT_F16x8\000"
4872 /* 9786 */ "LT_F16x8\000"
4873 /* 9795 */ "SQRT_F16x8\000"
4874 /* 9806 */ "NEAREST_F16x8\000"
4875 /* 9820 */ "DIV_F16x8\000"
4876 /* 9830 */ "PMAX_F16x8\000"
4877 /* 9841 */ "sint_to_fp_F16x8\000"
4878 /* 9858 */ "uint_to_fp_F16x8\000"
4879 /* 9875 */ "CONST_V128_I16x8\000"
4880 /* 9892 */ "SUB_I16x8\000"
4881 /* 9902 */ "ADD_I16x8\000"
4882 /* 9912 */ "REPLACE_LANE_I16x8\000"
4883 /* 9931 */ "ALLTRUE_I16x8\000"
4884 /* 9945 */ "NEG_I16x8\000"
4885 /* 9955 */ "BITMASK_I16x8\000"
4886 /* 9969 */ "SHL_I16x8\000"
4887 /* 9979 */ "MUL_I16x8\000"
4888 /* 9989 */ "EQ_I16x8\000"
4889 /* 9998 */ "ABS_I16x8\000"
4890 /* 10008 */ "GE_S_I16x8\000"
4891 /* 10019 */ "LE_S_I16x8\000"
4892 /* 10030 */ "EXTMUL_HIGH_S_I16x8\000"
4893 /* 10050 */ "MIN_S_I16x8\000"
4894 /* 10062 */ "SHR_S_I16x8\000"
4895 /* 10074 */ "RELAXED_Q15MULR_S_I16x8\000"
4896 /* 10098 */ "SUB_SAT_S_I16x8\000"
4897 /* 10114 */ "ADD_SAT_S_I16x8\000"
4898 /* 10130 */ "Q15MULR_SAT_S_I16x8\000"
4899 /* 10150 */ "GT_S_I16x8\000"
4900 /* 10161 */ "LT_S_I16x8\000"
4901 /* 10172 */ "EXTMUL_LOW_S_I16x8\000"
4902 /* 10191 */ "NARROW_S_I16x8\000"
4903 /* 10206 */ "MAX_S_I16x8\000"
4904 /* 10218 */ "SPLAT_I16x8\000"
4905 /* 10230 */ "LANESELECT_I16x8\000"
4906 /* 10247 */ "GE_U_I16x8\000"
4907 /* 10258 */ "LE_U_I16x8\000"
4908 /* 10269 */ "EXTMUL_HIGH_U_I16x8\000"
4909 /* 10289 */ "MIN_U_I16x8\000"
4910 /* 10301 */ "AVGR_U_I16x8\000"
4911 /* 10314 */ "SHR_U_I16x8\000"
4912 /* 10326 */ "SUB_SAT_U_I16x8\000"
4913 /* 10342 */ "ADD_SAT_U_I16x8\000"
4914 /* 10358 */ "GT_U_I16x8\000"
4915 /* 10369 */ "LT_U_I16x8\000"
4916 /* 10380 */ "EXTMUL_LOW_U_I16x8\000"
4917 /* 10399 */ "NARROW_U_I16x8\000"
4918 /* 10414 */ "MAX_U_I16x8\000"
4919 /* 10426 */ "extadd_pairwise_s_I16x8\000"
4920 /* 10450 */ "extend_high_s_I16x8\000"
4921 /* 10470 */ "extend_low_s_I16x8\000"
4922 /* 10489 */ "fp_to_sint_I16x8\000"
4923 /* 10506 */ "fp_to_uint_I16x8\000"
4924 /* 10523 */ "extadd_pairwise_u_I16x8\000"
4925 /* 10547 */ "extend_high_u_I16x8\000"
4926 /* 10567 */ "extend_low_u_I16x8\000"
4927 /* 10586 */ "G_FMA\000"
4928 /* 10592 */ "G_STRICT_FMA\000"
4929 /* 10605 */ "G_FSUB\000"
4930 /* 10612 */ "G_STRICT_FSUB\000"
4931 /* 10626 */ "G_ATOMICRMW_FSUB\000"
4932 /* 10643 */ "G_SUB\000"
4933 /* 10649 */ "G_ATOMICRMW_SUB\000"
4934 /* 10665 */ "G_INTRINSIC\000"
4935 /* 10677 */ "REF_FUNC\000"
4936 /* 10686 */ "G_FPTRUNC\000"
4937 /* 10696 */ "G_INTRINSIC_TRUNC\000"
4938 /* 10714 */ "G_TRUNC\000"
4939 /* 10722 */ "G_BUILD_VECTOR_TRUNC\000"
4940 /* 10743 */ "G_DYN_STACKALLOC\000"
4941 /* 10760 */ "G_FMAD\000"
4942 /* 10767 */ "G_INDEXED_SEXTLOAD\000"
4943 /* 10786 */ "G_SEXTLOAD\000"
4944 /* 10797 */ "G_INDEXED_ZEXTLOAD\000"
4945 /* 10816 */ "G_ZEXTLOAD\000"
4946 /* 10827 */ "G_INDEXED_LOAD\000"
4947 /* 10842 */ "G_LOAD\000"
4948 /* 10849 */ "G_VECREDUCE_FADD\000"
4949 /* 10866 */ "G_FADD\000"
4950 /* 10873 */ "G_VECREDUCE_SEQ_FADD\000"
4951 /* 10894 */ "G_STRICT_FADD\000"
4952 /* 10908 */ "G_ATOMICRMW_FADD\000"
4953 /* 10925 */ "G_VECREDUCE_ADD\000"
4954 /* 10941 */ "G_ADD\000"
4955 /* 10947 */ "G_PTR_ADD\000"
4956 /* 10957 */ "RELAXED_DOT_ADD\000"
4957 /* 10973 */ "G_ATOMICRMW_ADD\000"
4958 /* 10989 */ "G_ATOMICRMW_NAND\000"
4959 /* 11006 */ "G_VECREDUCE_AND\000"
4960 /* 11022 */ "G_AND\000"
4961 /* 11028 */ "G_ATOMICRMW_AND\000"
4962 /* 11044 */ "LIFETIME_END\000"
4963 /* 11057 */ "G_BRCOND\000"
4964 /* 11066 */ "G_ATOMICRMW_USUB_COND\000"
4965 /* 11088 */ "G_LLROUND\000"
4966 /* 11098 */ "G_LROUND\000"
4967 /* 11107 */ "G_INTRINSIC_ROUND\000"
4968 /* 11125 */ "G_INTRINSIC_FPTRUNC_ROUND\000"
4969 /* 11151 */ "LOAD_STACK_GUARD\000"
4970 /* 11168 */ "PSEUDO_PROBE\000"
4971 /* 11181 */ "G_SSUBE\000"
4972 /* 11189 */ "G_USUBE\000"
4973 /* 11197 */ "ATOMIC_FENCE\000"
4974 /* 11210 */ "G_FENCE\000"
4975 /* 11218 */ "ARITH_FENCE\000"
4976 /* 11230 */ "COMPILER_FENCE\000"
4977 /* 11245 */ "REG_SEQUENCE\000"
4978 /* 11258 */ "G_SADDE\000"
4979 /* 11266 */ "G_UADDE\000"
4980 /* 11274 */ "G_GET_FPMODE\000"
4981 /* 11287 */ "G_RESET_FPMODE\000"
4982 /* 11302 */ "G_SET_FPMODE\000"
4983 /* 11315 */ "G_FMINNUM_IEEE\000"
4984 /* 11330 */ "G_FMAXNUM_IEEE\000"
4985 /* 11345 */ "G_VSCALE\000"
4986 /* 11354 */ "DEBUG_UNREACHABLE\000"
4987 /* 11372 */ "G_JUMP_TABLE\000"
4988 /* 11385 */ "END_TRY_TABLE\000"
4989 /* 11399 */ "BUNDLE\000"
4990 /* 11406 */ "SHUFFLE\000"
4991 /* 11414 */ "RELAXED_SWIZZLE\000"
4992 /* 11430 */ "G_MEMCPY_INLINE\000"
4993 /* 11446 */ "RELOC_NONE\000"
4994 /* 11457 */ "LOCAL_ESCAPE\000"
4995 /* 11470 */ "G_STACKRESTORE\000"
4996 /* 11485 */ "G_INDEXED_STORE\000"
4997 /* 11501 */ "G_STORE\000"
4998 /* 11509 */ "ELSE\000"
4999 /* 11514 */ "G_BITREVERSE\000"
5000 /* 11527 */ "FAKE_USE\000"
5001 /* 11536 */ "DELEGATE\000"
5002 /* 11545 */ "DBG_VALUE\000"
5003 /* 11555 */ "G_GLOBAL_VALUE\000"
5004 /* 11570 */ "G_PTRAUTH_GLOBAL_VALUE\000"
5005 /* 11593 */ "CONVERGENCECTRL_GLUE\000"
5006 /* 11614 */ "ANYTRUE\000"
5007 /* 11622 */ "G_STACKSAVE\000"
5008 /* 11634 */ "G_MEMMOVE\000"
5009 /* 11644 */ "G_FREEZE\000"
5010 /* 11653 */ "G_FCANONICALIZE\000"
5011 /* 11669 */ "TABLE_SIZE\000"
5012 /* 11680 */ "G_FMODF\000"
5013 /* 11688 */ "G_CTLZ_ZERO_UNDEF\000"
5014 /* 11706 */ "G_CTTZ_ZERO_UNDEF\000"
5015 /* 11724 */ "INIT_UNDEF\000"
5016 /* 11735 */ "G_IMPLICIT_DEF\000"
5017 /* 11750 */ "LOCAL_TEE_FUNCREF\000"
5018 /* 11768 */ "TABLE_FILL_FUNCREF\000"
5019 /* 11787 */ "REF_NULL_FUNCREF\000"
5020 /* 11804 */ "REF_IS_NULL_FUNCREF\000"
5021 /* 11824 */ "DROP_FUNCREF\000"
5022 /* 11837 */ "SELECT_FUNCREF\000"
5023 /* 11852 */ "TABLE_GET_FUNCREF\000"
5024 /* 11870 */ "GLOBAL_GET_FUNCREF\000"
5025 /* 11889 */ "LOCAL_GET_FUNCREF\000"
5026 /* 11907 */ "TABLE_SET_FUNCREF\000"
5027 /* 11925 */ "GLOBAL_SET_FUNCREF\000"
5028 /* 11944 */ "LOCAL_SET_FUNCREF\000"
5029 /* 11962 */ "REF_TEST_FUNCREF\000"
5030 /* 11979 */ "TABLE_GROW_FUNCREF\000"
5031 /* 11998 */ "COPY_FUNCREF\000"
5032 /* 12011 */ "LOCAL_TEE_EXTERNREF\000"
5033 /* 12031 */ "TABLE_FILL_EXTERNREF\000"
5034 /* 12052 */ "REF_NULL_EXTERNREF\000"
5035 /* 12071 */ "REF_IS_NULL_EXTERNREF\000"
5036 /* 12093 */ "DROP_EXTERNREF\000"
5037 /* 12108 */ "SELECT_EXTERNREF\000"
5038 /* 12125 */ "TABLE_GET_EXTERNREF\000"
5039 /* 12145 */ "GLOBAL_GET_EXTERNREF\000"
5040 /* 12166 */ "LOCAL_GET_EXTERNREF\000"
5041 /* 12186 */ "TABLE_SET_EXTERNREF\000"
5042 /* 12206 */ "GLOBAL_SET_EXTERNREF\000"
5043 /* 12227 */ "LOCAL_SET_EXTERNREF\000"
5044 /* 12247 */ "TABLE_GROW_EXTERNREF\000"
5045 /* 12268 */ "COPY_EXTERNREF\000"
5046 /* 12283 */ "LOCAL_TEE_EXNREF\000"
5047 /* 12300 */ "TABLE_FILL_EXNREF\000"
5048 /* 12318 */ "REF_NULL_EXNREF\000"
5049 /* 12334 */ "REF_IS_NULL_EXNREF\000"
5050 /* 12353 */ "DROP_EXNREF\000"
5051 /* 12365 */ "SELECT_EXNREF\000"
5052 /* 12379 */ "TABLE_GET_EXNREF\000"
5053 /* 12396 */ "GLOBAL_GET_EXNREF\000"
5054 /* 12414 */ "LOCAL_GET_EXNREF\000"
5055 /* 12431 */ "TABLE_SET_EXNREF\000"
5056 /* 12448 */ "GLOBAL_SET_EXNREF\000"
5057 /* 12466 */ "LOCAL_SET_EXNREF\000"
5058 /* 12483 */ "TABLE_GROW_EXNREF\000"
5059 /* 12501 */ "COPY_EXNREF\000"
5060 /* 12513 */ "CATCH_REF\000"
5061 /* 12523 */ "CATCH_ALL_REF\000"
5062 /* 12537 */ "DBG_INSTR_REF\000"
5063 /* 12551 */ "THROW_REF\000"
5064 /* 12561 */ "END_IF\000"
5065 /* 12568 */ "BR_IF\000"
5066 /* 12574 */ "G_FNEG\000"
5067 /* 12581 */ "EXTRACT_SUBREG\000"
5068 /* 12596 */ "INSERT_SUBREG\000"
5069 /* 12610 */ "G_SEXT_INREG\000"
5070 /* 12623 */ "SUBREG_TO_REG\000"
5071 /* 12637 */ "G_ATOMIC_CMPXCHG\000"
5072 /* 12654 */ "G_ATOMICRMW_XCHG\000"
5073 /* 12671 */ "G_GET_ROUNDING\000"
5074 /* 12686 */ "G_SET_ROUNDING\000"
5075 /* 12701 */ "G_FLOG\000"
5076 /* 12708 */ "G_VAARG\000"
5077 /* 12716 */ "PREALLOCATED_ARG\000"
5078 /* 12733 */ "CATCH\000"
5079 /* 12739 */ "G_PREFETCH\000"
5080 /* 12750 */ "G_SMULH\000"
5081 /* 12758 */ "G_UMULH\000"
5082 /* 12766 */ "G_FTANH\000"
5083 /* 12774 */ "G_FSINH\000"
5084 /* 12782 */ "G_FCOSH\000"
5085 /* 12790 */ "DBG_PHI\000"
5086 /* 12798 */ "G_FPTOSI\000"
5087 /* 12807 */ "G_FPTOUI\000"
5088 /* 12816 */ "G_FPOWI\000"
5089 /* 12824 */ "END_BLOCK\000"
5090 /* 12834 */ "COPY_LANEMASK\000"
5091 /* 12848 */ "G_PTRMASK\000"
5092 /* 12858 */ "GC_LABEL\000"
5093 /* 12867 */ "DBG_LABEL\000"
5094 /* 12877 */ "EH_LABEL\000"
5095 /* 12886 */ "ANNOTATION_LABEL\000"
5096 /* 12903 */ "ICALL_BRANCH_FUNNEL\000"
5097 /* 12923 */ "G_FSHL\000"
5098 /* 12930 */ "G_SHL\000"
5099 /* 12936 */ "G_FCEIL\000"
5100 /* 12944 */ "G_SAVGCEIL\000"
5101 /* 12955 */ "G_UAVGCEIL\000"
5102 /* 12966 */ "PATCHABLE_TAIL_CALL\000"
5103 /* 12986 */ "RET_CALL\000"
5104 /* 12995 */ "PATCHABLE_TYPED_EVENT_CALL\000"
5105 /* 13022 */ "PATCHABLE_EVENT_CALL\000"
5106 /* 13043 */ "FENTRY_CALL\000"
5107 /* 13055 */ "CATCH_ALL\000"
5108 /* 13065 */ "KILL\000"
5109 /* 13070 */ "G_CONSTANT_POOL\000"
5110 /* 13086 */ "G_ROTL\000"
5111 /* 13093 */ "G_VECREDUCE_FMUL\000"
5112 /* 13110 */ "G_FMUL\000"
5113 /* 13117 */ "G_VECREDUCE_SEQ_FMUL\000"
5114 /* 13138 */ "G_STRICT_FMUL\000"
5115 /* 13152 */ "G_VECREDUCE_MUL\000"
5116 /* 13168 */ "G_MUL\000"
5117 /* 13174 */ "G_FREM\000"
5118 /* 13181 */ "G_STRICT_FREM\000"
5119 /* 13195 */ "G_SREM\000"
5120 /* 13202 */ "G_UREM\000"
5121 /* 13209 */ "G_SDIVREM\000"
5122 /* 13219 */ "G_UDIVREM\000"
5123 /* 13229 */ "INLINEASM\000"
5124 /* 13239 */ "G_VECREDUCE_FMINIMUM\000"
5125 /* 13260 */ "G_FMINIMUM\000"
5126 /* 13271 */ "G_ATOMICRMW_FMINIMUM\000"
5127 /* 13292 */ "G_VECREDUCE_FMAXIMUM\000"
5128 /* 13313 */ "G_FMAXIMUM\000"
5129 /* 13324 */ "G_ATOMICRMW_FMAXIMUM\000"
5130 /* 13345 */ "G_FMINIMUMNUM\000"
5131 /* 13359 */ "G_ATOMICRMW_FMINIMUMNUM\000"
5132 /* 13383 */ "G_FMAXIMUMNUM\000"
5133 /* 13397 */ "G_ATOMICRMW_FMAXIMUMNUM\000"
5134 /* 13421 */ "G_FMINNUM\000"
5135 /* 13431 */ "G_FMAXNUM\000"
5136 /* 13441 */ "G_FATAN\000"
5137 /* 13449 */ "G_FTAN\000"
5138 /* 13456 */ "G_INTRINSIC_ROUNDEVEN\000"
5139 /* 13478 */ "G_ASSERT_ALIGN\000"
5140 /* 13493 */ "G_FCOPYSIGN\000"
5141 /* 13505 */ "G_VECREDUCE_FMIN\000"
5142 /* 13522 */ "G_ATOMICRMW_FMIN\000"
5143 /* 13539 */ "G_VECREDUCE_SMIN\000"
5144 /* 13556 */ "G_SMIN\000"
5145 /* 13563 */ "G_VECREDUCE_UMIN\000"
5146 /* 13580 */ "G_UMIN\000"
5147 /* 13587 */ "G_ATOMICRMW_UMIN\000"
5148 /* 13604 */ "G_ATOMICRMW_MIN\000"
5149 /* 13620 */ "G_FASIN\000"
5150 /* 13628 */ "G_FSIN\000"
5151 /* 13635 */ "END_FUNCTION\000"
5152 /* 13648 */ "CFI_INSTRUCTION\000"
5153 /* 13664 */ "FALLTHROUGH_RETURN\000"
5154 /* 13683 */ "ADJCALLSTACKDOWN\000"
5155 /* 13700 */ "G_SSUBO\000"
5156 /* 13708 */ "G_USUBO\000"
5157 /* 13716 */ "G_SADDO\000"
5158 /* 13724 */ "G_UADDO\000"
5159 /* 13732 */ "JUMP_TABLE_DEBUG_INFO\000"
5160 /* 13754 */ "G_SMULO\000"
5161 /* 13762 */ "G_UMULO\000"
5162 /* 13770 */ "G_BZERO\000"
5163 /* 13778 */ "STACKMAP\000"
5164 /* 13787 */ "G_DEBUGTRAP\000"
5165 /* 13799 */ "G_UBSANTRAP\000"
5166 /* 13811 */ "G_TRAP\000"
5167 /* 13818 */ "G_ATOMICRMW_UDEC_WRAP\000"
5168 /* 13840 */ "G_ATOMICRMW_UINC_WRAP\000"
5169 /* 13862 */ "G_BSWAP\000"
5170 /* 13870 */ "G_SITOFP\000"
5171 /* 13879 */ "G_UITOFP\000"
5172 /* 13888 */ "G_FCMP\000"
5173 /* 13895 */ "G_ICMP\000"
5174 /* 13902 */ "G_SCMP\000"
5175 /* 13909 */ "G_UCMP\000"
5176 /* 13916 */ "NOP\000"
5177 /* 13920 */ "END_LOOP\000"
5178 /* 13929 */ "CONVERGENCECTRL_LOOP\000"
5179 /* 13950 */ "G_CTPOP\000"
5180 /* 13958 */ "DATA_DROP\000"
5181 /* 13968 */ "PATCHABLE_OP\000"
5182 /* 13981 */ "FAULTING_OP\000"
5183 /* 13993 */ "ADJCALLSTACKUP\000"
5184 /* 14008 */ "PREALLOCATED_SETUP\000"
5185 /* 14027 */ "G_FLDEXP\000"
5186 /* 14036 */ "G_STRICT_FLDEXP\000"
5187 /* 14052 */ "G_FEXP\000"
5188 /* 14059 */ "G_FFREXP\000"
5189 /* 14068 */ "G_BR\000"
5190 /* 14073 */ "INLINEASM_BR\000"
5191 /* 14086 */ "G_BLOCK_ADDR\000"
5192 /* 14099 */ "MEMBARRIER\000"
5193 /* 14110 */ "G_CONSTANT_FOLD_BARRIER\000"
5194 /* 14134 */ "PATCHABLE_FUNCTION_ENTER\000"
5195 /* 14159 */ "G_READCYCLECOUNTER\000"
5196 /* 14178 */ "G_READSTEADYCOUNTER\000"
5197 /* 14198 */ "G_READ_REGISTER\000"
5198 /* 14214 */ "G_WRITE_REGISTER\000"
5199 /* 14231 */ "G_ASHR\000"
5200 /* 14238 */ "G_FSHR\000"
5201 /* 14245 */ "G_LSHR\000"
5202 /* 14252 */ "CONVERGENCECTRL_ANCHOR\000"
5203 /* 14275 */ "G_FFLOOR\000"
5204 /* 14284 */ "G_SAVGFLOOR\000"
5205 /* 14296 */ "G_UAVGFLOOR\000"
5206 /* 14308 */ "G_EXTRACT_SUBVECTOR\000"
5207 /* 14328 */ "G_INSERT_SUBVECTOR\000"
5208 /* 14347 */ "G_BUILD_VECTOR\000"
5209 /* 14362 */ "G_SHUFFLE_VECTOR\000"
5210 /* 14379 */ "G_STEP_VECTOR\000"
5211 /* 14393 */ "G_SPLAT_VECTOR\000"
5212 /* 14408 */ "G_VECREDUCE_XOR\000"
5213 /* 14424 */ "G_XOR\000"
5214 /* 14430 */ "G_ATOMICRMW_XOR\000"
5215 /* 14446 */ "G_VECREDUCE_OR\000"
5216 /* 14461 */ "G_OR\000"
5217 /* 14466 */ "G_ATOMICRMW_OR\000"
5218 /* 14481 */ "G_ROTR\000"
5219 /* 14488 */ "G_INTTOPTR\000"
5220 /* 14499 */ "G_FABS\000"
5221 /* 14506 */ "G_ABS\000"
5222 /* 14512 */ "G_ABDS\000"
5223 /* 14519 */ "G_UNMERGE_VALUES\000"
5224 /* 14536 */ "G_MERGE_VALUES\000"
5225 /* 14551 */ "G_CTLS\000"
5226 /* 14558 */ "CALL_PARAMS\000"
5227 /* 14570 */ "G_FACOS\000"
5228 /* 14578 */ "G_FCOS\000"
5229 /* 14585 */ "G_FSINCOS\000"
5230 /* 14595 */ "G_CONCAT_VECTORS\000"
5231 /* 14612 */ "COPY_TO_REGCLASS\000"
5232 /* 14629 */ "G_IS_FPCLASS\000"
5233 /* 14642 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000"
5234 /* 14672 */ "BR_UNLESS\000"
5235 /* 14682 */ "G_VECTOR_COMPRESS\000"
5236 /* 14700 */ "G_INTRINSIC_W_SIDE_EFFECTS\000"
5237 /* 14727 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000"
5238 /* 14765 */ "RET_CALL_RESULTS\000"
5239 /* 14782 */ "LOAD_F16_F32_A32_S\000"
5240 /* 14801 */ "STORE_F16_F32_A32_S\000"
5241 /* 14821 */ "LOAD_F32_A32_S\000"
5242 /* 14836 */ "STORE_F32_A32_S\000"
5243 /* 14852 */ "ATOMIC_STORE16_I32_A32_S\000"
5244 /* 14877 */ "ATOMIC_STORE8_I32_A32_S\000"
5245 /* 14901 */ "ATOMIC_RMW16_U_SUB_I32_A32_S\000"
5246 /* 14930 */ "ATOMIC_RMW8_U_SUB_I32_A32_S\000"
5247 /* 14958 */ "ATOMIC_RMW_SUB_I32_A32_S\000"
5248 /* 14983 */ "ATOMIC_LOAD_I32_A32_S\000"
5249 /* 15005 */ "ATOMIC_RMW16_U_ADD_I32_A32_S\000"
5250 /* 15034 */ "ATOMIC_RMW8_U_ADD_I32_A32_S\000"
5251 /* 15062 */ "ATOMIC_RMW_ADD_I32_A32_S\000"
5252 /* 15087 */ "ATOMIC_RMW16_U_AND_I32_A32_S\000"
5253 /* 15116 */ "ATOMIC_RMW8_U_AND_I32_A32_S\000"
5254 /* 15144 */ "ATOMIC_RMW_AND_I32_A32_S\000"
5255 /* 15169 */ "ATOMIC_STORE_I32_A32_S\000"
5256 /* 15192 */ "ATOMIC_RMW16_U_CMPXCHG_I32_A32_S\000"
5257 /* 15225 */ "ATOMIC_RMW8_U_CMPXCHG_I32_A32_S\000"
5258 /* 15257 */ "ATOMIC_RMW_CMPXCHG_I32_A32_S\000"
5259 /* 15286 */ "ATOMIC_RMW16_U_XCHG_I32_A32_S\000"
5260 /* 15316 */ "ATOMIC_RMW8_U_XCHG_I32_A32_S\000"
5261 /* 15345 */ "ATOMIC_RMW_XCHG_I32_A32_S\000"
5262 /* 15371 */ "ATOMIC_RMW16_U_XOR_I32_A32_S\000"
5263 /* 15400 */ "ATOMIC_RMW8_U_XOR_I32_A32_S\000"
5264 /* 15428 */ "ATOMIC_RMW_XOR_I32_A32_S\000"
5265 /* 15453 */ "ATOMIC_RMW16_U_OR_I32_A32_S\000"
5266 /* 15481 */ "ATOMIC_RMW8_U_OR_I32_A32_S\000"
5267 /* 15508 */ "ATOMIC_RMW_OR_I32_A32_S\000"
5268 /* 15532 */ "LOAD16_S_I32_A32_S\000"
5269 /* 15551 */ "LOAD8_S_I32_A32_S\000"
5270 /* 15569 */ "ATOMIC_LOAD16_U_I32_A32_S\000"
5271 /* 15595 */ "ATOMIC_LOAD8_U_I32_A32_S\000"
5272 /* 15620 */ "MEMORY_ATOMIC_WAIT32_A32_S\000"
5273 /* 15647 */ "LOAD_LANE_32_A32_S\000"
5274 /* 15666 */ "LOAD_ZERO_32_A32_S\000"
5275 /* 15685 */ "STORE_LANE_I64x2_A32_S\000"
5276 /* 15708 */ "LOAD_EXTEND_S_I64x2_A32_S\000"
5277 /* 15734 */ "LOAD_EXTEND_U_I64x2_A32_S\000"
5278 /* 15760 */ "LOAD_F64_A32_S\000"
5279 /* 15775 */ "STORE_F64_A32_S\000"
5280 /* 15791 */ "ATOMIC_STORE32_I64_A32_S\000"
5281 /* 15816 */ "ATOMIC_STORE16_I64_A32_S\000"
5282 /* 15841 */ "ATOMIC_STORE8_I64_A32_S\000"
5283 /* 15865 */ "ATOMIC_RMW32_U_SUB_I64_A32_S\000"
5284 /* 15894 */ "ATOMIC_RMW16_U_SUB_I64_A32_S\000"
5285 /* 15923 */ "ATOMIC_RMW8_U_SUB_I64_A32_S\000"
5286 /* 15951 */ "ATOMIC_RMW_SUB_I64_A32_S\000"
5287 /* 15976 */ "ATOMIC_LOAD_I64_A32_S\000"
5288 /* 15998 */ "ATOMIC_RMW32_U_ADD_I64_A32_S\000"
5289 /* 16027 */ "ATOMIC_RMW16_U_ADD_I64_A32_S\000"
5290 /* 16056 */ "ATOMIC_RMW8_U_ADD_I64_A32_S\000"
5291 /* 16084 */ "ATOMIC_RMW_ADD_I64_A32_S\000"
5292 /* 16109 */ "ATOMIC_RMW32_U_AND_I64_A32_S\000"
5293 /* 16138 */ "ATOMIC_RMW16_U_AND_I64_A32_S\000"
5294 /* 16167 */ "ATOMIC_RMW8_U_AND_I64_A32_S\000"
5295 /* 16195 */ "ATOMIC_RMW_AND_I64_A32_S\000"
5296 /* 16220 */ "ATOMIC_STORE_I64_A32_S\000"
5297 /* 16243 */ "ATOMIC_RMW32_U_CMPXCHG_I64_A32_S\000"
5298 /* 16276 */ "ATOMIC_RMW16_U_CMPXCHG_I64_A32_S\000"
5299 /* 16309 */ "ATOMIC_RMW8_U_CMPXCHG_I64_A32_S\000"
5300 /* 16341 */ "ATOMIC_RMW_CMPXCHG_I64_A32_S\000"
5301 /* 16370 */ "ATOMIC_RMW32_U_XCHG_I64_A32_S\000"
5302 /* 16400 */ "ATOMIC_RMW16_U_XCHG_I64_A32_S\000"
5303 /* 16430 */ "ATOMIC_RMW8_U_XCHG_I64_A32_S\000"
5304 /* 16459 */ "ATOMIC_RMW_XCHG_I64_A32_S\000"
5305 /* 16485 */ "ATOMIC_RMW32_U_XOR_I64_A32_S\000"
5306 /* 16514 */ "ATOMIC_RMW16_U_XOR_I64_A32_S\000"
5307 /* 16543 */ "ATOMIC_RMW8_U_XOR_I64_A32_S\000"
5308 /* 16571 */ "ATOMIC_RMW_XOR_I64_A32_S\000"
5309 /* 16596 */ "ATOMIC_RMW32_U_OR_I64_A32_S\000"
5310 /* 16624 */ "ATOMIC_RMW16_U_OR_I64_A32_S\000"
5311 /* 16652 */ "ATOMIC_RMW8_U_OR_I64_A32_S\000"
5312 /* 16679 */ "ATOMIC_RMW_OR_I64_A32_S\000"
5313 /* 16703 */ "LOAD32_S_I64_A32_S\000"
5314 /* 16722 */ "LOAD16_S_I64_A32_S\000"
5315 /* 16741 */ "LOAD8_S_I64_A32_S\000"
5316 /* 16759 */ "ATOMIC_LOAD32_U_I64_A32_S\000"
5317 /* 16785 */ "ATOMIC_LOAD16_U_I64_A32_S\000"
5318 /* 16811 */ "ATOMIC_LOAD8_U_I64_A32_S\000"
5319 /* 16836 */ "MEMORY_ATOMIC_WAIT64_A32_S\000"
5320 /* 16863 */ "LOAD_LANE_64_A32_S\000"
5321 /* 16882 */ "LOAD_ZERO_64_A32_S\000"
5322 /* 16901 */ "STORE_LANE_I32x4_A32_S\000"
5323 /* 16924 */ "LOAD_EXTEND_S_I32x4_A32_S\000"
5324 /* 16950 */ "LOAD_EXTEND_U_I32x4_A32_S\000"
5325 /* 16976 */ "LOAD_LANE_16_A32_S\000"
5326 /* 16995 */ "STORE_LANE_I8x16_A32_S\000"
5327 /* 17018 */ "LOAD_V128_A32_S\000"
5328 /* 17034 */ "STORE_V128_A32_S\000"
5329 /* 17051 */ "LOAD_LANE_8_A32_S\000"
5330 /* 17069 */ "STORE_LANE_I16x8_A32_S\000"
5331 /* 17092 */ "LOAD_EXTEND_S_I16x8_A32_S\000"
5332 /* 17118 */ "LOAD_EXTEND_U_I16x8_A32_S\000"
5333 /* 17144 */ "anonymous_13975MEMORY_SIZE_A32_S\000"
5334 /* 17177 */ "MEMORY_FILL_A32_S\000"
5335 /* 17195 */ "LOAD32_SPLAT_A32_S\000"
5336 /* 17214 */ "LOAD64_SPLAT_A32_S\000"
5337 /* 17233 */ "LOAD16_SPLAT_A32_S\000"
5338 /* 17252 */ "LOAD8_SPLAT_A32_S\000"
5339 /* 17270 */ "MEMSET_A32_S\000"
5340 /* 17283 */ "MEMORY_INIT_A32_S\000"
5341 /* 17301 */ "anonymous_13975MEMORY_GROW_A32_S\000"
5342 /* 17334 */ "MEMORY_ATOMIC_NOTIFY_A32_S\000"
5343 /* 17361 */ "MEMCPY_A32_S\000"
5344 /* 17374 */ "MEMORY_COPY_A32_S\000"
5345 /* 17392 */ "FP_TO_SINT_I32_F32_S\000"
5346 /* 17413 */ "FP_TO_UINT_I32_F32_S\000"
5347 /* 17434 */ "FP_TO_SINT_I64_F32_S\000"
5348 /* 17455 */ "FP_TO_UINT_I64_F32_S\000"
5349 /* 17476 */ "SUB_F32_S\000"
5350 /* 17486 */ "TRUNC_F32_S\000"
5351 /* 17498 */ "ADD_F32_S\000"
5352 /* 17508 */ "LOCAL_TEE_F32_S\000"
5353 /* 17524 */ "GE_F32_S\000"
5354 /* 17533 */ "LE_F32_S\000"
5355 /* 17542 */ "NE_F32_S\000"
5356 /* 17551 */ "F64_PROMOTE_F32_S\000"
5357 /* 17569 */ "NEG_F32_S\000"
5358 /* 17579 */ "CEIL_F32_S\000"
5359 /* 17590 */ "MUL_F32_S\000"
5360 /* 17600 */ "COPYSIGN_F32_S\000"
5361 /* 17615 */ "MIN_F32_S\000"
5362 /* 17625 */ "DROP_F32_S\000"
5363 /* 17636 */ "EQ_F32_S\000"
5364 /* 17645 */ "FLOOR_F32_S\000"
5365 /* 17657 */ "ABS_F32_S\000"
5366 /* 17667 */ "I32_TRUNC_S_F32_S\000"
5367 /* 17685 */ "I64_TRUNC_S_F32_S\000"
5368 /* 17703 */ "I32_TRUNC_S_SAT_F32_S\000"
5369 /* 17725 */ "I64_TRUNC_S_SAT_F32_S\000"
5370 /* 17747 */ "I32_TRUNC_U_SAT_F32_S\000"
5371 /* 17769 */ "I64_TRUNC_U_SAT_F32_S\000"
5372 /* 17791 */ "SELECT_F32_S\000"
5373 /* 17804 */ "GLOBAL_GET_F32_S\000"
5374 /* 17821 */ "LOCAL_GET_F32_S\000"
5375 /* 17837 */ "I32_REINTERPRET_F32_S\000"
5376 /* 17859 */ "GLOBAL_SET_F32_S\000"
5377 /* 17876 */ "LOCAL_SET_F32_S\000"
5378 /* 17892 */ "GT_F32_S\000"
5379 /* 17901 */ "LT_F32_S\000"
5380 /* 17910 */ "SQRT_F32_S\000"
5381 /* 17921 */ "NEAREST_F32_S\000"
5382 /* 17935 */ "CONST_F32_S\000"
5383 /* 17947 */ "I32_TRUNC_U_F32_S\000"
5384 /* 17965 */ "I64_TRUNC_U_F32_S\000"
5385 /* 17983 */ "DIV_F32_S\000"
5386 /* 17993 */ "MAX_F32_S\000"
5387 /* 18003 */ "COPY_F32_S\000"
5388 /* 18014 */ "SUB_I32_S\000"
5389 /* 18024 */ "ADD_I32_S\000"
5390 /* 18034 */ "AND_I32_S\000"
5391 /* 18044 */ "LOCAL_TEE_I32_S\000"
5392 /* 18060 */ "BR_TABLE_I32_S\000"
5393 /* 18075 */ "NE_I32_S\000"
5394 /* 18084 */ "SHL_I32_S\000"
5395 /* 18094 */ "ROTL_I32_S\000"
5396 /* 18105 */ "MUL_I32_S\000"
5397 /* 18115 */ "DROP_I32_S\000"
5398 /* 18126 */ "EQ_I32_S\000"
5399 /* 18135 */ "XOR_I32_S\000"
5400 /* 18145 */ "ROTR_I32_S\000"
5401 /* 18156 */ "I32_EXTEND16_S_I32_S\000"
5402 /* 18177 */ "I32_EXTEND8_S_I32_S\000"
5403 /* 18197 */ "I64_EXTEND_S_I32_S\000"
5404 /* 18216 */ "GE_S_I32_S\000"
5405 /* 18227 */ "LE_S_I32_S\000"
5406 /* 18238 */ "REM_S_I32_S\000"
5407 /* 18250 */ "SHR_S_I32_S\000"
5408 /* 18262 */ "GT_S_I32_S\000"
5409 /* 18273 */ "LT_S_I32_S\000"
5410 /* 18284 */ "F32_CONVERT_S_I32_S\000"
5411 /* 18304 */ "F64_CONVERT_S_I32_S\000"
5412 /* 18324 */ "DIV_S_I32_S\000"
5413 /* 18336 */ "SELECT_I32_S\000"
5414 /* 18349 */ "GLOBAL_GET_I32_S\000"
5415 /* 18366 */ "LOCAL_GET_I32_S\000"
5416 /* 18382 */ "F32_REINTERPRET_I32_S\000"
5417 /* 18404 */ "GLOBAL_SET_I32_S\000"
5418 /* 18421 */ "LOCAL_SET_I32_S\000"
5419 /* 18437 */ "POPCNT_I32_S\000"
5420 /* 18450 */ "CONST_I32_S\000"
5421 /* 18462 */ "I64_EXTEND_U_I32_S\000"
5422 /* 18481 */ "GE_U_I32_S\000"
5423 /* 18492 */ "LE_U_I32_S\000"
5424 /* 18503 */ "REM_U_I32_S\000"
5425 /* 18515 */ "SHR_U_I32_S\000"
5426 /* 18527 */ "GT_U_I32_S\000"
5427 /* 18538 */ "LT_U_I32_S\000"
5428 /* 18549 */ "F32_CONVERT_U_I32_S\000"
5429 /* 18569 */ "F64_CONVERT_U_I32_S\000"
5430 /* 18589 */ "DIV_U_I32_S\000"
5431 /* 18601 */ "COPY_I32_S\000"
5432 /* 18612 */ "CLZ_I32_S\000"
5433 /* 18622 */ "EQZ_I32_S\000"
5434 /* 18632 */ "CTZ_I32_S\000"
5435 /* 18642 */ "ARGUMENT_v4f32_S\000"
5436 /* 18659 */ "ARGUMENT_f32_S\000"
5437 /* 18674 */ "ARGUMENT_v4i32_S\000"
5438 /* 18691 */ "ARGUMENT_i32_S\000"
5439 /* 18706 */ "CONST_V128_F64x2_S\000"
5440 /* 18725 */ "SUB_F64x2_S\000"
5441 /* 18737 */ "TRUNC_F64x2_S\000"
5442 /* 18751 */ "NMADD_F64x2_S\000"
5443 /* 18765 */ "GE_F64x2_S\000"
5444 /* 18776 */ "LE_F64x2_S\000"
5445 /* 18787 */ "REPLACE_LANE_F64x2_S\000"
5446 /* 18808 */ "EXTRACT_LANE_F64x2_S\000"
5447 /* 18829 */ "NEG_F64x2_S\000"
5448 /* 18841 */ "CEIL_F64x2_S\000"
5449 /* 18854 */ "MUL_F64x2_S\000"
5450 /* 18866 */ "SIMD_RELAXED_FMIN_F64x2_S\000"
5451 /* 18892 */ "PMIN_F64x2_S\000"
5452 /* 18905 */ "EQ_F64x2_S\000"
5453 /* 18916 */ "FLOOR_F64x2_S\000"
5454 /* 18930 */ "ABS_F64x2_S\000"
5455 /* 18942 */ "SPLAT_F64x2_S\000"
5456 /* 18956 */ "GT_F64x2_S\000"
5457 /* 18967 */ "LT_F64x2_S\000"
5458 /* 18978 */ "SQRT_F64x2_S\000"
5459 /* 18991 */ "NEAREST_F64x2_S\000"
5460 /* 19007 */ "DIV_F64x2_S\000"
5461 /* 19019 */ "SIMD_RELAXED_FMAX_F64x2_S\000"
5462 /* 19045 */ "PMAX_F64x2_S\000"
5463 /* 19058 */ "convert_low_s_F64x2_S\000"
5464 /* 19080 */ "convert_low_u_F64x2_S\000"
5465 /* 19102 */ "promote_low_F64x2_S\000"
5466 /* 19122 */ "CONST_V128_I64x2_S\000"
5467 /* 19141 */ "SUB_I64x2_S\000"
5468 /* 19153 */ "ADD_I64x2_S\000"
5469 /* 19165 */ "REPLACE_LANE_I64x2_S\000"
5470 /* 19186 */ "EXTRACT_LANE_I64x2_S\000"
5471 /* 19207 */ "ALLTRUE_I64x2_S\000"
5472 /* 19223 */ "NEG_I64x2_S\000"
5473 /* 19235 */ "BITMASK_I64x2_S\000"
5474 /* 19251 */ "SHL_I64x2_S\000"
5475 /* 19263 */ "MUL_I64x2_S\000"
5476 /* 19275 */ "EQ_I64x2_S\000"
5477 /* 19286 */ "ABS_I64x2_S\000"
5478 /* 19298 */ "GE_S_I64x2_S\000"
5479 /* 19311 */ "LE_S_I64x2_S\000"
5480 /* 19324 */ "EXTMUL_HIGH_S_I64x2_S\000"
5481 /* 19346 */ "SHR_S_I64x2_S\000"
5482 /* 19360 */ "GT_S_I64x2_S\000"
5483 /* 19373 */ "LT_S_I64x2_S\000"
5484 /* 19386 */ "EXTMUL_LOW_S_I64x2_S\000"
5485 /* 19407 */ "SPLAT_I64x2_S\000"
5486 /* 19421 */ "LANESELECT_I64x2_S\000"
5487 /* 19440 */ "EXTMUL_HIGH_U_I64x2_S\000"
5488 /* 19462 */ "SHR_U_I64x2_S\000"
5489 /* 19476 */ "EXTMUL_LOW_U_I64x2_S\000"
5490 /* 19497 */ "extend_high_s_I64x2_S\000"
5491 /* 19519 */ "extend_low_s_I64x2_S\000"
5492 /* 19540 */ "extend_high_u_I64x2_S\000"
5493 /* 19562 */ "extend_low_u_I64x2_S\000"
5494 /* 19583 */ "LOAD_F16_F32_A64_S\000"
5495 /* 19602 */ "STORE_F16_F32_A64_S\000"
5496 /* 19622 */ "LOAD_F32_A64_S\000"
5497 /* 19637 */ "STORE_F32_A64_S\000"
5498 /* 19653 */ "ATOMIC_STORE16_I32_A64_S\000"
5499 /* 19678 */ "ATOMIC_STORE8_I32_A64_S\000"
5500 /* 19702 */ "ATOMIC_RMW16_U_SUB_I32_A64_S\000"
5501 /* 19731 */ "ATOMIC_RMW8_U_SUB_I32_A64_S\000"
5502 /* 19759 */ "ATOMIC_RMW_SUB_I32_A64_S\000"
5503 /* 19784 */ "ATOMIC_LOAD_I32_A64_S\000"
5504 /* 19806 */ "ATOMIC_RMW16_U_ADD_I32_A64_S\000"
5505 /* 19835 */ "ATOMIC_RMW8_U_ADD_I32_A64_S\000"
5506 /* 19863 */ "ATOMIC_RMW_ADD_I32_A64_S\000"
5507 /* 19888 */ "ATOMIC_RMW16_U_AND_I32_A64_S\000"
5508 /* 19917 */ "ATOMIC_RMW8_U_AND_I32_A64_S\000"
5509 /* 19945 */ "ATOMIC_RMW_AND_I32_A64_S\000"
5510 /* 19970 */ "ATOMIC_STORE_I32_A64_S\000"
5511 /* 19993 */ "ATOMIC_RMW16_U_CMPXCHG_I32_A64_S\000"
5512 /* 20026 */ "ATOMIC_RMW8_U_CMPXCHG_I32_A64_S\000"
5513 /* 20058 */ "ATOMIC_RMW_CMPXCHG_I32_A64_S\000"
5514 /* 20087 */ "ATOMIC_RMW16_U_XCHG_I32_A64_S\000"
5515 /* 20117 */ "ATOMIC_RMW8_U_XCHG_I32_A64_S\000"
5516 /* 20146 */ "ATOMIC_RMW_XCHG_I32_A64_S\000"
5517 /* 20172 */ "ATOMIC_RMW16_U_XOR_I32_A64_S\000"
5518 /* 20201 */ "ATOMIC_RMW8_U_XOR_I32_A64_S\000"
5519 /* 20229 */ "ATOMIC_RMW_XOR_I32_A64_S\000"
5520 /* 20254 */ "ATOMIC_RMW16_U_OR_I32_A64_S\000"
5521 /* 20282 */ "ATOMIC_RMW8_U_OR_I32_A64_S\000"
5522 /* 20309 */ "ATOMIC_RMW_OR_I32_A64_S\000"
5523 /* 20333 */ "LOAD16_S_I32_A64_S\000"
5524 /* 20352 */ "LOAD8_S_I32_A64_S\000"
5525 /* 20370 */ "ATOMIC_LOAD16_U_I32_A64_S\000"
5526 /* 20396 */ "ATOMIC_LOAD8_U_I32_A64_S\000"
5527 /* 20421 */ "MEMORY_ATOMIC_WAIT32_A64_S\000"
5528 /* 20448 */ "LOAD_LANE_32_A64_S\000"
5529 /* 20467 */ "LOAD_ZERO_32_A64_S\000"
5530 /* 20486 */ "STORE_LANE_I64x2_A64_S\000"
5531 /* 20509 */ "LOAD_EXTEND_S_I64x2_A64_S\000"
5532 /* 20535 */ "LOAD_EXTEND_U_I64x2_A64_S\000"
5533 /* 20561 */ "LOAD_F64_A64_S\000"
5534 /* 20576 */ "STORE_F64_A64_S\000"
5535 /* 20592 */ "ATOMIC_STORE32_I64_A64_S\000"
5536 /* 20617 */ "ATOMIC_STORE16_I64_A64_S\000"
5537 /* 20642 */ "ATOMIC_STORE8_I64_A64_S\000"
5538 /* 20666 */ "ATOMIC_RMW32_U_SUB_I64_A64_S\000"
5539 /* 20695 */ "ATOMIC_RMW16_U_SUB_I64_A64_S\000"
5540 /* 20724 */ "ATOMIC_RMW8_U_SUB_I64_A64_S\000"
5541 /* 20752 */ "ATOMIC_RMW_SUB_I64_A64_S\000"
5542 /* 20777 */ "ATOMIC_LOAD_I64_A64_S\000"
5543 /* 20799 */ "ATOMIC_RMW32_U_ADD_I64_A64_S\000"
5544 /* 20828 */ "ATOMIC_RMW16_U_ADD_I64_A64_S\000"
5545 /* 20857 */ "ATOMIC_RMW8_U_ADD_I64_A64_S\000"
5546 /* 20885 */ "ATOMIC_RMW_ADD_I64_A64_S\000"
5547 /* 20910 */ "ATOMIC_RMW32_U_AND_I64_A64_S\000"
5548 /* 20939 */ "ATOMIC_RMW16_U_AND_I64_A64_S\000"
5549 /* 20968 */ "ATOMIC_RMW8_U_AND_I64_A64_S\000"
5550 /* 20996 */ "ATOMIC_RMW_AND_I64_A64_S\000"
5551 /* 21021 */ "ATOMIC_STORE_I64_A64_S\000"
5552 /* 21044 */ "ATOMIC_RMW32_U_CMPXCHG_I64_A64_S\000"
5553 /* 21077 */ "ATOMIC_RMW16_U_CMPXCHG_I64_A64_S\000"
5554 /* 21110 */ "ATOMIC_RMW8_U_CMPXCHG_I64_A64_S\000"
5555 /* 21142 */ "ATOMIC_RMW_CMPXCHG_I64_A64_S\000"
5556 /* 21171 */ "ATOMIC_RMW32_U_XCHG_I64_A64_S\000"
5557 /* 21201 */ "ATOMIC_RMW16_U_XCHG_I64_A64_S\000"
5558 /* 21231 */ "ATOMIC_RMW8_U_XCHG_I64_A64_S\000"
5559 /* 21260 */ "ATOMIC_RMW_XCHG_I64_A64_S\000"
5560 /* 21286 */ "ATOMIC_RMW32_U_XOR_I64_A64_S\000"
5561 /* 21315 */ "ATOMIC_RMW16_U_XOR_I64_A64_S\000"
5562 /* 21344 */ "ATOMIC_RMW8_U_XOR_I64_A64_S\000"
5563 /* 21372 */ "ATOMIC_RMW_XOR_I64_A64_S\000"
5564 /* 21397 */ "ATOMIC_RMW32_U_OR_I64_A64_S\000"
5565 /* 21425 */ "ATOMIC_RMW16_U_OR_I64_A64_S\000"
5566 /* 21453 */ "ATOMIC_RMW8_U_OR_I64_A64_S\000"
5567 /* 21480 */ "ATOMIC_RMW_OR_I64_A64_S\000"
5568 /* 21504 */ "LOAD32_S_I64_A64_S\000"
5569 /* 21523 */ "LOAD16_S_I64_A64_S\000"
5570 /* 21542 */ "LOAD8_S_I64_A64_S\000"
5571 /* 21560 */ "ATOMIC_LOAD32_U_I64_A64_S\000"
5572 /* 21586 */ "ATOMIC_LOAD16_U_I64_A64_S\000"
5573 /* 21612 */ "ATOMIC_LOAD8_U_I64_A64_S\000"
5574 /* 21637 */ "MEMORY_ATOMIC_WAIT64_A64_S\000"
5575 /* 21664 */ "LOAD_LANE_64_A64_S\000"
5576 /* 21683 */ "LOAD_ZERO_64_A64_S\000"
5577 /* 21702 */ "STORE_LANE_I32x4_A64_S\000"
5578 /* 21725 */ "LOAD_EXTEND_S_I32x4_A64_S\000"
5579 /* 21751 */ "LOAD_EXTEND_U_I32x4_A64_S\000"
5580 /* 21777 */ "LOAD_LANE_16_A64_S\000"
5581 /* 21796 */ "STORE_LANE_I8x16_A64_S\000"
5582 /* 21819 */ "LOAD_V128_A64_S\000"
5583 /* 21835 */ "STORE_V128_A64_S\000"
5584 /* 21852 */ "LOAD_LANE_8_A64_S\000"
5585 /* 21870 */ "STORE_LANE_I16x8_A64_S\000"
5586 /* 21893 */ "LOAD_EXTEND_S_I16x8_A64_S\000"
5587 /* 21919 */ "LOAD_EXTEND_U_I16x8_A64_S\000"
5588 /* 21945 */ "anonymous_13976MEMORY_SIZE_A64_S\000"
5589 /* 21978 */ "MEMORY_FILL_A64_S\000"
5590 /* 21996 */ "LOAD32_SPLAT_A64_S\000"
5591 /* 22015 */ "LOAD64_SPLAT_A64_S\000"
5592 /* 22034 */ "LOAD16_SPLAT_A64_S\000"
5593 /* 22053 */ "LOAD8_SPLAT_A64_S\000"
5594 /* 22071 */ "MEMSET_A64_S\000"
5595 /* 22084 */ "MEMORY_INIT_A64_S\000"
5596 /* 22102 */ "anonymous_13976MEMORY_GROW_A64_S\000"
5597 /* 22135 */ "MEMORY_ATOMIC_NOTIFY_A64_S\000"
5598 /* 22162 */ "MEMCPY_A64_S\000"
5599 /* 22175 */ "MEMORY_COPY_A64_S\000"
5600 /* 22193 */ "FP_TO_SINT_I32_F64_S\000"
5601 /* 22214 */ "FP_TO_UINT_I32_F64_S\000"
5602 /* 22235 */ "FP_TO_SINT_I64_F64_S\000"
5603 /* 22256 */ "FP_TO_UINT_I64_F64_S\000"
5604 /* 22277 */ "SUB_F64_S\000"
5605 /* 22287 */ "TRUNC_F64_S\000"
5606 /* 22299 */ "ADD_F64_S\000"
5607 /* 22309 */ "LOCAL_TEE_F64_S\000"
5608 /* 22325 */ "GE_F64_S\000"
5609 /* 22334 */ "LE_F64_S\000"
5610 /* 22343 */ "NE_F64_S\000"
5611 /* 22352 */ "F32_DEMOTE_F64_S\000"
5612 /* 22369 */ "NEG_F64_S\000"
5613 /* 22379 */ "CEIL_F64_S\000"
5614 /* 22390 */ "MUL_F64_S\000"
5615 /* 22400 */ "COPYSIGN_F64_S\000"
5616 /* 22415 */ "MIN_F64_S\000"
5617 /* 22425 */ "DROP_F64_S\000"
5618 /* 22436 */ "EQ_F64_S\000"
5619 /* 22445 */ "FLOOR_F64_S\000"
5620 /* 22457 */ "ABS_F64_S\000"
5621 /* 22467 */ "I32_TRUNC_S_F64_S\000"
5622 /* 22485 */ "I64_TRUNC_S_F64_S\000"
5623 /* 22503 */ "I32_TRUNC_S_SAT_F64_S\000"
5624 /* 22525 */ "I64_TRUNC_S_SAT_F64_S\000"
5625 /* 22547 */ "I32_TRUNC_U_SAT_F64_S\000"
5626 /* 22569 */ "I64_TRUNC_U_SAT_F64_S\000"
5627 /* 22591 */ "SELECT_F64_S\000"
5628 /* 22604 */ "GLOBAL_GET_F64_S\000"
5629 /* 22621 */ "LOCAL_GET_F64_S\000"
5630 /* 22637 */ "I64_REINTERPRET_F64_S\000"
5631 /* 22659 */ "GLOBAL_SET_F64_S\000"
5632 /* 22676 */ "LOCAL_SET_F64_S\000"
5633 /* 22692 */ "GT_F64_S\000"
5634 /* 22701 */ "LT_F64_S\000"
5635 /* 22710 */ "SQRT_F64_S\000"
5636 /* 22721 */ "NEAREST_F64_S\000"
5637 /* 22735 */ "CONST_F64_S\000"
5638 /* 22747 */ "I32_TRUNC_U_F64_S\000"
5639 /* 22765 */ "I64_TRUNC_U_F64_S\000"
5640 /* 22783 */ "DIV_F64_S\000"
5641 /* 22793 */ "MAX_F64_S\000"
5642 /* 22803 */ "COPY_F64_S\000"
5643 /* 22814 */ "SUB_I64_S\000"
5644 /* 22824 */ "ADD_I64_S\000"
5645 /* 22834 */ "AND_I64_S\000"
5646 /* 22844 */ "LOCAL_TEE_I64_S\000"
5647 /* 22860 */ "BR_TABLE_I64_S\000"
5648 /* 22875 */ "NE_I64_S\000"
5649 /* 22884 */ "SHL_I64_S\000"
5650 /* 22894 */ "ROTL_I64_S\000"
5651 /* 22905 */ "MUL_I64_S\000"
5652 /* 22915 */ "I32_WRAP_I64_S\000"
5653 /* 22930 */ "DROP_I64_S\000"
5654 /* 22941 */ "EQ_I64_S\000"
5655 /* 22950 */ "XOR_I64_S\000"
5656 /* 22960 */ "ROTR_I64_S\000"
5657 /* 22971 */ "I64_EXTEND32_S_I64_S\000"
5658 /* 22992 */ "I64_EXTEND16_S_I64_S\000"
5659 /* 23013 */ "I64_EXTEND8_S_I64_S\000"
5660 /* 23033 */ "GE_S_I64_S\000"
5661 /* 23044 */ "LE_S_I64_S\000"
5662 /* 23055 */ "REM_S_I64_S\000"
5663 /* 23067 */ "SHR_S_I64_S\000"
5664 /* 23079 */ "GT_S_I64_S\000"
5665 /* 23090 */ "LT_S_I64_S\000"
5666 /* 23101 */ "F32_CONVERT_S_I64_S\000"
5667 /* 23121 */ "F64_CONVERT_S_I64_S\000"
5668 /* 23141 */ "DIV_S_I64_S\000"
5669 /* 23153 */ "SELECT_I64_S\000"
5670 /* 23166 */ "GLOBAL_GET_I64_S\000"
5671 /* 23183 */ "LOCAL_GET_I64_S\000"
5672 /* 23199 */ "F64_REINTERPRET_I64_S\000"
5673 /* 23221 */ "GLOBAL_SET_I64_S\000"
5674 /* 23238 */ "LOCAL_SET_I64_S\000"
5675 /* 23254 */ "POPCNT_I64_S\000"
5676 /* 23267 */ "CONST_I64_S\000"
5677 /* 23279 */ "GE_U_I64_S\000"
5678 /* 23290 */ "LE_U_I64_S\000"
5679 /* 23301 */ "REM_U_I64_S\000"
5680 /* 23313 */ "SHR_U_I64_S\000"
5681 /* 23325 */ "GT_U_I64_S\000"
5682 /* 23336 */ "LT_U_I64_S\000"
5683 /* 23347 */ "F32_CONVERT_U_I64_S\000"
5684 /* 23367 */ "F64_CONVERT_U_I64_S\000"
5685 /* 23387 */ "DIV_U_I64_S\000"
5686 /* 23399 */ "COPY_I64_S\000"
5687 /* 23410 */ "CLZ_I64_S\000"
5688 /* 23420 */ "EQZ_I64_S\000"
5689 /* 23430 */ "CTZ_I64_S\000"
5690 /* 23440 */ "ARGUMENT_v2f64_S\000"
5691 /* 23457 */ "ARGUMENT_f64_S\000"
5692 /* 23472 */ "ARGUMENT_v2i64_S\000"
5693 /* 23489 */ "ARGUMENT_i64_S\000"
5694 /* 23504 */ "CONST_V128_F32x4_S\000"
5695 /* 23523 */ "SUB_F32x4_S\000"
5696 /* 23535 */ "TRUNC_F32x4_S\000"
5697 /* 23549 */ "NMADD_F32x4_S\000"
5698 /* 23563 */ "GE_F32x4_S\000"
5699 /* 23574 */ "LE_F32x4_S\000"
5700 /* 23585 */ "REPLACE_LANE_F32x4_S\000"
5701 /* 23606 */ "EXTRACT_LANE_F32x4_S\000"
5702 /* 23627 */ "NEG_F32x4_S\000"
5703 /* 23639 */ "CEIL_F32x4_S\000"
5704 /* 23652 */ "MUL_F32x4_S\000"
5705 /* 23664 */ "SIMD_RELAXED_FMIN_F32x4_S\000"
5706 /* 23690 */ "PMIN_F32x4_S\000"
5707 /* 23703 */ "EQ_F32x4_S\000"
5708 /* 23714 */ "FLOOR_F32x4_S\000"
5709 /* 23728 */ "ABS_F32x4_S\000"
5710 /* 23740 */ "SPLAT_F32x4_S\000"
5711 /* 23754 */ "GT_F32x4_S\000"
5712 /* 23765 */ "LT_F32x4_S\000"
5713 /* 23776 */ "SQRT_F32x4_S\000"
5714 /* 23789 */ "NEAREST_F32x4_S\000"
5715 /* 23805 */ "DIV_F32x4_S\000"
5716 /* 23817 */ "SIMD_RELAXED_FMAX_F32x4_S\000"
5717 /* 23843 */ "PMAX_F32x4_S\000"
5718 /* 23856 */ "demote_zero_F32x4_S\000"
5719 /* 23876 */ "sint_to_fp_F32x4_S\000"
5720 /* 23895 */ "uint_to_fp_F32x4_S\000"
5721 /* 23914 */ "CONST_V128_I32x4_S\000"
5722 /* 23933 */ "SUB_I32x4_S\000"
5723 /* 23945 */ "ADD_I32x4_S\000"
5724 /* 23957 */ "REPLACE_LANE_I32x4_S\000"
5725 /* 23978 */ "EXTRACT_LANE_I32x4_S\000"
5726 /* 23999 */ "ALLTRUE_I32x4_S\000"
5727 /* 24015 */ "NEG_I32x4_S\000"
5728 /* 24027 */ "BITMASK_I32x4_S\000"
5729 /* 24043 */ "SHL_I32x4_S\000"
5730 /* 24055 */ "MUL_I32x4_S\000"
5731 /* 24067 */ "EQ_I32x4_S\000"
5732 /* 24078 */ "ABS_I32x4_S\000"
5733 /* 24090 */ "GE_S_I32x4_S\000"
5734 /* 24103 */ "LE_S_I32x4_S\000"
5735 /* 24116 */ "EXTMUL_HIGH_S_I32x4_S\000"
5736 /* 24138 */ "MIN_S_I32x4_S\000"
5737 /* 24152 */ "SHR_S_I32x4_S\000"
5738 /* 24166 */ "GT_S_I32x4_S\000"
5739 /* 24179 */ "LT_S_I32x4_S\000"
5740 /* 24192 */ "EXTMUL_LOW_S_I32x4_S\000"
5741 /* 24213 */ "MAX_S_I32x4_S\000"
5742 /* 24227 */ "SPLAT_I32x4_S\000"
5743 /* 24241 */ "LANESELECT_I32x4_S\000"
5744 /* 24260 */ "GE_U_I32x4_S\000"
5745 /* 24273 */ "LE_U_I32x4_S\000"
5746 /* 24286 */ "EXTMUL_HIGH_U_I32x4_S\000"
5747 /* 24308 */ "MIN_U_I32x4_S\000"
5748 /* 24322 */ "SHR_U_I32x4_S\000"
5749 /* 24336 */ "GT_U_I32x4_S\000"
5750 /* 24349 */ "LT_U_I32x4_S\000"
5751 /* 24362 */ "EXTMUL_LOW_U_I32x4_S\000"
5752 /* 24383 */ "MAX_U_I32x4_S\000"
5753 /* 24397 */ "int_wasm_relaxed_trunc_signed_I32x4_S\000"
5754 /* 24435 */ "int_wasm_relaxed_trunc_unsigned_I32x4_S\000"
5755 /* 24475 */ "int_wasm_relaxed_trunc_signed_zero_I32x4_S\000"
5756 /* 24518 */ "int_wasm_relaxed_trunc_unsigned_zero_I32x4_S\000"
5757 /* 24563 */ "extadd_pairwise_s_I32x4_S\000"
5758 /* 24589 */ "extend_high_s_I32x4_S\000"
5759 /* 24611 */ "trunc_sat_zero_s_I32x4_S\000"
5760 /* 24636 */ "extend_low_s_I32x4_S\000"
5761 /* 24657 */ "fp_to_sint_I32x4_S\000"
5762 /* 24676 */ "fp_to_uint_I32x4_S\000"
5763 /* 24695 */ "extadd_pairwise_u_I32x4_S\000"
5764 /* 24721 */ "extend_high_u_I32x4_S\000"
5765 /* 24743 */ "trunc_sat_zero_u_I32x4_S\000"
5766 /* 24768 */ "extend_low_u_I32x4_S\000"
5767 /* 24789 */ "ARGUMENT_v8f16_S\000"
5768 /* 24806 */ "ARGUMENT_v8i16_S\000"
5769 /* 24823 */ "CONST_V128_I8x16_S\000"
5770 /* 24842 */ "SUB_I8x16_S\000"
5771 /* 24854 */ "ADD_I8x16_S\000"
5772 /* 24866 */ "REPLACE_LANE_I8x16_S\000"
5773 /* 24887 */ "ALLTRUE_I8x16_S\000"
5774 /* 24903 */ "NEG_I8x16_S\000"
5775 /* 24915 */ "BITMASK_I8x16_S\000"
5776 /* 24931 */ "SHL_I8x16_S\000"
5777 /* 24943 */ "EQ_I8x16_S\000"
5778 /* 24954 */ "ABS_I8x16_S\000"
5779 /* 24966 */ "GE_S_I8x16_S\000"
5780 /* 24979 */ "LE_S_I8x16_S\000"
5781 /* 24992 */ "MIN_S_I8x16_S\000"
5782 /* 25006 */ "SHR_S_I8x16_S\000"
5783 /* 25020 */ "SUB_SAT_S_I8x16_S\000"
5784 /* 25038 */ "ADD_SAT_S_I8x16_S\000"
5785 /* 25056 */ "GT_S_I8x16_S\000"
5786 /* 25069 */ "LT_S_I8x16_S\000"
5787 /* 25082 */ "NARROW_S_I8x16_S\000"
5788 /* 25099 */ "MAX_S_I8x16_S\000"
5789 /* 25113 */ "SPLAT_I8x16_S\000"
5790 /* 25127 */ "LANESELECT_I8x16_S\000"
5791 /* 25146 */ "POPCNT_I8x16_S\000"
5792 /* 25161 */ "GE_U_I8x16_S\000"
5793 /* 25174 */ "LE_U_I8x16_S\000"
5794 /* 25187 */ "MIN_U_I8x16_S\000"
5795 /* 25201 */ "AVGR_U_I8x16_S\000"
5796 /* 25216 */ "SHR_U_I8x16_S\000"
5797 /* 25230 */ "SUB_SAT_U_I8x16_S\000"
5798 /* 25248 */ "ADD_SAT_U_I8x16_S\000"
5799 /* 25266 */ "GT_U_I8x16_S\000"
5800 /* 25279 */ "LT_U_I8x16_S\000"
5801 /* 25292 */ "NARROW_U_I8x16_S\000"
5802 /* 25309 */ "MAX_U_I8x16_S\000"
5803 /* 25323 */ "I64_SUB128_S\000"
5804 /* 25336 */ "I64_ADD128_S\000"
5805 /* 25349 */ "LOCAL_TEE_V128_S\000"
5806 /* 25366 */ "DROP_V128_S\000"
5807 /* 25378 */ "SELECT_V128_S\000"
5808 /* 25392 */ "GLOBAL_GET_V128_S\000"
5809 /* 25410 */ "LOCAL_GET_V128_S\000"
5810 /* 25427 */ "GLOBAL_SET_V128_S\000"
5811 /* 25445 */ "LOCAL_SET_V128_S\000"
5812 /* 25462 */ "COPY_V128_S\000"
5813 /* 25474 */ "ARGUMENT_v16i8_S\000"
5814 /* 25491 */ "SUB_F16x8_S\000"
5815 /* 25503 */ "TRUNC_F16x8_S\000"
5816 /* 25517 */ "NMADD_F16x8_S\000"
5817 /* 25531 */ "GE_F16x8_S\000"
5818 /* 25542 */ "LE_F16x8_S\000"
5819 /* 25553 */ "REPLACE_LANE_F16x8_S\000"
5820 /* 25574 */ "EXTRACT_LANE_F16x8_S\000"
5821 /* 25595 */ "NEG_F16x8_S\000"
5822 /* 25607 */ "CEIL_F16x8_S\000"
5823 /* 25620 */ "MUL_F16x8_S\000"
5824 /* 25632 */ "PMIN_F16x8_S\000"
5825 /* 25645 */ "EQ_F16x8_S\000"
5826 /* 25656 */ "FLOOR_F16x8_S\000"
5827 /* 25670 */ "ABS_F16x8_S\000"
5828 /* 25682 */ "SPLAT_F16x8_S\000"
5829 /* 25696 */ "GT_F16x8_S\000"
5830 /* 25707 */ "LT_F16x8_S\000"
5831 /* 25718 */ "SQRT_F16x8_S\000"
5832 /* 25731 */ "NEAREST_F16x8_S\000"
5833 /* 25747 */ "DIV_F16x8_S\000"
5834 /* 25759 */ "PMAX_F16x8_S\000"
5835 /* 25772 */ "sint_to_fp_F16x8_S\000"
5836 /* 25791 */ "uint_to_fp_F16x8_S\000"
5837 /* 25810 */ "CONST_V128_I16x8_S\000"
5838 /* 25829 */ "SUB_I16x8_S\000"
5839 /* 25841 */ "ADD_I16x8_S\000"
5840 /* 25853 */ "REPLACE_LANE_I16x8_S\000"
5841 /* 25874 */ "ALLTRUE_I16x8_S\000"
5842 /* 25890 */ "NEG_I16x8_S\000"
5843 /* 25902 */ "BITMASK_I16x8_S\000"
5844 /* 25918 */ "SHL_I16x8_S\000"
5845 /* 25930 */ "MUL_I16x8_S\000"
5846 /* 25942 */ "EQ_I16x8_S\000"
5847 /* 25953 */ "ABS_I16x8_S\000"
5848 /* 25965 */ "GE_S_I16x8_S\000"
5849 /* 25978 */ "LE_S_I16x8_S\000"
5850 /* 25991 */ "EXTMUL_HIGH_S_I16x8_S\000"
5851 /* 26013 */ "MIN_S_I16x8_S\000"
5852 /* 26027 */ "SHR_S_I16x8_S\000"
5853 /* 26041 */ "RELAXED_Q15MULR_S_I16x8_S\000"
5854 /* 26067 */ "SUB_SAT_S_I16x8_S\000"
5855 /* 26085 */ "ADD_SAT_S_I16x8_S\000"
5856 /* 26103 */ "Q15MULR_SAT_S_I16x8_S\000"
5857 /* 26125 */ "GT_S_I16x8_S\000"
5858 /* 26138 */ "LT_S_I16x8_S\000"
5859 /* 26151 */ "EXTMUL_LOW_S_I16x8_S\000"
5860 /* 26172 */ "NARROW_S_I16x8_S\000"
5861 /* 26189 */ "MAX_S_I16x8_S\000"
5862 /* 26203 */ "SPLAT_I16x8_S\000"
5863 /* 26217 */ "LANESELECT_I16x8_S\000"
5864 /* 26236 */ "GE_U_I16x8_S\000"
5865 /* 26249 */ "LE_U_I16x8_S\000"
5866 /* 26262 */ "EXTMUL_HIGH_U_I16x8_S\000"
5867 /* 26284 */ "MIN_U_I16x8_S\000"
5868 /* 26298 */ "AVGR_U_I16x8_S\000"
5869 /* 26313 */ "SHR_U_I16x8_S\000"
5870 /* 26327 */ "SUB_SAT_U_I16x8_S\000"
5871 /* 26345 */ "ADD_SAT_U_I16x8_S\000"
5872 /* 26363 */ "GT_U_I16x8_S\000"
5873 /* 26376 */ "LT_U_I16x8_S\000"
5874 /* 26389 */ "EXTMUL_LOW_U_I16x8_S\000"
5875 /* 26410 */ "NARROW_U_I16x8_S\000"
5876 /* 26427 */ "MAX_U_I16x8_S\000"
5877 /* 26441 */ "extadd_pairwise_s_I16x8_S\000"
5878 /* 26467 */ "extend_high_s_I16x8_S\000"
5879 /* 26489 */ "extend_low_s_I16x8_S\000"
5880 /* 26510 */ "fp_to_sint_I16x8_S\000"
5881 /* 26529 */ "fp_to_uint_I16x8_S\000"
5882 /* 26548 */ "extadd_pairwise_u_I16x8_S\000"
5883 /* 26574 */ "extend_high_u_I16x8_S\000"
5884 /* 26596 */ "extend_low_u_I16x8_S\000"
5885 /* 26617 */ "REF_FUNC_S\000"
5886 /* 26628 */ "RELAXED_DOT_ADD_S\000"
5887 /* 26646 */ "AND_S\000"
5888 /* 26652 */ "END_S\000"
5889 /* 26658 */ "ATOMIC_FENCE_S\000"
5890 /* 26673 */ "COMPILER_FENCE_S\000"
5891 /* 26690 */ "I64_MUL_WIDE_S\000"
5892 /* 26705 */ "DEBUG_UNREACHABLE_S\000"
5893 /* 26725 */ "END_TRY_TABLE_S\000"
5894 /* 26741 */ "SHUFFLE_S\000"
5895 /* 26751 */ "RELAXED_SWIZZLE_S\000"
5896 /* 26769 */ "ELSE_S\000"
5897 /* 26776 */ "DELEGATE_S\000"
5898 /* 26787 */ "ANYTRUE_S\000"
5899 /* 26797 */ "TABLE_SIZE_S\000"
5900 /* 26810 */ "LOCAL_TEE_FUNCREF_S\000"
5901 /* 26830 */ "TABLE_FILL_FUNCREF_S\000"
5902 /* 26851 */ "REF_NULL_FUNCREF_S\000"
5903 /* 26870 */ "REF_IS_NULL_FUNCREF_S\000"
5904 /* 26892 */ "DROP_FUNCREF_S\000"
5905 /* 26907 */ "SELECT_FUNCREF_S\000"
5906 /* 26924 */ "TABLE_GET_FUNCREF_S\000"
5907 /* 26944 */ "GLOBAL_GET_FUNCREF_S\000"
5908 /* 26965 */ "LOCAL_GET_FUNCREF_S\000"
5909 /* 26985 */ "TABLE_SET_FUNCREF_S\000"
5910 /* 27005 */ "GLOBAL_SET_FUNCREF_S\000"
5911 /* 27026 */ "LOCAL_SET_FUNCREF_S\000"
5912 /* 27046 */ "REF_TEST_FUNCREF_S\000"
5913 /* 27065 */ "TABLE_GROW_FUNCREF_S\000"
5914 /* 27086 */ "COPY_FUNCREF_S\000"
5915 /* 27101 */ "LOCAL_TEE_EXTERNREF_S\000"
5916 /* 27123 */ "TABLE_FILL_EXTERNREF_S\000"
5917 /* 27146 */ "REF_NULL_EXTERNREF_S\000"
5918 /* 27167 */ "REF_IS_NULL_EXTERNREF_S\000"
5919 /* 27191 */ "DROP_EXTERNREF_S\000"
5920 /* 27208 */ "SELECT_EXTERNREF_S\000"
5921 /* 27227 */ "TABLE_GET_EXTERNREF_S\000"
5922 /* 27249 */ "GLOBAL_GET_EXTERNREF_S\000"
5923 /* 27272 */ "LOCAL_GET_EXTERNREF_S\000"
5924 /* 27294 */ "TABLE_SET_EXTERNREF_S\000"
5925 /* 27316 */ "GLOBAL_SET_EXTERNREF_S\000"
5926 /* 27339 */ "LOCAL_SET_EXTERNREF_S\000"
5927 /* 27361 */ "TABLE_GROW_EXTERNREF_S\000"
5928 /* 27384 */ "COPY_EXTERNREF_S\000"
5929 /* 27401 */ "LOCAL_TEE_EXNREF_S\000"
5930 /* 27420 */ "TABLE_FILL_EXNREF_S\000"
5931 /* 27440 */ "REF_NULL_EXNREF_S\000"
5932 /* 27458 */ "REF_IS_NULL_EXNREF_S\000"
5933 /* 27479 */ "DROP_EXNREF_S\000"
5934 /* 27493 */ "SELECT_EXNREF_S\000"
5935 /* 27509 */ "TABLE_GET_EXNREF_S\000"
5936 /* 27528 */ "GLOBAL_GET_EXNREF_S\000"
5937 /* 27548 */ "LOCAL_GET_EXNREF_S\000"
5938 /* 27567 */ "TABLE_SET_EXNREF_S\000"
5939 /* 27586 */ "GLOBAL_SET_EXNREF_S\000"
5940 /* 27606 */ "LOCAL_SET_EXNREF_S\000"
5941 /* 27625 */ "TABLE_GROW_EXNREF_S\000"
5942 /* 27645 */ "COPY_EXNREF_S\000"
5943 /* 27659 */ "CATCH_REF_S\000"
5944 /* 27671 */ "CATCH_ALL_REF_S\000"
5945 /* 27687 */ "THROW_REF_S\000"
5946 /* 27699 */ "END_IF_S\000"
5947 /* 27708 */ "BR_IF_S\000"
5948 /* 27716 */ "CATCH_S\000"
5949 /* 27724 */ "END_BLOCK_S\000"
5950 /* 27736 */ "RET_CALL_S\000"
5951 /* 27747 */ "CATCH_ALL_S\000"
5952 /* 27759 */ "END_FUNCTION_S\000"
5953 /* 27774 */ "FALLTHROUGH_RETURN_S\000"
5954 /* 27795 */ "ADJCALLSTACKDOWN_S\000"
5955 /* 27814 */ "NOP_S\000"
5956 /* 27820 */ "END_LOOP_S\000"
5957 /* 27831 */ "DATA_DROP_S\000"
5958 /* 27843 */ "ADJCALLSTACKUP_S\000"
5959 /* 27860 */ "BR_S\000"
5960 /* 27865 */ "XOR_S\000"
5961 /* 27871 */ "CALL_PARAMS_S\000"
5962 /* 27885 */ "BR_UNLESS_S\000"
5963 /* 27897 */ "RET_CALL_RESULTS_S\000"
5964 /* 27916 */ "I64_MUL_WIDE_S_S\000"
5965 /* 27933 */ "RELAXED_DOT_BFLOAT_S\000"
5966 /* 27954 */ "G_TRUNC_SSAT_S\000"
5967 /* 27969 */ "BITSELECT_S\000"
5968 /* 27981 */ "RET_CALL_INDIRECT_S\000"
5969 /* 28001 */ "CATCHRET_S\000"
5970 /* 28012 */ "CLEANUPRET_S\000"
5971 /* 28025 */ "RELAXED_DOT_S\000"
5972 /* 28039 */ "ANDNOT_S\000"
5973 /* 28048 */ "I64_MUL_WIDE_U_S\000"
5974 /* 28065 */ "RETHROW_S\000"
5975 /* 28075 */ "CATCH_LEGACY_S\000"
5976 /* 28090 */ "CATCH_ALL_LEGACY_S\000"
5977 /* 28109 */ "TABLE_COPY_S\000"
5978 /* 28122 */ "END_TRY_S\000"
5979 /* 28132 */ "ARGUMENT_funcref_S\000"
5980 /* 28151 */ "ARGUMENT_externref_S\000"
5981 /* 28172 */ "ARGUMENT_exnref_S\000"
5982 /* 28190 */ "EXTRACT_LANE_I8x16_s_S\000"
5983 /* 28213 */ "EXTRACT_LANE_I16x8_s_S\000"
5984 /* 28236 */ "EXTRACT_LANE_I8x16_u_S\000"
5985 /* 28259 */ "EXTRACT_LANE_I16x8_u_S\000"
5986 /* 28282 */ "RELAXED_DOT_BFLOAT\000"
5987 /* 28301 */ "G_SSUBSAT\000"
5988 /* 28311 */ "G_USUBSAT\000"
5989 /* 28321 */ "G_SADDSAT\000"
5990 /* 28331 */ "G_UADDSAT\000"
5991 /* 28341 */ "G_SSHLSAT\000"
5992 /* 28351 */ "G_USHLSAT\000"
5993 /* 28361 */ "G_SMULFIXSAT\000"
5994 /* 28374 */ "G_UMULFIXSAT\000"
5995 /* 28387 */ "G_SDIVFIXSAT\000"
5996 /* 28400 */ "G_UDIVFIXSAT\000"
5997 /* 28413 */ "G_ATOMICRMW_USUB_SAT\000"
5998 /* 28434 */ "G_FPTOSI_SAT\000"
5999 /* 28447 */ "G_FPTOUI_SAT\000"
6000 /* 28460 */ "G_EXTRACT\000"
6001 /* 28470 */ "BITSELECT\000"
6002 /* 28480 */ "G_SELECT\000"
6003 /* 28489 */ "G_BRINDIRECT\000"
6004 /* 28502 */ "RET_CALL_INDIRECT\000"
6005 /* 28520 */ "CATCHRET\000"
6006 /* 28529 */ "CLEANUPRET\000"
6007 /* 28540 */ "PATCHABLE_RET\000"
6008 /* 28554 */ "G_MEMSET\000"
6009 /* 28563 */ "PATCHABLE_FUNCTION_EXIT\000"
6010 /* 28587 */ "G_BRJT\000"
6011 /* 28594 */ "G_EXTRACT_VECTOR_ELT\000"
6012 /* 28615 */ "G_INSERT_VECTOR_ELT\000"
6013 /* 28635 */ "G_FCONSTANT\000"
6014 /* 28647 */ "G_CONSTANT\000"
6015 /* 28658 */ "G_INTRINSIC_CONVERGENT\000"
6016 /* 28681 */ "STATEPOINT\000"
6017 /* 28692 */ "PATCHPOINT\000"
6018 /* 28703 */ "G_PTRTOINT\000"
6019 /* 28714 */ "G_FRINT\000"
6020 /* 28722 */ "G_INTRINSIC_LLRINT\000"
6021 /* 28741 */ "G_INTRINSIC_LRINT\000"
6022 /* 28759 */ "G_FNEARBYINT\000"
6023 /* 28772 */ "RELAXED_DOT\000"
6024 /* 28784 */ "ANDNOT\000"
6025 /* 28791 */ "G_VASTART\000"
6026 /* 28801 */ "LIFETIME_START\000"
6027 /* 28816 */ "G_INVOKE_REGION_START\000"
6028 /* 28838 */ "G_INSERT\000"
6029 /* 28847 */ "G_FSQRT\000"
6030 /* 28855 */ "G_STRICT_FSQRT\000"
6031 /* 28870 */ "G_BITCAST\000"
6032 /* 28880 */ "G_ADDRSPACE_CAST\000"
6033 /* 28897 */ "DBG_VALUE_LIST\000"
6034 /* 28912 */ "G_FPEXT\000"
6035 /* 28920 */ "G_SEXT\000"
6036 /* 28927 */ "G_ASSERT_SEXT\000"
6037 /* 28941 */ "G_ANYEXT\000"
6038 /* 28950 */ "G_ZEXT\000"
6039 /* 28957 */ "G_ASSERT_ZEXT\000"
6040 /* 28971 */ "G_ABDU\000"
6041 /* 28978 */ "I64_MUL_WIDE_U\000"
6042 /* 28993 */ "G_TRUNC_SSAT_U\000"
6043 /* 29008 */ "G_TRUNC_USAT_U\000"
6044 /* 29023 */ "G_FDIV\000"
6045 /* 29030 */ "G_STRICT_FDIV\000"
6046 /* 29044 */ "G_SDIV\000"
6047 /* 29051 */ "G_UDIV\000"
6048 /* 29058 */ "G_GET_FPENV\000"
6049 /* 29070 */ "G_RESET_FPENV\000"
6050 /* 29084 */ "G_SET_FPENV\000"
6051 /* 29096 */ "G_FPOW\000"
6052 /* 29103 */ "RETHROW\000"
6053 /* 29111 */ "G_VECREDUCE_FMAX\000"
6054 /* 29128 */ "G_ATOMICRMW_FMAX\000"
6055 /* 29145 */ "G_VECREDUCE_SMAX\000"
6056 /* 29162 */ "G_SMAX\000"
6057 /* 29169 */ "G_VECREDUCE_UMAX\000"
6058 /* 29186 */ "G_UMAX\000"
6059 /* 29193 */ "G_ATOMICRMW_UMAX\000"
6060 /* 29210 */ "G_ATOMICRMW_MAX\000"
6061 /* 29226 */ "G_FRAME_INDEX\000"
6062 /* 29240 */ "G_SBFX\000"
6063 /* 29247 */ "G_UBFX\000"
6064 /* 29254 */ "G_SMULFIX\000"
6065 /* 29264 */ "G_UMULFIX\000"
6066 /* 29274 */ "G_SDIVFIX\000"
6067 /* 29284 */ "G_UDIVFIX\000"
6068 /* 29294 */ "CATCH_LEGACY\000"
6069 /* 29307 */ "CATCH_ALL_LEGACY\000"
6070 /* 29324 */ "G_MEMCPY\000"
6071 /* 29333 */ "TABLE_COPY\000"
6072 /* 29344 */ "CONVERGENCECTRL_ENTRY\000"
6073 /* 29366 */ "END_TRY\000"
6074 /* 29374 */ "G_CTLZ\000"
6075 /* 29381 */ "G_CTTZ\000"
6076 /* 29388 */ "ARGUMENT_funcref\000"
6077 /* 29405 */ "ARGUMENT_externref\000"
6078 /* 29424 */ "ARGUMENT_exnref\000"
6079 /* 29440 */ "EXTRACT_LANE_I8x16_s\000"
6080 /* 29461 */ "EXTRACT_LANE_I16x8_s\000"
6081 /* 29482 */ "EXTRACT_LANE_I8x16_u\000"
6082 /* 29503 */ "EXTRACT_LANE_I16x8_u\000"
6083};
6084#ifdef __GNUC__
6085#pragma GCC diagnostic pop
6086#endif
6087
6088extern const unsigned WebAssemblyInstrNameIndices[] = {
6089 12794U, 13229U, 14073U, 13648U, 12877U, 12858U, 12886U, 13065U,
6090 12581U, 12596U, 11737U, 11724U, 12623U, 14612U, 11545U, 28897U,
6091 12537U, 12790U, 12867U, 11245U, 29339U, 12834U, 11399U, 28801U,
6092 11044U, 11168U, 11218U, 13778U, 13043U, 28692U, 11151U, 14008U,
6093 12716U, 28681U, 11457U, 13981U, 13968U, 14134U, 28540U, 28563U,
6094 12966U, 13022U, 12995U, 12903U, 11527U, 14099U, 13732U, 11446U,
6095 29344U, 14252U, 13929U, 11593U, 28927U, 28957U, 13478U, 10941U,
6096 10643U, 13168U, 29044U, 29051U, 13195U, 13202U, 13209U, 13219U,
6097 11022U, 14461U, 14424U, 14512U, 28971U, 14296U, 12955U, 14284U,
6098 12944U, 11735U, 12792U, 29226U, 11555U, 11570U, 13070U, 28460U,
6099 14519U, 28838U, 14536U, 14347U, 10722U, 14595U, 28703U, 14488U,
6100 28870U, 11644U, 14110U, 11125U, 10696U, 11107U, 28741U, 28722U,
6101 13456U, 14159U, 14178U, 10842U, 10786U, 10816U, 10827U, 10767U,
6102 10797U, 11501U, 11485U, 14642U, 12637U, 12654U, 10973U, 10649U,
6103 11028U, 10989U, 14466U, 14430U, 29210U, 13604U, 29193U, 13587U,
6104 10908U, 10626U, 29128U, 13522U, 13324U, 13271U, 13397U, 13359U,
6105 13840U, 13818U, 11066U, 28413U, 11210U, 12739U, 11057U, 28489U,
6106 28816U, 10665U, 14700U, 28658U, 14727U, 28941U, 10714U, 27954U,
6107 28993U, 29008U, 28647U, 28635U, 28791U, 12708U, 28920U, 12610U,
6108 28950U, 12930U, 14245U, 14231U, 12923U, 14238U, 14481U, 13086U,
6109 13895U, 13888U, 13902U, 13909U, 28480U, 13724U, 11266U, 13708U,
6110 11189U, 13716U, 11258U, 13700U, 11181U, 13762U, 13754U, 12758U,
6111 12750U, 28331U, 28321U, 28311U, 28301U, 28351U, 28341U, 29254U,
6112 29264U, 28361U, 28374U, 29274U, 29284U, 28387U, 28400U, 10866U,
6113 10605U, 13110U, 10586U, 10760U, 29023U, 13174U, 11680U, 29096U,
6114 12816U, 14052U, 3559U, 9U, 12701U, 3542U, 0U, 14027U,
6115 14059U, 12574U, 28912U, 10686U, 12798U, 12807U, 13870U, 13879U,
6116 28434U, 28447U, 14499U, 13493U, 14629U, 11653U, 13421U, 13431U,
6117 11315U, 11330U, 13260U, 13313U, 13345U, 13383U, 29058U, 29084U,
6118 29070U, 11274U, 11302U, 11287U, 12671U, 12686U, 10947U, 12848U,
6119 13556U, 29162U, 13580U, 29186U, 14506U, 11098U, 11088U, 14068U,
6120 28587U, 11345U, 14328U, 14308U, 28615U, 28594U, 14362U, 14393U,
6121 14379U, 14682U, 29381U, 11706U, 29374U, 11688U, 14551U, 13950U,
6122 13862U, 11514U, 12936U, 14578U, 13628U, 14585U, 13449U, 14570U,
6123 13620U, 13441U, 3550U, 12782U, 12774U, 12766U, 28847U, 14275U,
6124 28714U, 28759U, 28880U, 14086U, 11372U, 10743U, 11622U, 11470U,
6125 10894U, 10612U, 13138U, 29030U, 13181U, 10592U, 28855U, 14036U,
6126 14198U, 14214U, 29324U, 11430U, 11634U, 28554U, 13770U, 13811U,
6127 13787U, 13799U, 10873U, 13117U, 10849U, 13093U, 29111U, 13505U,
6128 13292U, 13239U, 10925U, 13152U, 11006U, 14446U, 14408U, 29145U,
6129 13539U, 29169U, 13563U, 29240U, 29247U, 14558U, 27871U, 14769U,
6130 27901U, 28520U, 28001U, 28529U, 28012U, 11230U, 26673U, 14765U,
6131 27897U, 9755U, 25670U, 2641U, 17657U, 8049U, 23728U, 6956U,
6132 22457U, 3761U, 18930U, 9998U, 25953U, 8353U, 24078U, 4071U,
6133 19286U, 9137U, 24954U, 9626U, 25519U, 2510U, 17498U, 7896U,
6134 23551U, 6826U, 22299U, 3608U, 18753U, 9902U, 25841U, 2960U,
6135 18024U, 8238U, 23945U, 7275U, 22824U, 3956U, 19153U, 9051U,
6136 24854U, 10114U, 26085U, 9209U, 25038U, 10342U, 26345U, 9391U,
6137 25248U, 13683U, 27795U, 13993U, 27843U, 9931U, 25874U, 8286U,
6138 23999U, 4004U, 19207U, 9080U, 24887U, 11002U, 28784U, 28039U,
6139 2968U, 18034U, 7283U, 22834U, 26646U, 11614U, 26787U, 29424U,
6140 28172U, 29405U, 28151U, 3501U, 18659U, 7814U, 23457U, 29388U,
6141 28132U, 3529U, 18691U, 7842U, 23489U, 9587U, 25474U, 7799U,
6142 23440U, 7827U, 23472U, 3486U, 18642U, 3514U, 18674U, 8994U,
6143 24789U, 9009U, 24806U, 11197U, 26658U, 743U, 15569U, 5059U,
6144 20370U, 1865U, 16785U, 6181U, 21586U, 1841U, 16759U, 6157U,
6145 21560U, 767U, 15595U, 5083U, 20396U, 1889U, 16811U, 6205U,
6146 21612U, 201U, 14983U, 4517U, 19784U, 1116U, 15976U, 5432U,
6147 20777U, 221U, 15005U, 4537U, 19806U, 1163U, 16027U, 5479U,
6148 20828U, 297U, 15087U, 4613U, 19888U, 1266U, 16138U, 5582U,
6149 20939U, 394U, 15192U, 4710U, 19993U, 1394U, 16276U, 5710U,
6150 21077U, 637U, 15453U, 4953U, 20254U, 1718U, 16624U, 6034U,
6151 21425U, 125U, 14901U, 4441U, 19702U, 1040U, 15894U, 5356U,
6152 20695U, 482U, 15286U, 4798U, 20087U, 1510U, 16400U, 5826U,
6153 21201U, 561U, 15371U, 4877U, 20172U, 1616U, 16514U, 5932U,
6154 21315U, 1136U, 15998U, 5452U, 20799U, 1239U, 16109U, 5555U,
6155 20910U, 1363U, 16243U, 5679U, 21044U, 1692U, 16596U, 6008U,
6156 21397U, 1013U, 15865U, 5329U, 20666U, 1482U, 16370U, 5798U,
6157 21171U, 1589U, 16485U, 5905U, 21286U, 248U, 15034U, 4564U,
6158 19835U, 1190U, 16056U, 5506U, 20857U, 324U, 15116U, 4640U,
6159 19917U, 1293U, 16167U, 5609U, 20968U, 425U, 15225U, 4741U,
6160 20026U, 1425U, 16309U, 5741U, 21110U, 663U, 15481U, 4979U,
6161 20282U, 1744U, 16652U, 6060U, 21453U, 152U, 14930U, 4468U,
6162 19731U, 1067U, 15923U, 5383U, 20724U, 510U, 15316U, 4826U,
6163 20117U, 1538U, 16430U, 5854U, 21231U, 588U, 15400U, 4904U,
6164 20201U, 1643U, 16543U, 5959U, 21344U, 274U, 15062U, 4590U,
6165 19863U, 1216U, 16084U, 5532U, 20885U, 350U, 15144U, 4666U,
6166 19945U, 1319U, 16195U, 5635U, 20996U, 455U, 15257U, 4771U,
6167 20058U, 1455U, 16341U, 5771U, 21142U, 688U, 15508U, 5004U,
6168 20309U, 1769U, 16679U, 6085U, 21480U, 178U, 14958U, 4494U,
6169 19759U, 1093U, 15951U, 5409U, 20752U, 537U, 15345U, 4853U,
6170 20146U, 1565U, 16459U, 5881U, 21260U, 614U, 15428U, 4930U,
6171 20229U, 1669U, 16571U, 5985U, 21372U, 80U, 14852U, 4396U,
6172 19653U, 968U, 15816U, 5284U, 20617U, 945U, 15791U, 5261U,
6173 20592U, 103U, 14877U, 4419U, 19678U, 991U, 15841U, 5307U,
6174 20642U, 373U, 15169U, 4689U, 19970U, 1342U, 16220U, 5658U,
6175 21021U, 10301U, 26298U, 9350U, 25201U, 9955U, 25902U, 8310U,
6176 24027U, 4028U, 19235U, 9104U, 24915U, 28470U, 27969U, 12828U,
6177 27728U, 14070U, 12568U, 27708U, 27860U, 2990U, 18060U, 7305U,
6178 22860U, 14672U, 27885U, 12981U, 28506U, 27985U, 27740U, 12733U,
6179 13055U, 29307U, 28090U, 12523U, 27671U, 27747U, 29294U, 28075U,
6180 12513U, 27659U, 27716U, 9702U, 25607U, 2577U, 17579U, 7972U,
6181 23639U, 6892U, 22379U, 3684U, 18841U, 3462U, 18612U, 7775U,
6182 23410U, 2885U, 17935U, 7200U, 22735U, 3324U, 18450U, 7654U,
6183 23267U, 7855U, 23504U, 3567U, 18706U, 9875U, 25810U, 8211U,
6184 23914U, 3929U, 19122U, 9024U, 24823U, 2594U, 17600U, 6909U,
6185 22400U, 12501U, 27645U, 12268U, 27384U, 2943U, 18003U, 7258U,
6186 22803U, 11998U, 27086U, 3453U, 18601U, 7766U, 23399U, 9577U,
6187 25462U, 3478U, 18632U, 7791U, 23430U, 13958U, 27831U, 11354U,
6188 26705U, 11536U, 26776U, 9820U, 25747U, 2927U, 17983U, 8114U,
6189 23805U, 7242U, 22783U, 3826U, 19007U, 3214U, 18324U, 7544U,
6190 23141U, 3443U, 18589U, 7756U, 23387U, 28780U, 28033U, 12353U,
6191 27479U, 12093U, 27191U, 2615U, 17625U, 6930U, 22425U, 11824U,
6192 26892U, 3035U, 18115U, 7363U, 22930U, 9493U, 25366U, 11509U,
6193 26769U, 11053U, 12824U, 27724U, 13635U, 27759U, 12561U, 27699U,
6194 13920U, 27820U, 26652U, 29366U, 28122U, 11385U, 26725U, 3470U,
6195 18622U, 7783U, 23420U, 9734U, 25645U, 2624U, 17636U, 8028U,
6196 23703U, 6939U, 22436U, 3740U, 18905U, 9989U, 25942U, 3044U,
6197 18126U, 8344U, 24067U, 7372U, 22941U, 4062U, 19275U, 9128U,
6198 24943U, 10030U, 25991U, 8385U, 24116U, 4103U, 19324U, 10269U,
6199 26262U, 8533U, 24286U, 4205U, 19440U, 10172U, 26151U, 8451U,
6200 24192U, 4157U, 19386U, 10380U, 26389U, 8599U, 24362U, 4237U,
6201 19476U, 9673U, 25574U, 7943U, 23606U, 3655U, 18808U, 29461U,
6202 28213U, 29503U, 28259U, 8267U, 23978U, 3985U, 19186U, 29440U,
6203 28190U, 29482U, 28236U, 3178U, 18284U, 7508U, 23101U, 3407U,
6204 18549U, 7720U, 23347U, 6869U, 22352U, 3264U, 18382U, 3196U,
6205 18304U, 7526U, 23121U, 3425U, 18569U, 7738U, 23367U, 2553U,
6206 17551U, 7594U, 23199U, 13664U, 27774U, 9743U, 25656U, 2631U,
6207 17645U, 8037U, 23714U, 6946U, 22445U, 3749U, 18916U, 2416U,
6208 17392U, 6732U, 22193U, 2454U, 17434U, 6770U, 22235U, 2435U,
6209 17413U, 6751U, 22214U, 2473U, 17455U, 6789U, 22256U, 9636U,
6210 25531U, 2532U, 17524U, 7906U, 23563U, 6848U, 22325U, 3618U,
6211 18765U, 10008U, 25965U, 3122U, 18216U, 8363U, 24090U, 7452U,
6212 23033U, 4081U, 19298U, 9147U, 24966U, 10247U, 26236U, 3351U,
6213 18481U, 8511U, 24260U, 7664U, 23279U, 9316U, 25161U, 12396U,
6214 27528U, 12145U, 27249U, 2772U, 17804U, 7087U, 22604U, 11870U,
6215 26944U, 3235U, 18349U, 7565U, 23166U, 9515U, 25392U, 12448U,
6216 27586U, 12206U, 27316U, 2821U, 17859U, 7136U, 22659U, 11925U,
6217 27005U, 3284U, 18404U, 7614U, 23221U, 9546U, 25427U, 9777U,
6218 25696U, 2850U, 17892U, 8071U, 23754U, 7165U, 22692U, 3783U,
6219 18956U, 10150U, 26125U, 3160U, 18262U, 8429U, 24166U, 7490U,
6220 23079U, 4135U, 19360U, 9225U, 25056U, 10358U, 26363U, 3389U,
6221 18527U, 8577U, 24336U, 7702U, 23325U, 9407U, 25266U, 3068U,
6222 18156U, 3087U, 18177U, 2801U, 17837U, 2649U, 17667U, 6964U,
6223 22467U, 2681U, 17703U, 6996U, 22503U, 2895U, 17947U, 7210U,
6224 22747U, 2721U, 17747U, 7036U, 22547U, 7350U, 22915U, 9467U,
6225 25336U, 7415U, 22992U, 7396U, 22971U, 7434U, 23013U, 3105U,
6226 18197U, 3334U, 18462U, 26690U, 27916U, 28978U, 28048U, 7116U,
6227 22637U, 9456U, 25323U, 2665U, 17685U, 6980U, 22485U, 2701U,
6228 17725U, 7016U, 22525U, 2911U, 17965U, 7226U, 22765U, 2741U,
6229 17769U, 7056U, 22569U, 12565U, 27703U, 10230U, 26217U, 8494U,
6230 24241U, 4188U, 19421U, 9286U, 25127U, 9645U, 25542U, 2539U,
6231 17533U, 7915U, 23574U, 6855U, 22334U, 3627U, 18776U, 10019U,
6232 25978U, 3131U, 18227U, 8374U, 24103U, 7461U, 23044U, 4092U,
6233 19311U, 9158U, 24979U, 10258U, 26249U, 3360U, 18492U, 8522U,
6234 24273U, 7673U, 23290U, 9327U, 25174U, 2273U, 17233U, 6589U,
6235 22034U, 710U, 15532U, 5026U, 20333U, 1808U, 16722U, 6124U,
6236 21523U, 750U, 15576U, 5066U, 20377U, 1872U, 16792U, 6188U,
6237 21593U, 2239U, 17195U, 6555U, 21996U, 1791U, 16703U, 6107U,
6238 21504U, 1848U, 16766U, 6164U, 21567U, 2256U, 17214U, 6572U,
6239 22015U, 2290U, 17252U, 6606U, 22053U, 727U, 15551U, 5043U,
6240 20352U, 1825U, 16741U, 6141U, 21542U, 774U, 15602U, 5090U,
6241 20403U, 1896U, 16818U, 6212U, 21619U, 2144U, 17092U, 6460U,
6242 21893U, 1992U, 16924U, 6308U, 21725U, 870U, 15708U, 5186U,
6243 20509U, 2168U, 17118U, 6484U, 21919U, 2016U, 16950U, 6332U,
6244 21751U, 894U, 15734U, 5210U, 20535U, 18U, 14782U, 4334U,
6245 19583U, 53U, 14821U, 4369U, 19622U, 918U, 15760U, 5234U,
6246 20561U, 208U, 14990U, 4524U, 19791U, 1123U, 15983U, 5439U,
6247 20784U, 2040U, 16976U, 6356U, 21777U, 815U, 15647U, 5131U,
6248 20448U, 1937U, 16863U, 6253U, 21664U, 2107U, 17051U, 6423U,
6249 21852U, 2078U, 17018U, 6394U, 21819U, 832U, 15666U, 5148U,
6250 20467U, 1954U, 16882U, 6270U, 21683U, 12414U, 27548U, 12166U,
6251 27272U, 2787U, 17821U, 7102U, 22621U, 11889U, 26965U, 3250U,
6252 18366U, 7580U, 23183U, 9531U, 25410U, 12466U, 27606U, 12227U,
6253 27339U, 2836U, 17876U, 7151U, 22676U, 11944U, 27026U, 3299U,
6254 18421U, 7629U, 23238U, 9562U, 25445U, 12283U, 27401U, 12011U,
6255 27101U, 2518U, 17508U, 6834U, 22309U, 11750U, 26810U, 2976U,
6256 18044U, 7291U, 22844U, 9478U, 25349U, 13924U, 27824U, 9786U,
6257 25707U, 2857U, 17901U, 8080U, 23765U, 7172U, 22701U, 3792U,
6258 18967U, 10161U, 26138U, 3169U, 18273U, 8440U, 24179U, 7499U,
6259 23090U, 4146U, 19373U, 9236U, 25069U, 10369U, 26376U, 3398U,
6260 18538U, 8588U, 24349U, 7711U, 23336U, 9418U, 25279U, 9625U,
6261 25518U, 7895U, 23550U, 3607U, 18752U, 9831U, 25760U, 2935U,
6262 17993U, 8138U, 23831U, 7250U, 22793U, 3850U, 19033U, 10206U,
6263 26189U, 8470U, 24213U, 9262U, 25099U, 10414U, 26427U, 8618U,
6264 24383U, 9444U, 25309U, 2389U, 17361U, 6705U, 22162U, 2364U,
6265 17334U, 6680U, 22135U, 790U, 15620U, 5106U, 20421U, 1912U,
6266 16836U, 6228U, 21637U, 2400U, 17374U, 6716U, 22175U, 2223U,
6267 17177U, 6539U, 21978U, 2317U, 17283U, 6633U, 22084U, 2306U,
6268 17270U, 6622U, 22071U, 9724U, 25633U, 2607U, 17615U, 8007U,
6269 23678U, 6922U, 22415U, 3719U, 18880U, 10050U, 26013U, 8405U,
6270 24138U, 9169U, 24992U, 10289U, 26284U, 8553U, 24308U, 9338U,
6271 25187U, 9713U, 25620U, 2586U, 17590U, 7983U, 23652U, 6901U,
6272 22390U, 3695U, 18854U, 9979U, 25930U, 3027U, 18105U, 8334U,
6273 24055U, 7342U, 22905U, 4052U, 19263U, 10191U, 26172U, 9247U,
6274 25082U, 10399U, 26410U, 9429U, 25292U, 9806U, 25731U, 2873U,
6275 17921U, 8100U, 23789U, 7188U, 22721U, 3812U, 18991U, 9692U,
6276 25595U, 2569U, 17569U, 7962U, 23627U, 6884U, 22369U, 3674U,
6277 18829U, 9945U, 25890U, 8300U, 24015U, 4018U, 19223U, 9094U,
6278 24903U, 9664U, 25563U, 2546U, 17542U, 7934U, 23595U, 6862U,
6279 22343U, 3646U, 18797U, 9922U, 25863U, 3003U, 18075U, 8258U,
6280 23967U, 7318U, 22875U, 3976U, 19175U, 9071U, 24876U, 9624U,
6281 25517U, 7894U, 23549U, 3606U, 18751U, 13916U, 27814U, 28787U,
6282 28042U, 14272U, 3052U, 18136U, 7380U, 22951U, 27866U, 9830U,
6283 25759U, 8148U, 23843U, 3860U, 19045U, 9723U, 25632U, 8017U,
6284 23690U, 3729U, 18892U, 3313U, 18437U, 7643U, 23254U, 9303U,
6285 25146U, 10130U, 26103U, 10677U, 26617U, 12334U, 27458U, 12071U,
6286 27167U, 11804U, 26870U, 12318U, 27440U, 12052U, 27146U, 11787U,
6287 26851U, 11962U, 27046U, 28772U, 10957U, 26628U, 28282U, 27933U,
6288 28025U, 10074U, 26041U, 11414U, 26751U, 3140U, 18238U, 7470U,
6289 23055U, 3369U, 18503U, 7682U, 23301U, 9654U, 25553U, 7924U,
6290 23585U, 3636U, 18787U, 9912U, 25853U, 8248U, 23957U, 3966U,
6291 19165U, 9061U, 24866U, 29103U, 28065U, 13676U, 27786U, 12986U,
6292 28502U, 27981U, 27736U, 3018U, 18094U, 7333U, 22894U, 3059U,
6293 18145U, 7387U, 22960U, 12365U, 27493U, 12108U, 27208U, 2761U,
6294 17791U, 7076U, 22591U, 11837U, 26907U, 3224U, 18336U, 7554U,
6295 23153U, 9503U, 25378U, 9969U, 25918U, 3010U, 18084U, 8324U,
6296 24043U, 7325U, 22884U, 4042U, 19251U, 9118U, 24931U, 10062U,
6297 26027U, 3150U, 18250U, 8417U, 24152U, 7480U, 23067U, 4123U,
6298 19346U, 9181U, 25006U, 10314U, 26313U, 3379U, 18515U, 8565U,
6299 24322U, 7692U, 23313U, 4225U, 19462U, 9363U, 25216U, 11406U,
6300 26741U, 8124U, 23817U, 3836U, 19019U, 7993U, 23664U, 3705U,
6301 18866U, 9765U, 25682U, 8059U, 23740U, 3771U, 18942U, 10218U,
6302 26203U, 8482U, 24227U, 4176U, 19407U, 9274U, 25113U, 9795U,
6303 25718U, 2864U, 17910U, 8089U, 23776U, 7179U, 22710U, 3801U,
6304 18978U, 87U, 14859U, 4403U, 19660U, 975U, 15823U, 5291U,
6305 20624U, 952U, 15798U, 5268U, 20599U, 110U, 14884U, 4426U,
6306 19685U, 998U, 15848U, 5314U, 20649U, 35U, 14801U, 4351U,
6307 19602U, 66U, 14836U, 4382U, 19637U, 931U, 15775U, 5247U,
6308 20576U, 380U, 15176U, 4696U, 19977U, 1349U, 16227U, 5665U,
6309 21028U, 2123U, 17069U, 6439U, 21870U, 1971U, 16901U, 6287U,
6310 21702U, 849U, 15685U, 5165U, 20486U, 2057U, 16995U, 6373U,
6311 21796U, 2092U, 17034U, 6408U, 21835U, 9602U, 25491U, 2492U,
6312 17476U, 7872U, 23523U, 6808U, 22277U, 3584U, 18725U, 9892U,
6313 25829U, 2952U, 18014U, 8228U, 23933U, 7267U, 22814U, 3946U,
6314 19141U, 9041U, 24842U, 10098U, 26067U, 9193U, 25020U, 10326U,
6315 26327U, 9375U, 25230U, 11422U, 26759U, 29333U, 28109U, 12300U,
6316 27420U, 12031U, 27123U, 11768U, 26830U, 12379U, 27509U, 12125U,
6317 27227U, 11852U, 26924U, 12483U, 27625U, 12247U, 27361U, 11979U,
6318 27065U, 12431U, 27567U, 12186U, 27294U, 11907U, 26985U, 11669U,
6319 26797U, 12289U, 27407U, 12017U, 27107U, 2524U, 17514U, 6840U,
6320 22315U, 11756U, 26816U, 2982U, 18050U, 7297U, 22850U, 9484U,
6321 25355U, 29105U, 12551U, 27687U, 28067U, 9612U, 25503U, 2500U,
6322 17486U, 7882U, 23535U, 6816U, 22287U, 3594U, 18737U, 29362U,
6323 28126U, 11389U, 26729U, 11360U, 26711U, 14420U, 3051U, 18135U,
6324 7379U, 22950U, 27865U, 2333U, 17301U, 2192U, 17144U, 6649U,
6325 22102U, 6508U, 21945U, 3871U, 19058U, 3891U, 19080U, 8159U,
6326 23856U, 10426U, 26441U, 8788U, 24563U, 10523U, 26548U, 8908U,
6327 24695U, 10450U, 26467U, 8812U, 24589U, 4256U, 19497U, 10547U,
6328 26574U, 8932U, 24721U, 4295U, 19540U, 10470U, 26489U, 8855U,
6329 24636U, 4276U, 19519U, 10567U, 26596U, 8975U, 24768U, 4315U,
6330 19562U, 10489U, 26510U, 8874U, 24657U, 10506U, 26529U, 8891U,
6331 24676U, 8630U, 24397U, 8704U, 24475U, 8666U, 24435U, 8745U,
6332 24518U, 3911U, 19102U, 9841U, 25772U, 8177U, 23876U, 8832U,
6333 24611U, 8952U, 24743U, 9858U, 25791U, 8194U, 23895U,
6334};
6335
6336extern const int16_t WebAssemblyRegClassByHwModeTables[2][1] = {
6337 { // DefaultMode
6338 WebAssembly::I32RegClassID, // wasm_ptr_rc
6339 },
6340 { // WASM64
6341 WebAssembly::I64RegClassID, // wasm_ptr_rc
6342 },
6343};
6344
6345static inline void InitWebAssemblyMCInstrInfo(MCInstrInfo *II) {
6346 II->InitMCInstrInfo(WebAssemblyDescs.Insts, WebAssemblyInstrNameIndices, WebAssemblyInstrNameData, nullptr, nullptr, 1959, &WebAssemblyRegClassByHwModeTables[0][0], 1);
6347}
6348
6349
6350} // namespace llvm
6351
6352#endif // GET_INSTRINFO_MC_DESC
6353
6354#ifdef GET_INSTRINFO_HEADER
6355#undef GET_INSTRINFO_HEADER
6356
6357namespace llvm {
6358
6359struct WebAssemblyGenInstrInfo : public TargetInstrInfo {
6360 explicit WebAssemblyGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
6361 ~WebAssemblyGenInstrInfo() override = default;
6362};
6363extern const int16_t WebAssemblyRegClassByHwModeTables[2][1];
6364
6365} // namespace llvm
6366
6367namespace llvm::WebAssembly {
6368
6369
6370} // namespace llvm::WebAssembly
6371
6372#endif // GET_INSTRINFO_HEADER
6373
6374#ifdef GET_INSTRINFO_HELPER_DECLS
6375#undef GET_INSTRINFO_HELPER_DECLS
6376
6377
6378#endif // GET_INSTRINFO_HELPER_DECLS
6379
6380#ifdef GET_INSTRINFO_HELPERS
6381#undef GET_INSTRINFO_HELPERS
6382
6383
6384#endif // GET_INSTRINFO_HELPERS
6385
6386#ifdef GET_INSTRINFO_CTOR_DTOR
6387#undef GET_INSTRINFO_CTOR_DTOR
6388
6389namespace llvm {
6390
6391extern const WebAssemblyInstrTable WebAssemblyDescs;
6392extern const unsigned WebAssemblyInstrNameIndices[];
6393extern const char WebAssemblyInstrNameData[];
6394WebAssemblyGenInstrInfo::WebAssemblyGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
6395 : TargetInstrInfo(TRI, CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode, WebAssemblyRegClassByHwModeTables[STI.getHwMode(MCSubtargetInfo::HwMode_RegInfo)]) {
6396 InitMCInstrInfo(WebAssemblyDescs.Insts, WebAssemblyInstrNameIndices, WebAssemblyInstrNameData, nullptr, nullptr, 1959, &WebAssemblyRegClassByHwModeTables[0][0], 1);
6397}
6398
6399} // namespace llvm
6400
6401#endif // GET_INSTRINFO_CTOR_DTOR
6402
6403#ifdef GET_INSTRINFO_OPERAND_ENUM
6404#undef GET_INSTRINFO_OPERAND_ENUM
6405
6406namespace llvm::WebAssembly {
6407
6408enum class OpName : uint8_t {
6409 dst = 0,
6410 order = 1,
6411 p2align = 2,
6412 off = 3,
6413 addr = 4,
6414 val = 5,
6415 exp = 6,
6416 new_ = 7,
6417 idx = 8,
6418 vec = 9,
6419 count = 10,
6420 timeout = 11,
6421 NUM_OPERAND_NAMES = 12,
6422}; // enum class OpName
6423
6424LLVM_READONLY int16_t getNamedOperandIdx(uint32_t Opcode, OpName Name);
6425LLVM_READONLY OpName getOperandIdxName(uint32_t Opcode, int16_t Idx);
6426
6427} // namespace llvm::WebAssembly
6428
6429#endif // GET_INSTRINFO_OPERAND_ENUM
6430
6431#ifdef GET_INSTRINFO_NAMED_OPS
6432#undef GET_INSTRINFO_NAMED_OPS
6433
6434namespace llvm::WebAssembly {
6435
6436LLVM_READONLY static uint8_t getInstructionIndexForOpLookup(uint32_t Opcode) {
6437 static constexpr uint8_t InstructionIndex[] = {
6438 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6439 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6440 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6441 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6442 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6443 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6444 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6445 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6446 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6447 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6448 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6449 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6450 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6451 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6452 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6453 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6454 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6455 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6456 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6457 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6458 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6459 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6460 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6461 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6462 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6463 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6464 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6465 0, 0, 0, 0, 0, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1,
6466 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1,
6467 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3,
6468 2, 4, 2, 4, 2, 4, 2, 4, 2, 3, 2, 3, 2, 3, 2, 3,
6469 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3,
6470 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3,
6471 2, 4, 2, 4, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3,
6472 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3,
6473 2, 3, 2, 3, 2, 4, 2, 4, 2, 4, 2, 4, 2, 3, 2, 3,
6474 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3,
6475 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3,
6476 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 4, 2, 4,
6477 2, 4, 2, 4, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3,
6478 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3,
6479 2, 3, 2, 3, 2, 5, 2, 5, 2, 5, 2, 5, 2, 5, 2, 5,
6480 2, 5, 2, 5, 2, 5, 2, 5, 2, 5, 2, 5, 2, 5, 2, 5,
6481 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6482 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6483 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6484 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6485 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6486 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6487 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6488 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6489 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6490 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6491 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6492 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6493 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6494 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6495 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6496 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6497 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6498 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6499 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6500 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6501 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6502 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6503 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6504 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6505 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6506 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6507 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6508 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6509 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6510 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 7, 6,
6511 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6,
6512 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6,
6513 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6,
6514 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6,
6515 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6,
6516 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6,
6517 7, 8, 9, 8, 9, 8, 9, 8, 9, 8, 9, 8, 9, 8, 9, 8,
6518 9, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 0, 0, 0,
6519 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6520 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6521 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6522 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6523 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6524 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6525 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 10,
6526 2, 10, 2, 11, 2, 11, 2, 11, 2, 11, 2, 0, 0, 0, 0, 0,
6527 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6528 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6529 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6530 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6531 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6532 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6533 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6534 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6535 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6536 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6537 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6538 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6539 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6540 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6541 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6542 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6543 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6544 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6545 0, 0, 0, 0, 0, 0, 0, 0, 0, 12, 7, 12, 7, 12, 7, 12,
6546 7, 12, 7, 12, 7, 12, 7, 12, 7, 12, 7, 12, 7, 12, 7, 12,
6547 7, 12, 7, 12, 7, 12, 7, 12, 7, 12, 7, 12, 7, 12, 7, 12,
6548 7, 13, 9, 13, 9, 13, 9, 13, 9, 13, 9, 13, 9, 13, 9, 13,
6549 9, 14, 7, 14, 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6550 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6551 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6552 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6553 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6554 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6555 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6556 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6557 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6558 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6559 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6560 0, 0, 0, 0, 0, 0, 0,
6561 };
6562 return InstructionIndex[Opcode];
6563}
6564LLVM_READONLY int16_t getNamedOperandIdx(uint32_t Opcode, OpName Name) {
6565 assert(Name != OpName::NUM_OPERAND_NAMES);
6566 static constexpr int8_t OperandMap[][12] = {
6567 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
6568 {0, 1, 2, 3, 4, -1, -1, -1, -1, -1, -1, -1, },
6569 {-1, 0, 1, 2, -1, -1, -1, -1, -1, -1, -1, -1, },
6570 {0, 1, 2, 3, 4, 5, -1, -1, -1, -1, -1, -1, },
6571 {0, 1, 2, 3, 4, -1, 5, 6, -1, -1, -1, -1, },
6572 {-1, 0, 1, 2, 3, 4, -1, -1, -1, -1, -1, -1, },
6573 {0, -1, 1, 2, 3, -1, -1, -1, -1, -1, -1, -1, },
6574 {-1, -1, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, },
6575 {0, -1, 1, 2, 4, -1, -1, -1, 3, 5, -1, -1, },
6576 {-1, -1, 0, 1, -1, -1, -1, -1, 2, -1, -1, -1, },
6577 {0, 1, 2, 3, 4, -1, -1, -1, -1, -1, 5, -1, },
6578 {0, 1, 2, 3, 4, -1, 5, -1, -1, -1, -1, 6, },
6579 {-1, -1, 0, 1, 2, 3, -1, -1, -1, -1, -1, -1, },
6580 {-1, -1, 0, 1, 3, -1, -1, -1, 2, 4, -1, -1, },
6581 {-1, -1, 0, 1, 2, -1, -1, -1, -1, 3, -1, -1, },
6582 };
6583 unsigned InstrIdx = getInstructionIndexForOpLookup(Opcode);
6584 return OperandMap[InstrIdx][(unsigned)Name];
6585}
6586LLVM_READONLY OpName getOperandIdxName(uint32_t Opcode, int16_t Idx) {
6587 assert(Idx >= 0 && Idx < 7);
6588 static constexpr OpName OperandMap[][7] = {
6589 {OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
6590 {OpName::dst, OpName::order, OpName::p2align, OpName::off, OpName::addr, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
6591 {OpName::order, OpName::p2align, OpName::off, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
6592 {OpName::dst, OpName::order, OpName::p2align, OpName::off, OpName::addr, OpName::val, OpName::NUM_OPERAND_NAMES, },
6593 {OpName::dst, OpName::order, OpName::p2align, OpName::off, OpName::addr, OpName::exp, OpName::new_, },
6594 {OpName::order, OpName::p2align, OpName::off, OpName::addr, OpName::val, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
6595 {OpName::dst, OpName::p2align, OpName::off, OpName::addr, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
6596 {OpName::p2align, OpName::off, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
6597 {OpName::dst, OpName::p2align, OpName::off, OpName::idx, OpName::addr, OpName::vec, OpName::NUM_OPERAND_NAMES, },
6598 {OpName::p2align, OpName::off, OpName::idx, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
6599 {OpName::dst, OpName::order, OpName::p2align, OpName::off, OpName::addr, OpName::count, OpName::NUM_OPERAND_NAMES, },
6600 {OpName::dst, OpName::order, OpName::p2align, OpName::off, OpName::addr, OpName::exp, OpName::timeout, },
6601 {OpName::p2align, OpName::off, OpName::addr, OpName::val, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
6602 {OpName::p2align, OpName::off, OpName::idx, OpName::addr, OpName::vec, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
6603 {OpName::p2align, OpName::off, OpName::addr, OpName::vec, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
6604 };
6605 unsigned InstrIdx = getInstructionIndexForOpLookup(Opcode);
6606 return OperandMap[InstrIdx][(unsigned)Idx];
6607}
6608
6609} // namespace llvm::WebAssembly
6610
6611#endif // GET_INSTRINFO_NAMED_OPS
6612
6613#ifdef GET_INSTRINFO_MC_HELPER_DECLS
6614#undef GET_INSTRINFO_MC_HELPER_DECLS
6615
6616namespace llvm {
6617
6618class MCInst;
6619class FeatureBitset;
6620
6621namespace WebAssembly_MC {
6622
6623void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
6624
6625} // namespace WebAssembly_MC
6626
6627} // namespace llvm
6628
6629#endif // GET_INSTRINFO_MC_HELPER_DECLS
6630
6631#ifdef GET_INSTRINFO_MC_HELPERS
6632#undef GET_INSTRINFO_MC_HELPERS
6633
6634namespace llvm::WebAssembly_MC {
6635
6636
6637} // namespace llvm::WebAssembly_MC
6638
6639#endif // GET_INSTRINFO_MC_HELPERS
6640
6641#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
6642 defined(GET_AVAILABLE_OPCODE_CHECKER)
6643#define GET_COMPUTE_FEATURES
6644#endif
6645#ifdef GET_COMPUTE_FEATURES
6646#undef GET_COMPUTE_FEATURES
6647
6648namespace llvm::WebAssembly_MC {
6649
6650// Bits for subtarget features that participate in instruction matching.
6651enum SubtargetFeatureBits : uint8_t {
6652 Feature_HasAtomicsBit = 0,
6653 Feature_HasBulkMemoryBit = 1,
6654 Feature_HasBulkMemoryOptBit = 2,
6655 Feature_HasCallIndirectOverlongBit = 3,
6656 Feature_HasExceptionHandlingBit = 4,
6657 Feature_HasExtendedConstBit = 5,
6658 Feature_HasFP16Bit = 6,
6659 Feature_HasGCBit = 7,
6660 Feature_HasMultiMemoryBit = 8,
6661 Feature_HasMultivalueBit = 9,
6662 Feature_HasMutableGlobalsBit = 10,
6663 Feature_HasNontrappingFPToIntBit = 11,
6664 Feature_NotHasNontrappingFPToIntBit = 19,
6665 Feature_HasReferenceTypesBit = 12,
6666 Feature_HasRelaxedAtomicsBit = 13,
6667 Feature_HasRelaxedSIMDBit = 14,
6668 Feature_HasSignExtBit = 16,
6669 Feature_HasSIMD128Bit = 15,
6670 Feature_HasTailCallBit = 17,
6671 Feature_HasWideArithmeticBit = 18,
6672};
6673
6674inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
6675 FeatureBitset Features;
6676 if (FB[WebAssembly::FeatureAtomics])
6677 Features.set(Feature_HasAtomicsBit);
6678 if (FB[WebAssembly::FeatureBulkMemory])
6679 Features.set(Feature_HasBulkMemoryBit);
6680 if (FB[WebAssembly::FeatureBulkMemoryOpt])
6681 Features.set(Feature_HasBulkMemoryOptBit);
6682 if (FB[WebAssembly::FeatureCallIndirectOverlong])
6683 Features.set(Feature_HasCallIndirectOverlongBit);
6684 if (FB[WebAssembly::FeatureExceptionHandling])
6685 Features.set(Feature_HasExceptionHandlingBit);
6686 if (FB[WebAssembly::FeatureExtendedConst])
6687 Features.set(Feature_HasExtendedConstBit);
6688 if (FB[WebAssembly::FeatureFP16])
6689 Features.set(Feature_HasFP16Bit);
6690 if (FB[WebAssembly::FeatureGC])
6691 Features.set(Feature_HasGCBit);
6692 if (FB[WebAssembly::FeatureMultiMemory])
6693 Features.set(Feature_HasMultiMemoryBit);
6694 if (FB[WebAssembly::FeatureMultivalue])
6695 Features.set(Feature_HasMultivalueBit);
6696 if (FB[WebAssembly::FeatureMutableGlobals])
6697 Features.set(Feature_HasMutableGlobalsBit);
6698 if (FB[WebAssembly::FeatureNontrappingFPToInt])
6699 Features.set(Feature_HasNontrappingFPToIntBit);
6700 if (!FB[WebAssembly::FeatureNontrappingFPToInt])
6701 Features.set(Feature_NotHasNontrappingFPToIntBit);
6702 if (FB[WebAssembly::FeatureReferenceTypes])
6703 Features.set(Feature_HasReferenceTypesBit);
6704 if (FB[WebAssembly::FeatureRelaxedAtomics])
6705 Features.set(Feature_HasRelaxedAtomicsBit);
6706 if (FB[WebAssembly::FeatureRelaxedSIMD])
6707 Features.set(Feature_HasRelaxedSIMDBit);
6708 if (FB[WebAssembly::FeatureSignExt])
6709 Features.set(Feature_HasSignExtBit);
6710 if (FB[WebAssembly::FeatureSIMD128] || FB[WebAssembly::FeatureRelaxedSIMD])
6711 Features.set(Feature_HasSIMD128Bit);
6712 if (FB[WebAssembly::FeatureTailCall])
6713 Features.set(Feature_HasTailCallBit);
6714 if (FB[WebAssembly::FeatureWideArithmetic])
6715 Features.set(Feature_HasWideArithmeticBit);
6716 return Features;
6717}
6718
6719inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
6720 enum : uint8_t {
6721 CEFBS_None,
6722 CEFBS_HasAtomics,
6723 CEFBS_HasBulkMemoryOpt,
6724 CEFBS_HasExceptionHandling,
6725 CEFBS_HasFP16,
6726 CEFBS_HasGC,
6727 CEFBS_HasNontrappingFPToInt,
6728 CEFBS_HasReferenceTypes,
6729 CEFBS_HasRelaxedSIMD,
6730 CEFBS_HasSIMD128,
6731 CEFBS_HasSignExt,
6732 CEFBS_HasTailCall,
6733 CEFBS_HasWideArithmetic,
6734 CEFBS_NotHasNontrappingFPToInt,
6735 CEFBS_HasReferenceTypes_HasExceptionHandling,
6736 CEFBS_HasSIMD128_HasFP16,
6737 CEFBS_HasSIMD128_HasRelaxedSIMD,
6738 };
6739
6740 static constexpr FeatureBitset FeatureBitsets[] = {
6741 {}, // CEFBS_None
6742 {Feature_HasAtomicsBit, },
6743 {Feature_HasBulkMemoryOptBit, },
6744 {Feature_HasExceptionHandlingBit, },
6745 {Feature_HasFP16Bit, },
6746 {Feature_HasGCBit, },
6747 {Feature_HasNontrappingFPToIntBit, },
6748 {Feature_HasReferenceTypesBit, },
6749 {Feature_HasRelaxedSIMDBit, },
6750 {Feature_HasSIMD128Bit, },
6751 {Feature_HasSignExtBit, },
6752 {Feature_HasTailCallBit, },
6753 {Feature_HasWideArithmeticBit, },
6754 {Feature_NotHasNontrappingFPToIntBit, },
6755 {Feature_HasReferenceTypesBit, Feature_HasExceptionHandlingBit, },
6756 {Feature_HasSIMD128Bit, Feature_HasFP16Bit, },
6757 {Feature_HasSIMD128Bit, Feature_HasRelaxedSIMDBit, },
6758 };
6759 static constexpr uint8_t RequiredFeaturesRefs[] = {
6760 CEFBS_None, // PHI
6761 CEFBS_None, // INLINEASM
6762 CEFBS_None, // INLINEASM_BR
6763 CEFBS_None, // CFI_INSTRUCTION
6764 CEFBS_None, // EH_LABEL
6765 CEFBS_None, // GC_LABEL
6766 CEFBS_None, // ANNOTATION_LABEL
6767 CEFBS_None, // KILL
6768 CEFBS_None, // EXTRACT_SUBREG
6769 CEFBS_None, // INSERT_SUBREG
6770 CEFBS_None, // IMPLICIT_DEF
6771 CEFBS_None, // INIT_UNDEF
6772 CEFBS_None, // SUBREG_TO_REG
6773 CEFBS_None, // COPY_TO_REGCLASS
6774 CEFBS_None, // DBG_VALUE
6775 CEFBS_None, // DBG_VALUE_LIST
6776 CEFBS_None, // DBG_INSTR_REF
6777 CEFBS_None, // DBG_PHI
6778 CEFBS_None, // DBG_LABEL
6779 CEFBS_None, // REG_SEQUENCE
6780 CEFBS_None, // COPY
6781 CEFBS_None, // COPY_LANEMASK
6782 CEFBS_None, // BUNDLE
6783 CEFBS_None, // LIFETIME_START
6784 CEFBS_None, // LIFETIME_END
6785 CEFBS_None, // PSEUDO_PROBE
6786 CEFBS_None, // ARITH_FENCE
6787 CEFBS_None, // STACKMAP
6788 CEFBS_None, // FENTRY_CALL
6789 CEFBS_None, // PATCHPOINT
6790 CEFBS_None, // LOAD_STACK_GUARD
6791 CEFBS_None, // PREALLOCATED_SETUP
6792 CEFBS_None, // PREALLOCATED_ARG
6793 CEFBS_None, // STATEPOINT
6794 CEFBS_None, // LOCAL_ESCAPE
6795 CEFBS_None, // FAULTING_OP
6796 CEFBS_None, // PATCHABLE_OP
6797 CEFBS_None, // PATCHABLE_FUNCTION_ENTER
6798 CEFBS_None, // PATCHABLE_RET
6799 CEFBS_None, // PATCHABLE_FUNCTION_EXIT
6800 CEFBS_None, // PATCHABLE_TAIL_CALL
6801 CEFBS_None, // PATCHABLE_EVENT_CALL
6802 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL
6803 CEFBS_None, // ICALL_BRANCH_FUNNEL
6804 CEFBS_None, // FAKE_USE
6805 CEFBS_None, // MEMBARRIER
6806 CEFBS_None, // JUMP_TABLE_DEBUG_INFO
6807 CEFBS_None, // RELOC_NONE
6808 CEFBS_None, // CONVERGENCECTRL_ENTRY
6809 CEFBS_None, // CONVERGENCECTRL_ANCHOR
6810 CEFBS_None, // CONVERGENCECTRL_LOOP
6811 CEFBS_None, // CONVERGENCECTRL_GLUE
6812 CEFBS_None, // G_ASSERT_SEXT
6813 CEFBS_None, // G_ASSERT_ZEXT
6814 CEFBS_None, // G_ASSERT_ALIGN
6815 CEFBS_None, // G_ADD
6816 CEFBS_None, // G_SUB
6817 CEFBS_None, // G_MUL
6818 CEFBS_None, // G_SDIV
6819 CEFBS_None, // G_UDIV
6820 CEFBS_None, // G_SREM
6821 CEFBS_None, // G_UREM
6822 CEFBS_None, // G_SDIVREM
6823 CEFBS_None, // G_UDIVREM
6824 CEFBS_None, // G_AND
6825 CEFBS_None, // G_OR
6826 CEFBS_None, // G_XOR
6827 CEFBS_None, // G_ABDS
6828 CEFBS_None, // G_ABDU
6829 CEFBS_None, // G_UAVGFLOOR
6830 CEFBS_None, // G_UAVGCEIL
6831 CEFBS_None, // G_SAVGFLOOR
6832 CEFBS_None, // G_SAVGCEIL
6833 CEFBS_None, // G_IMPLICIT_DEF
6834 CEFBS_None, // G_PHI
6835 CEFBS_None, // G_FRAME_INDEX
6836 CEFBS_None, // G_GLOBAL_VALUE
6837 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE
6838 CEFBS_None, // G_CONSTANT_POOL
6839 CEFBS_None, // G_EXTRACT
6840 CEFBS_None, // G_UNMERGE_VALUES
6841 CEFBS_None, // G_INSERT
6842 CEFBS_None, // G_MERGE_VALUES
6843 CEFBS_None, // G_BUILD_VECTOR
6844 CEFBS_None, // G_BUILD_VECTOR_TRUNC
6845 CEFBS_None, // G_CONCAT_VECTORS
6846 CEFBS_None, // G_PTRTOINT
6847 CEFBS_None, // G_INTTOPTR
6848 CEFBS_None, // G_BITCAST
6849 CEFBS_None, // G_FREEZE
6850 CEFBS_None, // G_CONSTANT_FOLD_BARRIER
6851 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND
6852 CEFBS_None, // G_INTRINSIC_TRUNC
6853 CEFBS_None, // G_INTRINSIC_ROUND
6854 CEFBS_None, // G_INTRINSIC_LRINT
6855 CEFBS_None, // G_INTRINSIC_LLRINT
6856 CEFBS_None, // G_INTRINSIC_ROUNDEVEN
6857 CEFBS_None, // G_READCYCLECOUNTER
6858 CEFBS_None, // G_READSTEADYCOUNTER
6859 CEFBS_None, // G_LOAD
6860 CEFBS_None, // G_SEXTLOAD
6861 CEFBS_None, // G_ZEXTLOAD
6862 CEFBS_None, // G_INDEXED_LOAD
6863 CEFBS_None, // G_INDEXED_SEXTLOAD
6864 CEFBS_None, // G_INDEXED_ZEXTLOAD
6865 CEFBS_None, // G_STORE
6866 CEFBS_None, // G_INDEXED_STORE
6867 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
6868 CEFBS_None, // G_ATOMIC_CMPXCHG
6869 CEFBS_None, // G_ATOMICRMW_XCHG
6870 CEFBS_None, // G_ATOMICRMW_ADD
6871 CEFBS_None, // G_ATOMICRMW_SUB
6872 CEFBS_None, // G_ATOMICRMW_AND
6873 CEFBS_None, // G_ATOMICRMW_NAND
6874 CEFBS_None, // G_ATOMICRMW_OR
6875 CEFBS_None, // G_ATOMICRMW_XOR
6876 CEFBS_None, // G_ATOMICRMW_MAX
6877 CEFBS_None, // G_ATOMICRMW_MIN
6878 CEFBS_None, // G_ATOMICRMW_UMAX
6879 CEFBS_None, // G_ATOMICRMW_UMIN
6880 CEFBS_None, // G_ATOMICRMW_FADD
6881 CEFBS_None, // G_ATOMICRMW_FSUB
6882 CEFBS_None, // G_ATOMICRMW_FMAX
6883 CEFBS_None, // G_ATOMICRMW_FMIN
6884 CEFBS_None, // G_ATOMICRMW_FMAXIMUM
6885 CEFBS_None, // G_ATOMICRMW_FMINIMUM
6886 CEFBS_None, // G_ATOMICRMW_FMAXIMUMNUM
6887 CEFBS_None, // G_ATOMICRMW_FMINIMUMNUM
6888 CEFBS_None, // G_ATOMICRMW_UINC_WRAP
6889 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP
6890 CEFBS_None, // G_ATOMICRMW_USUB_COND
6891 CEFBS_None, // G_ATOMICRMW_USUB_SAT
6892 CEFBS_None, // G_FENCE
6893 CEFBS_None, // G_PREFETCH
6894 CEFBS_None, // G_BRCOND
6895 CEFBS_None, // G_BRINDIRECT
6896 CEFBS_None, // G_INVOKE_REGION_START
6897 CEFBS_None, // G_INTRINSIC
6898 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS
6899 CEFBS_None, // G_INTRINSIC_CONVERGENT
6900 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
6901 CEFBS_None, // G_ANYEXT
6902 CEFBS_None, // G_TRUNC
6903 CEFBS_None, // G_TRUNC_SSAT_S
6904 CEFBS_None, // G_TRUNC_SSAT_U
6905 CEFBS_None, // G_TRUNC_USAT_U
6906 CEFBS_None, // G_CONSTANT
6907 CEFBS_None, // G_FCONSTANT
6908 CEFBS_None, // G_VASTART
6909 CEFBS_None, // G_VAARG
6910 CEFBS_None, // G_SEXT
6911 CEFBS_None, // G_SEXT_INREG
6912 CEFBS_None, // G_ZEXT
6913 CEFBS_None, // G_SHL
6914 CEFBS_None, // G_LSHR
6915 CEFBS_None, // G_ASHR
6916 CEFBS_None, // G_FSHL
6917 CEFBS_None, // G_FSHR
6918 CEFBS_None, // G_ROTR
6919 CEFBS_None, // G_ROTL
6920 CEFBS_None, // G_ICMP
6921 CEFBS_None, // G_FCMP
6922 CEFBS_None, // G_SCMP
6923 CEFBS_None, // G_UCMP
6924 CEFBS_None, // G_SELECT
6925 CEFBS_None, // G_UADDO
6926 CEFBS_None, // G_UADDE
6927 CEFBS_None, // G_USUBO
6928 CEFBS_None, // G_USUBE
6929 CEFBS_None, // G_SADDO
6930 CEFBS_None, // G_SADDE
6931 CEFBS_None, // G_SSUBO
6932 CEFBS_None, // G_SSUBE
6933 CEFBS_None, // G_UMULO
6934 CEFBS_None, // G_SMULO
6935 CEFBS_None, // G_UMULH
6936 CEFBS_None, // G_SMULH
6937 CEFBS_None, // G_UADDSAT
6938 CEFBS_None, // G_SADDSAT
6939 CEFBS_None, // G_USUBSAT
6940 CEFBS_None, // G_SSUBSAT
6941 CEFBS_None, // G_USHLSAT
6942 CEFBS_None, // G_SSHLSAT
6943 CEFBS_None, // G_SMULFIX
6944 CEFBS_None, // G_UMULFIX
6945 CEFBS_None, // G_SMULFIXSAT
6946 CEFBS_None, // G_UMULFIXSAT
6947 CEFBS_None, // G_SDIVFIX
6948 CEFBS_None, // G_UDIVFIX
6949 CEFBS_None, // G_SDIVFIXSAT
6950 CEFBS_None, // G_UDIVFIXSAT
6951 CEFBS_None, // G_FADD
6952 CEFBS_None, // G_FSUB
6953 CEFBS_None, // G_FMUL
6954 CEFBS_None, // G_FMA
6955 CEFBS_None, // G_FMAD
6956 CEFBS_None, // G_FDIV
6957 CEFBS_None, // G_FREM
6958 CEFBS_None, // G_FMODF
6959 CEFBS_None, // G_FPOW
6960 CEFBS_None, // G_FPOWI
6961 CEFBS_None, // G_FEXP
6962 CEFBS_None, // G_FEXP2
6963 CEFBS_None, // G_FEXP10
6964 CEFBS_None, // G_FLOG
6965 CEFBS_None, // G_FLOG2
6966 CEFBS_None, // G_FLOG10
6967 CEFBS_None, // G_FLDEXP
6968 CEFBS_None, // G_FFREXP
6969 CEFBS_None, // G_FNEG
6970 CEFBS_None, // G_FPEXT
6971 CEFBS_None, // G_FPTRUNC
6972 CEFBS_None, // G_FPTOSI
6973 CEFBS_None, // G_FPTOUI
6974 CEFBS_None, // G_SITOFP
6975 CEFBS_None, // G_UITOFP
6976 CEFBS_None, // G_FPTOSI_SAT
6977 CEFBS_None, // G_FPTOUI_SAT
6978 CEFBS_None, // G_FABS
6979 CEFBS_None, // G_FCOPYSIGN
6980 CEFBS_None, // G_IS_FPCLASS
6981 CEFBS_None, // G_FCANONICALIZE
6982 CEFBS_None, // G_FMINNUM
6983 CEFBS_None, // G_FMAXNUM
6984 CEFBS_None, // G_FMINNUM_IEEE
6985 CEFBS_None, // G_FMAXNUM_IEEE
6986 CEFBS_None, // G_FMINIMUM
6987 CEFBS_None, // G_FMAXIMUM
6988 CEFBS_None, // G_FMINIMUMNUM
6989 CEFBS_None, // G_FMAXIMUMNUM
6990 CEFBS_None, // G_GET_FPENV
6991 CEFBS_None, // G_SET_FPENV
6992 CEFBS_None, // G_RESET_FPENV
6993 CEFBS_None, // G_GET_FPMODE
6994 CEFBS_None, // G_SET_FPMODE
6995 CEFBS_None, // G_RESET_FPMODE
6996 CEFBS_None, // G_GET_ROUNDING
6997 CEFBS_None, // G_SET_ROUNDING
6998 CEFBS_None, // G_PTR_ADD
6999 CEFBS_None, // G_PTRMASK
7000 CEFBS_None, // G_SMIN
7001 CEFBS_None, // G_SMAX
7002 CEFBS_None, // G_UMIN
7003 CEFBS_None, // G_UMAX
7004 CEFBS_None, // G_ABS
7005 CEFBS_None, // G_LROUND
7006 CEFBS_None, // G_LLROUND
7007 CEFBS_None, // G_BR
7008 CEFBS_None, // G_BRJT
7009 CEFBS_None, // G_VSCALE
7010 CEFBS_None, // G_INSERT_SUBVECTOR
7011 CEFBS_None, // G_EXTRACT_SUBVECTOR
7012 CEFBS_None, // G_INSERT_VECTOR_ELT
7013 CEFBS_None, // G_EXTRACT_VECTOR_ELT
7014 CEFBS_None, // G_SHUFFLE_VECTOR
7015 CEFBS_None, // G_SPLAT_VECTOR
7016 CEFBS_None, // G_STEP_VECTOR
7017 CEFBS_None, // G_VECTOR_COMPRESS
7018 CEFBS_None, // G_CTTZ
7019 CEFBS_None, // G_CTTZ_ZERO_UNDEF
7020 CEFBS_None, // G_CTLZ
7021 CEFBS_None, // G_CTLZ_ZERO_UNDEF
7022 CEFBS_None, // G_CTLS
7023 CEFBS_None, // G_CTPOP
7024 CEFBS_None, // G_BSWAP
7025 CEFBS_None, // G_BITREVERSE
7026 CEFBS_None, // G_FCEIL
7027 CEFBS_None, // G_FCOS
7028 CEFBS_None, // G_FSIN
7029 CEFBS_None, // G_FSINCOS
7030 CEFBS_None, // G_FTAN
7031 CEFBS_None, // G_FACOS
7032 CEFBS_None, // G_FASIN
7033 CEFBS_None, // G_FATAN
7034 CEFBS_None, // G_FATAN2
7035 CEFBS_None, // G_FCOSH
7036 CEFBS_None, // G_FSINH
7037 CEFBS_None, // G_FTANH
7038 CEFBS_None, // G_FSQRT
7039 CEFBS_None, // G_FFLOOR
7040 CEFBS_None, // G_FRINT
7041 CEFBS_None, // G_FNEARBYINT
7042 CEFBS_None, // G_ADDRSPACE_CAST
7043 CEFBS_None, // G_BLOCK_ADDR
7044 CEFBS_None, // G_JUMP_TABLE
7045 CEFBS_None, // G_DYN_STACKALLOC
7046 CEFBS_None, // G_STACKSAVE
7047 CEFBS_None, // G_STACKRESTORE
7048 CEFBS_None, // G_STRICT_FADD
7049 CEFBS_None, // G_STRICT_FSUB
7050 CEFBS_None, // G_STRICT_FMUL
7051 CEFBS_None, // G_STRICT_FDIV
7052 CEFBS_None, // G_STRICT_FREM
7053 CEFBS_None, // G_STRICT_FMA
7054 CEFBS_None, // G_STRICT_FSQRT
7055 CEFBS_None, // G_STRICT_FLDEXP
7056 CEFBS_None, // G_READ_REGISTER
7057 CEFBS_None, // G_WRITE_REGISTER
7058 CEFBS_None, // G_MEMCPY
7059 CEFBS_None, // G_MEMCPY_INLINE
7060 CEFBS_None, // G_MEMMOVE
7061 CEFBS_None, // G_MEMSET
7062 CEFBS_None, // G_BZERO
7063 CEFBS_None, // G_TRAP
7064 CEFBS_None, // G_DEBUGTRAP
7065 CEFBS_None, // G_UBSANTRAP
7066 CEFBS_None, // G_VECREDUCE_SEQ_FADD
7067 CEFBS_None, // G_VECREDUCE_SEQ_FMUL
7068 CEFBS_None, // G_VECREDUCE_FADD
7069 CEFBS_None, // G_VECREDUCE_FMUL
7070 CEFBS_None, // G_VECREDUCE_FMAX
7071 CEFBS_None, // G_VECREDUCE_FMIN
7072 CEFBS_None, // G_VECREDUCE_FMAXIMUM
7073 CEFBS_None, // G_VECREDUCE_FMINIMUM
7074 CEFBS_None, // G_VECREDUCE_ADD
7075 CEFBS_None, // G_VECREDUCE_MUL
7076 CEFBS_None, // G_VECREDUCE_AND
7077 CEFBS_None, // G_VECREDUCE_OR
7078 CEFBS_None, // G_VECREDUCE_XOR
7079 CEFBS_None, // G_VECREDUCE_SMAX
7080 CEFBS_None, // G_VECREDUCE_SMIN
7081 CEFBS_None, // G_VECREDUCE_UMAX
7082 CEFBS_None, // G_VECREDUCE_UMIN
7083 CEFBS_None, // G_SBFX
7084 CEFBS_None, // G_UBFX
7085 CEFBS_None, // CALL_PARAMS
7086 CEFBS_None, // CALL_PARAMS_S
7087 CEFBS_None, // CALL_RESULTS
7088 CEFBS_None, // CALL_RESULTS_S
7089 CEFBS_HasExceptionHandling, // CATCHRET
7090 CEFBS_HasExceptionHandling, // CATCHRET_S
7091 CEFBS_HasExceptionHandling, // CLEANUPRET
7092 CEFBS_HasExceptionHandling, // CLEANUPRET_S
7093 CEFBS_HasAtomics, // COMPILER_FENCE
7094 CEFBS_HasAtomics, // COMPILER_FENCE_S
7095 CEFBS_None, // RET_CALL_RESULTS
7096 CEFBS_None, // RET_CALL_RESULTS_S
7097 CEFBS_HasSIMD128_HasFP16, // ABS_F16x8
7098 CEFBS_HasSIMD128_HasFP16, // ABS_F16x8_S
7099 CEFBS_None, // ABS_F32
7100 CEFBS_None, // ABS_F32_S
7101 CEFBS_HasSIMD128, // ABS_F32x4
7102 CEFBS_HasSIMD128, // ABS_F32x4_S
7103 CEFBS_None, // ABS_F64
7104 CEFBS_None, // ABS_F64_S
7105 CEFBS_HasSIMD128, // ABS_F64x2
7106 CEFBS_HasSIMD128, // ABS_F64x2_S
7107 CEFBS_HasSIMD128, // ABS_I16x8
7108 CEFBS_HasSIMD128, // ABS_I16x8_S
7109 CEFBS_HasSIMD128, // ABS_I32x4
7110 CEFBS_HasSIMD128, // ABS_I32x4_S
7111 CEFBS_HasSIMD128, // ABS_I64x2
7112 CEFBS_HasSIMD128, // ABS_I64x2_S
7113 CEFBS_HasSIMD128, // ABS_I8x16
7114 CEFBS_HasSIMD128, // ABS_I8x16_S
7115 CEFBS_HasSIMD128_HasFP16, // ADD_F16x8
7116 CEFBS_HasSIMD128_HasFP16, // ADD_F16x8_S
7117 CEFBS_None, // ADD_F32
7118 CEFBS_None, // ADD_F32_S
7119 CEFBS_HasSIMD128, // ADD_F32x4
7120 CEFBS_HasSIMD128, // ADD_F32x4_S
7121 CEFBS_None, // ADD_F64
7122 CEFBS_None, // ADD_F64_S
7123 CEFBS_HasSIMD128, // ADD_F64x2
7124 CEFBS_HasSIMD128, // ADD_F64x2_S
7125 CEFBS_HasSIMD128, // ADD_I16x8
7126 CEFBS_HasSIMD128, // ADD_I16x8_S
7127 CEFBS_None, // ADD_I32
7128 CEFBS_None, // ADD_I32_S
7129 CEFBS_HasSIMD128, // ADD_I32x4
7130 CEFBS_HasSIMD128, // ADD_I32x4_S
7131 CEFBS_None, // ADD_I64
7132 CEFBS_None, // ADD_I64_S
7133 CEFBS_HasSIMD128, // ADD_I64x2
7134 CEFBS_HasSIMD128, // ADD_I64x2_S
7135 CEFBS_HasSIMD128, // ADD_I8x16
7136 CEFBS_HasSIMD128, // ADD_I8x16_S
7137 CEFBS_HasSIMD128, // ADD_SAT_S_I16x8
7138 CEFBS_HasSIMD128, // ADD_SAT_S_I16x8_S
7139 CEFBS_HasSIMD128, // ADD_SAT_S_I8x16
7140 CEFBS_HasSIMD128, // ADD_SAT_S_I8x16_S
7141 CEFBS_HasSIMD128, // ADD_SAT_U_I16x8
7142 CEFBS_HasSIMD128, // ADD_SAT_U_I16x8_S
7143 CEFBS_HasSIMD128, // ADD_SAT_U_I8x16
7144 CEFBS_HasSIMD128, // ADD_SAT_U_I8x16_S
7145 CEFBS_None, // ADJCALLSTACKDOWN
7146 CEFBS_None, // ADJCALLSTACKDOWN_S
7147 CEFBS_None, // ADJCALLSTACKUP
7148 CEFBS_None, // ADJCALLSTACKUP_S
7149 CEFBS_HasSIMD128, // ALLTRUE_I16x8
7150 CEFBS_HasSIMD128, // ALLTRUE_I16x8_S
7151 CEFBS_HasSIMD128, // ALLTRUE_I32x4
7152 CEFBS_HasSIMD128, // ALLTRUE_I32x4_S
7153 CEFBS_HasSIMD128, // ALLTRUE_I64x2
7154 CEFBS_HasSIMD128, // ALLTRUE_I64x2_S
7155 CEFBS_HasSIMD128, // ALLTRUE_I8x16
7156 CEFBS_HasSIMD128, // ALLTRUE_I8x16_S
7157 CEFBS_HasSIMD128, // AND
7158 CEFBS_HasSIMD128, // ANDNOT
7159 CEFBS_HasSIMD128, // ANDNOT_S
7160 CEFBS_None, // AND_I32
7161 CEFBS_None, // AND_I32_S
7162 CEFBS_None, // AND_I64
7163 CEFBS_None, // AND_I64_S
7164 CEFBS_HasSIMD128, // AND_S
7165 CEFBS_HasSIMD128, // ANYTRUE
7166 CEFBS_HasSIMD128, // ANYTRUE_S
7167 CEFBS_None, // ARGUMENT_exnref
7168 CEFBS_None, // ARGUMENT_exnref_S
7169 CEFBS_None, // ARGUMENT_externref
7170 CEFBS_None, // ARGUMENT_externref_S
7171 CEFBS_None, // ARGUMENT_f32
7172 CEFBS_None, // ARGUMENT_f32_S
7173 CEFBS_None, // ARGUMENT_f64
7174 CEFBS_None, // ARGUMENT_f64_S
7175 CEFBS_None, // ARGUMENT_funcref
7176 CEFBS_None, // ARGUMENT_funcref_S
7177 CEFBS_None, // ARGUMENT_i32
7178 CEFBS_None, // ARGUMENT_i32_S
7179 CEFBS_None, // ARGUMENT_i64
7180 CEFBS_None, // ARGUMENT_i64_S
7181 CEFBS_None, // ARGUMENT_v16i8
7182 CEFBS_None, // ARGUMENT_v16i8_S
7183 CEFBS_None, // ARGUMENT_v2f64
7184 CEFBS_None, // ARGUMENT_v2f64_S
7185 CEFBS_None, // ARGUMENT_v2i64
7186 CEFBS_None, // ARGUMENT_v2i64_S
7187 CEFBS_None, // ARGUMENT_v4f32
7188 CEFBS_None, // ARGUMENT_v4f32_S
7189 CEFBS_None, // ARGUMENT_v4i32
7190 CEFBS_None, // ARGUMENT_v4i32_S
7191 CEFBS_None, // ARGUMENT_v8f16
7192 CEFBS_None, // ARGUMENT_v8f16_S
7193 CEFBS_None, // ARGUMENT_v8i16
7194 CEFBS_None, // ARGUMENT_v8i16_S
7195 CEFBS_HasAtomics, // ATOMIC_FENCE
7196 CEFBS_HasAtomics, // ATOMIC_FENCE_S
7197 CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I32_A32
7198 CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I32_A32_S
7199 CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I32_A64
7200 CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I32_A64_S
7201 CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I64_A32
7202 CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I64_A32_S
7203 CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I64_A64
7204 CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I64_A64_S
7205 CEFBS_HasAtomics, // ATOMIC_LOAD32_U_I64_A32
7206 CEFBS_HasAtomics, // ATOMIC_LOAD32_U_I64_A32_S
7207 CEFBS_HasAtomics, // ATOMIC_LOAD32_U_I64_A64
7208 CEFBS_HasAtomics, // ATOMIC_LOAD32_U_I64_A64_S
7209 CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I32_A32
7210 CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I32_A32_S
7211 CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I32_A64
7212 CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I32_A64_S
7213 CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I64_A32
7214 CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I64_A32_S
7215 CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I64_A64
7216 CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I64_A64_S
7217 CEFBS_HasAtomics, // ATOMIC_LOAD_I32_A32
7218 CEFBS_HasAtomics, // ATOMIC_LOAD_I32_A32_S
7219 CEFBS_HasAtomics, // ATOMIC_LOAD_I32_A64
7220 CEFBS_HasAtomics, // ATOMIC_LOAD_I32_A64_S
7221 CEFBS_HasAtomics, // ATOMIC_LOAD_I64_A32
7222 CEFBS_HasAtomics, // ATOMIC_LOAD_I64_A32_S
7223 CEFBS_HasAtomics, // ATOMIC_LOAD_I64_A64
7224 CEFBS_HasAtomics, // ATOMIC_LOAD_I64_A64_S
7225 CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I32_A32
7226 CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I32_A32_S
7227 CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I32_A64
7228 CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I32_A64_S
7229 CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I64_A32
7230 CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I64_A32_S
7231 CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I64_A64
7232 CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I64_A64_S
7233 CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I32_A32
7234 CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I32_A32_S
7235 CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I32_A64
7236 CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I32_A64_S
7237 CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I64_A32
7238 CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I64_A32_S
7239 CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I64_A64
7240 CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I64_A64_S
7241 CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I32_A32
7242 CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I32_A32_S
7243 CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I32_A64
7244 CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I32_A64_S
7245 CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I64_A32
7246 CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I64_A32_S
7247 CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I64_A64
7248 CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I64_A64_S
7249 CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I32_A32
7250 CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I32_A32_S
7251 CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I32_A64
7252 CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I32_A64_S
7253 CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I64_A32
7254 CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I64_A32_S
7255 CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I64_A64
7256 CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I64_A64_S
7257 CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I32_A32
7258 CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I32_A32_S
7259 CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I32_A64
7260 CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I32_A64_S
7261 CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I64_A32
7262 CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I64_A32_S
7263 CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I64_A64
7264 CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I64_A64_S
7265 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I32_A32
7266 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I32_A32_S
7267 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I32_A64
7268 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I32_A64_S
7269 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I64_A32
7270 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I64_A32_S
7271 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I64_A64
7272 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I64_A64_S
7273 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I32_A32
7274 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I32_A32_S
7275 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I32_A64
7276 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I32_A64_S
7277 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I64_A32
7278 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I64_A32_S
7279 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I64_A64
7280 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I64_A64_S
7281 CEFBS_HasAtomics, // ATOMIC_RMW32_U_ADD_I64_A32
7282 CEFBS_HasAtomics, // ATOMIC_RMW32_U_ADD_I64_A32_S
7283 CEFBS_HasAtomics, // ATOMIC_RMW32_U_ADD_I64_A64
7284 CEFBS_HasAtomics, // ATOMIC_RMW32_U_ADD_I64_A64_S
7285 CEFBS_HasAtomics, // ATOMIC_RMW32_U_AND_I64_A32
7286 CEFBS_HasAtomics, // ATOMIC_RMW32_U_AND_I64_A32_S
7287 CEFBS_HasAtomics, // ATOMIC_RMW32_U_AND_I64_A64
7288 CEFBS_HasAtomics, // ATOMIC_RMW32_U_AND_I64_A64_S
7289 CEFBS_HasAtomics, // ATOMIC_RMW32_U_CMPXCHG_I64_A32
7290 CEFBS_HasAtomics, // ATOMIC_RMW32_U_CMPXCHG_I64_A32_S
7291 CEFBS_HasAtomics, // ATOMIC_RMW32_U_CMPXCHG_I64_A64
7292 CEFBS_HasAtomics, // ATOMIC_RMW32_U_CMPXCHG_I64_A64_S
7293 CEFBS_HasAtomics, // ATOMIC_RMW32_U_OR_I64_A32
7294 CEFBS_HasAtomics, // ATOMIC_RMW32_U_OR_I64_A32_S
7295 CEFBS_HasAtomics, // ATOMIC_RMW32_U_OR_I64_A64
7296 CEFBS_HasAtomics, // ATOMIC_RMW32_U_OR_I64_A64_S
7297 CEFBS_HasAtomics, // ATOMIC_RMW32_U_SUB_I64_A32
7298 CEFBS_HasAtomics, // ATOMIC_RMW32_U_SUB_I64_A32_S
7299 CEFBS_HasAtomics, // ATOMIC_RMW32_U_SUB_I64_A64
7300 CEFBS_HasAtomics, // ATOMIC_RMW32_U_SUB_I64_A64_S
7301 CEFBS_HasAtomics, // ATOMIC_RMW32_U_XCHG_I64_A32
7302 CEFBS_HasAtomics, // ATOMIC_RMW32_U_XCHG_I64_A32_S
7303 CEFBS_HasAtomics, // ATOMIC_RMW32_U_XCHG_I64_A64
7304 CEFBS_HasAtomics, // ATOMIC_RMW32_U_XCHG_I64_A64_S
7305 CEFBS_HasAtomics, // ATOMIC_RMW32_U_XOR_I64_A32
7306 CEFBS_HasAtomics, // ATOMIC_RMW32_U_XOR_I64_A32_S
7307 CEFBS_HasAtomics, // ATOMIC_RMW32_U_XOR_I64_A64
7308 CEFBS_HasAtomics, // ATOMIC_RMW32_U_XOR_I64_A64_S
7309 CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I32_A32
7310 CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I32_A32_S
7311 CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I32_A64
7312 CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I32_A64_S
7313 CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I64_A32
7314 CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I64_A32_S
7315 CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I64_A64
7316 CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I64_A64_S
7317 CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I32_A32
7318 CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I32_A32_S
7319 CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I32_A64
7320 CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I32_A64_S
7321 CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I64_A32
7322 CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I64_A32_S
7323 CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I64_A64
7324 CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I64_A64_S
7325 CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I32_A32
7326 CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I32_A32_S
7327 CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I32_A64
7328 CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I32_A64_S
7329 CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I64_A32
7330 CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I64_A32_S
7331 CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I64_A64
7332 CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I64_A64_S
7333 CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I32_A32
7334 CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I32_A32_S
7335 CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I32_A64
7336 CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I32_A64_S
7337 CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I64_A32
7338 CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I64_A32_S
7339 CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I64_A64
7340 CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I64_A64_S
7341 CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I32_A32
7342 CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I32_A32_S
7343 CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I32_A64
7344 CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I32_A64_S
7345 CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I64_A32
7346 CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I64_A32_S
7347 CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I64_A64
7348 CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I64_A64_S
7349 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I32_A32
7350 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I32_A32_S
7351 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I32_A64
7352 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I32_A64_S
7353 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I64_A32
7354 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I64_A32_S
7355 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I64_A64
7356 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I64_A64_S
7357 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I32_A32
7358 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I32_A32_S
7359 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I32_A64
7360 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I32_A64_S
7361 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I64_A32
7362 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I64_A32_S
7363 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I64_A64
7364 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I64_A64_S
7365 CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I32_A32
7366 CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I32_A32_S
7367 CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I32_A64
7368 CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I32_A64_S
7369 CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I64_A32
7370 CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I64_A32_S
7371 CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I64_A64
7372 CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I64_A64_S
7373 CEFBS_HasAtomics, // ATOMIC_RMW_AND_I32_A32
7374 CEFBS_HasAtomics, // ATOMIC_RMW_AND_I32_A32_S
7375 CEFBS_HasAtomics, // ATOMIC_RMW_AND_I32_A64
7376 CEFBS_HasAtomics, // ATOMIC_RMW_AND_I32_A64_S
7377 CEFBS_HasAtomics, // ATOMIC_RMW_AND_I64_A32
7378 CEFBS_HasAtomics, // ATOMIC_RMW_AND_I64_A32_S
7379 CEFBS_HasAtomics, // ATOMIC_RMW_AND_I64_A64
7380 CEFBS_HasAtomics, // ATOMIC_RMW_AND_I64_A64_S
7381 CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I32_A32
7382 CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I32_A32_S
7383 CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I32_A64
7384 CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I32_A64_S
7385 CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I64_A32
7386 CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I64_A32_S
7387 CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I64_A64
7388 CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I64_A64_S
7389 CEFBS_HasAtomics, // ATOMIC_RMW_OR_I32_A32
7390 CEFBS_HasAtomics, // ATOMIC_RMW_OR_I32_A32_S
7391 CEFBS_HasAtomics, // ATOMIC_RMW_OR_I32_A64
7392 CEFBS_HasAtomics, // ATOMIC_RMW_OR_I32_A64_S
7393 CEFBS_HasAtomics, // ATOMIC_RMW_OR_I64_A32
7394 CEFBS_HasAtomics, // ATOMIC_RMW_OR_I64_A32_S
7395 CEFBS_HasAtomics, // ATOMIC_RMW_OR_I64_A64
7396 CEFBS_HasAtomics, // ATOMIC_RMW_OR_I64_A64_S
7397 CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I32_A32
7398 CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I32_A32_S
7399 CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I32_A64
7400 CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I32_A64_S
7401 CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I64_A32
7402 CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I64_A32_S
7403 CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I64_A64
7404 CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I64_A64_S
7405 CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I32_A32
7406 CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I32_A32_S
7407 CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I32_A64
7408 CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I32_A64_S
7409 CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I64_A32
7410 CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I64_A32_S
7411 CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I64_A64
7412 CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I64_A64_S
7413 CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I32_A32
7414 CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I32_A32_S
7415 CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I32_A64
7416 CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I32_A64_S
7417 CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I64_A32
7418 CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I64_A32_S
7419 CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I64_A64
7420 CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I64_A64_S
7421 CEFBS_HasAtomics, // ATOMIC_STORE16_I32_A32
7422 CEFBS_HasAtomics, // ATOMIC_STORE16_I32_A32_S
7423 CEFBS_HasAtomics, // ATOMIC_STORE16_I32_A64
7424 CEFBS_HasAtomics, // ATOMIC_STORE16_I32_A64_S
7425 CEFBS_HasAtomics, // ATOMIC_STORE16_I64_A32
7426 CEFBS_HasAtomics, // ATOMIC_STORE16_I64_A32_S
7427 CEFBS_HasAtomics, // ATOMIC_STORE16_I64_A64
7428 CEFBS_HasAtomics, // ATOMIC_STORE16_I64_A64_S
7429 CEFBS_HasAtomics, // ATOMIC_STORE32_I64_A32
7430 CEFBS_HasAtomics, // ATOMIC_STORE32_I64_A32_S
7431 CEFBS_HasAtomics, // ATOMIC_STORE32_I64_A64
7432 CEFBS_HasAtomics, // ATOMIC_STORE32_I64_A64_S
7433 CEFBS_HasAtomics, // ATOMIC_STORE8_I32_A32
7434 CEFBS_HasAtomics, // ATOMIC_STORE8_I32_A32_S
7435 CEFBS_HasAtomics, // ATOMIC_STORE8_I32_A64
7436 CEFBS_HasAtomics, // ATOMIC_STORE8_I32_A64_S
7437 CEFBS_HasAtomics, // ATOMIC_STORE8_I64_A32
7438 CEFBS_HasAtomics, // ATOMIC_STORE8_I64_A32_S
7439 CEFBS_HasAtomics, // ATOMIC_STORE8_I64_A64
7440 CEFBS_HasAtomics, // ATOMIC_STORE8_I64_A64_S
7441 CEFBS_HasAtomics, // ATOMIC_STORE_I32_A32
7442 CEFBS_HasAtomics, // ATOMIC_STORE_I32_A32_S
7443 CEFBS_HasAtomics, // ATOMIC_STORE_I32_A64
7444 CEFBS_HasAtomics, // ATOMIC_STORE_I32_A64_S
7445 CEFBS_HasAtomics, // ATOMIC_STORE_I64_A32
7446 CEFBS_HasAtomics, // ATOMIC_STORE_I64_A32_S
7447 CEFBS_HasAtomics, // ATOMIC_STORE_I64_A64
7448 CEFBS_HasAtomics, // ATOMIC_STORE_I64_A64_S
7449 CEFBS_HasSIMD128, // AVGR_U_I16x8
7450 CEFBS_HasSIMD128, // AVGR_U_I16x8_S
7451 CEFBS_HasSIMD128, // AVGR_U_I8x16
7452 CEFBS_HasSIMD128, // AVGR_U_I8x16_S
7453 CEFBS_HasSIMD128, // BITMASK_I16x8
7454 CEFBS_HasSIMD128, // BITMASK_I16x8_S
7455 CEFBS_HasSIMD128, // BITMASK_I32x4
7456 CEFBS_HasSIMD128, // BITMASK_I32x4_S
7457 CEFBS_HasSIMD128, // BITMASK_I64x2
7458 CEFBS_HasSIMD128, // BITMASK_I64x2_S
7459 CEFBS_HasSIMD128, // BITMASK_I8x16
7460 CEFBS_HasSIMD128, // BITMASK_I8x16_S
7461 CEFBS_HasSIMD128, // BITSELECT
7462 CEFBS_HasSIMD128, // BITSELECT_S
7463 CEFBS_None, // BLOCK
7464 CEFBS_None, // BLOCK_S
7465 CEFBS_None, // BR
7466 CEFBS_None, // BR_IF
7467 CEFBS_None, // BR_IF_S
7468 CEFBS_None, // BR_S
7469 CEFBS_None, // BR_TABLE_I32
7470 CEFBS_None, // BR_TABLE_I32_S
7471 CEFBS_None, // BR_TABLE_I64
7472 CEFBS_None, // BR_TABLE_I64_S
7473 CEFBS_None, // BR_UNLESS
7474 CEFBS_None, // BR_UNLESS_S
7475 CEFBS_None, // CALL
7476 CEFBS_None, // CALL_INDIRECT
7477 CEFBS_None, // CALL_INDIRECT_S
7478 CEFBS_None, // CALL_S
7479 CEFBS_HasExceptionHandling, // CATCH
7480 CEFBS_HasExceptionHandling, // CATCH_ALL
7481 CEFBS_HasExceptionHandling, // CATCH_ALL_LEGACY
7482 CEFBS_HasExceptionHandling, // CATCH_ALL_LEGACY_S
7483 CEFBS_HasExceptionHandling, // CATCH_ALL_REF
7484 CEFBS_HasExceptionHandling, // CATCH_ALL_REF_S
7485 CEFBS_HasExceptionHandling, // CATCH_ALL_S
7486 CEFBS_HasExceptionHandling, // CATCH_LEGACY
7487 CEFBS_HasExceptionHandling, // CATCH_LEGACY_S
7488 CEFBS_HasExceptionHandling, // CATCH_REF
7489 CEFBS_HasExceptionHandling, // CATCH_REF_S
7490 CEFBS_HasExceptionHandling, // CATCH_S
7491 CEFBS_HasSIMD128_HasFP16, // CEIL_F16x8
7492 CEFBS_HasSIMD128_HasFP16, // CEIL_F16x8_S
7493 CEFBS_None, // CEIL_F32
7494 CEFBS_None, // CEIL_F32_S
7495 CEFBS_HasSIMD128, // CEIL_F32x4
7496 CEFBS_HasSIMD128, // CEIL_F32x4_S
7497 CEFBS_None, // CEIL_F64
7498 CEFBS_None, // CEIL_F64_S
7499 CEFBS_HasSIMD128, // CEIL_F64x2
7500 CEFBS_HasSIMD128, // CEIL_F64x2_S
7501 CEFBS_None, // CLZ_I32
7502 CEFBS_None, // CLZ_I32_S
7503 CEFBS_None, // CLZ_I64
7504 CEFBS_None, // CLZ_I64_S
7505 CEFBS_None, // CONST_F32
7506 CEFBS_None, // CONST_F32_S
7507 CEFBS_None, // CONST_F64
7508 CEFBS_None, // CONST_F64_S
7509 CEFBS_None, // CONST_I32
7510 CEFBS_None, // CONST_I32_S
7511 CEFBS_None, // CONST_I64
7512 CEFBS_None, // CONST_I64_S
7513 CEFBS_HasSIMD128, // CONST_V128_F32x4
7514 CEFBS_HasSIMD128, // CONST_V128_F32x4_S
7515 CEFBS_HasSIMD128, // CONST_V128_F64x2
7516 CEFBS_HasSIMD128, // CONST_V128_F64x2_S
7517 CEFBS_HasSIMD128, // CONST_V128_I16x8
7518 CEFBS_HasSIMD128, // CONST_V128_I16x8_S
7519 CEFBS_HasSIMD128, // CONST_V128_I32x4
7520 CEFBS_HasSIMD128, // CONST_V128_I32x4_S
7521 CEFBS_HasSIMD128, // CONST_V128_I64x2
7522 CEFBS_HasSIMD128, // CONST_V128_I64x2_S
7523 CEFBS_HasSIMD128, // CONST_V128_I8x16
7524 CEFBS_HasSIMD128, // CONST_V128_I8x16_S
7525 CEFBS_None, // COPYSIGN_F32
7526 CEFBS_None, // COPYSIGN_F32_S
7527 CEFBS_None, // COPYSIGN_F64
7528 CEFBS_None, // COPYSIGN_F64_S
7529 CEFBS_HasReferenceTypes_HasExceptionHandling, // COPY_EXNREF
7530 CEFBS_HasReferenceTypes_HasExceptionHandling, // COPY_EXNREF_S
7531 CEFBS_HasReferenceTypes, // COPY_EXTERNREF
7532 CEFBS_HasReferenceTypes, // COPY_EXTERNREF_S
7533 CEFBS_None, // COPY_F32
7534 CEFBS_None, // COPY_F32_S
7535 CEFBS_None, // COPY_F64
7536 CEFBS_None, // COPY_F64_S
7537 CEFBS_HasReferenceTypes, // COPY_FUNCREF
7538 CEFBS_HasReferenceTypes, // COPY_FUNCREF_S
7539 CEFBS_None, // COPY_I32
7540 CEFBS_None, // COPY_I32_S
7541 CEFBS_None, // COPY_I64
7542 CEFBS_None, // COPY_I64_S
7543 CEFBS_HasSIMD128, // COPY_V128
7544 CEFBS_HasSIMD128, // COPY_V128_S
7545 CEFBS_None, // CTZ_I32
7546 CEFBS_None, // CTZ_I32_S
7547 CEFBS_None, // CTZ_I64
7548 CEFBS_None, // CTZ_I64_S
7549 CEFBS_HasBulkMemoryOpt, // DATA_DROP
7550 CEFBS_HasBulkMemoryOpt, // DATA_DROP_S
7551 CEFBS_None, // DEBUG_UNREACHABLE
7552 CEFBS_None, // DEBUG_UNREACHABLE_S
7553 CEFBS_HasExceptionHandling, // DELEGATE
7554 CEFBS_HasExceptionHandling, // DELEGATE_S
7555 CEFBS_HasSIMD128_HasFP16, // DIV_F16x8
7556 CEFBS_HasSIMD128_HasFP16, // DIV_F16x8_S
7557 CEFBS_None, // DIV_F32
7558 CEFBS_None, // DIV_F32_S
7559 CEFBS_HasSIMD128, // DIV_F32x4
7560 CEFBS_HasSIMD128, // DIV_F32x4_S
7561 CEFBS_None, // DIV_F64
7562 CEFBS_None, // DIV_F64_S
7563 CEFBS_HasSIMD128, // DIV_F64x2
7564 CEFBS_HasSIMD128, // DIV_F64x2_S
7565 CEFBS_None, // DIV_S_I32
7566 CEFBS_None, // DIV_S_I32_S
7567 CEFBS_None, // DIV_S_I64
7568 CEFBS_None, // DIV_S_I64_S
7569 CEFBS_None, // DIV_U_I32
7570 CEFBS_None, // DIV_U_I32_S
7571 CEFBS_None, // DIV_U_I64
7572 CEFBS_None, // DIV_U_I64_S
7573 CEFBS_HasSIMD128, // DOT
7574 CEFBS_HasSIMD128, // DOT_S
7575 CEFBS_HasReferenceTypes_HasExceptionHandling, // DROP_EXNREF
7576 CEFBS_HasReferenceTypes_HasExceptionHandling, // DROP_EXNREF_S
7577 CEFBS_HasReferenceTypes, // DROP_EXTERNREF
7578 CEFBS_HasReferenceTypes, // DROP_EXTERNREF_S
7579 CEFBS_None, // DROP_F32
7580 CEFBS_None, // DROP_F32_S
7581 CEFBS_None, // DROP_F64
7582 CEFBS_None, // DROP_F64_S
7583 CEFBS_HasReferenceTypes, // DROP_FUNCREF
7584 CEFBS_HasReferenceTypes, // DROP_FUNCREF_S
7585 CEFBS_None, // DROP_I32
7586 CEFBS_None, // DROP_I32_S
7587 CEFBS_None, // DROP_I64
7588 CEFBS_None, // DROP_I64_S
7589 CEFBS_HasSIMD128, // DROP_V128
7590 CEFBS_HasSIMD128, // DROP_V128_S
7591 CEFBS_None, // ELSE
7592 CEFBS_None, // ELSE_S
7593 CEFBS_None, // END
7594 CEFBS_None, // END_BLOCK
7595 CEFBS_None, // END_BLOCK_S
7596 CEFBS_None, // END_FUNCTION
7597 CEFBS_None, // END_FUNCTION_S
7598 CEFBS_None, // END_IF
7599 CEFBS_None, // END_IF_S
7600 CEFBS_None, // END_LOOP
7601 CEFBS_None, // END_LOOP_S
7602 CEFBS_None, // END_S
7603 CEFBS_HasExceptionHandling, // END_TRY
7604 CEFBS_HasExceptionHandling, // END_TRY_S
7605 CEFBS_HasExceptionHandling, // END_TRY_TABLE
7606 CEFBS_HasExceptionHandling, // END_TRY_TABLE_S
7607 CEFBS_None, // EQZ_I32
7608 CEFBS_None, // EQZ_I32_S
7609 CEFBS_None, // EQZ_I64
7610 CEFBS_None, // EQZ_I64_S
7611 CEFBS_HasSIMD128_HasFP16, // EQ_F16x8
7612 CEFBS_HasSIMD128_HasFP16, // EQ_F16x8_S
7613 CEFBS_None, // EQ_F32
7614 CEFBS_None, // EQ_F32_S
7615 CEFBS_HasSIMD128, // EQ_F32x4
7616 CEFBS_HasSIMD128, // EQ_F32x4_S
7617 CEFBS_None, // EQ_F64
7618 CEFBS_None, // EQ_F64_S
7619 CEFBS_HasSIMD128, // EQ_F64x2
7620 CEFBS_HasSIMD128, // EQ_F64x2_S
7621 CEFBS_HasSIMD128, // EQ_I16x8
7622 CEFBS_HasSIMD128, // EQ_I16x8_S
7623 CEFBS_None, // EQ_I32
7624 CEFBS_None, // EQ_I32_S
7625 CEFBS_HasSIMD128, // EQ_I32x4
7626 CEFBS_HasSIMD128, // EQ_I32x4_S
7627 CEFBS_None, // EQ_I64
7628 CEFBS_None, // EQ_I64_S
7629 CEFBS_HasSIMD128, // EQ_I64x2
7630 CEFBS_HasSIMD128, // EQ_I64x2_S
7631 CEFBS_HasSIMD128, // EQ_I8x16
7632 CEFBS_HasSIMD128, // EQ_I8x16_S
7633 CEFBS_HasSIMD128, // EXTMUL_HIGH_S_I16x8
7634 CEFBS_HasSIMD128, // EXTMUL_HIGH_S_I16x8_S
7635 CEFBS_HasSIMD128, // EXTMUL_HIGH_S_I32x4
7636 CEFBS_HasSIMD128, // EXTMUL_HIGH_S_I32x4_S
7637 CEFBS_HasSIMD128, // EXTMUL_HIGH_S_I64x2
7638 CEFBS_HasSIMD128, // EXTMUL_HIGH_S_I64x2_S
7639 CEFBS_HasSIMD128, // EXTMUL_HIGH_U_I16x8
7640 CEFBS_HasSIMD128, // EXTMUL_HIGH_U_I16x8_S
7641 CEFBS_HasSIMD128, // EXTMUL_HIGH_U_I32x4
7642 CEFBS_HasSIMD128, // EXTMUL_HIGH_U_I32x4_S
7643 CEFBS_HasSIMD128, // EXTMUL_HIGH_U_I64x2
7644 CEFBS_HasSIMD128, // EXTMUL_HIGH_U_I64x2_S
7645 CEFBS_HasSIMD128, // EXTMUL_LOW_S_I16x8
7646 CEFBS_HasSIMD128, // EXTMUL_LOW_S_I16x8_S
7647 CEFBS_HasSIMD128, // EXTMUL_LOW_S_I32x4
7648 CEFBS_HasSIMD128, // EXTMUL_LOW_S_I32x4_S
7649 CEFBS_HasSIMD128, // EXTMUL_LOW_S_I64x2
7650 CEFBS_HasSIMD128, // EXTMUL_LOW_S_I64x2_S
7651 CEFBS_HasSIMD128, // EXTMUL_LOW_U_I16x8
7652 CEFBS_HasSIMD128, // EXTMUL_LOW_U_I16x8_S
7653 CEFBS_HasSIMD128, // EXTMUL_LOW_U_I32x4
7654 CEFBS_HasSIMD128, // EXTMUL_LOW_U_I32x4_S
7655 CEFBS_HasSIMD128, // EXTMUL_LOW_U_I64x2
7656 CEFBS_HasSIMD128, // EXTMUL_LOW_U_I64x2_S
7657 CEFBS_HasFP16, // EXTRACT_LANE_F16x8
7658 CEFBS_HasFP16, // EXTRACT_LANE_F16x8_S
7659 CEFBS_HasSIMD128, // EXTRACT_LANE_F32x4
7660 CEFBS_HasSIMD128, // EXTRACT_LANE_F32x4_S
7661 CEFBS_HasSIMD128, // EXTRACT_LANE_F64x2
7662 CEFBS_HasSIMD128, // EXTRACT_LANE_F64x2_S
7663 CEFBS_HasSIMD128, // EXTRACT_LANE_I16x8_s
7664 CEFBS_HasSIMD128, // EXTRACT_LANE_I16x8_s_S
7665 CEFBS_HasSIMD128, // EXTRACT_LANE_I16x8_u
7666 CEFBS_HasSIMD128, // EXTRACT_LANE_I16x8_u_S
7667 CEFBS_HasSIMD128, // EXTRACT_LANE_I32x4
7668 CEFBS_HasSIMD128, // EXTRACT_LANE_I32x4_S
7669 CEFBS_HasSIMD128, // EXTRACT_LANE_I64x2
7670 CEFBS_HasSIMD128, // EXTRACT_LANE_I64x2_S
7671 CEFBS_HasSIMD128, // EXTRACT_LANE_I8x16_s
7672 CEFBS_HasSIMD128, // EXTRACT_LANE_I8x16_s_S
7673 CEFBS_HasSIMD128, // EXTRACT_LANE_I8x16_u
7674 CEFBS_HasSIMD128, // EXTRACT_LANE_I8x16_u_S
7675 CEFBS_None, // F32_CONVERT_S_I32
7676 CEFBS_None, // F32_CONVERT_S_I32_S
7677 CEFBS_None, // F32_CONVERT_S_I64
7678 CEFBS_None, // F32_CONVERT_S_I64_S
7679 CEFBS_None, // F32_CONVERT_U_I32
7680 CEFBS_None, // F32_CONVERT_U_I32_S
7681 CEFBS_None, // F32_CONVERT_U_I64
7682 CEFBS_None, // F32_CONVERT_U_I64_S
7683 CEFBS_None, // F32_DEMOTE_F64
7684 CEFBS_None, // F32_DEMOTE_F64_S
7685 CEFBS_None, // F32_REINTERPRET_I32
7686 CEFBS_None, // F32_REINTERPRET_I32_S
7687 CEFBS_None, // F64_CONVERT_S_I32
7688 CEFBS_None, // F64_CONVERT_S_I32_S
7689 CEFBS_None, // F64_CONVERT_S_I64
7690 CEFBS_None, // F64_CONVERT_S_I64_S
7691 CEFBS_None, // F64_CONVERT_U_I32
7692 CEFBS_None, // F64_CONVERT_U_I32_S
7693 CEFBS_None, // F64_CONVERT_U_I64
7694 CEFBS_None, // F64_CONVERT_U_I64_S
7695 CEFBS_None, // F64_PROMOTE_F32
7696 CEFBS_None, // F64_PROMOTE_F32_S
7697 CEFBS_None, // F64_REINTERPRET_I64
7698 CEFBS_None, // F64_REINTERPRET_I64_S
7699 CEFBS_None, // FALLTHROUGH_RETURN
7700 CEFBS_None, // FALLTHROUGH_RETURN_S
7701 CEFBS_HasSIMD128_HasFP16, // FLOOR_F16x8
7702 CEFBS_HasSIMD128_HasFP16, // FLOOR_F16x8_S
7703 CEFBS_None, // FLOOR_F32
7704 CEFBS_None, // FLOOR_F32_S
7705 CEFBS_HasSIMD128, // FLOOR_F32x4
7706 CEFBS_HasSIMD128, // FLOOR_F32x4_S
7707 CEFBS_None, // FLOOR_F64
7708 CEFBS_None, // FLOOR_F64_S
7709 CEFBS_HasSIMD128, // FLOOR_F64x2
7710 CEFBS_HasSIMD128, // FLOOR_F64x2_S
7711 CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I32_F32
7712 CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I32_F32_S
7713 CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I32_F64
7714 CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I32_F64_S
7715 CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I64_F32
7716 CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I64_F32_S
7717 CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I64_F64
7718 CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I64_F64_S
7719 CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I32_F32
7720 CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I32_F32_S
7721 CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I32_F64
7722 CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I32_F64_S
7723 CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I64_F32
7724 CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I64_F32_S
7725 CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I64_F64
7726 CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I64_F64_S
7727 CEFBS_HasSIMD128_HasFP16, // GE_F16x8
7728 CEFBS_HasSIMD128_HasFP16, // GE_F16x8_S
7729 CEFBS_None, // GE_F32
7730 CEFBS_None, // GE_F32_S
7731 CEFBS_HasSIMD128, // GE_F32x4
7732 CEFBS_HasSIMD128, // GE_F32x4_S
7733 CEFBS_None, // GE_F64
7734 CEFBS_None, // GE_F64_S
7735 CEFBS_HasSIMD128, // GE_F64x2
7736 CEFBS_HasSIMD128, // GE_F64x2_S
7737 CEFBS_HasSIMD128, // GE_S_I16x8
7738 CEFBS_HasSIMD128, // GE_S_I16x8_S
7739 CEFBS_None, // GE_S_I32
7740 CEFBS_None, // GE_S_I32_S
7741 CEFBS_HasSIMD128, // GE_S_I32x4
7742 CEFBS_HasSIMD128, // GE_S_I32x4_S
7743 CEFBS_None, // GE_S_I64
7744 CEFBS_None, // GE_S_I64_S
7745 CEFBS_HasSIMD128, // GE_S_I64x2
7746 CEFBS_HasSIMD128, // GE_S_I64x2_S
7747 CEFBS_HasSIMD128, // GE_S_I8x16
7748 CEFBS_HasSIMD128, // GE_S_I8x16_S
7749 CEFBS_HasSIMD128, // GE_U_I16x8
7750 CEFBS_HasSIMD128, // GE_U_I16x8_S
7751 CEFBS_None, // GE_U_I32
7752 CEFBS_None, // GE_U_I32_S
7753 CEFBS_HasSIMD128, // GE_U_I32x4
7754 CEFBS_HasSIMD128, // GE_U_I32x4_S
7755 CEFBS_None, // GE_U_I64
7756 CEFBS_None, // GE_U_I64_S
7757 CEFBS_HasSIMD128, // GE_U_I8x16
7758 CEFBS_HasSIMD128, // GE_U_I8x16_S
7759 CEFBS_HasReferenceTypes_HasExceptionHandling, // GLOBAL_GET_EXNREF
7760 CEFBS_HasReferenceTypes_HasExceptionHandling, // GLOBAL_GET_EXNREF_S
7761 CEFBS_HasReferenceTypes, // GLOBAL_GET_EXTERNREF
7762 CEFBS_HasReferenceTypes, // GLOBAL_GET_EXTERNREF_S
7763 CEFBS_None, // GLOBAL_GET_F32
7764 CEFBS_None, // GLOBAL_GET_F32_S
7765 CEFBS_None, // GLOBAL_GET_F64
7766 CEFBS_None, // GLOBAL_GET_F64_S
7767 CEFBS_HasReferenceTypes, // GLOBAL_GET_FUNCREF
7768 CEFBS_HasReferenceTypes, // GLOBAL_GET_FUNCREF_S
7769 CEFBS_None, // GLOBAL_GET_I32
7770 CEFBS_None, // GLOBAL_GET_I32_S
7771 CEFBS_None, // GLOBAL_GET_I64
7772 CEFBS_None, // GLOBAL_GET_I64_S
7773 CEFBS_HasSIMD128, // GLOBAL_GET_V128
7774 CEFBS_HasSIMD128, // GLOBAL_GET_V128_S
7775 CEFBS_HasReferenceTypes_HasExceptionHandling, // GLOBAL_SET_EXNREF
7776 CEFBS_HasReferenceTypes_HasExceptionHandling, // GLOBAL_SET_EXNREF_S
7777 CEFBS_HasReferenceTypes, // GLOBAL_SET_EXTERNREF
7778 CEFBS_HasReferenceTypes, // GLOBAL_SET_EXTERNREF_S
7779 CEFBS_None, // GLOBAL_SET_F32
7780 CEFBS_None, // GLOBAL_SET_F32_S
7781 CEFBS_None, // GLOBAL_SET_F64
7782 CEFBS_None, // GLOBAL_SET_F64_S
7783 CEFBS_HasReferenceTypes, // GLOBAL_SET_FUNCREF
7784 CEFBS_HasReferenceTypes, // GLOBAL_SET_FUNCREF_S
7785 CEFBS_None, // GLOBAL_SET_I32
7786 CEFBS_None, // GLOBAL_SET_I32_S
7787 CEFBS_None, // GLOBAL_SET_I64
7788 CEFBS_None, // GLOBAL_SET_I64_S
7789 CEFBS_HasSIMD128, // GLOBAL_SET_V128
7790 CEFBS_HasSIMD128, // GLOBAL_SET_V128_S
7791 CEFBS_HasSIMD128_HasFP16, // GT_F16x8
7792 CEFBS_HasSIMD128_HasFP16, // GT_F16x8_S
7793 CEFBS_None, // GT_F32
7794 CEFBS_None, // GT_F32_S
7795 CEFBS_HasSIMD128, // GT_F32x4
7796 CEFBS_HasSIMD128, // GT_F32x4_S
7797 CEFBS_None, // GT_F64
7798 CEFBS_None, // GT_F64_S
7799 CEFBS_HasSIMD128, // GT_F64x2
7800 CEFBS_HasSIMD128, // GT_F64x2_S
7801 CEFBS_HasSIMD128, // GT_S_I16x8
7802 CEFBS_HasSIMD128, // GT_S_I16x8_S
7803 CEFBS_None, // GT_S_I32
7804 CEFBS_None, // GT_S_I32_S
7805 CEFBS_HasSIMD128, // GT_S_I32x4
7806 CEFBS_HasSIMD128, // GT_S_I32x4_S
7807 CEFBS_None, // GT_S_I64
7808 CEFBS_None, // GT_S_I64_S
7809 CEFBS_HasSIMD128, // GT_S_I64x2
7810 CEFBS_HasSIMD128, // GT_S_I64x2_S
7811 CEFBS_HasSIMD128, // GT_S_I8x16
7812 CEFBS_HasSIMD128, // GT_S_I8x16_S
7813 CEFBS_HasSIMD128, // GT_U_I16x8
7814 CEFBS_HasSIMD128, // GT_U_I16x8_S
7815 CEFBS_None, // GT_U_I32
7816 CEFBS_None, // GT_U_I32_S
7817 CEFBS_HasSIMD128, // GT_U_I32x4
7818 CEFBS_HasSIMD128, // GT_U_I32x4_S
7819 CEFBS_None, // GT_U_I64
7820 CEFBS_None, // GT_U_I64_S
7821 CEFBS_HasSIMD128, // GT_U_I8x16
7822 CEFBS_HasSIMD128, // GT_U_I8x16_S
7823 CEFBS_HasSignExt, // I32_EXTEND16_S_I32
7824 CEFBS_HasSignExt, // I32_EXTEND16_S_I32_S
7825 CEFBS_HasSignExt, // I32_EXTEND8_S_I32
7826 CEFBS_HasSignExt, // I32_EXTEND8_S_I32_S
7827 CEFBS_None, // I32_REINTERPRET_F32
7828 CEFBS_None, // I32_REINTERPRET_F32_S
7829 CEFBS_None, // I32_TRUNC_S_F32
7830 CEFBS_None, // I32_TRUNC_S_F32_S
7831 CEFBS_None, // I32_TRUNC_S_F64
7832 CEFBS_None, // I32_TRUNC_S_F64_S
7833 CEFBS_HasNontrappingFPToInt, // I32_TRUNC_S_SAT_F32
7834 CEFBS_HasNontrappingFPToInt, // I32_TRUNC_S_SAT_F32_S
7835 CEFBS_HasNontrappingFPToInt, // I32_TRUNC_S_SAT_F64
7836 CEFBS_HasNontrappingFPToInt, // I32_TRUNC_S_SAT_F64_S
7837 CEFBS_None, // I32_TRUNC_U_F32
7838 CEFBS_None, // I32_TRUNC_U_F32_S
7839 CEFBS_None, // I32_TRUNC_U_F64
7840 CEFBS_None, // I32_TRUNC_U_F64_S
7841 CEFBS_HasNontrappingFPToInt, // I32_TRUNC_U_SAT_F32
7842 CEFBS_HasNontrappingFPToInt, // I32_TRUNC_U_SAT_F32_S
7843 CEFBS_HasNontrappingFPToInt, // I32_TRUNC_U_SAT_F64
7844 CEFBS_HasNontrappingFPToInt, // I32_TRUNC_U_SAT_F64_S
7845 CEFBS_None, // I32_WRAP_I64
7846 CEFBS_None, // I32_WRAP_I64_S
7847 CEFBS_HasWideArithmetic, // I64_ADD128
7848 CEFBS_HasWideArithmetic, // I64_ADD128_S
7849 CEFBS_HasSignExt, // I64_EXTEND16_S_I64
7850 CEFBS_HasSignExt, // I64_EXTEND16_S_I64_S
7851 CEFBS_HasSignExt, // I64_EXTEND32_S_I64
7852 CEFBS_HasSignExt, // I64_EXTEND32_S_I64_S
7853 CEFBS_HasSignExt, // I64_EXTEND8_S_I64
7854 CEFBS_HasSignExt, // I64_EXTEND8_S_I64_S
7855 CEFBS_None, // I64_EXTEND_S_I32
7856 CEFBS_None, // I64_EXTEND_S_I32_S
7857 CEFBS_None, // I64_EXTEND_U_I32
7858 CEFBS_None, // I64_EXTEND_U_I32_S
7859 CEFBS_HasWideArithmetic, // I64_MUL_WIDE_S
7860 CEFBS_HasWideArithmetic, // I64_MUL_WIDE_S_S
7861 CEFBS_HasWideArithmetic, // I64_MUL_WIDE_U
7862 CEFBS_HasWideArithmetic, // I64_MUL_WIDE_U_S
7863 CEFBS_None, // I64_REINTERPRET_F64
7864 CEFBS_None, // I64_REINTERPRET_F64_S
7865 CEFBS_HasWideArithmetic, // I64_SUB128
7866 CEFBS_HasWideArithmetic, // I64_SUB128_S
7867 CEFBS_None, // I64_TRUNC_S_F32
7868 CEFBS_None, // I64_TRUNC_S_F32_S
7869 CEFBS_None, // I64_TRUNC_S_F64
7870 CEFBS_None, // I64_TRUNC_S_F64_S
7871 CEFBS_HasNontrappingFPToInt, // I64_TRUNC_S_SAT_F32
7872 CEFBS_HasNontrappingFPToInt, // I64_TRUNC_S_SAT_F32_S
7873 CEFBS_HasNontrappingFPToInt, // I64_TRUNC_S_SAT_F64
7874 CEFBS_HasNontrappingFPToInt, // I64_TRUNC_S_SAT_F64_S
7875 CEFBS_None, // I64_TRUNC_U_F32
7876 CEFBS_None, // I64_TRUNC_U_F32_S
7877 CEFBS_None, // I64_TRUNC_U_F64
7878 CEFBS_None, // I64_TRUNC_U_F64_S
7879 CEFBS_HasNontrappingFPToInt, // I64_TRUNC_U_SAT_F32
7880 CEFBS_HasNontrappingFPToInt, // I64_TRUNC_U_SAT_F32_S
7881 CEFBS_HasNontrappingFPToInt, // I64_TRUNC_U_SAT_F64
7882 CEFBS_HasNontrappingFPToInt, // I64_TRUNC_U_SAT_F64_S
7883 CEFBS_None, // IF
7884 CEFBS_None, // IF_S
7885 CEFBS_HasRelaxedSIMD, // LANESELECT_I16x8
7886 CEFBS_HasRelaxedSIMD, // LANESELECT_I16x8_S
7887 CEFBS_HasRelaxedSIMD, // LANESELECT_I32x4
7888 CEFBS_HasRelaxedSIMD, // LANESELECT_I32x4_S
7889 CEFBS_HasRelaxedSIMD, // LANESELECT_I64x2
7890 CEFBS_HasRelaxedSIMD, // LANESELECT_I64x2_S
7891 CEFBS_HasRelaxedSIMD, // LANESELECT_I8x16
7892 CEFBS_HasRelaxedSIMD, // LANESELECT_I8x16_S
7893 CEFBS_HasSIMD128_HasFP16, // LE_F16x8
7894 CEFBS_HasSIMD128_HasFP16, // LE_F16x8_S
7895 CEFBS_None, // LE_F32
7896 CEFBS_None, // LE_F32_S
7897 CEFBS_HasSIMD128, // LE_F32x4
7898 CEFBS_HasSIMD128, // LE_F32x4_S
7899 CEFBS_None, // LE_F64
7900 CEFBS_None, // LE_F64_S
7901 CEFBS_HasSIMD128, // LE_F64x2
7902 CEFBS_HasSIMD128, // LE_F64x2_S
7903 CEFBS_HasSIMD128, // LE_S_I16x8
7904 CEFBS_HasSIMD128, // LE_S_I16x8_S
7905 CEFBS_None, // LE_S_I32
7906 CEFBS_None, // LE_S_I32_S
7907 CEFBS_HasSIMD128, // LE_S_I32x4
7908 CEFBS_HasSIMD128, // LE_S_I32x4_S
7909 CEFBS_None, // LE_S_I64
7910 CEFBS_None, // LE_S_I64_S
7911 CEFBS_HasSIMD128, // LE_S_I64x2
7912 CEFBS_HasSIMD128, // LE_S_I64x2_S
7913 CEFBS_HasSIMD128, // LE_S_I8x16
7914 CEFBS_HasSIMD128, // LE_S_I8x16_S
7915 CEFBS_HasSIMD128, // LE_U_I16x8
7916 CEFBS_HasSIMD128, // LE_U_I16x8_S
7917 CEFBS_None, // LE_U_I32
7918 CEFBS_None, // LE_U_I32_S
7919 CEFBS_HasSIMD128, // LE_U_I32x4
7920 CEFBS_HasSIMD128, // LE_U_I32x4_S
7921 CEFBS_None, // LE_U_I64
7922 CEFBS_None, // LE_U_I64_S
7923 CEFBS_HasSIMD128, // LE_U_I8x16
7924 CEFBS_HasSIMD128, // LE_U_I8x16_S
7925 CEFBS_HasSIMD128, // LOAD16_SPLAT_A32
7926 CEFBS_HasSIMD128, // LOAD16_SPLAT_A32_S
7927 CEFBS_HasSIMD128, // LOAD16_SPLAT_A64
7928 CEFBS_HasSIMD128, // LOAD16_SPLAT_A64_S
7929 CEFBS_None, // LOAD16_S_I32_A32
7930 CEFBS_None, // LOAD16_S_I32_A32_S
7931 CEFBS_None, // LOAD16_S_I32_A64
7932 CEFBS_None, // LOAD16_S_I32_A64_S
7933 CEFBS_None, // LOAD16_S_I64_A32
7934 CEFBS_None, // LOAD16_S_I64_A32_S
7935 CEFBS_None, // LOAD16_S_I64_A64
7936 CEFBS_None, // LOAD16_S_I64_A64_S
7937 CEFBS_None, // LOAD16_U_I32_A32
7938 CEFBS_None, // LOAD16_U_I32_A32_S
7939 CEFBS_None, // LOAD16_U_I32_A64
7940 CEFBS_None, // LOAD16_U_I32_A64_S
7941 CEFBS_None, // LOAD16_U_I64_A32
7942 CEFBS_None, // LOAD16_U_I64_A32_S
7943 CEFBS_None, // LOAD16_U_I64_A64
7944 CEFBS_None, // LOAD16_U_I64_A64_S
7945 CEFBS_HasSIMD128, // LOAD32_SPLAT_A32
7946 CEFBS_HasSIMD128, // LOAD32_SPLAT_A32_S
7947 CEFBS_HasSIMD128, // LOAD32_SPLAT_A64
7948 CEFBS_HasSIMD128, // LOAD32_SPLAT_A64_S
7949 CEFBS_None, // LOAD32_S_I64_A32
7950 CEFBS_None, // LOAD32_S_I64_A32_S
7951 CEFBS_None, // LOAD32_S_I64_A64
7952 CEFBS_None, // LOAD32_S_I64_A64_S
7953 CEFBS_None, // LOAD32_U_I64_A32
7954 CEFBS_None, // LOAD32_U_I64_A32_S
7955 CEFBS_None, // LOAD32_U_I64_A64
7956 CEFBS_None, // LOAD32_U_I64_A64_S
7957 CEFBS_HasSIMD128, // LOAD64_SPLAT_A32
7958 CEFBS_HasSIMD128, // LOAD64_SPLAT_A32_S
7959 CEFBS_HasSIMD128, // LOAD64_SPLAT_A64
7960 CEFBS_HasSIMD128, // LOAD64_SPLAT_A64_S
7961 CEFBS_HasSIMD128, // LOAD8_SPLAT_A32
7962 CEFBS_HasSIMD128, // LOAD8_SPLAT_A32_S
7963 CEFBS_HasSIMD128, // LOAD8_SPLAT_A64
7964 CEFBS_HasSIMD128, // LOAD8_SPLAT_A64_S
7965 CEFBS_None, // LOAD8_S_I32_A32
7966 CEFBS_None, // LOAD8_S_I32_A32_S
7967 CEFBS_None, // LOAD8_S_I32_A64
7968 CEFBS_None, // LOAD8_S_I32_A64_S
7969 CEFBS_None, // LOAD8_S_I64_A32
7970 CEFBS_None, // LOAD8_S_I64_A32_S
7971 CEFBS_None, // LOAD8_S_I64_A64
7972 CEFBS_None, // LOAD8_S_I64_A64_S
7973 CEFBS_None, // LOAD8_U_I32_A32
7974 CEFBS_None, // LOAD8_U_I32_A32_S
7975 CEFBS_None, // LOAD8_U_I32_A64
7976 CEFBS_None, // LOAD8_U_I32_A64_S
7977 CEFBS_None, // LOAD8_U_I64_A32
7978 CEFBS_None, // LOAD8_U_I64_A32_S
7979 CEFBS_None, // LOAD8_U_I64_A64
7980 CEFBS_None, // LOAD8_U_I64_A64_S
7981 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I16x8_A32
7982 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I16x8_A32_S
7983 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I16x8_A64
7984 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I16x8_A64_S
7985 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I32x4_A32
7986 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I32x4_A32_S
7987 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I32x4_A64
7988 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I32x4_A64_S
7989 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I64x2_A32
7990 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I64x2_A32_S
7991 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I64x2_A64
7992 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I64x2_A64_S
7993 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I16x8_A32
7994 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I16x8_A32_S
7995 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I16x8_A64
7996 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I16x8_A64_S
7997 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I32x4_A32
7998 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I32x4_A32_S
7999 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I32x4_A64
8000 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I32x4_A64_S
8001 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I64x2_A32
8002 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I64x2_A32_S
8003 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I64x2_A64
8004 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I64x2_A64_S
8005 CEFBS_HasFP16, // LOAD_F16_F32_A32
8006 CEFBS_HasFP16, // LOAD_F16_F32_A32_S
8007 CEFBS_HasFP16, // LOAD_F16_F32_A64
8008 CEFBS_HasFP16, // LOAD_F16_F32_A64_S
8009 CEFBS_None, // LOAD_F32_A32
8010 CEFBS_None, // LOAD_F32_A32_S
8011 CEFBS_None, // LOAD_F32_A64
8012 CEFBS_None, // LOAD_F32_A64_S
8013 CEFBS_None, // LOAD_F64_A32
8014 CEFBS_None, // LOAD_F64_A32_S
8015 CEFBS_None, // LOAD_F64_A64
8016 CEFBS_None, // LOAD_F64_A64_S
8017 CEFBS_None, // LOAD_I32_A32
8018 CEFBS_None, // LOAD_I32_A32_S
8019 CEFBS_None, // LOAD_I32_A64
8020 CEFBS_None, // LOAD_I32_A64_S
8021 CEFBS_None, // LOAD_I64_A32
8022 CEFBS_None, // LOAD_I64_A32_S
8023 CEFBS_None, // LOAD_I64_A64
8024 CEFBS_None, // LOAD_I64_A64_S
8025 CEFBS_HasSIMD128, // LOAD_LANE_16_A32
8026 CEFBS_HasSIMD128, // LOAD_LANE_16_A32_S
8027 CEFBS_HasSIMD128, // LOAD_LANE_16_A64
8028 CEFBS_HasSIMD128, // LOAD_LANE_16_A64_S
8029 CEFBS_HasSIMD128, // LOAD_LANE_32_A32
8030 CEFBS_HasSIMD128, // LOAD_LANE_32_A32_S
8031 CEFBS_HasSIMD128, // LOAD_LANE_32_A64
8032 CEFBS_HasSIMD128, // LOAD_LANE_32_A64_S
8033 CEFBS_HasSIMD128, // LOAD_LANE_64_A32
8034 CEFBS_HasSIMD128, // LOAD_LANE_64_A32_S
8035 CEFBS_HasSIMD128, // LOAD_LANE_64_A64
8036 CEFBS_HasSIMD128, // LOAD_LANE_64_A64_S
8037 CEFBS_HasSIMD128, // LOAD_LANE_8_A32
8038 CEFBS_HasSIMD128, // LOAD_LANE_8_A32_S
8039 CEFBS_HasSIMD128, // LOAD_LANE_8_A64
8040 CEFBS_HasSIMD128, // LOAD_LANE_8_A64_S
8041 CEFBS_HasSIMD128, // LOAD_V128_A32
8042 CEFBS_HasSIMD128, // LOAD_V128_A32_S
8043 CEFBS_HasSIMD128, // LOAD_V128_A64
8044 CEFBS_HasSIMD128, // LOAD_V128_A64_S
8045 CEFBS_HasSIMD128, // LOAD_ZERO_32_A32
8046 CEFBS_HasSIMD128, // LOAD_ZERO_32_A32_S
8047 CEFBS_HasSIMD128, // LOAD_ZERO_32_A64
8048 CEFBS_HasSIMD128, // LOAD_ZERO_32_A64_S
8049 CEFBS_HasSIMD128, // LOAD_ZERO_64_A32
8050 CEFBS_HasSIMD128, // LOAD_ZERO_64_A32_S
8051 CEFBS_HasSIMD128, // LOAD_ZERO_64_A64
8052 CEFBS_HasSIMD128, // LOAD_ZERO_64_A64_S
8053 CEFBS_HasReferenceTypes_HasExceptionHandling, // LOCAL_GET_EXNREF
8054 CEFBS_HasReferenceTypes_HasExceptionHandling, // LOCAL_GET_EXNREF_S
8055 CEFBS_HasReferenceTypes, // LOCAL_GET_EXTERNREF
8056 CEFBS_HasReferenceTypes, // LOCAL_GET_EXTERNREF_S
8057 CEFBS_None, // LOCAL_GET_F32
8058 CEFBS_None, // LOCAL_GET_F32_S
8059 CEFBS_None, // LOCAL_GET_F64
8060 CEFBS_None, // LOCAL_GET_F64_S
8061 CEFBS_HasReferenceTypes, // LOCAL_GET_FUNCREF
8062 CEFBS_HasReferenceTypes, // LOCAL_GET_FUNCREF_S
8063 CEFBS_None, // LOCAL_GET_I32
8064 CEFBS_None, // LOCAL_GET_I32_S
8065 CEFBS_None, // LOCAL_GET_I64
8066 CEFBS_None, // LOCAL_GET_I64_S
8067 CEFBS_HasSIMD128, // LOCAL_GET_V128
8068 CEFBS_HasSIMD128, // LOCAL_GET_V128_S
8069 CEFBS_HasReferenceTypes_HasExceptionHandling, // LOCAL_SET_EXNREF
8070 CEFBS_HasReferenceTypes_HasExceptionHandling, // LOCAL_SET_EXNREF_S
8071 CEFBS_HasReferenceTypes, // LOCAL_SET_EXTERNREF
8072 CEFBS_HasReferenceTypes, // LOCAL_SET_EXTERNREF_S
8073 CEFBS_None, // LOCAL_SET_F32
8074 CEFBS_None, // LOCAL_SET_F32_S
8075 CEFBS_None, // LOCAL_SET_F64
8076 CEFBS_None, // LOCAL_SET_F64_S
8077 CEFBS_HasReferenceTypes, // LOCAL_SET_FUNCREF
8078 CEFBS_HasReferenceTypes, // LOCAL_SET_FUNCREF_S
8079 CEFBS_None, // LOCAL_SET_I32
8080 CEFBS_None, // LOCAL_SET_I32_S
8081 CEFBS_None, // LOCAL_SET_I64
8082 CEFBS_None, // LOCAL_SET_I64_S
8083 CEFBS_HasSIMD128, // LOCAL_SET_V128
8084 CEFBS_HasSIMD128, // LOCAL_SET_V128_S
8085 CEFBS_HasReferenceTypes_HasExceptionHandling, // LOCAL_TEE_EXNREF
8086 CEFBS_HasReferenceTypes_HasExceptionHandling, // LOCAL_TEE_EXNREF_S
8087 CEFBS_HasReferenceTypes, // LOCAL_TEE_EXTERNREF
8088 CEFBS_HasReferenceTypes, // LOCAL_TEE_EXTERNREF_S
8089 CEFBS_None, // LOCAL_TEE_F32
8090 CEFBS_None, // LOCAL_TEE_F32_S
8091 CEFBS_None, // LOCAL_TEE_F64
8092 CEFBS_None, // LOCAL_TEE_F64_S
8093 CEFBS_HasReferenceTypes, // LOCAL_TEE_FUNCREF
8094 CEFBS_HasReferenceTypes, // LOCAL_TEE_FUNCREF_S
8095 CEFBS_None, // LOCAL_TEE_I32
8096 CEFBS_None, // LOCAL_TEE_I32_S
8097 CEFBS_None, // LOCAL_TEE_I64
8098 CEFBS_None, // LOCAL_TEE_I64_S
8099 CEFBS_HasSIMD128, // LOCAL_TEE_V128
8100 CEFBS_HasSIMD128, // LOCAL_TEE_V128_S
8101 CEFBS_None, // LOOP
8102 CEFBS_None, // LOOP_S
8103 CEFBS_HasSIMD128_HasFP16, // LT_F16x8
8104 CEFBS_HasSIMD128_HasFP16, // LT_F16x8_S
8105 CEFBS_None, // LT_F32
8106 CEFBS_None, // LT_F32_S
8107 CEFBS_HasSIMD128, // LT_F32x4
8108 CEFBS_HasSIMD128, // LT_F32x4_S
8109 CEFBS_None, // LT_F64
8110 CEFBS_None, // LT_F64_S
8111 CEFBS_HasSIMD128, // LT_F64x2
8112 CEFBS_HasSIMD128, // LT_F64x2_S
8113 CEFBS_HasSIMD128, // LT_S_I16x8
8114 CEFBS_HasSIMD128, // LT_S_I16x8_S
8115 CEFBS_None, // LT_S_I32
8116 CEFBS_None, // LT_S_I32_S
8117 CEFBS_HasSIMD128, // LT_S_I32x4
8118 CEFBS_HasSIMD128, // LT_S_I32x4_S
8119 CEFBS_None, // LT_S_I64
8120 CEFBS_None, // LT_S_I64_S
8121 CEFBS_HasSIMD128, // LT_S_I64x2
8122 CEFBS_HasSIMD128, // LT_S_I64x2_S
8123 CEFBS_HasSIMD128, // LT_S_I8x16
8124 CEFBS_HasSIMD128, // LT_S_I8x16_S
8125 CEFBS_HasSIMD128, // LT_U_I16x8
8126 CEFBS_HasSIMD128, // LT_U_I16x8_S
8127 CEFBS_None, // LT_U_I32
8128 CEFBS_None, // LT_U_I32_S
8129 CEFBS_HasSIMD128, // LT_U_I32x4
8130 CEFBS_HasSIMD128, // LT_U_I32x4_S
8131 CEFBS_None, // LT_U_I64
8132 CEFBS_None, // LT_U_I64_S
8133 CEFBS_HasSIMD128, // LT_U_I8x16
8134 CEFBS_HasSIMD128, // LT_U_I8x16_S
8135 CEFBS_HasSIMD128_HasFP16, // MADD_F16x8
8136 CEFBS_HasSIMD128_HasFP16, // MADD_F16x8_S
8137 CEFBS_HasSIMD128_HasRelaxedSIMD, // MADD_F32x4
8138 CEFBS_HasSIMD128_HasRelaxedSIMD, // MADD_F32x4_S
8139 CEFBS_HasSIMD128_HasRelaxedSIMD, // MADD_F64x2
8140 CEFBS_HasSIMD128_HasRelaxedSIMD, // MADD_F64x2_S
8141 CEFBS_HasSIMD128_HasFP16, // MAX_F16x8
8142 CEFBS_HasSIMD128_HasFP16, // MAX_F16x8_S
8143 CEFBS_None, // MAX_F32
8144 CEFBS_None, // MAX_F32_S
8145 CEFBS_HasSIMD128, // MAX_F32x4
8146 CEFBS_HasSIMD128, // MAX_F32x4_S
8147 CEFBS_None, // MAX_F64
8148 CEFBS_None, // MAX_F64_S
8149 CEFBS_HasSIMD128, // MAX_F64x2
8150 CEFBS_HasSIMD128, // MAX_F64x2_S
8151 CEFBS_HasSIMD128, // MAX_S_I16x8
8152 CEFBS_HasSIMD128, // MAX_S_I16x8_S
8153 CEFBS_HasSIMD128, // MAX_S_I32x4
8154 CEFBS_HasSIMD128, // MAX_S_I32x4_S
8155 CEFBS_HasSIMD128, // MAX_S_I8x16
8156 CEFBS_HasSIMD128, // MAX_S_I8x16_S
8157 CEFBS_HasSIMD128, // MAX_U_I16x8
8158 CEFBS_HasSIMD128, // MAX_U_I16x8_S
8159 CEFBS_HasSIMD128, // MAX_U_I32x4
8160 CEFBS_HasSIMD128, // MAX_U_I32x4_S
8161 CEFBS_HasSIMD128, // MAX_U_I8x16
8162 CEFBS_HasSIMD128, // MAX_U_I8x16_S
8163 CEFBS_HasBulkMemoryOpt, // MEMCPY_A32
8164 CEFBS_HasBulkMemoryOpt, // MEMCPY_A32_S
8165 CEFBS_HasBulkMemoryOpt, // MEMCPY_A64
8166 CEFBS_HasBulkMemoryOpt, // MEMCPY_A64_S
8167 CEFBS_HasAtomics, // MEMORY_ATOMIC_NOTIFY_A32
8168 CEFBS_HasAtomics, // MEMORY_ATOMIC_NOTIFY_A32_S
8169 CEFBS_HasAtomics, // MEMORY_ATOMIC_NOTIFY_A64
8170 CEFBS_HasAtomics, // MEMORY_ATOMIC_NOTIFY_A64_S
8171 CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT32_A32
8172 CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT32_A32_S
8173 CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT32_A64
8174 CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT32_A64_S
8175 CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT64_A32
8176 CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT64_A32_S
8177 CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT64_A64
8178 CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT64_A64_S
8179 CEFBS_HasBulkMemoryOpt, // MEMORY_COPY_A32
8180 CEFBS_HasBulkMemoryOpt, // MEMORY_COPY_A32_S
8181 CEFBS_HasBulkMemoryOpt, // MEMORY_COPY_A64
8182 CEFBS_HasBulkMemoryOpt, // MEMORY_COPY_A64_S
8183 CEFBS_HasBulkMemoryOpt, // MEMORY_FILL_A32
8184 CEFBS_HasBulkMemoryOpt, // MEMORY_FILL_A32_S
8185 CEFBS_HasBulkMemoryOpt, // MEMORY_FILL_A64
8186 CEFBS_HasBulkMemoryOpt, // MEMORY_FILL_A64_S
8187 CEFBS_HasBulkMemoryOpt, // MEMORY_INIT_A32
8188 CEFBS_HasBulkMemoryOpt, // MEMORY_INIT_A32_S
8189 CEFBS_HasBulkMemoryOpt, // MEMORY_INIT_A64
8190 CEFBS_HasBulkMemoryOpt, // MEMORY_INIT_A64_S
8191 CEFBS_HasBulkMemoryOpt, // MEMSET_A32
8192 CEFBS_HasBulkMemoryOpt, // MEMSET_A32_S
8193 CEFBS_HasBulkMemoryOpt, // MEMSET_A64
8194 CEFBS_HasBulkMemoryOpt, // MEMSET_A64_S
8195 CEFBS_HasSIMD128_HasFP16, // MIN_F16x8
8196 CEFBS_HasSIMD128_HasFP16, // MIN_F16x8_S
8197 CEFBS_None, // MIN_F32
8198 CEFBS_None, // MIN_F32_S
8199 CEFBS_HasSIMD128, // MIN_F32x4
8200 CEFBS_HasSIMD128, // MIN_F32x4_S
8201 CEFBS_None, // MIN_F64
8202 CEFBS_None, // MIN_F64_S
8203 CEFBS_HasSIMD128, // MIN_F64x2
8204 CEFBS_HasSIMD128, // MIN_F64x2_S
8205 CEFBS_HasSIMD128, // MIN_S_I16x8
8206 CEFBS_HasSIMD128, // MIN_S_I16x8_S
8207 CEFBS_HasSIMD128, // MIN_S_I32x4
8208 CEFBS_HasSIMD128, // MIN_S_I32x4_S
8209 CEFBS_HasSIMD128, // MIN_S_I8x16
8210 CEFBS_HasSIMD128, // MIN_S_I8x16_S
8211 CEFBS_HasSIMD128, // MIN_U_I16x8
8212 CEFBS_HasSIMD128, // MIN_U_I16x8_S
8213 CEFBS_HasSIMD128, // MIN_U_I32x4
8214 CEFBS_HasSIMD128, // MIN_U_I32x4_S
8215 CEFBS_HasSIMD128, // MIN_U_I8x16
8216 CEFBS_HasSIMD128, // MIN_U_I8x16_S
8217 CEFBS_HasSIMD128_HasFP16, // MUL_F16x8
8218 CEFBS_HasSIMD128_HasFP16, // MUL_F16x8_S
8219 CEFBS_None, // MUL_F32
8220 CEFBS_None, // MUL_F32_S
8221 CEFBS_HasSIMD128, // MUL_F32x4
8222 CEFBS_HasSIMD128, // MUL_F32x4_S
8223 CEFBS_None, // MUL_F64
8224 CEFBS_None, // MUL_F64_S
8225 CEFBS_HasSIMD128, // MUL_F64x2
8226 CEFBS_HasSIMD128, // MUL_F64x2_S
8227 CEFBS_HasSIMD128, // MUL_I16x8
8228 CEFBS_HasSIMD128, // MUL_I16x8_S
8229 CEFBS_None, // MUL_I32
8230 CEFBS_None, // MUL_I32_S
8231 CEFBS_HasSIMD128, // MUL_I32x4
8232 CEFBS_HasSIMD128, // MUL_I32x4_S
8233 CEFBS_None, // MUL_I64
8234 CEFBS_None, // MUL_I64_S
8235 CEFBS_HasSIMD128, // MUL_I64x2
8236 CEFBS_HasSIMD128, // MUL_I64x2_S
8237 CEFBS_HasSIMD128, // NARROW_S_I16x8
8238 CEFBS_HasSIMD128, // NARROW_S_I16x8_S
8239 CEFBS_HasSIMD128, // NARROW_S_I8x16
8240 CEFBS_HasSIMD128, // NARROW_S_I8x16_S
8241 CEFBS_HasSIMD128, // NARROW_U_I16x8
8242 CEFBS_HasSIMD128, // NARROW_U_I16x8_S
8243 CEFBS_HasSIMD128, // NARROW_U_I8x16
8244 CEFBS_HasSIMD128, // NARROW_U_I8x16_S
8245 CEFBS_HasSIMD128_HasFP16, // NEAREST_F16x8
8246 CEFBS_HasSIMD128_HasFP16, // NEAREST_F16x8_S
8247 CEFBS_None, // NEAREST_F32
8248 CEFBS_None, // NEAREST_F32_S
8249 CEFBS_HasSIMD128, // NEAREST_F32x4
8250 CEFBS_HasSIMD128, // NEAREST_F32x4_S
8251 CEFBS_None, // NEAREST_F64
8252 CEFBS_None, // NEAREST_F64_S
8253 CEFBS_HasSIMD128, // NEAREST_F64x2
8254 CEFBS_HasSIMD128, // NEAREST_F64x2_S
8255 CEFBS_HasSIMD128_HasFP16, // NEG_F16x8
8256 CEFBS_HasSIMD128_HasFP16, // NEG_F16x8_S
8257 CEFBS_None, // NEG_F32
8258 CEFBS_None, // NEG_F32_S
8259 CEFBS_HasSIMD128, // NEG_F32x4
8260 CEFBS_HasSIMD128, // NEG_F32x4_S
8261 CEFBS_None, // NEG_F64
8262 CEFBS_None, // NEG_F64_S
8263 CEFBS_HasSIMD128, // NEG_F64x2
8264 CEFBS_HasSIMD128, // NEG_F64x2_S
8265 CEFBS_HasSIMD128, // NEG_I16x8
8266 CEFBS_HasSIMD128, // NEG_I16x8_S
8267 CEFBS_HasSIMD128, // NEG_I32x4
8268 CEFBS_HasSIMD128, // NEG_I32x4_S
8269 CEFBS_HasSIMD128, // NEG_I64x2
8270 CEFBS_HasSIMD128, // NEG_I64x2_S
8271 CEFBS_HasSIMD128, // NEG_I8x16
8272 CEFBS_HasSIMD128, // NEG_I8x16_S
8273 CEFBS_HasSIMD128_HasFP16, // NE_F16x8
8274 CEFBS_HasSIMD128_HasFP16, // NE_F16x8_S
8275 CEFBS_None, // NE_F32
8276 CEFBS_None, // NE_F32_S
8277 CEFBS_HasSIMD128, // NE_F32x4
8278 CEFBS_HasSIMD128, // NE_F32x4_S
8279 CEFBS_None, // NE_F64
8280 CEFBS_None, // NE_F64_S
8281 CEFBS_HasSIMD128, // NE_F64x2
8282 CEFBS_HasSIMD128, // NE_F64x2_S
8283 CEFBS_HasSIMD128, // NE_I16x8
8284 CEFBS_HasSIMD128, // NE_I16x8_S
8285 CEFBS_None, // NE_I32
8286 CEFBS_None, // NE_I32_S
8287 CEFBS_HasSIMD128, // NE_I32x4
8288 CEFBS_HasSIMD128, // NE_I32x4_S
8289 CEFBS_None, // NE_I64
8290 CEFBS_None, // NE_I64_S
8291 CEFBS_HasSIMD128, // NE_I64x2
8292 CEFBS_HasSIMD128, // NE_I64x2_S
8293 CEFBS_HasSIMD128, // NE_I8x16
8294 CEFBS_HasSIMD128, // NE_I8x16_S
8295 CEFBS_HasSIMD128_HasFP16, // NMADD_F16x8
8296 CEFBS_HasSIMD128_HasFP16, // NMADD_F16x8_S
8297 CEFBS_HasSIMD128_HasRelaxedSIMD, // NMADD_F32x4
8298 CEFBS_HasSIMD128_HasRelaxedSIMD, // NMADD_F32x4_S
8299 CEFBS_HasSIMD128_HasRelaxedSIMD, // NMADD_F64x2
8300 CEFBS_HasSIMD128_HasRelaxedSIMD, // NMADD_F64x2_S
8301 CEFBS_None, // NOP
8302 CEFBS_None, // NOP_S
8303 CEFBS_HasSIMD128, // NOT
8304 CEFBS_HasSIMD128, // NOT_S
8305 CEFBS_HasSIMD128, // OR
8306 CEFBS_None, // OR_I32
8307 CEFBS_None, // OR_I32_S
8308 CEFBS_None, // OR_I64
8309 CEFBS_None, // OR_I64_S
8310 CEFBS_HasSIMD128, // OR_S
8311 CEFBS_HasSIMD128_HasFP16, // PMAX_F16x8
8312 CEFBS_HasSIMD128_HasFP16, // PMAX_F16x8_S
8313 CEFBS_HasSIMD128, // PMAX_F32x4
8314 CEFBS_HasSIMD128, // PMAX_F32x4_S
8315 CEFBS_HasSIMD128, // PMAX_F64x2
8316 CEFBS_HasSIMD128, // PMAX_F64x2_S
8317 CEFBS_HasSIMD128_HasFP16, // PMIN_F16x8
8318 CEFBS_HasSIMD128_HasFP16, // PMIN_F16x8_S
8319 CEFBS_HasSIMD128, // PMIN_F32x4
8320 CEFBS_HasSIMD128, // PMIN_F32x4_S
8321 CEFBS_HasSIMD128, // PMIN_F64x2
8322 CEFBS_HasSIMD128, // PMIN_F64x2_S
8323 CEFBS_None, // POPCNT_I32
8324 CEFBS_None, // POPCNT_I32_S
8325 CEFBS_None, // POPCNT_I64
8326 CEFBS_None, // POPCNT_I64_S
8327 CEFBS_HasSIMD128, // POPCNT_I8x16
8328 CEFBS_HasSIMD128, // POPCNT_I8x16_S
8329 CEFBS_HasSIMD128, // Q15MULR_SAT_S_I16x8
8330 CEFBS_HasSIMD128, // Q15MULR_SAT_S_I16x8_S
8331 CEFBS_HasReferenceTypes, // REF_FUNC
8332 CEFBS_HasReferenceTypes, // REF_FUNC_S
8333 CEFBS_HasReferenceTypes, // REF_IS_NULL_EXNREF
8334 CEFBS_HasReferenceTypes, // REF_IS_NULL_EXNREF_S
8335 CEFBS_HasReferenceTypes, // REF_IS_NULL_EXTERNREF
8336 CEFBS_HasReferenceTypes, // REF_IS_NULL_EXTERNREF_S
8337 CEFBS_HasReferenceTypes, // REF_IS_NULL_FUNCREF
8338 CEFBS_HasReferenceTypes, // REF_IS_NULL_FUNCREF_S
8339 CEFBS_HasReferenceTypes, // REF_NULL_EXNREF
8340 CEFBS_HasReferenceTypes, // REF_NULL_EXNREF_S
8341 CEFBS_HasReferenceTypes, // REF_NULL_EXTERNREF
8342 CEFBS_HasReferenceTypes, // REF_NULL_EXTERNREF_S
8343 CEFBS_HasReferenceTypes, // REF_NULL_FUNCREF
8344 CEFBS_HasReferenceTypes, // REF_NULL_FUNCREF_S
8345 CEFBS_HasGC, // REF_TEST_FUNCREF
8346 CEFBS_HasGC, // REF_TEST_FUNCREF_S
8347 CEFBS_HasRelaxedSIMD, // RELAXED_DOT
8348 CEFBS_HasRelaxedSIMD, // RELAXED_DOT_ADD
8349 CEFBS_HasRelaxedSIMD, // RELAXED_DOT_ADD_S
8350 CEFBS_HasRelaxedSIMD, // RELAXED_DOT_BFLOAT
8351 CEFBS_HasRelaxedSIMD, // RELAXED_DOT_BFLOAT_S
8352 CEFBS_HasRelaxedSIMD, // RELAXED_DOT_S
8353 CEFBS_HasRelaxedSIMD, // RELAXED_Q15MULR_S_I16x8
8354 CEFBS_HasRelaxedSIMD, // RELAXED_Q15MULR_S_I16x8_S
8355 CEFBS_HasRelaxedSIMD, // RELAXED_SWIZZLE
8356 CEFBS_HasRelaxedSIMD, // RELAXED_SWIZZLE_S
8357 CEFBS_None, // REM_S_I32
8358 CEFBS_None, // REM_S_I32_S
8359 CEFBS_None, // REM_S_I64
8360 CEFBS_None, // REM_S_I64_S
8361 CEFBS_None, // REM_U_I32
8362 CEFBS_None, // REM_U_I32_S
8363 CEFBS_None, // REM_U_I64
8364 CEFBS_None, // REM_U_I64_S
8365 CEFBS_HasFP16, // REPLACE_LANE_F16x8
8366 CEFBS_HasFP16, // REPLACE_LANE_F16x8_S
8367 CEFBS_HasSIMD128, // REPLACE_LANE_F32x4
8368 CEFBS_HasSIMD128, // REPLACE_LANE_F32x4_S
8369 CEFBS_HasSIMD128, // REPLACE_LANE_F64x2
8370 CEFBS_HasSIMD128, // REPLACE_LANE_F64x2_S
8371 CEFBS_HasSIMD128, // REPLACE_LANE_I16x8
8372 CEFBS_HasSIMD128, // REPLACE_LANE_I16x8_S
8373 CEFBS_HasSIMD128, // REPLACE_LANE_I32x4
8374 CEFBS_HasSIMD128, // REPLACE_LANE_I32x4_S
8375 CEFBS_HasSIMD128, // REPLACE_LANE_I64x2
8376 CEFBS_HasSIMD128, // REPLACE_LANE_I64x2_S
8377 CEFBS_HasSIMD128, // REPLACE_LANE_I8x16
8378 CEFBS_HasSIMD128, // REPLACE_LANE_I8x16_S
8379 CEFBS_HasExceptionHandling, // RETHROW
8380 CEFBS_HasExceptionHandling, // RETHROW_S
8381 CEFBS_None, // RETURN
8382 CEFBS_None, // RETURN_S
8383 CEFBS_HasTailCall, // RET_CALL
8384 CEFBS_HasTailCall, // RET_CALL_INDIRECT
8385 CEFBS_HasTailCall, // RET_CALL_INDIRECT_S
8386 CEFBS_HasTailCall, // RET_CALL_S
8387 CEFBS_None, // ROTL_I32
8388 CEFBS_None, // ROTL_I32_S
8389 CEFBS_None, // ROTL_I64
8390 CEFBS_None, // ROTL_I64_S
8391 CEFBS_None, // ROTR_I32
8392 CEFBS_None, // ROTR_I32_S
8393 CEFBS_None, // ROTR_I64
8394 CEFBS_None, // ROTR_I64_S
8395 CEFBS_HasReferenceTypes, // SELECT_EXNREF
8396 CEFBS_HasReferenceTypes, // SELECT_EXNREF_S
8397 CEFBS_HasReferenceTypes, // SELECT_EXTERNREF
8398 CEFBS_HasReferenceTypes, // SELECT_EXTERNREF_S
8399 CEFBS_None, // SELECT_F32
8400 CEFBS_None, // SELECT_F32_S
8401 CEFBS_None, // SELECT_F64
8402 CEFBS_None, // SELECT_F64_S
8403 CEFBS_HasReferenceTypes, // SELECT_FUNCREF
8404 CEFBS_HasReferenceTypes, // SELECT_FUNCREF_S
8405 CEFBS_None, // SELECT_I32
8406 CEFBS_None, // SELECT_I32_S
8407 CEFBS_None, // SELECT_I64
8408 CEFBS_None, // SELECT_I64_S
8409 CEFBS_None, // SELECT_V128
8410 CEFBS_None, // SELECT_V128_S
8411 CEFBS_HasSIMD128, // SHL_I16x8
8412 CEFBS_HasSIMD128, // SHL_I16x8_S
8413 CEFBS_None, // SHL_I32
8414 CEFBS_None, // SHL_I32_S
8415 CEFBS_HasSIMD128, // SHL_I32x4
8416 CEFBS_HasSIMD128, // SHL_I32x4_S
8417 CEFBS_None, // SHL_I64
8418 CEFBS_None, // SHL_I64_S
8419 CEFBS_HasSIMD128, // SHL_I64x2
8420 CEFBS_HasSIMD128, // SHL_I64x2_S
8421 CEFBS_HasSIMD128, // SHL_I8x16
8422 CEFBS_HasSIMD128, // SHL_I8x16_S
8423 CEFBS_HasSIMD128, // SHR_S_I16x8
8424 CEFBS_HasSIMD128, // SHR_S_I16x8_S
8425 CEFBS_None, // SHR_S_I32
8426 CEFBS_None, // SHR_S_I32_S
8427 CEFBS_HasSIMD128, // SHR_S_I32x4
8428 CEFBS_HasSIMD128, // SHR_S_I32x4_S
8429 CEFBS_None, // SHR_S_I64
8430 CEFBS_None, // SHR_S_I64_S
8431 CEFBS_HasSIMD128, // SHR_S_I64x2
8432 CEFBS_HasSIMD128, // SHR_S_I64x2_S
8433 CEFBS_HasSIMD128, // SHR_S_I8x16
8434 CEFBS_HasSIMD128, // SHR_S_I8x16_S
8435 CEFBS_HasSIMD128, // SHR_U_I16x8
8436 CEFBS_HasSIMD128, // SHR_U_I16x8_S
8437 CEFBS_None, // SHR_U_I32
8438 CEFBS_None, // SHR_U_I32_S
8439 CEFBS_HasSIMD128, // SHR_U_I32x4
8440 CEFBS_HasSIMD128, // SHR_U_I32x4_S
8441 CEFBS_None, // SHR_U_I64
8442 CEFBS_None, // SHR_U_I64_S
8443 CEFBS_HasSIMD128, // SHR_U_I64x2
8444 CEFBS_HasSIMD128, // SHR_U_I64x2_S
8445 CEFBS_HasSIMD128, // SHR_U_I8x16
8446 CEFBS_HasSIMD128, // SHR_U_I8x16_S
8447 CEFBS_HasSIMD128, // SHUFFLE
8448 CEFBS_HasSIMD128, // SHUFFLE_S
8449 CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMAX_F32x4
8450 CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMAX_F32x4_S
8451 CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMAX_F64x2
8452 CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMAX_F64x2_S
8453 CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMIN_F32x4
8454 CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMIN_F32x4_S
8455 CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMIN_F64x2
8456 CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMIN_F64x2_S
8457 CEFBS_HasFP16, // SPLAT_F16x8
8458 CEFBS_HasFP16, // SPLAT_F16x8_S
8459 CEFBS_HasSIMD128, // SPLAT_F32x4
8460 CEFBS_HasSIMD128, // SPLAT_F32x4_S
8461 CEFBS_HasSIMD128, // SPLAT_F64x2
8462 CEFBS_HasSIMD128, // SPLAT_F64x2_S
8463 CEFBS_HasSIMD128, // SPLAT_I16x8
8464 CEFBS_HasSIMD128, // SPLAT_I16x8_S
8465 CEFBS_HasSIMD128, // SPLAT_I32x4
8466 CEFBS_HasSIMD128, // SPLAT_I32x4_S
8467 CEFBS_HasSIMD128, // SPLAT_I64x2
8468 CEFBS_HasSIMD128, // SPLAT_I64x2_S
8469 CEFBS_HasSIMD128, // SPLAT_I8x16
8470 CEFBS_HasSIMD128, // SPLAT_I8x16_S
8471 CEFBS_HasSIMD128_HasFP16, // SQRT_F16x8
8472 CEFBS_HasSIMD128_HasFP16, // SQRT_F16x8_S
8473 CEFBS_None, // SQRT_F32
8474 CEFBS_None, // SQRT_F32_S
8475 CEFBS_HasSIMD128, // SQRT_F32x4
8476 CEFBS_HasSIMD128, // SQRT_F32x4_S
8477 CEFBS_None, // SQRT_F64
8478 CEFBS_None, // SQRT_F64_S
8479 CEFBS_HasSIMD128, // SQRT_F64x2
8480 CEFBS_HasSIMD128, // SQRT_F64x2_S
8481 CEFBS_None, // STORE16_I32_A32
8482 CEFBS_None, // STORE16_I32_A32_S
8483 CEFBS_None, // STORE16_I32_A64
8484 CEFBS_None, // STORE16_I32_A64_S
8485 CEFBS_None, // STORE16_I64_A32
8486 CEFBS_None, // STORE16_I64_A32_S
8487 CEFBS_None, // STORE16_I64_A64
8488 CEFBS_None, // STORE16_I64_A64_S
8489 CEFBS_None, // STORE32_I64_A32
8490 CEFBS_None, // STORE32_I64_A32_S
8491 CEFBS_None, // STORE32_I64_A64
8492 CEFBS_None, // STORE32_I64_A64_S
8493 CEFBS_None, // STORE8_I32_A32
8494 CEFBS_None, // STORE8_I32_A32_S
8495 CEFBS_None, // STORE8_I32_A64
8496 CEFBS_None, // STORE8_I32_A64_S
8497 CEFBS_None, // STORE8_I64_A32
8498 CEFBS_None, // STORE8_I64_A32_S
8499 CEFBS_None, // STORE8_I64_A64
8500 CEFBS_None, // STORE8_I64_A64_S
8501 CEFBS_HasFP16, // STORE_F16_F32_A32
8502 CEFBS_HasFP16, // STORE_F16_F32_A32_S
8503 CEFBS_HasFP16, // STORE_F16_F32_A64
8504 CEFBS_HasFP16, // STORE_F16_F32_A64_S
8505 CEFBS_None, // STORE_F32_A32
8506 CEFBS_None, // STORE_F32_A32_S
8507 CEFBS_None, // STORE_F32_A64
8508 CEFBS_None, // STORE_F32_A64_S
8509 CEFBS_None, // STORE_F64_A32
8510 CEFBS_None, // STORE_F64_A32_S
8511 CEFBS_None, // STORE_F64_A64
8512 CEFBS_None, // STORE_F64_A64_S
8513 CEFBS_None, // STORE_I32_A32
8514 CEFBS_None, // STORE_I32_A32_S
8515 CEFBS_None, // STORE_I32_A64
8516 CEFBS_None, // STORE_I32_A64_S
8517 CEFBS_None, // STORE_I64_A32
8518 CEFBS_None, // STORE_I64_A32_S
8519 CEFBS_None, // STORE_I64_A64
8520 CEFBS_None, // STORE_I64_A64_S
8521 CEFBS_HasSIMD128, // STORE_LANE_I16x8_A32
8522 CEFBS_HasSIMD128, // STORE_LANE_I16x8_A32_S
8523 CEFBS_HasSIMD128, // STORE_LANE_I16x8_A64
8524 CEFBS_HasSIMD128, // STORE_LANE_I16x8_A64_S
8525 CEFBS_HasSIMD128, // STORE_LANE_I32x4_A32
8526 CEFBS_HasSIMD128, // STORE_LANE_I32x4_A32_S
8527 CEFBS_HasSIMD128, // STORE_LANE_I32x4_A64
8528 CEFBS_HasSIMD128, // STORE_LANE_I32x4_A64_S
8529 CEFBS_HasSIMD128, // STORE_LANE_I64x2_A32
8530 CEFBS_HasSIMD128, // STORE_LANE_I64x2_A32_S
8531 CEFBS_HasSIMD128, // STORE_LANE_I64x2_A64
8532 CEFBS_HasSIMD128, // STORE_LANE_I64x2_A64_S
8533 CEFBS_HasSIMD128, // STORE_LANE_I8x16_A32
8534 CEFBS_HasSIMD128, // STORE_LANE_I8x16_A32_S
8535 CEFBS_HasSIMD128, // STORE_LANE_I8x16_A64
8536 CEFBS_HasSIMD128, // STORE_LANE_I8x16_A64_S
8537 CEFBS_HasSIMD128, // STORE_V128_A32
8538 CEFBS_HasSIMD128, // STORE_V128_A32_S
8539 CEFBS_HasSIMD128, // STORE_V128_A64
8540 CEFBS_HasSIMD128, // STORE_V128_A64_S
8541 CEFBS_HasSIMD128_HasFP16, // SUB_F16x8
8542 CEFBS_HasSIMD128_HasFP16, // SUB_F16x8_S
8543 CEFBS_None, // SUB_F32
8544 CEFBS_None, // SUB_F32_S
8545 CEFBS_HasSIMD128, // SUB_F32x4
8546 CEFBS_HasSIMD128, // SUB_F32x4_S
8547 CEFBS_None, // SUB_F64
8548 CEFBS_None, // SUB_F64_S
8549 CEFBS_HasSIMD128, // SUB_F64x2
8550 CEFBS_HasSIMD128, // SUB_F64x2_S
8551 CEFBS_HasSIMD128, // SUB_I16x8
8552 CEFBS_HasSIMD128, // SUB_I16x8_S
8553 CEFBS_None, // SUB_I32
8554 CEFBS_None, // SUB_I32_S
8555 CEFBS_HasSIMD128, // SUB_I32x4
8556 CEFBS_HasSIMD128, // SUB_I32x4_S
8557 CEFBS_None, // SUB_I64
8558 CEFBS_None, // SUB_I64_S
8559 CEFBS_HasSIMD128, // SUB_I64x2
8560 CEFBS_HasSIMD128, // SUB_I64x2_S
8561 CEFBS_HasSIMD128, // SUB_I8x16
8562 CEFBS_HasSIMD128, // SUB_I8x16_S
8563 CEFBS_HasSIMD128, // SUB_SAT_S_I16x8
8564 CEFBS_HasSIMD128, // SUB_SAT_S_I16x8_S
8565 CEFBS_HasSIMD128, // SUB_SAT_S_I8x16
8566 CEFBS_HasSIMD128, // SUB_SAT_S_I8x16_S
8567 CEFBS_HasSIMD128, // SUB_SAT_U_I16x8
8568 CEFBS_HasSIMD128, // SUB_SAT_U_I16x8_S
8569 CEFBS_HasSIMD128, // SUB_SAT_U_I8x16
8570 CEFBS_HasSIMD128, // SUB_SAT_U_I8x16_S
8571 CEFBS_HasSIMD128, // SWIZZLE
8572 CEFBS_HasSIMD128, // SWIZZLE_S
8573 CEFBS_HasReferenceTypes, // TABLE_COPY
8574 CEFBS_HasReferenceTypes, // TABLE_COPY_S
8575 CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_FILL_EXNREF
8576 CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_FILL_EXNREF_S
8577 CEFBS_HasReferenceTypes, // TABLE_FILL_EXTERNREF
8578 CEFBS_HasReferenceTypes, // TABLE_FILL_EXTERNREF_S
8579 CEFBS_HasReferenceTypes, // TABLE_FILL_FUNCREF
8580 CEFBS_HasReferenceTypes, // TABLE_FILL_FUNCREF_S
8581 CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_GET_EXNREF
8582 CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_GET_EXNREF_S
8583 CEFBS_HasReferenceTypes, // TABLE_GET_EXTERNREF
8584 CEFBS_HasReferenceTypes, // TABLE_GET_EXTERNREF_S
8585 CEFBS_HasReferenceTypes, // TABLE_GET_FUNCREF
8586 CEFBS_HasReferenceTypes, // TABLE_GET_FUNCREF_S
8587 CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_GROW_EXNREF
8588 CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_GROW_EXNREF_S
8589 CEFBS_HasReferenceTypes, // TABLE_GROW_EXTERNREF
8590 CEFBS_HasReferenceTypes, // TABLE_GROW_EXTERNREF_S
8591 CEFBS_HasReferenceTypes, // TABLE_GROW_FUNCREF
8592 CEFBS_HasReferenceTypes, // TABLE_GROW_FUNCREF_S
8593 CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_SET_EXNREF
8594 CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_SET_EXNREF_S
8595 CEFBS_HasReferenceTypes, // TABLE_SET_EXTERNREF
8596 CEFBS_HasReferenceTypes, // TABLE_SET_EXTERNREF_S
8597 CEFBS_HasReferenceTypes, // TABLE_SET_FUNCREF
8598 CEFBS_HasReferenceTypes, // TABLE_SET_FUNCREF_S
8599 CEFBS_HasReferenceTypes, // TABLE_SIZE
8600 CEFBS_HasReferenceTypes, // TABLE_SIZE_S
8601 CEFBS_HasReferenceTypes_HasExceptionHandling, // TEE_EXNREF
8602 CEFBS_HasReferenceTypes_HasExceptionHandling, // TEE_EXNREF_S
8603 CEFBS_HasReferenceTypes, // TEE_EXTERNREF
8604 CEFBS_HasReferenceTypes, // TEE_EXTERNREF_S
8605 CEFBS_None, // TEE_F32
8606 CEFBS_None, // TEE_F32_S
8607 CEFBS_None, // TEE_F64
8608 CEFBS_None, // TEE_F64_S
8609 CEFBS_HasReferenceTypes, // TEE_FUNCREF
8610 CEFBS_HasReferenceTypes, // TEE_FUNCREF_S
8611 CEFBS_None, // TEE_I32
8612 CEFBS_None, // TEE_I32_S
8613 CEFBS_None, // TEE_I64
8614 CEFBS_None, // TEE_I64_S
8615 CEFBS_HasSIMD128, // TEE_V128
8616 CEFBS_HasSIMD128, // TEE_V128_S
8617 CEFBS_HasExceptionHandling, // THROW
8618 CEFBS_HasExceptionHandling, // THROW_REF
8619 CEFBS_HasExceptionHandling, // THROW_REF_S
8620 CEFBS_HasExceptionHandling, // THROW_S
8621 CEFBS_HasSIMD128_HasFP16, // TRUNC_F16x8
8622 CEFBS_HasSIMD128_HasFP16, // TRUNC_F16x8_S
8623 CEFBS_None, // TRUNC_F32
8624 CEFBS_None, // TRUNC_F32_S
8625 CEFBS_HasSIMD128, // TRUNC_F32x4
8626 CEFBS_HasSIMD128, // TRUNC_F32x4_S
8627 CEFBS_None, // TRUNC_F64
8628 CEFBS_None, // TRUNC_F64_S
8629 CEFBS_HasSIMD128, // TRUNC_F64x2
8630 CEFBS_HasSIMD128, // TRUNC_F64x2_S
8631 CEFBS_HasExceptionHandling, // TRY
8632 CEFBS_HasExceptionHandling, // TRY_S
8633 CEFBS_HasExceptionHandling, // TRY_TABLE
8634 CEFBS_HasExceptionHandling, // TRY_TABLE_S
8635 CEFBS_None, // UNREACHABLE
8636 CEFBS_None, // UNREACHABLE_S
8637 CEFBS_HasSIMD128, // XOR
8638 CEFBS_None, // XOR_I32
8639 CEFBS_None, // XOR_I32_S
8640 CEFBS_None, // XOR_I64
8641 CEFBS_None, // XOR_I64_S
8642 CEFBS_HasSIMD128, // XOR_S
8643 CEFBS_None, // anonymous_13975MEMORY_GROW_A32
8644 CEFBS_None, // anonymous_13975MEMORY_GROW_A32_S
8645 CEFBS_None, // anonymous_13975MEMORY_SIZE_A32
8646 CEFBS_None, // anonymous_13975MEMORY_SIZE_A32_S
8647 CEFBS_None, // anonymous_13976MEMORY_GROW_A64
8648 CEFBS_None, // anonymous_13976MEMORY_GROW_A64_S
8649 CEFBS_None, // anonymous_13976MEMORY_SIZE_A64
8650 CEFBS_None, // anonymous_13976MEMORY_SIZE_A64_S
8651 CEFBS_HasSIMD128, // convert_low_s_F64x2
8652 CEFBS_HasSIMD128, // convert_low_s_F64x2_S
8653 CEFBS_HasSIMD128, // convert_low_u_F64x2
8654 CEFBS_HasSIMD128, // convert_low_u_F64x2_S
8655 CEFBS_HasSIMD128, // demote_zero_F32x4
8656 CEFBS_HasSIMD128, // demote_zero_F32x4_S
8657 CEFBS_HasSIMD128, // extadd_pairwise_s_I16x8
8658 CEFBS_HasSIMD128, // extadd_pairwise_s_I16x8_S
8659 CEFBS_HasSIMD128, // extadd_pairwise_s_I32x4
8660 CEFBS_HasSIMD128, // extadd_pairwise_s_I32x4_S
8661 CEFBS_HasSIMD128, // extadd_pairwise_u_I16x8
8662 CEFBS_HasSIMD128, // extadd_pairwise_u_I16x8_S
8663 CEFBS_HasSIMD128, // extadd_pairwise_u_I32x4
8664 CEFBS_HasSIMD128, // extadd_pairwise_u_I32x4_S
8665 CEFBS_HasSIMD128, // extend_high_s_I16x8
8666 CEFBS_HasSIMD128, // extend_high_s_I16x8_S
8667 CEFBS_HasSIMD128, // extend_high_s_I32x4
8668 CEFBS_HasSIMD128, // extend_high_s_I32x4_S
8669 CEFBS_HasSIMD128, // extend_high_s_I64x2
8670 CEFBS_HasSIMD128, // extend_high_s_I64x2_S
8671 CEFBS_HasSIMD128, // extend_high_u_I16x8
8672 CEFBS_HasSIMD128, // extend_high_u_I16x8_S
8673 CEFBS_HasSIMD128, // extend_high_u_I32x4
8674 CEFBS_HasSIMD128, // extend_high_u_I32x4_S
8675 CEFBS_HasSIMD128, // extend_high_u_I64x2
8676 CEFBS_HasSIMD128, // extend_high_u_I64x2_S
8677 CEFBS_HasSIMD128, // extend_low_s_I16x8
8678 CEFBS_HasSIMD128, // extend_low_s_I16x8_S
8679 CEFBS_HasSIMD128, // extend_low_s_I32x4
8680 CEFBS_HasSIMD128, // extend_low_s_I32x4_S
8681 CEFBS_HasSIMD128, // extend_low_s_I64x2
8682 CEFBS_HasSIMD128, // extend_low_s_I64x2_S
8683 CEFBS_HasSIMD128, // extend_low_u_I16x8
8684 CEFBS_HasSIMD128, // extend_low_u_I16x8_S
8685 CEFBS_HasSIMD128, // extend_low_u_I32x4
8686 CEFBS_HasSIMD128, // extend_low_u_I32x4_S
8687 CEFBS_HasSIMD128, // extend_low_u_I64x2
8688 CEFBS_HasSIMD128, // extend_low_u_I64x2_S
8689 CEFBS_HasSIMD128_HasFP16, // fp_to_sint_I16x8
8690 CEFBS_HasSIMD128_HasFP16, // fp_to_sint_I16x8_S
8691 CEFBS_HasSIMD128, // fp_to_sint_I32x4
8692 CEFBS_HasSIMD128, // fp_to_sint_I32x4_S
8693 CEFBS_HasSIMD128_HasFP16, // fp_to_uint_I16x8
8694 CEFBS_HasSIMD128_HasFP16, // fp_to_uint_I16x8_S
8695 CEFBS_HasSIMD128, // fp_to_uint_I32x4
8696 CEFBS_HasSIMD128, // fp_to_uint_I32x4_S
8697 CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_signed_I32x4
8698 CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_signed_I32x4_S
8699 CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_signed_zero_I32x4
8700 CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_signed_zero_I32x4_S
8701 CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_unsigned_I32x4
8702 CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_unsigned_I32x4_S
8703 CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_unsigned_zero_I32x4
8704 CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_unsigned_zero_I32x4_S
8705 CEFBS_HasSIMD128, // promote_low_F64x2
8706 CEFBS_HasSIMD128, // promote_low_F64x2_S
8707 CEFBS_HasSIMD128_HasFP16, // sint_to_fp_F16x8
8708 CEFBS_HasSIMD128_HasFP16, // sint_to_fp_F16x8_S
8709 CEFBS_HasSIMD128, // sint_to_fp_F32x4
8710 CEFBS_HasSIMD128, // sint_to_fp_F32x4_S
8711 CEFBS_HasSIMD128, // trunc_sat_zero_s_I32x4
8712 CEFBS_HasSIMD128, // trunc_sat_zero_s_I32x4_S
8713 CEFBS_HasSIMD128, // trunc_sat_zero_u_I32x4
8714 CEFBS_HasSIMD128, // trunc_sat_zero_u_I32x4_S
8715 CEFBS_HasSIMD128_HasFP16, // uint_to_fp_F16x8
8716 CEFBS_HasSIMD128_HasFP16, // uint_to_fp_F16x8_S
8717 CEFBS_HasSIMD128, // uint_to_fp_F32x4
8718 CEFBS_HasSIMD128, // uint_to_fp_F32x4_S
8719 };
8720
8721 assert(Opcode < 1959);
8722 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
8723}
8724
8725
8726} // namespace llvm::WebAssembly_MC
8727
8728#endif // GET_COMPUTE_FEATURES
8729
8730#ifdef GET_AVAILABLE_OPCODE_CHECKER
8731#undef GET_AVAILABLE_OPCODE_CHECKER
8732
8733namespace llvm::WebAssembly_MC {
8734
8735bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
8736 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
8737 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
8738 FeatureBitset MissingFeatures =
8739 (AvailableFeatures & RequiredFeatures) ^
8740 RequiredFeatures;
8741 return !MissingFeatures.any();
8742}
8743
8744} // namespace llvm::WebAssembly_MC
8745
8746#endif // GET_AVAILABLE_OPCODE_CHECKER
8747
8748#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
8749#undef ENABLE_INSTR_PREDICATE_VERIFIER
8750
8751#include <sstream>
8752
8753namespace llvm::WebAssembly_MC {
8754
8755#ifndef NDEBUG
8756static const char *SubtargetFeatureNames[] = {
8757 "Feature_HasAtomics",
8758 "Feature_HasBulkMemory",
8759 "Feature_HasBulkMemoryOpt",
8760 "Feature_HasCallIndirectOverlong",
8761 "Feature_HasExceptionHandling",
8762 "Feature_HasExtendedConst",
8763 "Feature_HasFP16",
8764 "Feature_HasGC",
8765 "Feature_HasMultiMemory",
8766 "Feature_HasMultivalue",
8767 "Feature_HasMutableGlobals",
8768 "Feature_HasNontrappingFPToInt",
8769 "Feature_HasReferenceTypes",
8770 "Feature_HasRelaxedAtomics",
8771 "Feature_HasRelaxedSIMD",
8772 "Feature_HasSIMD128",
8773 "Feature_HasSignExt",
8774 "Feature_HasTailCall",
8775 "Feature_HasWideArithmetic",
8776 "Feature_NotHasNontrappingFPToInt",
8777 nullptr
8778};
8779
8780#endif // NDEBUG
8781
8782void verifyInstructionPredicates(
8783 unsigned Opcode, const FeatureBitset &Features) {
8784#ifndef NDEBUG
8785 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
8786 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
8787 FeatureBitset MissingFeatures =
8788 (AvailableFeatures & RequiredFeatures) ^
8789 RequiredFeatures;
8790 if (MissingFeatures.any()) {
8791 std::ostringstream Msg;
8792 Msg << "Attempting to emit " << &WebAssemblyInstrNameData[WebAssemblyInstrNameIndices[Opcode]]
8793 << " instruction but the ";
8794 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
8795 if (MissingFeatures.test(i))
8796 Msg << SubtargetFeatureNames[i] << " ";
8797 Msg << "predicate(s) are not met";
8798 report_fatal_error(Msg.str().c_str());
8799 }
8800#endif // NDEBUG
8801}
8802
8803} // namespace llvm::WebAssembly_MC
8804
8805#endif // ENABLE_INSTR_PREDICATE_VERIFIER
8806
8807#ifdef GET_INSTRMAP_INFO
8808#undef GET_INSTRMAP_INFO
8809
8810namespace llvm::WebAssembly {
8811
8812enum IsWasm64 {
8813 IsWasm64_1
8814};
8815
8816enum StackBased {
8817 StackBased_0,
8818 StackBased_1
8819};
8820
8821// getRegisterOpcode
8822LLVM_READONLY
8823int32_t getRegisterOpcode(uint32_t Opcode) {
8824 using namespace WebAssembly;
8825 static constexpr uint32_t Table[][2] = {
8826 { CALL_PARAMS_S, CALL_PARAMS },
8827 { CALL_RESULTS_S, CALL_RESULTS },
8828 { CATCHRET_S, CATCHRET },
8829 { CLEANUPRET_S, CLEANUPRET },
8830 { COMPILER_FENCE_S, COMPILER_FENCE },
8831 { RET_CALL_RESULTS_S, RET_CALL_RESULTS },
8832 { ABS_F16x8_S, ABS_F16x8 },
8833 { ABS_F32_S, ABS_F32 },
8834 { ABS_F32x4_S, ABS_F32x4 },
8835 { ABS_F64_S, ABS_F64 },
8836 { ABS_F64x2_S, ABS_F64x2 },
8837 { ABS_I16x8_S, ABS_I16x8 },
8838 { ABS_I32x4_S, ABS_I32x4 },
8839 { ABS_I64x2_S, ABS_I64x2 },
8840 { ABS_I8x16_S, ABS_I8x16 },
8841 { ADD_F16x8_S, ADD_F16x8 },
8842 { ADD_F32_S, ADD_F32 },
8843 { ADD_F32x4_S, ADD_F32x4 },
8844 { ADD_F64_S, ADD_F64 },
8845 { ADD_F64x2_S, ADD_F64x2 },
8846 { ADD_I16x8_S, ADD_I16x8 },
8847 { ADD_I32_S, ADD_I32 },
8848 { ADD_I32x4_S, ADD_I32x4 },
8849 { ADD_I64_S, ADD_I64 },
8850 { ADD_I64x2_S, ADD_I64x2 },
8851 { ADD_I8x16_S, ADD_I8x16 },
8852 { ADD_SAT_S_I16x8_S, ADD_SAT_S_I16x8 },
8853 { ADD_SAT_S_I8x16_S, ADD_SAT_S_I8x16 },
8854 { ADD_SAT_U_I16x8_S, ADD_SAT_U_I16x8 },
8855 { ADD_SAT_U_I8x16_S, ADD_SAT_U_I8x16 },
8856 { ADJCALLSTACKDOWN_S, ADJCALLSTACKDOWN },
8857 { ADJCALLSTACKUP_S, ADJCALLSTACKUP },
8858 { ALLTRUE_I16x8_S, ALLTRUE_I16x8 },
8859 { ALLTRUE_I32x4_S, ALLTRUE_I32x4 },
8860 { ALLTRUE_I64x2_S, ALLTRUE_I64x2 },
8861 { ALLTRUE_I8x16_S, ALLTRUE_I8x16 },
8862 { ANDNOT_S, ANDNOT },
8863 { AND_I32_S, AND_I32 },
8864 { AND_I64_S, AND_I64 },
8865 { AND_S, AND },
8866 { ANYTRUE_S, ANYTRUE },
8867 { ARGUMENT_exnref_S, ARGUMENT_exnref },
8868 { ARGUMENT_externref_S, ARGUMENT_externref },
8869 { ARGUMENT_f32_S, ARGUMENT_f32 },
8870 { ARGUMENT_f64_S, ARGUMENT_f64 },
8871 { ARGUMENT_funcref_S, ARGUMENT_funcref },
8872 { ARGUMENT_i32_S, ARGUMENT_i32 },
8873 { ARGUMENT_i64_S, ARGUMENT_i64 },
8874 { ARGUMENT_v16i8_S, ARGUMENT_v16i8 },
8875 { ARGUMENT_v2f64_S, ARGUMENT_v2f64 },
8876 { ARGUMENT_v2i64_S, ARGUMENT_v2i64 },
8877 { ARGUMENT_v4f32_S, ARGUMENT_v4f32 },
8878 { ARGUMENT_v4i32_S, ARGUMENT_v4i32 },
8879 { ARGUMENT_v8f16_S, ARGUMENT_v8f16 },
8880 { ARGUMENT_v8i16_S, ARGUMENT_v8i16 },
8881 { ATOMIC_FENCE_S, ATOMIC_FENCE },
8882 { ATOMIC_LOAD16_U_I32_A32_S, ATOMIC_LOAD16_U_I32_A32 },
8883 { ATOMIC_LOAD16_U_I32_A64_S, ATOMIC_LOAD16_U_I32_A64 },
8884 { ATOMIC_LOAD16_U_I64_A32_S, ATOMIC_LOAD16_U_I64_A32 },
8885 { ATOMIC_LOAD16_U_I64_A64_S, ATOMIC_LOAD16_U_I64_A64 },
8886 { ATOMIC_LOAD32_U_I64_A32_S, ATOMIC_LOAD32_U_I64_A32 },
8887 { ATOMIC_LOAD32_U_I64_A64_S, ATOMIC_LOAD32_U_I64_A64 },
8888 { ATOMIC_LOAD8_U_I32_A32_S, ATOMIC_LOAD8_U_I32_A32 },
8889 { ATOMIC_LOAD8_U_I32_A64_S, ATOMIC_LOAD8_U_I32_A64 },
8890 { ATOMIC_LOAD8_U_I64_A32_S, ATOMIC_LOAD8_U_I64_A32 },
8891 { ATOMIC_LOAD8_U_I64_A64_S, ATOMIC_LOAD8_U_I64_A64 },
8892 { ATOMIC_LOAD_I32_A32_S, ATOMIC_LOAD_I32_A32 },
8893 { ATOMIC_LOAD_I32_A64_S, ATOMIC_LOAD_I32_A64 },
8894 { ATOMIC_LOAD_I64_A32_S, ATOMIC_LOAD_I64_A32 },
8895 { ATOMIC_LOAD_I64_A64_S, ATOMIC_LOAD_I64_A64 },
8896 { ATOMIC_RMW16_U_ADD_I32_A32_S, ATOMIC_RMW16_U_ADD_I32_A32 },
8897 { ATOMIC_RMW16_U_ADD_I32_A64_S, ATOMIC_RMW16_U_ADD_I32_A64 },
8898 { ATOMIC_RMW16_U_ADD_I64_A32_S, ATOMIC_RMW16_U_ADD_I64_A32 },
8899 { ATOMIC_RMW16_U_ADD_I64_A64_S, ATOMIC_RMW16_U_ADD_I64_A64 },
8900 { ATOMIC_RMW16_U_AND_I32_A32_S, ATOMIC_RMW16_U_AND_I32_A32 },
8901 { ATOMIC_RMW16_U_AND_I32_A64_S, ATOMIC_RMW16_U_AND_I32_A64 },
8902 { ATOMIC_RMW16_U_AND_I64_A32_S, ATOMIC_RMW16_U_AND_I64_A32 },
8903 { ATOMIC_RMW16_U_AND_I64_A64_S, ATOMIC_RMW16_U_AND_I64_A64 },
8904 { ATOMIC_RMW16_U_CMPXCHG_I32_A32_S, ATOMIC_RMW16_U_CMPXCHG_I32_A32 },
8905 { ATOMIC_RMW16_U_CMPXCHG_I32_A64_S, ATOMIC_RMW16_U_CMPXCHG_I32_A64 },
8906 { ATOMIC_RMW16_U_CMPXCHG_I64_A32_S, ATOMIC_RMW16_U_CMPXCHG_I64_A32 },
8907 { ATOMIC_RMW16_U_CMPXCHG_I64_A64_S, ATOMIC_RMW16_U_CMPXCHG_I64_A64 },
8908 { ATOMIC_RMW16_U_OR_I32_A32_S, ATOMIC_RMW16_U_OR_I32_A32 },
8909 { ATOMIC_RMW16_U_OR_I32_A64_S, ATOMIC_RMW16_U_OR_I32_A64 },
8910 { ATOMIC_RMW16_U_OR_I64_A32_S, ATOMIC_RMW16_U_OR_I64_A32 },
8911 { ATOMIC_RMW16_U_OR_I64_A64_S, ATOMIC_RMW16_U_OR_I64_A64 },
8912 { ATOMIC_RMW16_U_SUB_I32_A32_S, ATOMIC_RMW16_U_SUB_I32_A32 },
8913 { ATOMIC_RMW16_U_SUB_I32_A64_S, ATOMIC_RMW16_U_SUB_I32_A64 },
8914 { ATOMIC_RMW16_U_SUB_I64_A32_S, ATOMIC_RMW16_U_SUB_I64_A32 },
8915 { ATOMIC_RMW16_U_SUB_I64_A64_S, ATOMIC_RMW16_U_SUB_I64_A64 },
8916 { ATOMIC_RMW16_U_XCHG_I32_A32_S, ATOMIC_RMW16_U_XCHG_I32_A32 },
8917 { ATOMIC_RMW16_U_XCHG_I32_A64_S, ATOMIC_RMW16_U_XCHG_I32_A64 },
8918 { ATOMIC_RMW16_U_XCHG_I64_A32_S, ATOMIC_RMW16_U_XCHG_I64_A32 },
8919 { ATOMIC_RMW16_U_XCHG_I64_A64_S, ATOMIC_RMW16_U_XCHG_I64_A64 },
8920 { ATOMIC_RMW16_U_XOR_I32_A32_S, ATOMIC_RMW16_U_XOR_I32_A32 },
8921 { ATOMIC_RMW16_U_XOR_I32_A64_S, ATOMIC_RMW16_U_XOR_I32_A64 },
8922 { ATOMIC_RMW16_U_XOR_I64_A32_S, ATOMIC_RMW16_U_XOR_I64_A32 },
8923 { ATOMIC_RMW16_U_XOR_I64_A64_S, ATOMIC_RMW16_U_XOR_I64_A64 },
8924 { ATOMIC_RMW32_U_ADD_I64_A32_S, ATOMIC_RMW32_U_ADD_I64_A32 },
8925 { ATOMIC_RMW32_U_ADD_I64_A64_S, ATOMIC_RMW32_U_ADD_I64_A64 },
8926 { ATOMIC_RMW32_U_AND_I64_A32_S, ATOMIC_RMW32_U_AND_I64_A32 },
8927 { ATOMIC_RMW32_U_AND_I64_A64_S, ATOMIC_RMW32_U_AND_I64_A64 },
8928 { ATOMIC_RMW32_U_CMPXCHG_I64_A32_S, ATOMIC_RMW32_U_CMPXCHG_I64_A32 },
8929 { ATOMIC_RMW32_U_CMPXCHG_I64_A64_S, ATOMIC_RMW32_U_CMPXCHG_I64_A64 },
8930 { ATOMIC_RMW32_U_OR_I64_A32_S, ATOMIC_RMW32_U_OR_I64_A32 },
8931 { ATOMIC_RMW32_U_OR_I64_A64_S, ATOMIC_RMW32_U_OR_I64_A64 },
8932 { ATOMIC_RMW32_U_SUB_I64_A32_S, ATOMIC_RMW32_U_SUB_I64_A32 },
8933 { ATOMIC_RMW32_U_SUB_I64_A64_S, ATOMIC_RMW32_U_SUB_I64_A64 },
8934 { ATOMIC_RMW32_U_XCHG_I64_A32_S, ATOMIC_RMW32_U_XCHG_I64_A32 },
8935 { ATOMIC_RMW32_U_XCHG_I64_A64_S, ATOMIC_RMW32_U_XCHG_I64_A64 },
8936 { ATOMIC_RMW32_U_XOR_I64_A32_S, ATOMIC_RMW32_U_XOR_I64_A32 },
8937 { ATOMIC_RMW32_U_XOR_I64_A64_S, ATOMIC_RMW32_U_XOR_I64_A64 },
8938 { ATOMIC_RMW8_U_ADD_I32_A32_S, ATOMIC_RMW8_U_ADD_I32_A32 },
8939 { ATOMIC_RMW8_U_ADD_I32_A64_S, ATOMIC_RMW8_U_ADD_I32_A64 },
8940 { ATOMIC_RMW8_U_ADD_I64_A32_S, ATOMIC_RMW8_U_ADD_I64_A32 },
8941 { ATOMIC_RMW8_U_ADD_I64_A64_S, ATOMIC_RMW8_U_ADD_I64_A64 },
8942 { ATOMIC_RMW8_U_AND_I32_A32_S, ATOMIC_RMW8_U_AND_I32_A32 },
8943 { ATOMIC_RMW8_U_AND_I32_A64_S, ATOMIC_RMW8_U_AND_I32_A64 },
8944 { ATOMIC_RMW8_U_AND_I64_A32_S, ATOMIC_RMW8_U_AND_I64_A32 },
8945 { ATOMIC_RMW8_U_AND_I64_A64_S, ATOMIC_RMW8_U_AND_I64_A64 },
8946 { ATOMIC_RMW8_U_CMPXCHG_I32_A32_S, ATOMIC_RMW8_U_CMPXCHG_I32_A32 },
8947 { ATOMIC_RMW8_U_CMPXCHG_I32_A64_S, ATOMIC_RMW8_U_CMPXCHG_I32_A64 },
8948 { ATOMIC_RMW8_U_CMPXCHG_I64_A32_S, ATOMIC_RMW8_U_CMPXCHG_I64_A32 },
8949 { ATOMIC_RMW8_U_CMPXCHG_I64_A64_S, ATOMIC_RMW8_U_CMPXCHG_I64_A64 },
8950 { ATOMIC_RMW8_U_OR_I32_A32_S, ATOMIC_RMW8_U_OR_I32_A32 },
8951 { ATOMIC_RMW8_U_OR_I32_A64_S, ATOMIC_RMW8_U_OR_I32_A64 },
8952 { ATOMIC_RMW8_U_OR_I64_A32_S, ATOMIC_RMW8_U_OR_I64_A32 },
8953 { ATOMIC_RMW8_U_OR_I64_A64_S, ATOMIC_RMW8_U_OR_I64_A64 },
8954 { ATOMIC_RMW8_U_SUB_I32_A32_S, ATOMIC_RMW8_U_SUB_I32_A32 },
8955 { ATOMIC_RMW8_U_SUB_I32_A64_S, ATOMIC_RMW8_U_SUB_I32_A64 },
8956 { ATOMIC_RMW8_U_SUB_I64_A32_S, ATOMIC_RMW8_U_SUB_I64_A32 },
8957 { ATOMIC_RMW8_U_SUB_I64_A64_S, ATOMIC_RMW8_U_SUB_I64_A64 },
8958 { ATOMIC_RMW8_U_XCHG_I32_A32_S, ATOMIC_RMW8_U_XCHG_I32_A32 },
8959 { ATOMIC_RMW8_U_XCHG_I32_A64_S, ATOMIC_RMW8_U_XCHG_I32_A64 },
8960 { ATOMIC_RMW8_U_XCHG_I64_A32_S, ATOMIC_RMW8_U_XCHG_I64_A32 },
8961 { ATOMIC_RMW8_U_XCHG_I64_A64_S, ATOMIC_RMW8_U_XCHG_I64_A64 },
8962 { ATOMIC_RMW8_U_XOR_I32_A32_S, ATOMIC_RMW8_U_XOR_I32_A32 },
8963 { ATOMIC_RMW8_U_XOR_I32_A64_S, ATOMIC_RMW8_U_XOR_I32_A64 },
8964 { ATOMIC_RMW8_U_XOR_I64_A32_S, ATOMIC_RMW8_U_XOR_I64_A32 },
8965 { ATOMIC_RMW8_U_XOR_I64_A64_S, ATOMIC_RMW8_U_XOR_I64_A64 },
8966 { ATOMIC_RMW_ADD_I32_A32_S, ATOMIC_RMW_ADD_I32_A32 },
8967 { ATOMIC_RMW_ADD_I32_A64_S, ATOMIC_RMW_ADD_I32_A64 },
8968 { ATOMIC_RMW_ADD_I64_A32_S, ATOMIC_RMW_ADD_I64_A32 },
8969 { ATOMIC_RMW_ADD_I64_A64_S, ATOMIC_RMW_ADD_I64_A64 },
8970 { ATOMIC_RMW_AND_I32_A32_S, ATOMIC_RMW_AND_I32_A32 },
8971 { ATOMIC_RMW_AND_I32_A64_S, ATOMIC_RMW_AND_I32_A64 },
8972 { ATOMIC_RMW_AND_I64_A32_S, ATOMIC_RMW_AND_I64_A32 },
8973 { ATOMIC_RMW_AND_I64_A64_S, ATOMIC_RMW_AND_I64_A64 },
8974 { ATOMIC_RMW_CMPXCHG_I32_A32_S, ATOMIC_RMW_CMPXCHG_I32_A32 },
8975 { ATOMIC_RMW_CMPXCHG_I32_A64_S, ATOMIC_RMW_CMPXCHG_I32_A64 },
8976 { ATOMIC_RMW_CMPXCHG_I64_A32_S, ATOMIC_RMW_CMPXCHG_I64_A32 },
8977 { ATOMIC_RMW_CMPXCHG_I64_A64_S, ATOMIC_RMW_CMPXCHG_I64_A64 },
8978 { ATOMIC_RMW_OR_I32_A32_S, ATOMIC_RMW_OR_I32_A32 },
8979 { ATOMIC_RMW_OR_I32_A64_S, ATOMIC_RMW_OR_I32_A64 },
8980 { ATOMIC_RMW_OR_I64_A32_S, ATOMIC_RMW_OR_I64_A32 },
8981 { ATOMIC_RMW_OR_I64_A64_S, ATOMIC_RMW_OR_I64_A64 },
8982 { ATOMIC_RMW_SUB_I32_A32_S, ATOMIC_RMW_SUB_I32_A32 },
8983 { ATOMIC_RMW_SUB_I32_A64_S, ATOMIC_RMW_SUB_I32_A64 },
8984 { ATOMIC_RMW_SUB_I64_A32_S, ATOMIC_RMW_SUB_I64_A32 },
8985 { ATOMIC_RMW_SUB_I64_A64_S, ATOMIC_RMW_SUB_I64_A64 },
8986 { ATOMIC_RMW_XCHG_I32_A32_S, ATOMIC_RMW_XCHG_I32_A32 },
8987 { ATOMIC_RMW_XCHG_I32_A64_S, ATOMIC_RMW_XCHG_I32_A64 },
8988 { ATOMIC_RMW_XCHG_I64_A32_S, ATOMIC_RMW_XCHG_I64_A32 },
8989 { ATOMIC_RMW_XCHG_I64_A64_S, ATOMIC_RMW_XCHG_I64_A64 },
8990 { ATOMIC_RMW_XOR_I32_A32_S, ATOMIC_RMW_XOR_I32_A32 },
8991 { ATOMIC_RMW_XOR_I32_A64_S, ATOMIC_RMW_XOR_I32_A64 },
8992 { ATOMIC_RMW_XOR_I64_A32_S, ATOMIC_RMW_XOR_I64_A32 },
8993 { ATOMIC_RMW_XOR_I64_A64_S, ATOMIC_RMW_XOR_I64_A64 },
8994 { ATOMIC_STORE16_I32_A32_S, ATOMIC_STORE16_I32_A32 },
8995 { ATOMIC_STORE16_I32_A64_S, ATOMIC_STORE16_I32_A64 },
8996 { ATOMIC_STORE16_I64_A32_S, ATOMIC_STORE16_I64_A32 },
8997 { ATOMIC_STORE16_I64_A64_S, ATOMIC_STORE16_I64_A64 },
8998 { ATOMIC_STORE32_I64_A32_S, ATOMIC_STORE32_I64_A32 },
8999 { ATOMIC_STORE32_I64_A64_S, ATOMIC_STORE32_I64_A64 },
9000 { ATOMIC_STORE8_I32_A32_S, ATOMIC_STORE8_I32_A32 },
9001 { ATOMIC_STORE8_I32_A64_S, ATOMIC_STORE8_I32_A64 },
9002 { ATOMIC_STORE8_I64_A32_S, ATOMIC_STORE8_I64_A32 },
9003 { ATOMIC_STORE8_I64_A64_S, ATOMIC_STORE8_I64_A64 },
9004 { ATOMIC_STORE_I32_A32_S, ATOMIC_STORE_I32_A32 },
9005 { ATOMIC_STORE_I32_A64_S, ATOMIC_STORE_I32_A64 },
9006 { ATOMIC_STORE_I64_A32_S, ATOMIC_STORE_I64_A32 },
9007 { ATOMIC_STORE_I64_A64_S, ATOMIC_STORE_I64_A64 },
9008 { AVGR_U_I16x8_S, AVGR_U_I16x8 },
9009 { AVGR_U_I8x16_S, AVGR_U_I8x16 },
9010 { BITMASK_I16x8_S, BITMASK_I16x8 },
9011 { BITMASK_I32x4_S, BITMASK_I32x4 },
9012 { BITMASK_I64x2_S, BITMASK_I64x2 },
9013 { BITMASK_I8x16_S, BITMASK_I8x16 },
9014 { BITSELECT_S, BITSELECT },
9015 { BLOCK_S, BLOCK },
9016 { BR_IF_S, BR_IF },
9017 { BR_S, BR },
9018 { BR_TABLE_I32_S, BR_TABLE_I32 },
9019 { BR_TABLE_I64_S, BR_TABLE_I64 },
9020 { BR_UNLESS_S, BR_UNLESS },
9021 { CALL_INDIRECT_S, CALL_INDIRECT },
9022 { CALL_S, CALL },
9023 { CATCH_ALL_LEGACY_S, CATCH_ALL_LEGACY },
9024 { CATCH_ALL_REF_S, CATCH_ALL_REF },
9025 { CATCH_ALL_S, CATCH_ALL },
9026 { CATCH_LEGACY_S, CATCH_LEGACY },
9027 { CATCH_REF_S, CATCH_REF },
9028 { CATCH_S, CATCH },
9029 { CEIL_F16x8_S, CEIL_F16x8 },
9030 { CEIL_F32_S, CEIL_F32 },
9031 { CEIL_F32x4_S, CEIL_F32x4 },
9032 { CEIL_F64_S, CEIL_F64 },
9033 { CEIL_F64x2_S, CEIL_F64x2 },
9034 { CLZ_I32_S, CLZ_I32 },
9035 { CLZ_I64_S, CLZ_I64 },
9036 { CONST_F32_S, CONST_F32 },
9037 { CONST_F64_S, CONST_F64 },
9038 { CONST_I32_S, CONST_I32 },
9039 { CONST_I64_S, CONST_I64 },
9040 { CONST_V128_F32x4_S, CONST_V128_F32x4 },
9041 { CONST_V128_F64x2_S, CONST_V128_F64x2 },
9042 { CONST_V128_I16x8_S, CONST_V128_I16x8 },
9043 { CONST_V128_I32x4_S, CONST_V128_I32x4 },
9044 { CONST_V128_I64x2_S, CONST_V128_I64x2 },
9045 { CONST_V128_I8x16_S, CONST_V128_I8x16 },
9046 { COPYSIGN_F32_S, COPYSIGN_F32 },
9047 { COPYSIGN_F64_S, COPYSIGN_F64 },
9048 { COPY_EXNREF_S, COPY_EXNREF },
9049 { COPY_EXTERNREF_S, COPY_EXTERNREF },
9050 { COPY_F32_S, COPY_F32 },
9051 { COPY_F64_S, COPY_F64 },
9052 { COPY_FUNCREF_S, COPY_FUNCREF },
9053 { COPY_I32_S, COPY_I32 },
9054 { COPY_I64_S, COPY_I64 },
9055 { COPY_V128_S, COPY_V128 },
9056 { CTZ_I32_S, CTZ_I32 },
9057 { CTZ_I64_S, CTZ_I64 },
9058 { DATA_DROP_S, DATA_DROP },
9059 { DEBUG_UNREACHABLE_S, DEBUG_UNREACHABLE },
9060 { DELEGATE_S, DELEGATE },
9061 { DIV_F16x8_S, DIV_F16x8 },
9062 { DIV_F32_S, DIV_F32 },
9063 { DIV_F32x4_S, DIV_F32x4 },
9064 { DIV_F64_S, DIV_F64 },
9065 { DIV_F64x2_S, DIV_F64x2 },
9066 { DIV_S_I32_S, DIV_S_I32 },
9067 { DIV_S_I64_S, DIV_S_I64 },
9068 { DIV_U_I32_S, DIV_U_I32 },
9069 { DIV_U_I64_S, DIV_U_I64 },
9070 { DOT_S, DOT },
9071 { DROP_EXNREF_S, DROP_EXNREF },
9072 { DROP_EXTERNREF_S, DROP_EXTERNREF },
9073 { DROP_F32_S, DROP_F32 },
9074 { DROP_F64_S, DROP_F64 },
9075 { DROP_FUNCREF_S, DROP_FUNCREF },
9076 { DROP_I32_S, DROP_I32 },
9077 { DROP_I64_S, DROP_I64 },
9078 { DROP_V128_S, DROP_V128 },
9079 { ELSE_S, ELSE },
9080 { END_BLOCK_S, END_BLOCK },
9081 { END_FUNCTION_S, END_FUNCTION },
9082 { END_IF_S, END_IF },
9083 { END_LOOP_S, END_LOOP },
9084 { END_S, END },
9085 { END_TRY_S, END_TRY },
9086 { END_TRY_TABLE_S, END_TRY_TABLE },
9087 { EQZ_I32_S, EQZ_I32 },
9088 { EQZ_I64_S, EQZ_I64 },
9089 { EQ_F16x8_S, EQ_F16x8 },
9090 { EQ_F32_S, EQ_F32 },
9091 { EQ_F32x4_S, EQ_F32x4 },
9092 { EQ_F64_S, EQ_F64 },
9093 { EQ_F64x2_S, EQ_F64x2 },
9094 { EQ_I16x8_S, EQ_I16x8 },
9095 { EQ_I32_S, EQ_I32 },
9096 { EQ_I32x4_S, EQ_I32x4 },
9097 { EQ_I64_S, EQ_I64 },
9098 { EQ_I64x2_S, EQ_I64x2 },
9099 { EQ_I8x16_S, EQ_I8x16 },
9100 { EXTMUL_HIGH_S_I16x8_S, EXTMUL_HIGH_S_I16x8 },
9101 { EXTMUL_HIGH_S_I32x4_S, EXTMUL_HIGH_S_I32x4 },
9102 { EXTMUL_HIGH_S_I64x2_S, EXTMUL_HIGH_S_I64x2 },
9103 { EXTMUL_HIGH_U_I16x8_S, EXTMUL_HIGH_U_I16x8 },
9104 { EXTMUL_HIGH_U_I32x4_S, EXTMUL_HIGH_U_I32x4 },
9105 { EXTMUL_HIGH_U_I64x2_S, EXTMUL_HIGH_U_I64x2 },
9106 { EXTMUL_LOW_S_I16x8_S, EXTMUL_LOW_S_I16x8 },
9107 { EXTMUL_LOW_S_I32x4_S, EXTMUL_LOW_S_I32x4 },
9108 { EXTMUL_LOW_S_I64x2_S, EXTMUL_LOW_S_I64x2 },
9109 { EXTMUL_LOW_U_I16x8_S, EXTMUL_LOW_U_I16x8 },
9110 { EXTMUL_LOW_U_I32x4_S, EXTMUL_LOW_U_I32x4 },
9111 { EXTMUL_LOW_U_I64x2_S, EXTMUL_LOW_U_I64x2 },
9112 { EXTRACT_LANE_F16x8_S, EXTRACT_LANE_F16x8 },
9113 { EXTRACT_LANE_F32x4_S, EXTRACT_LANE_F32x4 },
9114 { EXTRACT_LANE_F64x2_S, EXTRACT_LANE_F64x2 },
9115 { EXTRACT_LANE_I16x8_s_S, EXTRACT_LANE_I16x8_s },
9116 { EXTRACT_LANE_I16x8_u_S, EXTRACT_LANE_I16x8_u },
9117 { EXTRACT_LANE_I32x4_S, EXTRACT_LANE_I32x4 },
9118 { EXTRACT_LANE_I64x2_S, EXTRACT_LANE_I64x2 },
9119 { EXTRACT_LANE_I8x16_s_S, EXTRACT_LANE_I8x16_s },
9120 { EXTRACT_LANE_I8x16_u_S, EXTRACT_LANE_I8x16_u },
9121 { F32_CONVERT_S_I32_S, F32_CONVERT_S_I32 },
9122 { F32_CONVERT_S_I64_S, F32_CONVERT_S_I64 },
9123 { F32_CONVERT_U_I32_S, F32_CONVERT_U_I32 },
9124 { F32_CONVERT_U_I64_S, F32_CONVERT_U_I64 },
9125 { F32_DEMOTE_F64_S, F32_DEMOTE_F64 },
9126 { F32_REINTERPRET_I32_S, F32_REINTERPRET_I32 },
9127 { F64_CONVERT_S_I32_S, F64_CONVERT_S_I32 },
9128 { F64_CONVERT_S_I64_S, F64_CONVERT_S_I64 },
9129 { F64_CONVERT_U_I32_S, F64_CONVERT_U_I32 },
9130 { F64_CONVERT_U_I64_S, F64_CONVERT_U_I64 },
9131 { F64_PROMOTE_F32_S, F64_PROMOTE_F32 },
9132 { F64_REINTERPRET_I64_S, F64_REINTERPRET_I64 },
9133 { FALLTHROUGH_RETURN_S, FALLTHROUGH_RETURN },
9134 { FLOOR_F16x8_S, FLOOR_F16x8 },
9135 { FLOOR_F32_S, FLOOR_F32 },
9136 { FLOOR_F32x4_S, FLOOR_F32x4 },
9137 { FLOOR_F64_S, FLOOR_F64 },
9138 { FLOOR_F64x2_S, FLOOR_F64x2 },
9139 { FP_TO_SINT_I32_F32_S, FP_TO_SINT_I32_F32 },
9140 { FP_TO_SINT_I32_F64_S, FP_TO_SINT_I32_F64 },
9141 { FP_TO_SINT_I64_F32_S, FP_TO_SINT_I64_F32 },
9142 { FP_TO_SINT_I64_F64_S, FP_TO_SINT_I64_F64 },
9143 { FP_TO_UINT_I32_F32_S, FP_TO_UINT_I32_F32 },
9144 { FP_TO_UINT_I32_F64_S, FP_TO_UINT_I32_F64 },
9145 { FP_TO_UINT_I64_F32_S, FP_TO_UINT_I64_F32 },
9146 { FP_TO_UINT_I64_F64_S, FP_TO_UINT_I64_F64 },
9147 { GE_F16x8_S, GE_F16x8 },
9148 { GE_F32_S, GE_F32 },
9149 { GE_F32x4_S, GE_F32x4 },
9150 { GE_F64_S, GE_F64 },
9151 { GE_F64x2_S, GE_F64x2 },
9152 { GE_S_I16x8_S, GE_S_I16x8 },
9153 { GE_S_I32_S, GE_S_I32 },
9154 { GE_S_I32x4_S, GE_S_I32x4 },
9155 { GE_S_I64_S, GE_S_I64 },
9156 { GE_S_I64x2_S, GE_S_I64x2 },
9157 { GE_S_I8x16_S, GE_S_I8x16 },
9158 { GE_U_I16x8_S, GE_U_I16x8 },
9159 { GE_U_I32_S, GE_U_I32 },
9160 { GE_U_I32x4_S, GE_U_I32x4 },
9161 { GE_U_I64_S, GE_U_I64 },
9162 { GE_U_I8x16_S, GE_U_I8x16 },
9163 { GLOBAL_GET_EXNREF_S, GLOBAL_GET_EXNREF },
9164 { GLOBAL_GET_EXTERNREF_S, GLOBAL_GET_EXTERNREF },
9165 { GLOBAL_GET_F32_S, GLOBAL_GET_F32 },
9166 { GLOBAL_GET_F64_S, GLOBAL_GET_F64 },
9167 { GLOBAL_GET_FUNCREF_S, GLOBAL_GET_FUNCREF },
9168 { GLOBAL_GET_I32_S, GLOBAL_GET_I32 },
9169 { GLOBAL_GET_I64_S, GLOBAL_GET_I64 },
9170 { GLOBAL_GET_V128_S, GLOBAL_GET_V128 },
9171 { GLOBAL_SET_EXNREF_S, GLOBAL_SET_EXNREF },
9172 { GLOBAL_SET_EXTERNREF_S, GLOBAL_SET_EXTERNREF },
9173 { GLOBAL_SET_F32_S, GLOBAL_SET_F32 },
9174 { GLOBAL_SET_F64_S, GLOBAL_SET_F64 },
9175 { GLOBAL_SET_FUNCREF_S, GLOBAL_SET_FUNCREF },
9176 { GLOBAL_SET_I32_S, GLOBAL_SET_I32 },
9177 { GLOBAL_SET_I64_S, GLOBAL_SET_I64 },
9178 { GLOBAL_SET_V128_S, GLOBAL_SET_V128 },
9179 { GT_F16x8_S, GT_F16x8 },
9180 { GT_F32_S, GT_F32 },
9181 { GT_F32x4_S, GT_F32x4 },
9182 { GT_F64_S, GT_F64 },
9183 { GT_F64x2_S, GT_F64x2 },
9184 { GT_S_I16x8_S, GT_S_I16x8 },
9185 { GT_S_I32_S, GT_S_I32 },
9186 { GT_S_I32x4_S, GT_S_I32x4 },
9187 { GT_S_I64_S, GT_S_I64 },
9188 { GT_S_I64x2_S, GT_S_I64x2 },
9189 { GT_S_I8x16_S, GT_S_I8x16 },
9190 { GT_U_I16x8_S, GT_U_I16x8 },
9191 { GT_U_I32_S, GT_U_I32 },
9192 { GT_U_I32x4_S, GT_U_I32x4 },
9193 { GT_U_I64_S, GT_U_I64 },
9194 { GT_U_I8x16_S, GT_U_I8x16 },
9195 { I32_EXTEND16_S_I32_S, I32_EXTEND16_S_I32 },
9196 { I32_EXTEND8_S_I32_S, I32_EXTEND8_S_I32 },
9197 { I32_REINTERPRET_F32_S, I32_REINTERPRET_F32 },
9198 { I32_TRUNC_S_F32_S, I32_TRUNC_S_F32 },
9199 { I32_TRUNC_S_F64_S, I32_TRUNC_S_F64 },
9200 { I32_TRUNC_S_SAT_F32_S, I32_TRUNC_S_SAT_F32 },
9201 { I32_TRUNC_S_SAT_F64_S, I32_TRUNC_S_SAT_F64 },
9202 { I32_TRUNC_U_F32_S, I32_TRUNC_U_F32 },
9203 { I32_TRUNC_U_F64_S, I32_TRUNC_U_F64 },
9204 { I32_TRUNC_U_SAT_F32_S, I32_TRUNC_U_SAT_F32 },
9205 { I32_TRUNC_U_SAT_F64_S, I32_TRUNC_U_SAT_F64 },
9206 { I32_WRAP_I64_S, I32_WRAP_I64 },
9207 { I64_ADD128_S, I64_ADD128 },
9208 { I64_EXTEND16_S_I64_S, I64_EXTEND16_S_I64 },
9209 { I64_EXTEND32_S_I64_S, I64_EXTEND32_S_I64 },
9210 { I64_EXTEND8_S_I64_S, I64_EXTEND8_S_I64 },
9211 { I64_EXTEND_S_I32_S, I64_EXTEND_S_I32 },
9212 { I64_EXTEND_U_I32_S, I64_EXTEND_U_I32 },
9213 { I64_MUL_WIDE_S_S, I64_MUL_WIDE_S },
9214 { I64_MUL_WIDE_U_S, I64_MUL_WIDE_U },
9215 { I64_REINTERPRET_F64_S, I64_REINTERPRET_F64 },
9216 { I64_SUB128_S, I64_SUB128 },
9217 { I64_TRUNC_S_F32_S, I64_TRUNC_S_F32 },
9218 { I64_TRUNC_S_F64_S, I64_TRUNC_S_F64 },
9219 { I64_TRUNC_S_SAT_F32_S, I64_TRUNC_S_SAT_F32 },
9220 { I64_TRUNC_S_SAT_F64_S, I64_TRUNC_S_SAT_F64 },
9221 { I64_TRUNC_U_F32_S, I64_TRUNC_U_F32 },
9222 { I64_TRUNC_U_F64_S, I64_TRUNC_U_F64 },
9223 { I64_TRUNC_U_SAT_F32_S, I64_TRUNC_U_SAT_F32 },
9224 { I64_TRUNC_U_SAT_F64_S, I64_TRUNC_U_SAT_F64 },
9225 { IF_S, IF },
9226 { LANESELECT_I16x8_S, LANESELECT_I16x8 },
9227 { LANESELECT_I32x4_S, LANESELECT_I32x4 },
9228 { LANESELECT_I64x2_S, LANESELECT_I64x2 },
9229 { LANESELECT_I8x16_S, LANESELECT_I8x16 },
9230 { LE_F16x8_S, LE_F16x8 },
9231 { LE_F32_S, LE_F32 },
9232 { LE_F32x4_S, LE_F32x4 },
9233 { LE_F64_S, LE_F64 },
9234 { LE_F64x2_S, LE_F64x2 },
9235 { LE_S_I16x8_S, LE_S_I16x8 },
9236 { LE_S_I32_S, LE_S_I32 },
9237 { LE_S_I32x4_S, LE_S_I32x4 },
9238 { LE_S_I64_S, LE_S_I64 },
9239 { LE_S_I64x2_S, LE_S_I64x2 },
9240 { LE_S_I8x16_S, LE_S_I8x16 },
9241 { LE_U_I16x8_S, LE_U_I16x8 },
9242 { LE_U_I32_S, LE_U_I32 },
9243 { LE_U_I32x4_S, LE_U_I32x4 },
9244 { LE_U_I64_S, LE_U_I64 },
9245 { LE_U_I8x16_S, LE_U_I8x16 },
9246 { LOAD16_SPLAT_A32_S, LOAD16_SPLAT_A32 },
9247 { LOAD16_SPLAT_A64_S, LOAD16_SPLAT_A64 },
9248 { LOAD16_S_I32_A32_S, LOAD16_S_I32_A32 },
9249 { LOAD16_S_I32_A64_S, LOAD16_S_I32_A64 },
9250 { LOAD16_S_I64_A32_S, LOAD16_S_I64_A32 },
9251 { LOAD16_S_I64_A64_S, LOAD16_S_I64_A64 },
9252 { LOAD16_U_I32_A32_S, LOAD16_U_I32_A32 },
9253 { LOAD16_U_I32_A64_S, LOAD16_U_I32_A64 },
9254 { LOAD16_U_I64_A32_S, LOAD16_U_I64_A32 },
9255 { LOAD16_U_I64_A64_S, LOAD16_U_I64_A64 },
9256 { LOAD32_SPLAT_A32_S, LOAD32_SPLAT_A32 },
9257 { LOAD32_SPLAT_A64_S, LOAD32_SPLAT_A64 },
9258 { LOAD32_S_I64_A32_S, LOAD32_S_I64_A32 },
9259 { LOAD32_S_I64_A64_S, LOAD32_S_I64_A64 },
9260 { LOAD32_U_I64_A32_S, LOAD32_U_I64_A32 },
9261 { LOAD32_U_I64_A64_S, LOAD32_U_I64_A64 },
9262 { LOAD64_SPLAT_A32_S, LOAD64_SPLAT_A32 },
9263 { LOAD64_SPLAT_A64_S, LOAD64_SPLAT_A64 },
9264 { LOAD8_SPLAT_A32_S, LOAD8_SPLAT_A32 },
9265 { LOAD8_SPLAT_A64_S, LOAD8_SPLAT_A64 },
9266 { LOAD8_S_I32_A32_S, LOAD8_S_I32_A32 },
9267 { LOAD8_S_I32_A64_S, LOAD8_S_I32_A64 },
9268 { LOAD8_S_I64_A32_S, LOAD8_S_I64_A32 },
9269 { LOAD8_S_I64_A64_S, LOAD8_S_I64_A64 },
9270 { LOAD8_U_I32_A32_S, LOAD8_U_I32_A32 },
9271 { LOAD8_U_I32_A64_S, LOAD8_U_I32_A64 },
9272 { LOAD8_U_I64_A32_S, LOAD8_U_I64_A32 },
9273 { LOAD8_U_I64_A64_S, LOAD8_U_I64_A64 },
9274 { LOAD_EXTEND_S_I16x8_A32_S, LOAD_EXTEND_S_I16x8_A32 },
9275 { LOAD_EXTEND_S_I16x8_A64_S, LOAD_EXTEND_S_I16x8_A64 },
9276 { LOAD_EXTEND_S_I32x4_A32_S, LOAD_EXTEND_S_I32x4_A32 },
9277 { LOAD_EXTEND_S_I32x4_A64_S, LOAD_EXTEND_S_I32x4_A64 },
9278 { LOAD_EXTEND_S_I64x2_A32_S, LOAD_EXTEND_S_I64x2_A32 },
9279 { LOAD_EXTEND_S_I64x2_A64_S, LOAD_EXTEND_S_I64x2_A64 },
9280 { LOAD_EXTEND_U_I16x8_A32_S, LOAD_EXTEND_U_I16x8_A32 },
9281 { LOAD_EXTEND_U_I16x8_A64_S, LOAD_EXTEND_U_I16x8_A64 },
9282 { LOAD_EXTEND_U_I32x4_A32_S, LOAD_EXTEND_U_I32x4_A32 },
9283 { LOAD_EXTEND_U_I32x4_A64_S, LOAD_EXTEND_U_I32x4_A64 },
9284 { LOAD_EXTEND_U_I64x2_A32_S, LOAD_EXTEND_U_I64x2_A32 },
9285 { LOAD_EXTEND_U_I64x2_A64_S, LOAD_EXTEND_U_I64x2_A64 },
9286 { LOAD_F16_F32_A32_S, LOAD_F16_F32_A32 },
9287 { LOAD_F16_F32_A64_S, LOAD_F16_F32_A64 },
9288 { LOAD_F32_A32_S, LOAD_F32_A32 },
9289 { LOAD_F32_A64_S, LOAD_F32_A64 },
9290 { LOAD_F64_A32_S, LOAD_F64_A32 },
9291 { LOAD_F64_A64_S, LOAD_F64_A64 },
9292 { LOAD_I32_A32_S, LOAD_I32_A32 },
9293 { LOAD_I32_A64_S, LOAD_I32_A64 },
9294 { LOAD_I64_A32_S, LOAD_I64_A32 },
9295 { LOAD_I64_A64_S, LOAD_I64_A64 },
9296 { LOAD_LANE_16_A32_S, LOAD_LANE_16_A32 },
9297 { LOAD_LANE_16_A64_S, LOAD_LANE_16_A64 },
9298 { LOAD_LANE_32_A32_S, LOAD_LANE_32_A32 },
9299 { LOAD_LANE_32_A64_S, LOAD_LANE_32_A64 },
9300 { LOAD_LANE_64_A32_S, LOAD_LANE_64_A32 },
9301 { LOAD_LANE_64_A64_S, LOAD_LANE_64_A64 },
9302 { LOAD_LANE_8_A32_S, LOAD_LANE_8_A32 },
9303 { LOAD_LANE_8_A64_S, LOAD_LANE_8_A64 },
9304 { LOAD_V128_A32_S, LOAD_V128_A32 },
9305 { LOAD_V128_A64_S, LOAD_V128_A64 },
9306 { LOAD_ZERO_32_A32_S, LOAD_ZERO_32_A32 },
9307 { LOAD_ZERO_32_A64_S, LOAD_ZERO_32_A64 },
9308 { LOAD_ZERO_64_A32_S, LOAD_ZERO_64_A32 },
9309 { LOAD_ZERO_64_A64_S, LOAD_ZERO_64_A64 },
9310 { LOCAL_GET_EXNREF_S, LOCAL_GET_EXNREF },
9311 { LOCAL_GET_EXTERNREF_S, LOCAL_GET_EXTERNREF },
9312 { LOCAL_GET_F32_S, LOCAL_GET_F32 },
9313 { LOCAL_GET_F64_S, LOCAL_GET_F64 },
9314 { LOCAL_GET_FUNCREF_S, LOCAL_GET_FUNCREF },
9315 { LOCAL_GET_I32_S, LOCAL_GET_I32 },
9316 { LOCAL_GET_I64_S, LOCAL_GET_I64 },
9317 { LOCAL_GET_V128_S, LOCAL_GET_V128 },
9318 { LOCAL_SET_EXNREF_S, LOCAL_SET_EXNREF },
9319 { LOCAL_SET_EXTERNREF_S, LOCAL_SET_EXTERNREF },
9320 { LOCAL_SET_F32_S, LOCAL_SET_F32 },
9321 { LOCAL_SET_F64_S, LOCAL_SET_F64 },
9322 { LOCAL_SET_FUNCREF_S, LOCAL_SET_FUNCREF },
9323 { LOCAL_SET_I32_S, LOCAL_SET_I32 },
9324 { LOCAL_SET_I64_S, LOCAL_SET_I64 },
9325 { LOCAL_SET_V128_S, LOCAL_SET_V128 },
9326 { LOCAL_TEE_EXNREF_S, LOCAL_TEE_EXNREF },
9327 { LOCAL_TEE_EXTERNREF_S, LOCAL_TEE_EXTERNREF },
9328 { LOCAL_TEE_F32_S, LOCAL_TEE_F32 },
9329 { LOCAL_TEE_F64_S, LOCAL_TEE_F64 },
9330 { LOCAL_TEE_FUNCREF_S, LOCAL_TEE_FUNCREF },
9331 { LOCAL_TEE_I32_S, LOCAL_TEE_I32 },
9332 { LOCAL_TEE_I64_S, LOCAL_TEE_I64 },
9333 { LOCAL_TEE_V128_S, LOCAL_TEE_V128 },
9334 { LOOP_S, LOOP },
9335 { LT_F16x8_S, LT_F16x8 },
9336 { LT_F32_S, LT_F32 },
9337 { LT_F32x4_S, LT_F32x4 },
9338 { LT_F64_S, LT_F64 },
9339 { LT_F64x2_S, LT_F64x2 },
9340 { LT_S_I16x8_S, LT_S_I16x8 },
9341 { LT_S_I32_S, LT_S_I32 },
9342 { LT_S_I32x4_S, LT_S_I32x4 },
9343 { LT_S_I64_S, LT_S_I64 },
9344 { LT_S_I64x2_S, LT_S_I64x2 },
9345 { LT_S_I8x16_S, LT_S_I8x16 },
9346 { LT_U_I16x8_S, LT_U_I16x8 },
9347 { LT_U_I32_S, LT_U_I32 },
9348 { LT_U_I32x4_S, LT_U_I32x4 },
9349 { LT_U_I64_S, LT_U_I64 },
9350 { LT_U_I8x16_S, LT_U_I8x16 },
9351 { MADD_F16x8_S, MADD_F16x8 },
9352 { MADD_F32x4_S, MADD_F32x4 },
9353 { MADD_F64x2_S, MADD_F64x2 },
9354 { MAX_F16x8_S, MAX_F16x8 },
9355 { MAX_F32_S, MAX_F32 },
9356 { MAX_F32x4_S, MAX_F32x4 },
9357 { MAX_F64_S, MAX_F64 },
9358 { MAX_F64x2_S, MAX_F64x2 },
9359 { MAX_S_I16x8_S, MAX_S_I16x8 },
9360 { MAX_S_I32x4_S, MAX_S_I32x4 },
9361 { MAX_S_I8x16_S, MAX_S_I8x16 },
9362 { MAX_U_I16x8_S, MAX_U_I16x8 },
9363 { MAX_U_I32x4_S, MAX_U_I32x4 },
9364 { MAX_U_I8x16_S, MAX_U_I8x16 },
9365 { MEMCPY_A32_S, MEMCPY_A32 },
9366 { MEMCPY_A64_S, MEMCPY_A64 },
9367 { MEMORY_ATOMIC_NOTIFY_A32_S, MEMORY_ATOMIC_NOTIFY_A32 },
9368 { MEMORY_ATOMIC_NOTIFY_A64_S, MEMORY_ATOMIC_NOTIFY_A64 },
9369 { MEMORY_ATOMIC_WAIT32_A32_S, MEMORY_ATOMIC_WAIT32_A32 },
9370 { MEMORY_ATOMIC_WAIT32_A64_S, MEMORY_ATOMIC_WAIT32_A64 },
9371 { MEMORY_ATOMIC_WAIT64_A32_S, MEMORY_ATOMIC_WAIT64_A32 },
9372 { MEMORY_ATOMIC_WAIT64_A64_S, MEMORY_ATOMIC_WAIT64_A64 },
9373 { MEMORY_COPY_A32_S, MEMORY_COPY_A32 },
9374 { MEMORY_COPY_A64_S, MEMORY_COPY_A64 },
9375 { MEMORY_FILL_A32_S, MEMORY_FILL_A32 },
9376 { MEMORY_FILL_A64_S, MEMORY_FILL_A64 },
9377 { MEMORY_INIT_A32_S, MEMORY_INIT_A32 },
9378 { MEMORY_INIT_A64_S, MEMORY_INIT_A64 },
9379 { MEMSET_A32_S, MEMSET_A32 },
9380 { MEMSET_A64_S, MEMSET_A64 },
9381 { MIN_F16x8_S, MIN_F16x8 },
9382 { MIN_F32_S, MIN_F32 },
9383 { MIN_F32x4_S, MIN_F32x4 },
9384 { MIN_F64_S, MIN_F64 },
9385 { MIN_F64x2_S, MIN_F64x2 },
9386 { MIN_S_I16x8_S, MIN_S_I16x8 },
9387 { MIN_S_I32x4_S, MIN_S_I32x4 },
9388 { MIN_S_I8x16_S, MIN_S_I8x16 },
9389 { MIN_U_I16x8_S, MIN_U_I16x8 },
9390 { MIN_U_I32x4_S, MIN_U_I32x4 },
9391 { MIN_U_I8x16_S, MIN_U_I8x16 },
9392 { MUL_F16x8_S, MUL_F16x8 },
9393 { MUL_F32_S, MUL_F32 },
9394 { MUL_F32x4_S, MUL_F32x4 },
9395 { MUL_F64_S, MUL_F64 },
9396 { MUL_F64x2_S, MUL_F64x2 },
9397 { MUL_I16x8_S, MUL_I16x8 },
9398 { MUL_I32_S, MUL_I32 },
9399 { MUL_I32x4_S, MUL_I32x4 },
9400 { MUL_I64_S, MUL_I64 },
9401 { MUL_I64x2_S, MUL_I64x2 },
9402 { NARROW_S_I16x8_S, NARROW_S_I16x8 },
9403 { NARROW_S_I8x16_S, NARROW_S_I8x16 },
9404 { NARROW_U_I16x8_S, NARROW_U_I16x8 },
9405 { NARROW_U_I8x16_S, NARROW_U_I8x16 },
9406 { NEAREST_F16x8_S, NEAREST_F16x8 },
9407 { NEAREST_F32_S, NEAREST_F32 },
9408 { NEAREST_F32x4_S, NEAREST_F32x4 },
9409 { NEAREST_F64_S, NEAREST_F64 },
9410 { NEAREST_F64x2_S, NEAREST_F64x2 },
9411 { NEG_F16x8_S, NEG_F16x8 },
9412 { NEG_F32_S, NEG_F32 },
9413 { NEG_F32x4_S, NEG_F32x4 },
9414 { NEG_F64_S, NEG_F64 },
9415 { NEG_F64x2_S, NEG_F64x2 },
9416 { NEG_I16x8_S, NEG_I16x8 },
9417 { NEG_I32x4_S, NEG_I32x4 },
9418 { NEG_I64x2_S, NEG_I64x2 },
9419 { NEG_I8x16_S, NEG_I8x16 },
9420 { NE_F16x8_S, NE_F16x8 },
9421 { NE_F32_S, NE_F32 },
9422 { NE_F32x4_S, NE_F32x4 },
9423 { NE_F64_S, NE_F64 },
9424 { NE_F64x2_S, NE_F64x2 },
9425 { NE_I16x8_S, NE_I16x8 },
9426 { NE_I32_S, NE_I32 },
9427 { NE_I32x4_S, NE_I32x4 },
9428 { NE_I64_S, NE_I64 },
9429 { NE_I64x2_S, NE_I64x2 },
9430 { NE_I8x16_S, NE_I8x16 },
9431 { NMADD_F16x8_S, NMADD_F16x8 },
9432 { NMADD_F32x4_S, NMADD_F32x4 },
9433 { NMADD_F64x2_S, NMADD_F64x2 },
9434 { NOP_S, NOP },
9435 { NOT_S, NOT },
9436 { OR_I32_S, OR_I32 },
9437 { OR_I64_S, OR_I64 },
9438 { OR_S, OR },
9439 { PMAX_F16x8_S, PMAX_F16x8 },
9440 { PMAX_F32x4_S, PMAX_F32x4 },
9441 { PMAX_F64x2_S, PMAX_F64x2 },
9442 { PMIN_F16x8_S, PMIN_F16x8 },
9443 { PMIN_F32x4_S, PMIN_F32x4 },
9444 { PMIN_F64x2_S, PMIN_F64x2 },
9445 { POPCNT_I32_S, POPCNT_I32 },
9446 { POPCNT_I64_S, POPCNT_I64 },
9447 { POPCNT_I8x16_S, POPCNT_I8x16 },
9448 { Q15MULR_SAT_S_I16x8_S, Q15MULR_SAT_S_I16x8 },
9449 { REF_FUNC_S, REF_FUNC },
9450 { REF_IS_NULL_EXNREF_S, REF_IS_NULL_EXNREF },
9451 { REF_IS_NULL_EXTERNREF_S, REF_IS_NULL_EXTERNREF },
9452 { REF_IS_NULL_FUNCREF_S, REF_IS_NULL_FUNCREF },
9453 { REF_NULL_EXNREF_S, REF_NULL_EXNREF },
9454 { REF_NULL_EXTERNREF_S, REF_NULL_EXTERNREF },
9455 { REF_NULL_FUNCREF_S, REF_NULL_FUNCREF },
9456 { REF_TEST_FUNCREF_S, REF_TEST_FUNCREF },
9457 { RELAXED_DOT_ADD_S, RELAXED_DOT_ADD },
9458 { RELAXED_DOT_BFLOAT_S, RELAXED_DOT_BFLOAT },
9459 { RELAXED_DOT_S, RELAXED_DOT },
9460 { RELAXED_Q15MULR_S_I16x8_S, RELAXED_Q15MULR_S_I16x8 },
9461 { RELAXED_SWIZZLE_S, RELAXED_SWIZZLE },
9462 { REM_S_I32_S, REM_S_I32 },
9463 { REM_S_I64_S, REM_S_I64 },
9464 { REM_U_I32_S, REM_U_I32 },
9465 { REM_U_I64_S, REM_U_I64 },
9466 { REPLACE_LANE_F16x8_S, REPLACE_LANE_F16x8 },
9467 { REPLACE_LANE_F32x4_S, REPLACE_LANE_F32x4 },
9468 { REPLACE_LANE_F64x2_S, REPLACE_LANE_F64x2 },
9469 { REPLACE_LANE_I16x8_S, REPLACE_LANE_I16x8 },
9470 { REPLACE_LANE_I32x4_S, REPLACE_LANE_I32x4 },
9471 { REPLACE_LANE_I64x2_S, REPLACE_LANE_I64x2 },
9472 { REPLACE_LANE_I8x16_S, REPLACE_LANE_I8x16 },
9473 { RETHROW_S, RETHROW },
9474 { RETURN_S, RETURN },
9475 { RET_CALL_INDIRECT_S, RET_CALL_INDIRECT },
9476 { RET_CALL_S, RET_CALL },
9477 { ROTL_I32_S, ROTL_I32 },
9478 { ROTL_I64_S, ROTL_I64 },
9479 { ROTR_I32_S, ROTR_I32 },
9480 { ROTR_I64_S, ROTR_I64 },
9481 { SELECT_EXNREF_S, SELECT_EXNREF },
9482 { SELECT_EXTERNREF_S, SELECT_EXTERNREF },
9483 { SELECT_F32_S, SELECT_F32 },
9484 { SELECT_F64_S, SELECT_F64 },
9485 { SELECT_FUNCREF_S, SELECT_FUNCREF },
9486 { SELECT_I32_S, SELECT_I32 },
9487 { SELECT_I64_S, SELECT_I64 },
9488 { SELECT_V128_S, SELECT_V128 },
9489 { SHL_I16x8_S, SHL_I16x8 },
9490 { SHL_I32_S, SHL_I32 },
9491 { SHL_I32x4_S, SHL_I32x4 },
9492 { SHL_I64_S, SHL_I64 },
9493 { SHL_I64x2_S, SHL_I64x2 },
9494 { SHL_I8x16_S, SHL_I8x16 },
9495 { SHR_S_I16x8_S, SHR_S_I16x8 },
9496 { SHR_S_I32_S, SHR_S_I32 },
9497 { SHR_S_I32x4_S, SHR_S_I32x4 },
9498 { SHR_S_I64_S, SHR_S_I64 },
9499 { SHR_S_I64x2_S, SHR_S_I64x2 },
9500 { SHR_S_I8x16_S, SHR_S_I8x16 },
9501 { SHR_U_I16x8_S, SHR_U_I16x8 },
9502 { SHR_U_I32_S, SHR_U_I32 },
9503 { SHR_U_I32x4_S, SHR_U_I32x4 },
9504 { SHR_U_I64_S, SHR_U_I64 },
9505 { SHR_U_I64x2_S, SHR_U_I64x2 },
9506 { SHR_U_I8x16_S, SHR_U_I8x16 },
9507 { SHUFFLE_S, SHUFFLE },
9508 { SIMD_RELAXED_FMAX_F32x4_S, SIMD_RELAXED_FMAX_F32x4 },
9509 { SIMD_RELAXED_FMAX_F64x2_S, SIMD_RELAXED_FMAX_F64x2 },
9510 { SIMD_RELAXED_FMIN_F32x4_S, SIMD_RELAXED_FMIN_F32x4 },
9511 { SIMD_RELAXED_FMIN_F64x2_S, SIMD_RELAXED_FMIN_F64x2 },
9512 { SPLAT_F16x8_S, SPLAT_F16x8 },
9513 { SPLAT_F32x4_S, SPLAT_F32x4 },
9514 { SPLAT_F64x2_S, SPLAT_F64x2 },
9515 { SPLAT_I16x8_S, SPLAT_I16x8 },
9516 { SPLAT_I32x4_S, SPLAT_I32x4 },
9517 { SPLAT_I64x2_S, SPLAT_I64x2 },
9518 { SPLAT_I8x16_S, SPLAT_I8x16 },
9519 { SQRT_F16x8_S, SQRT_F16x8 },
9520 { SQRT_F32_S, SQRT_F32 },
9521 { SQRT_F32x4_S, SQRT_F32x4 },
9522 { SQRT_F64_S, SQRT_F64 },
9523 { SQRT_F64x2_S, SQRT_F64x2 },
9524 { STORE16_I32_A32_S, STORE16_I32_A32 },
9525 { STORE16_I32_A64_S, STORE16_I32_A64 },
9526 { STORE16_I64_A32_S, STORE16_I64_A32 },
9527 { STORE16_I64_A64_S, STORE16_I64_A64 },
9528 { STORE32_I64_A32_S, STORE32_I64_A32 },
9529 { STORE32_I64_A64_S, STORE32_I64_A64 },
9530 { STORE8_I32_A32_S, STORE8_I32_A32 },
9531 { STORE8_I32_A64_S, STORE8_I32_A64 },
9532 { STORE8_I64_A32_S, STORE8_I64_A32 },
9533 { STORE8_I64_A64_S, STORE8_I64_A64 },
9534 { STORE_F16_F32_A32_S, STORE_F16_F32_A32 },
9535 { STORE_F16_F32_A64_S, STORE_F16_F32_A64 },
9536 { STORE_F32_A32_S, STORE_F32_A32 },
9537 { STORE_F32_A64_S, STORE_F32_A64 },
9538 { STORE_F64_A32_S, STORE_F64_A32 },
9539 { STORE_F64_A64_S, STORE_F64_A64 },
9540 { STORE_I32_A32_S, STORE_I32_A32 },
9541 { STORE_I32_A64_S, STORE_I32_A64 },
9542 { STORE_I64_A32_S, STORE_I64_A32 },
9543 { STORE_I64_A64_S, STORE_I64_A64 },
9544 { STORE_LANE_I16x8_A32_S, STORE_LANE_I16x8_A32 },
9545 { STORE_LANE_I16x8_A64_S, STORE_LANE_I16x8_A64 },
9546 { STORE_LANE_I32x4_A32_S, STORE_LANE_I32x4_A32 },
9547 { STORE_LANE_I32x4_A64_S, STORE_LANE_I32x4_A64 },
9548 { STORE_LANE_I64x2_A32_S, STORE_LANE_I64x2_A32 },
9549 { STORE_LANE_I64x2_A64_S, STORE_LANE_I64x2_A64 },
9550 { STORE_LANE_I8x16_A32_S, STORE_LANE_I8x16_A32 },
9551 { STORE_LANE_I8x16_A64_S, STORE_LANE_I8x16_A64 },
9552 { STORE_V128_A32_S, STORE_V128_A32 },
9553 { STORE_V128_A64_S, STORE_V128_A64 },
9554 { SUB_F16x8_S, SUB_F16x8 },
9555 { SUB_F32_S, SUB_F32 },
9556 { SUB_F32x4_S, SUB_F32x4 },
9557 { SUB_F64_S, SUB_F64 },
9558 { SUB_F64x2_S, SUB_F64x2 },
9559 { SUB_I16x8_S, SUB_I16x8 },
9560 { SUB_I32_S, SUB_I32 },
9561 { SUB_I32x4_S, SUB_I32x4 },
9562 { SUB_I64_S, SUB_I64 },
9563 { SUB_I64x2_S, SUB_I64x2 },
9564 { SUB_I8x16_S, SUB_I8x16 },
9565 { SUB_SAT_S_I16x8_S, SUB_SAT_S_I16x8 },
9566 { SUB_SAT_S_I8x16_S, SUB_SAT_S_I8x16 },
9567 { SUB_SAT_U_I16x8_S, SUB_SAT_U_I16x8 },
9568 { SUB_SAT_U_I8x16_S, SUB_SAT_U_I8x16 },
9569 { SWIZZLE_S, SWIZZLE },
9570 { TABLE_COPY_S, TABLE_COPY },
9571 { TABLE_FILL_EXNREF_S, TABLE_FILL_EXNREF },
9572 { TABLE_FILL_EXTERNREF_S, TABLE_FILL_EXTERNREF },
9573 { TABLE_FILL_FUNCREF_S, TABLE_FILL_FUNCREF },
9574 { TABLE_GET_EXNREF_S, TABLE_GET_EXNREF },
9575 { TABLE_GET_EXTERNREF_S, TABLE_GET_EXTERNREF },
9576 { TABLE_GET_FUNCREF_S, TABLE_GET_FUNCREF },
9577 { TABLE_GROW_EXNREF_S, TABLE_GROW_EXNREF },
9578 { TABLE_GROW_EXTERNREF_S, TABLE_GROW_EXTERNREF },
9579 { TABLE_GROW_FUNCREF_S, TABLE_GROW_FUNCREF },
9580 { TABLE_SET_EXNREF_S, TABLE_SET_EXNREF },
9581 { TABLE_SET_EXTERNREF_S, TABLE_SET_EXTERNREF },
9582 { TABLE_SET_FUNCREF_S, TABLE_SET_FUNCREF },
9583 { TABLE_SIZE_S, TABLE_SIZE },
9584 { TEE_EXNREF_S, TEE_EXNREF },
9585 { TEE_EXTERNREF_S, TEE_EXTERNREF },
9586 { TEE_F32_S, TEE_F32 },
9587 { TEE_F64_S, TEE_F64 },
9588 { TEE_FUNCREF_S, TEE_FUNCREF },
9589 { TEE_I32_S, TEE_I32 },
9590 { TEE_I64_S, TEE_I64 },
9591 { TEE_V128_S, TEE_V128 },
9592 { THROW_REF_S, THROW_REF },
9593 { THROW_S, THROW },
9594 { TRUNC_F16x8_S, TRUNC_F16x8 },
9595 { TRUNC_F32_S, TRUNC_F32 },
9596 { TRUNC_F32x4_S, TRUNC_F32x4 },
9597 { TRUNC_F64_S, TRUNC_F64 },
9598 { TRUNC_F64x2_S, TRUNC_F64x2 },
9599 { TRY_S, TRY },
9600 { TRY_TABLE_S, TRY_TABLE },
9601 { UNREACHABLE_S, UNREACHABLE },
9602 { XOR_I32_S, XOR_I32 },
9603 { XOR_I64_S, XOR_I64 },
9604 { XOR_S, XOR },
9605 { anonymous_13975MEMORY_GROW_A32_S, anonymous_13975MEMORY_GROW_A32 },
9606 { anonymous_13975MEMORY_SIZE_A32_S, anonymous_13975MEMORY_SIZE_A32 },
9607 { anonymous_13976MEMORY_GROW_A64_S, anonymous_13976MEMORY_GROW_A64 },
9608 { anonymous_13976MEMORY_SIZE_A64_S, anonymous_13976MEMORY_SIZE_A64 },
9609 { convert_low_s_F64x2_S, convert_low_s_F64x2 },
9610 { convert_low_u_F64x2_S, convert_low_u_F64x2 },
9611 { demote_zero_F32x4_S, demote_zero_F32x4 },
9612 { extadd_pairwise_s_I16x8_S, extadd_pairwise_s_I16x8 },
9613 { extadd_pairwise_s_I32x4_S, extadd_pairwise_s_I32x4 },
9614 { extadd_pairwise_u_I16x8_S, extadd_pairwise_u_I16x8 },
9615 { extadd_pairwise_u_I32x4_S, extadd_pairwise_u_I32x4 },
9616 { extend_high_s_I16x8_S, extend_high_s_I16x8 },
9617 { extend_high_s_I32x4_S, extend_high_s_I32x4 },
9618 { extend_high_s_I64x2_S, extend_high_s_I64x2 },
9619 { extend_high_u_I16x8_S, extend_high_u_I16x8 },
9620 { extend_high_u_I32x4_S, extend_high_u_I32x4 },
9621 { extend_high_u_I64x2_S, extend_high_u_I64x2 },
9622 { extend_low_s_I16x8_S, extend_low_s_I16x8 },
9623 { extend_low_s_I32x4_S, extend_low_s_I32x4 },
9624 { extend_low_s_I64x2_S, extend_low_s_I64x2 },
9625 { extend_low_u_I16x8_S, extend_low_u_I16x8 },
9626 { extend_low_u_I32x4_S, extend_low_u_I32x4 },
9627 { extend_low_u_I64x2_S, extend_low_u_I64x2 },
9628 { fp_to_sint_I16x8_S, fp_to_sint_I16x8 },
9629 { fp_to_sint_I32x4_S, fp_to_sint_I32x4 },
9630 { fp_to_uint_I16x8_S, fp_to_uint_I16x8 },
9631 { fp_to_uint_I32x4_S, fp_to_uint_I32x4 },
9632 { int_wasm_relaxed_trunc_signed_I32x4_S, int_wasm_relaxed_trunc_signed_I32x4 },
9633 { int_wasm_relaxed_trunc_signed_zero_I32x4_S, int_wasm_relaxed_trunc_signed_zero_I32x4 },
9634 { int_wasm_relaxed_trunc_unsigned_I32x4_S, int_wasm_relaxed_trunc_unsigned_I32x4 },
9635 { int_wasm_relaxed_trunc_unsigned_zero_I32x4_S, int_wasm_relaxed_trunc_unsigned_zero_I32x4 },
9636 { promote_low_F64x2_S, promote_low_F64x2 },
9637 { sint_to_fp_F16x8_S, sint_to_fp_F16x8 },
9638 { sint_to_fp_F32x4_S, sint_to_fp_F32x4 },
9639 { trunc_sat_zero_s_I32x4_S, trunc_sat_zero_s_I32x4 },
9640 { trunc_sat_zero_u_I32x4_S, trunc_sat_zero_u_I32x4 },
9641 { uint_to_fp_F16x8_S, uint_to_fp_F16x8 },
9642 { uint_to_fp_F32x4_S, uint_to_fp_F32x4 },
9643 }; // End of Table
9644
9645 unsigned mid;
9646 unsigned start = 0;
9647 unsigned end = 817;
9648 while (start < end) {
9649 mid = start + (end - start) / 2;
9650 if (Opcode == Table[mid][0])
9651 break;
9652 if (Opcode < Table[mid][0])
9653 end = mid;
9654 else
9655 start = mid + 1;
9656 }
9657 if (start == end)
9658 return -1; // Instruction doesn't exist in this table.
9659
9660 return Table[mid][1];
9661}
9662
9663// getStackOpcode
9664LLVM_READONLY
9665int32_t getStackOpcode(uint32_t Opcode) {
9666 using namespace WebAssembly;
9667 static constexpr uint32_t Table[][2] = {
9668 { CALL_PARAMS, CALL_PARAMS_S },
9669 { CALL_RESULTS, CALL_RESULTS_S },
9670 { CATCHRET, CATCHRET_S },
9671 { CLEANUPRET, CLEANUPRET_S },
9672 { COMPILER_FENCE, COMPILER_FENCE_S },
9673 { RET_CALL_RESULTS, RET_CALL_RESULTS_S },
9674 { ABS_F16x8, ABS_F16x8_S },
9675 { ABS_F32, ABS_F32_S },
9676 { ABS_F32x4, ABS_F32x4_S },
9677 { ABS_F64, ABS_F64_S },
9678 { ABS_F64x2, ABS_F64x2_S },
9679 { ABS_I16x8, ABS_I16x8_S },
9680 { ABS_I32x4, ABS_I32x4_S },
9681 { ABS_I64x2, ABS_I64x2_S },
9682 { ABS_I8x16, ABS_I8x16_S },
9683 { ADD_F16x8, ADD_F16x8_S },
9684 { ADD_F32, ADD_F32_S },
9685 { ADD_F32x4, ADD_F32x4_S },
9686 { ADD_F64, ADD_F64_S },
9687 { ADD_F64x2, ADD_F64x2_S },
9688 { ADD_I16x8, ADD_I16x8_S },
9689 { ADD_I32, ADD_I32_S },
9690 { ADD_I32x4, ADD_I32x4_S },
9691 { ADD_I64, ADD_I64_S },
9692 { ADD_I64x2, ADD_I64x2_S },
9693 { ADD_I8x16, ADD_I8x16_S },
9694 { ADD_SAT_S_I16x8, ADD_SAT_S_I16x8_S },
9695 { ADD_SAT_S_I8x16, ADD_SAT_S_I8x16_S },
9696 { ADD_SAT_U_I16x8, ADD_SAT_U_I16x8_S },
9697 { ADD_SAT_U_I8x16, ADD_SAT_U_I8x16_S },
9698 { ADJCALLSTACKDOWN, ADJCALLSTACKDOWN_S },
9699 { ADJCALLSTACKUP, ADJCALLSTACKUP_S },
9700 { ALLTRUE_I16x8, ALLTRUE_I16x8_S },
9701 { ALLTRUE_I32x4, ALLTRUE_I32x4_S },
9702 { ALLTRUE_I64x2, ALLTRUE_I64x2_S },
9703 { ALLTRUE_I8x16, ALLTRUE_I8x16_S },
9704 { AND, AND_S },
9705 { ANDNOT, ANDNOT_S },
9706 { AND_I32, AND_I32_S },
9707 { AND_I64, AND_I64_S },
9708 { ANYTRUE, ANYTRUE_S },
9709 { ARGUMENT_exnref, ARGUMENT_exnref_S },
9710 { ARGUMENT_externref, ARGUMENT_externref_S },
9711 { ARGUMENT_f32, ARGUMENT_f32_S },
9712 { ARGUMENT_f64, ARGUMENT_f64_S },
9713 { ARGUMENT_funcref, ARGUMENT_funcref_S },
9714 { ARGUMENT_i32, ARGUMENT_i32_S },
9715 { ARGUMENT_i64, ARGUMENT_i64_S },
9716 { ARGUMENT_v16i8, ARGUMENT_v16i8_S },
9717 { ARGUMENT_v2f64, ARGUMENT_v2f64_S },
9718 { ARGUMENT_v2i64, ARGUMENT_v2i64_S },
9719 { ARGUMENT_v4f32, ARGUMENT_v4f32_S },
9720 { ARGUMENT_v4i32, ARGUMENT_v4i32_S },
9721 { ARGUMENT_v8f16, ARGUMENT_v8f16_S },
9722 { ARGUMENT_v8i16, ARGUMENT_v8i16_S },
9723 { ATOMIC_FENCE, ATOMIC_FENCE_S },
9724 { ATOMIC_LOAD16_U_I32_A32, ATOMIC_LOAD16_U_I32_A32_S },
9725 { ATOMIC_LOAD16_U_I32_A64, ATOMIC_LOAD16_U_I32_A64_S },
9726 { ATOMIC_LOAD16_U_I64_A32, ATOMIC_LOAD16_U_I64_A32_S },
9727 { ATOMIC_LOAD16_U_I64_A64, ATOMIC_LOAD16_U_I64_A64_S },
9728 { ATOMIC_LOAD32_U_I64_A32, ATOMIC_LOAD32_U_I64_A32_S },
9729 { ATOMIC_LOAD32_U_I64_A64, ATOMIC_LOAD32_U_I64_A64_S },
9730 { ATOMIC_LOAD8_U_I32_A32, ATOMIC_LOAD8_U_I32_A32_S },
9731 { ATOMIC_LOAD8_U_I32_A64, ATOMIC_LOAD8_U_I32_A64_S },
9732 { ATOMIC_LOAD8_U_I64_A32, ATOMIC_LOAD8_U_I64_A32_S },
9733 { ATOMIC_LOAD8_U_I64_A64, ATOMIC_LOAD8_U_I64_A64_S },
9734 { ATOMIC_LOAD_I32_A32, ATOMIC_LOAD_I32_A32_S },
9735 { ATOMIC_LOAD_I32_A64, ATOMIC_LOAD_I32_A64_S },
9736 { ATOMIC_LOAD_I64_A32, ATOMIC_LOAD_I64_A32_S },
9737 { ATOMIC_LOAD_I64_A64, ATOMIC_LOAD_I64_A64_S },
9738 { ATOMIC_RMW16_U_ADD_I32_A32, ATOMIC_RMW16_U_ADD_I32_A32_S },
9739 { ATOMIC_RMW16_U_ADD_I32_A64, ATOMIC_RMW16_U_ADD_I32_A64_S },
9740 { ATOMIC_RMW16_U_ADD_I64_A32, ATOMIC_RMW16_U_ADD_I64_A32_S },
9741 { ATOMIC_RMW16_U_ADD_I64_A64, ATOMIC_RMW16_U_ADD_I64_A64_S },
9742 { ATOMIC_RMW16_U_AND_I32_A32, ATOMIC_RMW16_U_AND_I32_A32_S },
9743 { ATOMIC_RMW16_U_AND_I32_A64, ATOMIC_RMW16_U_AND_I32_A64_S },
9744 { ATOMIC_RMW16_U_AND_I64_A32, ATOMIC_RMW16_U_AND_I64_A32_S },
9745 { ATOMIC_RMW16_U_AND_I64_A64, ATOMIC_RMW16_U_AND_I64_A64_S },
9746 { ATOMIC_RMW16_U_CMPXCHG_I32_A32, ATOMIC_RMW16_U_CMPXCHG_I32_A32_S },
9747 { ATOMIC_RMW16_U_CMPXCHG_I32_A64, ATOMIC_RMW16_U_CMPXCHG_I32_A64_S },
9748 { ATOMIC_RMW16_U_CMPXCHG_I64_A32, ATOMIC_RMW16_U_CMPXCHG_I64_A32_S },
9749 { ATOMIC_RMW16_U_CMPXCHG_I64_A64, ATOMIC_RMW16_U_CMPXCHG_I64_A64_S },
9750 { ATOMIC_RMW16_U_OR_I32_A32, ATOMIC_RMW16_U_OR_I32_A32_S },
9751 { ATOMIC_RMW16_U_OR_I32_A64, ATOMIC_RMW16_U_OR_I32_A64_S },
9752 { ATOMIC_RMW16_U_OR_I64_A32, ATOMIC_RMW16_U_OR_I64_A32_S },
9753 { ATOMIC_RMW16_U_OR_I64_A64, ATOMIC_RMW16_U_OR_I64_A64_S },
9754 { ATOMIC_RMW16_U_SUB_I32_A32, ATOMIC_RMW16_U_SUB_I32_A32_S },
9755 { ATOMIC_RMW16_U_SUB_I32_A64, ATOMIC_RMW16_U_SUB_I32_A64_S },
9756 { ATOMIC_RMW16_U_SUB_I64_A32, ATOMIC_RMW16_U_SUB_I64_A32_S },
9757 { ATOMIC_RMW16_U_SUB_I64_A64, ATOMIC_RMW16_U_SUB_I64_A64_S },
9758 { ATOMIC_RMW16_U_XCHG_I32_A32, ATOMIC_RMW16_U_XCHG_I32_A32_S },
9759 { ATOMIC_RMW16_U_XCHG_I32_A64, ATOMIC_RMW16_U_XCHG_I32_A64_S },
9760 { ATOMIC_RMW16_U_XCHG_I64_A32, ATOMIC_RMW16_U_XCHG_I64_A32_S },
9761 { ATOMIC_RMW16_U_XCHG_I64_A64, ATOMIC_RMW16_U_XCHG_I64_A64_S },
9762 { ATOMIC_RMW16_U_XOR_I32_A32, ATOMIC_RMW16_U_XOR_I32_A32_S },
9763 { ATOMIC_RMW16_U_XOR_I32_A64, ATOMIC_RMW16_U_XOR_I32_A64_S },
9764 { ATOMIC_RMW16_U_XOR_I64_A32, ATOMIC_RMW16_U_XOR_I64_A32_S },
9765 { ATOMIC_RMW16_U_XOR_I64_A64, ATOMIC_RMW16_U_XOR_I64_A64_S },
9766 { ATOMIC_RMW32_U_ADD_I64_A32, ATOMIC_RMW32_U_ADD_I64_A32_S },
9767 { ATOMIC_RMW32_U_ADD_I64_A64, ATOMIC_RMW32_U_ADD_I64_A64_S },
9768 { ATOMIC_RMW32_U_AND_I64_A32, ATOMIC_RMW32_U_AND_I64_A32_S },
9769 { ATOMIC_RMW32_U_AND_I64_A64, ATOMIC_RMW32_U_AND_I64_A64_S },
9770 { ATOMIC_RMW32_U_CMPXCHG_I64_A32, ATOMIC_RMW32_U_CMPXCHG_I64_A32_S },
9771 { ATOMIC_RMW32_U_CMPXCHG_I64_A64, ATOMIC_RMW32_U_CMPXCHG_I64_A64_S },
9772 { ATOMIC_RMW32_U_OR_I64_A32, ATOMIC_RMW32_U_OR_I64_A32_S },
9773 { ATOMIC_RMW32_U_OR_I64_A64, ATOMIC_RMW32_U_OR_I64_A64_S },
9774 { ATOMIC_RMW32_U_SUB_I64_A32, ATOMIC_RMW32_U_SUB_I64_A32_S },
9775 { ATOMIC_RMW32_U_SUB_I64_A64, ATOMIC_RMW32_U_SUB_I64_A64_S },
9776 { ATOMIC_RMW32_U_XCHG_I64_A32, ATOMIC_RMW32_U_XCHG_I64_A32_S },
9777 { ATOMIC_RMW32_U_XCHG_I64_A64, ATOMIC_RMW32_U_XCHG_I64_A64_S },
9778 { ATOMIC_RMW32_U_XOR_I64_A32, ATOMIC_RMW32_U_XOR_I64_A32_S },
9779 { ATOMIC_RMW32_U_XOR_I64_A64, ATOMIC_RMW32_U_XOR_I64_A64_S },
9780 { ATOMIC_RMW8_U_ADD_I32_A32, ATOMIC_RMW8_U_ADD_I32_A32_S },
9781 { ATOMIC_RMW8_U_ADD_I32_A64, ATOMIC_RMW8_U_ADD_I32_A64_S },
9782 { ATOMIC_RMW8_U_ADD_I64_A32, ATOMIC_RMW8_U_ADD_I64_A32_S },
9783 { ATOMIC_RMW8_U_ADD_I64_A64, ATOMIC_RMW8_U_ADD_I64_A64_S },
9784 { ATOMIC_RMW8_U_AND_I32_A32, ATOMIC_RMW8_U_AND_I32_A32_S },
9785 { ATOMIC_RMW8_U_AND_I32_A64, ATOMIC_RMW8_U_AND_I32_A64_S },
9786 { ATOMIC_RMW8_U_AND_I64_A32, ATOMIC_RMW8_U_AND_I64_A32_S },
9787 { ATOMIC_RMW8_U_AND_I64_A64, ATOMIC_RMW8_U_AND_I64_A64_S },
9788 { ATOMIC_RMW8_U_CMPXCHG_I32_A32, ATOMIC_RMW8_U_CMPXCHG_I32_A32_S },
9789 { ATOMIC_RMW8_U_CMPXCHG_I32_A64, ATOMIC_RMW8_U_CMPXCHG_I32_A64_S },
9790 { ATOMIC_RMW8_U_CMPXCHG_I64_A32, ATOMIC_RMW8_U_CMPXCHG_I64_A32_S },
9791 { ATOMIC_RMW8_U_CMPXCHG_I64_A64, ATOMIC_RMW8_U_CMPXCHG_I64_A64_S },
9792 { ATOMIC_RMW8_U_OR_I32_A32, ATOMIC_RMW8_U_OR_I32_A32_S },
9793 { ATOMIC_RMW8_U_OR_I32_A64, ATOMIC_RMW8_U_OR_I32_A64_S },
9794 { ATOMIC_RMW8_U_OR_I64_A32, ATOMIC_RMW8_U_OR_I64_A32_S },
9795 { ATOMIC_RMW8_U_OR_I64_A64, ATOMIC_RMW8_U_OR_I64_A64_S },
9796 { ATOMIC_RMW8_U_SUB_I32_A32, ATOMIC_RMW8_U_SUB_I32_A32_S },
9797 { ATOMIC_RMW8_U_SUB_I32_A64, ATOMIC_RMW8_U_SUB_I32_A64_S },
9798 { ATOMIC_RMW8_U_SUB_I64_A32, ATOMIC_RMW8_U_SUB_I64_A32_S },
9799 { ATOMIC_RMW8_U_SUB_I64_A64, ATOMIC_RMW8_U_SUB_I64_A64_S },
9800 { ATOMIC_RMW8_U_XCHG_I32_A32, ATOMIC_RMW8_U_XCHG_I32_A32_S },
9801 { ATOMIC_RMW8_U_XCHG_I32_A64, ATOMIC_RMW8_U_XCHG_I32_A64_S },
9802 { ATOMIC_RMW8_U_XCHG_I64_A32, ATOMIC_RMW8_U_XCHG_I64_A32_S },
9803 { ATOMIC_RMW8_U_XCHG_I64_A64, ATOMIC_RMW8_U_XCHG_I64_A64_S },
9804 { ATOMIC_RMW8_U_XOR_I32_A32, ATOMIC_RMW8_U_XOR_I32_A32_S },
9805 { ATOMIC_RMW8_U_XOR_I32_A64, ATOMIC_RMW8_U_XOR_I32_A64_S },
9806 { ATOMIC_RMW8_U_XOR_I64_A32, ATOMIC_RMW8_U_XOR_I64_A32_S },
9807 { ATOMIC_RMW8_U_XOR_I64_A64, ATOMIC_RMW8_U_XOR_I64_A64_S },
9808 { ATOMIC_RMW_ADD_I32_A32, ATOMIC_RMW_ADD_I32_A32_S },
9809 { ATOMIC_RMW_ADD_I32_A64, ATOMIC_RMW_ADD_I32_A64_S },
9810 { ATOMIC_RMW_ADD_I64_A32, ATOMIC_RMW_ADD_I64_A32_S },
9811 { ATOMIC_RMW_ADD_I64_A64, ATOMIC_RMW_ADD_I64_A64_S },
9812 { ATOMIC_RMW_AND_I32_A32, ATOMIC_RMW_AND_I32_A32_S },
9813 { ATOMIC_RMW_AND_I32_A64, ATOMIC_RMW_AND_I32_A64_S },
9814 { ATOMIC_RMW_AND_I64_A32, ATOMIC_RMW_AND_I64_A32_S },
9815 { ATOMIC_RMW_AND_I64_A64, ATOMIC_RMW_AND_I64_A64_S },
9816 { ATOMIC_RMW_CMPXCHG_I32_A32, ATOMIC_RMW_CMPXCHG_I32_A32_S },
9817 { ATOMIC_RMW_CMPXCHG_I32_A64, ATOMIC_RMW_CMPXCHG_I32_A64_S },
9818 { ATOMIC_RMW_CMPXCHG_I64_A32, ATOMIC_RMW_CMPXCHG_I64_A32_S },
9819 { ATOMIC_RMW_CMPXCHG_I64_A64, ATOMIC_RMW_CMPXCHG_I64_A64_S },
9820 { ATOMIC_RMW_OR_I32_A32, ATOMIC_RMW_OR_I32_A32_S },
9821 { ATOMIC_RMW_OR_I32_A64, ATOMIC_RMW_OR_I32_A64_S },
9822 { ATOMIC_RMW_OR_I64_A32, ATOMIC_RMW_OR_I64_A32_S },
9823 { ATOMIC_RMW_OR_I64_A64, ATOMIC_RMW_OR_I64_A64_S },
9824 { ATOMIC_RMW_SUB_I32_A32, ATOMIC_RMW_SUB_I32_A32_S },
9825 { ATOMIC_RMW_SUB_I32_A64, ATOMIC_RMW_SUB_I32_A64_S },
9826 { ATOMIC_RMW_SUB_I64_A32, ATOMIC_RMW_SUB_I64_A32_S },
9827 { ATOMIC_RMW_SUB_I64_A64, ATOMIC_RMW_SUB_I64_A64_S },
9828 { ATOMIC_RMW_XCHG_I32_A32, ATOMIC_RMW_XCHG_I32_A32_S },
9829 { ATOMIC_RMW_XCHG_I32_A64, ATOMIC_RMW_XCHG_I32_A64_S },
9830 { ATOMIC_RMW_XCHG_I64_A32, ATOMIC_RMW_XCHG_I64_A32_S },
9831 { ATOMIC_RMW_XCHG_I64_A64, ATOMIC_RMW_XCHG_I64_A64_S },
9832 { ATOMIC_RMW_XOR_I32_A32, ATOMIC_RMW_XOR_I32_A32_S },
9833 { ATOMIC_RMW_XOR_I32_A64, ATOMIC_RMW_XOR_I32_A64_S },
9834 { ATOMIC_RMW_XOR_I64_A32, ATOMIC_RMW_XOR_I64_A32_S },
9835 { ATOMIC_RMW_XOR_I64_A64, ATOMIC_RMW_XOR_I64_A64_S },
9836 { ATOMIC_STORE16_I32_A32, ATOMIC_STORE16_I32_A32_S },
9837 { ATOMIC_STORE16_I32_A64, ATOMIC_STORE16_I32_A64_S },
9838 { ATOMIC_STORE16_I64_A32, ATOMIC_STORE16_I64_A32_S },
9839 { ATOMIC_STORE16_I64_A64, ATOMIC_STORE16_I64_A64_S },
9840 { ATOMIC_STORE32_I64_A32, ATOMIC_STORE32_I64_A32_S },
9841 { ATOMIC_STORE32_I64_A64, ATOMIC_STORE32_I64_A64_S },
9842 { ATOMIC_STORE8_I32_A32, ATOMIC_STORE8_I32_A32_S },
9843 { ATOMIC_STORE8_I32_A64, ATOMIC_STORE8_I32_A64_S },
9844 { ATOMIC_STORE8_I64_A32, ATOMIC_STORE8_I64_A32_S },
9845 { ATOMIC_STORE8_I64_A64, ATOMIC_STORE8_I64_A64_S },
9846 { ATOMIC_STORE_I32_A32, ATOMIC_STORE_I32_A32_S },
9847 { ATOMIC_STORE_I32_A64, ATOMIC_STORE_I32_A64_S },
9848 { ATOMIC_STORE_I64_A32, ATOMIC_STORE_I64_A32_S },
9849 { ATOMIC_STORE_I64_A64, ATOMIC_STORE_I64_A64_S },
9850 { AVGR_U_I16x8, AVGR_U_I16x8_S },
9851 { AVGR_U_I8x16, AVGR_U_I8x16_S },
9852 { BITMASK_I16x8, BITMASK_I16x8_S },
9853 { BITMASK_I32x4, BITMASK_I32x4_S },
9854 { BITMASK_I64x2, BITMASK_I64x2_S },
9855 { BITMASK_I8x16, BITMASK_I8x16_S },
9856 { BITSELECT, BITSELECT_S },
9857 { BLOCK, BLOCK_S },
9858 { BR, BR_S },
9859 { BR_IF, BR_IF_S },
9860 { BR_TABLE_I32, BR_TABLE_I32_S },
9861 { BR_TABLE_I64, BR_TABLE_I64_S },
9862 { BR_UNLESS, BR_UNLESS_S },
9863 { CALL, CALL_S },
9864 { CALL_INDIRECT, CALL_INDIRECT_S },
9865 { CATCH, CATCH_S },
9866 { CATCH_ALL, CATCH_ALL_S },
9867 { CATCH_ALL_LEGACY, CATCH_ALL_LEGACY_S },
9868 { CATCH_ALL_REF, CATCH_ALL_REF_S },
9869 { CATCH_LEGACY, CATCH_LEGACY_S },
9870 { CATCH_REF, CATCH_REF_S },
9871 { CEIL_F16x8, CEIL_F16x8_S },
9872 { CEIL_F32, CEIL_F32_S },
9873 { CEIL_F32x4, CEIL_F32x4_S },
9874 { CEIL_F64, CEIL_F64_S },
9875 { CEIL_F64x2, CEIL_F64x2_S },
9876 { CLZ_I32, CLZ_I32_S },
9877 { CLZ_I64, CLZ_I64_S },
9878 { CONST_F32, CONST_F32_S },
9879 { CONST_F64, CONST_F64_S },
9880 { CONST_I32, CONST_I32_S },
9881 { CONST_I64, CONST_I64_S },
9882 { CONST_V128_F32x4, CONST_V128_F32x4_S },
9883 { CONST_V128_F64x2, CONST_V128_F64x2_S },
9884 { CONST_V128_I16x8, CONST_V128_I16x8_S },
9885 { CONST_V128_I32x4, CONST_V128_I32x4_S },
9886 { CONST_V128_I64x2, CONST_V128_I64x2_S },
9887 { CONST_V128_I8x16, CONST_V128_I8x16_S },
9888 { COPYSIGN_F32, COPYSIGN_F32_S },
9889 { COPYSIGN_F64, COPYSIGN_F64_S },
9890 { COPY_EXNREF, COPY_EXNREF_S },
9891 { COPY_EXTERNREF, COPY_EXTERNREF_S },
9892 { COPY_F32, COPY_F32_S },
9893 { COPY_F64, COPY_F64_S },
9894 { COPY_FUNCREF, COPY_FUNCREF_S },
9895 { COPY_I32, COPY_I32_S },
9896 { COPY_I64, COPY_I64_S },
9897 { COPY_V128, COPY_V128_S },
9898 { CTZ_I32, CTZ_I32_S },
9899 { CTZ_I64, CTZ_I64_S },
9900 { DATA_DROP, DATA_DROP_S },
9901 { DEBUG_UNREACHABLE, DEBUG_UNREACHABLE_S },
9902 { DELEGATE, DELEGATE_S },
9903 { DIV_F16x8, DIV_F16x8_S },
9904 { DIV_F32, DIV_F32_S },
9905 { DIV_F32x4, DIV_F32x4_S },
9906 { DIV_F64, DIV_F64_S },
9907 { DIV_F64x2, DIV_F64x2_S },
9908 { DIV_S_I32, DIV_S_I32_S },
9909 { DIV_S_I64, DIV_S_I64_S },
9910 { DIV_U_I32, DIV_U_I32_S },
9911 { DIV_U_I64, DIV_U_I64_S },
9912 { DOT, DOT_S },
9913 { DROP_EXNREF, DROP_EXNREF_S },
9914 { DROP_EXTERNREF, DROP_EXTERNREF_S },
9915 { DROP_F32, DROP_F32_S },
9916 { DROP_F64, DROP_F64_S },
9917 { DROP_FUNCREF, DROP_FUNCREF_S },
9918 { DROP_I32, DROP_I32_S },
9919 { DROP_I64, DROP_I64_S },
9920 { DROP_V128, DROP_V128_S },
9921 { ELSE, ELSE_S },
9922 { END, END_S },
9923 { END_BLOCK, END_BLOCK_S },
9924 { END_FUNCTION, END_FUNCTION_S },
9925 { END_IF, END_IF_S },
9926 { END_LOOP, END_LOOP_S },
9927 { END_TRY, END_TRY_S },
9928 { END_TRY_TABLE, END_TRY_TABLE_S },
9929 { EQZ_I32, EQZ_I32_S },
9930 { EQZ_I64, EQZ_I64_S },
9931 { EQ_F16x8, EQ_F16x8_S },
9932 { EQ_F32, EQ_F32_S },
9933 { EQ_F32x4, EQ_F32x4_S },
9934 { EQ_F64, EQ_F64_S },
9935 { EQ_F64x2, EQ_F64x2_S },
9936 { EQ_I16x8, EQ_I16x8_S },
9937 { EQ_I32, EQ_I32_S },
9938 { EQ_I32x4, EQ_I32x4_S },
9939 { EQ_I64, EQ_I64_S },
9940 { EQ_I64x2, EQ_I64x2_S },
9941 { EQ_I8x16, EQ_I8x16_S },
9942 { EXTMUL_HIGH_S_I16x8, EXTMUL_HIGH_S_I16x8_S },
9943 { EXTMUL_HIGH_S_I32x4, EXTMUL_HIGH_S_I32x4_S },
9944 { EXTMUL_HIGH_S_I64x2, EXTMUL_HIGH_S_I64x2_S },
9945 { EXTMUL_HIGH_U_I16x8, EXTMUL_HIGH_U_I16x8_S },
9946 { EXTMUL_HIGH_U_I32x4, EXTMUL_HIGH_U_I32x4_S },
9947 { EXTMUL_HIGH_U_I64x2, EXTMUL_HIGH_U_I64x2_S },
9948 { EXTMUL_LOW_S_I16x8, EXTMUL_LOW_S_I16x8_S },
9949 { EXTMUL_LOW_S_I32x4, EXTMUL_LOW_S_I32x4_S },
9950 { EXTMUL_LOW_S_I64x2, EXTMUL_LOW_S_I64x2_S },
9951 { EXTMUL_LOW_U_I16x8, EXTMUL_LOW_U_I16x8_S },
9952 { EXTMUL_LOW_U_I32x4, EXTMUL_LOW_U_I32x4_S },
9953 { EXTMUL_LOW_U_I64x2, EXTMUL_LOW_U_I64x2_S },
9954 { EXTRACT_LANE_F16x8, EXTRACT_LANE_F16x8_S },
9955 { EXTRACT_LANE_F32x4, EXTRACT_LANE_F32x4_S },
9956 { EXTRACT_LANE_F64x2, EXTRACT_LANE_F64x2_S },
9957 { EXTRACT_LANE_I16x8_s, EXTRACT_LANE_I16x8_s_S },
9958 { EXTRACT_LANE_I16x8_u, EXTRACT_LANE_I16x8_u_S },
9959 { EXTRACT_LANE_I32x4, EXTRACT_LANE_I32x4_S },
9960 { EXTRACT_LANE_I64x2, EXTRACT_LANE_I64x2_S },
9961 { EXTRACT_LANE_I8x16_s, EXTRACT_LANE_I8x16_s_S },
9962 { EXTRACT_LANE_I8x16_u, EXTRACT_LANE_I8x16_u_S },
9963 { F32_CONVERT_S_I32, F32_CONVERT_S_I32_S },
9964 { F32_CONVERT_S_I64, F32_CONVERT_S_I64_S },
9965 { F32_CONVERT_U_I32, F32_CONVERT_U_I32_S },
9966 { F32_CONVERT_U_I64, F32_CONVERT_U_I64_S },
9967 { F32_DEMOTE_F64, F32_DEMOTE_F64_S },
9968 { F32_REINTERPRET_I32, F32_REINTERPRET_I32_S },
9969 { F64_CONVERT_S_I32, F64_CONVERT_S_I32_S },
9970 { F64_CONVERT_S_I64, F64_CONVERT_S_I64_S },
9971 { F64_CONVERT_U_I32, F64_CONVERT_U_I32_S },
9972 { F64_CONVERT_U_I64, F64_CONVERT_U_I64_S },
9973 { F64_PROMOTE_F32, F64_PROMOTE_F32_S },
9974 { F64_REINTERPRET_I64, F64_REINTERPRET_I64_S },
9975 { FALLTHROUGH_RETURN, FALLTHROUGH_RETURN_S },
9976 { FLOOR_F16x8, FLOOR_F16x8_S },
9977 { FLOOR_F32, FLOOR_F32_S },
9978 { FLOOR_F32x4, FLOOR_F32x4_S },
9979 { FLOOR_F64, FLOOR_F64_S },
9980 { FLOOR_F64x2, FLOOR_F64x2_S },
9981 { FP_TO_SINT_I32_F32, FP_TO_SINT_I32_F32_S },
9982 { FP_TO_SINT_I32_F64, FP_TO_SINT_I32_F64_S },
9983 { FP_TO_SINT_I64_F32, FP_TO_SINT_I64_F32_S },
9984 { FP_TO_SINT_I64_F64, FP_TO_SINT_I64_F64_S },
9985 { FP_TO_UINT_I32_F32, FP_TO_UINT_I32_F32_S },
9986 { FP_TO_UINT_I32_F64, FP_TO_UINT_I32_F64_S },
9987 { FP_TO_UINT_I64_F32, FP_TO_UINT_I64_F32_S },
9988 { FP_TO_UINT_I64_F64, FP_TO_UINT_I64_F64_S },
9989 { GE_F16x8, GE_F16x8_S },
9990 { GE_F32, GE_F32_S },
9991 { GE_F32x4, GE_F32x4_S },
9992 { GE_F64, GE_F64_S },
9993 { GE_F64x2, GE_F64x2_S },
9994 { GE_S_I16x8, GE_S_I16x8_S },
9995 { GE_S_I32, GE_S_I32_S },
9996 { GE_S_I32x4, GE_S_I32x4_S },
9997 { GE_S_I64, GE_S_I64_S },
9998 { GE_S_I64x2, GE_S_I64x2_S },
9999 { GE_S_I8x16, GE_S_I8x16_S },
10000 { GE_U_I16x8, GE_U_I16x8_S },
10001 { GE_U_I32, GE_U_I32_S },
10002 { GE_U_I32x4, GE_U_I32x4_S },
10003 { GE_U_I64, GE_U_I64_S },
10004 { GE_U_I8x16, GE_U_I8x16_S },
10005 { GLOBAL_GET_EXNREF, GLOBAL_GET_EXNREF_S },
10006 { GLOBAL_GET_EXTERNREF, GLOBAL_GET_EXTERNREF_S },
10007 { GLOBAL_GET_F32, GLOBAL_GET_F32_S },
10008 { GLOBAL_GET_F64, GLOBAL_GET_F64_S },
10009 { GLOBAL_GET_FUNCREF, GLOBAL_GET_FUNCREF_S },
10010 { GLOBAL_GET_I32, GLOBAL_GET_I32_S },
10011 { GLOBAL_GET_I64, GLOBAL_GET_I64_S },
10012 { GLOBAL_GET_V128, GLOBAL_GET_V128_S },
10013 { GLOBAL_SET_EXNREF, GLOBAL_SET_EXNREF_S },
10014 { GLOBAL_SET_EXTERNREF, GLOBAL_SET_EXTERNREF_S },
10015 { GLOBAL_SET_F32, GLOBAL_SET_F32_S },
10016 { GLOBAL_SET_F64, GLOBAL_SET_F64_S },
10017 { GLOBAL_SET_FUNCREF, GLOBAL_SET_FUNCREF_S },
10018 { GLOBAL_SET_I32, GLOBAL_SET_I32_S },
10019 { GLOBAL_SET_I64, GLOBAL_SET_I64_S },
10020 { GLOBAL_SET_V128, GLOBAL_SET_V128_S },
10021 { GT_F16x8, GT_F16x8_S },
10022 { GT_F32, GT_F32_S },
10023 { GT_F32x4, GT_F32x4_S },
10024 { GT_F64, GT_F64_S },
10025 { GT_F64x2, GT_F64x2_S },
10026 { GT_S_I16x8, GT_S_I16x8_S },
10027 { GT_S_I32, GT_S_I32_S },
10028 { GT_S_I32x4, GT_S_I32x4_S },
10029 { GT_S_I64, GT_S_I64_S },
10030 { GT_S_I64x2, GT_S_I64x2_S },
10031 { GT_S_I8x16, GT_S_I8x16_S },
10032 { GT_U_I16x8, GT_U_I16x8_S },
10033 { GT_U_I32, GT_U_I32_S },
10034 { GT_U_I32x4, GT_U_I32x4_S },
10035 { GT_U_I64, GT_U_I64_S },
10036 { GT_U_I8x16, GT_U_I8x16_S },
10037 { I32_EXTEND16_S_I32, I32_EXTEND16_S_I32_S },
10038 { I32_EXTEND8_S_I32, I32_EXTEND8_S_I32_S },
10039 { I32_REINTERPRET_F32, I32_REINTERPRET_F32_S },
10040 { I32_TRUNC_S_F32, I32_TRUNC_S_F32_S },
10041 { I32_TRUNC_S_F64, I32_TRUNC_S_F64_S },
10042 { I32_TRUNC_S_SAT_F32, I32_TRUNC_S_SAT_F32_S },
10043 { I32_TRUNC_S_SAT_F64, I32_TRUNC_S_SAT_F64_S },
10044 { I32_TRUNC_U_F32, I32_TRUNC_U_F32_S },
10045 { I32_TRUNC_U_F64, I32_TRUNC_U_F64_S },
10046 { I32_TRUNC_U_SAT_F32, I32_TRUNC_U_SAT_F32_S },
10047 { I32_TRUNC_U_SAT_F64, I32_TRUNC_U_SAT_F64_S },
10048 { I32_WRAP_I64, I32_WRAP_I64_S },
10049 { I64_ADD128, I64_ADD128_S },
10050 { I64_EXTEND16_S_I64, I64_EXTEND16_S_I64_S },
10051 { I64_EXTEND32_S_I64, I64_EXTEND32_S_I64_S },
10052 { I64_EXTEND8_S_I64, I64_EXTEND8_S_I64_S },
10053 { I64_EXTEND_S_I32, I64_EXTEND_S_I32_S },
10054 { I64_EXTEND_U_I32, I64_EXTEND_U_I32_S },
10055 { I64_MUL_WIDE_S, I64_MUL_WIDE_S_S },
10056 { I64_MUL_WIDE_U, I64_MUL_WIDE_U_S },
10057 { I64_REINTERPRET_F64, I64_REINTERPRET_F64_S },
10058 { I64_SUB128, I64_SUB128_S },
10059 { I64_TRUNC_S_F32, I64_TRUNC_S_F32_S },
10060 { I64_TRUNC_S_F64, I64_TRUNC_S_F64_S },
10061 { I64_TRUNC_S_SAT_F32, I64_TRUNC_S_SAT_F32_S },
10062 { I64_TRUNC_S_SAT_F64, I64_TRUNC_S_SAT_F64_S },
10063 { I64_TRUNC_U_F32, I64_TRUNC_U_F32_S },
10064 { I64_TRUNC_U_F64, I64_TRUNC_U_F64_S },
10065 { I64_TRUNC_U_SAT_F32, I64_TRUNC_U_SAT_F32_S },
10066 { I64_TRUNC_U_SAT_F64, I64_TRUNC_U_SAT_F64_S },
10067 { IF, IF_S },
10068 { LANESELECT_I16x8, LANESELECT_I16x8_S },
10069 { LANESELECT_I32x4, LANESELECT_I32x4_S },
10070 { LANESELECT_I64x2, LANESELECT_I64x2_S },
10071 { LANESELECT_I8x16, LANESELECT_I8x16_S },
10072 { LE_F16x8, LE_F16x8_S },
10073 { LE_F32, LE_F32_S },
10074 { LE_F32x4, LE_F32x4_S },
10075 { LE_F64, LE_F64_S },
10076 { LE_F64x2, LE_F64x2_S },
10077 { LE_S_I16x8, LE_S_I16x8_S },
10078 { LE_S_I32, LE_S_I32_S },
10079 { LE_S_I32x4, LE_S_I32x4_S },
10080 { LE_S_I64, LE_S_I64_S },
10081 { LE_S_I64x2, LE_S_I64x2_S },
10082 { LE_S_I8x16, LE_S_I8x16_S },
10083 { LE_U_I16x8, LE_U_I16x8_S },
10084 { LE_U_I32, LE_U_I32_S },
10085 { LE_U_I32x4, LE_U_I32x4_S },
10086 { LE_U_I64, LE_U_I64_S },
10087 { LE_U_I8x16, LE_U_I8x16_S },
10088 { LOAD16_SPLAT_A32, LOAD16_SPLAT_A32_S },
10089 { LOAD16_SPLAT_A64, LOAD16_SPLAT_A64_S },
10090 { LOAD16_S_I32_A32, LOAD16_S_I32_A32_S },
10091 { LOAD16_S_I32_A64, LOAD16_S_I32_A64_S },
10092 { LOAD16_S_I64_A32, LOAD16_S_I64_A32_S },
10093 { LOAD16_S_I64_A64, LOAD16_S_I64_A64_S },
10094 { LOAD16_U_I32_A32, LOAD16_U_I32_A32_S },
10095 { LOAD16_U_I32_A64, LOAD16_U_I32_A64_S },
10096 { LOAD16_U_I64_A32, LOAD16_U_I64_A32_S },
10097 { LOAD16_U_I64_A64, LOAD16_U_I64_A64_S },
10098 { LOAD32_SPLAT_A32, LOAD32_SPLAT_A32_S },
10099 { LOAD32_SPLAT_A64, LOAD32_SPLAT_A64_S },
10100 { LOAD32_S_I64_A32, LOAD32_S_I64_A32_S },
10101 { LOAD32_S_I64_A64, LOAD32_S_I64_A64_S },
10102 { LOAD32_U_I64_A32, LOAD32_U_I64_A32_S },
10103 { LOAD32_U_I64_A64, LOAD32_U_I64_A64_S },
10104 { LOAD64_SPLAT_A32, LOAD64_SPLAT_A32_S },
10105 { LOAD64_SPLAT_A64, LOAD64_SPLAT_A64_S },
10106 { LOAD8_SPLAT_A32, LOAD8_SPLAT_A32_S },
10107 { LOAD8_SPLAT_A64, LOAD8_SPLAT_A64_S },
10108 { LOAD8_S_I32_A32, LOAD8_S_I32_A32_S },
10109 { LOAD8_S_I32_A64, LOAD8_S_I32_A64_S },
10110 { LOAD8_S_I64_A32, LOAD8_S_I64_A32_S },
10111 { LOAD8_S_I64_A64, LOAD8_S_I64_A64_S },
10112 { LOAD8_U_I32_A32, LOAD8_U_I32_A32_S },
10113 { LOAD8_U_I32_A64, LOAD8_U_I32_A64_S },
10114 { LOAD8_U_I64_A32, LOAD8_U_I64_A32_S },
10115 { LOAD8_U_I64_A64, LOAD8_U_I64_A64_S },
10116 { LOAD_EXTEND_S_I16x8_A32, LOAD_EXTEND_S_I16x8_A32_S },
10117 { LOAD_EXTEND_S_I16x8_A64, LOAD_EXTEND_S_I16x8_A64_S },
10118 { LOAD_EXTEND_S_I32x4_A32, LOAD_EXTEND_S_I32x4_A32_S },
10119 { LOAD_EXTEND_S_I32x4_A64, LOAD_EXTEND_S_I32x4_A64_S },
10120 { LOAD_EXTEND_S_I64x2_A32, LOAD_EXTEND_S_I64x2_A32_S },
10121 { LOAD_EXTEND_S_I64x2_A64, LOAD_EXTEND_S_I64x2_A64_S },
10122 { LOAD_EXTEND_U_I16x8_A32, LOAD_EXTEND_U_I16x8_A32_S },
10123 { LOAD_EXTEND_U_I16x8_A64, LOAD_EXTEND_U_I16x8_A64_S },
10124 { LOAD_EXTEND_U_I32x4_A32, LOAD_EXTEND_U_I32x4_A32_S },
10125 { LOAD_EXTEND_U_I32x4_A64, LOAD_EXTEND_U_I32x4_A64_S },
10126 { LOAD_EXTEND_U_I64x2_A32, LOAD_EXTEND_U_I64x2_A32_S },
10127 { LOAD_EXTEND_U_I64x2_A64, LOAD_EXTEND_U_I64x2_A64_S },
10128 { LOAD_F16_F32_A32, LOAD_F16_F32_A32_S },
10129 { LOAD_F16_F32_A64, LOAD_F16_F32_A64_S },
10130 { LOAD_F32_A32, LOAD_F32_A32_S },
10131 { LOAD_F32_A64, LOAD_F32_A64_S },
10132 { LOAD_F64_A32, LOAD_F64_A32_S },
10133 { LOAD_F64_A64, LOAD_F64_A64_S },
10134 { LOAD_I32_A32, LOAD_I32_A32_S },
10135 { LOAD_I32_A64, LOAD_I32_A64_S },
10136 { LOAD_I64_A32, LOAD_I64_A32_S },
10137 { LOAD_I64_A64, LOAD_I64_A64_S },
10138 { LOAD_LANE_16_A32, LOAD_LANE_16_A32_S },
10139 { LOAD_LANE_16_A64, LOAD_LANE_16_A64_S },
10140 { LOAD_LANE_32_A32, LOAD_LANE_32_A32_S },
10141 { LOAD_LANE_32_A64, LOAD_LANE_32_A64_S },
10142 { LOAD_LANE_64_A32, LOAD_LANE_64_A32_S },
10143 { LOAD_LANE_64_A64, LOAD_LANE_64_A64_S },
10144 { LOAD_LANE_8_A32, LOAD_LANE_8_A32_S },
10145 { LOAD_LANE_8_A64, LOAD_LANE_8_A64_S },
10146 { LOAD_V128_A32, LOAD_V128_A32_S },
10147 { LOAD_V128_A64, LOAD_V128_A64_S },
10148 { LOAD_ZERO_32_A32, LOAD_ZERO_32_A32_S },
10149 { LOAD_ZERO_32_A64, LOAD_ZERO_32_A64_S },
10150 { LOAD_ZERO_64_A32, LOAD_ZERO_64_A32_S },
10151 { LOAD_ZERO_64_A64, LOAD_ZERO_64_A64_S },
10152 { LOCAL_GET_EXNREF, LOCAL_GET_EXNREF_S },
10153 { LOCAL_GET_EXTERNREF, LOCAL_GET_EXTERNREF_S },
10154 { LOCAL_GET_F32, LOCAL_GET_F32_S },
10155 { LOCAL_GET_F64, LOCAL_GET_F64_S },
10156 { LOCAL_GET_FUNCREF, LOCAL_GET_FUNCREF_S },
10157 { LOCAL_GET_I32, LOCAL_GET_I32_S },
10158 { LOCAL_GET_I64, LOCAL_GET_I64_S },
10159 { LOCAL_GET_V128, LOCAL_GET_V128_S },
10160 { LOCAL_SET_EXNREF, LOCAL_SET_EXNREF_S },
10161 { LOCAL_SET_EXTERNREF, LOCAL_SET_EXTERNREF_S },
10162 { LOCAL_SET_F32, LOCAL_SET_F32_S },
10163 { LOCAL_SET_F64, LOCAL_SET_F64_S },
10164 { LOCAL_SET_FUNCREF, LOCAL_SET_FUNCREF_S },
10165 { LOCAL_SET_I32, LOCAL_SET_I32_S },
10166 { LOCAL_SET_I64, LOCAL_SET_I64_S },
10167 { LOCAL_SET_V128, LOCAL_SET_V128_S },
10168 { LOCAL_TEE_EXNREF, LOCAL_TEE_EXNREF_S },
10169 { LOCAL_TEE_EXTERNREF, LOCAL_TEE_EXTERNREF_S },
10170 { LOCAL_TEE_F32, LOCAL_TEE_F32_S },
10171 { LOCAL_TEE_F64, LOCAL_TEE_F64_S },
10172 { LOCAL_TEE_FUNCREF, LOCAL_TEE_FUNCREF_S },
10173 { LOCAL_TEE_I32, LOCAL_TEE_I32_S },
10174 { LOCAL_TEE_I64, LOCAL_TEE_I64_S },
10175 { LOCAL_TEE_V128, LOCAL_TEE_V128_S },
10176 { LOOP, LOOP_S },
10177 { LT_F16x8, LT_F16x8_S },
10178 { LT_F32, LT_F32_S },
10179 { LT_F32x4, LT_F32x4_S },
10180 { LT_F64, LT_F64_S },
10181 { LT_F64x2, LT_F64x2_S },
10182 { LT_S_I16x8, LT_S_I16x8_S },
10183 { LT_S_I32, LT_S_I32_S },
10184 { LT_S_I32x4, LT_S_I32x4_S },
10185 { LT_S_I64, LT_S_I64_S },
10186 { LT_S_I64x2, LT_S_I64x2_S },
10187 { LT_S_I8x16, LT_S_I8x16_S },
10188 { LT_U_I16x8, LT_U_I16x8_S },
10189 { LT_U_I32, LT_U_I32_S },
10190 { LT_U_I32x4, LT_U_I32x4_S },
10191 { LT_U_I64, LT_U_I64_S },
10192 { LT_U_I8x16, LT_U_I8x16_S },
10193 { MADD_F16x8, MADD_F16x8_S },
10194 { MADD_F32x4, MADD_F32x4_S },
10195 { MADD_F64x2, MADD_F64x2_S },
10196 { MAX_F16x8, MAX_F16x8_S },
10197 { MAX_F32, MAX_F32_S },
10198 { MAX_F32x4, MAX_F32x4_S },
10199 { MAX_F64, MAX_F64_S },
10200 { MAX_F64x2, MAX_F64x2_S },
10201 { MAX_S_I16x8, MAX_S_I16x8_S },
10202 { MAX_S_I32x4, MAX_S_I32x4_S },
10203 { MAX_S_I8x16, MAX_S_I8x16_S },
10204 { MAX_U_I16x8, MAX_U_I16x8_S },
10205 { MAX_U_I32x4, MAX_U_I32x4_S },
10206 { MAX_U_I8x16, MAX_U_I8x16_S },
10207 { MEMCPY_A32, MEMCPY_A32_S },
10208 { MEMCPY_A64, MEMCPY_A64_S },
10209 { MEMORY_ATOMIC_NOTIFY_A32, MEMORY_ATOMIC_NOTIFY_A32_S },
10210 { MEMORY_ATOMIC_NOTIFY_A64, MEMORY_ATOMIC_NOTIFY_A64_S },
10211 { MEMORY_ATOMIC_WAIT32_A32, MEMORY_ATOMIC_WAIT32_A32_S },
10212 { MEMORY_ATOMIC_WAIT32_A64, MEMORY_ATOMIC_WAIT32_A64_S },
10213 { MEMORY_ATOMIC_WAIT64_A32, MEMORY_ATOMIC_WAIT64_A32_S },
10214 { MEMORY_ATOMIC_WAIT64_A64, MEMORY_ATOMIC_WAIT64_A64_S },
10215 { MEMORY_COPY_A32, MEMORY_COPY_A32_S },
10216 { MEMORY_COPY_A64, MEMORY_COPY_A64_S },
10217 { MEMORY_FILL_A32, MEMORY_FILL_A32_S },
10218 { MEMORY_FILL_A64, MEMORY_FILL_A64_S },
10219 { MEMORY_INIT_A32, MEMORY_INIT_A32_S },
10220 { MEMORY_INIT_A64, MEMORY_INIT_A64_S },
10221 { MEMSET_A32, MEMSET_A32_S },
10222 { MEMSET_A64, MEMSET_A64_S },
10223 { MIN_F16x8, MIN_F16x8_S },
10224 { MIN_F32, MIN_F32_S },
10225 { MIN_F32x4, MIN_F32x4_S },
10226 { MIN_F64, MIN_F64_S },
10227 { MIN_F64x2, MIN_F64x2_S },
10228 { MIN_S_I16x8, MIN_S_I16x8_S },
10229 { MIN_S_I32x4, MIN_S_I32x4_S },
10230 { MIN_S_I8x16, MIN_S_I8x16_S },
10231 { MIN_U_I16x8, MIN_U_I16x8_S },
10232 { MIN_U_I32x4, MIN_U_I32x4_S },
10233 { MIN_U_I8x16, MIN_U_I8x16_S },
10234 { MUL_F16x8, MUL_F16x8_S },
10235 { MUL_F32, MUL_F32_S },
10236 { MUL_F32x4, MUL_F32x4_S },
10237 { MUL_F64, MUL_F64_S },
10238 { MUL_F64x2, MUL_F64x2_S },
10239 { MUL_I16x8, MUL_I16x8_S },
10240 { MUL_I32, MUL_I32_S },
10241 { MUL_I32x4, MUL_I32x4_S },
10242 { MUL_I64, MUL_I64_S },
10243 { MUL_I64x2, MUL_I64x2_S },
10244 { NARROW_S_I16x8, NARROW_S_I16x8_S },
10245 { NARROW_S_I8x16, NARROW_S_I8x16_S },
10246 { NARROW_U_I16x8, NARROW_U_I16x8_S },
10247 { NARROW_U_I8x16, NARROW_U_I8x16_S },
10248 { NEAREST_F16x8, NEAREST_F16x8_S },
10249 { NEAREST_F32, NEAREST_F32_S },
10250 { NEAREST_F32x4, NEAREST_F32x4_S },
10251 { NEAREST_F64, NEAREST_F64_S },
10252 { NEAREST_F64x2, NEAREST_F64x2_S },
10253 { NEG_F16x8, NEG_F16x8_S },
10254 { NEG_F32, NEG_F32_S },
10255 { NEG_F32x4, NEG_F32x4_S },
10256 { NEG_F64, NEG_F64_S },
10257 { NEG_F64x2, NEG_F64x2_S },
10258 { NEG_I16x8, NEG_I16x8_S },
10259 { NEG_I32x4, NEG_I32x4_S },
10260 { NEG_I64x2, NEG_I64x2_S },
10261 { NEG_I8x16, NEG_I8x16_S },
10262 { NE_F16x8, NE_F16x8_S },
10263 { NE_F32, NE_F32_S },
10264 { NE_F32x4, NE_F32x4_S },
10265 { NE_F64, NE_F64_S },
10266 { NE_F64x2, NE_F64x2_S },
10267 { NE_I16x8, NE_I16x8_S },
10268 { NE_I32, NE_I32_S },
10269 { NE_I32x4, NE_I32x4_S },
10270 { NE_I64, NE_I64_S },
10271 { NE_I64x2, NE_I64x2_S },
10272 { NE_I8x16, NE_I8x16_S },
10273 { NMADD_F16x8, NMADD_F16x8_S },
10274 { NMADD_F32x4, NMADD_F32x4_S },
10275 { NMADD_F64x2, NMADD_F64x2_S },
10276 { NOP, NOP_S },
10277 { NOT, NOT_S },
10278 { OR, OR_S },
10279 { OR_I32, OR_I32_S },
10280 { OR_I64, OR_I64_S },
10281 { PMAX_F16x8, PMAX_F16x8_S },
10282 { PMAX_F32x4, PMAX_F32x4_S },
10283 { PMAX_F64x2, PMAX_F64x2_S },
10284 { PMIN_F16x8, PMIN_F16x8_S },
10285 { PMIN_F32x4, PMIN_F32x4_S },
10286 { PMIN_F64x2, PMIN_F64x2_S },
10287 { POPCNT_I32, POPCNT_I32_S },
10288 { POPCNT_I64, POPCNT_I64_S },
10289 { POPCNT_I8x16, POPCNT_I8x16_S },
10290 { Q15MULR_SAT_S_I16x8, Q15MULR_SAT_S_I16x8_S },
10291 { REF_FUNC, REF_FUNC_S },
10292 { REF_IS_NULL_EXNREF, REF_IS_NULL_EXNREF_S },
10293 { REF_IS_NULL_EXTERNREF, REF_IS_NULL_EXTERNREF_S },
10294 { REF_IS_NULL_FUNCREF, REF_IS_NULL_FUNCREF_S },
10295 { REF_NULL_EXNREF, REF_NULL_EXNREF_S },
10296 { REF_NULL_EXTERNREF, REF_NULL_EXTERNREF_S },
10297 { REF_NULL_FUNCREF, REF_NULL_FUNCREF_S },
10298 { REF_TEST_FUNCREF, REF_TEST_FUNCREF_S },
10299 { RELAXED_DOT, RELAXED_DOT_S },
10300 { RELAXED_DOT_ADD, RELAXED_DOT_ADD_S },
10301 { RELAXED_DOT_BFLOAT, RELAXED_DOT_BFLOAT_S },
10302 { RELAXED_Q15MULR_S_I16x8, RELAXED_Q15MULR_S_I16x8_S },
10303 { RELAXED_SWIZZLE, RELAXED_SWIZZLE_S },
10304 { REM_S_I32, REM_S_I32_S },
10305 { REM_S_I64, REM_S_I64_S },
10306 { REM_U_I32, REM_U_I32_S },
10307 { REM_U_I64, REM_U_I64_S },
10308 { REPLACE_LANE_F16x8, REPLACE_LANE_F16x8_S },
10309 { REPLACE_LANE_F32x4, REPLACE_LANE_F32x4_S },
10310 { REPLACE_LANE_F64x2, REPLACE_LANE_F64x2_S },
10311 { REPLACE_LANE_I16x8, REPLACE_LANE_I16x8_S },
10312 { REPLACE_LANE_I32x4, REPLACE_LANE_I32x4_S },
10313 { REPLACE_LANE_I64x2, REPLACE_LANE_I64x2_S },
10314 { REPLACE_LANE_I8x16, REPLACE_LANE_I8x16_S },
10315 { RETHROW, RETHROW_S },
10316 { RETURN, RETURN_S },
10317 { RET_CALL, RET_CALL_S },
10318 { RET_CALL_INDIRECT, RET_CALL_INDIRECT_S },
10319 { ROTL_I32, ROTL_I32_S },
10320 { ROTL_I64, ROTL_I64_S },
10321 { ROTR_I32, ROTR_I32_S },
10322 { ROTR_I64, ROTR_I64_S },
10323 { SELECT_EXNREF, SELECT_EXNREF_S },
10324 { SELECT_EXTERNREF, SELECT_EXTERNREF_S },
10325 { SELECT_F32, SELECT_F32_S },
10326 { SELECT_F64, SELECT_F64_S },
10327 { SELECT_FUNCREF, SELECT_FUNCREF_S },
10328 { SELECT_I32, SELECT_I32_S },
10329 { SELECT_I64, SELECT_I64_S },
10330 { SELECT_V128, SELECT_V128_S },
10331 { SHL_I16x8, SHL_I16x8_S },
10332 { SHL_I32, SHL_I32_S },
10333 { SHL_I32x4, SHL_I32x4_S },
10334 { SHL_I64, SHL_I64_S },
10335 { SHL_I64x2, SHL_I64x2_S },
10336 { SHL_I8x16, SHL_I8x16_S },
10337 { SHR_S_I16x8, SHR_S_I16x8_S },
10338 { SHR_S_I32, SHR_S_I32_S },
10339 { SHR_S_I32x4, SHR_S_I32x4_S },
10340 { SHR_S_I64, SHR_S_I64_S },
10341 { SHR_S_I64x2, SHR_S_I64x2_S },
10342 { SHR_S_I8x16, SHR_S_I8x16_S },
10343 { SHR_U_I16x8, SHR_U_I16x8_S },
10344 { SHR_U_I32, SHR_U_I32_S },
10345 { SHR_U_I32x4, SHR_U_I32x4_S },
10346 { SHR_U_I64, SHR_U_I64_S },
10347 { SHR_U_I64x2, SHR_U_I64x2_S },
10348 { SHR_U_I8x16, SHR_U_I8x16_S },
10349 { SHUFFLE, SHUFFLE_S },
10350 { SIMD_RELAXED_FMAX_F32x4, SIMD_RELAXED_FMAX_F32x4_S },
10351 { SIMD_RELAXED_FMAX_F64x2, SIMD_RELAXED_FMAX_F64x2_S },
10352 { SIMD_RELAXED_FMIN_F32x4, SIMD_RELAXED_FMIN_F32x4_S },
10353 { SIMD_RELAXED_FMIN_F64x2, SIMD_RELAXED_FMIN_F64x2_S },
10354 { SPLAT_F16x8, SPLAT_F16x8_S },
10355 { SPLAT_F32x4, SPLAT_F32x4_S },
10356 { SPLAT_F64x2, SPLAT_F64x2_S },
10357 { SPLAT_I16x8, SPLAT_I16x8_S },
10358 { SPLAT_I32x4, SPLAT_I32x4_S },
10359 { SPLAT_I64x2, SPLAT_I64x2_S },
10360 { SPLAT_I8x16, SPLAT_I8x16_S },
10361 { SQRT_F16x8, SQRT_F16x8_S },
10362 { SQRT_F32, SQRT_F32_S },
10363 { SQRT_F32x4, SQRT_F32x4_S },
10364 { SQRT_F64, SQRT_F64_S },
10365 { SQRT_F64x2, SQRT_F64x2_S },
10366 { STORE16_I32_A32, STORE16_I32_A32_S },
10367 { STORE16_I32_A64, STORE16_I32_A64_S },
10368 { STORE16_I64_A32, STORE16_I64_A32_S },
10369 { STORE16_I64_A64, STORE16_I64_A64_S },
10370 { STORE32_I64_A32, STORE32_I64_A32_S },
10371 { STORE32_I64_A64, STORE32_I64_A64_S },
10372 { STORE8_I32_A32, STORE8_I32_A32_S },
10373 { STORE8_I32_A64, STORE8_I32_A64_S },
10374 { STORE8_I64_A32, STORE8_I64_A32_S },
10375 { STORE8_I64_A64, STORE8_I64_A64_S },
10376 { STORE_F16_F32_A32, STORE_F16_F32_A32_S },
10377 { STORE_F16_F32_A64, STORE_F16_F32_A64_S },
10378 { STORE_F32_A32, STORE_F32_A32_S },
10379 { STORE_F32_A64, STORE_F32_A64_S },
10380 { STORE_F64_A32, STORE_F64_A32_S },
10381 { STORE_F64_A64, STORE_F64_A64_S },
10382 { STORE_I32_A32, STORE_I32_A32_S },
10383 { STORE_I32_A64, STORE_I32_A64_S },
10384 { STORE_I64_A32, STORE_I64_A32_S },
10385 { STORE_I64_A64, STORE_I64_A64_S },
10386 { STORE_LANE_I16x8_A32, STORE_LANE_I16x8_A32_S },
10387 { STORE_LANE_I16x8_A64, STORE_LANE_I16x8_A64_S },
10388 { STORE_LANE_I32x4_A32, STORE_LANE_I32x4_A32_S },
10389 { STORE_LANE_I32x4_A64, STORE_LANE_I32x4_A64_S },
10390 { STORE_LANE_I64x2_A32, STORE_LANE_I64x2_A32_S },
10391 { STORE_LANE_I64x2_A64, STORE_LANE_I64x2_A64_S },
10392 { STORE_LANE_I8x16_A32, STORE_LANE_I8x16_A32_S },
10393 { STORE_LANE_I8x16_A64, STORE_LANE_I8x16_A64_S },
10394 { STORE_V128_A32, STORE_V128_A32_S },
10395 { STORE_V128_A64, STORE_V128_A64_S },
10396 { SUB_F16x8, SUB_F16x8_S },
10397 { SUB_F32, SUB_F32_S },
10398 { SUB_F32x4, SUB_F32x4_S },
10399 { SUB_F64, SUB_F64_S },
10400 { SUB_F64x2, SUB_F64x2_S },
10401 { SUB_I16x8, SUB_I16x8_S },
10402 { SUB_I32, SUB_I32_S },
10403 { SUB_I32x4, SUB_I32x4_S },
10404 { SUB_I64, SUB_I64_S },
10405 { SUB_I64x2, SUB_I64x2_S },
10406 { SUB_I8x16, SUB_I8x16_S },
10407 { SUB_SAT_S_I16x8, SUB_SAT_S_I16x8_S },
10408 { SUB_SAT_S_I8x16, SUB_SAT_S_I8x16_S },
10409 { SUB_SAT_U_I16x8, SUB_SAT_U_I16x8_S },
10410 { SUB_SAT_U_I8x16, SUB_SAT_U_I8x16_S },
10411 { SWIZZLE, SWIZZLE_S },
10412 { TABLE_COPY, TABLE_COPY_S },
10413 { TABLE_FILL_EXNREF, TABLE_FILL_EXNREF_S },
10414 { TABLE_FILL_EXTERNREF, TABLE_FILL_EXTERNREF_S },
10415 { TABLE_FILL_FUNCREF, TABLE_FILL_FUNCREF_S },
10416 { TABLE_GET_EXNREF, TABLE_GET_EXNREF_S },
10417 { TABLE_GET_EXTERNREF, TABLE_GET_EXTERNREF_S },
10418 { TABLE_GET_FUNCREF, TABLE_GET_FUNCREF_S },
10419 { TABLE_GROW_EXNREF, TABLE_GROW_EXNREF_S },
10420 { TABLE_GROW_EXTERNREF, TABLE_GROW_EXTERNREF_S },
10421 { TABLE_GROW_FUNCREF, TABLE_GROW_FUNCREF_S },
10422 { TABLE_SET_EXNREF, TABLE_SET_EXNREF_S },
10423 { TABLE_SET_EXTERNREF, TABLE_SET_EXTERNREF_S },
10424 { TABLE_SET_FUNCREF, TABLE_SET_FUNCREF_S },
10425 { TABLE_SIZE, TABLE_SIZE_S },
10426 { TEE_EXNREF, TEE_EXNREF_S },
10427 { TEE_EXTERNREF, TEE_EXTERNREF_S },
10428 { TEE_F32, TEE_F32_S },
10429 { TEE_F64, TEE_F64_S },
10430 { TEE_FUNCREF, TEE_FUNCREF_S },
10431 { TEE_I32, TEE_I32_S },
10432 { TEE_I64, TEE_I64_S },
10433 { TEE_V128, TEE_V128_S },
10434 { THROW, THROW_S },
10435 { THROW_REF, THROW_REF_S },
10436 { TRUNC_F16x8, TRUNC_F16x8_S },
10437 { TRUNC_F32, TRUNC_F32_S },
10438 { TRUNC_F32x4, TRUNC_F32x4_S },
10439 { TRUNC_F64, TRUNC_F64_S },
10440 { TRUNC_F64x2, TRUNC_F64x2_S },
10441 { TRY, TRY_S },
10442 { TRY_TABLE, TRY_TABLE_S },
10443 { UNREACHABLE, UNREACHABLE_S },
10444 { XOR, XOR_S },
10445 { XOR_I32, XOR_I32_S },
10446 { XOR_I64, XOR_I64_S },
10447 { anonymous_13975MEMORY_GROW_A32, anonymous_13975MEMORY_GROW_A32_S },
10448 { anonymous_13975MEMORY_SIZE_A32, anonymous_13975MEMORY_SIZE_A32_S },
10449 { anonymous_13976MEMORY_GROW_A64, anonymous_13976MEMORY_GROW_A64_S },
10450 { anonymous_13976MEMORY_SIZE_A64, anonymous_13976MEMORY_SIZE_A64_S },
10451 { convert_low_s_F64x2, convert_low_s_F64x2_S },
10452 { convert_low_u_F64x2, convert_low_u_F64x2_S },
10453 { demote_zero_F32x4, demote_zero_F32x4_S },
10454 { extadd_pairwise_s_I16x8, extadd_pairwise_s_I16x8_S },
10455 { extadd_pairwise_s_I32x4, extadd_pairwise_s_I32x4_S },
10456 { extadd_pairwise_u_I16x8, extadd_pairwise_u_I16x8_S },
10457 { extadd_pairwise_u_I32x4, extadd_pairwise_u_I32x4_S },
10458 { extend_high_s_I16x8, extend_high_s_I16x8_S },
10459 { extend_high_s_I32x4, extend_high_s_I32x4_S },
10460 { extend_high_s_I64x2, extend_high_s_I64x2_S },
10461 { extend_high_u_I16x8, extend_high_u_I16x8_S },
10462 { extend_high_u_I32x4, extend_high_u_I32x4_S },
10463 { extend_high_u_I64x2, extend_high_u_I64x2_S },
10464 { extend_low_s_I16x8, extend_low_s_I16x8_S },
10465 { extend_low_s_I32x4, extend_low_s_I32x4_S },
10466 { extend_low_s_I64x2, extend_low_s_I64x2_S },
10467 { extend_low_u_I16x8, extend_low_u_I16x8_S },
10468 { extend_low_u_I32x4, extend_low_u_I32x4_S },
10469 { extend_low_u_I64x2, extend_low_u_I64x2_S },
10470 { fp_to_sint_I16x8, fp_to_sint_I16x8_S },
10471 { fp_to_sint_I32x4, fp_to_sint_I32x4_S },
10472 { fp_to_uint_I16x8, fp_to_uint_I16x8_S },
10473 { fp_to_uint_I32x4, fp_to_uint_I32x4_S },
10474 { int_wasm_relaxed_trunc_signed_I32x4, int_wasm_relaxed_trunc_signed_I32x4_S },
10475 { int_wasm_relaxed_trunc_signed_zero_I32x4, int_wasm_relaxed_trunc_signed_zero_I32x4_S },
10476 { int_wasm_relaxed_trunc_unsigned_I32x4, int_wasm_relaxed_trunc_unsigned_I32x4_S },
10477 { int_wasm_relaxed_trunc_unsigned_zero_I32x4, int_wasm_relaxed_trunc_unsigned_zero_I32x4_S },
10478 { promote_low_F64x2, promote_low_F64x2_S },
10479 { sint_to_fp_F16x8, sint_to_fp_F16x8_S },
10480 { sint_to_fp_F32x4, sint_to_fp_F32x4_S },
10481 { trunc_sat_zero_s_I32x4, trunc_sat_zero_s_I32x4_S },
10482 { trunc_sat_zero_u_I32x4, trunc_sat_zero_u_I32x4_S },
10483 { uint_to_fp_F16x8, uint_to_fp_F16x8_S },
10484 { uint_to_fp_F32x4, uint_to_fp_F32x4_S },
10485 }; // End of Table
10486
10487 unsigned mid;
10488 unsigned start = 0;
10489 unsigned end = 817;
10490 while (start < end) {
10491 mid = start + (end - start) / 2;
10492 if (Opcode == Table[mid][0])
10493 break;
10494 if (Opcode < Table[mid][0])
10495 end = mid;
10496 else
10497 start = mid + 1;
10498 }
10499 if (start == end)
10500 return -1; // Instruction doesn't exist in this table.
10501
10502 return Table[mid][1];
10503}
10504
10505// getWasm64Opcode
10506LLVM_READONLY
10507int32_t getWasm64Opcode(uint32_t Opcode) {
10508 using namespace WebAssembly;
10509 static constexpr uint32_t Table[][2] = {
10510 { ATOMIC_LOAD16_U_I32_A32, ATOMIC_LOAD16_U_I32_A64 },
10511 { ATOMIC_LOAD16_U_I32_A32_S, ATOMIC_LOAD16_U_I32_A64_S },
10512 { ATOMIC_LOAD16_U_I64_A32, ATOMIC_LOAD16_U_I64_A64 },
10513 { ATOMIC_LOAD16_U_I64_A32_S, ATOMIC_LOAD16_U_I64_A64_S },
10514 { ATOMIC_LOAD32_U_I64_A32, ATOMIC_LOAD32_U_I64_A64 },
10515 { ATOMIC_LOAD32_U_I64_A32_S, ATOMIC_LOAD32_U_I64_A64_S },
10516 { ATOMIC_LOAD8_U_I32_A32, ATOMIC_LOAD8_U_I32_A64 },
10517 { ATOMIC_LOAD8_U_I32_A32_S, ATOMIC_LOAD8_U_I32_A64_S },
10518 { ATOMIC_LOAD8_U_I64_A32, ATOMIC_LOAD8_U_I64_A64 },
10519 { ATOMIC_LOAD8_U_I64_A32_S, ATOMIC_LOAD8_U_I64_A64_S },
10520 { ATOMIC_LOAD_I32_A32, ATOMIC_LOAD_I32_A64 },
10521 { ATOMIC_LOAD_I32_A32_S, ATOMIC_LOAD_I32_A64_S },
10522 { ATOMIC_LOAD_I64_A32, ATOMIC_LOAD_I64_A64 },
10523 { ATOMIC_LOAD_I64_A32_S, ATOMIC_LOAD_I64_A64_S },
10524 { ATOMIC_RMW16_U_ADD_I32_A32, ATOMIC_RMW16_U_ADD_I32_A64 },
10525 { ATOMIC_RMW16_U_ADD_I32_A32_S, ATOMIC_RMW16_U_ADD_I32_A64_S },
10526 { ATOMIC_RMW16_U_ADD_I64_A32, ATOMIC_RMW16_U_ADD_I64_A64 },
10527 { ATOMIC_RMW16_U_ADD_I64_A32_S, ATOMIC_RMW16_U_ADD_I64_A64_S },
10528 { ATOMIC_RMW16_U_AND_I32_A32, ATOMIC_RMW16_U_AND_I32_A64 },
10529 { ATOMIC_RMW16_U_AND_I32_A32_S, ATOMIC_RMW16_U_AND_I32_A64_S },
10530 { ATOMIC_RMW16_U_AND_I64_A32, ATOMIC_RMW16_U_AND_I64_A64 },
10531 { ATOMIC_RMW16_U_AND_I64_A32_S, ATOMIC_RMW16_U_AND_I64_A64_S },
10532 { ATOMIC_RMW16_U_CMPXCHG_I32_A32, ATOMIC_RMW16_U_CMPXCHG_I32_A64 },
10533 { ATOMIC_RMW16_U_CMPXCHG_I32_A32_S, ATOMIC_RMW16_U_CMPXCHG_I32_A64_S },
10534 { ATOMIC_RMW16_U_CMPXCHG_I64_A32, ATOMIC_RMW16_U_CMPXCHG_I64_A64 },
10535 { ATOMIC_RMW16_U_CMPXCHG_I64_A32_S, ATOMIC_RMW16_U_CMPXCHG_I64_A64_S },
10536 { ATOMIC_RMW16_U_OR_I32_A32, ATOMIC_RMW16_U_OR_I32_A64 },
10537 { ATOMIC_RMW16_U_OR_I32_A32_S, ATOMIC_RMW16_U_OR_I32_A64_S },
10538 { ATOMIC_RMW16_U_OR_I64_A32, ATOMIC_RMW16_U_OR_I64_A64 },
10539 { ATOMIC_RMW16_U_OR_I64_A32_S, ATOMIC_RMW16_U_OR_I64_A64_S },
10540 { ATOMIC_RMW16_U_SUB_I32_A32, ATOMIC_RMW16_U_SUB_I32_A64 },
10541 { ATOMIC_RMW16_U_SUB_I32_A32_S, ATOMIC_RMW16_U_SUB_I32_A64_S },
10542 { ATOMIC_RMW16_U_SUB_I64_A32, ATOMIC_RMW16_U_SUB_I64_A64 },
10543 { ATOMIC_RMW16_U_SUB_I64_A32_S, ATOMIC_RMW16_U_SUB_I64_A64_S },
10544 { ATOMIC_RMW16_U_XCHG_I32_A32, ATOMIC_RMW16_U_XCHG_I32_A64 },
10545 { ATOMIC_RMW16_U_XCHG_I32_A32_S, ATOMIC_RMW16_U_XCHG_I32_A64_S },
10546 { ATOMIC_RMW16_U_XCHG_I64_A32, ATOMIC_RMW16_U_XCHG_I64_A64 },
10547 { ATOMIC_RMW16_U_XCHG_I64_A32_S, ATOMIC_RMW16_U_XCHG_I64_A64_S },
10548 { ATOMIC_RMW16_U_XOR_I32_A32, ATOMIC_RMW16_U_XOR_I32_A64 },
10549 { ATOMIC_RMW16_U_XOR_I32_A32_S, ATOMIC_RMW16_U_XOR_I32_A64_S },
10550 { ATOMIC_RMW16_U_XOR_I64_A32, ATOMIC_RMW16_U_XOR_I64_A64 },
10551 { ATOMIC_RMW16_U_XOR_I64_A32_S, ATOMIC_RMW16_U_XOR_I64_A64_S },
10552 { ATOMIC_RMW32_U_ADD_I64_A32, ATOMIC_RMW32_U_ADD_I64_A64 },
10553 { ATOMIC_RMW32_U_ADD_I64_A32_S, ATOMIC_RMW32_U_ADD_I64_A64_S },
10554 { ATOMIC_RMW32_U_AND_I64_A32, ATOMIC_RMW32_U_AND_I64_A64 },
10555 { ATOMIC_RMW32_U_AND_I64_A32_S, ATOMIC_RMW32_U_AND_I64_A64_S },
10556 { ATOMIC_RMW32_U_CMPXCHG_I64_A32, ATOMIC_RMW32_U_CMPXCHG_I64_A64 },
10557 { ATOMIC_RMW32_U_CMPXCHG_I64_A32_S, ATOMIC_RMW32_U_CMPXCHG_I64_A64_S },
10558 { ATOMIC_RMW32_U_OR_I64_A32, ATOMIC_RMW32_U_OR_I64_A64 },
10559 { ATOMIC_RMW32_U_OR_I64_A32_S, ATOMIC_RMW32_U_OR_I64_A64_S },
10560 { ATOMIC_RMW32_U_SUB_I64_A32, ATOMIC_RMW32_U_SUB_I64_A64 },
10561 { ATOMIC_RMW32_U_SUB_I64_A32_S, ATOMIC_RMW32_U_SUB_I64_A64_S },
10562 { ATOMIC_RMW32_U_XCHG_I64_A32, ATOMIC_RMW32_U_XCHG_I64_A64 },
10563 { ATOMIC_RMW32_U_XCHG_I64_A32_S, ATOMIC_RMW32_U_XCHG_I64_A64_S },
10564 { ATOMIC_RMW32_U_XOR_I64_A32, ATOMIC_RMW32_U_XOR_I64_A64 },
10565 { ATOMIC_RMW32_U_XOR_I64_A32_S, ATOMIC_RMW32_U_XOR_I64_A64_S },
10566 { ATOMIC_RMW8_U_ADD_I32_A32, ATOMIC_RMW8_U_ADD_I32_A64 },
10567 { ATOMIC_RMW8_U_ADD_I32_A32_S, ATOMIC_RMW8_U_ADD_I32_A64_S },
10568 { ATOMIC_RMW8_U_ADD_I64_A32, ATOMIC_RMW8_U_ADD_I64_A64 },
10569 { ATOMIC_RMW8_U_ADD_I64_A32_S, ATOMIC_RMW8_U_ADD_I64_A64_S },
10570 { ATOMIC_RMW8_U_AND_I32_A32, ATOMIC_RMW8_U_AND_I32_A64 },
10571 { ATOMIC_RMW8_U_AND_I32_A32_S, ATOMIC_RMW8_U_AND_I32_A64_S },
10572 { ATOMIC_RMW8_U_AND_I64_A32, ATOMIC_RMW8_U_AND_I64_A64 },
10573 { ATOMIC_RMW8_U_AND_I64_A32_S, ATOMIC_RMW8_U_AND_I64_A64_S },
10574 { ATOMIC_RMW8_U_CMPXCHG_I32_A32, ATOMIC_RMW8_U_CMPXCHG_I32_A64 },
10575 { ATOMIC_RMW8_U_CMPXCHG_I32_A32_S, ATOMIC_RMW8_U_CMPXCHG_I32_A64_S },
10576 { ATOMIC_RMW8_U_CMPXCHG_I64_A32, ATOMIC_RMW8_U_CMPXCHG_I64_A64 },
10577 { ATOMIC_RMW8_U_CMPXCHG_I64_A32_S, ATOMIC_RMW8_U_CMPXCHG_I64_A64_S },
10578 { ATOMIC_RMW8_U_OR_I32_A32, ATOMIC_RMW8_U_OR_I32_A64 },
10579 { ATOMIC_RMW8_U_OR_I32_A32_S, ATOMIC_RMW8_U_OR_I32_A64_S },
10580 { ATOMIC_RMW8_U_OR_I64_A32, ATOMIC_RMW8_U_OR_I64_A64 },
10581 { ATOMIC_RMW8_U_OR_I64_A32_S, ATOMIC_RMW8_U_OR_I64_A64_S },
10582 { ATOMIC_RMW8_U_SUB_I32_A32, ATOMIC_RMW8_U_SUB_I32_A64 },
10583 { ATOMIC_RMW8_U_SUB_I32_A32_S, ATOMIC_RMW8_U_SUB_I32_A64_S },
10584 { ATOMIC_RMW8_U_SUB_I64_A32, ATOMIC_RMW8_U_SUB_I64_A64 },
10585 { ATOMIC_RMW8_U_SUB_I64_A32_S, ATOMIC_RMW8_U_SUB_I64_A64_S },
10586 { ATOMIC_RMW8_U_XCHG_I32_A32, ATOMIC_RMW8_U_XCHG_I32_A64 },
10587 { ATOMIC_RMW8_U_XCHG_I32_A32_S, ATOMIC_RMW8_U_XCHG_I32_A64_S },
10588 { ATOMIC_RMW8_U_XCHG_I64_A32, ATOMIC_RMW8_U_XCHG_I64_A64 },
10589 { ATOMIC_RMW8_U_XCHG_I64_A32_S, ATOMIC_RMW8_U_XCHG_I64_A64_S },
10590 { ATOMIC_RMW8_U_XOR_I32_A32, ATOMIC_RMW8_U_XOR_I32_A64 },
10591 { ATOMIC_RMW8_U_XOR_I32_A32_S, ATOMIC_RMW8_U_XOR_I32_A64_S },
10592 { ATOMIC_RMW8_U_XOR_I64_A32, ATOMIC_RMW8_U_XOR_I64_A64 },
10593 { ATOMIC_RMW8_U_XOR_I64_A32_S, ATOMIC_RMW8_U_XOR_I64_A64_S },
10594 { ATOMIC_RMW_ADD_I32_A32, ATOMIC_RMW_ADD_I32_A64 },
10595 { ATOMIC_RMW_ADD_I32_A32_S, ATOMIC_RMW_ADD_I32_A64_S },
10596 { ATOMIC_RMW_ADD_I64_A32, ATOMIC_RMW_ADD_I64_A64 },
10597 { ATOMIC_RMW_ADD_I64_A32_S, ATOMIC_RMW_ADD_I64_A64_S },
10598 { ATOMIC_RMW_AND_I32_A32, ATOMIC_RMW_AND_I32_A64 },
10599 { ATOMIC_RMW_AND_I32_A32_S, ATOMIC_RMW_AND_I32_A64_S },
10600 { ATOMIC_RMW_AND_I64_A32, ATOMIC_RMW_AND_I64_A64 },
10601 { ATOMIC_RMW_AND_I64_A32_S, ATOMIC_RMW_AND_I64_A64_S },
10602 { ATOMIC_RMW_CMPXCHG_I32_A32, ATOMIC_RMW_CMPXCHG_I32_A64 },
10603 { ATOMIC_RMW_CMPXCHG_I32_A32_S, ATOMIC_RMW_CMPXCHG_I32_A64_S },
10604 { ATOMIC_RMW_CMPXCHG_I64_A32, ATOMIC_RMW_CMPXCHG_I64_A64 },
10605 { ATOMIC_RMW_CMPXCHG_I64_A32_S, ATOMIC_RMW_CMPXCHG_I64_A64_S },
10606 { ATOMIC_RMW_OR_I32_A32, ATOMIC_RMW_OR_I32_A64 },
10607 { ATOMIC_RMW_OR_I32_A32_S, ATOMIC_RMW_OR_I32_A64_S },
10608 { ATOMIC_RMW_OR_I64_A32, ATOMIC_RMW_OR_I64_A64 },
10609 { ATOMIC_RMW_OR_I64_A32_S, ATOMIC_RMW_OR_I64_A64_S },
10610 { ATOMIC_RMW_SUB_I32_A32, ATOMIC_RMW_SUB_I32_A64 },
10611 { ATOMIC_RMW_SUB_I32_A32_S, ATOMIC_RMW_SUB_I32_A64_S },
10612 { ATOMIC_RMW_SUB_I64_A32, ATOMIC_RMW_SUB_I64_A64 },
10613 { ATOMIC_RMW_SUB_I64_A32_S, ATOMIC_RMW_SUB_I64_A64_S },
10614 { ATOMIC_RMW_XCHG_I32_A32, ATOMIC_RMW_XCHG_I32_A64 },
10615 { ATOMIC_RMW_XCHG_I32_A32_S, ATOMIC_RMW_XCHG_I32_A64_S },
10616 { ATOMIC_RMW_XCHG_I64_A32, ATOMIC_RMW_XCHG_I64_A64 },
10617 { ATOMIC_RMW_XCHG_I64_A32_S, ATOMIC_RMW_XCHG_I64_A64_S },
10618 { ATOMIC_RMW_XOR_I32_A32, ATOMIC_RMW_XOR_I32_A64 },
10619 { ATOMIC_RMW_XOR_I32_A32_S, ATOMIC_RMW_XOR_I32_A64_S },
10620 { ATOMIC_RMW_XOR_I64_A32, ATOMIC_RMW_XOR_I64_A64 },
10621 { ATOMIC_RMW_XOR_I64_A32_S, ATOMIC_RMW_XOR_I64_A64_S },
10622 { ATOMIC_STORE16_I32_A32, ATOMIC_STORE16_I32_A64 },
10623 { ATOMIC_STORE16_I32_A32_S, ATOMIC_STORE16_I32_A64_S },
10624 { ATOMIC_STORE16_I64_A32, ATOMIC_STORE16_I64_A64 },
10625 { ATOMIC_STORE16_I64_A32_S, ATOMIC_STORE16_I64_A64_S },
10626 { ATOMIC_STORE32_I64_A32, ATOMIC_STORE32_I64_A64 },
10627 { ATOMIC_STORE32_I64_A32_S, ATOMIC_STORE32_I64_A64_S },
10628 { ATOMIC_STORE8_I32_A32, ATOMIC_STORE8_I32_A64 },
10629 { ATOMIC_STORE8_I32_A32_S, ATOMIC_STORE8_I32_A64_S },
10630 { ATOMIC_STORE8_I64_A32, ATOMIC_STORE8_I64_A64 },
10631 { ATOMIC_STORE8_I64_A32_S, ATOMIC_STORE8_I64_A64_S },
10632 { ATOMIC_STORE_I32_A32, ATOMIC_STORE_I32_A64 },
10633 { ATOMIC_STORE_I32_A32_S, ATOMIC_STORE_I32_A64_S },
10634 { ATOMIC_STORE_I64_A32, ATOMIC_STORE_I64_A64 },
10635 { ATOMIC_STORE_I64_A32_S, ATOMIC_STORE_I64_A64_S },
10636 { LOAD16_S_I32_A32, LOAD16_S_I32_A64 },
10637 { LOAD16_S_I32_A32_S, LOAD16_S_I32_A64_S },
10638 { LOAD16_S_I64_A32, LOAD16_S_I64_A64 },
10639 { LOAD16_S_I64_A32_S, LOAD16_S_I64_A64_S },
10640 { LOAD16_U_I32_A32, LOAD16_U_I32_A64 },
10641 { LOAD16_U_I32_A32_S, LOAD16_U_I32_A64_S },
10642 { LOAD16_U_I64_A32, LOAD16_U_I64_A64 },
10643 { LOAD16_U_I64_A32_S, LOAD16_U_I64_A64_S },
10644 { LOAD32_S_I64_A32, LOAD32_S_I64_A64 },
10645 { LOAD32_S_I64_A32_S, LOAD32_S_I64_A64_S },
10646 { LOAD32_U_I64_A32, LOAD32_U_I64_A64 },
10647 { LOAD32_U_I64_A32_S, LOAD32_U_I64_A64_S },
10648 { LOAD8_S_I32_A32, LOAD8_S_I32_A64 },
10649 { LOAD8_S_I32_A32_S, LOAD8_S_I32_A64_S },
10650 { LOAD8_S_I64_A32, LOAD8_S_I64_A64 },
10651 { LOAD8_S_I64_A32_S, LOAD8_S_I64_A64_S },
10652 { LOAD8_U_I32_A32, LOAD8_U_I32_A64 },
10653 { LOAD8_U_I32_A32_S, LOAD8_U_I32_A64_S },
10654 { LOAD8_U_I64_A32, LOAD8_U_I64_A64 },
10655 { LOAD8_U_I64_A32_S, LOAD8_U_I64_A64_S },
10656 { LOAD_F16_F32_A32, LOAD_F16_F32_A64 },
10657 { LOAD_F16_F32_A32_S, LOAD_F16_F32_A64_S },
10658 { LOAD_F32_A32, LOAD_F32_A64 },
10659 { LOAD_F32_A32_S, LOAD_F32_A64_S },
10660 { LOAD_F64_A32, LOAD_F64_A64 },
10661 { LOAD_F64_A32_S, LOAD_F64_A64_S },
10662 { LOAD_I32_A32, LOAD_I32_A64 },
10663 { LOAD_I32_A32_S, LOAD_I32_A64_S },
10664 { LOAD_I64_A32, LOAD_I64_A64 },
10665 { LOAD_I64_A32_S, LOAD_I64_A64_S },
10666 { MEMORY_ATOMIC_NOTIFY_A32, MEMORY_ATOMIC_NOTIFY_A64 },
10667 { MEMORY_ATOMIC_NOTIFY_A32_S, MEMORY_ATOMIC_NOTIFY_A64_S },
10668 { MEMORY_ATOMIC_WAIT32_A32, MEMORY_ATOMIC_WAIT32_A64 },
10669 { MEMORY_ATOMIC_WAIT32_A32_S, MEMORY_ATOMIC_WAIT32_A64_S },
10670 { MEMORY_ATOMIC_WAIT64_A32, MEMORY_ATOMIC_WAIT64_A64 },
10671 { MEMORY_ATOMIC_WAIT64_A32_S, MEMORY_ATOMIC_WAIT64_A64_S },
10672 { STORE16_I32_A32, STORE16_I32_A64 },
10673 { STORE16_I32_A32_S, STORE16_I32_A64_S },
10674 { STORE16_I64_A32, STORE16_I64_A64 },
10675 { STORE16_I64_A32_S, STORE16_I64_A64_S },
10676 { STORE32_I64_A32, STORE32_I64_A64 },
10677 { STORE32_I64_A32_S, STORE32_I64_A64_S },
10678 { STORE8_I32_A32, STORE8_I32_A64 },
10679 { STORE8_I32_A32_S, STORE8_I32_A64_S },
10680 { STORE8_I64_A32, STORE8_I64_A64 },
10681 { STORE8_I64_A32_S, STORE8_I64_A64_S },
10682 { STORE_F16_F32_A32, STORE_F16_F32_A64 },
10683 { STORE_F16_F32_A32_S, STORE_F16_F32_A64_S },
10684 { STORE_F32_A32, STORE_F32_A64 },
10685 { STORE_F32_A32_S, STORE_F32_A64_S },
10686 { STORE_F64_A32, STORE_F64_A64 },
10687 { STORE_F64_A32_S, STORE_F64_A64_S },
10688 { STORE_I32_A32, STORE_I32_A64 },
10689 { STORE_I32_A32_S, STORE_I32_A64_S },
10690 { STORE_I64_A32, STORE_I64_A64 },
10691 { STORE_I64_A32_S, STORE_I64_A64_S },
10692 }; // End of Table
10693
10694 unsigned mid;
10695 unsigned start = 0;
10696 unsigned end = 182;
10697 while (start < end) {
10698 mid = start + (end - start) / 2;
10699 if (Opcode == Table[mid][0])
10700 break;
10701 if (Opcode < Table[mid][0])
10702 end = mid;
10703 else
10704 start = mid + 1;
10705 }
10706 if (start == end)
10707 return -1; // Instruction doesn't exist in this table.
10708
10709 return Table[mid][1];
10710}
10711
10712
10713} // namespace llvm::WebAssembly
10714
10715#endif // GET_INSTRMAP_INFO
10716
10717