| 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
|---|---|
| 2 | |* *| |
| 3 | |* Target Instruction Enum Values and Descriptors *| |
| 4 | |* *| |
| 5 | |* Automatically generated file, do not edit! *| |
| 6 | |* *| |
| 7 | \*===----------------------------------------------------------------------===*/ |
| 8 | |
| 9 | #ifdef GET_INSTRINFO_ENUM |
| 10 | #undef GET_INSTRINFO_ENUM |
| 11 | |
| 12 | namespace llvm::WebAssembly { |
| 13 | |
| 14 | enum { |
| 15 | PHI = 0, // Target.td:1314 |
| 16 | INLINEASM = 1, // Target.td:1320 |
| 17 | INLINEASM_BR = 2, // Target.td:1326 |
| 18 | CFI_INSTRUCTION = 3, // Target.td:1335 |
| 19 | EH_LABEL = 4, // Target.td:1344 |
| 20 | GC_LABEL = 5, // Target.td:1353 |
| 21 | ANNOTATION_LABEL = 6, // Target.td:1362 |
| 22 | KILL = 7, // Target.td:1370 |
| 23 | EXTRACT_SUBREG = 8, // Target.td:1377 |
| 24 | INSERT_SUBREG = 9, // Target.td:1383 |
| 25 | IMPLICIT_DEF = 10, // Target.td:1390 |
| 26 | INIT_UNDEF = 11, // Target.td:1399 |
| 27 | SUBREG_TO_REG = 12, // Target.td:1406 |
| 28 | COPY_TO_REGCLASS = 13, // Target.td:1412 |
| 29 | DBG_VALUE = 14, // Target.td:1419 |
| 30 | DBG_VALUE_LIST = 15, // Target.td:1426 |
| 31 | DBG_INSTR_REF = 16, // Target.td:1433 |
| 32 | DBG_PHI = 17, // Target.td:1440 |
| 33 | DBG_LABEL = 18, // Target.td:1447 |
| 34 | REG_SEQUENCE = 19, // Target.td:1454 |
| 35 | COPY = 20, // Target.td:1461 |
| 36 | COPY_LANEMASK = 21, // Target.td:1469 |
| 37 | BUNDLE = 22, // Target.td:1476 |
| 38 | LIFETIME_START = 23, // Target.td:1482 |
| 39 | LIFETIME_END = 24, // Target.td:1489 |
| 40 | PSEUDO_PROBE = 25, // Target.td:1496 |
| 41 | ARITH_FENCE = 26, // Target.td:1503 |
| 42 | STACKMAP = 27, // Target.td:1512 |
| 43 | FENTRY_CALL = 28, // Target.td:1647 |
| 44 | PATCHPOINT = 29, // Target.td:1520 |
| 45 | LOAD_STACK_GUARD = 30, // Target.td:1538 |
| 46 | PREALLOCATED_SETUP = 31, // Target.td:1546 |
| 47 | PREALLOCATED_ARG = 32, // Target.td:1552 |
| 48 | STATEPOINT = 33, // Target.td:1529 |
| 49 | LOCAL_ESCAPE = 34, // Target.td:1558 |
| 50 | FAULTING_OP = 35, // Target.td:1567 |
| 51 | PATCHABLE_OP = 36, // Target.td:1587 |
| 52 | PATCHABLE_FUNCTION_ENTER = 37, // Target.td:1595 |
| 53 | PATCHABLE_RET = 38, // Target.td:1602 |
| 54 | PATCHABLE_FUNCTION_EXIT = 39, // Target.td:1611 |
| 55 | PATCHABLE_TAIL_CALL = 40, // Target.td:1619 |
| 56 | PATCHABLE_EVENT_CALL = 41, // Target.td:1627 |
| 57 | PATCHABLE_TYPED_EVENT_CALL = 42, // Target.td:1637 |
| 58 | ICALL_BRANCH_FUNNEL = 43, // Target.td:1657 |
| 59 | FAKE_USE = 44, // Target.td:1577 |
| 60 | MEMBARRIER = 45, // Target.td:1663 |
| 61 | JUMP_TABLE_DEBUG_INFO = 46, // Target.td:1671 |
| 62 | RELOC_NONE = 47, // Target.td:1679 |
| 63 | CONVERGENCECTRL_ENTRY = 48, // Target.td:1691 |
| 64 | CONVERGENCECTRL_ANCHOR = 49, // Target.td:1687 |
| 65 | CONVERGENCECTRL_LOOP = 50, // Target.td:1695 |
| 66 | CONVERGENCECTRL_GLUE = 51, // Target.td:1699 |
| 67 | G_ASSERT_SEXT = 52, // GenericOpcodes.td:1945 |
| 68 | G_ASSERT_ZEXT = 53, // GenericOpcodes.td:1937 |
| 69 | G_ASSERT_ALIGN = 54, // GenericOpcodes.td:1952 |
| 70 | G_ADD = 55, // GenericOpcodes.td:308 |
| 71 | G_SUB = 56, // GenericOpcodes.td:316 |
| 72 | G_MUL = 57, // GenericOpcodes.td:324 |
| 73 | G_SDIV = 58, // GenericOpcodes.td:332 |
| 74 | G_UDIV = 59, // GenericOpcodes.td:340 |
| 75 | G_SREM = 60, // GenericOpcodes.td:348 |
| 76 | G_UREM = 61, // GenericOpcodes.td:356 |
| 77 | G_SDIVREM = 62, // GenericOpcodes.td:364 |
| 78 | G_UDIVREM = 63, // GenericOpcodes.td:372 |
| 79 | G_AND = 64, // GenericOpcodes.td:380 |
| 80 | G_OR = 65, // GenericOpcodes.td:388 |
| 81 | G_XOR = 66, // GenericOpcodes.td:396 |
| 82 | G_ABDS = 67, // GenericOpcodes.td:425 |
| 83 | G_ABDU = 68, // GenericOpcodes.td:433 |
| 84 | G_UAVGFLOOR = 69, // GenericOpcodes.td:441 |
| 85 | G_UAVGCEIL = 70, // GenericOpcodes.td:448 |
| 86 | G_SAVGFLOOR = 71, // GenericOpcodes.td:455 |
| 87 | G_SAVGCEIL = 72, // GenericOpcodes.td:462 |
| 88 | G_IMPLICIT_DEF = 73, // GenericOpcodes.td:111 |
| 89 | G_PHI = 74, // GenericOpcodes.td:118 |
| 90 | G_FRAME_INDEX = 75, // GenericOpcodes.td:125 |
| 91 | G_GLOBAL_VALUE = 76, // GenericOpcodes.td:131 |
| 92 | G_PTRAUTH_GLOBAL_VALUE = 77, // GenericOpcodes.td:137 |
| 93 | G_CONSTANT_POOL = 78, // GenericOpcodes.td:143 |
| 94 | G_EXTRACT = 79, // GenericOpcodes.td:1530 |
| 95 | G_UNMERGE_VALUES = 80, // GenericOpcodes.td:1543 |
| 96 | G_INSERT = 81, // GenericOpcodes.td:1552 |
| 97 | G_MERGE_VALUES = 82, // GenericOpcodes.td:1562 |
| 98 | G_BUILD_VECTOR = 83, // GenericOpcodes.td:1582 |
| 99 | G_BUILD_VECTOR_TRUNC = 84, // GenericOpcodes.td:1592 |
| 100 | G_CONCAT_VECTORS = 85, // GenericOpcodes.td:1599 |
| 101 | G_PTRTOINT = 86, // GenericOpcodes.td:155 |
| 102 | G_INTTOPTR = 87, // GenericOpcodes.td:149 |
| 103 | G_BITCAST = 88, // GenericOpcodes.td:161 |
| 104 | G_FREEZE = 89, // GenericOpcodes.td:284 |
| 105 | G_CONSTANT_FOLD_BARRIER = 90, // GenericOpcodes.td:1959 |
| 106 | G_INTRINSIC_FPTRUNC_ROUND = 91, // GenericOpcodes.td:1288 |
| 107 | G_INTRINSIC_TRUNC = 92, // GenericOpcodes.td:1294 |
| 108 | G_INTRINSIC_ROUND = 93, // GenericOpcodes.td:1300 |
| 109 | G_INTRINSIC_LRINT = 94, // GenericOpcodes.td:1306 |
| 110 | G_INTRINSIC_LLRINT = 95, // GenericOpcodes.td:1312 |
| 111 | G_INTRINSIC_ROUNDEVEN = 96, // GenericOpcodes.td:1318 |
| 112 | G_READCYCLECOUNTER = 97, // GenericOpcodes.td:1324 |
| 113 | G_READSTEADYCOUNTER = 98, // GenericOpcodes.td:1330 |
| 114 | G_LOAD = 99, // GenericOpcodes.td:1357 |
| 115 | G_SEXTLOAD = 100, // GenericOpcodes.td:1366 |
| 116 | G_ZEXTLOAD = 101, // GenericOpcodes.td:1374 |
| 117 | G_FPEXTLOAD = 102, // GenericOpcodes.td:1383 |
| 118 | G_INDEXED_LOAD = 103, // GenericOpcodes.td:1393 |
| 119 | G_INDEXED_SEXTLOAD = 104, // GenericOpcodes.td:1402 |
| 120 | G_INDEXED_ZEXTLOAD = 105, // GenericOpcodes.td:1410 |
| 121 | G_STORE = 106, // GenericOpcodes.td:1418 |
| 122 | G_FPTRUNCSTORE = 107, // GenericOpcodes.td:1428 |
| 123 | G_INDEXED_STORE = 108, // GenericOpcodes.td:1436 |
| 124 | G_ATOMIC_CMPXCHG_WITH_SUCCESS = 109, // GenericOpcodes.td:1447 |
| 125 | G_ATOMIC_CMPXCHG = 110, // GenericOpcodes.td:1458 |
| 126 | G_ATOMICRMW_XCHG = 111, // GenericOpcodes.td:1478 |
| 127 | G_ATOMICRMW_ADD = 112, // GenericOpcodes.td:1479 |
| 128 | G_ATOMICRMW_SUB = 113, // GenericOpcodes.td:1480 |
| 129 | G_ATOMICRMW_AND = 114, // GenericOpcodes.td:1481 |
| 130 | G_ATOMICRMW_NAND = 115, // GenericOpcodes.td:1482 |
| 131 | G_ATOMICRMW_OR = 116, // GenericOpcodes.td:1483 |
| 132 | G_ATOMICRMW_XOR = 117, // GenericOpcodes.td:1484 |
| 133 | G_ATOMICRMW_MAX = 118, // GenericOpcodes.td:1485 |
| 134 | G_ATOMICRMW_MIN = 119, // GenericOpcodes.td:1486 |
| 135 | G_ATOMICRMW_UMAX = 120, // GenericOpcodes.td:1487 |
| 136 | G_ATOMICRMW_UMIN = 121, // GenericOpcodes.td:1488 |
| 137 | G_ATOMICRMW_FADD = 122, // GenericOpcodes.td:1499 |
| 138 | G_ATOMICRMW_FSUB = 123, // GenericOpcodes.td:1500 |
| 139 | G_ATOMICRMW_FMAX = 124, // GenericOpcodes.td:1501 |
| 140 | G_ATOMICRMW_FMIN = 125, // GenericOpcodes.td:1502 |
| 141 | G_ATOMICRMW_FMAXIMUM = 126, // GenericOpcodes.td:1503 |
| 142 | G_ATOMICRMW_FMINIMUM = 127, // GenericOpcodes.td:1504 |
| 143 | G_ATOMICRMW_FMAXIMUMNUM = 128, // GenericOpcodes.td:1505 |
| 144 | G_ATOMICRMW_FMINIMUMNUM = 129, // GenericOpcodes.td:1506 |
| 145 | G_ATOMICRMW_UINC_WRAP = 130, // GenericOpcodes.td:1489 |
| 146 | G_ATOMICRMW_UDEC_WRAP = 131, // GenericOpcodes.td:1490 |
| 147 | G_ATOMICRMW_USUB_COND = 132, // GenericOpcodes.td:1491 |
| 148 | G_ATOMICRMW_USUB_SAT = 133, // GenericOpcodes.td:1492 |
| 149 | G_FENCE = 134, // GenericOpcodes.td:1508 |
| 150 | G_PREFETCH = 135, // GenericOpcodes.td:1515 |
| 151 | G_BRCOND = 136, // GenericOpcodes.td:1655 |
| 152 | G_BRINDIRECT = 137, // GenericOpcodes.td:1664 |
| 153 | G_INVOKE_REGION_START = 138, // GenericOpcodes.td:1687 |
| 154 | G_INTRINSIC = 139, // GenericOpcodes.td:1607 |
| 155 | G_INTRINSIC_W_SIDE_EFFECTS = 140, // GenericOpcodes.td:1614 |
| 156 | G_INTRINSIC_CONVERGENT = 141, // GenericOpcodes.td:1623 |
| 157 | G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 142, // GenericOpcodes.td:1631 |
| 158 | G_ANYEXT = 143, // GenericOpcodes.td:44 |
| 159 | G_TRUNC = 144, // GenericOpcodes.td:83 |
| 160 | G_TRUNC_SSAT_S = 145, // GenericOpcodes.td:91 |
| 161 | G_TRUNC_SSAT_U = 146, // GenericOpcodes.td:98 |
| 162 | G_TRUNC_USAT_U = 147, // GenericOpcodes.td:105 |
| 163 | G_CONSTANT = 148, // GenericOpcodes.td:169 |
| 164 | G_FCONSTANT = 149, // GenericOpcodes.td:177 |
| 165 | G_VASTART = 150, // GenericOpcodes.td:184 |
| 166 | G_VAARG = 151, // GenericOpcodes.td:191 |
| 167 | G_SEXT = 152, // GenericOpcodes.td:52 |
| 168 | G_SEXT_INREG = 153, // GenericOpcodes.td:66 |
| 169 | G_ZEXT = 154, // GenericOpcodes.td:74 |
| 170 | G_SHL = 155, // GenericOpcodes.td:404 |
| 171 | G_LSHR = 156, // GenericOpcodes.td:411 |
| 172 | G_ASHR = 157, // GenericOpcodes.td:418 |
| 173 | G_FSHL = 158, // GenericOpcodes.td:470 |
| 174 | G_FSHR = 159, // GenericOpcodes.td:478 |
| 175 | G_ROTR = 160, // GenericOpcodes.td:485 |
| 176 | G_ROTL = 161, // GenericOpcodes.td:492 |
| 177 | G_ICMP = 162, // GenericOpcodes.td:499 |
| 178 | G_FCMP = 163, // GenericOpcodes.td:506 |
| 179 | G_SCMP = 164, // GenericOpcodes.td:513 |
| 180 | G_UCMP = 165, // GenericOpcodes.td:520 |
| 181 | G_SELECT = 166, // GenericOpcodes.td:527 |
| 182 | G_UADDO = 167, // GenericOpcodes.td:609 |
| 183 | G_UADDE = 168, // GenericOpcodes.td:617 |
| 184 | G_USUBO = 169, // GenericOpcodes.td:639 |
| 185 | G_USUBE = 170, // GenericOpcodes.td:645 |
| 186 | G_SADDO = 171, // GenericOpcodes.td:624 |
| 187 | G_SADDE = 172, // GenericOpcodes.td:632 |
| 188 | G_SSUBO = 173, // GenericOpcodes.td:652 |
| 189 | G_SSUBE = 174, // GenericOpcodes.td:659 |
| 190 | G_UMULO = 175, // GenericOpcodes.td:666 |
| 191 | G_SMULO = 176, // GenericOpcodes.td:674 |
| 192 | G_UMULH = 177, // GenericOpcodes.td:683 |
| 193 | G_SMULH = 178, // GenericOpcodes.td:692 |
| 194 | G_UADDSAT = 179, // GenericOpcodes.td:704 |
| 195 | G_SADDSAT = 180, // GenericOpcodes.td:712 |
| 196 | G_USUBSAT = 181, // GenericOpcodes.td:720 |
| 197 | G_SSUBSAT = 182, // GenericOpcodes.td:728 |
| 198 | G_USHLSAT = 183, // GenericOpcodes.td:736 |
| 199 | G_SSHLSAT = 184, // GenericOpcodes.td:744 |
| 200 | G_SMULFIX = 185, // GenericOpcodes.td:756 |
| 201 | G_UMULFIX = 186, // GenericOpcodes.td:763 |
| 202 | G_SMULFIXSAT = 187, // GenericOpcodes.td:773 |
| 203 | G_UMULFIXSAT = 188, // GenericOpcodes.td:780 |
| 204 | G_SDIVFIX = 189, // GenericOpcodes.td:791 |
| 205 | G_UDIVFIX = 190, // GenericOpcodes.td:798 |
| 206 | G_SDIVFIXSAT = 191, // GenericOpcodes.td:808 |
| 207 | G_UDIVFIXSAT = 192, // GenericOpcodes.td:815 |
| 208 | G_FADD = 193, // GenericOpcodes.td:988 |
| 209 | G_FSUB = 194, // GenericOpcodes.td:996 |
| 210 | G_FMUL = 195, // GenericOpcodes.td:1004 |
| 211 | G_FMA = 196, // GenericOpcodes.td:1013 |
| 212 | G_FMAD = 197, // GenericOpcodes.td:1022 |
| 213 | G_FDIV = 198, // GenericOpcodes.td:1030 |
| 214 | G_FREM = 199, // GenericOpcodes.td:1037 |
| 215 | G_FMODF = 200, // GenericOpcodes.td:1044 |
| 216 | G_FPOW = 201, // GenericOpcodes.td:1051 |
| 217 | G_FPOWI = 202, // GenericOpcodes.td:1058 |
| 218 | G_FEXP = 203, // GenericOpcodes.td:1065 |
| 219 | G_FEXP2 = 204, // GenericOpcodes.td:1072 |
| 220 | G_FEXP10 = 205, // GenericOpcodes.td:1079 |
| 221 | G_FLOG = 206, // GenericOpcodes.td:1086 |
| 222 | G_FLOG2 = 207, // GenericOpcodes.td:1093 |
| 223 | G_FLOG10 = 208, // GenericOpcodes.td:1100 |
| 224 | G_FLDEXP = 209, // GenericOpcodes.td:1107 |
| 225 | G_FFREXP = 210, // GenericOpcodes.td:1114 |
| 226 | G_FNEG = 211, // GenericOpcodes.td:826 |
| 227 | G_FPEXT = 212, // GenericOpcodes.td:832 |
| 228 | G_FPTRUNC = 213, // GenericOpcodes.td:838 |
| 229 | G_FPTOSI = 214, // GenericOpcodes.td:844 |
| 230 | G_FPTOUI = 215, // GenericOpcodes.td:850 |
| 231 | G_SITOFP = 216, // GenericOpcodes.td:856 |
| 232 | G_UITOFP = 217, // GenericOpcodes.td:862 |
| 233 | G_FPTOSI_SAT = 218, // GenericOpcodes.td:868 |
| 234 | G_FPTOUI_SAT = 219, // GenericOpcodes.td:874 |
| 235 | G_FABS = 220, // GenericOpcodes.td:880 |
| 236 | G_FCOPYSIGN = 221, // GenericOpcodes.td:886 |
| 237 | G_IS_FPCLASS = 222, // GenericOpcodes.td:899 |
| 238 | G_FCANONICALIZE = 223, // GenericOpcodes.td:892 |
| 239 | G_FMINNUM = 224, // GenericOpcodes.td:912 |
| 240 | G_FMAXNUM = 225, // GenericOpcodes.td:919 |
| 241 | G_FMINNUM_IEEE = 226, // GenericOpcodes.td:937 |
| 242 | G_FMAXNUM_IEEE = 227, // GenericOpcodes.td:944 |
| 243 | G_FMINIMUM = 228, // GenericOpcodes.td:954 |
| 244 | G_FMAXIMUM = 229, // GenericOpcodes.td:961 |
| 245 | G_FMINIMUMNUM = 230, // GenericOpcodes.td:969 |
| 246 | G_FMAXIMUMNUM = 231, // GenericOpcodes.td:976 |
| 247 | G_GET_FPENV = 232, // GenericOpcodes.td:1244 |
| 248 | G_SET_FPENV = 233, // GenericOpcodes.td:1251 |
| 249 | G_RESET_FPENV = 234, // GenericOpcodes.td:1258 |
| 250 | G_GET_FPMODE = 235, // GenericOpcodes.td:1265 |
| 251 | G_SET_FPMODE = 236, // GenericOpcodes.td:1272 |
| 252 | G_RESET_FPMODE = 237, // GenericOpcodes.td:1279 |
| 253 | G_GET_ROUNDING = 238, // GenericOpcodes.td:1336 |
| 254 | G_SET_ROUNDING = 239, // GenericOpcodes.td:1342 |
| 255 | G_PTR_ADD = 240, // GenericOpcodes.td:534 |
| 256 | G_PTRMASK = 241, // GenericOpcodes.td:542 |
| 257 | G_SMIN = 242, // GenericOpcodes.td:549 |
| 258 | G_SMAX = 243, // GenericOpcodes.td:557 |
| 259 | G_UMIN = 244, // GenericOpcodes.td:565 |
| 260 | G_UMAX = 245, // GenericOpcodes.td:573 |
| 261 | G_ABS = 246, // GenericOpcodes.td:581 |
| 262 | G_LROUND = 247, // GenericOpcodes.td:291 |
| 263 | G_LLROUND = 248, // GenericOpcodes.td:297 |
| 264 | G_BR = 249, // GenericOpcodes.td:1645 |
| 265 | G_BRJT = 250, // GenericOpcodes.td:1675 |
| 266 | G_VSCALE = 251, // GenericOpcodes.td:1573 |
| 267 | G_INSERT_SUBVECTOR = 252, // GenericOpcodes.td:1719 |
| 268 | G_EXTRACT_SUBVECTOR = 253, // GenericOpcodes.td:1727 |
| 269 | G_INSERT_VECTOR_ELT = 254, // GenericOpcodes.td:1735 |
| 270 | G_EXTRACT_VECTOR_ELT = 255, // GenericOpcodes.td:1743 |
| 271 | G_SHUFFLE_VECTOR = 256, // GenericOpcodes.td:1754 |
| 272 | G_SPLAT_VECTOR = 257, // GenericOpcodes.td:1762 |
| 273 | G_STEP_VECTOR = 258, // GenericOpcodes.td:1770 |
| 274 | G_VECTOR_COMPRESS = 259, // GenericOpcodes.td:1777 |
| 275 | G_CTTZ = 260, // GenericOpcodes.td:211 |
| 276 | G_CTTZ_ZERO_POISON = 261, // GenericOpcodes.td:217 |
| 277 | G_CTLZ = 262, // GenericOpcodes.td:199 |
| 278 | G_CTLZ_ZERO_POISON = 263, // GenericOpcodes.td:205 |
| 279 | G_CTLS = 264, // GenericOpcodes.td:223 |
| 280 | G_CTPOP = 265, // GenericOpcodes.td:229 |
| 281 | G_BSWAP = 266, // GenericOpcodes.td:235 |
| 282 | G_BITREVERSE = 267, // GenericOpcodes.td:242 |
| 283 | G_CLMUL = 268, // GenericOpcodes.td:588 |
| 284 | G_CLMULH = 269, // GenericOpcodes.td:596 |
| 285 | G_FCEIL = 270, // GenericOpcodes.td:1121 |
| 286 | G_FCOS = 271, // GenericOpcodes.td:1128 |
| 287 | G_FSIN = 272, // GenericOpcodes.td:1135 |
| 288 | G_FSINCOS = 273, // GenericOpcodes.td:1142 |
| 289 | G_FTAN = 274, // GenericOpcodes.td:1149 |
| 290 | G_FACOS = 275, // GenericOpcodes.td:1156 |
| 291 | G_FASIN = 276, // GenericOpcodes.td:1163 |
| 292 | G_FATAN = 277, // GenericOpcodes.td:1170 |
| 293 | G_FATAN2 = 278, // GenericOpcodes.td:1177 |
| 294 | G_FCOSH = 279, // GenericOpcodes.td:1184 |
| 295 | G_FSINH = 280, // GenericOpcodes.td:1191 |
| 296 | G_FTANH = 281, // GenericOpcodes.td:1198 |
| 297 | G_FSQRT = 282, // GenericOpcodes.td:1208 |
| 298 | G_FFLOOR = 283, // GenericOpcodes.td:1215 |
| 299 | G_FRINT = 284, // GenericOpcodes.td:1222 |
| 300 | G_FNEARBYINT = 285, // GenericOpcodes.td:1229 |
| 301 | G_ADDRSPACE_CAST = 286, // GenericOpcodes.td:248 |
| 302 | G_BLOCK_ADDR = 287, // GenericOpcodes.td:254 |
| 303 | G_JUMP_TABLE = 288, // GenericOpcodes.td:260 |
| 304 | G_DYN_STACKALLOC = 289, // GenericOpcodes.td:266 |
| 305 | G_STACKSAVE = 290, // GenericOpcodes.td:272 |
| 306 | G_STACKRESTORE = 291, // GenericOpcodes.td:278 |
| 307 | G_STRICT_FADD = 292, // GenericOpcodes.td:1829 |
| 308 | G_STRICT_FSUB = 293, // GenericOpcodes.td:1830 |
| 309 | G_STRICT_FMUL = 294, // GenericOpcodes.td:1831 |
| 310 | G_STRICT_FDIV = 295, // GenericOpcodes.td:1832 |
| 311 | G_STRICT_FREM = 296, // GenericOpcodes.td:1833 |
| 312 | G_STRICT_FMA = 297, // GenericOpcodes.td:1834 |
| 313 | G_STRICT_FSQRT = 298, // GenericOpcodes.td:1835 |
| 314 | G_STRICT_FLDEXP = 299, // GenericOpcodes.td:1836 |
| 315 | G_STRICT_FCMP = 300, // GenericOpcodes.td:1837 |
| 316 | G_STRICT_FCMPS = 301, // GenericOpcodes.td:1838 |
| 317 | G_READ_REGISTER = 302, // GenericOpcodes.td:1694 |
| 318 | G_WRITE_REGISTER = 303, // GenericOpcodes.td:1704 |
| 319 | G_MEMCPY = 304, // GenericOpcodes.td:1844 |
| 320 | G_MEMCPY_INLINE = 305, // GenericOpcodes.td:1852 |
| 321 | G_MEMMOVE = 306, // GenericOpcodes.td:1860 |
| 322 | G_MEMSET = 307, // GenericOpcodes.td:1868 |
| 323 | G_BZERO = 308, // GenericOpcodes.td:1875 |
| 324 | G_MEMSET_INLINE = 309, // GenericOpcodes.td:1882 |
| 325 | G_TRAP = 310, // GenericOpcodes.td:1892 |
| 326 | G_DEBUGTRAP = 311, // GenericOpcodes.td:1899 |
| 327 | G_UBSANTRAP = 312, // GenericOpcodes.td:1905 |
| 328 | G_VECREDUCE_SEQ_FADD = 313, // GenericOpcodes.td:1793 |
| 329 | G_VECREDUCE_SEQ_FMUL = 314, // GenericOpcodes.td:1799 |
| 330 | G_VECREDUCE_FADD = 315, // GenericOpcodes.td:1805 |
| 331 | G_VECREDUCE_FMUL = 316, // GenericOpcodes.td:1806 |
| 332 | G_VECREDUCE_FMAX = 317, // GenericOpcodes.td:1808 |
| 333 | G_VECREDUCE_FMIN = 318, // GenericOpcodes.td:1809 |
| 334 | G_VECREDUCE_FMAXIMUM = 319, // GenericOpcodes.td:1810 |
| 335 | G_VECREDUCE_FMINIMUM = 320, // GenericOpcodes.td:1811 |
| 336 | G_VECREDUCE_FMAXIMUMNUM = 321, // GenericOpcodes.td:1812 |
| 337 | G_VECREDUCE_FMINIMUMNUM = 322, // GenericOpcodes.td:1813 |
| 338 | G_VECREDUCE_ADD = 323, // GenericOpcodes.td:1815 |
| 339 | G_VECREDUCE_MUL = 324, // GenericOpcodes.td:1816 |
| 340 | G_VECREDUCE_AND = 325, // GenericOpcodes.td:1817 |
| 341 | G_VECREDUCE_OR = 326, // GenericOpcodes.td:1818 |
| 342 | G_VECREDUCE_XOR = 327, // GenericOpcodes.td:1819 |
| 343 | G_VECREDUCE_SMAX = 328, // GenericOpcodes.td:1820 |
| 344 | G_VECREDUCE_SMIN = 329, // GenericOpcodes.td:1821 |
| 345 | G_VECREDUCE_UMAX = 330, // GenericOpcodes.td:1822 |
| 346 | G_VECREDUCE_UMIN = 331, // GenericOpcodes.td:1823 |
| 347 | G_SBFX = 332, // GenericOpcodes.td:1917 |
| 348 | G_UBFX = 333, // GenericOpcodes.td:1925 |
| 349 | CALL_PARAMS = 334, // WebAssemblyInstrFormats.td:59 |
| 350 | CALL_PARAMS_S = 335, // WebAssemblyInstrFormats.td:61 |
| 351 | CALL_RESULTS = 336, // WebAssemblyInstrFormats.td:59 |
| 352 | CALL_RESULTS_S = 337, // WebAssemblyInstrFormats.td:61 |
| 353 | CATCHRET = 338, // WebAssemblyInstrFormats.td:59 |
| 354 | CATCHRET_S = 339, // WebAssemblyInstrFormats.td:61 |
| 355 | CLEANUPRET = 340, // WebAssemblyInstrFormats.td:59 |
| 356 | CLEANUPRET_S = 341, // WebAssemblyInstrFormats.td:61 |
| 357 | COMPILER_FENCE = 342, // WebAssemblyInstrFormats.td:59 |
| 358 | COMPILER_FENCE_S = 343, // WebAssemblyInstrFormats.td:61 |
| 359 | RET_CALL_RESULTS = 344, // WebAssemblyInstrFormats.td:59 |
| 360 | RET_CALL_RESULTS_S = 345, // WebAssemblyInstrFormats.td:61 |
| 361 | ABS_F16x8 = 346, // WebAssemblyInstrFormats.td:59 |
| 362 | ABS_F16x8_S = 347, // WebAssemblyInstrFormats.td:61 |
| 363 | ABS_F32 = 348, // WebAssemblyInstrFormats.td:59 |
| 364 | ABS_F32_S = 349, // WebAssemblyInstrFormats.td:61 |
| 365 | ABS_F32x4 = 350, // WebAssemblyInstrFormats.td:59 |
| 366 | ABS_F32x4_S = 351, // WebAssemblyInstrFormats.td:61 |
| 367 | ABS_F64 = 352, // WebAssemblyInstrFormats.td:59 |
| 368 | ABS_F64_S = 353, // WebAssemblyInstrFormats.td:61 |
| 369 | ABS_F64x2 = 354, // WebAssemblyInstrFormats.td:59 |
| 370 | ABS_F64x2_S = 355, // WebAssemblyInstrFormats.td:61 |
| 371 | ABS_I16x8 = 356, // WebAssemblyInstrFormats.td:59 |
| 372 | ABS_I16x8_S = 357, // WebAssemblyInstrFormats.td:61 |
| 373 | ABS_I32x4 = 358, // WebAssemblyInstrFormats.td:59 |
| 374 | ABS_I32x4_S = 359, // WebAssemblyInstrFormats.td:61 |
| 375 | ABS_I64x2 = 360, // WebAssemblyInstrFormats.td:59 |
| 376 | ABS_I64x2_S = 361, // WebAssemblyInstrFormats.td:61 |
| 377 | ABS_I8x16 = 362, // WebAssemblyInstrFormats.td:59 |
| 378 | ABS_I8x16_S = 363, // WebAssemblyInstrFormats.td:61 |
| 379 | ADD_F16x8 = 364, // WebAssemblyInstrFormats.td:59 |
| 380 | ADD_F16x8_S = 365, // WebAssemblyInstrFormats.td:61 |
| 381 | ADD_F32 = 366, // WebAssemblyInstrFormats.td:59 |
| 382 | ADD_F32_S = 367, // WebAssemblyInstrFormats.td:61 |
| 383 | ADD_F32x4 = 368, // WebAssemblyInstrFormats.td:59 |
| 384 | ADD_F32x4_S = 369, // WebAssemblyInstrFormats.td:61 |
| 385 | ADD_F64 = 370, // WebAssemblyInstrFormats.td:59 |
| 386 | ADD_F64_S = 371, // WebAssemblyInstrFormats.td:61 |
| 387 | ADD_F64x2 = 372, // WebAssemblyInstrFormats.td:59 |
| 388 | ADD_F64x2_S = 373, // WebAssemblyInstrFormats.td:61 |
| 389 | ADD_I16x8 = 374, // WebAssemblyInstrFormats.td:59 |
| 390 | ADD_I16x8_S = 375, // WebAssemblyInstrFormats.td:61 |
| 391 | ADD_I32 = 376, // WebAssemblyInstrFormats.td:59 |
| 392 | ADD_I32_S = 377, // WebAssemblyInstrFormats.td:61 |
| 393 | ADD_I32x4 = 378, // WebAssemblyInstrFormats.td:59 |
| 394 | ADD_I32x4_S = 379, // WebAssemblyInstrFormats.td:61 |
| 395 | ADD_I64 = 380, // WebAssemblyInstrFormats.td:59 |
| 396 | ADD_I64_S = 381, // WebAssemblyInstrFormats.td:61 |
| 397 | ADD_I64x2 = 382, // WebAssemblyInstrFormats.td:59 |
| 398 | ADD_I64x2_S = 383, // WebAssemblyInstrFormats.td:61 |
| 399 | ADD_I8x16 = 384, // WebAssemblyInstrFormats.td:59 |
| 400 | ADD_I8x16_S = 385, // WebAssemblyInstrFormats.td:61 |
| 401 | ADD_SAT_S_I16x8 = 386, // WebAssemblyInstrFormats.td:59 |
| 402 | ADD_SAT_S_I16x8_S = 387, // WebAssemblyInstrFormats.td:61 |
| 403 | ADD_SAT_S_I8x16 = 388, // WebAssemblyInstrFormats.td:59 |
| 404 | ADD_SAT_S_I8x16_S = 389, // WebAssemblyInstrFormats.td:61 |
| 405 | ADD_SAT_U_I16x8 = 390, // WebAssemblyInstrFormats.td:59 |
| 406 | ADD_SAT_U_I16x8_S = 391, // WebAssemblyInstrFormats.td:61 |
| 407 | ADD_SAT_U_I8x16 = 392, // WebAssemblyInstrFormats.td:59 |
| 408 | ADD_SAT_U_I8x16_S = 393, // WebAssemblyInstrFormats.td:61 |
| 409 | ADJCALLSTACKDOWN = 394, // WebAssemblyInstrFormats.td:59 |
| 410 | ADJCALLSTACKDOWN_S = 395, // WebAssemblyInstrFormats.td:61 |
| 411 | ADJCALLSTACKUP = 396, // WebAssemblyInstrFormats.td:59 |
| 412 | ADJCALLSTACKUP_S = 397, // WebAssemblyInstrFormats.td:61 |
| 413 | ALLTRUE_I16x8 = 398, // WebAssemblyInstrFormats.td:59 |
| 414 | ALLTRUE_I16x8_S = 399, // WebAssemblyInstrFormats.td:61 |
| 415 | ALLTRUE_I32x4 = 400, // WebAssemblyInstrFormats.td:59 |
| 416 | ALLTRUE_I32x4_S = 401, // WebAssemblyInstrFormats.td:61 |
| 417 | ALLTRUE_I64x2 = 402, // WebAssemblyInstrFormats.td:59 |
| 418 | ALLTRUE_I64x2_S = 403, // WebAssemblyInstrFormats.td:61 |
| 419 | ALLTRUE_I8x16 = 404, // WebAssemblyInstrFormats.td:59 |
| 420 | ALLTRUE_I8x16_S = 405, // WebAssemblyInstrFormats.td:61 |
| 421 | AND = 406, // WebAssemblyInstrFormats.td:59 |
| 422 | ANDNOT = 407, // WebAssemblyInstrFormats.td:59 |
| 423 | ANDNOT_S = 408, // WebAssemblyInstrFormats.td:61 |
| 424 | AND_I32 = 409, // WebAssemblyInstrFormats.td:59 |
| 425 | AND_I32_S = 410, // WebAssemblyInstrFormats.td:61 |
| 426 | AND_I64 = 411, // WebAssemblyInstrFormats.td:59 |
| 427 | AND_I64_S = 412, // WebAssemblyInstrFormats.td:61 |
| 428 | AND_S = 413, // WebAssemblyInstrFormats.td:61 |
| 429 | ANYTRUE = 414, // WebAssemblyInstrFormats.td:59 |
| 430 | ANYTRUE_S = 415, // WebAssemblyInstrFormats.td:61 |
| 431 | ARGUMENT_exnref = 416, // WebAssemblyInstrFormats.td:59 |
| 432 | ARGUMENT_exnref_S = 417, // WebAssemblyInstrFormats.td:61 |
| 433 | ARGUMENT_externref = 418, // WebAssemblyInstrFormats.td:59 |
| 434 | ARGUMENT_externref_S = 419, // WebAssemblyInstrFormats.td:61 |
| 435 | ARGUMENT_f32 = 420, // WebAssemblyInstrFormats.td:59 |
| 436 | ARGUMENT_f32_S = 421, // WebAssemblyInstrFormats.td:61 |
| 437 | ARGUMENT_f64 = 422, // WebAssemblyInstrFormats.td:59 |
| 438 | ARGUMENT_f64_S = 423, // WebAssemblyInstrFormats.td:61 |
| 439 | ARGUMENT_funcref = 424, // WebAssemblyInstrFormats.td:59 |
| 440 | ARGUMENT_funcref_S = 425, // WebAssemblyInstrFormats.td:61 |
| 441 | ARGUMENT_i32 = 426, // WebAssemblyInstrFormats.td:59 |
| 442 | ARGUMENT_i32_S = 427, // WebAssemblyInstrFormats.td:61 |
| 443 | ARGUMENT_i64 = 428, // WebAssemblyInstrFormats.td:59 |
| 444 | ARGUMENT_i64_S = 429, // WebAssemblyInstrFormats.td:61 |
| 445 | ARGUMENT_v16i8 = 430, // WebAssemblyInstrFormats.td:59 |
| 446 | ARGUMENT_v16i8_S = 431, // WebAssemblyInstrFormats.td:61 |
| 447 | ARGUMENT_v2f64 = 432, // WebAssemblyInstrFormats.td:59 |
| 448 | ARGUMENT_v2f64_S = 433, // WebAssemblyInstrFormats.td:61 |
| 449 | ARGUMENT_v2i64 = 434, // WebAssemblyInstrFormats.td:59 |
| 450 | ARGUMENT_v2i64_S = 435, // WebAssemblyInstrFormats.td:61 |
| 451 | ARGUMENT_v4f32 = 436, // WebAssemblyInstrFormats.td:59 |
| 452 | ARGUMENT_v4f32_S = 437, // WebAssemblyInstrFormats.td:61 |
| 453 | ARGUMENT_v4i32 = 438, // WebAssemblyInstrFormats.td:59 |
| 454 | ARGUMENT_v4i32_S = 439, // WebAssemblyInstrFormats.td:61 |
| 455 | ARGUMENT_v8f16 = 440, // WebAssemblyInstrFormats.td:59 |
| 456 | ARGUMENT_v8f16_S = 441, // WebAssemblyInstrFormats.td:61 |
| 457 | ARGUMENT_v8i16 = 442, // WebAssemblyInstrFormats.td:59 |
| 458 | ARGUMENT_v8i16_S = 443, // WebAssemblyInstrFormats.td:61 |
| 459 | ATOMIC_FENCE = 444, // WebAssemblyInstrFormats.td:59 |
| 460 | ATOMIC_FENCE_S = 445, // WebAssemblyInstrFormats.td:61 |
| 461 | ATOMIC_LOAD16_U_I32_A32 = 446, // WebAssemblyInstrFormats.td:59 |
| 462 | ATOMIC_LOAD16_U_I32_A32_S = 447, // WebAssemblyInstrFormats.td:61 |
| 463 | ATOMIC_LOAD16_U_I32_A64 = 448, // WebAssemblyInstrFormats.td:59 |
| 464 | ATOMIC_LOAD16_U_I32_A64_S = 449, // WebAssemblyInstrFormats.td:61 |
| 465 | ATOMIC_LOAD16_U_I64_A32 = 450, // WebAssemblyInstrFormats.td:59 |
| 466 | ATOMIC_LOAD16_U_I64_A32_S = 451, // WebAssemblyInstrFormats.td:61 |
| 467 | ATOMIC_LOAD16_U_I64_A64 = 452, // WebAssemblyInstrFormats.td:59 |
| 468 | ATOMIC_LOAD16_U_I64_A64_S = 453, // WebAssemblyInstrFormats.td:61 |
| 469 | ATOMIC_LOAD32_U_I64_A32 = 454, // WebAssemblyInstrFormats.td:59 |
| 470 | ATOMIC_LOAD32_U_I64_A32_S = 455, // WebAssemblyInstrFormats.td:61 |
| 471 | ATOMIC_LOAD32_U_I64_A64 = 456, // WebAssemblyInstrFormats.td:59 |
| 472 | ATOMIC_LOAD32_U_I64_A64_S = 457, // WebAssemblyInstrFormats.td:61 |
| 473 | ATOMIC_LOAD8_U_I32_A32 = 458, // WebAssemblyInstrFormats.td:59 |
| 474 | ATOMIC_LOAD8_U_I32_A32_S = 459, // WebAssemblyInstrFormats.td:61 |
| 475 | ATOMIC_LOAD8_U_I32_A64 = 460, // WebAssemblyInstrFormats.td:59 |
| 476 | ATOMIC_LOAD8_U_I32_A64_S = 461, // WebAssemblyInstrFormats.td:61 |
| 477 | ATOMIC_LOAD8_U_I64_A32 = 462, // WebAssemblyInstrFormats.td:59 |
| 478 | ATOMIC_LOAD8_U_I64_A32_S = 463, // WebAssemblyInstrFormats.td:61 |
| 479 | ATOMIC_LOAD8_U_I64_A64 = 464, // WebAssemblyInstrFormats.td:59 |
| 480 | ATOMIC_LOAD8_U_I64_A64_S = 465, // WebAssemblyInstrFormats.td:61 |
| 481 | ATOMIC_LOAD_I32_A32 = 466, // WebAssemblyInstrFormats.td:59 |
| 482 | ATOMIC_LOAD_I32_A32_S = 467, // WebAssemblyInstrFormats.td:61 |
| 483 | ATOMIC_LOAD_I32_A64 = 468, // WebAssemblyInstrFormats.td:59 |
| 484 | ATOMIC_LOAD_I32_A64_S = 469, // WebAssemblyInstrFormats.td:61 |
| 485 | ATOMIC_LOAD_I64_A32 = 470, // WebAssemblyInstrFormats.td:59 |
| 486 | ATOMIC_LOAD_I64_A32_S = 471, // WebAssemblyInstrFormats.td:61 |
| 487 | ATOMIC_LOAD_I64_A64 = 472, // WebAssemblyInstrFormats.td:59 |
| 488 | ATOMIC_LOAD_I64_A64_S = 473, // WebAssemblyInstrFormats.td:61 |
| 489 | ATOMIC_RMW16_U_ADD_I32_A32 = 474, // WebAssemblyInstrFormats.td:59 |
| 490 | ATOMIC_RMW16_U_ADD_I32_A32_S = 475, // WebAssemblyInstrFormats.td:61 |
| 491 | ATOMIC_RMW16_U_ADD_I32_A64 = 476, // WebAssemblyInstrFormats.td:59 |
| 492 | ATOMIC_RMW16_U_ADD_I32_A64_S = 477, // WebAssemblyInstrFormats.td:61 |
| 493 | ATOMIC_RMW16_U_ADD_I64_A32 = 478, // WebAssemblyInstrFormats.td:59 |
| 494 | ATOMIC_RMW16_U_ADD_I64_A32_S = 479, // WebAssemblyInstrFormats.td:61 |
| 495 | ATOMIC_RMW16_U_ADD_I64_A64 = 480, // WebAssemblyInstrFormats.td:59 |
| 496 | ATOMIC_RMW16_U_ADD_I64_A64_S = 481, // WebAssemblyInstrFormats.td:61 |
| 497 | ATOMIC_RMW16_U_AND_I32_A32 = 482, // WebAssemblyInstrFormats.td:59 |
| 498 | ATOMIC_RMW16_U_AND_I32_A32_S = 483, // WebAssemblyInstrFormats.td:61 |
| 499 | ATOMIC_RMW16_U_AND_I32_A64 = 484, // WebAssemblyInstrFormats.td:59 |
| 500 | ATOMIC_RMW16_U_AND_I32_A64_S = 485, // WebAssemblyInstrFormats.td:61 |
| 501 | ATOMIC_RMW16_U_AND_I64_A32 = 486, // WebAssemblyInstrFormats.td:59 |
| 502 | ATOMIC_RMW16_U_AND_I64_A32_S = 487, // WebAssemblyInstrFormats.td:61 |
| 503 | ATOMIC_RMW16_U_AND_I64_A64 = 488, // WebAssemblyInstrFormats.td:59 |
| 504 | ATOMIC_RMW16_U_AND_I64_A64_S = 489, // WebAssemblyInstrFormats.td:61 |
| 505 | ATOMIC_RMW16_U_CMPXCHG_I32_A32 = 490, // WebAssemblyInstrFormats.td:59 |
| 506 | ATOMIC_RMW16_U_CMPXCHG_I32_A32_S = 491, // WebAssemblyInstrFormats.td:61 |
| 507 | ATOMIC_RMW16_U_CMPXCHG_I32_A64 = 492, // WebAssemblyInstrFormats.td:59 |
| 508 | ATOMIC_RMW16_U_CMPXCHG_I32_A64_S = 493, // WebAssemblyInstrFormats.td:61 |
| 509 | ATOMIC_RMW16_U_CMPXCHG_I64_A32 = 494, // WebAssemblyInstrFormats.td:59 |
| 510 | ATOMIC_RMW16_U_CMPXCHG_I64_A32_S = 495, // WebAssemblyInstrFormats.td:61 |
| 511 | ATOMIC_RMW16_U_CMPXCHG_I64_A64 = 496, // WebAssemblyInstrFormats.td:59 |
| 512 | ATOMIC_RMW16_U_CMPXCHG_I64_A64_S = 497, // WebAssemblyInstrFormats.td:61 |
| 513 | ATOMIC_RMW16_U_OR_I32_A32 = 498, // WebAssemblyInstrFormats.td:59 |
| 514 | ATOMIC_RMW16_U_OR_I32_A32_S = 499, // WebAssemblyInstrFormats.td:61 |
| 515 | ATOMIC_RMW16_U_OR_I32_A64 = 500, // WebAssemblyInstrFormats.td:59 |
| 516 | ATOMIC_RMW16_U_OR_I32_A64_S = 501, // WebAssemblyInstrFormats.td:61 |
| 517 | ATOMIC_RMW16_U_OR_I64_A32 = 502, // WebAssemblyInstrFormats.td:59 |
| 518 | ATOMIC_RMW16_U_OR_I64_A32_S = 503, // WebAssemblyInstrFormats.td:61 |
| 519 | ATOMIC_RMW16_U_OR_I64_A64 = 504, // WebAssemblyInstrFormats.td:59 |
| 520 | ATOMIC_RMW16_U_OR_I64_A64_S = 505, // WebAssemblyInstrFormats.td:61 |
| 521 | ATOMIC_RMW16_U_SUB_I32_A32 = 506, // WebAssemblyInstrFormats.td:59 |
| 522 | ATOMIC_RMW16_U_SUB_I32_A32_S = 507, // WebAssemblyInstrFormats.td:61 |
| 523 | ATOMIC_RMW16_U_SUB_I32_A64 = 508, // WebAssemblyInstrFormats.td:59 |
| 524 | ATOMIC_RMW16_U_SUB_I32_A64_S = 509, // WebAssemblyInstrFormats.td:61 |
| 525 | ATOMIC_RMW16_U_SUB_I64_A32 = 510, // WebAssemblyInstrFormats.td:59 |
| 526 | ATOMIC_RMW16_U_SUB_I64_A32_S = 511, // WebAssemblyInstrFormats.td:61 |
| 527 | ATOMIC_RMW16_U_SUB_I64_A64 = 512, // WebAssemblyInstrFormats.td:59 |
| 528 | ATOMIC_RMW16_U_SUB_I64_A64_S = 513, // WebAssemblyInstrFormats.td:61 |
| 529 | ATOMIC_RMW16_U_XCHG_I32_A32 = 514, // WebAssemblyInstrFormats.td:59 |
| 530 | ATOMIC_RMW16_U_XCHG_I32_A32_S = 515, // WebAssemblyInstrFormats.td:61 |
| 531 | ATOMIC_RMW16_U_XCHG_I32_A64 = 516, // WebAssemblyInstrFormats.td:59 |
| 532 | ATOMIC_RMW16_U_XCHG_I32_A64_S = 517, // WebAssemblyInstrFormats.td:61 |
| 533 | ATOMIC_RMW16_U_XCHG_I64_A32 = 518, // WebAssemblyInstrFormats.td:59 |
| 534 | ATOMIC_RMW16_U_XCHG_I64_A32_S = 519, // WebAssemblyInstrFormats.td:61 |
| 535 | ATOMIC_RMW16_U_XCHG_I64_A64 = 520, // WebAssemblyInstrFormats.td:59 |
| 536 | ATOMIC_RMW16_U_XCHG_I64_A64_S = 521, // WebAssemblyInstrFormats.td:61 |
| 537 | ATOMIC_RMW16_U_XOR_I32_A32 = 522, // WebAssemblyInstrFormats.td:59 |
| 538 | ATOMIC_RMW16_U_XOR_I32_A32_S = 523, // WebAssemblyInstrFormats.td:61 |
| 539 | ATOMIC_RMW16_U_XOR_I32_A64 = 524, // WebAssemblyInstrFormats.td:59 |
| 540 | ATOMIC_RMW16_U_XOR_I32_A64_S = 525, // WebAssemblyInstrFormats.td:61 |
| 541 | ATOMIC_RMW16_U_XOR_I64_A32 = 526, // WebAssemblyInstrFormats.td:59 |
| 542 | ATOMIC_RMW16_U_XOR_I64_A32_S = 527, // WebAssemblyInstrFormats.td:61 |
| 543 | ATOMIC_RMW16_U_XOR_I64_A64 = 528, // WebAssemblyInstrFormats.td:59 |
| 544 | ATOMIC_RMW16_U_XOR_I64_A64_S = 529, // WebAssemblyInstrFormats.td:61 |
| 545 | ATOMIC_RMW32_U_ADD_I64_A32 = 530, // WebAssemblyInstrFormats.td:59 |
| 546 | ATOMIC_RMW32_U_ADD_I64_A32_S = 531, // WebAssemblyInstrFormats.td:61 |
| 547 | ATOMIC_RMW32_U_ADD_I64_A64 = 532, // WebAssemblyInstrFormats.td:59 |
| 548 | ATOMIC_RMW32_U_ADD_I64_A64_S = 533, // WebAssemblyInstrFormats.td:61 |
| 549 | ATOMIC_RMW32_U_AND_I64_A32 = 534, // WebAssemblyInstrFormats.td:59 |
| 550 | ATOMIC_RMW32_U_AND_I64_A32_S = 535, // WebAssemblyInstrFormats.td:61 |
| 551 | ATOMIC_RMW32_U_AND_I64_A64 = 536, // WebAssemblyInstrFormats.td:59 |
| 552 | ATOMIC_RMW32_U_AND_I64_A64_S = 537, // WebAssemblyInstrFormats.td:61 |
| 553 | ATOMIC_RMW32_U_CMPXCHG_I64_A32 = 538, // WebAssemblyInstrFormats.td:59 |
| 554 | ATOMIC_RMW32_U_CMPXCHG_I64_A32_S = 539, // WebAssemblyInstrFormats.td:61 |
| 555 | ATOMIC_RMW32_U_CMPXCHG_I64_A64 = 540, // WebAssemblyInstrFormats.td:59 |
| 556 | ATOMIC_RMW32_U_CMPXCHG_I64_A64_S = 541, // WebAssemblyInstrFormats.td:61 |
| 557 | ATOMIC_RMW32_U_OR_I64_A32 = 542, // WebAssemblyInstrFormats.td:59 |
| 558 | ATOMIC_RMW32_U_OR_I64_A32_S = 543, // WebAssemblyInstrFormats.td:61 |
| 559 | ATOMIC_RMW32_U_OR_I64_A64 = 544, // WebAssemblyInstrFormats.td:59 |
| 560 | ATOMIC_RMW32_U_OR_I64_A64_S = 545, // WebAssemblyInstrFormats.td:61 |
| 561 | ATOMIC_RMW32_U_SUB_I64_A32 = 546, // WebAssemblyInstrFormats.td:59 |
| 562 | ATOMIC_RMW32_U_SUB_I64_A32_S = 547, // WebAssemblyInstrFormats.td:61 |
| 563 | ATOMIC_RMW32_U_SUB_I64_A64 = 548, // WebAssemblyInstrFormats.td:59 |
| 564 | ATOMIC_RMW32_U_SUB_I64_A64_S = 549, // WebAssemblyInstrFormats.td:61 |
| 565 | ATOMIC_RMW32_U_XCHG_I64_A32 = 550, // WebAssemblyInstrFormats.td:59 |
| 566 | ATOMIC_RMW32_U_XCHG_I64_A32_S = 551, // WebAssemblyInstrFormats.td:61 |
| 567 | ATOMIC_RMW32_U_XCHG_I64_A64 = 552, // WebAssemblyInstrFormats.td:59 |
| 568 | ATOMIC_RMW32_U_XCHG_I64_A64_S = 553, // WebAssemblyInstrFormats.td:61 |
| 569 | ATOMIC_RMW32_U_XOR_I64_A32 = 554, // WebAssemblyInstrFormats.td:59 |
| 570 | ATOMIC_RMW32_U_XOR_I64_A32_S = 555, // WebAssemblyInstrFormats.td:61 |
| 571 | ATOMIC_RMW32_U_XOR_I64_A64 = 556, // WebAssemblyInstrFormats.td:59 |
| 572 | ATOMIC_RMW32_U_XOR_I64_A64_S = 557, // WebAssemblyInstrFormats.td:61 |
| 573 | ATOMIC_RMW8_U_ADD_I32_A32 = 558, // WebAssemblyInstrFormats.td:59 |
| 574 | ATOMIC_RMW8_U_ADD_I32_A32_S = 559, // WebAssemblyInstrFormats.td:61 |
| 575 | ATOMIC_RMW8_U_ADD_I32_A64 = 560, // WebAssemblyInstrFormats.td:59 |
| 576 | ATOMIC_RMW8_U_ADD_I32_A64_S = 561, // WebAssemblyInstrFormats.td:61 |
| 577 | ATOMIC_RMW8_U_ADD_I64_A32 = 562, // WebAssemblyInstrFormats.td:59 |
| 578 | ATOMIC_RMW8_U_ADD_I64_A32_S = 563, // WebAssemblyInstrFormats.td:61 |
| 579 | ATOMIC_RMW8_U_ADD_I64_A64 = 564, // WebAssemblyInstrFormats.td:59 |
| 580 | ATOMIC_RMW8_U_ADD_I64_A64_S = 565, // WebAssemblyInstrFormats.td:61 |
| 581 | ATOMIC_RMW8_U_AND_I32_A32 = 566, // WebAssemblyInstrFormats.td:59 |
| 582 | ATOMIC_RMW8_U_AND_I32_A32_S = 567, // WebAssemblyInstrFormats.td:61 |
| 583 | ATOMIC_RMW8_U_AND_I32_A64 = 568, // WebAssemblyInstrFormats.td:59 |
| 584 | ATOMIC_RMW8_U_AND_I32_A64_S = 569, // WebAssemblyInstrFormats.td:61 |
| 585 | ATOMIC_RMW8_U_AND_I64_A32 = 570, // WebAssemblyInstrFormats.td:59 |
| 586 | ATOMIC_RMW8_U_AND_I64_A32_S = 571, // WebAssemblyInstrFormats.td:61 |
| 587 | ATOMIC_RMW8_U_AND_I64_A64 = 572, // WebAssemblyInstrFormats.td:59 |
| 588 | ATOMIC_RMW8_U_AND_I64_A64_S = 573, // WebAssemblyInstrFormats.td:61 |
| 589 | ATOMIC_RMW8_U_CMPXCHG_I32_A32 = 574, // WebAssemblyInstrFormats.td:59 |
| 590 | ATOMIC_RMW8_U_CMPXCHG_I32_A32_S = 575, // WebAssemblyInstrFormats.td:61 |
| 591 | ATOMIC_RMW8_U_CMPXCHG_I32_A64 = 576, // WebAssemblyInstrFormats.td:59 |
| 592 | ATOMIC_RMW8_U_CMPXCHG_I32_A64_S = 577, // WebAssemblyInstrFormats.td:61 |
| 593 | ATOMIC_RMW8_U_CMPXCHG_I64_A32 = 578, // WebAssemblyInstrFormats.td:59 |
| 594 | ATOMIC_RMW8_U_CMPXCHG_I64_A32_S = 579, // WebAssemblyInstrFormats.td:61 |
| 595 | ATOMIC_RMW8_U_CMPXCHG_I64_A64 = 580, // WebAssemblyInstrFormats.td:59 |
| 596 | ATOMIC_RMW8_U_CMPXCHG_I64_A64_S = 581, // WebAssemblyInstrFormats.td:61 |
| 597 | ATOMIC_RMW8_U_OR_I32_A32 = 582, // WebAssemblyInstrFormats.td:59 |
| 598 | ATOMIC_RMW8_U_OR_I32_A32_S = 583, // WebAssemblyInstrFormats.td:61 |
| 599 | ATOMIC_RMW8_U_OR_I32_A64 = 584, // WebAssemblyInstrFormats.td:59 |
| 600 | ATOMIC_RMW8_U_OR_I32_A64_S = 585, // WebAssemblyInstrFormats.td:61 |
| 601 | ATOMIC_RMW8_U_OR_I64_A32 = 586, // WebAssemblyInstrFormats.td:59 |
| 602 | ATOMIC_RMW8_U_OR_I64_A32_S = 587, // WebAssemblyInstrFormats.td:61 |
| 603 | ATOMIC_RMW8_U_OR_I64_A64 = 588, // WebAssemblyInstrFormats.td:59 |
| 604 | ATOMIC_RMW8_U_OR_I64_A64_S = 589, // WebAssemblyInstrFormats.td:61 |
| 605 | ATOMIC_RMW8_U_SUB_I32_A32 = 590, // WebAssemblyInstrFormats.td:59 |
| 606 | ATOMIC_RMW8_U_SUB_I32_A32_S = 591, // WebAssemblyInstrFormats.td:61 |
| 607 | ATOMIC_RMW8_U_SUB_I32_A64 = 592, // WebAssemblyInstrFormats.td:59 |
| 608 | ATOMIC_RMW8_U_SUB_I32_A64_S = 593, // WebAssemblyInstrFormats.td:61 |
| 609 | ATOMIC_RMW8_U_SUB_I64_A32 = 594, // WebAssemblyInstrFormats.td:59 |
| 610 | ATOMIC_RMW8_U_SUB_I64_A32_S = 595, // WebAssemblyInstrFormats.td:61 |
| 611 | ATOMIC_RMW8_U_SUB_I64_A64 = 596, // WebAssemblyInstrFormats.td:59 |
| 612 | ATOMIC_RMW8_U_SUB_I64_A64_S = 597, // WebAssemblyInstrFormats.td:61 |
| 613 | ATOMIC_RMW8_U_XCHG_I32_A32 = 598, // WebAssemblyInstrFormats.td:59 |
| 614 | ATOMIC_RMW8_U_XCHG_I32_A32_S = 599, // WebAssemblyInstrFormats.td:61 |
| 615 | ATOMIC_RMW8_U_XCHG_I32_A64 = 600, // WebAssemblyInstrFormats.td:59 |
| 616 | ATOMIC_RMW8_U_XCHG_I32_A64_S = 601, // WebAssemblyInstrFormats.td:61 |
| 617 | ATOMIC_RMW8_U_XCHG_I64_A32 = 602, // WebAssemblyInstrFormats.td:59 |
| 618 | ATOMIC_RMW8_U_XCHG_I64_A32_S = 603, // WebAssemblyInstrFormats.td:61 |
| 619 | ATOMIC_RMW8_U_XCHG_I64_A64 = 604, // WebAssemblyInstrFormats.td:59 |
| 620 | ATOMIC_RMW8_U_XCHG_I64_A64_S = 605, // WebAssemblyInstrFormats.td:61 |
| 621 | ATOMIC_RMW8_U_XOR_I32_A32 = 606, // WebAssemblyInstrFormats.td:59 |
| 622 | ATOMIC_RMW8_U_XOR_I32_A32_S = 607, // WebAssemblyInstrFormats.td:61 |
| 623 | ATOMIC_RMW8_U_XOR_I32_A64 = 608, // WebAssemblyInstrFormats.td:59 |
| 624 | ATOMIC_RMW8_U_XOR_I32_A64_S = 609, // WebAssemblyInstrFormats.td:61 |
| 625 | ATOMIC_RMW8_U_XOR_I64_A32 = 610, // WebAssemblyInstrFormats.td:59 |
| 626 | ATOMIC_RMW8_U_XOR_I64_A32_S = 611, // WebAssemblyInstrFormats.td:61 |
| 627 | ATOMIC_RMW8_U_XOR_I64_A64 = 612, // WebAssemblyInstrFormats.td:59 |
| 628 | ATOMIC_RMW8_U_XOR_I64_A64_S = 613, // WebAssemblyInstrFormats.td:61 |
| 629 | ATOMIC_RMW_ADD_I32_A32 = 614, // WebAssemblyInstrFormats.td:59 |
| 630 | ATOMIC_RMW_ADD_I32_A32_S = 615, // WebAssemblyInstrFormats.td:61 |
| 631 | ATOMIC_RMW_ADD_I32_A64 = 616, // WebAssemblyInstrFormats.td:59 |
| 632 | ATOMIC_RMW_ADD_I32_A64_S = 617, // WebAssemblyInstrFormats.td:61 |
| 633 | ATOMIC_RMW_ADD_I64_A32 = 618, // WebAssemblyInstrFormats.td:59 |
| 634 | ATOMIC_RMW_ADD_I64_A32_S = 619, // WebAssemblyInstrFormats.td:61 |
| 635 | ATOMIC_RMW_ADD_I64_A64 = 620, // WebAssemblyInstrFormats.td:59 |
| 636 | ATOMIC_RMW_ADD_I64_A64_S = 621, // WebAssemblyInstrFormats.td:61 |
| 637 | ATOMIC_RMW_AND_I32_A32 = 622, // WebAssemblyInstrFormats.td:59 |
| 638 | ATOMIC_RMW_AND_I32_A32_S = 623, // WebAssemblyInstrFormats.td:61 |
| 639 | ATOMIC_RMW_AND_I32_A64 = 624, // WebAssemblyInstrFormats.td:59 |
| 640 | ATOMIC_RMW_AND_I32_A64_S = 625, // WebAssemblyInstrFormats.td:61 |
| 641 | ATOMIC_RMW_AND_I64_A32 = 626, // WebAssemblyInstrFormats.td:59 |
| 642 | ATOMIC_RMW_AND_I64_A32_S = 627, // WebAssemblyInstrFormats.td:61 |
| 643 | ATOMIC_RMW_AND_I64_A64 = 628, // WebAssemblyInstrFormats.td:59 |
| 644 | ATOMIC_RMW_AND_I64_A64_S = 629, // WebAssemblyInstrFormats.td:61 |
| 645 | ATOMIC_RMW_CMPXCHG_I32_A32 = 630, // WebAssemblyInstrFormats.td:59 |
| 646 | ATOMIC_RMW_CMPXCHG_I32_A32_S = 631, // WebAssemblyInstrFormats.td:61 |
| 647 | ATOMIC_RMW_CMPXCHG_I32_A64 = 632, // WebAssemblyInstrFormats.td:59 |
| 648 | ATOMIC_RMW_CMPXCHG_I32_A64_S = 633, // WebAssemblyInstrFormats.td:61 |
| 649 | ATOMIC_RMW_CMPXCHG_I64_A32 = 634, // WebAssemblyInstrFormats.td:59 |
| 650 | ATOMIC_RMW_CMPXCHG_I64_A32_S = 635, // WebAssemblyInstrFormats.td:61 |
| 651 | ATOMIC_RMW_CMPXCHG_I64_A64 = 636, // WebAssemblyInstrFormats.td:59 |
| 652 | ATOMIC_RMW_CMPXCHG_I64_A64_S = 637, // WebAssemblyInstrFormats.td:61 |
| 653 | ATOMIC_RMW_OR_I32_A32 = 638, // WebAssemblyInstrFormats.td:59 |
| 654 | ATOMIC_RMW_OR_I32_A32_S = 639, // WebAssemblyInstrFormats.td:61 |
| 655 | ATOMIC_RMW_OR_I32_A64 = 640, // WebAssemblyInstrFormats.td:59 |
| 656 | ATOMIC_RMW_OR_I32_A64_S = 641, // WebAssemblyInstrFormats.td:61 |
| 657 | ATOMIC_RMW_OR_I64_A32 = 642, // WebAssemblyInstrFormats.td:59 |
| 658 | ATOMIC_RMW_OR_I64_A32_S = 643, // WebAssemblyInstrFormats.td:61 |
| 659 | ATOMIC_RMW_OR_I64_A64 = 644, // WebAssemblyInstrFormats.td:59 |
| 660 | ATOMIC_RMW_OR_I64_A64_S = 645, // WebAssemblyInstrFormats.td:61 |
| 661 | ATOMIC_RMW_SUB_I32_A32 = 646, // WebAssemblyInstrFormats.td:59 |
| 662 | ATOMIC_RMW_SUB_I32_A32_S = 647, // WebAssemblyInstrFormats.td:61 |
| 663 | ATOMIC_RMW_SUB_I32_A64 = 648, // WebAssemblyInstrFormats.td:59 |
| 664 | ATOMIC_RMW_SUB_I32_A64_S = 649, // WebAssemblyInstrFormats.td:61 |
| 665 | ATOMIC_RMW_SUB_I64_A32 = 650, // WebAssemblyInstrFormats.td:59 |
| 666 | ATOMIC_RMW_SUB_I64_A32_S = 651, // WebAssemblyInstrFormats.td:61 |
| 667 | ATOMIC_RMW_SUB_I64_A64 = 652, // WebAssemblyInstrFormats.td:59 |
| 668 | ATOMIC_RMW_SUB_I64_A64_S = 653, // WebAssemblyInstrFormats.td:61 |
| 669 | ATOMIC_RMW_XCHG_I32_A32 = 654, // WebAssemblyInstrFormats.td:59 |
| 670 | ATOMIC_RMW_XCHG_I32_A32_S = 655, // WebAssemblyInstrFormats.td:61 |
| 671 | ATOMIC_RMW_XCHG_I32_A64 = 656, // WebAssemblyInstrFormats.td:59 |
| 672 | ATOMIC_RMW_XCHG_I32_A64_S = 657, // WebAssemblyInstrFormats.td:61 |
| 673 | ATOMIC_RMW_XCHG_I64_A32 = 658, // WebAssemblyInstrFormats.td:59 |
| 674 | ATOMIC_RMW_XCHG_I64_A32_S = 659, // WebAssemblyInstrFormats.td:61 |
| 675 | ATOMIC_RMW_XCHG_I64_A64 = 660, // WebAssemblyInstrFormats.td:59 |
| 676 | ATOMIC_RMW_XCHG_I64_A64_S = 661, // WebAssemblyInstrFormats.td:61 |
| 677 | ATOMIC_RMW_XOR_I32_A32 = 662, // WebAssemblyInstrFormats.td:59 |
| 678 | ATOMIC_RMW_XOR_I32_A32_S = 663, // WebAssemblyInstrFormats.td:61 |
| 679 | ATOMIC_RMW_XOR_I32_A64 = 664, // WebAssemblyInstrFormats.td:59 |
| 680 | ATOMIC_RMW_XOR_I32_A64_S = 665, // WebAssemblyInstrFormats.td:61 |
| 681 | ATOMIC_RMW_XOR_I64_A32 = 666, // WebAssemblyInstrFormats.td:59 |
| 682 | ATOMIC_RMW_XOR_I64_A32_S = 667, // WebAssemblyInstrFormats.td:61 |
| 683 | ATOMIC_RMW_XOR_I64_A64 = 668, // WebAssemblyInstrFormats.td:59 |
| 684 | ATOMIC_RMW_XOR_I64_A64_S = 669, // WebAssemblyInstrFormats.td:61 |
| 685 | ATOMIC_STORE16_I32_A32 = 670, // WebAssemblyInstrFormats.td:59 |
| 686 | ATOMIC_STORE16_I32_A32_S = 671, // WebAssemblyInstrFormats.td:61 |
| 687 | ATOMIC_STORE16_I32_A64 = 672, // WebAssemblyInstrFormats.td:59 |
| 688 | ATOMIC_STORE16_I32_A64_S = 673, // WebAssemblyInstrFormats.td:61 |
| 689 | ATOMIC_STORE16_I64_A32 = 674, // WebAssemblyInstrFormats.td:59 |
| 690 | ATOMIC_STORE16_I64_A32_S = 675, // WebAssemblyInstrFormats.td:61 |
| 691 | ATOMIC_STORE16_I64_A64 = 676, // WebAssemblyInstrFormats.td:59 |
| 692 | ATOMIC_STORE16_I64_A64_S = 677, // WebAssemblyInstrFormats.td:61 |
| 693 | ATOMIC_STORE32_I64_A32 = 678, // WebAssemblyInstrFormats.td:59 |
| 694 | ATOMIC_STORE32_I64_A32_S = 679, // WebAssemblyInstrFormats.td:61 |
| 695 | ATOMIC_STORE32_I64_A64 = 680, // WebAssemblyInstrFormats.td:59 |
| 696 | ATOMIC_STORE32_I64_A64_S = 681, // WebAssemblyInstrFormats.td:61 |
| 697 | ATOMIC_STORE8_I32_A32 = 682, // WebAssemblyInstrFormats.td:59 |
| 698 | ATOMIC_STORE8_I32_A32_S = 683, // WebAssemblyInstrFormats.td:61 |
| 699 | ATOMIC_STORE8_I32_A64 = 684, // WebAssemblyInstrFormats.td:59 |
| 700 | ATOMIC_STORE8_I32_A64_S = 685, // WebAssemblyInstrFormats.td:61 |
| 701 | ATOMIC_STORE8_I64_A32 = 686, // WebAssemblyInstrFormats.td:59 |
| 702 | ATOMIC_STORE8_I64_A32_S = 687, // WebAssemblyInstrFormats.td:61 |
| 703 | ATOMIC_STORE8_I64_A64 = 688, // WebAssemblyInstrFormats.td:59 |
| 704 | ATOMIC_STORE8_I64_A64_S = 689, // WebAssemblyInstrFormats.td:61 |
| 705 | ATOMIC_STORE_I32_A32 = 690, // WebAssemblyInstrFormats.td:59 |
| 706 | ATOMIC_STORE_I32_A32_S = 691, // WebAssemblyInstrFormats.td:61 |
| 707 | ATOMIC_STORE_I32_A64 = 692, // WebAssemblyInstrFormats.td:59 |
| 708 | ATOMIC_STORE_I32_A64_S = 693, // WebAssemblyInstrFormats.td:61 |
| 709 | ATOMIC_STORE_I64_A32 = 694, // WebAssemblyInstrFormats.td:59 |
| 710 | ATOMIC_STORE_I64_A32_S = 695, // WebAssemblyInstrFormats.td:61 |
| 711 | ATOMIC_STORE_I64_A64 = 696, // WebAssemblyInstrFormats.td:59 |
| 712 | ATOMIC_STORE_I64_A64_S = 697, // WebAssemblyInstrFormats.td:61 |
| 713 | AVGR_U_I16x8 = 698, // WebAssemblyInstrFormats.td:59 |
| 714 | AVGR_U_I16x8_S = 699, // WebAssemblyInstrFormats.td:61 |
| 715 | AVGR_U_I8x16 = 700, // WebAssemblyInstrFormats.td:59 |
| 716 | AVGR_U_I8x16_S = 701, // WebAssemblyInstrFormats.td:61 |
| 717 | BITMASK_I16x8 = 702, // WebAssemblyInstrFormats.td:59 |
| 718 | BITMASK_I16x8_S = 703, // WebAssemblyInstrFormats.td:61 |
| 719 | BITMASK_I32x4 = 704, // WebAssemblyInstrFormats.td:59 |
| 720 | BITMASK_I32x4_S = 705, // WebAssemblyInstrFormats.td:61 |
| 721 | BITMASK_I64x2 = 706, // WebAssemblyInstrFormats.td:59 |
| 722 | BITMASK_I64x2_S = 707, // WebAssemblyInstrFormats.td:61 |
| 723 | BITMASK_I8x16 = 708, // WebAssemblyInstrFormats.td:59 |
| 724 | BITMASK_I8x16_S = 709, // WebAssemblyInstrFormats.td:61 |
| 725 | BITSELECT = 710, // WebAssemblyInstrFormats.td:59 |
| 726 | BITSELECT_S = 711, // WebAssemblyInstrFormats.td:61 |
| 727 | BLOCK = 712, // WebAssemblyInstrFormats.td:59 |
| 728 | BLOCK_S = 713, // WebAssemblyInstrFormats.td:61 |
| 729 | BR = 714, // WebAssemblyInstrFormats.td:59 |
| 730 | BR_IF = 715, // WebAssemblyInstrFormats.td:59 |
| 731 | BR_IF_S = 716, // WebAssemblyInstrFormats.td:61 |
| 732 | BR_S = 717, // WebAssemblyInstrFormats.td:61 |
| 733 | BR_TABLE_I32 = 718, // WebAssemblyInstrFormats.td:59 |
| 734 | BR_TABLE_I32_S = 719, // WebAssemblyInstrFormats.td:61 |
| 735 | BR_TABLE_I64 = 720, // WebAssemblyInstrFormats.td:59 |
| 736 | BR_TABLE_I64_S = 721, // WebAssemblyInstrFormats.td:61 |
| 737 | BR_UNLESS = 722, // WebAssemblyInstrFormats.td:59 |
| 738 | BR_UNLESS_S = 723, // WebAssemblyInstrFormats.td:61 |
| 739 | CALL = 724, // WebAssemblyInstrFormats.td:59 |
| 740 | CALL_INDIRECT = 725, // WebAssemblyInstrFormats.td:59 |
| 741 | CALL_INDIRECT_S = 726, // WebAssemblyInstrFormats.td:61 |
| 742 | CALL_REF = 727, // WebAssemblyInstrFormats.td:59 |
| 743 | CALL_REF_S = 728, // WebAssemblyInstrFormats.td:61 |
| 744 | CALL_S = 729, // WebAssemblyInstrFormats.td:61 |
| 745 | CATCH = 730, // WebAssemblyInstrFormats.td:59 |
| 746 | CATCH_ALL = 731, // WebAssemblyInstrFormats.td:59 |
| 747 | CATCH_ALL_LEGACY = 732, // WebAssemblyInstrFormats.td:59 |
| 748 | CATCH_ALL_LEGACY_S = 733, // WebAssemblyInstrFormats.td:61 |
| 749 | CATCH_ALL_REF = 734, // WebAssemblyInstrFormats.td:59 |
| 750 | CATCH_ALL_REF_S = 735, // WebAssemblyInstrFormats.td:61 |
| 751 | CATCH_ALL_S = 736, // WebAssemblyInstrFormats.td:61 |
| 752 | CATCH_LEGACY = 737, // WebAssemblyInstrFormats.td:59 |
| 753 | CATCH_LEGACY_S = 738, // WebAssemblyInstrFormats.td:61 |
| 754 | CATCH_REF = 739, // WebAssemblyInstrFormats.td:59 |
| 755 | CATCH_REF_S = 740, // WebAssemblyInstrFormats.td:61 |
| 756 | CATCH_S = 741, // WebAssemblyInstrFormats.td:61 |
| 757 | CEIL_F16x8 = 742, // WebAssemblyInstrFormats.td:59 |
| 758 | CEIL_F16x8_S = 743, // WebAssemblyInstrFormats.td:61 |
| 759 | CEIL_F32 = 744, // WebAssemblyInstrFormats.td:59 |
| 760 | CEIL_F32_S = 745, // WebAssemblyInstrFormats.td:61 |
| 761 | CEIL_F32x4 = 746, // WebAssemblyInstrFormats.td:59 |
| 762 | CEIL_F32x4_S = 747, // WebAssemblyInstrFormats.td:61 |
| 763 | CEIL_F64 = 748, // WebAssemblyInstrFormats.td:59 |
| 764 | CEIL_F64_S = 749, // WebAssemblyInstrFormats.td:61 |
| 765 | CEIL_F64x2 = 750, // WebAssemblyInstrFormats.td:59 |
| 766 | CEIL_F64x2_S = 751, // WebAssemblyInstrFormats.td:61 |
| 767 | CLZ_I32 = 752, // WebAssemblyInstrFormats.td:59 |
| 768 | CLZ_I32_S = 753, // WebAssemblyInstrFormats.td:61 |
| 769 | CLZ_I64 = 754, // WebAssemblyInstrFormats.td:59 |
| 770 | CLZ_I64_S = 755, // WebAssemblyInstrFormats.td:61 |
| 771 | CONST_F32 = 756, // WebAssemblyInstrFormats.td:59 |
| 772 | CONST_F32_S = 757, // WebAssemblyInstrFormats.td:61 |
| 773 | CONST_F64 = 758, // WebAssemblyInstrFormats.td:59 |
| 774 | CONST_F64_S = 759, // WebAssemblyInstrFormats.td:61 |
| 775 | CONST_I32 = 760, // WebAssemblyInstrFormats.td:59 |
| 776 | CONST_I32_S = 761, // WebAssemblyInstrFormats.td:61 |
| 777 | CONST_I64 = 762, // WebAssemblyInstrFormats.td:59 |
| 778 | CONST_I64_S = 763, // WebAssemblyInstrFormats.td:61 |
| 779 | CONST_V128_F32x4 = 764, // WebAssemblyInstrFormats.td:59 |
| 780 | CONST_V128_F32x4_S = 765, // WebAssemblyInstrFormats.td:61 |
| 781 | CONST_V128_F64x2 = 766, // WebAssemblyInstrFormats.td:59 |
| 782 | CONST_V128_F64x2_S = 767, // WebAssemblyInstrFormats.td:61 |
| 783 | CONST_V128_I16x8 = 768, // WebAssemblyInstrFormats.td:59 |
| 784 | CONST_V128_I16x8_S = 769, // WebAssemblyInstrFormats.td:61 |
| 785 | CONST_V128_I32x4 = 770, // WebAssemblyInstrFormats.td:59 |
| 786 | CONST_V128_I32x4_S = 771, // WebAssemblyInstrFormats.td:61 |
| 787 | CONST_V128_I64x2 = 772, // WebAssemblyInstrFormats.td:59 |
| 788 | CONST_V128_I64x2_S = 773, // WebAssemblyInstrFormats.td:61 |
| 789 | CONST_V128_I8x16 = 774, // WebAssemblyInstrFormats.td:59 |
| 790 | CONST_V128_I8x16_S = 775, // WebAssemblyInstrFormats.td:61 |
| 791 | COPYSIGN_F32 = 776, // WebAssemblyInstrFormats.td:59 |
| 792 | COPYSIGN_F32_S = 777, // WebAssemblyInstrFormats.td:61 |
| 793 | COPYSIGN_F64 = 778, // WebAssemblyInstrFormats.td:59 |
| 794 | COPYSIGN_F64_S = 779, // WebAssemblyInstrFormats.td:61 |
| 795 | COPY_EXNREF = 780, // WebAssemblyInstrFormats.td:59 |
| 796 | COPY_EXNREF_S = 781, // WebAssemblyInstrFormats.td:61 |
| 797 | COPY_EXTERNREF = 782, // WebAssemblyInstrFormats.td:59 |
| 798 | COPY_EXTERNREF_S = 783, // WebAssemblyInstrFormats.td:61 |
| 799 | COPY_F32 = 784, // WebAssemblyInstrFormats.td:59 |
| 800 | COPY_F32_S = 785, // WebAssemblyInstrFormats.td:61 |
| 801 | COPY_F64 = 786, // WebAssemblyInstrFormats.td:59 |
| 802 | COPY_F64_S = 787, // WebAssemblyInstrFormats.td:61 |
| 803 | COPY_FUNCREF = 788, // WebAssemblyInstrFormats.td:59 |
| 804 | COPY_FUNCREF_S = 789, // WebAssemblyInstrFormats.td:61 |
| 805 | COPY_I32 = 790, // WebAssemblyInstrFormats.td:59 |
| 806 | COPY_I32_S = 791, // WebAssemblyInstrFormats.td:61 |
| 807 | COPY_I64 = 792, // WebAssemblyInstrFormats.td:59 |
| 808 | COPY_I64_S = 793, // WebAssemblyInstrFormats.td:61 |
| 809 | COPY_V128 = 794, // WebAssemblyInstrFormats.td:59 |
| 810 | COPY_V128_S = 795, // WebAssemblyInstrFormats.td:61 |
| 811 | CTZ_I32 = 796, // WebAssemblyInstrFormats.td:59 |
| 812 | CTZ_I32_S = 797, // WebAssemblyInstrFormats.td:61 |
| 813 | CTZ_I64 = 798, // WebAssemblyInstrFormats.td:59 |
| 814 | CTZ_I64_S = 799, // WebAssemblyInstrFormats.td:61 |
| 815 | DATA_DROP = 800, // WebAssemblyInstrFormats.td:59 |
| 816 | DATA_DROP_S = 801, // WebAssemblyInstrFormats.td:61 |
| 817 | DEBUG_UNREACHABLE = 802, // WebAssemblyInstrFormats.td:59 |
| 818 | DEBUG_UNREACHABLE_S = 803, // WebAssemblyInstrFormats.td:61 |
| 819 | DELEGATE = 804, // WebAssemblyInstrFormats.td:59 |
| 820 | DELEGATE_S = 805, // WebAssemblyInstrFormats.td:61 |
| 821 | DIV_F16x8 = 806, // WebAssemblyInstrFormats.td:59 |
| 822 | DIV_F16x8_S = 807, // WebAssemblyInstrFormats.td:61 |
| 823 | DIV_F32 = 808, // WebAssemblyInstrFormats.td:59 |
| 824 | DIV_F32_S = 809, // WebAssemblyInstrFormats.td:61 |
| 825 | DIV_F32x4 = 810, // WebAssemblyInstrFormats.td:59 |
| 826 | DIV_F32x4_S = 811, // WebAssemblyInstrFormats.td:61 |
| 827 | DIV_F64 = 812, // WebAssemblyInstrFormats.td:59 |
| 828 | DIV_F64_S = 813, // WebAssemblyInstrFormats.td:61 |
| 829 | DIV_F64x2 = 814, // WebAssemblyInstrFormats.td:59 |
| 830 | DIV_F64x2_S = 815, // WebAssemblyInstrFormats.td:61 |
| 831 | DIV_S_I32 = 816, // WebAssemblyInstrFormats.td:59 |
| 832 | DIV_S_I32_S = 817, // WebAssemblyInstrFormats.td:61 |
| 833 | DIV_S_I64 = 818, // WebAssemblyInstrFormats.td:59 |
| 834 | DIV_S_I64_S = 819, // WebAssemblyInstrFormats.td:61 |
| 835 | DIV_U_I32 = 820, // WebAssemblyInstrFormats.td:59 |
| 836 | DIV_U_I32_S = 821, // WebAssemblyInstrFormats.td:61 |
| 837 | DIV_U_I64 = 822, // WebAssemblyInstrFormats.td:59 |
| 838 | DIV_U_I64_S = 823, // WebAssemblyInstrFormats.td:61 |
| 839 | DOT = 824, // WebAssemblyInstrFormats.td:59 |
| 840 | DOT_S = 825, // WebAssemblyInstrFormats.td:61 |
| 841 | DROP_EXNREF = 826, // WebAssemblyInstrFormats.td:59 |
| 842 | DROP_EXNREF_S = 827, // WebAssemblyInstrFormats.td:61 |
| 843 | DROP_EXTERNREF = 828, // WebAssemblyInstrFormats.td:59 |
| 844 | DROP_EXTERNREF_S = 829, // WebAssemblyInstrFormats.td:61 |
| 845 | DROP_F32 = 830, // WebAssemblyInstrFormats.td:59 |
| 846 | DROP_F32_S = 831, // WebAssemblyInstrFormats.td:61 |
| 847 | DROP_F64 = 832, // WebAssemblyInstrFormats.td:59 |
| 848 | DROP_F64_S = 833, // WebAssemblyInstrFormats.td:61 |
| 849 | DROP_FUNCREF = 834, // WebAssemblyInstrFormats.td:59 |
| 850 | DROP_FUNCREF_S = 835, // WebAssemblyInstrFormats.td:61 |
| 851 | DROP_I32 = 836, // WebAssemblyInstrFormats.td:59 |
| 852 | DROP_I32_S = 837, // WebAssemblyInstrFormats.td:61 |
| 853 | DROP_I64 = 838, // WebAssemblyInstrFormats.td:59 |
| 854 | DROP_I64_S = 839, // WebAssemblyInstrFormats.td:61 |
| 855 | DROP_V128 = 840, // WebAssemblyInstrFormats.td:59 |
| 856 | DROP_V128_S = 841, // WebAssemblyInstrFormats.td:61 |
| 857 | ELSE = 842, // WebAssemblyInstrFormats.td:59 |
| 858 | ELSE_S = 843, // WebAssemblyInstrFormats.td:61 |
| 859 | END = 844, // WebAssemblyInstrFormats.td:59 |
| 860 | END_BLOCK = 845, // WebAssemblyInstrFormats.td:59 |
| 861 | END_BLOCK_S = 846, // WebAssemblyInstrFormats.td:61 |
| 862 | END_FUNCTION = 847, // WebAssemblyInstrFormats.td:59 |
| 863 | END_FUNCTION_S = 848, // WebAssemblyInstrFormats.td:61 |
| 864 | END_IF = 849, // WebAssemblyInstrFormats.td:59 |
| 865 | END_IF_S = 850, // WebAssemblyInstrFormats.td:61 |
| 866 | END_LOOP = 851, // WebAssemblyInstrFormats.td:59 |
| 867 | END_LOOP_S = 852, // WebAssemblyInstrFormats.td:61 |
| 868 | END_S = 853, // WebAssemblyInstrFormats.td:61 |
| 869 | END_TRY = 854, // WebAssemblyInstrFormats.td:59 |
| 870 | END_TRY_S = 855, // WebAssemblyInstrFormats.td:61 |
| 871 | END_TRY_TABLE = 856, // WebAssemblyInstrFormats.td:59 |
| 872 | END_TRY_TABLE_S = 857, // WebAssemblyInstrFormats.td:61 |
| 873 | EQZ_I32 = 858, // WebAssemblyInstrFormats.td:59 |
| 874 | EQZ_I32_S = 859, // WebAssemblyInstrFormats.td:61 |
| 875 | EQZ_I64 = 860, // WebAssemblyInstrFormats.td:59 |
| 876 | EQZ_I64_S = 861, // WebAssemblyInstrFormats.td:61 |
| 877 | EQ_F16x8 = 862, // WebAssemblyInstrFormats.td:59 |
| 878 | EQ_F16x8_S = 863, // WebAssemblyInstrFormats.td:61 |
| 879 | EQ_F32 = 864, // WebAssemblyInstrFormats.td:59 |
| 880 | EQ_F32_S = 865, // WebAssemblyInstrFormats.td:61 |
| 881 | EQ_F32x4 = 866, // WebAssemblyInstrFormats.td:59 |
| 882 | EQ_F32x4_S = 867, // WebAssemblyInstrFormats.td:61 |
| 883 | EQ_F64 = 868, // WebAssemblyInstrFormats.td:59 |
| 884 | EQ_F64_S = 869, // WebAssemblyInstrFormats.td:61 |
| 885 | EQ_F64x2 = 870, // WebAssemblyInstrFormats.td:59 |
| 886 | EQ_F64x2_S = 871, // WebAssemblyInstrFormats.td:61 |
| 887 | EQ_I16x8 = 872, // WebAssemblyInstrFormats.td:59 |
| 888 | EQ_I16x8_S = 873, // WebAssemblyInstrFormats.td:61 |
| 889 | EQ_I32 = 874, // WebAssemblyInstrFormats.td:59 |
| 890 | EQ_I32_S = 875, // WebAssemblyInstrFormats.td:61 |
| 891 | EQ_I32x4 = 876, // WebAssemblyInstrFormats.td:59 |
| 892 | EQ_I32x4_S = 877, // WebAssemblyInstrFormats.td:61 |
| 893 | EQ_I64 = 878, // WebAssemblyInstrFormats.td:59 |
| 894 | EQ_I64_S = 879, // WebAssemblyInstrFormats.td:61 |
| 895 | EQ_I64x2 = 880, // WebAssemblyInstrFormats.td:59 |
| 896 | EQ_I64x2_S = 881, // WebAssemblyInstrFormats.td:61 |
| 897 | EQ_I8x16 = 882, // WebAssemblyInstrFormats.td:59 |
| 898 | EQ_I8x16_S = 883, // WebAssemblyInstrFormats.td:61 |
| 899 | EXTMUL_HIGH_S_I16x8 = 884, // WebAssemblyInstrFormats.td:59 |
| 900 | EXTMUL_HIGH_S_I16x8_S = 885, // WebAssemblyInstrFormats.td:61 |
| 901 | EXTMUL_HIGH_S_I32x4 = 886, // WebAssemblyInstrFormats.td:59 |
| 902 | EXTMUL_HIGH_S_I32x4_S = 887, // WebAssemblyInstrFormats.td:61 |
| 903 | EXTMUL_HIGH_S_I64x2 = 888, // WebAssemblyInstrFormats.td:59 |
| 904 | EXTMUL_HIGH_S_I64x2_S = 889, // WebAssemblyInstrFormats.td:61 |
| 905 | EXTMUL_HIGH_U_I16x8 = 890, // WebAssemblyInstrFormats.td:59 |
| 906 | EXTMUL_HIGH_U_I16x8_S = 891, // WebAssemblyInstrFormats.td:61 |
| 907 | EXTMUL_HIGH_U_I32x4 = 892, // WebAssemblyInstrFormats.td:59 |
| 908 | EXTMUL_HIGH_U_I32x4_S = 893, // WebAssemblyInstrFormats.td:61 |
| 909 | EXTMUL_HIGH_U_I64x2 = 894, // WebAssemblyInstrFormats.td:59 |
| 910 | EXTMUL_HIGH_U_I64x2_S = 895, // WebAssemblyInstrFormats.td:61 |
| 911 | EXTMUL_LOW_S_I16x8 = 896, // WebAssemblyInstrFormats.td:59 |
| 912 | EXTMUL_LOW_S_I16x8_S = 897, // WebAssemblyInstrFormats.td:61 |
| 913 | EXTMUL_LOW_S_I32x4 = 898, // WebAssemblyInstrFormats.td:59 |
| 914 | EXTMUL_LOW_S_I32x4_S = 899, // WebAssemblyInstrFormats.td:61 |
| 915 | EXTMUL_LOW_S_I64x2 = 900, // WebAssemblyInstrFormats.td:59 |
| 916 | EXTMUL_LOW_S_I64x2_S = 901, // WebAssemblyInstrFormats.td:61 |
| 917 | EXTMUL_LOW_U_I16x8 = 902, // WebAssemblyInstrFormats.td:59 |
| 918 | EXTMUL_LOW_U_I16x8_S = 903, // WebAssemblyInstrFormats.td:61 |
| 919 | EXTMUL_LOW_U_I32x4 = 904, // WebAssemblyInstrFormats.td:59 |
| 920 | EXTMUL_LOW_U_I32x4_S = 905, // WebAssemblyInstrFormats.td:61 |
| 921 | EXTMUL_LOW_U_I64x2 = 906, // WebAssemblyInstrFormats.td:59 |
| 922 | EXTMUL_LOW_U_I64x2_S = 907, // WebAssemblyInstrFormats.td:61 |
| 923 | EXTRACT_LANE_F16x8 = 908, // WebAssemblyInstrFormats.td:59 |
| 924 | EXTRACT_LANE_F16x8_S = 909, // WebAssemblyInstrFormats.td:61 |
| 925 | EXTRACT_LANE_F32x4 = 910, // WebAssemblyInstrFormats.td:59 |
| 926 | EXTRACT_LANE_F32x4_S = 911, // WebAssemblyInstrFormats.td:61 |
| 927 | EXTRACT_LANE_F64x2 = 912, // WebAssemblyInstrFormats.td:59 |
| 928 | EXTRACT_LANE_F64x2_S = 913, // WebAssemblyInstrFormats.td:61 |
| 929 | EXTRACT_LANE_I16x8_s = 914, // WebAssemblyInstrFormats.td:59 |
| 930 | EXTRACT_LANE_I16x8_s_S = 915, // WebAssemblyInstrFormats.td:61 |
| 931 | EXTRACT_LANE_I16x8_u = 916, // WebAssemblyInstrFormats.td:59 |
| 932 | EXTRACT_LANE_I16x8_u_S = 917, // WebAssemblyInstrFormats.td:61 |
| 933 | EXTRACT_LANE_I32x4 = 918, // WebAssemblyInstrFormats.td:59 |
| 934 | EXTRACT_LANE_I32x4_S = 919, // WebAssemblyInstrFormats.td:61 |
| 935 | EXTRACT_LANE_I64x2 = 920, // WebAssemblyInstrFormats.td:59 |
| 936 | EXTRACT_LANE_I64x2_S = 921, // WebAssemblyInstrFormats.td:61 |
| 937 | EXTRACT_LANE_I8x16_s = 922, // WebAssemblyInstrFormats.td:59 |
| 938 | EXTRACT_LANE_I8x16_s_S = 923, // WebAssemblyInstrFormats.td:61 |
| 939 | EXTRACT_LANE_I8x16_u = 924, // WebAssemblyInstrFormats.td:59 |
| 940 | EXTRACT_LANE_I8x16_u_S = 925, // WebAssemblyInstrFormats.td:61 |
| 941 | F32_CONVERT_S_I32 = 926, // WebAssemblyInstrFormats.td:59 |
| 942 | F32_CONVERT_S_I32_S = 927, // WebAssemblyInstrFormats.td:61 |
| 943 | F32_CONVERT_S_I64 = 928, // WebAssemblyInstrFormats.td:59 |
| 944 | F32_CONVERT_S_I64_S = 929, // WebAssemblyInstrFormats.td:61 |
| 945 | F32_CONVERT_U_I32 = 930, // WebAssemblyInstrFormats.td:59 |
| 946 | F32_CONVERT_U_I32_S = 931, // WebAssemblyInstrFormats.td:61 |
| 947 | F32_CONVERT_U_I64 = 932, // WebAssemblyInstrFormats.td:59 |
| 948 | F32_CONVERT_U_I64_S = 933, // WebAssemblyInstrFormats.td:61 |
| 949 | F32_DEMOTE_F64 = 934, // WebAssemblyInstrFormats.td:59 |
| 950 | F32_DEMOTE_F64_S = 935, // WebAssemblyInstrFormats.td:61 |
| 951 | F32_REINTERPRET_I32 = 936, // WebAssemblyInstrFormats.td:59 |
| 952 | F32_REINTERPRET_I32_S = 937, // WebAssemblyInstrFormats.td:61 |
| 953 | F64_CONVERT_S_I32 = 938, // WebAssemblyInstrFormats.td:59 |
| 954 | F64_CONVERT_S_I32_S = 939, // WebAssemblyInstrFormats.td:61 |
| 955 | F64_CONVERT_S_I64 = 940, // WebAssemblyInstrFormats.td:59 |
| 956 | F64_CONVERT_S_I64_S = 941, // WebAssemblyInstrFormats.td:61 |
| 957 | F64_CONVERT_U_I32 = 942, // WebAssemblyInstrFormats.td:59 |
| 958 | F64_CONVERT_U_I32_S = 943, // WebAssemblyInstrFormats.td:61 |
| 959 | F64_CONVERT_U_I64 = 944, // WebAssemblyInstrFormats.td:59 |
| 960 | F64_CONVERT_U_I64_S = 945, // WebAssemblyInstrFormats.td:61 |
| 961 | F64_PROMOTE_F32 = 946, // WebAssemblyInstrFormats.td:59 |
| 962 | F64_PROMOTE_F32_S = 947, // WebAssemblyInstrFormats.td:61 |
| 963 | F64_REINTERPRET_I64 = 948, // WebAssemblyInstrFormats.td:59 |
| 964 | F64_REINTERPRET_I64_S = 949, // WebAssemblyInstrFormats.td:61 |
| 965 | FALLTHROUGH_RETURN = 950, // WebAssemblyInstrFormats.td:59 |
| 966 | FALLTHROUGH_RETURN_S = 951, // WebAssemblyInstrFormats.td:61 |
| 967 | FLOOR_F16x8 = 952, // WebAssemblyInstrFormats.td:59 |
| 968 | FLOOR_F16x8_S = 953, // WebAssemblyInstrFormats.td:61 |
| 969 | FLOOR_F32 = 954, // WebAssemblyInstrFormats.td:59 |
| 970 | FLOOR_F32_S = 955, // WebAssemblyInstrFormats.td:61 |
| 971 | FLOOR_F32x4 = 956, // WebAssemblyInstrFormats.td:59 |
| 972 | FLOOR_F32x4_S = 957, // WebAssemblyInstrFormats.td:61 |
| 973 | FLOOR_F64 = 958, // WebAssemblyInstrFormats.td:59 |
| 974 | FLOOR_F64_S = 959, // WebAssemblyInstrFormats.td:61 |
| 975 | FLOOR_F64x2 = 960, // WebAssemblyInstrFormats.td:59 |
| 976 | FLOOR_F64x2_S = 961, // WebAssemblyInstrFormats.td:61 |
| 977 | FP_TO_SINT_I32_F32 = 962, // WebAssemblyInstrFormats.td:59 |
| 978 | FP_TO_SINT_I32_F32_S = 963, // WebAssemblyInstrFormats.td:61 |
| 979 | FP_TO_SINT_I32_F64 = 964, // WebAssemblyInstrFormats.td:59 |
| 980 | FP_TO_SINT_I32_F64_S = 965, // WebAssemblyInstrFormats.td:61 |
| 981 | FP_TO_SINT_I64_F32 = 966, // WebAssemblyInstrFormats.td:59 |
| 982 | FP_TO_SINT_I64_F32_S = 967, // WebAssemblyInstrFormats.td:61 |
| 983 | FP_TO_SINT_I64_F64 = 968, // WebAssemblyInstrFormats.td:59 |
| 984 | FP_TO_SINT_I64_F64_S = 969, // WebAssemblyInstrFormats.td:61 |
| 985 | FP_TO_UINT_I32_F32 = 970, // WebAssemblyInstrFormats.td:59 |
| 986 | FP_TO_UINT_I32_F32_S = 971, // WebAssemblyInstrFormats.td:61 |
| 987 | FP_TO_UINT_I32_F64 = 972, // WebAssemblyInstrFormats.td:59 |
| 988 | FP_TO_UINT_I32_F64_S = 973, // WebAssemblyInstrFormats.td:61 |
| 989 | FP_TO_UINT_I64_F32 = 974, // WebAssemblyInstrFormats.td:59 |
| 990 | FP_TO_UINT_I64_F32_S = 975, // WebAssemblyInstrFormats.td:61 |
| 991 | FP_TO_UINT_I64_F64 = 976, // WebAssemblyInstrFormats.td:59 |
| 992 | FP_TO_UINT_I64_F64_S = 977, // WebAssemblyInstrFormats.td:61 |
| 993 | GE_F16x8 = 978, // WebAssemblyInstrFormats.td:59 |
| 994 | GE_F16x8_S = 979, // WebAssemblyInstrFormats.td:61 |
| 995 | GE_F32 = 980, // WebAssemblyInstrFormats.td:59 |
| 996 | GE_F32_S = 981, // WebAssemblyInstrFormats.td:61 |
| 997 | GE_F32x4 = 982, // WebAssemblyInstrFormats.td:59 |
| 998 | GE_F32x4_S = 983, // WebAssemblyInstrFormats.td:61 |
| 999 | GE_F64 = 984, // WebAssemblyInstrFormats.td:59 |
| 1000 | GE_F64_S = 985, // WebAssemblyInstrFormats.td:61 |
| 1001 | GE_F64x2 = 986, // WebAssemblyInstrFormats.td:59 |
| 1002 | GE_F64x2_S = 987, // WebAssemblyInstrFormats.td:61 |
| 1003 | GE_S_I16x8 = 988, // WebAssemblyInstrFormats.td:59 |
| 1004 | GE_S_I16x8_S = 989, // WebAssemblyInstrFormats.td:61 |
| 1005 | GE_S_I32 = 990, // WebAssemblyInstrFormats.td:59 |
| 1006 | GE_S_I32_S = 991, // WebAssemblyInstrFormats.td:61 |
| 1007 | GE_S_I32x4 = 992, // WebAssemblyInstrFormats.td:59 |
| 1008 | GE_S_I32x4_S = 993, // WebAssemblyInstrFormats.td:61 |
| 1009 | GE_S_I64 = 994, // WebAssemblyInstrFormats.td:59 |
| 1010 | GE_S_I64_S = 995, // WebAssemblyInstrFormats.td:61 |
| 1011 | GE_S_I64x2 = 996, // WebAssemblyInstrFormats.td:59 |
| 1012 | GE_S_I64x2_S = 997, // WebAssemblyInstrFormats.td:61 |
| 1013 | GE_S_I8x16 = 998, // WebAssemblyInstrFormats.td:59 |
| 1014 | GE_S_I8x16_S = 999, // WebAssemblyInstrFormats.td:61 |
| 1015 | GE_U_I16x8 = 1000, // WebAssemblyInstrFormats.td:59 |
| 1016 | GE_U_I16x8_S = 1001, // WebAssemblyInstrFormats.td:61 |
| 1017 | GE_U_I32 = 1002, // WebAssemblyInstrFormats.td:59 |
| 1018 | GE_U_I32_S = 1003, // WebAssemblyInstrFormats.td:61 |
| 1019 | GE_U_I32x4 = 1004, // WebAssemblyInstrFormats.td:59 |
| 1020 | GE_U_I32x4_S = 1005, // WebAssemblyInstrFormats.td:61 |
| 1021 | GE_U_I64 = 1006, // WebAssemblyInstrFormats.td:59 |
| 1022 | GE_U_I64_S = 1007, // WebAssemblyInstrFormats.td:61 |
| 1023 | GE_U_I8x16 = 1008, // WebAssemblyInstrFormats.td:59 |
| 1024 | GE_U_I8x16_S = 1009, // WebAssemblyInstrFormats.td:61 |
| 1025 | GLOBAL_GET_EXNREF = 1010, // WebAssemblyInstrFormats.td:59 |
| 1026 | GLOBAL_GET_EXNREF_S = 1011, // WebAssemblyInstrFormats.td:61 |
| 1027 | GLOBAL_GET_EXTERNREF = 1012, // WebAssemblyInstrFormats.td:59 |
| 1028 | GLOBAL_GET_EXTERNREF_S = 1013, // WebAssemblyInstrFormats.td:61 |
| 1029 | GLOBAL_GET_F32 = 1014, // WebAssemblyInstrFormats.td:59 |
| 1030 | GLOBAL_GET_F32_S = 1015, // WebAssemblyInstrFormats.td:61 |
| 1031 | GLOBAL_GET_F64 = 1016, // WebAssemblyInstrFormats.td:59 |
| 1032 | GLOBAL_GET_F64_S = 1017, // WebAssemblyInstrFormats.td:61 |
| 1033 | GLOBAL_GET_FUNCREF = 1018, // WebAssemblyInstrFormats.td:59 |
| 1034 | GLOBAL_GET_FUNCREF_S = 1019, // WebAssemblyInstrFormats.td:61 |
| 1035 | GLOBAL_GET_I32 = 1020, // WebAssemblyInstrFormats.td:59 |
| 1036 | GLOBAL_GET_I32_S = 1021, // WebAssemblyInstrFormats.td:61 |
| 1037 | GLOBAL_GET_I64 = 1022, // WebAssemblyInstrFormats.td:59 |
| 1038 | GLOBAL_GET_I64_S = 1023, // WebAssemblyInstrFormats.td:61 |
| 1039 | GLOBAL_GET_V128 = 1024, // WebAssemblyInstrFormats.td:59 |
| 1040 | GLOBAL_GET_V128_S = 1025, // WebAssemblyInstrFormats.td:61 |
| 1041 | GLOBAL_SET_EXNREF = 1026, // WebAssemblyInstrFormats.td:59 |
| 1042 | GLOBAL_SET_EXNREF_S = 1027, // WebAssemblyInstrFormats.td:61 |
| 1043 | GLOBAL_SET_EXTERNREF = 1028, // WebAssemblyInstrFormats.td:59 |
| 1044 | GLOBAL_SET_EXTERNREF_S = 1029, // WebAssemblyInstrFormats.td:61 |
| 1045 | GLOBAL_SET_F32 = 1030, // WebAssemblyInstrFormats.td:59 |
| 1046 | GLOBAL_SET_F32_S = 1031, // WebAssemblyInstrFormats.td:61 |
| 1047 | GLOBAL_SET_F64 = 1032, // WebAssemblyInstrFormats.td:59 |
| 1048 | GLOBAL_SET_F64_S = 1033, // WebAssemblyInstrFormats.td:61 |
| 1049 | GLOBAL_SET_FUNCREF = 1034, // WebAssemblyInstrFormats.td:59 |
| 1050 | GLOBAL_SET_FUNCREF_S = 1035, // WebAssemblyInstrFormats.td:61 |
| 1051 | GLOBAL_SET_I32 = 1036, // WebAssemblyInstrFormats.td:59 |
| 1052 | GLOBAL_SET_I32_S = 1037, // WebAssemblyInstrFormats.td:61 |
| 1053 | GLOBAL_SET_I64 = 1038, // WebAssemblyInstrFormats.td:59 |
| 1054 | GLOBAL_SET_I64_S = 1039, // WebAssemblyInstrFormats.td:61 |
| 1055 | GLOBAL_SET_V128 = 1040, // WebAssemblyInstrFormats.td:59 |
| 1056 | GLOBAL_SET_V128_S = 1041, // WebAssemblyInstrFormats.td:61 |
| 1057 | GT_F16x8 = 1042, // WebAssemblyInstrFormats.td:59 |
| 1058 | GT_F16x8_S = 1043, // WebAssemblyInstrFormats.td:61 |
| 1059 | GT_F32 = 1044, // WebAssemblyInstrFormats.td:59 |
| 1060 | GT_F32_S = 1045, // WebAssemblyInstrFormats.td:61 |
| 1061 | GT_F32x4 = 1046, // WebAssemblyInstrFormats.td:59 |
| 1062 | GT_F32x4_S = 1047, // WebAssemblyInstrFormats.td:61 |
| 1063 | GT_F64 = 1048, // WebAssemblyInstrFormats.td:59 |
| 1064 | GT_F64_S = 1049, // WebAssemblyInstrFormats.td:61 |
| 1065 | GT_F64x2 = 1050, // WebAssemblyInstrFormats.td:59 |
| 1066 | GT_F64x2_S = 1051, // WebAssemblyInstrFormats.td:61 |
| 1067 | GT_S_I16x8 = 1052, // WebAssemblyInstrFormats.td:59 |
| 1068 | GT_S_I16x8_S = 1053, // WebAssemblyInstrFormats.td:61 |
| 1069 | GT_S_I32 = 1054, // WebAssemblyInstrFormats.td:59 |
| 1070 | GT_S_I32_S = 1055, // WebAssemblyInstrFormats.td:61 |
| 1071 | GT_S_I32x4 = 1056, // WebAssemblyInstrFormats.td:59 |
| 1072 | GT_S_I32x4_S = 1057, // WebAssemblyInstrFormats.td:61 |
| 1073 | GT_S_I64 = 1058, // WebAssemblyInstrFormats.td:59 |
| 1074 | GT_S_I64_S = 1059, // WebAssemblyInstrFormats.td:61 |
| 1075 | GT_S_I64x2 = 1060, // WebAssemblyInstrFormats.td:59 |
| 1076 | GT_S_I64x2_S = 1061, // WebAssemblyInstrFormats.td:61 |
| 1077 | GT_S_I8x16 = 1062, // WebAssemblyInstrFormats.td:59 |
| 1078 | GT_S_I8x16_S = 1063, // WebAssemblyInstrFormats.td:61 |
| 1079 | GT_U_I16x8 = 1064, // WebAssemblyInstrFormats.td:59 |
| 1080 | GT_U_I16x8_S = 1065, // WebAssemblyInstrFormats.td:61 |
| 1081 | GT_U_I32 = 1066, // WebAssemblyInstrFormats.td:59 |
| 1082 | GT_U_I32_S = 1067, // WebAssemblyInstrFormats.td:61 |
| 1083 | GT_U_I32x4 = 1068, // WebAssemblyInstrFormats.td:59 |
| 1084 | GT_U_I32x4_S = 1069, // WebAssemblyInstrFormats.td:61 |
| 1085 | GT_U_I64 = 1070, // WebAssemblyInstrFormats.td:59 |
| 1086 | GT_U_I64_S = 1071, // WebAssemblyInstrFormats.td:61 |
| 1087 | GT_U_I8x16 = 1072, // WebAssemblyInstrFormats.td:59 |
| 1088 | GT_U_I8x16_S = 1073, // WebAssemblyInstrFormats.td:61 |
| 1089 | I32_EXTEND16_S_I32 = 1074, // WebAssemblyInstrFormats.td:59 |
| 1090 | I32_EXTEND16_S_I32_S = 1075, // WebAssemblyInstrFormats.td:61 |
| 1091 | I32_EXTEND8_S_I32 = 1076, // WebAssemblyInstrFormats.td:59 |
| 1092 | I32_EXTEND8_S_I32_S = 1077, // WebAssemblyInstrFormats.td:61 |
| 1093 | I32_REINTERPRET_F32 = 1078, // WebAssemblyInstrFormats.td:59 |
| 1094 | I32_REINTERPRET_F32_S = 1079, // WebAssemblyInstrFormats.td:61 |
| 1095 | I32_TRUNC_S_F32 = 1080, // WebAssemblyInstrFormats.td:59 |
| 1096 | I32_TRUNC_S_F32_S = 1081, // WebAssemblyInstrFormats.td:61 |
| 1097 | I32_TRUNC_S_F64 = 1082, // WebAssemblyInstrFormats.td:59 |
| 1098 | I32_TRUNC_S_F64_S = 1083, // WebAssemblyInstrFormats.td:61 |
| 1099 | I32_TRUNC_S_SAT_F32 = 1084, // WebAssemblyInstrFormats.td:59 |
| 1100 | I32_TRUNC_S_SAT_F32_S = 1085, // WebAssemblyInstrFormats.td:61 |
| 1101 | I32_TRUNC_S_SAT_F64 = 1086, // WebAssemblyInstrFormats.td:59 |
| 1102 | I32_TRUNC_S_SAT_F64_S = 1087, // WebAssemblyInstrFormats.td:61 |
| 1103 | I32_TRUNC_U_F32 = 1088, // WebAssemblyInstrFormats.td:59 |
| 1104 | I32_TRUNC_U_F32_S = 1089, // WebAssemblyInstrFormats.td:61 |
| 1105 | I32_TRUNC_U_F64 = 1090, // WebAssemblyInstrFormats.td:59 |
| 1106 | I32_TRUNC_U_F64_S = 1091, // WebAssemblyInstrFormats.td:61 |
| 1107 | I32_TRUNC_U_SAT_F32 = 1092, // WebAssemblyInstrFormats.td:59 |
| 1108 | I32_TRUNC_U_SAT_F32_S = 1093, // WebAssemblyInstrFormats.td:61 |
| 1109 | I32_TRUNC_U_SAT_F64 = 1094, // WebAssemblyInstrFormats.td:59 |
| 1110 | I32_TRUNC_U_SAT_F64_S = 1095, // WebAssemblyInstrFormats.td:61 |
| 1111 | I32_WRAP_I64 = 1096, // WebAssemblyInstrFormats.td:59 |
| 1112 | I32_WRAP_I64_S = 1097, // WebAssemblyInstrFormats.td:61 |
| 1113 | I64_ADD128 = 1098, // WebAssemblyInstrFormats.td:59 |
| 1114 | I64_ADD128_S = 1099, // WebAssemblyInstrFormats.td:61 |
| 1115 | I64_EXTEND16_S_I64 = 1100, // WebAssemblyInstrFormats.td:59 |
| 1116 | I64_EXTEND16_S_I64_S = 1101, // WebAssemblyInstrFormats.td:61 |
| 1117 | I64_EXTEND32_S_I64 = 1102, // WebAssemblyInstrFormats.td:59 |
| 1118 | I64_EXTEND32_S_I64_S = 1103, // WebAssemblyInstrFormats.td:61 |
| 1119 | I64_EXTEND8_S_I64 = 1104, // WebAssemblyInstrFormats.td:59 |
| 1120 | I64_EXTEND8_S_I64_S = 1105, // WebAssemblyInstrFormats.td:61 |
| 1121 | I64_EXTEND_S_I32 = 1106, // WebAssemblyInstrFormats.td:59 |
| 1122 | I64_EXTEND_S_I32_S = 1107, // WebAssemblyInstrFormats.td:61 |
| 1123 | I64_EXTEND_U_I32 = 1108, // WebAssemblyInstrFormats.td:59 |
| 1124 | I64_EXTEND_U_I32_S = 1109, // WebAssemblyInstrFormats.td:61 |
| 1125 | I64_MUL_WIDE_S = 1110, // WebAssemblyInstrFormats.td:59 |
| 1126 | I64_MUL_WIDE_S_S = 1111, // WebAssemblyInstrFormats.td:61 |
| 1127 | I64_MUL_WIDE_U = 1112, // WebAssemblyInstrFormats.td:59 |
| 1128 | I64_MUL_WIDE_U_S = 1113, // WebAssemblyInstrFormats.td:61 |
| 1129 | I64_REINTERPRET_F64 = 1114, // WebAssemblyInstrFormats.td:59 |
| 1130 | I64_REINTERPRET_F64_S = 1115, // WebAssemblyInstrFormats.td:61 |
| 1131 | I64_SUB128 = 1116, // WebAssemblyInstrFormats.td:59 |
| 1132 | I64_SUB128_S = 1117, // WebAssemblyInstrFormats.td:61 |
| 1133 | I64_TRUNC_S_F32 = 1118, // WebAssemblyInstrFormats.td:59 |
| 1134 | I64_TRUNC_S_F32_S = 1119, // WebAssemblyInstrFormats.td:61 |
| 1135 | I64_TRUNC_S_F64 = 1120, // WebAssemblyInstrFormats.td:59 |
| 1136 | I64_TRUNC_S_F64_S = 1121, // WebAssemblyInstrFormats.td:61 |
| 1137 | I64_TRUNC_S_SAT_F32 = 1122, // WebAssemblyInstrFormats.td:59 |
| 1138 | I64_TRUNC_S_SAT_F32_S = 1123, // WebAssemblyInstrFormats.td:61 |
| 1139 | I64_TRUNC_S_SAT_F64 = 1124, // WebAssemblyInstrFormats.td:59 |
| 1140 | I64_TRUNC_S_SAT_F64_S = 1125, // WebAssemblyInstrFormats.td:61 |
| 1141 | I64_TRUNC_U_F32 = 1126, // WebAssemblyInstrFormats.td:59 |
| 1142 | I64_TRUNC_U_F32_S = 1127, // WebAssemblyInstrFormats.td:61 |
| 1143 | I64_TRUNC_U_F64 = 1128, // WebAssemblyInstrFormats.td:59 |
| 1144 | I64_TRUNC_U_F64_S = 1129, // WebAssemblyInstrFormats.td:61 |
| 1145 | I64_TRUNC_U_SAT_F32 = 1130, // WebAssemblyInstrFormats.td:59 |
| 1146 | I64_TRUNC_U_SAT_F32_S = 1131, // WebAssemblyInstrFormats.td:61 |
| 1147 | I64_TRUNC_U_SAT_F64 = 1132, // WebAssemblyInstrFormats.td:59 |
| 1148 | I64_TRUNC_U_SAT_F64_S = 1133, // WebAssemblyInstrFormats.td:61 |
| 1149 | IF = 1134, // WebAssemblyInstrFormats.td:59 |
| 1150 | IF_S = 1135, // WebAssemblyInstrFormats.td:61 |
| 1151 | LANESELECT_I16x8 = 1136, // WebAssemblyInstrFormats.td:59 |
| 1152 | LANESELECT_I16x8_S = 1137, // WebAssemblyInstrFormats.td:61 |
| 1153 | LANESELECT_I32x4 = 1138, // WebAssemblyInstrFormats.td:59 |
| 1154 | LANESELECT_I32x4_S = 1139, // WebAssemblyInstrFormats.td:61 |
| 1155 | LANESELECT_I64x2 = 1140, // WebAssemblyInstrFormats.td:59 |
| 1156 | LANESELECT_I64x2_S = 1141, // WebAssemblyInstrFormats.td:61 |
| 1157 | LANESELECT_I8x16 = 1142, // WebAssemblyInstrFormats.td:59 |
| 1158 | LANESELECT_I8x16_S = 1143, // WebAssemblyInstrFormats.td:61 |
| 1159 | LE_F16x8 = 1144, // WebAssemblyInstrFormats.td:59 |
| 1160 | LE_F16x8_S = 1145, // WebAssemblyInstrFormats.td:61 |
| 1161 | LE_F32 = 1146, // WebAssemblyInstrFormats.td:59 |
| 1162 | LE_F32_S = 1147, // WebAssemblyInstrFormats.td:61 |
| 1163 | LE_F32x4 = 1148, // WebAssemblyInstrFormats.td:59 |
| 1164 | LE_F32x4_S = 1149, // WebAssemblyInstrFormats.td:61 |
| 1165 | LE_F64 = 1150, // WebAssemblyInstrFormats.td:59 |
| 1166 | LE_F64_S = 1151, // WebAssemblyInstrFormats.td:61 |
| 1167 | LE_F64x2 = 1152, // WebAssemblyInstrFormats.td:59 |
| 1168 | LE_F64x2_S = 1153, // WebAssemblyInstrFormats.td:61 |
| 1169 | LE_S_I16x8 = 1154, // WebAssemblyInstrFormats.td:59 |
| 1170 | LE_S_I16x8_S = 1155, // WebAssemblyInstrFormats.td:61 |
| 1171 | LE_S_I32 = 1156, // WebAssemblyInstrFormats.td:59 |
| 1172 | LE_S_I32_S = 1157, // WebAssemblyInstrFormats.td:61 |
| 1173 | LE_S_I32x4 = 1158, // WebAssemblyInstrFormats.td:59 |
| 1174 | LE_S_I32x4_S = 1159, // WebAssemblyInstrFormats.td:61 |
| 1175 | LE_S_I64 = 1160, // WebAssemblyInstrFormats.td:59 |
| 1176 | LE_S_I64_S = 1161, // WebAssemblyInstrFormats.td:61 |
| 1177 | LE_S_I64x2 = 1162, // WebAssemblyInstrFormats.td:59 |
| 1178 | LE_S_I64x2_S = 1163, // WebAssemblyInstrFormats.td:61 |
| 1179 | LE_S_I8x16 = 1164, // WebAssemblyInstrFormats.td:59 |
| 1180 | LE_S_I8x16_S = 1165, // WebAssemblyInstrFormats.td:61 |
| 1181 | LE_U_I16x8 = 1166, // WebAssemblyInstrFormats.td:59 |
| 1182 | LE_U_I16x8_S = 1167, // WebAssemblyInstrFormats.td:61 |
| 1183 | LE_U_I32 = 1168, // WebAssemblyInstrFormats.td:59 |
| 1184 | LE_U_I32_S = 1169, // WebAssemblyInstrFormats.td:61 |
| 1185 | LE_U_I32x4 = 1170, // WebAssemblyInstrFormats.td:59 |
| 1186 | LE_U_I32x4_S = 1171, // WebAssemblyInstrFormats.td:61 |
| 1187 | LE_U_I64 = 1172, // WebAssemblyInstrFormats.td:59 |
| 1188 | LE_U_I64_S = 1173, // WebAssemblyInstrFormats.td:61 |
| 1189 | LE_U_I8x16 = 1174, // WebAssemblyInstrFormats.td:59 |
| 1190 | LE_U_I8x16_S = 1175, // WebAssemblyInstrFormats.td:61 |
| 1191 | LOAD16_SPLAT_A32 = 1176, // WebAssemblyInstrFormats.td:59 |
| 1192 | LOAD16_SPLAT_A32_S = 1177, // WebAssemblyInstrFormats.td:61 |
| 1193 | LOAD16_SPLAT_A64 = 1178, // WebAssemblyInstrFormats.td:59 |
| 1194 | LOAD16_SPLAT_A64_S = 1179, // WebAssemblyInstrFormats.td:61 |
| 1195 | LOAD16_S_I32_A32 = 1180, // WebAssemblyInstrFormats.td:59 |
| 1196 | LOAD16_S_I32_A32_S = 1181, // WebAssemblyInstrFormats.td:61 |
| 1197 | LOAD16_S_I32_A64 = 1182, // WebAssemblyInstrFormats.td:59 |
| 1198 | LOAD16_S_I32_A64_S = 1183, // WebAssemblyInstrFormats.td:61 |
| 1199 | LOAD16_S_I64_A32 = 1184, // WebAssemblyInstrFormats.td:59 |
| 1200 | LOAD16_S_I64_A32_S = 1185, // WebAssemblyInstrFormats.td:61 |
| 1201 | LOAD16_S_I64_A64 = 1186, // WebAssemblyInstrFormats.td:59 |
| 1202 | LOAD16_S_I64_A64_S = 1187, // WebAssemblyInstrFormats.td:61 |
| 1203 | LOAD16_U_I32_A32 = 1188, // WebAssemblyInstrFormats.td:59 |
| 1204 | LOAD16_U_I32_A32_S = 1189, // WebAssemblyInstrFormats.td:61 |
| 1205 | LOAD16_U_I32_A64 = 1190, // WebAssemblyInstrFormats.td:59 |
| 1206 | LOAD16_U_I32_A64_S = 1191, // WebAssemblyInstrFormats.td:61 |
| 1207 | LOAD16_U_I64_A32 = 1192, // WebAssemblyInstrFormats.td:59 |
| 1208 | LOAD16_U_I64_A32_S = 1193, // WebAssemblyInstrFormats.td:61 |
| 1209 | LOAD16_U_I64_A64 = 1194, // WebAssemblyInstrFormats.td:59 |
| 1210 | LOAD16_U_I64_A64_S = 1195, // WebAssemblyInstrFormats.td:61 |
| 1211 | LOAD32_SPLAT_A32 = 1196, // WebAssemblyInstrFormats.td:59 |
| 1212 | LOAD32_SPLAT_A32_S = 1197, // WebAssemblyInstrFormats.td:61 |
| 1213 | LOAD32_SPLAT_A64 = 1198, // WebAssemblyInstrFormats.td:59 |
| 1214 | LOAD32_SPLAT_A64_S = 1199, // WebAssemblyInstrFormats.td:61 |
| 1215 | LOAD32_S_I64_A32 = 1200, // WebAssemblyInstrFormats.td:59 |
| 1216 | LOAD32_S_I64_A32_S = 1201, // WebAssemblyInstrFormats.td:61 |
| 1217 | LOAD32_S_I64_A64 = 1202, // WebAssemblyInstrFormats.td:59 |
| 1218 | LOAD32_S_I64_A64_S = 1203, // WebAssemblyInstrFormats.td:61 |
| 1219 | LOAD32_U_I64_A32 = 1204, // WebAssemblyInstrFormats.td:59 |
| 1220 | LOAD32_U_I64_A32_S = 1205, // WebAssemblyInstrFormats.td:61 |
| 1221 | LOAD32_U_I64_A64 = 1206, // WebAssemblyInstrFormats.td:59 |
| 1222 | LOAD32_U_I64_A64_S = 1207, // WebAssemblyInstrFormats.td:61 |
| 1223 | LOAD64_SPLAT_A32 = 1208, // WebAssemblyInstrFormats.td:59 |
| 1224 | LOAD64_SPLAT_A32_S = 1209, // WebAssemblyInstrFormats.td:61 |
| 1225 | LOAD64_SPLAT_A64 = 1210, // WebAssemblyInstrFormats.td:59 |
| 1226 | LOAD64_SPLAT_A64_S = 1211, // WebAssemblyInstrFormats.td:61 |
| 1227 | LOAD8_SPLAT_A32 = 1212, // WebAssemblyInstrFormats.td:59 |
| 1228 | LOAD8_SPLAT_A32_S = 1213, // WebAssemblyInstrFormats.td:61 |
| 1229 | LOAD8_SPLAT_A64 = 1214, // WebAssemblyInstrFormats.td:59 |
| 1230 | LOAD8_SPLAT_A64_S = 1215, // WebAssemblyInstrFormats.td:61 |
| 1231 | LOAD8_S_I32_A32 = 1216, // WebAssemblyInstrFormats.td:59 |
| 1232 | LOAD8_S_I32_A32_S = 1217, // WebAssemblyInstrFormats.td:61 |
| 1233 | LOAD8_S_I32_A64 = 1218, // WebAssemblyInstrFormats.td:59 |
| 1234 | LOAD8_S_I32_A64_S = 1219, // WebAssemblyInstrFormats.td:61 |
| 1235 | LOAD8_S_I64_A32 = 1220, // WebAssemblyInstrFormats.td:59 |
| 1236 | LOAD8_S_I64_A32_S = 1221, // WebAssemblyInstrFormats.td:61 |
| 1237 | LOAD8_S_I64_A64 = 1222, // WebAssemblyInstrFormats.td:59 |
| 1238 | LOAD8_S_I64_A64_S = 1223, // WebAssemblyInstrFormats.td:61 |
| 1239 | LOAD8_U_I32_A32 = 1224, // WebAssemblyInstrFormats.td:59 |
| 1240 | LOAD8_U_I32_A32_S = 1225, // WebAssemblyInstrFormats.td:61 |
| 1241 | LOAD8_U_I32_A64 = 1226, // WebAssemblyInstrFormats.td:59 |
| 1242 | LOAD8_U_I32_A64_S = 1227, // WebAssemblyInstrFormats.td:61 |
| 1243 | LOAD8_U_I64_A32 = 1228, // WebAssemblyInstrFormats.td:59 |
| 1244 | LOAD8_U_I64_A32_S = 1229, // WebAssemblyInstrFormats.td:61 |
| 1245 | LOAD8_U_I64_A64 = 1230, // WebAssemblyInstrFormats.td:59 |
| 1246 | LOAD8_U_I64_A64_S = 1231, // WebAssemblyInstrFormats.td:61 |
| 1247 | LOAD_EXTEND_S_I16x8_A32 = 1232, // WebAssemblyInstrFormats.td:59 |
| 1248 | LOAD_EXTEND_S_I16x8_A32_S = 1233, // WebAssemblyInstrFormats.td:61 |
| 1249 | LOAD_EXTEND_S_I16x8_A64 = 1234, // WebAssemblyInstrFormats.td:59 |
| 1250 | LOAD_EXTEND_S_I16x8_A64_S = 1235, // WebAssemblyInstrFormats.td:61 |
| 1251 | LOAD_EXTEND_S_I32x4_A32 = 1236, // WebAssemblyInstrFormats.td:59 |
| 1252 | LOAD_EXTEND_S_I32x4_A32_S = 1237, // WebAssemblyInstrFormats.td:61 |
| 1253 | LOAD_EXTEND_S_I32x4_A64 = 1238, // WebAssemblyInstrFormats.td:59 |
| 1254 | LOAD_EXTEND_S_I32x4_A64_S = 1239, // WebAssemblyInstrFormats.td:61 |
| 1255 | LOAD_EXTEND_S_I64x2_A32 = 1240, // WebAssemblyInstrFormats.td:59 |
| 1256 | LOAD_EXTEND_S_I64x2_A32_S = 1241, // WebAssemblyInstrFormats.td:61 |
| 1257 | LOAD_EXTEND_S_I64x2_A64 = 1242, // WebAssemblyInstrFormats.td:59 |
| 1258 | LOAD_EXTEND_S_I64x2_A64_S = 1243, // WebAssemblyInstrFormats.td:61 |
| 1259 | LOAD_EXTEND_U_I16x8_A32 = 1244, // WebAssemblyInstrFormats.td:59 |
| 1260 | LOAD_EXTEND_U_I16x8_A32_S = 1245, // WebAssemblyInstrFormats.td:61 |
| 1261 | LOAD_EXTEND_U_I16x8_A64 = 1246, // WebAssemblyInstrFormats.td:59 |
| 1262 | LOAD_EXTEND_U_I16x8_A64_S = 1247, // WebAssemblyInstrFormats.td:61 |
| 1263 | LOAD_EXTEND_U_I32x4_A32 = 1248, // WebAssemblyInstrFormats.td:59 |
| 1264 | LOAD_EXTEND_U_I32x4_A32_S = 1249, // WebAssemblyInstrFormats.td:61 |
| 1265 | LOAD_EXTEND_U_I32x4_A64 = 1250, // WebAssemblyInstrFormats.td:59 |
| 1266 | LOAD_EXTEND_U_I32x4_A64_S = 1251, // WebAssemblyInstrFormats.td:61 |
| 1267 | LOAD_EXTEND_U_I64x2_A32 = 1252, // WebAssemblyInstrFormats.td:59 |
| 1268 | LOAD_EXTEND_U_I64x2_A32_S = 1253, // WebAssemblyInstrFormats.td:61 |
| 1269 | LOAD_EXTEND_U_I64x2_A64 = 1254, // WebAssemblyInstrFormats.td:59 |
| 1270 | LOAD_EXTEND_U_I64x2_A64_S = 1255, // WebAssemblyInstrFormats.td:61 |
| 1271 | LOAD_F16_F32_A32 = 1256, // WebAssemblyInstrFormats.td:59 |
| 1272 | LOAD_F16_F32_A32_S = 1257, // WebAssemblyInstrFormats.td:61 |
| 1273 | LOAD_F16_F32_A64 = 1258, // WebAssemblyInstrFormats.td:59 |
| 1274 | LOAD_F16_F32_A64_S = 1259, // WebAssemblyInstrFormats.td:61 |
| 1275 | LOAD_F32_A32 = 1260, // WebAssemblyInstrFormats.td:59 |
| 1276 | LOAD_F32_A32_S = 1261, // WebAssemblyInstrFormats.td:61 |
| 1277 | LOAD_F32_A64 = 1262, // WebAssemblyInstrFormats.td:59 |
| 1278 | LOAD_F32_A64_S = 1263, // WebAssemblyInstrFormats.td:61 |
| 1279 | LOAD_F64_A32 = 1264, // WebAssemblyInstrFormats.td:59 |
| 1280 | LOAD_F64_A32_S = 1265, // WebAssemblyInstrFormats.td:61 |
| 1281 | LOAD_F64_A64 = 1266, // WebAssemblyInstrFormats.td:59 |
| 1282 | LOAD_F64_A64_S = 1267, // WebAssemblyInstrFormats.td:61 |
| 1283 | LOAD_I32_A32 = 1268, // WebAssemblyInstrFormats.td:59 |
| 1284 | LOAD_I32_A32_S = 1269, // WebAssemblyInstrFormats.td:61 |
| 1285 | LOAD_I32_A64 = 1270, // WebAssemblyInstrFormats.td:59 |
| 1286 | LOAD_I32_A64_S = 1271, // WebAssemblyInstrFormats.td:61 |
| 1287 | LOAD_I64_A32 = 1272, // WebAssemblyInstrFormats.td:59 |
| 1288 | LOAD_I64_A32_S = 1273, // WebAssemblyInstrFormats.td:61 |
| 1289 | LOAD_I64_A64 = 1274, // WebAssemblyInstrFormats.td:59 |
| 1290 | LOAD_I64_A64_S = 1275, // WebAssemblyInstrFormats.td:61 |
| 1291 | LOAD_LANE_16_A32 = 1276, // WebAssemblyInstrFormats.td:59 |
| 1292 | LOAD_LANE_16_A32_S = 1277, // WebAssemblyInstrFormats.td:61 |
| 1293 | LOAD_LANE_16_A64 = 1278, // WebAssemblyInstrFormats.td:59 |
| 1294 | LOAD_LANE_16_A64_S = 1279, // WebAssemblyInstrFormats.td:61 |
| 1295 | LOAD_LANE_32_A32 = 1280, // WebAssemblyInstrFormats.td:59 |
| 1296 | LOAD_LANE_32_A32_S = 1281, // WebAssemblyInstrFormats.td:61 |
| 1297 | LOAD_LANE_32_A64 = 1282, // WebAssemblyInstrFormats.td:59 |
| 1298 | LOAD_LANE_32_A64_S = 1283, // WebAssemblyInstrFormats.td:61 |
| 1299 | LOAD_LANE_64_A32 = 1284, // WebAssemblyInstrFormats.td:59 |
| 1300 | LOAD_LANE_64_A32_S = 1285, // WebAssemblyInstrFormats.td:61 |
| 1301 | LOAD_LANE_64_A64 = 1286, // WebAssemblyInstrFormats.td:59 |
| 1302 | LOAD_LANE_64_A64_S = 1287, // WebAssemblyInstrFormats.td:61 |
| 1303 | LOAD_LANE_8_A32 = 1288, // WebAssemblyInstrFormats.td:59 |
| 1304 | LOAD_LANE_8_A32_S = 1289, // WebAssemblyInstrFormats.td:61 |
| 1305 | LOAD_LANE_8_A64 = 1290, // WebAssemblyInstrFormats.td:59 |
| 1306 | LOAD_LANE_8_A64_S = 1291, // WebAssemblyInstrFormats.td:61 |
| 1307 | LOAD_V128_A32 = 1292, // WebAssemblyInstrFormats.td:59 |
| 1308 | LOAD_V128_A32_S = 1293, // WebAssemblyInstrFormats.td:61 |
| 1309 | LOAD_V128_A64 = 1294, // WebAssemblyInstrFormats.td:59 |
| 1310 | LOAD_V128_A64_S = 1295, // WebAssemblyInstrFormats.td:61 |
| 1311 | LOAD_ZERO_32_A32 = 1296, // WebAssemblyInstrFormats.td:59 |
| 1312 | LOAD_ZERO_32_A32_S = 1297, // WebAssemblyInstrFormats.td:61 |
| 1313 | LOAD_ZERO_32_A64 = 1298, // WebAssemblyInstrFormats.td:59 |
| 1314 | LOAD_ZERO_32_A64_S = 1299, // WebAssemblyInstrFormats.td:61 |
| 1315 | LOAD_ZERO_64_A32 = 1300, // WebAssemblyInstrFormats.td:59 |
| 1316 | LOAD_ZERO_64_A32_S = 1301, // WebAssemblyInstrFormats.td:61 |
| 1317 | LOAD_ZERO_64_A64 = 1302, // WebAssemblyInstrFormats.td:59 |
| 1318 | LOAD_ZERO_64_A64_S = 1303, // WebAssemblyInstrFormats.td:61 |
| 1319 | LOCAL_GET_EXNREF = 1304, // WebAssemblyInstrFormats.td:59 |
| 1320 | LOCAL_GET_EXNREF_S = 1305, // WebAssemblyInstrFormats.td:61 |
| 1321 | LOCAL_GET_EXTERNREF = 1306, // WebAssemblyInstrFormats.td:59 |
| 1322 | LOCAL_GET_EXTERNREF_S = 1307, // WebAssemblyInstrFormats.td:61 |
| 1323 | LOCAL_GET_F32 = 1308, // WebAssemblyInstrFormats.td:59 |
| 1324 | LOCAL_GET_F32_S = 1309, // WebAssemblyInstrFormats.td:61 |
| 1325 | LOCAL_GET_F64 = 1310, // WebAssemblyInstrFormats.td:59 |
| 1326 | LOCAL_GET_F64_S = 1311, // WebAssemblyInstrFormats.td:61 |
| 1327 | LOCAL_GET_FUNCREF = 1312, // WebAssemblyInstrFormats.td:59 |
| 1328 | LOCAL_GET_FUNCREF_S = 1313, // WebAssemblyInstrFormats.td:61 |
| 1329 | LOCAL_GET_I32 = 1314, // WebAssemblyInstrFormats.td:59 |
| 1330 | LOCAL_GET_I32_S = 1315, // WebAssemblyInstrFormats.td:61 |
| 1331 | LOCAL_GET_I64 = 1316, // WebAssemblyInstrFormats.td:59 |
| 1332 | LOCAL_GET_I64_S = 1317, // WebAssemblyInstrFormats.td:61 |
| 1333 | LOCAL_GET_V128 = 1318, // WebAssemblyInstrFormats.td:59 |
| 1334 | LOCAL_GET_V128_S = 1319, // WebAssemblyInstrFormats.td:61 |
| 1335 | LOCAL_SET_EXNREF = 1320, // WebAssemblyInstrFormats.td:59 |
| 1336 | LOCAL_SET_EXNREF_S = 1321, // WebAssemblyInstrFormats.td:61 |
| 1337 | LOCAL_SET_EXTERNREF = 1322, // WebAssemblyInstrFormats.td:59 |
| 1338 | LOCAL_SET_EXTERNREF_S = 1323, // WebAssemblyInstrFormats.td:61 |
| 1339 | LOCAL_SET_F32 = 1324, // WebAssemblyInstrFormats.td:59 |
| 1340 | LOCAL_SET_F32_S = 1325, // WebAssemblyInstrFormats.td:61 |
| 1341 | LOCAL_SET_F64 = 1326, // WebAssemblyInstrFormats.td:59 |
| 1342 | LOCAL_SET_F64_S = 1327, // WebAssemblyInstrFormats.td:61 |
| 1343 | LOCAL_SET_FUNCREF = 1328, // WebAssemblyInstrFormats.td:59 |
| 1344 | LOCAL_SET_FUNCREF_S = 1329, // WebAssemblyInstrFormats.td:61 |
| 1345 | LOCAL_SET_I32 = 1330, // WebAssemblyInstrFormats.td:59 |
| 1346 | LOCAL_SET_I32_S = 1331, // WebAssemblyInstrFormats.td:61 |
| 1347 | LOCAL_SET_I64 = 1332, // WebAssemblyInstrFormats.td:59 |
| 1348 | LOCAL_SET_I64_S = 1333, // WebAssemblyInstrFormats.td:61 |
| 1349 | LOCAL_SET_V128 = 1334, // WebAssemblyInstrFormats.td:59 |
| 1350 | LOCAL_SET_V128_S = 1335, // WebAssemblyInstrFormats.td:61 |
| 1351 | LOCAL_TEE_EXNREF = 1336, // WebAssemblyInstrFormats.td:59 |
| 1352 | LOCAL_TEE_EXNREF_S = 1337, // WebAssemblyInstrFormats.td:61 |
| 1353 | LOCAL_TEE_EXTERNREF = 1338, // WebAssemblyInstrFormats.td:59 |
| 1354 | LOCAL_TEE_EXTERNREF_S = 1339, // WebAssemblyInstrFormats.td:61 |
| 1355 | LOCAL_TEE_F32 = 1340, // WebAssemblyInstrFormats.td:59 |
| 1356 | LOCAL_TEE_F32_S = 1341, // WebAssemblyInstrFormats.td:61 |
| 1357 | LOCAL_TEE_F64 = 1342, // WebAssemblyInstrFormats.td:59 |
| 1358 | LOCAL_TEE_F64_S = 1343, // WebAssemblyInstrFormats.td:61 |
| 1359 | LOCAL_TEE_FUNCREF = 1344, // WebAssemblyInstrFormats.td:59 |
| 1360 | LOCAL_TEE_FUNCREF_S = 1345, // WebAssemblyInstrFormats.td:61 |
| 1361 | LOCAL_TEE_I32 = 1346, // WebAssemblyInstrFormats.td:59 |
| 1362 | LOCAL_TEE_I32_S = 1347, // WebAssemblyInstrFormats.td:61 |
| 1363 | LOCAL_TEE_I64 = 1348, // WebAssemblyInstrFormats.td:59 |
| 1364 | LOCAL_TEE_I64_S = 1349, // WebAssemblyInstrFormats.td:61 |
| 1365 | LOCAL_TEE_V128 = 1350, // WebAssemblyInstrFormats.td:59 |
| 1366 | LOCAL_TEE_V128_S = 1351, // WebAssemblyInstrFormats.td:61 |
| 1367 | LOOP = 1352, // WebAssemblyInstrFormats.td:59 |
| 1368 | LOOP_S = 1353, // WebAssemblyInstrFormats.td:61 |
| 1369 | LT_F16x8 = 1354, // WebAssemblyInstrFormats.td:59 |
| 1370 | LT_F16x8_S = 1355, // WebAssemblyInstrFormats.td:61 |
| 1371 | LT_F32 = 1356, // WebAssemblyInstrFormats.td:59 |
| 1372 | LT_F32_S = 1357, // WebAssemblyInstrFormats.td:61 |
| 1373 | LT_F32x4 = 1358, // WebAssemblyInstrFormats.td:59 |
| 1374 | LT_F32x4_S = 1359, // WebAssemblyInstrFormats.td:61 |
| 1375 | LT_F64 = 1360, // WebAssemblyInstrFormats.td:59 |
| 1376 | LT_F64_S = 1361, // WebAssemblyInstrFormats.td:61 |
| 1377 | LT_F64x2 = 1362, // WebAssemblyInstrFormats.td:59 |
| 1378 | LT_F64x2_S = 1363, // WebAssemblyInstrFormats.td:61 |
| 1379 | LT_S_I16x8 = 1364, // WebAssemblyInstrFormats.td:59 |
| 1380 | LT_S_I16x8_S = 1365, // WebAssemblyInstrFormats.td:61 |
| 1381 | LT_S_I32 = 1366, // WebAssemblyInstrFormats.td:59 |
| 1382 | LT_S_I32_S = 1367, // WebAssemblyInstrFormats.td:61 |
| 1383 | LT_S_I32x4 = 1368, // WebAssemblyInstrFormats.td:59 |
| 1384 | LT_S_I32x4_S = 1369, // WebAssemblyInstrFormats.td:61 |
| 1385 | LT_S_I64 = 1370, // WebAssemblyInstrFormats.td:59 |
| 1386 | LT_S_I64_S = 1371, // WebAssemblyInstrFormats.td:61 |
| 1387 | LT_S_I64x2 = 1372, // WebAssemblyInstrFormats.td:59 |
| 1388 | LT_S_I64x2_S = 1373, // WebAssemblyInstrFormats.td:61 |
| 1389 | LT_S_I8x16 = 1374, // WebAssemblyInstrFormats.td:59 |
| 1390 | LT_S_I8x16_S = 1375, // WebAssemblyInstrFormats.td:61 |
| 1391 | LT_U_I16x8 = 1376, // WebAssemblyInstrFormats.td:59 |
| 1392 | LT_U_I16x8_S = 1377, // WebAssemblyInstrFormats.td:61 |
| 1393 | LT_U_I32 = 1378, // WebAssemblyInstrFormats.td:59 |
| 1394 | LT_U_I32_S = 1379, // WebAssemblyInstrFormats.td:61 |
| 1395 | LT_U_I32x4 = 1380, // WebAssemblyInstrFormats.td:59 |
| 1396 | LT_U_I32x4_S = 1381, // WebAssemblyInstrFormats.td:61 |
| 1397 | LT_U_I64 = 1382, // WebAssemblyInstrFormats.td:59 |
| 1398 | LT_U_I64_S = 1383, // WebAssemblyInstrFormats.td:61 |
| 1399 | LT_U_I8x16 = 1384, // WebAssemblyInstrFormats.td:59 |
| 1400 | LT_U_I8x16_S = 1385, // WebAssemblyInstrFormats.td:61 |
| 1401 | MADD_F16x8 = 1386, // WebAssemblyInstrFormats.td:59 |
| 1402 | MADD_F16x8_S = 1387, // WebAssemblyInstrFormats.td:61 |
| 1403 | MADD_F32x4 = 1388, // WebAssemblyInstrFormats.td:59 |
| 1404 | MADD_F32x4_S = 1389, // WebAssemblyInstrFormats.td:61 |
| 1405 | MADD_F64x2 = 1390, // WebAssemblyInstrFormats.td:59 |
| 1406 | MADD_F64x2_S = 1391, // WebAssemblyInstrFormats.td:61 |
| 1407 | MAX_F16x8 = 1392, // WebAssemblyInstrFormats.td:59 |
| 1408 | MAX_F16x8_S = 1393, // WebAssemblyInstrFormats.td:61 |
| 1409 | MAX_F32 = 1394, // WebAssemblyInstrFormats.td:59 |
| 1410 | MAX_F32_S = 1395, // WebAssemblyInstrFormats.td:61 |
| 1411 | MAX_F32x4 = 1396, // WebAssemblyInstrFormats.td:59 |
| 1412 | MAX_F32x4_S = 1397, // WebAssemblyInstrFormats.td:61 |
| 1413 | MAX_F64 = 1398, // WebAssemblyInstrFormats.td:59 |
| 1414 | MAX_F64_S = 1399, // WebAssemblyInstrFormats.td:61 |
| 1415 | MAX_F64x2 = 1400, // WebAssemblyInstrFormats.td:59 |
| 1416 | MAX_F64x2_S = 1401, // WebAssemblyInstrFormats.td:61 |
| 1417 | MAX_S_I16x8 = 1402, // WebAssemblyInstrFormats.td:59 |
| 1418 | MAX_S_I16x8_S = 1403, // WebAssemblyInstrFormats.td:61 |
| 1419 | MAX_S_I32x4 = 1404, // WebAssemblyInstrFormats.td:59 |
| 1420 | MAX_S_I32x4_S = 1405, // WebAssemblyInstrFormats.td:61 |
| 1421 | MAX_S_I8x16 = 1406, // WebAssemblyInstrFormats.td:59 |
| 1422 | MAX_S_I8x16_S = 1407, // WebAssemblyInstrFormats.td:61 |
| 1423 | MAX_U_I16x8 = 1408, // WebAssemblyInstrFormats.td:59 |
| 1424 | MAX_U_I16x8_S = 1409, // WebAssemblyInstrFormats.td:61 |
| 1425 | MAX_U_I32x4 = 1410, // WebAssemblyInstrFormats.td:59 |
| 1426 | MAX_U_I32x4_S = 1411, // WebAssemblyInstrFormats.td:61 |
| 1427 | MAX_U_I8x16 = 1412, // WebAssemblyInstrFormats.td:59 |
| 1428 | MAX_U_I8x16_S = 1413, // WebAssemblyInstrFormats.td:61 |
| 1429 | MEMCPY_A32 = 1414, // WebAssemblyInstrFormats.td:59 |
| 1430 | MEMCPY_A32_S = 1415, // WebAssemblyInstrFormats.td:61 |
| 1431 | MEMCPY_A64 = 1416, // WebAssemblyInstrFormats.td:59 |
| 1432 | MEMCPY_A64_S = 1417, // WebAssemblyInstrFormats.td:61 |
| 1433 | MEMORY_ATOMIC_NOTIFY_A32 = 1418, // WebAssemblyInstrFormats.td:59 |
| 1434 | MEMORY_ATOMIC_NOTIFY_A32_S = 1419, // WebAssemblyInstrFormats.td:61 |
| 1435 | MEMORY_ATOMIC_NOTIFY_A64 = 1420, // WebAssemblyInstrFormats.td:59 |
| 1436 | MEMORY_ATOMIC_NOTIFY_A64_S = 1421, // WebAssemblyInstrFormats.td:61 |
| 1437 | MEMORY_ATOMIC_WAIT32_A32 = 1422, // WebAssemblyInstrFormats.td:59 |
| 1438 | MEMORY_ATOMIC_WAIT32_A32_S = 1423, // WebAssemblyInstrFormats.td:61 |
| 1439 | MEMORY_ATOMIC_WAIT32_A64 = 1424, // WebAssemblyInstrFormats.td:59 |
| 1440 | MEMORY_ATOMIC_WAIT32_A64_S = 1425, // WebAssemblyInstrFormats.td:61 |
| 1441 | MEMORY_ATOMIC_WAIT64_A32 = 1426, // WebAssemblyInstrFormats.td:59 |
| 1442 | MEMORY_ATOMIC_WAIT64_A32_S = 1427, // WebAssemblyInstrFormats.td:61 |
| 1443 | MEMORY_ATOMIC_WAIT64_A64 = 1428, // WebAssemblyInstrFormats.td:59 |
| 1444 | MEMORY_ATOMIC_WAIT64_A64_S = 1429, // WebAssemblyInstrFormats.td:61 |
| 1445 | MEMORY_COPY_A32 = 1430, // WebAssemblyInstrFormats.td:59 |
| 1446 | MEMORY_COPY_A32_S = 1431, // WebAssemblyInstrFormats.td:61 |
| 1447 | MEMORY_COPY_A64 = 1432, // WebAssemblyInstrFormats.td:59 |
| 1448 | MEMORY_COPY_A64_S = 1433, // WebAssemblyInstrFormats.td:61 |
| 1449 | MEMORY_FILL_A32 = 1434, // WebAssemblyInstrFormats.td:59 |
| 1450 | MEMORY_FILL_A32_S = 1435, // WebAssemblyInstrFormats.td:61 |
| 1451 | MEMORY_FILL_A64 = 1436, // WebAssemblyInstrFormats.td:59 |
| 1452 | MEMORY_FILL_A64_S = 1437, // WebAssemblyInstrFormats.td:61 |
| 1453 | MEMORY_INIT_A32 = 1438, // WebAssemblyInstrFormats.td:59 |
| 1454 | MEMORY_INIT_A32_S = 1439, // WebAssemblyInstrFormats.td:61 |
| 1455 | MEMORY_INIT_A64 = 1440, // WebAssemblyInstrFormats.td:59 |
| 1456 | MEMORY_INIT_A64_S = 1441, // WebAssemblyInstrFormats.td:61 |
| 1457 | MEMSET_A32 = 1442, // WebAssemblyInstrFormats.td:59 |
| 1458 | MEMSET_A32_S = 1443, // WebAssemblyInstrFormats.td:61 |
| 1459 | MEMSET_A64 = 1444, // WebAssemblyInstrFormats.td:59 |
| 1460 | MEMSET_A64_S = 1445, // WebAssemblyInstrFormats.td:61 |
| 1461 | MIN_F16x8 = 1446, // WebAssemblyInstrFormats.td:59 |
| 1462 | MIN_F16x8_S = 1447, // WebAssemblyInstrFormats.td:61 |
| 1463 | MIN_F32 = 1448, // WebAssemblyInstrFormats.td:59 |
| 1464 | MIN_F32_S = 1449, // WebAssemblyInstrFormats.td:61 |
| 1465 | MIN_F32x4 = 1450, // WebAssemblyInstrFormats.td:59 |
| 1466 | MIN_F32x4_S = 1451, // WebAssemblyInstrFormats.td:61 |
| 1467 | MIN_F64 = 1452, // WebAssemblyInstrFormats.td:59 |
| 1468 | MIN_F64_S = 1453, // WebAssemblyInstrFormats.td:61 |
| 1469 | MIN_F64x2 = 1454, // WebAssemblyInstrFormats.td:59 |
| 1470 | MIN_F64x2_S = 1455, // WebAssemblyInstrFormats.td:61 |
| 1471 | MIN_S_I16x8 = 1456, // WebAssemblyInstrFormats.td:59 |
| 1472 | MIN_S_I16x8_S = 1457, // WebAssemblyInstrFormats.td:61 |
| 1473 | MIN_S_I32x4 = 1458, // WebAssemblyInstrFormats.td:59 |
| 1474 | MIN_S_I32x4_S = 1459, // WebAssemblyInstrFormats.td:61 |
| 1475 | MIN_S_I8x16 = 1460, // WebAssemblyInstrFormats.td:59 |
| 1476 | MIN_S_I8x16_S = 1461, // WebAssemblyInstrFormats.td:61 |
| 1477 | MIN_U_I16x8 = 1462, // WebAssemblyInstrFormats.td:59 |
| 1478 | MIN_U_I16x8_S = 1463, // WebAssemblyInstrFormats.td:61 |
| 1479 | MIN_U_I32x4 = 1464, // WebAssemblyInstrFormats.td:59 |
| 1480 | MIN_U_I32x4_S = 1465, // WebAssemblyInstrFormats.td:61 |
| 1481 | MIN_U_I8x16 = 1466, // WebAssemblyInstrFormats.td:59 |
| 1482 | MIN_U_I8x16_S = 1467, // WebAssemblyInstrFormats.td:61 |
| 1483 | MUL_F16x8 = 1468, // WebAssemblyInstrFormats.td:59 |
| 1484 | MUL_F16x8_S = 1469, // WebAssemblyInstrFormats.td:61 |
| 1485 | MUL_F32 = 1470, // WebAssemblyInstrFormats.td:59 |
| 1486 | MUL_F32_S = 1471, // WebAssemblyInstrFormats.td:61 |
| 1487 | MUL_F32x4 = 1472, // WebAssemblyInstrFormats.td:59 |
| 1488 | MUL_F32x4_S = 1473, // WebAssemblyInstrFormats.td:61 |
| 1489 | MUL_F64 = 1474, // WebAssemblyInstrFormats.td:59 |
| 1490 | MUL_F64_S = 1475, // WebAssemblyInstrFormats.td:61 |
| 1491 | MUL_F64x2 = 1476, // WebAssemblyInstrFormats.td:59 |
| 1492 | MUL_F64x2_S = 1477, // WebAssemblyInstrFormats.td:61 |
| 1493 | MUL_I16x8 = 1478, // WebAssemblyInstrFormats.td:59 |
| 1494 | MUL_I16x8_S = 1479, // WebAssemblyInstrFormats.td:61 |
| 1495 | MUL_I32 = 1480, // WebAssemblyInstrFormats.td:59 |
| 1496 | MUL_I32_S = 1481, // WebAssemblyInstrFormats.td:61 |
| 1497 | MUL_I32x4 = 1482, // WebAssemblyInstrFormats.td:59 |
| 1498 | MUL_I32x4_S = 1483, // WebAssemblyInstrFormats.td:61 |
| 1499 | MUL_I64 = 1484, // WebAssemblyInstrFormats.td:59 |
| 1500 | MUL_I64_S = 1485, // WebAssemblyInstrFormats.td:61 |
| 1501 | MUL_I64x2 = 1486, // WebAssemblyInstrFormats.td:59 |
| 1502 | MUL_I64x2_S = 1487, // WebAssemblyInstrFormats.td:61 |
| 1503 | NARROW_S_I16x8 = 1488, // WebAssemblyInstrFormats.td:59 |
| 1504 | NARROW_S_I16x8_S = 1489, // WebAssemblyInstrFormats.td:61 |
| 1505 | NARROW_S_I8x16 = 1490, // WebAssemblyInstrFormats.td:59 |
| 1506 | NARROW_S_I8x16_S = 1491, // WebAssemblyInstrFormats.td:61 |
| 1507 | NARROW_U_I16x8 = 1492, // WebAssemblyInstrFormats.td:59 |
| 1508 | NARROW_U_I16x8_S = 1493, // WebAssemblyInstrFormats.td:61 |
| 1509 | NARROW_U_I8x16 = 1494, // WebAssemblyInstrFormats.td:59 |
| 1510 | NARROW_U_I8x16_S = 1495, // WebAssemblyInstrFormats.td:61 |
| 1511 | NEAREST_F16x8 = 1496, // WebAssemblyInstrFormats.td:59 |
| 1512 | NEAREST_F16x8_S = 1497, // WebAssemblyInstrFormats.td:61 |
| 1513 | NEAREST_F32 = 1498, // WebAssemblyInstrFormats.td:59 |
| 1514 | NEAREST_F32_S = 1499, // WebAssemblyInstrFormats.td:61 |
| 1515 | NEAREST_F32x4 = 1500, // WebAssemblyInstrFormats.td:59 |
| 1516 | NEAREST_F32x4_S = 1501, // WebAssemblyInstrFormats.td:61 |
| 1517 | NEAREST_F64 = 1502, // WebAssemblyInstrFormats.td:59 |
| 1518 | NEAREST_F64_S = 1503, // WebAssemblyInstrFormats.td:61 |
| 1519 | NEAREST_F64x2 = 1504, // WebAssemblyInstrFormats.td:59 |
| 1520 | NEAREST_F64x2_S = 1505, // WebAssemblyInstrFormats.td:61 |
| 1521 | NEG_F16x8 = 1506, // WebAssemblyInstrFormats.td:59 |
| 1522 | NEG_F16x8_S = 1507, // WebAssemblyInstrFormats.td:61 |
| 1523 | NEG_F32 = 1508, // WebAssemblyInstrFormats.td:59 |
| 1524 | NEG_F32_S = 1509, // WebAssemblyInstrFormats.td:61 |
| 1525 | NEG_F32x4 = 1510, // WebAssemblyInstrFormats.td:59 |
| 1526 | NEG_F32x4_S = 1511, // WebAssemblyInstrFormats.td:61 |
| 1527 | NEG_F64 = 1512, // WebAssemblyInstrFormats.td:59 |
| 1528 | NEG_F64_S = 1513, // WebAssemblyInstrFormats.td:61 |
| 1529 | NEG_F64x2 = 1514, // WebAssemblyInstrFormats.td:59 |
| 1530 | NEG_F64x2_S = 1515, // WebAssemblyInstrFormats.td:61 |
| 1531 | NEG_I16x8 = 1516, // WebAssemblyInstrFormats.td:59 |
| 1532 | NEG_I16x8_S = 1517, // WebAssemblyInstrFormats.td:61 |
| 1533 | NEG_I32x4 = 1518, // WebAssemblyInstrFormats.td:59 |
| 1534 | NEG_I32x4_S = 1519, // WebAssemblyInstrFormats.td:61 |
| 1535 | NEG_I64x2 = 1520, // WebAssemblyInstrFormats.td:59 |
| 1536 | NEG_I64x2_S = 1521, // WebAssemblyInstrFormats.td:61 |
| 1537 | NEG_I8x16 = 1522, // WebAssemblyInstrFormats.td:59 |
| 1538 | NEG_I8x16_S = 1523, // WebAssemblyInstrFormats.td:61 |
| 1539 | NE_F16x8 = 1524, // WebAssemblyInstrFormats.td:59 |
| 1540 | NE_F16x8_S = 1525, // WebAssemblyInstrFormats.td:61 |
| 1541 | NE_F32 = 1526, // WebAssemblyInstrFormats.td:59 |
| 1542 | NE_F32_S = 1527, // WebAssemblyInstrFormats.td:61 |
| 1543 | NE_F32x4 = 1528, // WebAssemblyInstrFormats.td:59 |
| 1544 | NE_F32x4_S = 1529, // WebAssemblyInstrFormats.td:61 |
| 1545 | NE_F64 = 1530, // WebAssemblyInstrFormats.td:59 |
| 1546 | NE_F64_S = 1531, // WebAssemblyInstrFormats.td:61 |
| 1547 | NE_F64x2 = 1532, // WebAssemblyInstrFormats.td:59 |
| 1548 | NE_F64x2_S = 1533, // WebAssemblyInstrFormats.td:61 |
| 1549 | NE_I16x8 = 1534, // WebAssemblyInstrFormats.td:59 |
| 1550 | NE_I16x8_S = 1535, // WebAssemblyInstrFormats.td:61 |
| 1551 | NE_I32 = 1536, // WebAssemblyInstrFormats.td:59 |
| 1552 | NE_I32_S = 1537, // WebAssemblyInstrFormats.td:61 |
| 1553 | NE_I32x4 = 1538, // WebAssemblyInstrFormats.td:59 |
| 1554 | NE_I32x4_S = 1539, // WebAssemblyInstrFormats.td:61 |
| 1555 | NE_I64 = 1540, // WebAssemblyInstrFormats.td:59 |
| 1556 | NE_I64_S = 1541, // WebAssemblyInstrFormats.td:61 |
| 1557 | NE_I64x2 = 1542, // WebAssemblyInstrFormats.td:59 |
| 1558 | NE_I64x2_S = 1543, // WebAssemblyInstrFormats.td:61 |
| 1559 | NE_I8x16 = 1544, // WebAssemblyInstrFormats.td:59 |
| 1560 | NE_I8x16_S = 1545, // WebAssemblyInstrFormats.td:61 |
| 1561 | NMADD_F16x8 = 1546, // WebAssemblyInstrFormats.td:59 |
| 1562 | NMADD_F16x8_S = 1547, // WebAssemblyInstrFormats.td:61 |
| 1563 | NMADD_F32x4 = 1548, // WebAssemblyInstrFormats.td:59 |
| 1564 | NMADD_F32x4_S = 1549, // WebAssemblyInstrFormats.td:61 |
| 1565 | NMADD_F64x2 = 1550, // WebAssemblyInstrFormats.td:59 |
| 1566 | NMADD_F64x2_S = 1551, // WebAssemblyInstrFormats.td:61 |
| 1567 | NOP = 1552, // WebAssemblyInstrFormats.td:59 |
| 1568 | NOP_S = 1553, // WebAssemblyInstrFormats.td:61 |
| 1569 | NOT = 1554, // WebAssemblyInstrFormats.td:59 |
| 1570 | NOT_S = 1555, // WebAssemblyInstrFormats.td:61 |
| 1571 | OR = 1556, // WebAssemblyInstrFormats.td:59 |
| 1572 | OR_I32 = 1557, // WebAssemblyInstrFormats.td:59 |
| 1573 | OR_I32_S = 1558, // WebAssemblyInstrFormats.td:61 |
| 1574 | OR_I64 = 1559, // WebAssemblyInstrFormats.td:59 |
| 1575 | OR_I64_S = 1560, // WebAssemblyInstrFormats.td:61 |
| 1576 | OR_S = 1561, // WebAssemblyInstrFormats.td:61 |
| 1577 | PMAX_F16x8 = 1562, // WebAssemblyInstrFormats.td:59 |
| 1578 | PMAX_F16x8_S = 1563, // WebAssemblyInstrFormats.td:61 |
| 1579 | PMAX_F32x4 = 1564, // WebAssemblyInstrFormats.td:59 |
| 1580 | PMAX_F32x4_S = 1565, // WebAssemblyInstrFormats.td:61 |
| 1581 | PMAX_F64x2 = 1566, // WebAssemblyInstrFormats.td:59 |
| 1582 | PMAX_F64x2_S = 1567, // WebAssemblyInstrFormats.td:61 |
| 1583 | PMIN_F16x8 = 1568, // WebAssemblyInstrFormats.td:59 |
| 1584 | PMIN_F16x8_S = 1569, // WebAssemblyInstrFormats.td:61 |
| 1585 | PMIN_F32x4 = 1570, // WebAssemblyInstrFormats.td:59 |
| 1586 | PMIN_F32x4_S = 1571, // WebAssemblyInstrFormats.td:61 |
| 1587 | PMIN_F64x2 = 1572, // WebAssemblyInstrFormats.td:59 |
| 1588 | PMIN_F64x2_S = 1573, // WebAssemblyInstrFormats.td:61 |
| 1589 | POPCNT_I32 = 1574, // WebAssemblyInstrFormats.td:59 |
| 1590 | POPCNT_I32_S = 1575, // WebAssemblyInstrFormats.td:61 |
| 1591 | POPCNT_I64 = 1576, // WebAssemblyInstrFormats.td:59 |
| 1592 | POPCNT_I64_S = 1577, // WebAssemblyInstrFormats.td:61 |
| 1593 | POPCNT_I8x16 = 1578, // WebAssemblyInstrFormats.td:59 |
| 1594 | POPCNT_I8x16_S = 1579, // WebAssemblyInstrFormats.td:61 |
| 1595 | Q15MULR_SAT_S_I16x8 = 1580, // WebAssemblyInstrFormats.td:59 |
| 1596 | Q15MULR_SAT_S_I16x8_S = 1581, // WebAssemblyInstrFormats.td:61 |
| 1597 | REF_CAST_FUNCREF = 1582, // WebAssemblyInstrFormats.td:59 |
| 1598 | REF_CAST_FUNCREF_S = 1583, // WebAssemblyInstrFormats.td:61 |
| 1599 | REF_FUNC = 1584, // WebAssemblyInstrFormats.td:59 |
| 1600 | REF_FUNC_S = 1585, // WebAssemblyInstrFormats.td:61 |
| 1601 | REF_IS_NULL_EXNREF = 1586, // WebAssemblyInstrFormats.td:59 |
| 1602 | REF_IS_NULL_EXNREF_S = 1587, // WebAssemblyInstrFormats.td:61 |
| 1603 | REF_IS_NULL_EXTERNREF = 1588, // WebAssemblyInstrFormats.td:59 |
| 1604 | REF_IS_NULL_EXTERNREF_S = 1589, // WebAssemblyInstrFormats.td:61 |
| 1605 | REF_IS_NULL_FUNCREF = 1590, // WebAssemblyInstrFormats.td:59 |
| 1606 | REF_IS_NULL_FUNCREF_S = 1591, // WebAssemblyInstrFormats.td:61 |
| 1607 | REF_NULL_EXNREF = 1592, // WebAssemblyInstrFormats.td:59 |
| 1608 | REF_NULL_EXNREF_S = 1593, // WebAssemblyInstrFormats.td:61 |
| 1609 | REF_NULL_EXTERNREF = 1594, // WebAssemblyInstrFormats.td:59 |
| 1610 | REF_NULL_EXTERNREF_S = 1595, // WebAssemblyInstrFormats.td:61 |
| 1611 | REF_NULL_FUNCREF = 1596, // WebAssemblyInstrFormats.td:59 |
| 1612 | REF_NULL_FUNCREF_S = 1597, // WebAssemblyInstrFormats.td:61 |
| 1613 | REF_TEST_FUNCREF = 1598, // WebAssemblyInstrFormats.td:59 |
| 1614 | REF_TEST_FUNCREF_S = 1599, // WebAssemblyInstrFormats.td:61 |
| 1615 | RELAXED_DOT = 1600, // WebAssemblyInstrFormats.td:59 |
| 1616 | RELAXED_DOT_ADD = 1601, // WebAssemblyInstrFormats.td:59 |
| 1617 | RELAXED_DOT_ADD_S = 1602, // WebAssemblyInstrFormats.td:61 |
| 1618 | RELAXED_DOT_BFLOAT = 1603, // WebAssemblyInstrFormats.td:59 |
| 1619 | RELAXED_DOT_BFLOAT_S = 1604, // WebAssemblyInstrFormats.td:61 |
| 1620 | RELAXED_DOT_S = 1605, // WebAssemblyInstrFormats.td:61 |
| 1621 | RELAXED_Q15MULR_S_I16x8 = 1606, // WebAssemblyInstrFormats.td:59 |
| 1622 | RELAXED_Q15MULR_S_I16x8_S = 1607, // WebAssemblyInstrFormats.td:61 |
| 1623 | RELAXED_SWIZZLE = 1608, // WebAssemblyInstrFormats.td:59 |
| 1624 | RELAXED_SWIZZLE_S = 1609, // WebAssemblyInstrFormats.td:61 |
| 1625 | REM_S_I32 = 1610, // WebAssemblyInstrFormats.td:59 |
| 1626 | REM_S_I32_S = 1611, // WebAssemblyInstrFormats.td:61 |
| 1627 | REM_S_I64 = 1612, // WebAssemblyInstrFormats.td:59 |
| 1628 | REM_S_I64_S = 1613, // WebAssemblyInstrFormats.td:61 |
| 1629 | REM_U_I32 = 1614, // WebAssemblyInstrFormats.td:59 |
| 1630 | REM_U_I32_S = 1615, // WebAssemblyInstrFormats.td:61 |
| 1631 | REM_U_I64 = 1616, // WebAssemblyInstrFormats.td:59 |
| 1632 | REM_U_I64_S = 1617, // WebAssemblyInstrFormats.td:61 |
| 1633 | REPLACE_LANE_F16x8 = 1618, // WebAssemblyInstrFormats.td:59 |
| 1634 | REPLACE_LANE_F16x8_S = 1619, // WebAssemblyInstrFormats.td:61 |
| 1635 | REPLACE_LANE_F32x4 = 1620, // WebAssemblyInstrFormats.td:59 |
| 1636 | REPLACE_LANE_F32x4_S = 1621, // WebAssemblyInstrFormats.td:61 |
| 1637 | REPLACE_LANE_F64x2 = 1622, // WebAssemblyInstrFormats.td:59 |
| 1638 | REPLACE_LANE_F64x2_S = 1623, // WebAssemblyInstrFormats.td:61 |
| 1639 | REPLACE_LANE_I16x8 = 1624, // WebAssemblyInstrFormats.td:59 |
| 1640 | REPLACE_LANE_I16x8_S = 1625, // WebAssemblyInstrFormats.td:61 |
| 1641 | REPLACE_LANE_I32x4 = 1626, // WebAssemblyInstrFormats.td:59 |
| 1642 | REPLACE_LANE_I32x4_S = 1627, // WebAssemblyInstrFormats.td:61 |
| 1643 | REPLACE_LANE_I64x2 = 1628, // WebAssemblyInstrFormats.td:59 |
| 1644 | REPLACE_LANE_I64x2_S = 1629, // WebAssemblyInstrFormats.td:61 |
| 1645 | REPLACE_LANE_I8x16 = 1630, // WebAssemblyInstrFormats.td:59 |
| 1646 | REPLACE_LANE_I8x16_S = 1631, // WebAssemblyInstrFormats.td:61 |
| 1647 | RETHROW = 1632, // WebAssemblyInstrFormats.td:59 |
| 1648 | RETHROW_S = 1633, // WebAssemblyInstrFormats.td:61 |
| 1649 | RETURN = 1634, // WebAssemblyInstrFormats.td:59 |
| 1650 | RETURN_S = 1635, // WebAssemblyInstrFormats.td:61 |
| 1651 | RET_CALL = 1636, // WebAssemblyInstrFormats.td:59 |
| 1652 | RET_CALL_INDIRECT = 1637, // WebAssemblyInstrFormats.td:59 |
| 1653 | RET_CALL_INDIRECT_S = 1638, // WebAssemblyInstrFormats.td:61 |
| 1654 | RET_CALL_REF = 1639, // WebAssemblyInstrFormats.td:59 |
| 1655 | RET_CALL_REF_S = 1640, // WebAssemblyInstrFormats.td:61 |
| 1656 | RET_CALL_S = 1641, // WebAssemblyInstrFormats.td:61 |
| 1657 | ROTL_I32 = 1642, // WebAssemblyInstrFormats.td:59 |
| 1658 | ROTL_I32_S = 1643, // WebAssemblyInstrFormats.td:61 |
| 1659 | ROTL_I64 = 1644, // WebAssemblyInstrFormats.td:59 |
| 1660 | ROTL_I64_S = 1645, // WebAssemblyInstrFormats.td:61 |
| 1661 | ROTR_I32 = 1646, // WebAssemblyInstrFormats.td:59 |
| 1662 | ROTR_I32_S = 1647, // WebAssemblyInstrFormats.td:61 |
| 1663 | ROTR_I64 = 1648, // WebAssemblyInstrFormats.td:59 |
| 1664 | ROTR_I64_S = 1649, // WebAssemblyInstrFormats.td:61 |
| 1665 | SELECT_EXNREF = 1650, // WebAssemblyInstrFormats.td:59 |
| 1666 | SELECT_EXNREF_S = 1651, // WebAssemblyInstrFormats.td:61 |
| 1667 | SELECT_EXTERNREF = 1652, // WebAssemblyInstrFormats.td:59 |
| 1668 | SELECT_EXTERNREF_S = 1653, // WebAssemblyInstrFormats.td:61 |
| 1669 | SELECT_F32 = 1654, // WebAssemblyInstrFormats.td:59 |
| 1670 | SELECT_F32_S = 1655, // WebAssemblyInstrFormats.td:61 |
| 1671 | SELECT_F64 = 1656, // WebAssemblyInstrFormats.td:59 |
| 1672 | SELECT_F64_S = 1657, // WebAssemblyInstrFormats.td:61 |
| 1673 | SELECT_FUNCREF = 1658, // WebAssemblyInstrFormats.td:59 |
| 1674 | SELECT_FUNCREF_S = 1659, // WebAssemblyInstrFormats.td:61 |
| 1675 | SELECT_I32 = 1660, // WebAssemblyInstrFormats.td:59 |
| 1676 | SELECT_I32_S = 1661, // WebAssemblyInstrFormats.td:61 |
| 1677 | SELECT_I64 = 1662, // WebAssemblyInstrFormats.td:59 |
| 1678 | SELECT_I64_S = 1663, // WebAssemblyInstrFormats.td:61 |
| 1679 | SELECT_T = 1664, // WebAssemblyInstrFormats.td:59 |
| 1680 | SELECT_T_S = 1665, // WebAssemblyInstrFormats.td:61 |
| 1681 | SELECT_V128 = 1666, // WebAssemblyInstrFormats.td:59 |
| 1682 | SELECT_V128_S = 1667, // WebAssemblyInstrFormats.td:61 |
| 1683 | SHL_I16x8 = 1668, // WebAssemblyInstrFormats.td:59 |
| 1684 | SHL_I16x8_S = 1669, // WebAssemblyInstrFormats.td:61 |
| 1685 | SHL_I32 = 1670, // WebAssemblyInstrFormats.td:59 |
| 1686 | SHL_I32_S = 1671, // WebAssemblyInstrFormats.td:61 |
| 1687 | SHL_I32x4 = 1672, // WebAssemblyInstrFormats.td:59 |
| 1688 | SHL_I32x4_S = 1673, // WebAssemblyInstrFormats.td:61 |
| 1689 | SHL_I64 = 1674, // WebAssemblyInstrFormats.td:59 |
| 1690 | SHL_I64_S = 1675, // WebAssemblyInstrFormats.td:61 |
| 1691 | SHL_I64x2 = 1676, // WebAssemblyInstrFormats.td:59 |
| 1692 | SHL_I64x2_S = 1677, // WebAssemblyInstrFormats.td:61 |
| 1693 | SHL_I8x16 = 1678, // WebAssemblyInstrFormats.td:59 |
| 1694 | SHL_I8x16_S = 1679, // WebAssemblyInstrFormats.td:61 |
| 1695 | SHR_S_I16x8 = 1680, // WebAssemblyInstrFormats.td:59 |
| 1696 | SHR_S_I16x8_S = 1681, // WebAssemblyInstrFormats.td:61 |
| 1697 | SHR_S_I32 = 1682, // WebAssemblyInstrFormats.td:59 |
| 1698 | SHR_S_I32_S = 1683, // WebAssemblyInstrFormats.td:61 |
| 1699 | SHR_S_I32x4 = 1684, // WebAssemblyInstrFormats.td:59 |
| 1700 | SHR_S_I32x4_S = 1685, // WebAssemblyInstrFormats.td:61 |
| 1701 | SHR_S_I64 = 1686, // WebAssemblyInstrFormats.td:59 |
| 1702 | SHR_S_I64_S = 1687, // WebAssemblyInstrFormats.td:61 |
| 1703 | SHR_S_I64x2 = 1688, // WebAssemblyInstrFormats.td:59 |
| 1704 | SHR_S_I64x2_S = 1689, // WebAssemblyInstrFormats.td:61 |
| 1705 | SHR_S_I8x16 = 1690, // WebAssemblyInstrFormats.td:59 |
| 1706 | SHR_S_I8x16_S = 1691, // WebAssemblyInstrFormats.td:61 |
| 1707 | SHR_U_I16x8 = 1692, // WebAssemblyInstrFormats.td:59 |
| 1708 | SHR_U_I16x8_S = 1693, // WebAssemblyInstrFormats.td:61 |
| 1709 | SHR_U_I32 = 1694, // WebAssemblyInstrFormats.td:59 |
| 1710 | SHR_U_I32_S = 1695, // WebAssemblyInstrFormats.td:61 |
| 1711 | SHR_U_I32x4 = 1696, // WebAssemblyInstrFormats.td:59 |
| 1712 | SHR_U_I32x4_S = 1697, // WebAssemblyInstrFormats.td:61 |
| 1713 | SHR_U_I64 = 1698, // WebAssemblyInstrFormats.td:59 |
| 1714 | SHR_U_I64_S = 1699, // WebAssemblyInstrFormats.td:61 |
| 1715 | SHR_U_I64x2 = 1700, // WebAssemblyInstrFormats.td:59 |
| 1716 | SHR_U_I64x2_S = 1701, // WebAssemblyInstrFormats.td:61 |
| 1717 | SHR_U_I8x16 = 1702, // WebAssemblyInstrFormats.td:59 |
| 1718 | SHR_U_I8x16_S = 1703, // WebAssemblyInstrFormats.td:61 |
| 1719 | SHUFFLE = 1704, // WebAssemblyInstrFormats.td:59 |
| 1720 | SHUFFLE_S = 1705, // WebAssemblyInstrFormats.td:61 |
| 1721 | SIMD_RELAXED_FMAX_F32x4 = 1706, // WebAssemblyInstrFormats.td:59 |
| 1722 | SIMD_RELAXED_FMAX_F32x4_S = 1707, // WebAssemblyInstrFormats.td:61 |
| 1723 | SIMD_RELAXED_FMAX_F64x2 = 1708, // WebAssemblyInstrFormats.td:59 |
| 1724 | SIMD_RELAXED_FMAX_F64x2_S = 1709, // WebAssemblyInstrFormats.td:61 |
| 1725 | SIMD_RELAXED_FMIN_F32x4 = 1710, // WebAssemblyInstrFormats.td:59 |
| 1726 | SIMD_RELAXED_FMIN_F32x4_S = 1711, // WebAssemblyInstrFormats.td:61 |
| 1727 | SIMD_RELAXED_FMIN_F64x2 = 1712, // WebAssemblyInstrFormats.td:59 |
| 1728 | SIMD_RELAXED_FMIN_F64x2_S = 1713, // WebAssemblyInstrFormats.td:61 |
| 1729 | SPLAT_F16x8 = 1714, // WebAssemblyInstrFormats.td:59 |
| 1730 | SPLAT_F16x8_S = 1715, // WebAssemblyInstrFormats.td:61 |
| 1731 | SPLAT_F32x4 = 1716, // WebAssemblyInstrFormats.td:59 |
| 1732 | SPLAT_F32x4_S = 1717, // WebAssemblyInstrFormats.td:61 |
| 1733 | SPLAT_F64x2 = 1718, // WebAssemblyInstrFormats.td:59 |
| 1734 | SPLAT_F64x2_S = 1719, // WebAssemblyInstrFormats.td:61 |
| 1735 | SPLAT_I16x8 = 1720, // WebAssemblyInstrFormats.td:59 |
| 1736 | SPLAT_I16x8_S = 1721, // WebAssemblyInstrFormats.td:61 |
| 1737 | SPLAT_I32x4 = 1722, // WebAssemblyInstrFormats.td:59 |
| 1738 | SPLAT_I32x4_S = 1723, // WebAssemblyInstrFormats.td:61 |
| 1739 | SPLAT_I64x2 = 1724, // WebAssemblyInstrFormats.td:59 |
| 1740 | SPLAT_I64x2_S = 1725, // WebAssemblyInstrFormats.td:61 |
| 1741 | SPLAT_I8x16 = 1726, // WebAssemblyInstrFormats.td:59 |
| 1742 | SPLAT_I8x16_S = 1727, // WebAssemblyInstrFormats.td:61 |
| 1743 | SQRT_F16x8 = 1728, // WebAssemblyInstrFormats.td:59 |
| 1744 | SQRT_F16x8_S = 1729, // WebAssemblyInstrFormats.td:61 |
| 1745 | SQRT_F32 = 1730, // WebAssemblyInstrFormats.td:59 |
| 1746 | SQRT_F32_S = 1731, // WebAssemblyInstrFormats.td:61 |
| 1747 | SQRT_F32x4 = 1732, // WebAssemblyInstrFormats.td:59 |
| 1748 | SQRT_F32x4_S = 1733, // WebAssemblyInstrFormats.td:61 |
| 1749 | SQRT_F64 = 1734, // WebAssemblyInstrFormats.td:59 |
| 1750 | SQRT_F64_S = 1735, // WebAssemblyInstrFormats.td:61 |
| 1751 | SQRT_F64x2 = 1736, // WebAssemblyInstrFormats.td:59 |
| 1752 | SQRT_F64x2_S = 1737, // WebAssemblyInstrFormats.td:61 |
| 1753 | STORE16_I32_A32 = 1738, // WebAssemblyInstrFormats.td:59 |
| 1754 | STORE16_I32_A32_S = 1739, // WebAssemblyInstrFormats.td:61 |
| 1755 | STORE16_I32_A64 = 1740, // WebAssemblyInstrFormats.td:59 |
| 1756 | STORE16_I32_A64_S = 1741, // WebAssemblyInstrFormats.td:61 |
| 1757 | STORE16_I64_A32 = 1742, // WebAssemblyInstrFormats.td:59 |
| 1758 | STORE16_I64_A32_S = 1743, // WebAssemblyInstrFormats.td:61 |
| 1759 | STORE16_I64_A64 = 1744, // WebAssemblyInstrFormats.td:59 |
| 1760 | STORE16_I64_A64_S = 1745, // WebAssemblyInstrFormats.td:61 |
| 1761 | STORE32_I64_A32 = 1746, // WebAssemblyInstrFormats.td:59 |
| 1762 | STORE32_I64_A32_S = 1747, // WebAssemblyInstrFormats.td:61 |
| 1763 | STORE32_I64_A64 = 1748, // WebAssemblyInstrFormats.td:59 |
| 1764 | STORE32_I64_A64_S = 1749, // WebAssemblyInstrFormats.td:61 |
| 1765 | STORE8_I32_A32 = 1750, // WebAssemblyInstrFormats.td:59 |
| 1766 | STORE8_I32_A32_S = 1751, // WebAssemblyInstrFormats.td:61 |
| 1767 | STORE8_I32_A64 = 1752, // WebAssemblyInstrFormats.td:59 |
| 1768 | STORE8_I32_A64_S = 1753, // WebAssemblyInstrFormats.td:61 |
| 1769 | STORE8_I64_A32 = 1754, // WebAssemblyInstrFormats.td:59 |
| 1770 | STORE8_I64_A32_S = 1755, // WebAssemblyInstrFormats.td:61 |
| 1771 | STORE8_I64_A64 = 1756, // WebAssemblyInstrFormats.td:59 |
| 1772 | STORE8_I64_A64_S = 1757, // WebAssemblyInstrFormats.td:61 |
| 1773 | STORE_F16_F32_A32 = 1758, // WebAssemblyInstrFormats.td:59 |
| 1774 | STORE_F16_F32_A32_S = 1759, // WebAssemblyInstrFormats.td:61 |
| 1775 | STORE_F16_F32_A64 = 1760, // WebAssemblyInstrFormats.td:59 |
| 1776 | STORE_F16_F32_A64_S = 1761, // WebAssemblyInstrFormats.td:61 |
| 1777 | STORE_F32_A32 = 1762, // WebAssemblyInstrFormats.td:59 |
| 1778 | STORE_F32_A32_S = 1763, // WebAssemblyInstrFormats.td:61 |
| 1779 | STORE_F32_A64 = 1764, // WebAssemblyInstrFormats.td:59 |
| 1780 | STORE_F32_A64_S = 1765, // WebAssemblyInstrFormats.td:61 |
| 1781 | STORE_F64_A32 = 1766, // WebAssemblyInstrFormats.td:59 |
| 1782 | STORE_F64_A32_S = 1767, // WebAssemblyInstrFormats.td:61 |
| 1783 | STORE_F64_A64 = 1768, // WebAssemblyInstrFormats.td:59 |
| 1784 | STORE_F64_A64_S = 1769, // WebAssemblyInstrFormats.td:61 |
| 1785 | STORE_I32_A32 = 1770, // WebAssemblyInstrFormats.td:59 |
| 1786 | STORE_I32_A32_S = 1771, // WebAssemblyInstrFormats.td:61 |
| 1787 | STORE_I32_A64 = 1772, // WebAssemblyInstrFormats.td:59 |
| 1788 | STORE_I32_A64_S = 1773, // WebAssemblyInstrFormats.td:61 |
| 1789 | STORE_I64_A32 = 1774, // WebAssemblyInstrFormats.td:59 |
| 1790 | STORE_I64_A32_S = 1775, // WebAssemblyInstrFormats.td:61 |
| 1791 | STORE_I64_A64 = 1776, // WebAssemblyInstrFormats.td:59 |
| 1792 | STORE_I64_A64_S = 1777, // WebAssemblyInstrFormats.td:61 |
| 1793 | STORE_LANE_I16x8_A32 = 1778, // WebAssemblyInstrFormats.td:59 |
| 1794 | STORE_LANE_I16x8_A32_S = 1779, // WebAssemblyInstrFormats.td:61 |
| 1795 | STORE_LANE_I16x8_A64 = 1780, // WebAssemblyInstrFormats.td:59 |
| 1796 | STORE_LANE_I16x8_A64_S = 1781, // WebAssemblyInstrFormats.td:61 |
| 1797 | STORE_LANE_I32x4_A32 = 1782, // WebAssemblyInstrFormats.td:59 |
| 1798 | STORE_LANE_I32x4_A32_S = 1783, // WebAssemblyInstrFormats.td:61 |
| 1799 | STORE_LANE_I32x4_A64 = 1784, // WebAssemblyInstrFormats.td:59 |
| 1800 | STORE_LANE_I32x4_A64_S = 1785, // WebAssemblyInstrFormats.td:61 |
| 1801 | STORE_LANE_I64x2_A32 = 1786, // WebAssemblyInstrFormats.td:59 |
| 1802 | STORE_LANE_I64x2_A32_S = 1787, // WebAssemblyInstrFormats.td:61 |
| 1803 | STORE_LANE_I64x2_A64 = 1788, // WebAssemblyInstrFormats.td:59 |
| 1804 | STORE_LANE_I64x2_A64_S = 1789, // WebAssemblyInstrFormats.td:61 |
| 1805 | STORE_LANE_I8x16_A32 = 1790, // WebAssemblyInstrFormats.td:59 |
| 1806 | STORE_LANE_I8x16_A32_S = 1791, // WebAssemblyInstrFormats.td:61 |
| 1807 | STORE_LANE_I8x16_A64 = 1792, // WebAssemblyInstrFormats.td:59 |
| 1808 | STORE_LANE_I8x16_A64_S = 1793, // WebAssemblyInstrFormats.td:61 |
| 1809 | STORE_V128_A32 = 1794, // WebAssemblyInstrFormats.td:59 |
| 1810 | STORE_V128_A32_S = 1795, // WebAssemblyInstrFormats.td:61 |
| 1811 | STORE_V128_A64 = 1796, // WebAssemblyInstrFormats.td:59 |
| 1812 | STORE_V128_A64_S = 1797, // WebAssemblyInstrFormats.td:61 |
| 1813 | SUB_F16x8 = 1798, // WebAssemblyInstrFormats.td:59 |
| 1814 | SUB_F16x8_S = 1799, // WebAssemblyInstrFormats.td:61 |
| 1815 | SUB_F32 = 1800, // WebAssemblyInstrFormats.td:59 |
| 1816 | SUB_F32_S = 1801, // WebAssemblyInstrFormats.td:61 |
| 1817 | SUB_F32x4 = 1802, // WebAssemblyInstrFormats.td:59 |
| 1818 | SUB_F32x4_S = 1803, // WebAssemblyInstrFormats.td:61 |
| 1819 | SUB_F64 = 1804, // WebAssemblyInstrFormats.td:59 |
| 1820 | SUB_F64_S = 1805, // WebAssemblyInstrFormats.td:61 |
| 1821 | SUB_F64x2 = 1806, // WebAssemblyInstrFormats.td:59 |
| 1822 | SUB_F64x2_S = 1807, // WebAssemblyInstrFormats.td:61 |
| 1823 | SUB_I16x8 = 1808, // WebAssemblyInstrFormats.td:59 |
| 1824 | SUB_I16x8_S = 1809, // WebAssemblyInstrFormats.td:61 |
| 1825 | SUB_I32 = 1810, // WebAssemblyInstrFormats.td:59 |
| 1826 | SUB_I32_S = 1811, // WebAssemblyInstrFormats.td:61 |
| 1827 | SUB_I32x4 = 1812, // WebAssemblyInstrFormats.td:59 |
| 1828 | SUB_I32x4_S = 1813, // WebAssemblyInstrFormats.td:61 |
| 1829 | SUB_I64 = 1814, // WebAssemblyInstrFormats.td:59 |
| 1830 | SUB_I64_S = 1815, // WebAssemblyInstrFormats.td:61 |
| 1831 | SUB_I64x2 = 1816, // WebAssemblyInstrFormats.td:59 |
| 1832 | SUB_I64x2_S = 1817, // WebAssemblyInstrFormats.td:61 |
| 1833 | SUB_I8x16 = 1818, // WebAssemblyInstrFormats.td:59 |
| 1834 | SUB_I8x16_S = 1819, // WebAssemblyInstrFormats.td:61 |
| 1835 | SUB_SAT_S_I16x8 = 1820, // WebAssemblyInstrFormats.td:59 |
| 1836 | SUB_SAT_S_I16x8_S = 1821, // WebAssemblyInstrFormats.td:61 |
| 1837 | SUB_SAT_S_I8x16 = 1822, // WebAssemblyInstrFormats.td:59 |
| 1838 | SUB_SAT_S_I8x16_S = 1823, // WebAssemblyInstrFormats.td:61 |
| 1839 | SUB_SAT_U_I16x8 = 1824, // WebAssemblyInstrFormats.td:59 |
| 1840 | SUB_SAT_U_I16x8_S = 1825, // WebAssemblyInstrFormats.td:61 |
| 1841 | SUB_SAT_U_I8x16 = 1826, // WebAssemblyInstrFormats.td:59 |
| 1842 | SUB_SAT_U_I8x16_S = 1827, // WebAssemblyInstrFormats.td:61 |
| 1843 | SWIZZLE = 1828, // WebAssemblyInstrFormats.td:59 |
| 1844 | SWIZZLE_S = 1829, // WebAssemblyInstrFormats.td:61 |
| 1845 | TABLE_COPY = 1830, // WebAssemblyInstrFormats.td:59 |
| 1846 | TABLE_COPY_S = 1831, // WebAssemblyInstrFormats.td:61 |
| 1847 | TABLE_FILL_EXNREF = 1832, // WebAssemblyInstrFormats.td:59 |
| 1848 | TABLE_FILL_EXNREF_S = 1833, // WebAssemblyInstrFormats.td:61 |
| 1849 | TABLE_FILL_EXTERNREF = 1834, // WebAssemblyInstrFormats.td:59 |
| 1850 | TABLE_FILL_EXTERNREF_S = 1835, // WebAssemblyInstrFormats.td:61 |
| 1851 | TABLE_FILL_FUNCREF = 1836, // WebAssemblyInstrFormats.td:59 |
| 1852 | TABLE_FILL_FUNCREF_S = 1837, // WebAssemblyInstrFormats.td:61 |
| 1853 | TABLE_GET_EXNREF = 1838, // WebAssemblyInstrFormats.td:59 |
| 1854 | TABLE_GET_EXNREF_S = 1839, // WebAssemblyInstrFormats.td:61 |
| 1855 | TABLE_GET_EXTERNREF = 1840, // WebAssemblyInstrFormats.td:59 |
| 1856 | TABLE_GET_EXTERNREF_S = 1841, // WebAssemblyInstrFormats.td:61 |
| 1857 | TABLE_GET_FUNCREF = 1842, // WebAssemblyInstrFormats.td:59 |
| 1858 | TABLE_GET_FUNCREF_S = 1843, // WebAssemblyInstrFormats.td:61 |
| 1859 | TABLE_GROW_EXNREF = 1844, // WebAssemblyInstrFormats.td:59 |
| 1860 | TABLE_GROW_EXNREF_S = 1845, // WebAssemblyInstrFormats.td:61 |
| 1861 | TABLE_GROW_EXTERNREF = 1846, // WebAssemblyInstrFormats.td:59 |
| 1862 | TABLE_GROW_EXTERNREF_S = 1847, // WebAssemblyInstrFormats.td:61 |
| 1863 | TABLE_GROW_FUNCREF = 1848, // WebAssemblyInstrFormats.td:59 |
| 1864 | TABLE_GROW_FUNCREF_S = 1849, // WebAssemblyInstrFormats.td:61 |
| 1865 | TABLE_SET_EXNREF = 1850, // WebAssemblyInstrFormats.td:59 |
| 1866 | TABLE_SET_EXNREF_S = 1851, // WebAssemblyInstrFormats.td:61 |
| 1867 | TABLE_SET_EXTERNREF = 1852, // WebAssemblyInstrFormats.td:59 |
| 1868 | TABLE_SET_EXTERNREF_S = 1853, // WebAssemblyInstrFormats.td:61 |
| 1869 | TABLE_SET_FUNCREF = 1854, // WebAssemblyInstrFormats.td:59 |
| 1870 | TABLE_SET_FUNCREF_S = 1855, // WebAssemblyInstrFormats.td:61 |
| 1871 | TABLE_SIZE = 1856, // WebAssemblyInstrFormats.td:59 |
| 1872 | TABLE_SIZE_S = 1857, // WebAssemblyInstrFormats.td:61 |
| 1873 | TEE_EXNREF = 1858, // WebAssemblyInstrFormats.td:59 |
| 1874 | TEE_EXNREF_S = 1859, // WebAssemblyInstrFormats.td:61 |
| 1875 | TEE_EXTERNREF = 1860, // WebAssemblyInstrFormats.td:59 |
| 1876 | TEE_EXTERNREF_S = 1861, // WebAssemblyInstrFormats.td:61 |
| 1877 | TEE_F32 = 1862, // WebAssemblyInstrFormats.td:59 |
| 1878 | TEE_F32_S = 1863, // WebAssemblyInstrFormats.td:61 |
| 1879 | TEE_F64 = 1864, // WebAssemblyInstrFormats.td:59 |
| 1880 | TEE_F64_S = 1865, // WebAssemblyInstrFormats.td:61 |
| 1881 | TEE_FUNCREF = 1866, // WebAssemblyInstrFormats.td:59 |
| 1882 | TEE_FUNCREF_S = 1867, // WebAssemblyInstrFormats.td:61 |
| 1883 | TEE_I32 = 1868, // WebAssemblyInstrFormats.td:59 |
| 1884 | TEE_I32_S = 1869, // WebAssemblyInstrFormats.td:61 |
| 1885 | TEE_I64 = 1870, // WebAssemblyInstrFormats.td:59 |
| 1886 | TEE_I64_S = 1871, // WebAssemblyInstrFormats.td:61 |
| 1887 | TEE_V128 = 1872, // WebAssemblyInstrFormats.td:59 |
| 1888 | TEE_V128_S = 1873, // WebAssemblyInstrFormats.td:61 |
| 1889 | THROW = 1874, // WebAssemblyInstrFormats.td:59 |
| 1890 | THROW_REF = 1875, // WebAssemblyInstrFormats.td:59 |
| 1891 | THROW_REF_S = 1876, // WebAssemblyInstrFormats.td:61 |
| 1892 | THROW_S = 1877, // WebAssemblyInstrFormats.td:61 |
| 1893 | TRUNC_F16x8 = 1878, // WebAssemblyInstrFormats.td:59 |
| 1894 | TRUNC_F16x8_S = 1879, // WebAssemblyInstrFormats.td:61 |
| 1895 | TRUNC_F32 = 1880, // WebAssemblyInstrFormats.td:59 |
| 1896 | TRUNC_F32_S = 1881, // WebAssemblyInstrFormats.td:61 |
| 1897 | TRUNC_F32x4 = 1882, // WebAssemblyInstrFormats.td:59 |
| 1898 | TRUNC_F32x4_S = 1883, // WebAssemblyInstrFormats.td:61 |
| 1899 | TRUNC_F64 = 1884, // WebAssemblyInstrFormats.td:59 |
| 1900 | TRUNC_F64_S = 1885, // WebAssemblyInstrFormats.td:61 |
| 1901 | TRUNC_F64x2 = 1886, // WebAssemblyInstrFormats.td:59 |
| 1902 | TRUNC_F64x2_S = 1887, // WebAssemblyInstrFormats.td:61 |
| 1903 | TRY = 1888, // WebAssemblyInstrFormats.td:59 |
| 1904 | TRY_S = 1889, // WebAssemblyInstrFormats.td:61 |
| 1905 | TRY_TABLE = 1890, // WebAssemblyInstrFormats.td:59 |
| 1906 | TRY_TABLE_S = 1891, // WebAssemblyInstrFormats.td:61 |
| 1907 | UNREACHABLE = 1892, // WebAssemblyInstrFormats.td:59 |
| 1908 | UNREACHABLE_S = 1893, // WebAssemblyInstrFormats.td:61 |
| 1909 | XOR = 1894, // WebAssemblyInstrFormats.td:59 |
| 1910 | XOR_I32 = 1895, // WebAssemblyInstrFormats.td:59 |
| 1911 | XOR_I32_S = 1896, // WebAssemblyInstrFormats.td:61 |
| 1912 | XOR_I64 = 1897, // WebAssemblyInstrFormats.td:59 |
| 1913 | XOR_I64_S = 1898, // WebAssemblyInstrFormats.td:61 |
| 1914 | XOR_S = 1899, // WebAssemblyInstrFormats.td:61 |
| 1915 | anonymous_14793MEMORY_GROW_A32 = 1900, // WebAssemblyInstrFormats.td:59 |
| 1916 | anonymous_14793MEMORY_GROW_A32_S = 1901, // WebAssemblyInstrFormats.td:61 |
| 1917 | anonymous_14793MEMORY_SIZE_A32 = 1902, // WebAssemblyInstrFormats.td:59 |
| 1918 | anonymous_14793MEMORY_SIZE_A32_S = 1903, // WebAssemblyInstrFormats.td:61 |
| 1919 | anonymous_14794MEMORY_GROW_A64 = 1904, // WebAssemblyInstrFormats.td:59 |
| 1920 | anonymous_14794MEMORY_GROW_A64_S = 1905, // WebAssemblyInstrFormats.td:61 |
| 1921 | anonymous_14794MEMORY_SIZE_A64 = 1906, // WebAssemblyInstrFormats.td:59 |
| 1922 | anonymous_14794MEMORY_SIZE_A64_S = 1907, // WebAssemblyInstrFormats.td:61 |
| 1923 | convert_low_s_F64x2 = 1908, // WebAssemblyInstrFormats.td:59 |
| 1924 | convert_low_s_F64x2_S = 1909, // WebAssemblyInstrFormats.td:61 |
| 1925 | convert_low_u_F64x2 = 1910, // WebAssemblyInstrFormats.td:59 |
| 1926 | convert_low_u_F64x2_S = 1911, // WebAssemblyInstrFormats.td:61 |
| 1927 | demote_zero_F16x8 = 1912, // WebAssemblyInstrFormats.td:59 |
| 1928 | demote_zero_F16x8_S = 1913, // WebAssemblyInstrFormats.td:61 |
| 1929 | demote_zero_F32x4 = 1914, // WebAssemblyInstrFormats.td:59 |
| 1930 | demote_zero_F32x4_S = 1915, // WebAssemblyInstrFormats.td:61 |
| 1931 | extadd_pairwise_s_I16x8 = 1916, // WebAssemblyInstrFormats.td:59 |
| 1932 | extadd_pairwise_s_I16x8_S = 1917, // WebAssemblyInstrFormats.td:61 |
| 1933 | extadd_pairwise_s_I32x4 = 1918, // WebAssemblyInstrFormats.td:59 |
| 1934 | extadd_pairwise_s_I32x4_S = 1919, // WebAssemblyInstrFormats.td:61 |
| 1935 | extadd_pairwise_u_I16x8 = 1920, // WebAssemblyInstrFormats.td:59 |
| 1936 | extadd_pairwise_u_I16x8_S = 1921, // WebAssemblyInstrFormats.td:61 |
| 1937 | extadd_pairwise_u_I32x4 = 1922, // WebAssemblyInstrFormats.td:59 |
| 1938 | extadd_pairwise_u_I32x4_S = 1923, // WebAssemblyInstrFormats.td:61 |
| 1939 | extend_high_s_I16x8 = 1924, // WebAssemblyInstrFormats.td:59 |
| 1940 | extend_high_s_I16x8_S = 1925, // WebAssemblyInstrFormats.td:61 |
| 1941 | extend_high_s_I32x4 = 1926, // WebAssemblyInstrFormats.td:59 |
| 1942 | extend_high_s_I32x4_S = 1927, // WebAssemblyInstrFormats.td:61 |
| 1943 | extend_high_s_I64x2 = 1928, // WebAssemblyInstrFormats.td:59 |
| 1944 | extend_high_s_I64x2_S = 1929, // WebAssemblyInstrFormats.td:61 |
| 1945 | extend_high_u_I16x8 = 1930, // WebAssemblyInstrFormats.td:59 |
| 1946 | extend_high_u_I16x8_S = 1931, // WebAssemblyInstrFormats.td:61 |
| 1947 | extend_high_u_I32x4 = 1932, // WebAssemblyInstrFormats.td:59 |
| 1948 | extend_high_u_I32x4_S = 1933, // WebAssemblyInstrFormats.td:61 |
| 1949 | extend_high_u_I64x2 = 1934, // WebAssemblyInstrFormats.td:59 |
| 1950 | extend_high_u_I64x2_S = 1935, // WebAssemblyInstrFormats.td:61 |
| 1951 | extend_low_s_I16x8 = 1936, // WebAssemblyInstrFormats.td:59 |
| 1952 | extend_low_s_I16x8_S = 1937, // WebAssemblyInstrFormats.td:61 |
| 1953 | extend_low_s_I32x4 = 1938, // WebAssemblyInstrFormats.td:59 |
| 1954 | extend_low_s_I32x4_S = 1939, // WebAssemblyInstrFormats.td:61 |
| 1955 | extend_low_s_I64x2 = 1940, // WebAssemblyInstrFormats.td:59 |
| 1956 | extend_low_s_I64x2_S = 1941, // WebAssemblyInstrFormats.td:61 |
| 1957 | extend_low_u_I16x8 = 1942, // WebAssemblyInstrFormats.td:59 |
| 1958 | extend_low_u_I16x8_S = 1943, // WebAssemblyInstrFormats.td:61 |
| 1959 | extend_low_u_I32x4 = 1944, // WebAssemblyInstrFormats.td:59 |
| 1960 | extend_low_u_I32x4_S = 1945, // WebAssemblyInstrFormats.td:61 |
| 1961 | extend_low_u_I64x2 = 1946, // WebAssemblyInstrFormats.td:59 |
| 1962 | extend_low_u_I64x2_S = 1947, // WebAssemblyInstrFormats.td:61 |
| 1963 | fp_to_sint_I16x8 = 1948, // WebAssemblyInstrFormats.td:59 |
| 1964 | fp_to_sint_I16x8_S = 1949, // WebAssemblyInstrFormats.td:61 |
| 1965 | fp_to_sint_I32x4 = 1950, // WebAssemblyInstrFormats.td:59 |
| 1966 | fp_to_sint_I32x4_S = 1951, // WebAssemblyInstrFormats.td:61 |
| 1967 | fp_to_uint_I16x8 = 1952, // WebAssemblyInstrFormats.td:59 |
| 1968 | fp_to_uint_I16x8_S = 1953, // WebAssemblyInstrFormats.td:61 |
| 1969 | fp_to_uint_I32x4 = 1954, // WebAssemblyInstrFormats.td:59 |
| 1970 | fp_to_uint_I32x4_S = 1955, // WebAssemblyInstrFormats.td:61 |
| 1971 | int_wasm_relaxed_trunc_signed_I32x4 = 1956, // WebAssemblyInstrFormats.td:59 |
| 1972 | int_wasm_relaxed_trunc_signed_I32x4_S = 1957, // WebAssemblyInstrFormats.td:61 |
| 1973 | int_wasm_relaxed_trunc_signed_zero_I32x4 = 1958, // WebAssemblyInstrFormats.td:59 |
| 1974 | int_wasm_relaxed_trunc_signed_zero_I32x4_S = 1959, // WebAssemblyInstrFormats.td:61 |
| 1975 | int_wasm_relaxed_trunc_unsigned_I32x4 = 1960, // WebAssemblyInstrFormats.td:59 |
| 1976 | int_wasm_relaxed_trunc_unsigned_I32x4_S = 1961, // WebAssemblyInstrFormats.td:61 |
| 1977 | int_wasm_relaxed_trunc_unsigned_zero_I32x4 = 1962, // WebAssemblyInstrFormats.td:59 |
| 1978 | int_wasm_relaxed_trunc_unsigned_zero_I32x4_S = 1963, // WebAssemblyInstrFormats.td:61 |
| 1979 | promote_low_F32x4 = 1964, // WebAssemblyInstrFormats.td:59 |
| 1980 | promote_low_F32x4_S = 1965, // WebAssemblyInstrFormats.td:61 |
| 1981 | promote_low_F64x2 = 1966, // WebAssemblyInstrFormats.td:59 |
| 1982 | promote_low_F64x2_S = 1967, // WebAssemblyInstrFormats.td:61 |
| 1983 | sint_to_fp_F16x8 = 1968, // WebAssemblyInstrFormats.td:59 |
| 1984 | sint_to_fp_F16x8_S = 1969, // WebAssemblyInstrFormats.td:61 |
| 1985 | sint_to_fp_F32x4 = 1970, // WebAssemblyInstrFormats.td:59 |
| 1986 | sint_to_fp_F32x4_S = 1971, // WebAssemblyInstrFormats.td:61 |
| 1987 | trunc_sat_zero_s_I32x4 = 1972, // WebAssemblyInstrFormats.td:59 |
| 1988 | trunc_sat_zero_s_I32x4_S = 1973, // WebAssemblyInstrFormats.td:61 |
| 1989 | trunc_sat_zero_u_I32x4 = 1974, // WebAssemblyInstrFormats.td:59 |
| 1990 | trunc_sat_zero_u_I32x4_S = 1975, // WebAssemblyInstrFormats.td:61 |
| 1991 | uint_to_fp_F16x8 = 1976, // WebAssemblyInstrFormats.td:59 |
| 1992 | uint_to_fp_F16x8_S = 1977, // WebAssemblyInstrFormats.td:61 |
| 1993 | uint_to_fp_F32x4 = 1978, // WebAssemblyInstrFormats.td:59 |
| 1994 | uint_to_fp_F32x4_S = 1979, // WebAssemblyInstrFormats.td:61 |
| 1995 | INSTRUCTION_LIST_END = 1980 |
| 1996 | }; |
| 1997 | enum RegClassByHwModeUses : uint16_t { |
| 1998 | wasm_ptr_rc, |
| 1999 | }; |
| 2000 | |
| 2001 | } // namespace llvm::WebAssembly |
| 2002 | |
| 2003 | #endif // GET_INSTRINFO_ENUM |
| 2004 | |
| 2005 | #ifdef GET_INSTRINFO_SCHED_ENUM |
| 2006 | #undef GET_INSTRINFO_SCHED_ENUM |
| 2007 | |
| 2008 | namespace llvm::WebAssembly::Sched { |
| 2009 | |
| 2010 | enum { |
| 2011 | NoInstrModel = 0, |
| 2012 | SCHED_LIST_END = 1 |
| 2013 | }; |
| 2014 | |
| 2015 | } // namespace llvm::WebAssembly::Sched |
| 2016 | |
| 2017 | #endif // GET_INSTRINFO_SCHED_ENUM |
| 2018 | |
| 2019 | #if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR) |
| 2020 | |
| 2021 | namespace llvm { |
| 2022 | |
| 2023 | struct WebAssemblyInstrTable { |
| 2024 | MCInstrDesc Insts[1980]; |
| 2025 | static_assert(alignof(MCInstrDesc) >= alignof(MCPhysReg), "Unwanted padding between Insts and ImplicitOps"); |
| 2026 | MCPhysReg ImplicitOps[10]; |
| 2027 | char Padding[sizeof(MCOperandInfo) - sizeof ImplicitOps % sizeof(MCOperandInfo)]; |
| 2028 | static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo"); |
| 2029 | MCOperandInfo OperandInfo[890]; |
| 2030 | }; |
| 2031 | } // namespace llvm |
| 2032 | |
| 2033 | #endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR) |
| 2034 | |
| 2035 | #ifdef GET_INSTRINFO_MC_DESC |
| 2036 | #undef GET_INSTRINFO_MC_DESC |
| 2037 | |
| 2038 | namespace llvm { |
| 2039 | |
| 2040 | static_assert((sizeof WebAssemblyInstrTable::ImplicitOps + sizeof WebAssemblyInstrTable::Padding) % sizeof(MCOperandInfo) == 0); |
| 2041 | static constexpr unsigned WebAssemblyOpInfoBase = (sizeof WebAssemblyInstrTable::ImplicitOps + sizeof WebAssemblyInstrTable::Padding) / sizeof(MCOperandInfo); |
| 2042 | |
| 2043 | extern const WebAssemblyInstrTable WebAssemblyDescs = { |
| 2044 | { |
| 2045 | { 1979, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // uint_to_fp_F32x4_S |
| 2046 | { 1978, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // uint_to_fp_F32x4 |
| 2047 | { 1977, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // uint_to_fp_F16x8_S |
| 2048 | { 1976, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // uint_to_fp_F16x8 |
| 2049 | { 1975, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // trunc_sat_zero_u_I32x4_S |
| 2050 | { 1974, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // trunc_sat_zero_u_I32x4 |
| 2051 | { 1973, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // trunc_sat_zero_s_I32x4_S |
| 2052 | { 1972, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // trunc_sat_zero_s_I32x4 |
| 2053 | { 1971, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // sint_to_fp_F32x4_S |
| 2054 | { 1970, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // sint_to_fp_F32x4 |
| 2055 | { 1969, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // sint_to_fp_F16x8_S |
| 2056 | { 1968, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // sint_to_fp_F16x8 |
| 2057 | { 1967, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // promote_low_F64x2_S |
| 2058 | { 1966, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // promote_low_F64x2 |
| 2059 | { 1965, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // promote_low_F32x4_S |
| 2060 | { 1964, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // promote_low_F32x4 |
| 2061 | { 1963, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // int_wasm_relaxed_trunc_unsigned_zero_I32x4_S |
| 2062 | { 1962, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // int_wasm_relaxed_trunc_unsigned_zero_I32x4 |
| 2063 | { 1961, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // int_wasm_relaxed_trunc_unsigned_I32x4_S |
| 2064 | { 1960, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // int_wasm_relaxed_trunc_unsigned_I32x4 |
| 2065 | { 1959, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // int_wasm_relaxed_trunc_signed_zero_I32x4_S |
| 2066 | { 1958, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // int_wasm_relaxed_trunc_signed_zero_I32x4 |
| 2067 | { 1957, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // int_wasm_relaxed_trunc_signed_I32x4_S |
| 2068 | { 1956, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // int_wasm_relaxed_trunc_signed_I32x4 |
| 2069 | { 1955, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // fp_to_uint_I32x4_S |
| 2070 | { 1954, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // fp_to_uint_I32x4 |
| 2071 | { 1953, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // fp_to_uint_I16x8_S |
| 2072 | { 1952, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // fp_to_uint_I16x8 |
| 2073 | { 1951, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // fp_to_sint_I32x4_S |
| 2074 | { 1950, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // fp_to_sint_I32x4 |
| 2075 | { 1949, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // fp_to_sint_I16x8_S |
| 2076 | { 1948, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // fp_to_sint_I16x8 |
| 2077 | { 1947, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_low_u_I64x2_S |
| 2078 | { 1946, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_low_u_I64x2 |
| 2079 | { 1945, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_low_u_I32x4_S |
| 2080 | { 1944, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_low_u_I32x4 |
| 2081 | { 1943, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_low_u_I16x8_S |
| 2082 | { 1942, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_low_u_I16x8 |
| 2083 | { 1941, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_low_s_I64x2_S |
| 2084 | { 1940, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_low_s_I64x2 |
| 2085 | { 1939, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_low_s_I32x4_S |
| 2086 | { 1938, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_low_s_I32x4 |
| 2087 | { 1937, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_low_s_I16x8_S |
| 2088 | { 1936, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_low_s_I16x8 |
| 2089 | { 1935, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_high_u_I64x2_S |
| 2090 | { 1934, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_high_u_I64x2 |
| 2091 | { 1933, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_high_u_I32x4_S |
| 2092 | { 1932, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_high_u_I32x4 |
| 2093 | { 1931, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_high_u_I16x8_S |
| 2094 | { 1930, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_high_u_I16x8 |
| 2095 | { 1929, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_high_s_I64x2_S |
| 2096 | { 1928, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_high_s_I64x2 |
| 2097 | { 1927, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_high_s_I32x4_S |
| 2098 | { 1926, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_high_s_I32x4 |
| 2099 | { 1925, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_high_s_I16x8_S |
| 2100 | { 1924, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_high_s_I16x8 |
| 2101 | { 1923, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extadd_pairwise_u_I32x4_S |
| 2102 | { 1922, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extadd_pairwise_u_I32x4 |
| 2103 | { 1921, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extadd_pairwise_u_I16x8_S |
| 2104 | { 1920, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extadd_pairwise_u_I16x8 |
| 2105 | { 1919, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extadd_pairwise_s_I32x4_S |
| 2106 | { 1918, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extadd_pairwise_s_I32x4 |
| 2107 | { 1917, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extadd_pairwise_s_I16x8_S |
| 2108 | { 1916, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extadd_pairwise_s_I16x8 |
| 2109 | { 1915, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // demote_zero_F32x4_S |
| 2110 | { 1914, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // demote_zero_F32x4 |
| 2111 | { 1913, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // demote_zero_F16x8_S |
| 2112 | { 1912, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // demote_zero_F16x8 |
| 2113 | { 1911, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // convert_low_u_F64x2_S |
| 2114 | { 1910, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // convert_low_u_F64x2 |
| 2115 | { 1909, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // convert_low_s_F64x2_S |
| 2116 | { 1908, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // convert_low_s_F64x2 |
| 2117 | { 1907, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14794MEMORY_SIZE_A64_S |
| 2118 | { 1906, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 190, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14794MEMORY_SIZE_A64 |
| 2119 | { 1905, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14794MEMORY_GROW_A64_S |
| 2120 | { 1904, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 887, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14794MEMORY_GROW_A64 |
| 2121 | { 1903, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14793MEMORY_SIZE_A32_S |
| 2122 | { 1902, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 188, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14793MEMORY_SIZE_A32 |
| 2123 | { 1901, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14793MEMORY_GROW_A32_S |
| 2124 | { 1900, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 884, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14793MEMORY_GROW_A32 |
| 2125 | { 1899, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_S |
| 2126 | { 1898, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_I64_S |
| 2127 | { 1897, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_I64 |
| 2128 | { 1896, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_I32_S |
| 2129 | { 1895, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_I32 |
| 2130 | { 1894, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR |
| 2131 | { 1893, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Trap)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // UNREACHABLE_S |
| 2132 | { 1892, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Trap)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // UNREACHABLE |
| 2133 | { 1891, 2, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 882, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRY_TABLE_S |
| 2134 | { 1890, 1, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 297, 8, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRY_TABLE |
| 2135 | { 1889, 1, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 297, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRY_S |
| 2136 | { 1888, 1, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 297, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRY |
| 2137 | { 1887, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRUNC_F64x2_S |
| 2138 | { 1886, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRUNC_F64x2 |
| 2139 | { 1885, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRUNC_F64_S |
| 2140 | { 1884, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRUNC_F64 |
| 2141 | { 1883, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRUNC_F32x4_S |
| 2142 | { 1882, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRUNC_F32x4 |
| 2143 | { 1881, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRUNC_F32_S |
| 2144 | { 1880, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 157, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRUNC_F32 |
| 2145 | { 1879, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRUNC_F16x8_S |
| 2146 | { 1878, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRUNC_F16x8 |
| 2147 | { 1877, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 308, 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // THROW_S |
| 2148 | { 1876, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // THROW_REF_S |
| 2149 | { 1875, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 309, 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // THROW_REF |
| 2150 | { 1874, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 308, 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // THROW |
| 2151 | { 1873, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_V128_S |
| 2152 | { 1872, 3, 2, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_V128 |
| 2153 | { 1871, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_I64_S |
| 2154 | { 1870, 3, 2, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_I64 |
| 2155 | { 1869, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_I32_S |
| 2156 | { 1868, 3, 2, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_I32 |
| 2157 | { 1867, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_FUNCREF_S |
| 2158 | { 1866, 3, 2, 0, 0, 0, 1, WebAssemblyOpInfoBase + 879, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_FUNCREF |
| 2159 | { 1865, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_F64_S |
| 2160 | { 1864, 3, 2, 0, 0, 0, 1, WebAssemblyOpInfoBase + 167, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_F64 |
| 2161 | { 1863, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_F32_S |
| 2162 | { 1862, 3, 2, 0, 0, 0, 1, WebAssemblyOpInfoBase + 164, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_F32 |
| 2163 | { 1861, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_EXTERNREF_S |
| 2164 | { 1860, 3, 2, 0, 0, 0, 1, WebAssemblyOpInfoBase + 876, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_EXTERNREF |
| 2165 | { 1859, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_EXNREF_S |
| 2166 | { 1858, 3, 2, 0, 0, 0, 1, WebAssemblyOpInfoBase + 873, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_EXNREF |
| 2167 | { 1857, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 832, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_SIZE_S |
| 2168 | { 1856, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 871, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_SIZE |
| 2169 | { 1855, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 832, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_SET_FUNCREF_S |
| 2170 | { 1854, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 868, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_SET_FUNCREF |
| 2171 | { 1853, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 832, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_SET_EXTERNREF_S |
| 2172 | { 1852, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 865, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_SET_EXTERNREF |
| 2173 | { 1851, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 832, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_SET_EXNREF_S |
| 2174 | { 1850, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 862, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_SET_EXNREF |
| 2175 | { 1849, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 832, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_GROW_FUNCREF_S |
| 2176 | { 1848, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 858, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_GROW_FUNCREF |
| 2177 | { 1847, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 832, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_GROW_EXTERNREF_S |
| 2178 | { 1846, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 854, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_GROW_EXTERNREF |
| 2179 | { 1845, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 832, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_GROW_EXNREF_S |
| 2180 | { 1844, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 850, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_GROW_EXNREF |
| 2181 | { 1843, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 832, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_GET_FUNCREF_S |
| 2182 | { 1842, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 847, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_GET_FUNCREF |
| 2183 | { 1841, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 832, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_GET_EXTERNREF_S |
| 2184 | { 1840, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 844, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_GET_EXTERNREF |
| 2185 | { 1839, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 832, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_GET_EXNREF_S |
| 2186 | { 1838, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 841, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_GET_EXNREF |
| 2187 | { 1837, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 832, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_FILL_FUNCREF_S |
| 2188 | { 1836, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 837, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_FILL_FUNCREF |
| 2189 | { 1835, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 832, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_FILL_EXTERNREF_S |
| 2190 | { 1834, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 833, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_FILL_EXTERNREF |
| 2191 | { 1833, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 832, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_FILL_EXNREF_S |
| 2192 | { 1832, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 828, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_FILL_EXNREF |
| 2193 | { 1831, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 826, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_COPY_S |
| 2194 | { 1830, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 821, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_COPY |
| 2195 | { 1829, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SWIZZLE_S |
| 2196 | { 1828, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SWIZZLE |
| 2197 | { 1827, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_SAT_U_I8x16_S |
| 2198 | { 1826, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_SAT_U_I8x16 |
| 2199 | { 1825, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_SAT_U_I16x8_S |
| 2200 | { 1824, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_SAT_U_I16x8 |
| 2201 | { 1823, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_SAT_S_I8x16_S |
| 2202 | { 1822, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_SAT_S_I8x16 |
| 2203 | { 1821, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_SAT_S_I16x8_S |
| 2204 | { 1820, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_SAT_S_I16x8 |
| 2205 | { 1819, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I8x16_S |
| 2206 | { 1818, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I8x16 |
| 2207 | { 1817, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I64x2_S |
| 2208 | { 1816, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I64x2 |
| 2209 | { 1815, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I64_S |
| 2210 | { 1814, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I64 |
| 2211 | { 1813, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I32x4_S |
| 2212 | { 1812, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I32x4 |
| 2213 | { 1811, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I32_S |
| 2214 | { 1810, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I32 |
| 2215 | { 1809, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I16x8_S |
| 2216 | { 1808, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I16x8 |
| 2217 | { 1807, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F64x2_S |
| 2218 | { 1806, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F64x2 |
| 2219 | { 1805, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F64_S |
| 2220 | { 1804, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 167, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F64 |
| 2221 | { 1803, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F32x4_S |
| 2222 | { 1802, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F32x4 |
| 2223 | { 1801, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F32_S |
| 2224 | { 1800, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 164, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F32 |
| 2225 | { 1799, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F16x8_S |
| 2226 | { 1798, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F16x8 |
| 2227 | { 1797, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_V128_A64_S |
| 2228 | { 1796, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 817, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_V128_A64 |
| 2229 | { 1795, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_V128_A32_S |
| 2230 | { 1794, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 813, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_V128_A32 |
| 2231 | { 1793, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 565, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I8x16_A64_S |
| 2232 | { 1792, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 808, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I8x16_A64 |
| 2233 | { 1791, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 556, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I8x16_A32_S |
| 2234 | { 1790, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 803, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I8x16_A32 |
| 2235 | { 1789, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 565, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I64x2_A64_S |
| 2236 | { 1788, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 808, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I64x2_A64 |
| 2237 | { 1787, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 556, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I64x2_A32_S |
| 2238 | { 1786, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 803, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I64x2_A32 |
| 2239 | { 1785, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 565, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I32x4_A64_S |
| 2240 | { 1784, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 808, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I32x4_A64 |
| 2241 | { 1783, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 556, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I32x4_A32_S |
| 2242 | { 1782, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 803, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I32x4_A32 |
| 2243 | { 1781, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 565, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I16x8_A64_S |
| 2244 | { 1780, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 808, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I16x8_A64 |
| 2245 | { 1779, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 556, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I16x8_A32_S |
| 2246 | { 1778, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 803, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I16x8_A32 |
| 2247 | { 1777, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_I64_A64_S |
| 2248 | { 1776, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 783, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_I64_A64 |
| 2249 | { 1775, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_I64_A32_S |
| 2250 | { 1774, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 779, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_I64_A32 |
| 2251 | { 1773, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_I32_A64_S |
| 2252 | { 1772, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 775, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_I32_A64 |
| 2253 | { 1771, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_I32_A32_S |
| 2254 | { 1770, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 771, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_I32_A32 |
| 2255 | { 1769, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_F64_A64_S |
| 2256 | { 1768, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 799, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_F64_A64 |
| 2257 | { 1767, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_F64_A32_S |
| 2258 | { 1766, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 795, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_F64_A32 |
| 2259 | { 1765, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_F32_A64_S |
| 2260 | { 1764, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 791, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_F32_A64 |
| 2261 | { 1763, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_F32_A32_S |
| 2262 | { 1762, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 787, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_F32_A32 |
| 2263 | { 1761, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_F16_F32_A64_S |
| 2264 | { 1760, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 791, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_F16_F32_A64 |
| 2265 | { 1759, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_F16_F32_A32_S |
| 2266 | { 1758, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 787, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_F16_F32_A32 |
| 2267 | { 1757, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE8_I64_A64_S |
| 2268 | { 1756, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 783, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE8_I64_A64 |
| 2269 | { 1755, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE8_I64_A32_S |
| 2270 | { 1754, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 779, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE8_I64_A32 |
| 2271 | { 1753, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE8_I32_A64_S |
| 2272 | { 1752, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 775, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE8_I32_A64 |
| 2273 | { 1751, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE8_I32_A32_S |
| 2274 | { 1750, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 771, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE8_I32_A32 |
| 2275 | { 1749, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE32_I64_A64_S |
| 2276 | { 1748, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 783, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE32_I64_A64 |
| 2277 | { 1747, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE32_I64_A32_S |
| 2278 | { 1746, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 779, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE32_I64_A32 |
| 2279 | { 1745, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE16_I64_A64_S |
| 2280 | { 1744, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 783, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE16_I64_A64 |
| 2281 | { 1743, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE16_I64_A32_S |
| 2282 | { 1742, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 779, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE16_I64_A32 |
| 2283 | { 1741, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE16_I32_A64_S |
| 2284 | { 1740, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 775, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE16_I32_A64 |
| 2285 | { 1739, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE16_I32_A32_S |
| 2286 | { 1738, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 771, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE16_I32_A32 |
| 2287 | { 1737, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SQRT_F64x2_S |
| 2288 | { 1736, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SQRT_F64x2 |
| 2289 | { 1735, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SQRT_F64_S |
| 2290 | { 1734, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SQRT_F64 |
| 2291 | { 1733, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SQRT_F32x4_S |
| 2292 | { 1732, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SQRT_F32x4 |
| 2293 | { 1731, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SQRT_F32_S |
| 2294 | { 1730, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 157, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SQRT_F32 |
| 2295 | { 1729, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SQRT_F16x8_S |
| 2296 | { 1728, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SQRT_F16x8 |
| 2297 | { 1727, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_I8x16_S |
| 2298 | { 1726, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 767, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_I8x16 |
| 2299 | { 1725, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_I64x2_S |
| 2300 | { 1724, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 769, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_I64x2 |
| 2301 | { 1723, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_I32x4_S |
| 2302 | { 1722, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 767, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_I32x4 |
| 2303 | { 1721, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_I16x8_S |
| 2304 | { 1720, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 767, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_I16x8 |
| 2305 | { 1719, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_F64x2_S |
| 2306 | { 1718, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 765, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_F64x2 |
| 2307 | { 1717, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_F32x4_S |
| 2308 | { 1716, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 763, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_F32x4 |
| 2309 | { 1715, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_F16x8_S |
| 2310 | { 1714, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 763, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_F16x8 |
| 2311 | { 1713, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SIMD_RELAXED_FMIN_F64x2_S |
| 2312 | { 1712, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SIMD_RELAXED_FMIN_F64x2 |
| 2313 | { 1711, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SIMD_RELAXED_FMIN_F32x4_S |
| 2314 | { 1710, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SIMD_RELAXED_FMIN_F32x4 |
| 2315 | { 1709, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SIMD_RELAXED_FMAX_F64x2_S |
| 2316 | { 1708, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SIMD_RELAXED_FMAX_F64x2 |
| 2317 | { 1707, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SIMD_RELAXED_FMAX_F32x4_S |
| 2318 | { 1706, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SIMD_RELAXED_FMAX_F32x4 |
| 2319 | { 1705, 16, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 388, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHUFFLE_S |
| 2320 | { 1704, 19, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 744, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHUFFLE |
| 2321 | { 1703, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_U_I8x16_S |
| 2322 | { 1702, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 741, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_U_I8x16 |
| 2323 | { 1701, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_U_I64x2_S |
| 2324 | { 1700, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 741, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_U_I64x2 |
| 2325 | { 1699, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_U_I64_S |
| 2326 | { 1698, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_U_I64 |
| 2327 | { 1697, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_U_I32x4_S |
| 2328 | { 1696, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 741, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_U_I32x4 |
| 2329 | { 1695, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_U_I32_S |
| 2330 | { 1694, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_U_I32 |
| 2331 | { 1693, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_U_I16x8_S |
| 2332 | { 1692, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 741, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_U_I16x8 |
| 2333 | { 1691, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_S_I8x16_S |
| 2334 | { 1690, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 741, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_S_I8x16 |
| 2335 | { 1689, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_S_I64x2_S |
| 2336 | { 1688, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 741, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_S_I64x2 |
| 2337 | { 1687, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_S_I64_S |
| 2338 | { 1686, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_S_I64 |
| 2339 | { 1685, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_S_I32x4_S |
| 2340 | { 1684, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 741, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_S_I32x4 |
| 2341 | { 1683, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_S_I32_S |
| 2342 | { 1682, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_S_I32 |
| 2343 | { 1681, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_S_I16x8_S |
| 2344 | { 1680, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 741, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_S_I16x8 |
| 2345 | { 1679, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_I8x16_S |
| 2346 | { 1678, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 741, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_I8x16 |
| 2347 | { 1677, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_I64x2_S |
| 2348 | { 1676, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 741, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_I64x2 |
| 2349 | { 1675, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_I64_S |
| 2350 | { 1674, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_I64 |
| 2351 | { 1673, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_I32x4_S |
| 2352 | { 1672, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 741, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_I32x4 |
| 2353 | { 1671, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_I32_S |
| 2354 | { 1670, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_I32 |
| 2355 | { 1669, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_I16x8_S |
| 2356 | { 1668, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 741, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_I16x8 |
| 2357 | { 1667, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_V128_S |
| 2358 | { 1666, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 737, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_V128 |
| 2359 | { 1665, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 736, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_T_S |
| 2360 | { 1664, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 736, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_T |
| 2361 | { 1663, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_I64_S |
| 2362 | { 1662, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 732, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_I64 |
| 2363 | { 1661, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_I32_S |
| 2364 | { 1660, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 728, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_I32 |
| 2365 | { 1659, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_FUNCREF_S |
| 2366 | { 1658, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 724, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_FUNCREF |
| 2367 | { 1657, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_F64_S |
| 2368 | { 1656, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 720, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_F64 |
| 2369 | { 1655, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_F32_S |
| 2370 | { 1654, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 716, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_F32 |
| 2371 | { 1653, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_EXTERNREF_S |
| 2372 | { 1652, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 712, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_EXTERNREF |
| 2373 | { 1651, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_EXNREF_S |
| 2374 | { 1650, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 708, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_EXNREF |
| 2375 | { 1649, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ROTR_I64_S |
| 2376 | { 1648, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ROTR_I64 |
| 2377 | { 1647, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ROTR_I32_S |
| 2378 | { 1646, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ROTR_I32 |
| 2379 | { 1645, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ROTL_I64_S |
| 2380 | { 1644, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ROTL_I64 |
| 2381 | { 1643, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ROTL_I32_S |
| 2382 | { 1642, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ROTL_I32 |
| 2383 | { 1641, 1, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 151, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RET_CALL_S |
| 2384 | { 1640, 1, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 307, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RET_CALL_REF_S |
| 2385 | { 1639, 2, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 305, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RET_CALL_REF |
| 2386 | { 1638, 2, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 303, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RET_CALL_INDIRECT_S |
| 2387 | { 1637, 2, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 303, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RET_CALL_INDIRECT |
| 2388 | { 1636, 1, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 151, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RET_CALL |
| 2389 | { 1635, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RETURN_S |
| 2390 | { 1634, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RETURN |
| 2391 | { 1633, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 154, 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RETHROW_S |
| 2392 | { 1632, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 154, 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RETHROW |
| 2393 | { 1631, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 429, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_I8x16_S |
| 2394 | { 1630, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 700, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_I8x16 |
| 2395 | { 1629, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 429, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_I64x2_S |
| 2396 | { 1628, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 704, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_I64x2 |
| 2397 | { 1627, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 429, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_I32x4_S |
| 2398 | { 1626, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 700, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_I32x4 |
| 2399 | { 1625, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 429, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_I16x8_S |
| 2400 | { 1624, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 700, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_I16x8 |
| 2401 | { 1623, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 429, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_F64x2_S |
| 2402 | { 1622, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 696, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_F64x2 |
| 2403 | { 1621, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 429, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_F32x4_S |
| 2404 | { 1620, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 692, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_F32x4 |
| 2405 | { 1619, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 429, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_F16x8_S |
| 2406 | { 1618, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 692, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_F16x8 |
| 2407 | { 1617, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REM_U_I64_S |
| 2408 | { 1616, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REM_U_I64 |
| 2409 | { 1615, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REM_U_I32_S |
| 2410 | { 1614, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REM_U_I32 |
| 2411 | { 1613, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REM_S_I64_S |
| 2412 | { 1612, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REM_S_I64 |
| 2413 | { 1611, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REM_S_I32_S |
| 2414 | { 1610, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REM_S_I32 |
| 2415 | { 1609, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELAXED_SWIZZLE_S |
| 2416 | { 1608, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELAXED_SWIZZLE |
| 2417 | { 1607, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELAXED_Q15MULR_S_I16x8_S |
| 2418 | { 1606, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELAXED_Q15MULR_S_I16x8 |
| 2419 | { 1605, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELAXED_DOT_S |
| 2420 | { 1604, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELAXED_DOT_BFLOAT_S |
| 2421 | { 1603, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 293, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELAXED_DOT_BFLOAT |
| 2422 | { 1602, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELAXED_DOT_ADD_S |
| 2423 | { 1601, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 293, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELAXED_DOT_ADD |
| 2424 | { 1600, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELAXED_DOT |
| 2425 | { 1599, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 307, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_TEST_FUNCREF_S |
| 2426 | { 1598, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 689, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_TEST_FUNCREF |
| 2427 | { 1597, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_NULL_FUNCREF_S |
| 2428 | { 1596, 1, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 413, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_NULL_FUNCREF |
| 2429 | { 1595, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_NULL_EXTERNREF_S |
| 2430 | { 1594, 1, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 410, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_NULL_EXTERNREF |
| 2431 | { 1593, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_NULL_EXNREF_S |
| 2432 | { 1592, 1, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 309, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_NULL_EXNREF |
| 2433 | { 1591, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_IS_NULL_FUNCREF_S |
| 2434 | { 1590, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 687, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_IS_NULL_FUNCREF |
| 2435 | { 1589, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_IS_NULL_EXTERNREF_S |
| 2436 | { 1588, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 685, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_IS_NULL_EXTERNREF |
| 2437 | { 1587, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_IS_NULL_EXNREF_S |
| 2438 | { 1586, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 683, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_IS_NULL_EXNREF |
| 2439 | { 1585, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 151, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_FUNC_S |
| 2440 | { 1584, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 681, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_FUNC |
| 2441 | { 1583, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 307, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_CAST_FUNCREF_S |
| 2442 | { 1582, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 678, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_CAST_FUNCREF |
| 2443 | { 1581, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Q15MULR_SAT_S_I16x8_S |
| 2444 | { 1580, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Q15MULR_SAT_S_I16x8 |
| 2445 | { 1579, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // POPCNT_I8x16_S |
| 2446 | { 1578, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // POPCNT_I8x16 |
| 2447 | { 1577, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // POPCNT_I64_S |
| 2448 | { 1576, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 312, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // POPCNT_I64 |
| 2449 | { 1575, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // POPCNT_I32_S |
| 2450 | { 1574, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 310, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // POPCNT_I32 |
| 2451 | { 1573, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PMIN_F64x2_S |
| 2452 | { 1572, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PMIN_F64x2 |
| 2453 | { 1571, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PMIN_F32x4_S |
| 2454 | { 1570, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PMIN_F32x4 |
| 2455 | { 1569, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PMIN_F16x8_S |
| 2456 | { 1568, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PMIN_F16x8 |
| 2457 | { 1567, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PMAX_F64x2_S |
| 2458 | { 1566, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PMAX_F64x2 |
| 2459 | { 1565, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PMAX_F32x4_S |
| 2460 | { 1564, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PMAX_F32x4 |
| 2461 | { 1563, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PMAX_F16x8_S |
| 2462 | { 1562, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PMAX_F16x8 |
| 2463 | { 1561, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_S |
| 2464 | { 1560, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_I64_S |
| 2465 | { 1559, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_I64 |
| 2466 | { 1558, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_I32_S |
| 2467 | { 1557, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_I32 |
| 2468 | { 1556, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR |
| 2469 | { 1555, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NOT_S |
| 2470 | { 1554, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NOT |
| 2471 | { 1553, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NOP_S |
| 2472 | { 1552, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NOP |
| 2473 | { 1551, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NMADD_F64x2_S |
| 2474 | { 1550, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 293, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NMADD_F64x2 |
| 2475 | { 1549, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NMADD_F32x4_S |
| 2476 | { 1548, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 293, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NMADD_F32x4 |
| 2477 | { 1547, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NMADD_F16x8_S |
| 2478 | { 1546, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 293, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NMADD_F16x8 |
| 2479 | { 1545, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_I8x16_S |
| 2480 | { 1544, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_I8x16 |
| 2481 | { 1543, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_I64x2_S |
| 2482 | { 1542, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_I64x2 |
| 2483 | { 1541, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_I64_S |
| 2484 | { 1540, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 423, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_I64 |
| 2485 | { 1539, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_I32x4_S |
| 2486 | { 1538, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_I32x4 |
| 2487 | { 1537, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_I32_S |
| 2488 | { 1536, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_I32 |
| 2489 | { 1535, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_I16x8_S |
| 2490 | { 1534, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_I16x8 |
| 2491 | { 1533, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_F64x2_S |
| 2492 | { 1532, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_F64x2 |
| 2493 | { 1531, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_F64_S |
| 2494 | { 1530, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 420, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_F64 |
| 2495 | { 1529, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_F32x4_S |
| 2496 | { 1528, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_F32x4 |
| 2497 | { 1527, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_F32_S |
| 2498 | { 1526, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 417, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_F32 |
| 2499 | { 1525, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_F16x8_S |
| 2500 | { 1524, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_F16x8 |
| 2501 | { 1523, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_I8x16_S |
| 2502 | { 1522, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_I8x16 |
| 2503 | { 1521, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_I64x2_S |
| 2504 | { 1520, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_I64x2 |
| 2505 | { 1519, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_I32x4_S |
| 2506 | { 1518, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_I32x4 |
| 2507 | { 1517, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_I16x8_S |
| 2508 | { 1516, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_I16x8 |
| 2509 | { 1515, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_F64x2_S |
| 2510 | { 1514, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_F64x2 |
| 2511 | { 1513, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_F64_S |
| 2512 | { 1512, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_F64 |
| 2513 | { 1511, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_F32x4_S |
| 2514 | { 1510, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_F32x4 |
| 2515 | { 1509, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_F32_S |
| 2516 | { 1508, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 157, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_F32 |
| 2517 | { 1507, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_F16x8_S |
| 2518 | { 1506, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_F16x8 |
| 2519 | { 1505, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEAREST_F64x2_S |
| 2520 | { 1504, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEAREST_F64x2 |
| 2521 | { 1503, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEAREST_F64_S |
| 2522 | { 1502, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEAREST_F64 |
| 2523 | { 1501, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEAREST_F32x4_S |
| 2524 | { 1500, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEAREST_F32x4 |
| 2525 | { 1499, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEAREST_F32_S |
| 2526 | { 1498, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 157, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEAREST_F32 |
| 2527 | { 1497, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEAREST_F16x8_S |
| 2528 | { 1496, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEAREST_F16x8 |
| 2529 | { 1495, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NARROW_U_I8x16_S |
| 2530 | { 1494, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NARROW_U_I8x16 |
| 2531 | { 1493, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NARROW_U_I16x8_S |
| 2532 | { 1492, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NARROW_U_I16x8 |
| 2533 | { 1491, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NARROW_S_I8x16_S |
| 2534 | { 1490, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NARROW_S_I8x16 |
| 2535 | { 1489, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NARROW_S_I16x8_S |
| 2536 | { 1488, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NARROW_S_I16x8 |
| 2537 | { 1487, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_I64x2_S |
| 2538 | { 1486, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_I64x2 |
| 2539 | { 1485, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_I64_S |
| 2540 | { 1484, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_I64 |
| 2541 | { 1483, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_I32x4_S |
| 2542 | { 1482, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_I32x4 |
| 2543 | { 1481, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_I32_S |
| 2544 | { 1480, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_I32 |
| 2545 | { 1479, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_I16x8_S |
| 2546 | { 1478, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_I16x8 |
| 2547 | { 1477, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_F64x2_S |
| 2548 | { 1476, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_F64x2 |
| 2549 | { 1475, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_F64_S |
| 2550 | { 1474, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 167, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_F64 |
| 2551 | { 1473, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_F32x4_S |
| 2552 | { 1472, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_F32x4 |
| 2553 | { 1471, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_F32_S |
| 2554 | { 1470, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 164, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_F32 |
| 2555 | { 1469, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_F16x8_S |
| 2556 | { 1468, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_F16x8 |
| 2557 | { 1467, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_U_I8x16_S |
| 2558 | { 1466, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_U_I8x16 |
| 2559 | { 1465, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_U_I32x4_S |
| 2560 | { 1464, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_U_I32x4 |
| 2561 | { 1463, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_U_I16x8_S |
| 2562 | { 1462, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_U_I16x8 |
| 2563 | { 1461, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_S_I8x16_S |
| 2564 | { 1460, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_S_I8x16 |
| 2565 | { 1459, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_S_I32x4_S |
| 2566 | { 1458, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_S_I32x4 |
| 2567 | { 1457, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_S_I16x8_S |
| 2568 | { 1456, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_S_I16x8 |
| 2569 | { 1455, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_F64x2_S |
| 2570 | { 1454, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_F64x2 |
| 2571 | { 1453, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_F64_S |
| 2572 | { 1452, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 167, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_F64 |
| 2573 | { 1451, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_F32x4_S |
| 2574 | { 1450, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_F32x4 |
| 2575 | { 1449, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_F32_S |
| 2576 | { 1448, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 164, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_F32 |
| 2577 | { 1447, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_F16x8_S |
| 2578 | { 1446, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_F16x8 |
| 2579 | { 1445, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 322, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMSET_A64_S |
| 2580 | { 1444, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 669, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMSET_A64 |
| 2581 | { 1443, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 322, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMSET_A32_S |
| 2582 | { 1442, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 665, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMSET_A32 |
| 2583 | { 1441, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 630, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_INIT_A64_S |
| 2584 | { 1440, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 673, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_INIT_A64 |
| 2585 | { 1439, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 630, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_INIT_A32_S |
| 2586 | { 1438, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 625, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_INIT_A32 |
| 2587 | { 1437, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 322, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_FILL_A64_S |
| 2588 | { 1436, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 669, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_FILL_A64 |
| 2589 | { 1435, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 322, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_FILL_A32_S |
| 2590 | { 1434, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 665, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_FILL_A32 |
| 2591 | { 1433, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 630, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_COPY_A64_S |
| 2592 | { 1432, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 632, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_COPY_A64 |
| 2593 | { 1431, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 630, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_COPY_A32_S |
| 2594 | { 1430, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 625, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_COPY_A32 |
| 2595 | { 1429, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_ATOMIC_WAIT64_A64_S |
| 2596 | { 1428, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 658, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_ATOMIC_WAIT64_A64 |
| 2597 | { 1427, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_ATOMIC_WAIT64_A32_S |
| 2598 | { 1426, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 651, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_ATOMIC_WAIT64_A32 |
| 2599 | { 1425, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_ATOMIC_WAIT32_A64_S |
| 2600 | { 1424, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 644, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_ATOMIC_WAIT32_A64 |
| 2601 | { 1423, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_ATOMIC_WAIT32_A32_S |
| 2602 | { 1422, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 637, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_ATOMIC_WAIT32_A32 |
| 2603 | { 1421, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_ATOMIC_NOTIFY_A64_S |
| 2604 | { 1420, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_ATOMIC_NOTIFY_A64 |
| 2605 | { 1419, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_ATOMIC_NOTIFY_A32_S |
| 2606 | { 1418, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_ATOMIC_NOTIFY_A32 |
| 2607 | { 1417, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 630, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMCPY_A64_S |
| 2608 | { 1416, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 632, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMCPY_A64 |
| 2609 | { 1415, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 630, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMCPY_A32_S |
| 2610 | { 1414, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 625, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMCPY_A32 |
| 2611 | { 1413, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_U_I8x16_S |
| 2612 | { 1412, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_U_I8x16 |
| 2613 | { 1411, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_U_I32x4_S |
| 2614 | { 1410, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_U_I32x4 |
| 2615 | { 1409, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_U_I16x8_S |
| 2616 | { 1408, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_U_I16x8 |
| 2617 | { 1407, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_S_I8x16_S |
| 2618 | { 1406, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_S_I8x16 |
| 2619 | { 1405, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_S_I32x4_S |
| 2620 | { 1404, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_S_I32x4 |
| 2621 | { 1403, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_S_I16x8_S |
| 2622 | { 1402, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_S_I16x8 |
| 2623 | { 1401, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_F64x2_S |
| 2624 | { 1400, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_F64x2 |
| 2625 | { 1399, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_F64_S |
| 2626 | { 1398, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 167, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_F64 |
| 2627 | { 1397, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_F32x4_S |
| 2628 | { 1396, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_F32x4 |
| 2629 | { 1395, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_F32_S |
| 2630 | { 1394, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 164, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_F32 |
| 2631 | { 1393, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_F16x8_S |
| 2632 | { 1392, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_F16x8 |
| 2633 | { 1391, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MADD_F64x2_S |
| 2634 | { 1390, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 293, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MADD_F64x2 |
| 2635 | { 1389, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MADD_F32x4_S |
| 2636 | { 1388, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 293, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MADD_F32x4 |
| 2637 | { 1387, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MADD_F16x8_S |
| 2638 | { 1386, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 293, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MADD_F16x8 |
| 2639 | { 1385, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_U_I8x16_S |
| 2640 | { 1384, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_U_I8x16 |
| 2641 | { 1383, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_U_I64_S |
| 2642 | { 1382, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 423, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_U_I64 |
| 2643 | { 1381, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_U_I32x4_S |
| 2644 | { 1380, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_U_I32x4 |
| 2645 | { 1379, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_U_I32_S |
| 2646 | { 1378, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_U_I32 |
| 2647 | { 1377, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_U_I16x8_S |
| 2648 | { 1376, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_U_I16x8 |
| 2649 | { 1375, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_S_I8x16_S |
| 2650 | { 1374, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_S_I8x16 |
| 2651 | { 1373, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_S_I64x2_S |
| 2652 | { 1372, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_S_I64x2 |
| 2653 | { 1371, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_S_I64_S |
| 2654 | { 1370, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 423, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_S_I64 |
| 2655 | { 1369, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_S_I32x4_S |
| 2656 | { 1368, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_S_I32x4 |
| 2657 | { 1367, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_S_I32_S |
| 2658 | { 1366, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_S_I32 |
| 2659 | { 1365, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_S_I16x8_S |
| 2660 | { 1364, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_S_I16x8 |
| 2661 | { 1363, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_F64x2_S |
| 2662 | { 1362, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_F64x2 |
| 2663 | { 1361, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_F64_S |
| 2664 | { 1360, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 420, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_F64 |
| 2665 | { 1359, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_F32x4_S |
| 2666 | { 1358, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_F32x4 |
| 2667 | { 1357, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_F32_S |
| 2668 | { 1356, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 417, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_F32 |
| 2669 | { 1355, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_F16x8_S |
| 2670 | { 1354, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_F16x8 |
| 2671 | { 1353, 1, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 297, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOOP_S |
| 2672 | { 1352, 1, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 297, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOOP |
| 2673 | { 1351, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_V128_S |
| 2674 | { 1350, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 622, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_V128 |
| 2675 | { 1349, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_I64_S |
| 2676 | { 1348, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 619, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_I64 |
| 2677 | { 1347, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_I32_S |
| 2678 | { 1346, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 616, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_I32 |
| 2679 | { 1345, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_FUNCREF_S |
| 2680 | { 1344, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 613, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_FUNCREF |
| 2681 | { 1343, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_F64_S |
| 2682 | { 1342, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 610, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_F64 |
| 2683 | { 1341, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_F32_S |
| 2684 | { 1340, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 607, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_F32 |
| 2685 | { 1339, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_EXTERNREF_S |
| 2686 | { 1338, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 604, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_EXTERNREF |
| 2687 | { 1337, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_EXNREF_S |
| 2688 | { 1336, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 601, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_EXNREF |
| 2689 | { 1335, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_V128_S |
| 2690 | { 1334, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 599, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_V128 |
| 2691 | { 1333, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_I64_S |
| 2692 | { 1332, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 597, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_I64 |
| 2693 | { 1331, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_I32_S |
| 2694 | { 1330, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 595, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_I32 |
| 2695 | { 1329, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_FUNCREF_S |
| 2696 | { 1328, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 593, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_FUNCREF |
| 2697 | { 1327, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_F64_S |
| 2698 | { 1326, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 591, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_F64 |
| 2699 | { 1325, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_F32_S |
| 2700 | { 1324, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 589, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_F32 |
| 2701 | { 1323, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_EXTERNREF_S |
| 2702 | { 1322, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 587, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_EXTERNREF |
| 2703 | { 1321, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_EXNREF_S |
| 2704 | { 1320, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 585, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_EXNREF |
| 2705 | { 1319, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_V128_S |
| 2706 | { 1318, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 583, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_V128 |
| 2707 | { 1317, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_I64_S |
| 2708 | { 1316, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 581, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_I64 |
| 2709 | { 1315, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_I32_S |
| 2710 | { 1314, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 579, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_I32 |
| 2711 | { 1313, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_FUNCREF_S |
| 2712 | { 1312, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 577, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_FUNCREF |
| 2713 | { 1311, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_F64_S |
| 2714 | { 1310, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 575, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_F64 |
| 2715 | { 1309, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_F32_S |
| 2716 | { 1308, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 573, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_F32 |
| 2717 | { 1307, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_EXTERNREF_S |
| 2718 | { 1306, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 571, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_EXTERNREF |
| 2719 | { 1305, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 570, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_EXNREF_S |
| 2720 | { 1304, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 568, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_EXNREF |
| 2721 | { 1303, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_ZERO_64_A64_S |
| 2722 | { 1302, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 512, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_ZERO_64_A64 |
| 2723 | { 1301, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_ZERO_64_A32_S |
| 2724 | { 1300, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 506, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_ZERO_64_A32 |
| 2725 | { 1299, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_ZERO_32_A64_S |
| 2726 | { 1298, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 512, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_ZERO_32_A64 |
| 2727 | { 1297, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_ZERO_32_A32_S |
| 2728 | { 1296, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 506, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_ZERO_32_A32 |
| 2729 | { 1295, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_V128_A64_S |
| 2730 | { 1294, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 512, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_V128_A64 |
| 2731 | { 1293, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_V128_A32_S |
| 2732 | { 1292, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 506, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_V128_A32 |
| 2733 | { 1291, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 565, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_8_A64_S |
| 2734 | { 1290, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 559, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_8_A64 |
| 2735 | { 1289, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 556, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_8_A32_S |
| 2736 | { 1288, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 550, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_8_A32 |
| 2737 | { 1287, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 565, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_64_A64_S |
| 2738 | { 1286, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 559, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_64_A64 |
| 2739 | { 1285, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 556, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_64_A32_S |
| 2740 | { 1284, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 550, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_64_A32 |
| 2741 | { 1283, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 565, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_32_A64_S |
| 2742 | { 1282, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 559, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_32_A64 |
| 2743 | { 1281, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 556, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_32_A32_S |
| 2744 | { 1280, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 550, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_32_A32 |
| 2745 | { 1279, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 565, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_16_A64_S |
| 2746 | { 1278, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 559, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_16_A64 |
| 2747 | { 1277, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 556, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_16_A32_S |
| 2748 | { 1276, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 550, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_16_A32 |
| 2749 | { 1275, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_I64_A64_S |
| 2750 | { 1274, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 530, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_I64_A64 |
| 2751 | { 1273, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_I64_A32_S |
| 2752 | { 1272, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 526, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_I64_A32 |
| 2753 | { 1271, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_I32_A64_S |
| 2754 | { 1270, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 522, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_I32_A64 |
| 2755 | { 1269, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_I32_A32_S |
| 2756 | { 1268, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 518, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_I32_A32 |
| 2757 | { 1267, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_F64_A64_S |
| 2758 | { 1266, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 546, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_F64_A64 |
| 2759 | { 1265, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_F64_A32_S |
| 2760 | { 1264, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 542, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_F64_A32 |
| 2761 | { 1263, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_F32_A64_S |
| 2762 | { 1262, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 538, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_F32_A64 |
| 2763 | { 1261, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_F32_A32_S |
| 2764 | { 1260, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 534, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_F32_A32 |
| 2765 | { 1259, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_F16_F32_A64_S |
| 2766 | { 1258, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 538, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_F16_F32_A64 |
| 2767 | { 1257, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_F16_F32_A32_S |
| 2768 | { 1256, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 534, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_F16_F32_A32 |
| 2769 | { 1255, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_U_I64x2_A64_S |
| 2770 | { 1254, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 512, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_U_I64x2_A64 |
| 2771 | { 1253, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_U_I64x2_A32_S |
| 2772 | { 1252, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 506, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_U_I64x2_A32 |
| 2773 | { 1251, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_U_I32x4_A64_S |
| 2774 | { 1250, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 512, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_U_I32x4_A64 |
| 2775 | { 1249, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_U_I32x4_A32_S |
| 2776 | { 1248, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 506, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_U_I32x4_A32 |
| 2777 | { 1247, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_U_I16x8_A64_S |
| 2778 | { 1246, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 512, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_U_I16x8_A64 |
| 2779 | { 1245, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_U_I16x8_A32_S |
| 2780 | { 1244, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 506, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_U_I16x8_A32 |
| 2781 | { 1243, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_S_I64x2_A64_S |
| 2782 | { 1242, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 512, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_S_I64x2_A64 |
| 2783 | { 1241, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_S_I64x2_A32_S |
| 2784 | { 1240, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 506, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_S_I64x2_A32 |
| 2785 | { 1239, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_S_I32x4_A64_S |
| 2786 | { 1238, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 512, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_S_I32x4_A64 |
| 2787 | { 1237, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_S_I32x4_A32_S |
| 2788 | { 1236, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 506, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_S_I32x4_A32 |
| 2789 | { 1235, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_S_I16x8_A64_S |
| 2790 | { 1234, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 512, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_S_I16x8_A64 |
| 2791 | { 1233, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_S_I16x8_A32_S |
| 2792 | { 1232, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 506, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_S_I16x8_A32 |
| 2793 | { 1231, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_U_I64_A64_S |
| 2794 | { 1230, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 530, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_U_I64_A64 |
| 2795 | { 1229, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_U_I64_A32_S |
| 2796 | { 1228, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 526, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_U_I64_A32 |
| 2797 | { 1227, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_U_I32_A64_S |
| 2798 | { 1226, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 522, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_U_I32_A64 |
| 2799 | { 1225, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_U_I32_A32_S |
| 2800 | { 1224, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 518, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_U_I32_A32 |
| 2801 | { 1223, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_S_I64_A64_S |
| 2802 | { 1222, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 530, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_S_I64_A64 |
| 2803 | { 1221, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_S_I64_A32_S |
| 2804 | { 1220, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 526, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_S_I64_A32 |
| 2805 | { 1219, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_S_I32_A64_S |
| 2806 | { 1218, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 522, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_S_I32_A64 |
| 2807 | { 1217, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_S_I32_A32_S |
| 2808 | { 1216, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 518, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_S_I32_A32 |
| 2809 | { 1215, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_SPLAT_A64_S |
| 2810 | { 1214, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 512, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_SPLAT_A64 |
| 2811 | { 1213, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_SPLAT_A32_S |
| 2812 | { 1212, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 506, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_SPLAT_A32 |
| 2813 | { 1211, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD64_SPLAT_A64_S |
| 2814 | { 1210, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 512, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD64_SPLAT_A64 |
| 2815 | { 1209, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD64_SPLAT_A32_S |
| 2816 | { 1208, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 506, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD64_SPLAT_A32 |
| 2817 | { 1207, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD32_U_I64_A64_S |
| 2818 | { 1206, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 530, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD32_U_I64_A64 |
| 2819 | { 1205, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD32_U_I64_A32_S |
| 2820 | { 1204, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 526, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD32_U_I64_A32 |
| 2821 | { 1203, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD32_S_I64_A64_S |
| 2822 | { 1202, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 530, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD32_S_I64_A64 |
| 2823 | { 1201, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD32_S_I64_A32_S |
| 2824 | { 1200, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 526, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD32_S_I64_A32 |
| 2825 | { 1199, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD32_SPLAT_A64_S |
| 2826 | { 1198, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 512, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD32_SPLAT_A64 |
| 2827 | { 1197, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD32_SPLAT_A32_S |
| 2828 | { 1196, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 506, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD32_SPLAT_A32 |
| 2829 | { 1195, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_U_I64_A64_S |
| 2830 | { 1194, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 530, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_U_I64_A64 |
| 2831 | { 1193, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_U_I64_A32_S |
| 2832 | { 1192, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 526, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_U_I64_A32 |
| 2833 | { 1191, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_U_I32_A64_S |
| 2834 | { 1190, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 522, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_U_I32_A64 |
| 2835 | { 1189, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_U_I32_A32_S |
| 2836 | { 1188, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 518, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_U_I32_A32 |
| 2837 | { 1187, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_S_I64_A64_S |
| 2838 | { 1186, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 530, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_S_I64_A64 |
| 2839 | { 1185, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_S_I64_A32_S |
| 2840 | { 1184, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 526, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_S_I64_A32 |
| 2841 | { 1183, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_S_I32_A64_S |
| 2842 | { 1182, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 522, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_S_I32_A64 |
| 2843 | { 1181, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_S_I32_A32_S |
| 2844 | { 1180, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 518, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_S_I32_A32 |
| 2845 | { 1179, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 516, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_SPLAT_A64_S |
| 2846 | { 1178, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 512, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_SPLAT_A64 |
| 2847 | { 1177, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 510, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_SPLAT_A32_S |
| 2848 | { 1176, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 506, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_SPLAT_A32 |
| 2849 | { 1175, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_U_I8x16_S |
| 2850 | { 1174, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_U_I8x16 |
| 2851 | { 1173, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_U_I64_S |
| 2852 | { 1172, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 423, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_U_I64 |
| 2853 | { 1171, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_U_I32x4_S |
| 2854 | { 1170, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_U_I32x4 |
| 2855 | { 1169, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_U_I32_S |
| 2856 | { 1168, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_U_I32 |
| 2857 | { 1167, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_U_I16x8_S |
| 2858 | { 1166, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_U_I16x8 |
| 2859 | { 1165, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_S_I8x16_S |
| 2860 | { 1164, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_S_I8x16 |
| 2861 | { 1163, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_S_I64x2_S |
| 2862 | { 1162, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_S_I64x2 |
| 2863 | { 1161, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_S_I64_S |
| 2864 | { 1160, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 423, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_S_I64 |
| 2865 | { 1159, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_S_I32x4_S |
| 2866 | { 1158, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_S_I32x4 |
| 2867 | { 1157, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_S_I32_S |
| 2868 | { 1156, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_S_I32 |
| 2869 | { 1155, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_S_I16x8_S |
| 2870 | { 1154, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_S_I16x8 |
| 2871 | { 1153, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_F64x2_S |
| 2872 | { 1152, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_F64x2 |
| 2873 | { 1151, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_F64_S |
| 2874 | { 1150, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 420, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_F64 |
| 2875 | { 1149, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_F32x4_S |
| 2876 | { 1148, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_F32x4 |
| 2877 | { 1147, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_F32_S |
| 2878 | { 1146, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 417, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_F32 |
| 2879 | { 1145, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_F16x8_S |
| 2880 | { 1144, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_F16x8 |
| 2881 | { 1143, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LANESELECT_I8x16_S |
| 2882 | { 1142, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 293, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LANESELECT_I8x16 |
| 2883 | { 1141, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LANESELECT_I64x2_S |
| 2884 | { 1140, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 293, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LANESELECT_I64x2 |
| 2885 | { 1139, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LANESELECT_I32x4_S |
| 2886 | { 1138, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 293, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LANESELECT_I32x4 |
| 2887 | { 1137, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LANESELECT_I16x8_S |
| 2888 | { 1136, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 293, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LANESELECT_I16x8 |
| 2889 | { 1135, 1, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 297, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // IF_S |
| 2890 | { 1134, 2, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 504, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // IF |
| 2891 | { 1133, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_U_SAT_F64_S |
| 2892 | { 1132, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 457, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_U_SAT_F64 |
| 2893 | { 1131, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_U_SAT_F32_S |
| 2894 | { 1130, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 455, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_U_SAT_F32 |
| 2895 | { 1129, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_U_F64_S |
| 2896 | { 1128, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 457, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_U_F64 |
| 2897 | { 1127, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_U_F32_S |
| 2898 | { 1126, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 455, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_U_F32 |
| 2899 | { 1125, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_S_SAT_F64_S |
| 2900 | { 1124, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 457, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_S_SAT_F64 |
| 2901 | { 1123, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_S_SAT_F32_S |
| 2902 | { 1122, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 455, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_S_SAT_F32 |
| 2903 | { 1121, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_S_F64_S |
| 2904 | { 1120, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 457, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_S_F64 |
| 2905 | { 1119, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_S_F32_S |
| 2906 | { 1118, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 455, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_S_F32 |
| 2907 | { 1117, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_SUB128_S |
| 2908 | { 1116, 6, 2, 0, 0, 0, 1, WebAssemblyOpInfoBase + 492, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_SUB128 |
| 2909 | { 1115, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_REINTERPRET_F64_S |
| 2910 | { 1114, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 457, 3, 0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_REINTERPRET_F64 |
| 2911 | { 1113, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_MUL_WIDE_U_S |
| 2912 | { 1112, 4, 2, 0, 0, 0, 1, WebAssemblyOpInfoBase + 500, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_MUL_WIDE_U |
| 2913 | { 1111, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_MUL_WIDE_S_S |
| 2914 | { 1110, 4, 2, 0, 0, 0, 1, WebAssemblyOpInfoBase + 500, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_MUL_WIDE_S |
| 2915 | { 1109, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_EXTEND_U_I32_S |
| 2916 | { 1108, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 498, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_EXTEND_U_I32 |
| 2917 | { 1107, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_EXTEND_S_I32_S |
| 2918 | { 1106, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 498, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_EXTEND_S_I32 |
| 2919 | { 1105, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_EXTEND8_S_I64_S |
| 2920 | { 1104, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 312, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_EXTEND8_S_I64 |
| 2921 | { 1103, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_EXTEND32_S_I64_S |
| 2922 | { 1102, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 312, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_EXTEND32_S_I64 |
| 2923 | { 1101, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_EXTEND16_S_I64_S |
| 2924 | { 1100, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 312, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_EXTEND16_S_I64 |
| 2925 | { 1099, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_ADD128_S |
| 2926 | { 1098, 6, 2, 0, 0, 0, 1, WebAssemblyOpInfoBase + 492, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_ADD128 |
| 2927 | { 1097, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_WRAP_I64_S |
| 2928 | { 1096, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 415, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_WRAP_I64 |
| 2929 | { 1095, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_U_SAT_F64_S |
| 2930 | { 1094, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 453, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_U_SAT_F64 |
| 2931 | { 1093, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_U_SAT_F32_S |
| 2932 | { 1092, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 451, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_U_SAT_F32 |
| 2933 | { 1091, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_U_F64_S |
| 2934 | { 1090, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 453, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_U_F64 |
| 2935 | { 1089, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_U_F32_S |
| 2936 | { 1088, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 451, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_U_F32 |
| 2937 | { 1087, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_S_SAT_F64_S |
| 2938 | { 1086, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 453, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_S_SAT_F64 |
| 2939 | { 1085, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_S_SAT_F32_S |
| 2940 | { 1084, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 451, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_S_SAT_F32 |
| 2941 | { 1083, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_S_F64_S |
| 2942 | { 1082, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 453, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_S_F64 |
| 2943 | { 1081, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_S_F32_S |
| 2944 | { 1080, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 451, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_S_F32 |
| 2945 | { 1079, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_REINTERPRET_F32_S |
| 2946 | { 1078, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 451, 3, 0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_REINTERPRET_F32 |
| 2947 | { 1077, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_EXTEND8_S_I32_S |
| 2948 | { 1076, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 310, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_EXTEND8_S_I32 |
| 2949 | { 1075, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_EXTEND16_S_I32_S |
| 2950 | { 1074, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 310, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_EXTEND16_S_I32 |
| 2951 | { 1073, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_U_I8x16_S |
| 2952 | { 1072, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_U_I8x16 |
| 2953 | { 1071, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_U_I64_S |
| 2954 | { 1070, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 423, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_U_I64 |
| 2955 | { 1069, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_U_I32x4_S |
| 2956 | { 1068, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_U_I32x4 |
| 2957 | { 1067, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_U_I32_S |
| 2958 | { 1066, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_U_I32 |
| 2959 | { 1065, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_U_I16x8_S |
| 2960 | { 1064, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_U_I16x8 |
| 2961 | { 1063, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_S_I8x16_S |
| 2962 | { 1062, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_S_I8x16 |
| 2963 | { 1061, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_S_I64x2_S |
| 2964 | { 1060, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_S_I64x2 |
| 2965 | { 1059, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_S_I64_S |
| 2966 | { 1058, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 423, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_S_I64 |
| 2967 | { 1057, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_S_I32x4_S |
| 2968 | { 1056, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_S_I32x4 |
| 2969 | { 1055, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_S_I32_S |
| 2970 | { 1054, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_S_I32 |
| 2971 | { 1053, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_S_I16x8_S |
| 2972 | { 1052, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_S_I16x8 |
| 2973 | { 1051, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_F64x2_S |
| 2974 | { 1050, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_F64x2 |
| 2975 | { 1049, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_F64_S |
| 2976 | { 1048, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 420, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_F64 |
| 2977 | { 1047, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_F32x4_S |
| 2978 | { 1046, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_F32x4 |
| 2979 | { 1045, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_F32_S |
| 2980 | { 1044, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 417, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_F32 |
| 2981 | { 1043, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_F16x8_S |
| 2982 | { 1042, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_F16x8 |
| 2983 | { 1041, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 461, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_V128_S |
| 2984 | { 1040, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 490, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_V128 |
| 2985 | { 1039, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 461, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_I64_S |
| 2986 | { 1038, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 488, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_I64 |
| 2987 | { 1037, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 461, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_I32_S |
| 2988 | { 1036, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 486, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_I32 |
| 2989 | { 1035, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 461, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_FUNCREF_S |
| 2990 | { 1034, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 484, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_FUNCREF |
| 2991 | { 1033, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 461, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_F64_S |
| 2992 | { 1032, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 482, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_F64 |
| 2993 | { 1031, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 461, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_F32_S |
| 2994 | { 1030, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 480, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_F32 |
| 2995 | { 1029, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 461, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_EXTERNREF_S |
| 2996 | { 1028, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 478, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_EXTERNREF |
| 2997 | { 1027, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 461, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_EXNREF_S |
| 2998 | { 1026, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 476, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_EXNREF |
| 2999 | { 1025, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 461, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_V128_S |
| 3000 | { 1024, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 474, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_V128 |
| 3001 | { 1023, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 461, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_I64_S |
| 3002 | { 1022, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 472, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_I64 |
| 3003 | { 1021, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 461, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_I32_S |
| 3004 | { 1020, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 470, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_I32 |
| 3005 | { 1019, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 461, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_FUNCREF_S |
| 3006 | { 1018, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 468, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_FUNCREF |
| 3007 | { 1017, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 461, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_F64_S |
| 3008 | { 1016, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 466, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_F64 |
| 3009 | { 1015, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 461, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_F32_S |
| 3010 | { 1014, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 464, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_F32 |
| 3011 | { 1013, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 461, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_EXTERNREF_S |
| 3012 | { 1012, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 462, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_EXTERNREF |
| 3013 | { 1011, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 461, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_EXNREF_S |
| 3014 | { 1010, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 459, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_EXNREF |
| 3015 | { 1009, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_U_I8x16_S |
| 3016 | { 1008, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_U_I8x16 |
| 3017 | { 1007, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_U_I64_S |
| 3018 | { 1006, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 423, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_U_I64 |
| 3019 | { 1005, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_U_I32x4_S |
| 3020 | { 1004, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_U_I32x4 |
| 3021 | { 1003, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_U_I32_S |
| 3022 | { 1002, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_U_I32 |
| 3023 | { 1001, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_U_I16x8_S |
| 3024 | { 1000, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_U_I16x8 |
| 3025 | { 999, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_S_I8x16_S |
| 3026 | { 998, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_S_I8x16 |
| 3027 | { 997, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_S_I64x2_S |
| 3028 | { 996, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_S_I64x2 |
| 3029 | { 995, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_S_I64_S |
| 3030 | { 994, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 423, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_S_I64 |
| 3031 | { 993, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_S_I32x4_S |
| 3032 | { 992, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_S_I32x4 |
| 3033 | { 991, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_S_I32_S |
| 3034 | { 990, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_S_I32 |
| 3035 | { 989, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_S_I16x8_S |
| 3036 | { 988, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_S_I16x8 |
| 3037 | { 987, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_F64x2_S |
| 3038 | { 986, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_F64x2 |
| 3039 | { 985, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_F64_S |
| 3040 | { 984, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 420, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_F64 |
| 3041 | { 983, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_F32x4_S |
| 3042 | { 982, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_F32x4 |
| 3043 | { 981, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_F32_S |
| 3044 | { 980, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 417, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_F32 |
| 3045 | { 979, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_F16x8_S |
| 3046 | { 978, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_F16x8 |
| 3047 | { 977, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_UINT_I64_F64_S |
| 3048 | { 976, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 457, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_UINT_I64_F64 |
| 3049 | { 975, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_UINT_I64_F32_S |
| 3050 | { 974, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 455, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_UINT_I64_F32 |
| 3051 | { 973, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_UINT_I32_F64_S |
| 3052 | { 972, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 453, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_UINT_I32_F64 |
| 3053 | { 971, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_UINT_I32_F32_S |
| 3054 | { 970, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 451, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_UINT_I32_F32 |
| 3055 | { 969, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_SINT_I64_F64_S |
| 3056 | { 968, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 457, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_SINT_I64_F64 |
| 3057 | { 967, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_SINT_I64_F32_S |
| 3058 | { 966, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 455, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_SINT_I64_F32 |
| 3059 | { 965, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_SINT_I32_F64_S |
| 3060 | { 964, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 453, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_SINT_I32_F64 |
| 3061 | { 963, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_SINT_I32_F32_S |
| 3062 | { 962, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 451, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_SINT_I32_F32 |
| 3063 | { 961, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FLOOR_F64x2_S |
| 3064 | { 960, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FLOOR_F64x2 |
| 3065 | { 959, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FLOOR_F64_S |
| 3066 | { 958, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FLOOR_F64 |
| 3067 | { 957, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FLOOR_F32x4_S |
| 3068 | { 956, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FLOOR_F32x4 |
| 3069 | { 955, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FLOOR_F32_S |
| 3070 | { 954, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 157, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FLOOR_F32 |
| 3071 | { 953, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FLOOR_F16x8_S |
| 3072 | { 952, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FLOOR_F16x8 |
| 3073 | { 951, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FALLTHROUGH_RETURN_S |
| 3074 | { 950, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FALLTHROUGH_RETURN |
| 3075 | { 949, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F64_REINTERPRET_I64_S |
| 3076 | { 948, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 447, 3, 0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F64_REINTERPRET_I64 |
| 3077 | { 947, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F64_PROMOTE_F32_S |
| 3078 | { 946, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 449, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F64_PROMOTE_F32 |
| 3079 | { 945, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F64_CONVERT_U_I64_S |
| 3080 | { 944, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 447, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F64_CONVERT_U_I64 |
| 3081 | { 943, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F64_CONVERT_U_I32_S |
| 3082 | { 942, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 445, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F64_CONVERT_U_I32 |
| 3083 | { 941, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F64_CONVERT_S_I64_S |
| 3084 | { 940, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 447, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F64_CONVERT_S_I64 |
| 3085 | { 939, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F64_CONVERT_S_I32_S |
| 3086 | { 938, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 445, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F64_CONVERT_S_I32 |
| 3087 | { 937, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F32_REINTERPRET_I32_S |
| 3088 | { 936, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 439, 3, 0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F32_REINTERPRET_I32 |
| 3089 | { 935, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F32_DEMOTE_F64_S |
| 3090 | { 934, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 443, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F32_DEMOTE_F64 |
| 3091 | { 933, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F32_CONVERT_U_I64_S |
| 3092 | { 932, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 441, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F32_CONVERT_U_I64 |
| 3093 | { 931, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F32_CONVERT_U_I32_S |
| 3094 | { 930, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 439, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F32_CONVERT_U_I32 |
| 3095 | { 929, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F32_CONVERT_S_I64_S |
| 3096 | { 928, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 441, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F32_CONVERT_S_I64 |
| 3097 | { 927, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F32_CONVERT_S_I32_S |
| 3098 | { 926, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 439, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F32_CONVERT_S_I32 |
| 3099 | { 925, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 429, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_I8x16_u_S |
| 3100 | { 924, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 433, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_I8x16_u |
| 3101 | { 923, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 429, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_I8x16_s_S |
| 3102 | { 922, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 433, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_I8x16_s |
| 3103 | { 921, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 429, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_I64x2_S |
| 3104 | { 920, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 436, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_I64x2 |
| 3105 | { 919, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 429, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_I32x4_S |
| 3106 | { 918, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 433, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_I32x4 |
| 3107 | { 917, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 429, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_I16x8_u_S |
| 3108 | { 916, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 433, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_I16x8_u |
| 3109 | { 915, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 429, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_I16x8_s_S |
| 3110 | { 914, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 433, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_I16x8_s |
| 3111 | { 913, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 429, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_F64x2_S |
| 3112 | { 912, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 430, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_F64x2 |
| 3113 | { 911, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 429, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_F32x4_S |
| 3114 | { 910, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 426, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_F32x4 |
| 3115 | { 909, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 429, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_F16x8_S |
| 3116 | { 908, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 426, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_F16x8 |
| 3117 | { 907, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_LOW_U_I64x2_S |
| 3118 | { 906, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_LOW_U_I64x2 |
| 3119 | { 905, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_LOW_U_I32x4_S |
| 3120 | { 904, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_LOW_U_I32x4 |
| 3121 | { 903, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_LOW_U_I16x8_S |
| 3122 | { 902, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_LOW_U_I16x8 |
| 3123 | { 901, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_LOW_S_I64x2_S |
| 3124 | { 900, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_LOW_S_I64x2 |
| 3125 | { 899, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_LOW_S_I32x4_S |
| 3126 | { 898, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_LOW_S_I32x4 |
| 3127 | { 897, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_LOW_S_I16x8_S |
| 3128 | { 896, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_LOW_S_I16x8 |
| 3129 | { 895, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_HIGH_U_I64x2_S |
| 3130 | { 894, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_HIGH_U_I64x2 |
| 3131 | { 893, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_HIGH_U_I32x4_S |
| 3132 | { 892, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_HIGH_U_I32x4 |
| 3133 | { 891, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_HIGH_U_I16x8_S |
| 3134 | { 890, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_HIGH_U_I16x8 |
| 3135 | { 889, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_HIGH_S_I64x2_S |
| 3136 | { 888, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_HIGH_S_I64x2 |
| 3137 | { 887, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_HIGH_S_I32x4_S |
| 3138 | { 886, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_HIGH_S_I32x4 |
| 3139 | { 885, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_HIGH_S_I16x8_S |
| 3140 | { 884, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_HIGH_S_I16x8 |
| 3141 | { 883, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_I8x16_S |
| 3142 | { 882, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_I8x16 |
| 3143 | { 881, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_I64x2_S |
| 3144 | { 880, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_I64x2 |
| 3145 | { 879, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_I64_S |
| 3146 | { 878, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 423, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_I64 |
| 3147 | { 877, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_I32x4_S |
| 3148 | { 876, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_I32x4 |
| 3149 | { 875, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_I32_S |
| 3150 | { 874, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_I32 |
| 3151 | { 873, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_I16x8_S |
| 3152 | { 872, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_I16x8 |
| 3153 | { 871, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_F64x2_S |
| 3154 | { 870, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_F64x2 |
| 3155 | { 869, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_F64_S |
| 3156 | { 868, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 420, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_F64 |
| 3157 | { 867, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_F32x4_S |
| 3158 | { 866, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_F32x4 |
| 3159 | { 865, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_F32_S |
| 3160 | { 864, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 417, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_F32 |
| 3161 | { 863, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_F16x8_S |
| 3162 | { 862, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_F16x8 |
| 3163 | { 861, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQZ_I64_S |
| 3164 | { 860, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 415, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQZ_I64 |
| 3165 | { 859, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQZ_I32_S |
| 3166 | { 858, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 310, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQZ_I32 |
| 3167 | { 857, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_TRY_TABLE_S |
| 3168 | { 856, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_TRY_TABLE |
| 3169 | { 855, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_TRY_S |
| 3170 | { 854, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_TRY |
| 3171 | { 853, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_S |
| 3172 | { 852, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_LOOP_S |
| 3173 | { 851, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_LOOP |
| 3174 | { 850, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_IF_S |
| 3175 | { 849, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_IF |
| 3176 | { 848, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_FUNCTION_S |
| 3177 | { 847, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_FUNCTION |
| 3178 | { 846, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_BLOCK_S |
| 3179 | { 845, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_BLOCK |
| 3180 | { 844, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END |
| 3181 | { 843, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ELSE_S |
| 3182 | { 842, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ELSE |
| 3183 | { 841, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_V128_S |
| 3184 | { 840, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 414, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_V128 |
| 3185 | { 839, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_I64_S |
| 3186 | { 838, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 302, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_I64 |
| 3187 | { 837, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_I32_S |
| 3188 | { 836, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 300, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_I32 |
| 3189 | { 835, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_FUNCREF_S |
| 3190 | { 834, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 413, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_FUNCREF |
| 3191 | { 833, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_F64_S |
| 3192 | { 832, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 412, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_F64 |
| 3193 | { 831, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_F32_S |
| 3194 | { 830, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 411, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_F32 |
| 3195 | { 829, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_EXTERNREF_S |
| 3196 | { 828, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 410, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_EXTERNREF |
| 3197 | { 827, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_EXNREF_S |
| 3198 | { 826, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 309, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_EXNREF |
| 3199 | { 825, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DOT_S |
| 3200 | { 824, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DOT |
| 3201 | { 823, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_U_I64_S |
| 3202 | { 822, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_U_I64 |
| 3203 | { 821, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_U_I32_S |
| 3204 | { 820, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_U_I32 |
| 3205 | { 819, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_S_I64_S |
| 3206 | { 818, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_S_I64 |
| 3207 | { 817, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_S_I32_S |
| 3208 | { 816, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_S_I32 |
| 3209 | { 815, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_F64x2_S |
| 3210 | { 814, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_F64x2 |
| 3211 | { 813, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_F64_S |
| 3212 | { 812, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 167, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_F64 |
| 3213 | { 811, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_F32x4_S |
| 3214 | { 810, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_F32x4 |
| 3215 | { 809, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_F32_S |
| 3216 | { 808, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 164, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_F32 |
| 3217 | { 807, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_F16x8_S |
| 3218 | { 806, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_F16x8 |
| 3219 | { 805, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 154, 3, 0|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DELEGATE_S |
| 3220 | { 804, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 154, 3, 0|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DELEGATE |
| 3221 | { 803, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Trap)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DEBUG_UNREACHABLE_S |
| 3222 | { 802, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Trap)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DEBUG_UNREACHABLE |
| 3223 | { 801, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 322, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DATA_DROP_S |
| 3224 | { 800, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 322, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DATA_DROP |
| 3225 | { 799, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CTZ_I64_S |
| 3226 | { 798, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 312, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CTZ_I64 |
| 3227 | { 797, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CTZ_I32_S |
| 3228 | { 796, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 310, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CTZ_I32 |
| 3229 | { 795, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_V128_S |
| 3230 | { 794, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_V128 |
| 3231 | { 793, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_I64_S |
| 3232 | { 792, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 312, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_I64 |
| 3233 | { 791, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_I32_S |
| 3234 | { 790, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 310, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_I32 |
| 3235 | { 789, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_FUNCREF_S |
| 3236 | { 788, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 408, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_FUNCREF |
| 3237 | { 787, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_F64_S |
| 3238 | { 786, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_F64 |
| 3239 | { 785, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_F32_S |
| 3240 | { 784, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 157, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_F32 |
| 3241 | { 783, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_EXTERNREF_S |
| 3242 | { 782, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 406, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_EXTERNREF |
| 3243 | { 781, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_EXNREF_S |
| 3244 | { 780, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 404, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_EXNREF |
| 3245 | { 779, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPYSIGN_F64_S |
| 3246 | { 778, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 167, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPYSIGN_F64 |
| 3247 | { 777, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPYSIGN_F32_S |
| 3248 | { 776, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 164, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPYSIGN_F32 |
| 3249 | { 775, 16, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 388, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_V128_I8x16_S |
| 3250 | { 774, 17, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 371, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_V128_I8x16 |
| 3251 | { 773, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 369, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_V128_I64x2_S |
| 3252 | { 772, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 366, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_V128_I64x2 |
| 3253 | { 771, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 362, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_V128_I32x4_S |
| 3254 | { 770, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 357, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_V128_I32x4 |
| 3255 | { 769, 8, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 349, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_V128_I16x8_S |
| 3256 | { 768, 9, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 340, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_V128_I16x8 |
| 3257 | { 767, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 338, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_V128_F64x2_S |
| 3258 | { 766, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 335, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_V128_F64x2 |
| 3259 | { 765, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 331, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_V128_F32x4_S |
| 3260 | { 764, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 326, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_V128_F32x4 |
| 3261 | { 763, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 325, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_I64_S |
| 3262 | { 762, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 323, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_I64 |
| 3263 | { 761, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 322, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_I32_S |
| 3264 | { 760, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 320, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_I32 |
| 3265 | { 759, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 319, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_F64_S |
| 3266 | { 758, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 317, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_F64 |
| 3267 | { 757, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 316, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_F32_S |
| 3268 | { 756, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 314, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_F32 |
| 3269 | { 755, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLZ_I64_S |
| 3270 | { 754, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 312, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLZ_I64 |
| 3271 | { 753, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLZ_I32_S |
| 3272 | { 752, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 310, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLZ_I32 |
| 3273 | { 751, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CEIL_F64x2_S |
| 3274 | { 750, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CEIL_F64x2 |
| 3275 | { 749, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CEIL_F64_S |
| 3276 | { 748, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CEIL_F64 |
| 3277 | { 747, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CEIL_F32x4_S |
| 3278 | { 746, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CEIL_F32x4 |
| 3279 | { 745, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CEIL_F32_S |
| 3280 | { 744, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 157, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CEIL_F32 |
| 3281 | { 743, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CEIL_F16x8_S |
| 3282 | { 742, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CEIL_F16x8 |
| 3283 | { 741, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 308, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CATCH_S |
| 3284 | { 740, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 308, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CATCH_REF_S |
| 3285 | { 739, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 308, 3, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CATCH_REF |
| 3286 | { 738, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 308, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CATCH_LEGACY_S |
| 3287 | { 737, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 308, 3, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CATCH_LEGACY |
| 3288 | { 736, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CATCH_ALL_S |
| 3289 | { 735, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CATCH_ALL_REF_S |
| 3290 | { 734, 1, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 309, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CATCH_ALL_REF |
| 3291 | { 733, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CATCH_ALL_LEGACY_S |
| 3292 | { 732, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CATCH_ALL_LEGACY |
| 3293 | { 731, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CATCH_ALL |
| 3294 | { 730, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 308, 3, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CATCH |
| 3295 | { 729, 1, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 151, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CALL_S |
| 3296 | { 728, 1, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 307, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CALL_REF_S |
| 3297 | { 727, 2, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 305, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CALL_REF |
| 3298 | { 726, 2, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 303, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CALL_INDIRECT_S |
| 3299 | { 725, 2, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 303, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CALL_INDIRECT |
| 3300 | { 724, 1, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 151, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CALL |
| 3301 | { 723, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 154, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BR_UNLESS_S |
| 3302 | { 722, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 298, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BR_UNLESS |
| 3303 | { 721, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 301, 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BR_TABLE_I64_S |
| 3304 | { 720, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 302, 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BR_TABLE_I64 |
| 3305 | { 719, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 301, 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BR_TABLE_I32_S |
| 3306 | { 718, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 300, 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BR_TABLE_I32 |
| 3307 | { 717, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 154, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BR_S |
| 3308 | { 716, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 154, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BR_IF_S |
| 3309 | { 715, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 298, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BR_IF |
| 3310 | { 714, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 154, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BR |
| 3311 | { 713, 1, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 297, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLOCK_S |
| 3312 | { 712, 1, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 297, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLOCK |
| 3313 | { 711, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BITSELECT_S |
| 3314 | { 710, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 293, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BITSELECT |
| 3315 | { 709, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BITMASK_I8x16_S |
| 3316 | { 708, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 176, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BITMASK_I8x16 |
| 3317 | { 707, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BITMASK_I64x2_S |
| 3318 | { 706, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 176, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BITMASK_I64x2 |
| 3319 | { 705, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BITMASK_I32x4_S |
| 3320 | { 704, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 176, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BITMASK_I32x4 |
| 3321 | { 703, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BITMASK_I16x8_S |
| 3322 | { 702, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 176, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BITMASK_I16x8 |
| 3323 | { 701, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AVGR_U_I8x16_S |
| 3324 | { 700, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AVGR_U_I8x16 |
| 3325 | { 699, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AVGR_U_I16x8_S |
| 3326 | { 698, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AVGR_U_I16x8 |
| 3327 | { 697, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE_I64_A64_S |
| 3328 | { 696, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 288, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE_I64_A64 |
| 3329 | { 695, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE_I64_A32_S |
| 3330 | { 694, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 283, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE_I64_A32 |
| 3331 | { 693, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE_I32_A64_S |
| 3332 | { 692, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 278, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE_I32_A64 |
| 3333 | { 691, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE_I32_A32_S |
| 3334 | { 690, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 273, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE_I32_A32 |
| 3335 | { 689, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE8_I64_A64_S |
| 3336 | { 688, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 288, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE8_I64_A64 |
| 3337 | { 687, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE8_I64_A32_S |
| 3338 | { 686, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 283, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE8_I64_A32 |
| 3339 | { 685, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE8_I32_A64_S |
| 3340 | { 684, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 278, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE8_I32_A64 |
| 3341 | { 683, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE8_I32_A32_S |
| 3342 | { 682, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 273, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE8_I32_A32 |
| 3343 | { 681, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE32_I64_A64_S |
| 3344 | { 680, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 288, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE32_I64_A64 |
| 3345 | { 679, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE32_I64_A32_S |
| 3346 | { 678, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 283, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE32_I64_A32 |
| 3347 | { 677, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE16_I64_A64_S |
| 3348 | { 676, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 288, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE16_I64_A64 |
| 3349 | { 675, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE16_I64_A32_S |
| 3350 | { 674, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 283, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE16_I64_A32 |
| 3351 | { 673, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE16_I32_A64_S |
| 3352 | { 672, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 278, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE16_I32_A64 |
| 3353 | { 671, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE16_I32_A32_S |
| 3354 | { 670, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 273, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE16_I32_A32 |
| 3355 | { 669, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XOR_I64_A64_S |
| 3356 | { 668, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XOR_I64_A64 |
| 3357 | { 667, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XOR_I64_A32_S |
| 3358 | { 666, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XOR_I64_A32 |
| 3359 | { 665, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XOR_I32_A64_S |
| 3360 | { 664, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XOR_I32_A64 |
| 3361 | { 663, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XOR_I32_A32_S |
| 3362 | { 662, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XOR_I32_A32 |
| 3363 | { 661, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XCHG_I64_A64_S |
| 3364 | { 660, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XCHG_I64_A64 |
| 3365 | { 659, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XCHG_I64_A32_S |
| 3366 | { 658, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XCHG_I64_A32 |
| 3367 | { 657, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XCHG_I32_A64_S |
| 3368 | { 656, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XCHG_I32_A64 |
| 3369 | { 655, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XCHG_I32_A32_S |
| 3370 | { 654, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XCHG_I32_A32 |
| 3371 | { 653, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_SUB_I64_A64_S |
| 3372 | { 652, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_SUB_I64_A64 |
| 3373 | { 651, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_SUB_I64_A32_S |
| 3374 | { 650, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_SUB_I64_A32 |
| 3375 | { 649, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_SUB_I32_A64_S |
| 3376 | { 648, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_SUB_I32_A64 |
| 3377 | { 647, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_SUB_I32_A32_S |
| 3378 | { 646, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_SUB_I32_A32 |
| 3379 | { 645, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_OR_I64_A64_S |
| 3380 | { 644, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_OR_I64_A64 |
| 3381 | { 643, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_OR_I64_A32_S |
| 3382 | { 642, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_OR_I64_A32 |
| 3383 | { 641, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_OR_I32_A64_S |
| 3384 | { 640, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_OR_I32_A64 |
| 3385 | { 639, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_OR_I32_A32_S |
| 3386 | { 638, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_OR_I32_A32 |
| 3387 | { 637, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_CMPXCHG_I64_A64_S |
| 3388 | { 636, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 266, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_CMPXCHG_I64_A64 |
| 3389 | { 635, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_CMPXCHG_I64_A32_S |
| 3390 | { 634, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 259, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_CMPXCHG_I64_A32 |
| 3391 | { 633, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_CMPXCHG_I32_A64_S |
| 3392 | { 632, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 252, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_CMPXCHG_I32_A64 |
| 3393 | { 631, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_CMPXCHG_I32_A32_S |
| 3394 | { 630, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 245, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_CMPXCHG_I32_A32 |
| 3395 | { 629, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_AND_I64_A64_S |
| 3396 | { 628, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_AND_I64_A64 |
| 3397 | { 627, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_AND_I64_A32_S |
| 3398 | { 626, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_AND_I64_A32 |
| 3399 | { 625, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_AND_I32_A64_S |
| 3400 | { 624, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_AND_I32_A64 |
| 3401 | { 623, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_AND_I32_A32_S |
| 3402 | { 622, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_AND_I32_A32 |
| 3403 | { 621, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_ADD_I64_A64_S |
| 3404 | { 620, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_ADD_I64_A64 |
| 3405 | { 619, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_ADD_I64_A32_S |
| 3406 | { 618, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_ADD_I64_A32 |
| 3407 | { 617, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_ADD_I32_A64_S |
| 3408 | { 616, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_ADD_I32_A64 |
| 3409 | { 615, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_ADD_I32_A32_S |
| 3410 | { 614, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_ADD_I32_A32 |
| 3411 | { 613, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XOR_I64_A64_S |
| 3412 | { 612, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XOR_I64_A64 |
| 3413 | { 611, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XOR_I64_A32_S |
| 3414 | { 610, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XOR_I64_A32 |
| 3415 | { 609, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XOR_I32_A64_S |
| 3416 | { 608, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XOR_I32_A64 |
| 3417 | { 607, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XOR_I32_A32_S |
| 3418 | { 606, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XOR_I32_A32 |
| 3419 | { 605, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XCHG_I64_A64_S |
| 3420 | { 604, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XCHG_I64_A64 |
| 3421 | { 603, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XCHG_I64_A32_S |
| 3422 | { 602, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XCHG_I64_A32 |
| 3423 | { 601, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XCHG_I32_A64_S |
| 3424 | { 600, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XCHG_I32_A64 |
| 3425 | { 599, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XCHG_I32_A32_S |
| 3426 | { 598, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XCHG_I32_A32 |
| 3427 | { 597, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_SUB_I64_A64_S |
| 3428 | { 596, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_SUB_I64_A64 |
| 3429 | { 595, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_SUB_I64_A32_S |
| 3430 | { 594, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_SUB_I64_A32 |
| 3431 | { 593, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_SUB_I32_A64_S |
| 3432 | { 592, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_SUB_I32_A64 |
| 3433 | { 591, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_SUB_I32_A32_S |
| 3434 | { 590, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_SUB_I32_A32 |
| 3435 | { 589, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_OR_I64_A64_S |
| 3436 | { 588, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_OR_I64_A64 |
| 3437 | { 587, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_OR_I64_A32_S |
| 3438 | { 586, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_OR_I64_A32 |
| 3439 | { 585, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_OR_I32_A64_S |
| 3440 | { 584, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_OR_I32_A64 |
| 3441 | { 583, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_OR_I32_A32_S |
| 3442 | { 582, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_OR_I32_A32 |
| 3443 | { 581, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_CMPXCHG_I64_A64_S |
| 3444 | { 580, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 266, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_CMPXCHG_I64_A64 |
| 3445 | { 579, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_CMPXCHG_I64_A32_S |
| 3446 | { 578, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 259, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_CMPXCHG_I64_A32 |
| 3447 | { 577, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_CMPXCHG_I32_A64_S |
| 3448 | { 576, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 252, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_CMPXCHG_I32_A64 |
| 3449 | { 575, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_CMPXCHG_I32_A32_S |
| 3450 | { 574, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 245, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_CMPXCHG_I32_A32 |
| 3451 | { 573, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_AND_I64_A64_S |
| 3452 | { 572, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_AND_I64_A64 |
| 3453 | { 571, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_AND_I64_A32_S |
| 3454 | { 570, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_AND_I64_A32 |
| 3455 | { 569, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_AND_I32_A64_S |
| 3456 | { 568, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_AND_I32_A64 |
| 3457 | { 567, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_AND_I32_A32_S |
| 3458 | { 566, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_AND_I32_A32 |
| 3459 | { 565, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_ADD_I64_A64_S |
| 3460 | { 564, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_ADD_I64_A64 |
| 3461 | { 563, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_ADD_I64_A32_S |
| 3462 | { 562, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_ADD_I64_A32 |
| 3463 | { 561, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_ADD_I32_A64_S |
| 3464 | { 560, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_ADD_I32_A64 |
| 3465 | { 559, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_ADD_I32_A32_S |
| 3466 | { 558, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_ADD_I32_A32 |
| 3467 | { 557, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_XOR_I64_A64_S |
| 3468 | { 556, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_XOR_I64_A64 |
| 3469 | { 555, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_XOR_I64_A32_S |
| 3470 | { 554, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_XOR_I64_A32 |
| 3471 | { 553, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_XCHG_I64_A64_S |
| 3472 | { 552, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_XCHG_I64_A64 |
| 3473 | { 551, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_XCHG_I64_A32_S |
| 3474 | { 550, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_XCHG_I64_A32 |
| 3475 | { 549, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_SUB_I64_A64_S |
| 3476 | { 548, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_SUB_I64_A64 |
| 3477 | { 547, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_SUB_I64_A32_S |
| 3478 | { 546, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_SUB_I64_A32 |
| 3479 | { 545, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_OR_I64_A64_S |
| 3480 | { 544, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_OR_I64_A64 |
| 3481 | { 543, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_OR_I64_A32_S |
| 3482 | { 542, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_OR_I64_A32 |
| 3483 | { 541, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_CMPXCHG_I64_A64_S |
| 3484 | { 540, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 266, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_CMPXCHG_I64_A64 |
| 3485 | { 539, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_CMPXCHG_I64_A32_S |
| 3486 | { 538, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 259, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_CMPXCHG_I64_A32 |
| 3487 | { 537, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_AND_I64_A64_S |
| 3488 | { 536, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_AND_I64_A64 |
| 3489 | { 535, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_AND_I64_A32_S |
| 3490 | { 534, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_AND_I64_A32 |
| 3491 | { 533, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_ADD_I64_A64_S |
| 3492 | { 532, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_ADD_I64_A64 |
| 3493 | { 531, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_ADD_I64_A32_S |
| 3494 | { 530, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_ADD_I64_A32 |
| 3495 | { 529, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XOR_I64_A64_S |
| 3496 | { 528, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XOR_I64_A64 |
| 3497 | { 527, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XOR_I64_A32_S |
| 3498 | { 526, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XOR_I64_A32 |
| 3499 | { 525, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XOR_I32_A64_S |
| 3500 | { 524, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XOR_I32_A64 |
| 3501 | { 523, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XOR_I32_A32_S |
| 3502 | { 522, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XOR_I32_A32 |
| 3503 | { 521, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XCHG_I64_A64_S |
| 3504 | { 520, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XCHG_I64_A64 |
| 3505 | { 519, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XCHG_I64_A32_S |
| 3506 | { 518, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XCHG_I64_A32 |
| 3507 | { 517, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XCHG_I32_A64_S |
| 3508 | { 516, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XCHG_I32_A64 |
| 3509 | { 515, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XCHG_I32_A32_S |
| 3510 | { 514, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XCHG_I32_A32 |
| 3511 | { 513, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_SUB_I64_A64_S |
| 3512 | { 512, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_SUB_I64_A64 |
| 3513 | { 511, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_SUB_I64_A32_S |
| 3514 | { 510, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_SUB_I64_A32 |
| 3515 | { 509, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_SUB_I32_A64_S |
| 3516 | { 508, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_SUB_I32_A64 |
| 3517 | { 507, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_SUB_I32_A32_S |
| 3518 | { 506, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_SUB_I32_A32 |
| 3519 | { 505, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_OR_I64_A64_S |
| 3520 | { 504, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_OR_I64_A64 |
| 3521 | { 503, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_OR_I64_A32_S |
| 3522 | { 502, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_OR_I64_A32 |
| 3523 | { 501, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_OR_I32_A64_S |
| 3524 | { 500, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_OR_I32_A64 |
| 3525 | { 499, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_OR_I32_A32_S |
| 3526 | { 498, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_OR_I32_A32 |
| 3527 | { 497, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_CMPXCHG_I64_A64_S |
| 3528 | { 496, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 266, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_CMPXCHG_I64_A64 |
| 3529 | { 495, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_CMPXCHG_I64_A32_S |
| 3530 | { 494, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 259, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_CMPXCHG_I64_A32 |
| 3531 | { 493, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_CMPXCHG_I32_A64_S |
| 3532 | { 492, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 252, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_CMPXCHG_I32_A64 |
| 3533 | { 491, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_CMPXCHG_I32_A32_S |
| 3534 | { 490, 7, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 245, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_CMPXCHG_I32_A32 |
| 3535 | { 489, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_AND_I64_A64_S |
| 3536 | { 488, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_AND_I64_A64 |
| 3537 | { 487, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_AND_I64_A32_S |
| 3538 | { 486, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_AND_I64_A32 |
| 3539 | { 485, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_AND_I32_A64_S |
| 3540 | { 484, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_AND_I32_A64 |
| 3541 | { 483, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_AND_I32_A32_S |
| 3542 | { 482, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_AND_I32_A32 |
| 3543 | { 481, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_ADD_I64_A64_S |
| 3544 | { 480, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 239, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_ADD_I64_A64 |
| 3545 | { 479, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_ADD_I64_A32_S |
| 3546 | { 478, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_ADD_I64_A32 |
| 3547 | { 477, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_ADD_I32_A64_S |
| 3548 | { 476, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 227, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_ADD_I32_A64 |
| 3549 | { 475, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_ADD_I32_A32_S |
| 3550 | { 474, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 221, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_ADD_I32_A32 |
| 3551 | { 473, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD_I64_A64_S |
| 3552 | { 472, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 216, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD_I64_A64 |
| 3553 | { 471, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD_I64_A32_S |
| 3554 | { 470, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 211, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD_I64_A32 |
| 3555 | { 469, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD_I32_A64_S |
| 3556 | { 468, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 203, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD_I32_A64 |
| 3557 | { 467, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD_I32_A32_S |
| 3558 | { 466, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 195, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD_I32_A32 |
| 3559 | { 465, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD8_U_I64_A64_S |
| 3560 | { 464, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 216, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD8_U_I64_A64 |
| 3561 | { 463, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD8_U_I64_A32_S |
| 3562 | { 462, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 211, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD8_U_I64_A32 |
| 3563 | { 461, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD8_U_I32_A64_S |
| 3564 | { 460, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 203, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD8_U_I32_A64 |
| 3565 | { 459, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD8_U_I32_A32_S |
| 3566 | { 458, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 195, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD8_U_I32_A32 |
| 3567 | { 457, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD32_U_I64_A64_S |
| 3568 | { 456, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 216, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD32_U_I64_A64 |
| 3569 | { 455, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD32_U_I64_A32_S |
| 3570 | { 454, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 211, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD32_U_I64_A32 |
| 3571 | { 453, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD16_U_I64_A64_S |
| 3572 | { 452, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 216, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD16_U_I64_A64 |
| 3573 | { 451, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD16_U_I64_A32_S |
| 3574 | { 450, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 211, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD16_U_I64_A32 |
| 3575 | { 449, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD16_U_I32_A64_S |
| 3576 | { 448, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 203, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD16_U_I32_A64 |
| 3577 | { 447, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 200, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD16_U_I32_A32_S |
| 3578 | { 446, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 195, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD16_U_I32_A32 |
| 3579 | { 445, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 194, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_FENCE_S |
| 3580 | { 444, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 194, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_FENCE |
| 3581 | { 443, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v8i16_S |
| 3582 | { 442, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 192, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v8i16 |
| 3583 | { 441, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v8f16_S |
| 3584 | { 440, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 192, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v8f16 |
| 3585 | { 439, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v4i32_S |
| 3586 | { 438, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 192, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v4i32 |
| 3587 | { 437, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v4f32_S |
| 3588 | { 436, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 192, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v4f32 |
| 3589 | { 435, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v2i64_S |
| 3590 | { 434, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 192, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v2i64 |
| 3591 | { 433, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v2f64_S |
| 3592 | { 432, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 192, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v2f64 |
| 3593 | { 431, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v16i8_S |
| 3594 | { 430, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 192, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v16i8 |
| 3595 | { 429, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_i64_S |
| 3596 | { 428, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 190, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_i64 |
| 3597 | { 427, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_i32_S |
| 3598 | { 426, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 188, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_i32 |
| 3599 | { 425, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_funcref_S |
| 3600 | { 424, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 186, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_funcref |
| 3601 | { 423, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_f64_S |
| 3602 | { 422, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 184, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_f64 |
| 3603 | { 421, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_f32_S |
| 3604 | { 420, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 182, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_f32 |
| 3605 | { 419, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_externref_S |
| 3606 | { 418, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 180, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_externref |
| 3607 | { 417, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_exnref_S |
| 3608 | { 416, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 178, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_exnref |
| 3609 | { 415, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANYTRUE_S |
| 3610 | { 414, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 176, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANYTRUE |
| 3611 | { 413, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_S |
| 3612 | { 412, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_I64_S |
| 3613 | { 411, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_I64 |
| 3614 | { 410, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_I32_S |
| 3615 | { 409, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_I32 |
| 3616 | { 408, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANDNOT_S |
| 3617 | { 407, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANDNOT |
| 3618 | { 406, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND |
| 3619 | { 405, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ALLTRUE_I8x16_S |
| 3620 | { 404, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 176, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ALLTRUE_I8x16 |
| 3621 | { 403, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ALLTRUE_I64x2_S |
| 3622 | { 402, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 176, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ALLTRUE_I64x2 |
| 3623 | { 401, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ALLTRUE_I32x4_S |
| 3624 | { 400, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 176, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ALLTRUE_I32x4 |
| 3625 | { 399, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ALLTRUE_I16x8_S |
| 3626 | { 398, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 176, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ALLTRUE_I16x8 |
| 3627 | { 397, 2, 0, 0, 0, 2, 2, WebAssemblyOpInfoBase + 20, 4, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKUP_S |
| 3628 | { 396, 2, 0, 0, 0, 2, 2, WebAssemblyOpInfoBase + 20, 4, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKUP |
| 3629 | { 395, 2, 0, 0, 0, 2, 2, WebAssemblyOpInfoBase + 20, 4, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKDOWN_S |
| 3630 | { 394, 2, 0, 0, 0, 2, 2, WebAssemblyOpInfoBase + 20, 4, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKDOWN |
| 3631 | { 393, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_SAT_U_I8x16_S |
| 3632 | { 392, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_SAT_U_I8x16 |
| 3633 | { 391, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_SAT_U_I16x8_S |
| 3634 | { 390, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_SAT_U_I16x8 |
| 3635 | { 389, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_SAT_S_I8x16_S |
| 3636 | { 388, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_SAT_S_I8x16 |
| 3637 | { 387, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_SAT_S_I16x8_S |
| 3638 | { 386, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_SAT_S_I16x8 |
| 3639 | { 385, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I8x16_S |
| 3640 | { 384, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I8x16 |
| 3641 | { 383, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I64x2_S |
| 3642 | { 382, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I64x2 |
| 3643 | { 381, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I64_S |
| 3644 | { 380, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 173, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I64 |
| 3645 | { 379, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I32x4_S |
| 3646 | { 378, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I32x4 |
| 3647 | { 377, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I32_S |
| 3648 | { 376, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 170, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I32 |
| 3649 | { 375, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I16x8_S |
| 3650 | { 374, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I16x8 |
| 3651 | { 373, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F64x2_S |
| 3652 | { 372, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F64x2 |
| 3653 | { 371, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F64_S |
| 3654 | { 370, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 167, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F64 |
| 3655 | { 369, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F32x4_S |
| 3656 | { 368, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F32x4 |
| 3657 | { 367, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F32_S |
| 3658 | { 366, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 164, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F32 |
| 3659 | { 365, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F16x8_S |
| 3660 | { 364, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F16x8 |
| 3661 | { 363, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_I8x16_S |
| 3662 | { 362, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_I8x16 |
| 3663 | { 361, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_I64x2_S |
| 3664 | { 360, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_I64x2 |
| 3665 | { 359, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_I32x4_S |
| 3666 | { 358, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_I32x4 |
| 3667 | { 357, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_I16x8_S |
| 3668 | { 356, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_I16x8 |
| 3669 | { 355, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_F64x2_S |
| 3670 | { 354, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_F64x2 |
| 3671 | { 353, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_F64_S |
| 3672 | { 352, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_F64 |
| 3673 | { 351, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_F32x4_S |
| 3674 | { 350, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_F32x4 |
| 3675 | { 349, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_F32_S |
| 3676 | { 348, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 157, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_F32 |
| 3677 | { 347, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_F16x8_S |
| 3678 | { 346, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_F16x8 |
| 3679 | { 345, 0, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // RET_CALL_RESULTS_S |
| 3680 | { 344, 0, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // RET_CALL_RESULTS |
| 3681 | { 343, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COMPILER_FENCE_S |
| 3682 | { 342, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COMPILER_FENCE |
| 3683 | { 341, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 154, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLEANUPRET_S |
| 3684 | { 340, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 154, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLEANUPRET |
| 3685 | { 339, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 152, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CATCHRET_S |
| 3686 | { 338, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 152, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CATCHRET |
| 3687 | { 337, 0, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CALL_RESULTS_S |
| 3688 | { 336, 0, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CALL_RESULTS |
| 3689 | { 335, 1, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 151, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CALL_PARAMS_S |
| 3690 | { 334, 1, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 151, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CALL_PARAMS |
| 3691 | { 333, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBFX |
| 3692 | { 332, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SBFX |
| 3693 | { 331, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMIN |
| 3694 | { 330, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMAX |
| 3695 | { 329, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMIN |
| 3696 | { 328, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMAX |
| 3697 | { 327, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_XOR |
| 3698 | { 326, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_OR |
| 3699 | { 325, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_AND |
| 3700 | { 324, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_MUL |
| 3701 | { 323, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_ADD |
| 3702 | { 322, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMINIMUMNUM |
| 3703 | { 321, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAXIMUMNUM |
| 3704 | { 320, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMINIMUM |
| 3705 | { 319, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAXIMUM |
| 3706 | { 318, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMIN |
| 3707 | { 317, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAX |
| 3708 | { 316, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMUL |
| 3709 | { 315, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FADD |
| 3710 | { 314, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FMUL |
| 3711 | { 313, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FADD |
| 3712 | { 312, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBSANTRAP |
| 3713 | { 311, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DEBUGTRAP |
| 3714 | { 310, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRAP |
| 3715 | { 309, 3, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET_INLINE |
| 3716 | { 308, 3, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BZERO |
| 3717 | { 307, 4, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET |
| 3718 | { 306, 4, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMMOVE |
| 3719 | { 305, 3, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY_INLINE |
| 3720 | { 304, 4, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY |
| 3721 | { 303, 2, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 141, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_WRITE_REGISTER |
| 3722 | { 302, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_READ_REGISTER |
| 3723 | { 301, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FCMPS |
| 3724 | { 300, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FCMP |
| 3725 | { 299, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FLDEXP |
| 3726 | { 298, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSQRT |
| 3727 | { 297, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMA |
| 3728 | { 296, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FREM |
| 3729 | { 295, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FDIV |
| 3730 | { 294, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMUL |
| 3731 | { 293, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSUB |
| 3732 | { 292, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FADD |
| 3733 | { 291, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKRESTORE |
| 3734 | { 290, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKSAVE |
| 3735 | { 289, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DYN_STACKALLOC |
| 3736 | { 288, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_JUMP_TABLE |
| 3737 | { 287, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BLOCK_ADDR |
| 3738 | { 286, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADDRSPACE_CAST |
| 3739 | { 285, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEARBYINT |
| 3740 | { 284, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRINT |
| 3741 | { 283, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFLOOR |
| 3742 | { 282, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSQRT |
| 3743 | { 281, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTANH |
| 3744 | { 280, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINH |
| 3745 | { 279, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOSH |
| 3746 | { 278, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN2 |
| 3747 | { 277, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN |
| 3748 | { 276, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FASIN |
| 3749 | { 275, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FACOS |
| 3750 | { 274, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTAN |
| 3751 | { 273, 3, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINCOS |
| 3752 | { 272, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSIN |
| 3753 | { 271, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOS |
| 3754 | { 270, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCEIL |
| 3755 | { 269, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CLMULH |
| 3756 | { 268, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CLMUL |
| 3757 | { 267, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITREVERSE |
| 3758 | { 266, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BSWAP |
| 3759 | { 265, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTPOP |
| 3760 | { 264, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLS |
| 3761 | { 263, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ_ZERO_POISON |
| 3762 | { 262, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ |
| 3763 | { 261, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ_ZERO_POISON |
| 3764 | { 260, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ |
| 3765 | { 259, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 137, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECTOR_COMPRESS |
| 3766 | { 258, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STEP_VECTOR |
| 3767 | { 257, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SPLAT_VECTOR |
| 3768 | { 256, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 133, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHUFFLE_VECTOR |
| 3769 | { 255, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_VECTOR_ELT |
| 3770 | { 254, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 126, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_VECTOR_ELT |
| 3771 | { 253, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_SUBVECTOR |
| 3772 | { 252, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_SUBVECTOR |
| 3773 | { 251, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VSCALE |
| 3774 | { 250, 3, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRJT |
| 3775 | { 249, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BR |
| 3776 | { 248, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LLROUND |
| 3777 | { 247, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LROUND |
| 3778 | { 246, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABS |
| 3779 | { 245, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMAX |
| 3780 | { 244, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMIN |
| 3781 | { 243, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMAX |
| 3782 | { 242, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMIN |
| 3783 | { 241, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRMASK |
| 3784 | { 240, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTR_ADD |
| 3785 | { 239, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_ROUNDING |
| 3786 | { 238, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_ROUNDING |
| 3787 | { 237, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPMODE |
| 3788 | { 236, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPMODE |
| 3789 | { 235, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPMODE |
| 3790 | { 234, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPENV |
| 3791 | { 233, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPENV |
| 3792 | { 232, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPENV |
| 3793 | { 231, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUMNUM |
| 3794 | { 230, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUMNUM |
| 3795 | { 229, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUM |
| 3796 | { 228, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUM |
| 3797 | { 227, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM_IEEE |
| 3798 | { 226, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM_IEEE |
| 3799 | { 225, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM |
| 3800 | { 224, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM |
| 3801 | { 223, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCANONICALIZE |
| 3802 | { 222, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IS_FPCLASS |
| 3803 | { 221, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOPYSIGN |
| 3804 | { 220, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FABS |
| 3805 | { 219, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI_SAT |
| 3806 | { 218, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI_SAT |
| 3807 | { 217, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UITOFP |
| 3808 | { 216, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SITOFP |
| 3809 | { 215, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI |
| 3810 | { 214, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI |
| 3811 | { 213, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNC |
| 3812 | { 212, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXT |
| 3813 | { 211, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEG |
| 3814 | { 210, 3, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFREXP |
| 3815 | { 209, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLDEXP |
| 3816 | { 208, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG10 |
| 3817 | { 207, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG2 |
| 3818 | { 206, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG |
| 3819 | { 205, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP10 |
| 3820 | { 204, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP2 |
| 3821 | { 203, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP |
| 3822 | { 202, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOWI |
| 3823 | { 201, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOW |
| 3824 | { 200, 3, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMODF |
| 3825 | { 199, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREM |
| 3826 | { 198, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FDIV |
| 3827 | { 197, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAD |
| 3828 | { 196, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMA |
| 3829 | { 195, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMUL |
| 3830 | { 194, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSUB |
| 3831 | { 193, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FADD |
| 3832 | { 192, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIXSAT |
| 3833 | { 191, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIXSAT |
| 3834 | { 190, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIX |
| 3835 | { 189, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIX |
| 3836 | { 188, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIXSAT |
| 3837 | { 187, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIXSAT |
| 3838 | { 186, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIX |
| 3839 | { 185, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIX |
| 3840 | { 184, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSHLSAT |
| 3841 | { 183, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USHLSAT |
| 3842 | { 182, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBSAT |
| 3843 | { 181, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBSAT |
| 3844 | { 180, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDSAT |
| 3845 | { 179, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDSAT |
| 3846 | { 178, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULH |
| 3847 | { 177, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULH |
| 3848 | { 176, 4, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULO |
| 3849 | { 175, 4, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULO |
| 3850 | { 174, 5, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBE |
| 3851 | { 173, 4, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBO |
| 3852 | { 172, 5, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDE |
| 3853 | { 171, 4, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDO |
| 3854 | { 170, 5, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBE |
| 3855 | { 169, 4, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBO |
| 3856 | { 168, 5, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDE |
| 3857 | { 167, 4, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDO |
| 3858 | { 166, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SELECT |
| 3859 | { 165, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UCMP |
| 3860 | { 164, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SCMP |
| 3861 | { 163, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCMP |
| 3862 | { 162, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ICMP |
| 3863 | { 161, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTL |
| 3864 | { 160, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTR |
| 3865 | { 159, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHR |
| 3866 | { 158, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHL |
| 3867 | { 157, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASHR |
| 3868 | { 156, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LSHR |
| 3869 | { 155, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHL |
| 3870 | { 154, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXT |
| 3871 | { 153, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT_INREG |
| 3872 | { 152, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT |
| 3873 | { 151, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VAARG |
| 3874 | { 150, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VASTART |
| 3875 | { 149, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCONSTANT |
| 3876 | { 148, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT |
| 3877 | { 147, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_USAT_U |
| 3878 | { 146, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_U |
| 3879 | { 145, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_S |
| 3880 | { 144, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC |
| 3881 | { 143, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ANYEXT |
| 3882 | { 142, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS |
| 3883 | { 141, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT |
| 3884 | { 140, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_W_SIDE_EFFECTS |
| 3885 | { 139, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC |
| 3886 | { 138, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INVOKE_REGION_START |
| 3887 | { 137, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRINDIRECT |
| 3888 | { 136, 2, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRCOND |
| 3889 | { 135, 4, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 93, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PREFETCH |
| 3890 | { 134, 2, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 20, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FENCE |
| 3891 | { 133, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_SAT |
| 3892 | { 132, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_COND |
| 3893 | { 131, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UDEC_WRAP |
| 3894 | { 130, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UINC_WRAP |
| 3895 | { 129, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUMNUM |
| 3896 | { 128, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUMNUM |
| 3897 | { 127, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUM |
| 3898 | { 126, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUM |
| 3899 | { 125, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMIN |
| 3900 | { 124, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAX |
| 3901 | { 123, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FSUB |
| 3902 | { 122, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FADD |
| 3903 | { 121, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMIN |
| 3904 | { 120, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMAX |
| 3905 | { 119, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MIN |
| 3906 | { 118, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MAX |
| 3907 | { 117, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XOR |
| 3908 | { 116, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_OR |
| 3909 | { 115, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_NAND |
| 3910 | { 114, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_AND |
| 3911 | { 113, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_SUB |
| 3912 | { 112, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_ADD |
| 3913 | { 111, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XCHG |
| 3914 | { 110, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG |
| 3915 | { 109, 5, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 81, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG_WITH_SUCCESS |
| 3916 | { 108, 5, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 76, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_STORE |
| 3917 | { 107, 2, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNCSTORE |
| 3918 | { 106, 2, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STORE |
| 3919 | { 105, 5, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_ZEXTLOAD |
| 3920 | { 104, 5, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_SEXTLOAD |
| 3921 | { 103, 5, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_LOAD |
| 3922 | { 102, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXTLOAD |
| 3923 | { 101, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXTLOAD |
| 3924 | { 100, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXTLOAD |
| 3925 | { 99, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LOAD |
| 3926 | { 98, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READSTEADYCOUNTER |
| 3927 | { 97, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READCYCLECOUNTER |
| 3928 | { 96, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUNDEVEN |
| 3929 | { 95, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LLRINT |
| 3930 | { 94, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LRINT |
| 3931 | { 93, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUND |
| 3932 | { 92, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_TRUNC |
| 3933 | { 91, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_FPTRUNC_ROUND |
| 3934 | { 90, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_FOLD_BARRIER |
| 3935 | { 89, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREEZE |
| 3936 | { 88, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITCAST |
| 3937 | { 87, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTTOPTR |
| 3938 | { 86, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRTOINT |
| 3939 | { 85, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONCAT_VECTORS |
| 3940 | { 84, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR_TRUNC |
| 3941 | { 83, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR |
| 3942 | { 82, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MERGE_VALUES |
| 3943 | { 81, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT |
| 3944 | { 80, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UNMERGE_VALUES |
| 3945 | { 79, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT |
| 3946 | { 78, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_POOL |
| 3947 | { 77, 5, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 52, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRAUTH_GLOBAL_VALUE |
| 3948 | { 76, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GLOBAL_VALUE |
| 3949 | { 75, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRAME_INDEX |
| 3950 | { 74, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PHI |
| 3951 | { 73, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IMPLICIT_DEF |
| 3952 | { 72, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGCEIL |
| 3953 | { 71, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGFLOOR |
| 3954 | { 70, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGCEIL |
| 3955 | { 69, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGFLOOR |
| 3956 | { 68, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDU |
| 3957 | { 67, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDS |
| 3958 | { 66, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_XOR |
| 3959 | { 65, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_OR |
| 3960 | { 64, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_AND |
| 3961 | { 63, 4, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVREM |
| 3962 | { 62, 4, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVREM |
| 3963 | { 61, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UREM |
| 3964 | { 60, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SREM |
| 3965 | { 59, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIV |
| 3966 | { 58, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIV |
| 3967 | { 57, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MUL |
| 3968 | { 56, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SUB |
| 3969 | { 55, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADD |
| 3970 | { 54, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ALIGN |
| 3971 | { 53, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ZEXT |
| 3972 | { 52, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_SEXT |
| 3973 | { 51, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_GLUE |
| 3974 | { 50, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_LOOP |
| 3975 | { 49, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ANCHOR |
| 3976 | { 48, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ENTRY |
| 3977 | { 47, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELOC_NONE |
| 3978 | { 46, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUMP_TABLE_DEBUG_INFO |
| 3979 | { 45, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMBARRIER |
| 3980 | { 44, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAKE_USE |
| 3981 | { 43, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ICALL_BRANCH_FUNNEL |
| 3982 | { 42, 3, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 36, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_15651 |
| 3983 | { 41, 2, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 34, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_15650 |
| 3984 | { 40, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_TAIL_CALL |
| 3985 | { 39, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_EXIT |
| 3986 | { 38, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_RET |
| 3987 | { 37, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_ENTER |
| 3988 | { 36, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_OP |
| 3989 | { 35, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAULTING_OP |
| 3990 | { 34, 2, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 32, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_ESCAPE |
| 3991 | { 33, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STATEPOINT |
| 3992 | { 32, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 29, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_15649 |
| 3993 | { 31, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PREALLOCATED_SETUP |
| 3994 | { 30, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 28, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14348 |
| 3995 | { 29, 6, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 22, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHPOINT |
| 3996 | { 28, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FENTRY_CALL |
| 3997 | { 27, 2, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STACKMAP |
| 3998 | { 26, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 18, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARITH_FENCE |
| 3999 | { 25, 4, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 14, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PSEUDO_PROBE |
| 4000 | { 24, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_END |
| 4001 | { 23, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_START |
| 4002 | { 22, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BUNDLE |
| 4003 | { 21, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 11, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_LANEMASK |
| 4004 | { 20, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY |
| 4005 | { 19, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REG_SEQUENCE |
| 4006 | { 18, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_LABEL |
| 4007 | { 17, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_PHI |
| 4008 | { 16, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_INSTR_REF |
| 4009 | { 15, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE_LIST |
| 4010 | { 14, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE |
| 4011 | { 13, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_TO_REGCLASS |
| 4012 | { 12, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBREG_TO_REG |
| 4013 | { 11, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INIT_UNDEF |
| 4014 | { 10, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // IMPLICIT_DEF |
| 4015 | { 9, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 5, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INSERT_SUBREG |
| 4016 | { 8, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_SUBREG |
| 4017 | { 7, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KILL |
| 4018 | { 6, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANNOTATION_LABEL |
| 4019 | { 5, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GC_LABEL |
| 4020 | { 4, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EH_LABEL |
| 4021 | { 3, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CFI_INSTRUCTION |
| 4022 | { 2, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM_BR |
| 4023 | { 1, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM |
| 4024 | { 0, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PHI |
| 4025 | }, { |
| 4026 | /* 0 */ |
| 4027 | /* 0 */ WebAssembly::SP32, WebAssembly::SP64, WebAssembly::ARGUMENTS, |
| 4028 | /* 3 */ WebAssembly::ARGUMENTS, |
| 4029 | /* 4 */ WebAssembly::SP32, WebAssembly::SP64, WebAssembly::SP32, WebAssembly::SP64, |
| 4030 | /* 8 */ WebAssembly::VALUE_STACK, WebAssembly::VALUE_STACK, |
| 4031 | }, { |
| 4032 | 0 |
| 4033 | }, { |
| 4034 | /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 4035 | /* 1 */ |
| 4036 | /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 4037 | /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 4038 | /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 4039 | /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 4040 | /* 11 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 4041 | /* 14 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 4042 | /* 18 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, |
| 4043 | /* 20 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 4044 | /* 22 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 4045 | /* 28 */ { WebAssembly::wasm_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 }, |
| 4046 | /* 29 */ { WebAssembly::wasm_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 4047 | /* 32 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 4048 | /* 34 */ { WebAssembly::wasm_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 4049 | /* 36 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { WebAssembly::wasm_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 4050 | /* 39 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, |
| 4051 | /* 42 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 4052 | /* 45 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 4053 | /* 49 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 4054 | /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 4055 | /* 52 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 4056 | /* 57 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, |
| 4057 | /* 60 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 4058 | /* 62 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, |
| 4059 | /* 66 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 4060 | /* 68 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 4061 | /* 71 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 4062 | /* 76 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 4063 | /* 81 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 4064 | /* 86 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 4065 | /* 90 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 4066 | /* 93 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_2, 0 }, |
| 4067 | /* 97 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 4068 | /* 100 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 4069 | /* 103 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 4070 | /* 107 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 4071 | /* 111 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 4072 | /* 114 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 4073 | /* 119 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, |
| 4074 | /* 123 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 4075 | /* 126 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, |
| 4076 | /* 130 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, |
| 4077 | /* 133 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 4078 | /* 137 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 4079 | /* 141 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 4080 | /* 143 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, |
| 4081 | /* 147 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 4082 | /* 151 */ { -1, 0, WebAssembly::OPERAND_FUNCTION32, 0 }, |
| 4083 | /* 152 */ { -1, 0, WebAssembly::OPERAND_BASIC_BLOCK, 0 }, { -1, 0, WebAssembly::OPERAND_BASIC_BLOCK, 0 }, |
| 4084 | /* 154 */ { -1, 0, WebAssembly::OPERAND_BASIC_BLOCK, 0 }, |
| 4085 | /* 155 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4086 | /* 157 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4087 | /* 159 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4088 | /* 161 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4089 | /* 164 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4090 | /* 167 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4091 | /* 170 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4092 | /* 173 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4093 | /* 176 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4094 | /* 178 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 4095 | /* 180 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 4096 | /* 182 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 4097 | /* 184 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 4098 | /* 186 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 4099 | /* 188 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 4100 | /* 190 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 4101 | /* 192 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 4102 | /* 194 */ { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, |
| 4103 | /* 195 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4104 | /* 200 */ { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, |
| 4105 | /* 203 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4106 | /* 208 */ { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, |
| 4107 | /* 211 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4108 | /* 216 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4109 | /* 221 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4110 | /* 227 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4111 | /* 233 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4112 | /* 239 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4113 | /* 245 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4114 | /* 252 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4115 | /* 259 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4116 | /* 266 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4117 | /* 273 */ { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4118 | /* 278 */ { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4119 | /* 283 */ { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4120 | /* 288 */ { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4121 | /* 293 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4122 | /* 297 */ { -1, 0, WebAssembly::OPERAND_SIGNATURE, 0 }, |
| 4123 | /* 298 */ { -1, 0, WebAssembly::OPERAND_BASIC_BLOCK, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4124 | /* 300 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4125 | /* 301 */ { -1, 0, WebAssembly::OPERAND_BRLIST, 0 }, |
| 4126 | /* 302 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4127 | /* 303 */ { -1, 0, WebAssembly::OPERAND_TYPEINDEX, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, |
| 4128 | /* 305 */ { -1, 0, WebAssembly::OPERAND_TYPEINDEX, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4129 | /* 307 */ { -1, 0, WebAssembly::OPERAND_TYPEINDEX, 0 }, |
| 4130 | /* 308 */ { -1, 0, WebAssembly::OPERAND_TAG, 0 }, |
| 4131 | /* 309 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4132 | /* 310 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4133 | /* 312 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4134 | /* 314 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, |
| 4135 | /* 316 */ { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, |
| 4136 | /* 317 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_F64IMM, 0 }, |
| 4137 | /* 319 */ { -1, 0, WebAssembly::OPERAND_F64IMM, 0 }, |
| 4138 | /* 320 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, |
| 4139 | /* 322 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, |
| 4140 | /* 323 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_I64IMM, 0 }, |
| 4141 | /* 325 */ { -1, 0, WebAssembly::OPERAND_I64IMM, 0 }, |
| 4142 | /* 326 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, |
| 4143 | /* 331 */ { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, |
| 4144 | /* 335 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_F64IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F64IMM, 0 }, |
| 4145 | /* 338 */ { -1, 0, WebAssembly::OPERAND_F64IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F64IMM, 0 }, |
| 4146 | /* 340 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, |
| 4147 | /* 349 */ { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, |
| 4148 | /* 357 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, |
| 4149 | /* 362 */ { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, |
| 4150 | /* 366 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I64IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I64IMM, 0 }, |
| 4151 | /* 369 */ { -1, 0, WebAssembly::OPERAND_VEC_I64IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I64IMM, 0 }, |
| 4152 | /* 371 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, |
| 4153 | /* 388 */ { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, |
| 4154 | /* 404 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4155 | /* 406 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4156 | /* 408 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4157 | /* 410 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4158 | /* 411 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4159 | /* 412 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4160 | /* 413 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4161 | /* 414 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4162 | /* 415 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4163 | /* 417 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4164 | /* 420 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4165 | /* 423 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4166 | /* 426 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, |
| 4167 | /* 429 */ { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, |
| 4168 | /* 430 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, |
| 4169 | /* 433 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, |
| 4170 | /* 436 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, |
| 4171 | /* 439 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4172 | /* 441 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4173 | /* 443 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4174 | /* 445 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4175 | /* 447 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4176 | /* 449 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4177 | /* 451 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4178 | /* 453 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4179 | /* 455 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4180 | /* 457 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4181 | /* 459 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, |
| 4182 | /* 461 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, |
| 4183 | /* 462 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, |
| 4184 | /* 464 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, |
| 4185 | /* 466 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, |
| 4186 | /* 468 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, |
| 4187 | /* 470 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, |
| 4188 | /* 472 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, |
| 4189 | /* 474 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, |
| 4190 | /* 476 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4191 | /* 478 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4192 | /* 480 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4193 | /* 482 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4194 | /* 484 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4195 | /* 486 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4196 | /* 488 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4197 | /* 490 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4198 | /* 492 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4199 | /* 498 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4200 | /* 500 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4201 | /* 504 */ { -1, 0, WebAssembly::OPERAND_SIGNATURE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4202 | /* 506 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4203 | /* 510 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, |
| 4204 | /* 512 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4205 | /* 516 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, |
| 4206 | /* 518 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4207 | /* 522 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4208 | /* 526 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4209 | /* 530 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4210 | /* 534 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4211 | /* 538 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4212 | /* 542 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4213 | /* 546 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4214 | /* 550 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4215 | /* 556 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, |
| 4216 | /* 559 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4217 | /* 565 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, |
| 4218 | /* 568 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, |
| 4219 | /* 570 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, |
| 4220 | /* 571 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, |
| 4221 | /* 573 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, |
| 4222 | /* 575 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, |
| 4223 | /* 577 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, |
| 4224 | /* 579 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, |
| 4225 | /* 581 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, |
| 4226 | /* 583 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, |
| 4227 | /* 585 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4228 | /* 587 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4229 | /* 589 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4230 | /* 591 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4231 | /* 593 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4232 | /* 595 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4233 | /* 597 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4234 | /* 599 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4235 | /* 601 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4236 | /* 604 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4237 | /* 607 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4238 | /* 610 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4239 | /* 613 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4240 | /* 616 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4241 | /* 619 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4242 | /* 622 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4243 | /* 625 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4244 | /* 630 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, |
| 4245 | /* 632 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4246 | /* 637 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4247 | /* 644 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4248 | /* 651 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4249 | /* 658 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_MEMORDER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4250 | /* 665 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4251 | /* 669 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4252 | /* 673 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4253 | /* 678 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TYPEINDEX, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4254 | /* 681 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_FUNCTION32, 0 }, |
| 4255 | /* 683 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4256 | /* 685 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4257 | /* 687 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4258 | /* 689 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TYPEINDEX, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4259 | /* 692 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4260 | /* 696 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4261 | /* 700 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4262 | /* 704 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4263 | /* 708 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4264 | /* 712 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4265 | /* 716 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4266 | /* 720 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4267 | /* 724 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4268 | /* 728 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4269 | /* 732 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4270 | /* 736 */ { -1, 0, WebAssembly::OPERAND_VALTYPE_LIST, 0 }, |
| 4271 | /* 737 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4272 | /* 741 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4273 | /* 744 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, |
| 4274 | /* 763 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4275 | /* 765 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4276 | /* 767 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4277 | /* 769 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4278 | /* 771 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4279 | /* 775 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4280 | /* 779 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4281 | /* 783 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4282 | /* 787 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4283 | /* 791 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4284 | /* 795 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4285 | /* 799 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4286 | /* 803 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4287 | /* 808 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4288 | /* 813 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4289 | /* 817 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4290 | /* 821 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4291 | /* 826 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, |
| 4292 | /* 828 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4293 | /* 832 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, |
| 4294 | /* 833 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4295 | /* 837 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4296 | /* 841 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4297 | /* 844 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4298 | /* 847 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4299 | /* 850 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4300 | /* 854 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4301 | /* 858 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4302 | /* 862 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4303 | /* 865 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4304 | /* 868 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4305 | /* 871 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, |
| 4306 | /* 873 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4307 | /* 876 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4308 | /* 879 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4309 | /* 882 */ { -1, 0, WebAssembly::OPERAND_SIGNATURE, 0 }, { -1, 0, WebAssembly::OPERAND_CATCH_LIST, 0 }, |
| 4310 | /* 884 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4311 | /* 887 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4312 | } |
| 4313 | }; |
| 4314 | |
| 4315 | |
| 4316 | #ifdef __GNUC__ |
| 4317 | #pragma GCC diagnostic push |
| 4318 | #pragma GCC diagnostic ignored "-Woverlength-strings" |
| 4319 | #endif |
| 4320 | extern const char WebAssemblyInstrNameData[] = { |
| 4321 | /* 0 */ "G_FLOG10\000" |
| 4322 | /* 9 */ "G_FEXP10\000" |
| 4323 | /* 18 */ "LOAD_F16_F32_A32\000" |
| 4324 | /* 35 */ "STORE_F16_F32_A32\000" |
| 4325 | /* 53 */ "LOAD_F32_A32\000" |
| 4326 | /* 66 */ "STORE_F32_A32\000" |
| 4327 | /* 80 */ "ATOMIC_STORE16_I32_A32\000" |
| 4328 | /* 103 */ "ATOMIC_STORE8_I32_A32\000" |
| 4329 | /* 125 */ "ATOMIC_RMW16_U_SUB_I32_A32\000" |
| 4330 | /* 152 */ "ATOMIC_RMW8_U_SUB_I32_A32\000" |
| 4331 | /* 178 */ "ATOMIC_RMW_SUB_I32_A32\000" |
| 4332 | /* 201 */ "ATOMIC_LOAD_I32_A32\000" |
| 4333 | /* 221 */ "ATOMIC_RMW16_U_ADD_I32_A32\000" |
| 4334 | /* 248 */ "ATOMIC_RMW8_U_ADD_I32_A32\000" |
| 4335 | /* 274 */ "ATOMIC_RMW_ADD_I32_A32\000" |
| 4336 | /* 297 */ "ATOMIC_RMW16_U_AND_I32_A32\000" |
| 4337 | /* 324 */ "ATOMIC_RMW8_U_AND_I32_A32\000" |
| 4338 | /* 350 */ "ATOMIC_RMW_AND_I32_A32\000" |
| 4339 | /* 373 */ "ATOMIC_STORE_I32_A32\000" |
| 4340 | /* 394 */ "ATOMIC_RMW16_U_CMPXCHG_I32_A32\000" |
| 4341 | /* 425 */ "ATOMIC_RMW8_U_CMPXCHG_I32_A32\000" |
| 4342 | /* 455 */ "ATOMIC_RMW_CMPXCHG_I32_A32\000" |
| 4343 | /* 482 */ "ATOMIC_RMW16_U_XCHG_I32_A32\000" |
| 4344 | /* 510 */ "ATOMIC_RMW8_U_XCHG_I32_A32\000" |
| 4345 | /* 537 */ "ATOMIC_RMW_XCHG_I32_A32\000" |
| 4346 | /* 561 */ "ATOMIC_RMW16_U_XOR_I32_A32\000" |
| 4347 | /* 588 */ "ATOMIC_RMW8_U_XOR_I32_A32\000" |
| 4348 | /* 614 */ "ATOMIC_RMW_XOR_I32_A32\000" |
| 4349 | /* 637 */ "ATOMIC_RMW16_U_OR_I32_A32\000" |
| 4350 | /* 663 */ "ATOMIC_RMW8_U_OR_I32_A32\000" |
| 4351 | /* 688 */ "ATOMIC_RMW_OR_I32_A32\000" |
| 4352 | /* 710 */ "LOAD16_S_I32_A32\000" |
| 4353 | /* 727 */ "LOAD8_S_I32_A32\000" |
| 4354 | /* 743 */ "ATOMIC_LOAD16_U_I32_A32\000" |
| 4355 | /* 767 */ "ATOMIC_LOAD8_U_I32_A32\000" |
| 4356 | /* 790 */ "MEMORY_ATOMIC_WAIT32_A32\000" |
| 4357 | /* 815 */ "LOAD_LANE_32_A32\000" |
| 4358 | /* 832 */ "LOAD_ZERO_32_A32\000" |
| 4359 | /* 849 */ "STORE_LANE_I64x2_A32\000" |
| 4360 | /* 870 */ "LOAD_EXTEND_S_I64x2_A32\000" |
| 4361 | /* 894 */ "LOAD_EXTEND_U_I64x2_A32\000" |
| 4362 | /* 918 */ "LOAD_F64_A32\000" |
| 4363 | /* 931 */ "STORE_F64_A32\000" |
| 4364 | /* 945 */ "ATOMIC_STORE32_I64_A32\000" |
| 4365 | /* 968 */ "ATOMIC_STORE16_I64_A32\000" |
| 4366 | /* 991 */ "ATOMIC_STORE8_I64_A32\000" |
| 4367 | /* 1013 */ "ATOMIC_RMW32_U_SUB_I64_A32\000" |
| 4368 | /* 1040 */ "ATOMIC_RMW16_U_SUB_I64_A32\000" |
| 4369 | /* 1067 */ "ATOMIC_RMW8_U_SUB_I64_A32\000" |
| 4370 | /* 1093 */ "ATOMIC_RMW_SUB_I64_A32\000" |
| 4371 | /* 1116 */ "ATOMIC_LOAD_I64_A32\000" |
| 4372 | /* 1136 */ "ATOMIC_RMW32_U_ADD_I64_A32\000" |
| 4373 | /* 1163 */ "ATOMIC_RMW16_U_ADD_I64_A32\000" |
| 4374 | /* 1190 */ "ATOMIC_RMW8_U_ADD_I64_A32\000" |
| 4375 | /* 1216 */ "ATOMIC_RMW_ADD_I64_A32\000" |
| 4376 | /* 1239 */ "ATOMIC_RMW32_U_AND_I64_A32\000" |
| 4377 | /* 1266 */ "ATOMIC_RMW16_U_AND_I64_A32\000" |
| 4378 | /* 1293 */ "ATOMIC_RMW8_U_AND_I64_A32\000" |
| 4379 | /* 1319 */ "ATOMIC_RMW_AND_I64_A32\000" |
| 4380 | /* 1342 */ "ATOMIC_STORE_I64_A32\000" |
| 4381 | /* 1363 */ "ATOMIC_RMW32_U_CMPXCHG_I64_A32\000" |
| 4382 | /* 1394 */ "ATOMIC_RMW16_U_CMPXCHG_I64_A32\000" |
| 4383 | /* 1425 */ "ATOMIC_RMW8_U_CMPXCHG_I64_A32\000" |
| 4384 | /* 1455 */ "ATOMIC_RMW_CMPXCHG_I64_A32\000" |
| 4385 | /* 1482 */ "ATOMIC_RMW32_U_XCHG_I64_A32\000" |
| 4386 | /* 1510 */ "ATOMIC_RMW16_U_XCHG_I64_A32\000" |
| 4387 | /* 1538 */ "ATOMIC_RMW8_U_XCHG_I64_A32\000" |
| 4388 | /* 1565 */ "ATOMIC_RMW_XCHG_I64_A32\000" |
| 4389 | /* 1589 */ "ATOMIC_RMW32_U_XOR_I64_A32\000" |
| 4390 | /* 1616 */ "ATOMIC_RMW16_U_XOR_I64_A32\000" |
| 4391 | /* 1643 */ "ATOMIC_RMW8_U_XOR_I64_A32\000" |
| 4392 | /* 1669 */ "ATOMIC_RMW_XOR_I64_A32\000" |
| 4393 | /* 1692 */ "ATOMIC_RMW32_U_OR_I64_A32\000" |
| 4394 | /* 1718 */ "ATOMIC_RMW16_U_OR_I64_A32\000" |
| 4395 | /* 1744 */ "ATOMIC_RMW8_U_OR_I64_A32\000" |
| 4396 | /* 1769 */ "ATOMIC_RMW_OR_I64_A32\000" |
| 4397 | /* 1791 */ "LOAD32_S_I64_A32\000" |
| 4398 | /* 1808 */ "LOAD16_S_I64_A32\000" |
| 4399 | /* 1825 */ "LOAD8_S_I64_A32\000" |
| 4400 | /* 1841 */ "ATOMIC_LOAD32_U_I64_A32\000" |
| 4401 | /* 1865 */ "ATOMIC_LOAD16_U_I64_A32\000" |
| 4402 | /* 1889 */ "ATOMIC_LOAD8_U_I64_A32\000" |
| 4403 | /* 1912 */ "MEMORY_ATOMIC_WAIT64_A32\000" |
| 4404 | /* 1937 */ "LOAD_LANE_64_A32\000" |
| 4405 | /* 1954 */ "LOAD_ZERO_64_A32\000" |
| 4406 | /* 1971 */ "STORE_LANE_I32x4_A32\000" |
| 4407 | /* 1992 */ "LOAD_EXTEND_S_I32x4_A32\000" |
| 4408 | /* 2016 */ "LOAD_EXTEND_U_I32x4_A32\000" |
| 4409 | /* 2040 */ "LOAD_LANE_16_A32\000" |
| 4410 | /* 2057 */ "STORE_LANE_I8x16_A32\000" |
| 4411 | /* 2078 */ "LOAD_V128_A32\000" |
| 4412 | /* 2092 */ "STORE_V128_A32\000" |
| 4413 | /* 2107 */ "LOAD_LANE_8_A32\000" |
| 4414 | /* 2123 */ "STORE_LANE_I16x8_A32\000" |
| 4415 | /* 2144 */ "LOAD_EXTEND_S_I16x8_A32\000" |
| 4416 | /* 2168 */ "LOAD_EXTEND_U_I16x8_A32\000" |
| 4417 | /* 2192 */ "anonymous_14793MEMORY_SIZE_A32\000" |
| 4418 | /* 2223 */ "MEMORY_FILL_A32\000" |
| 4419 | /* 2239 */ "LOAD32_SPLAT_A32\000" |
| 4420 | /* 2256 */ "LOAD64_SPLAT_A32\000" |
| 4421 | /* 2273 */ "LOAD16_SPLAT_A32\000" |
| 4422 | /* 2290 */ "LOAD8_SPLAT_A32\000" |
| 4423 | /* 2306 */ "MEMSET_A32\000" |
| 4424 | /* 2317 */ "MEMORY_INIT_A32\000" |
| 4425 | /* 2333 */ "anonymous_14793MEMORY_GROW_A32\000" |
| 4426 | /* 2364 */ "MEMORY_ATOMIC_NOTIFY_A32\000" |
| 4427 | /* 2389 */ "MEMCPY_A32\000" |
| 4428 | /* 2400 */ "MEMORY_COPY_A32\000" |
| 4429 | /* 2416 */ "FP_TO_SINT_I32_F32\000" |
| 4430 | /* 2435 */ "FP_TO_UINT_I32_F32\000" |
| 4431 | /* 2454 */ "FP_TO_SINT_I64_F32\000" |
| 4432 | /* 2473 */ "FP_TO_UINT_I64_F32\000" |
| 4433 | /* 2492 */ "SUB_F32\000" |
| 4434 | /* 2500 */ "TRUNC_F32\000" |
| 4435 | /* 2510 */ "ADD_F32\000" |
| 4436 | /* 2518 */ "LOCAL_TEE_F32\000" |
| 4437 | /* 2532 */ "GE_F32\000" |
| 4438 | /* 2539 */ "LE_F32\000" |
| 4439 | /* 2546 */ "NE_F32\000" |
| 4440 | /* 2553 */ "F64_PROMOTE_F32\000" |
| 4441 | /* 2569 */ "NEG_F32\000" |
| 4442 | /* 2577 */ "CEIL_F32\000" |
| 4443 | /* 2586 */ "MUL_F32\000" |
| 4444 | /* 2594 */ "COPYSIGN_F32\000" |
| 4445 | /* 2607 */ "MIN_F32\000" |
| 4446 | /* 2615 */ "DROP_F32\000" |
| 4447 | /* 2624 */ "EQ_F32\000" |
| 4448 | /* 2631 */ "FLOOR_F32\000" |
| 4449 | /* 2641 */ "ABS_F32\000" |
| 4450 | /* 2649 */ "I32_TRUNC_S_F32\000" |
| 4451 | /* 2665 */ "I64_TRUNC_S_F32\000" |
| 4452 | /* 2681 */ "I32_TRUNC_S_SAT_F32\000" |
| 4453 | /* 2701 */ "I64_TRUNC_S_SAT_F32\000" |
| 4454 | /* 2721 */ "I32_TRUNC_U_SAT_F32\000" |
| 4455 | /* 2741 */ "I64_TRUNC_U_SAT_F32\000" |
| 4456 | /* 2761 */ "SELECT_F32\000" |
| 4457 | /* 2772 */ "GLOBAL_GET_F32\000" |
| 4458 | /* 2787 */ "LOCAL_GET_F32\000" |
| 4459 | /* 2801 */ "I32_REINTERPRET_F32\000" |
| 4460 | /* 2821 */ "GLOBAL_SET_F32\000" |
| 4461 | /* 2836 */ "LOCAL_SET_F32\000" |
| 4462 | /* 2850 */ "GT_F32\000" |
| 4463 | /* 2857 */ "LT_F32\000" |
| 4464 | /* 2864 */ "SQRT_F32\000" |
| 4465 | /* 2873 */ "NEAREST_F32\000" |
| 4466 | /* 2885 */ "CONST_F32\000" |
| 4467 | /* 2895 */ "I32_TRUNC_U_F32\000" |
| 4468 | /* 2911 */ "I64_TRUNC_U_F32\000" |
| 4469 | /* 2927 */ "DIV_F32\000" |
| 4470 | /* 2935 */ "MAX_F32\000" |
| 4471 | /* 2943 */ "COPY_F32\000" |
| 4472 | /* 2952 */ "SUB_I32\000" |
| 4473 | /* 2960 */ "ADD_I32\000" |
| 4474 | /* 2968 */ "AND_I32\000" |
| 4475 | /* 2976 */ "LOCAL_TEE_I32\000" |
| 4476 | /* 2990 */ "BR_TABLE_I32\000" |
| 4477 | /* 3003 */ "NE_I32\000" |
| 4478 | /* 3010 */ "SHL_I32\000" |
| 4479 | /* 3018 */ "ROTL_I32\000" |
| 4480 | /* 3027 */ "MUL_I32\000" |
| 4481 | /* 3035 */ "DROP_I32\000" |
| 4482 | /* 3044 */ "EQ_I32\000" |
| 4483 | /* 3051 */ "XOR_I32\000" |
| 4484 | /* 3059 */ "ROTR_I32\000" |
| 4485 | /* 3068 */ "I32_EXTEND16_S_I32\000" |
| 4486 | /* 3087 */ "I32_EXTEND8_S_I32\000" |
| 4487 | /* 3105 */ "I64_EXTEND_S_I32\000" |
| 4488 | /* 3122 */ "GE_S_I32\000" |
| 4489 | /* 3131 */ "LE_S_I32\000" |
| 4490 | /* 3140 */ "REM_S_I32\000" |
| 4491 | /* 3150 */ "SHR_S_I32\000" |
| 4492 | /* 3160 */ "GT_S_I32\000" |
| 4493 | /* 3169 */ "LT_S_I32\000" |
| 4494 | /* 3178 */ "F32_CONVERT_S_I32\000" |
| 4495 | /* 3196 */ "F64_CONVERT_S_I32\000" |
| 4496 | /* 3214 */ "DIV_S_I32\000" |
| 4497 | /* 3224 */ "SELECT_I32\000" |
| 4498 | /* 3235 */ "GLOBAL_GET_I32\000" |
| 4499 | /* 3250 */ "LOCAL_GET_I32\000" |
| 4500 | /* 3264 */ "F32_REINTERPRET_I32\000" |
| 4501 | /* 3284 */ "GLOBAL_SET_I32\000" |
| 4502 | /* 3299 */ "LOCAL_SET_I32\000" |
| 4503 | /* 3313 */ "POPCNT_I32\000" |
| 4504 | /* 3324 */ "CONST_I32\000" |
| 4505 | /* 3334 */ "I64_EXTEND_U_I32\000" |
| 4506 | /* 3351 */ "GE_U_I32\000" |
| 4507 | /* 3360 */ "LE_U_I32\000" |
| 4508 | /* 3369 */ "REM_U_I32\000" |
| 4509 | /* 3379 */ "SHR_U_I32\000" |
| 4510 | /* 3389 */ "GT_U_I32\000" |
| 4511 | /* 3398 */ "LT_U_I32\000" |
| 4512 | /* 3407 */ "F32_CONVERT_U_I32\000" |
| 4513 | /* 3425 */ "F64_CONVERT_U_I32\000" |
| 4514 | /* 3443 */ "DIV_U_I32\000" |
| 4515 | /* 3453 */ "COPY_I32\000" |
| 4516 | /* 3462 */ "CLZ_I32\000" |
| 4517 | /* 3470 */ "EQZ_I32\000" |
| 4518 | /* 3478 */ "CTZ_I32\000" |
| 4519 | /* 3486 */ "ARGUMENT_v4f32\000" |
| 4520 | /* 3501 */ "ARGUMENT_f32\000" |
| 4521 | /* 3514 */ "ARGUMENT_v4i32\000" |
| 4522 | /* 3529 */ "ARGUMENT_i32\000" |
| 4523 | /* 3542 */ "G_FLOG2\000" |
| 4524 | /* 3550 */ "G_FATAN2\000" |
| 4525 | /* 3559 */ "G_FEXP2\000" |
| 4526 | /* 3567 */ "CONST_V128_F64x2\000" |
| 4527 | /* 3584 */ "SUB_F64x2\000" |
| 4528 | /* 3594 */ "TRUNC_F64x2\000" |
| 4529 | /* 3606 */ "NMADD_F64x2\000" |
| 4530 | /* 3618 */ "GE_F64x2\000" |
| 4531 | /* 3627 */ "LE_F64x2\000" |
| 4532 | /* 3636 */ "REPLACE_LANE_F64x2\000" |
| 4533 | /* 3655 */ "EXTRACT_LANE_F64x2\000" |
| 4534 | /* 3674 */ "NEG_F64x2\000" |
| 4535 | /* 3684 */ "CEIL_F64x2\000" |
| 4536 | /* 3695 */ "MUL_F64x2\000" |
| 4537 | /* 3705 */ "SIMD_RELAXED_FMIN_F64x2\000" |
| 4538 | /* 3729 */ "PMIN_F64x2\000" |
| 4539 | /* 3740 */ "EQ_F64x2\000" |
| 4540 | /* 3749 */ "FLOOR_F64x2\000" |
| 4541 | /* 3761 */ "ABS_F64x2\000" |
| 4542 | /* 3771 */ "SPLAT_F64x2\000" |
| 4543 | /* 3783 */ "GT_F64x2\000" |
| 4544 | /* 3792 */ "LT_F64x2\000" |
| 4545 | /* 3801 */ "SQRT_F64x2\000" |
| 4546 | /* 3812 */ "NEAREST_F64x2\000" |
| 4547 | /* 3826 */ "DIV_F64x2\000" |
| 4548 | /* 3836 */ "SIMD_RELAXED_FMAX_F64x2\000" |
| 4549 | /* 3860 */ "PMAX_F64x2\000" |
| 4550 | /* 3871 */ "convert_low_s_F64x2\000" |
| 4551 | /* 3891 */ "convert_low_u_F64x2\000" |
| 4552 | /* 3911 */ "promote_low_F64x2\000" |
| 4553 | /* 3929 */ "CONST_V128_I64x2\000" |
| 4554 | /* 3946 */ "SUB_I64x2\000" |
| 4555 | /* 3956 */ "ADD_I64x2\000" |
| 4556 | /* 3966 */ "REPLACE_LANE_I64x2\000" |
| 4557 | /* 3985 */ "EXTRACT_LANE_I64x2\000" |
| 4558 | /* 4004 */ "ALLTRUE_I64x2\000" |
| 4559 | /* 4018 */ "NEG_I64x2\000" |
| 4560 | /* 4028 */ "BITMASK_I64x2\000" |
| 4561 | /* 4042 */ "SHL_I64x2\000" |
| 4562 | /* 4052 */ "MUL_I64x2\000" |
| 4563 | /* 4062 */ "EQ_I64x2\000" |
| 4564 | /* 4071 */ "ABS_I64x2\000" |
| 4565 | /* 4081 */ "GE_S_I64x2\000" |
| 4566 | /* 4092 */ "LE_S_I64x2\000" |
| 4567 | /* 4103 */ "EXTMUL_HIGH_S_I64x2\000" |
| 4568 | /* 4123 */ "SHR_S_I64x2\000" |
| 4569 | /* 4135 */ "GT_S_I64x2\000" |
| 4570 | /* 4146 */ "LT_S_I64x2\000" |
| 4571 | /* 4157 */ "EXTMUL_LOW_S_I64x2\000" |
| 4572 | /* 4176 */ "SPLAT_I64x2\000" |
| 4573 | /* 4188 */ "LANESELECT_I64x2\000" |
| 4574 | /* 4205 */ "EXTMUL_HIGH_U_I64x2\000" |
| 4575 | /* 4225 */ "SHR_U_I64x2\000" |
| 4576 | /* 4237 */ "EXTMUL_LOW_U_I64x2\000" |
| 4577 | /* 4256 */ "extend_high_s_I64x2\000" |
| 4578 | /* 4276 */ "extend_low_s_I64x2\000" |
| 4579 | /* 4295 */ "extend_high_u_I64x2\000" |
| 4580 | /* 4315 */ "extend_low_u_I64x2\000" |
| 4581 | /* 4334 */ "LOAD_F16_F32_A64\000" |
| 4582 | /* 4351 */ "STORE_F16_F32_A64\000" |
| 4583 | /* 4369 */ "LOAD_F32_A64\000" |
| 4584 | /* 4382 */ "STORE_F32_A64\000" |
| 4585 | /* 4396 */ "ATOMIC_STORE16_I32_A64\000" |
| 4586 | /* 4419 */ "ATOMIC_STORE8_I32_A64\000" |
| 4587 | /* 4441 */ "ATOMIC_RMW16_U_SUB_I32_A64\000" |
| 4588 | /* 4468 */ "ATOMIC_RMW8_U_SUB_I32_A64\000" |
| 4589 | /* 4494 */ "ATOMIC_RMW_SUB_I32_A64\000" |
| 4590 | /* 4517 */ "ATOMIC_LOAD_I32_A64\000" |
| 4591 | /* 4537 */ "ATOMIC_RMW16_U_ADD_I32_A64\000" |
| 4592 | /* 4564 */ "ATOMIC_RMW8_U_ADD_I32_A64\000" |
| 4593 | /* 4590 */ "ATOMIC_RMW_ADD_I32_A64\000" |
| 4594 | /* 4613 */ "ATOMIC_RMW16_U_AND_I32_A64\000" |
| 4595 | /* 4640 */ "ATOMIC_RMW8_U_AND_I32_A64\000" |
| 4596 | /* 4666 */ "ATOMIC_RMW_AND_I32_A64\000" |
| 4597 | /* 4689 */ "ATOMIC_STORE_I32_A64\000" |
| 4598 | /* 4710 */ "ATOMIC_RMW16_U_CMPXCHG_I32_A64\000" |
| 4599 | /* 4741 */ "ATOMIC_RMW8_U_CMPXCHG_I32_A64\000" |
| 4600 | /* 4771 */ "ATOMIC_RMW_CMPXCHG_I32_A64\000" |
| 4601 | /* 4798 */ "ATOMIC_RMW16_U_XCHG_I32_A64\000" |
| 4602 | /* 4826 */ "ATOMIC_RMW8_U_XCHG_I32_A64\000" |
| 4603 | /* 4853 */ "ATOMIC_RMW_XCHG_I32_A64\000" |
| 4604 | /* 4877 */ "ATOMIC_RMW16_U_XOR_I32_A64\000" |
| 4605 | /* 4904 */ "ATOMIC_RMW8_U_XOR_I32_A64\000" |
| 4606 | /* 4930 */ "ATOMIC_RMW_XOR_I32_A64\000" |
| 4607 | /* 4953 */ "ATOMIC_RMW16_U_OR_I32_A64\000" |
| 4608 | /* 4979 */ "ATOMIC_RMW8_U_OR_I32_A64\000" |
| 4609 | /* 5004 */ "ATOMIC_RMW_OR_I32_A64\000" |
| 4610 | /* 5026 */ "LOAD16_S_I32_A64\000" |
| 4611 | /* 5043 */ "LOAD8_S_I32_A64\000" |
| 4612 | /* 5059 */ "ATOMIC_LOAD16_U_I32_A64\000" |
| 4613 | /* 5083 */ "ATOMIC_LOAD8_U_I32_A64\000" |
| 4614 | /* 5106 */ "MEMORY_ATOMIC_WAIT32_A64\000" |
| 4615 | /* 5131 */ "LOAD_LANE_32_A64\000" |
| 4616 | /* 5148 */ "LOAD_ZERO_32_A64\000" |
| 4617 | /* 5165 */ "STORE_LANE_I64x2_A64\000" |
| 4618 | /* 5186 */ "LOAD_EXTEND_S_I64x2_A64\000" |
| 4619 | /* 5210 */ "LOAD_EXTEND_U_I64x2_A64\000" |
| 4620 | /* 5234 */ "LOAD_F64_A64\000" |
| 4621 | /* 5247 */ "STORE_F64_A64\000" |
| 4622 | /* 5261 */ "ATOMIC_STORE32_I64_A64\000" |
| 4623 | /* 5284 */ "ATOMIC_STORE16_I64_A64\000" |
| 4624 | /* 5307 */ "ATOMIC_STORE8_I64_A64\000" |
| 4625 | /* 5329 */ "ATOMIC_RMW32_U_SUB_I64_A64\000" |
| 4626 | /* 5356 */ "ATOMIC_RMW16_U_SUB_I64_A64\000" |
| 4627 | /* 5383 */ "ATOMIC_RMW8_U_SUB_I64_A64\000" |
| 4628 | /* 5409 */ "ATOMIC_RMW_SUB_I64_A64\000" |
| 4629 | /* 5432 */ "ATOMIC_LOAD_I64_A64\000" |
| 4630 | /* 5452 */ "ATOMIC_RMW32_U_ADD_I64_A64\000" |
| 4631 | /* 5479 */ "ATOMIC_RMW16_U_ADD_I64_A64\000" |
| 4632 | /* 5506 */ "ATOMIC_RMW8_U_ADD_I64_A64\000" |
| 4633 | /* 5532 */ "ATOMIC_RMW_ADD_I64_A64\000" |
| 4634 | /* 5555 */ "ATOMIC_RMW32_U_AND_I64_A64\000" |
| 4635 | /* 5582 */ "ATOMIC_RMW16_U_AND_I64_A64\000" |
| 4636 | /* 5609 */ "ATOMIC_RMW8_U_AND_I64_A64\000" |
| 4637 | /* 5635 */ "ATOMIC_RMW_AND_I64_A64\000" |
| 4638 | /* 5658 */ "ATOMIC_STORE_I64_A64\000" |
| 4639 | /* 5679 */ "ATOMIC_RMW32_U_CMPXCHG_I64_A64\000" |
| 4640 | /* 5710 */ "ATOMIC_RMW16_U_CMPXCHG_I64_A64\000" |
| 4641 | /* 5741 */ "ATOMIC_RMW8_U_CMPXCHG_I64_A64\000" |
| 4642 | /* 5771 */ "ATOMIC_RMW_CMPXCHG_I64_A64\000" |
| 4643 | /* 5798 */ "ATOMIC_RMW32_U_XCHG_I64_A64\000" |
| 4644 | /* 5826 */ "ATOMIC_RMW16_U_XCHG_I64_A64\000" |
| 4645 | /* 5854 */ "ATOMIC_RMW8_U_XCHG_I64_A64\000" |
| 4646 | /* 5881 */ "ATOMIC_RMW_XCHG_I64_A64\000" |
| 4647 | /* 5905 */ "ATOMIC_RMW32_U_XOR_I64_A64\000" |
| 4648 | /* 5932 */ "ATOMIC_RMW16_U_XOR_I64_A64\000" |
| 4649 | /* 5959 */ "ATOMIC_RMW8_U_XOR_I64_A64\000" |
| 4650 | /* 5985 */ "ATOMIC_RMW_XOR_I64_A64\000" |
| 4651 | /* 6008 */ "ATOMIC_RMW32_U_OR_I64_A64\000" |
| 4652 | /* 6034 */ "ATOMIC_RMW16_U_OR_I64_A64\000" |
| 4653 | /* 6060 */ "ATOMIC_RMW8_U_OR_I64_A64\000" |
| 4654 | /* 6085 */ "ATOMIC_RMW_OR_I64_A64\000" |
| 4655 | /* 6107 */ "LOAD32_S_I64_A64\000" |
| 4656 | /* 6124 */ "LOAD16_S_I64_A64\000" |
| 4657 | /* 6141 */ "LOAD8_S_I64_A64\000" |
| 4658 | /* 6157 */ "ATOMIC_LOAD32_U_I64_A64\000" |
| 4659 | /* 6181 */ "ATOMIC_LOAD16_U_I64_A64\000" |
| 4660 | /* 6205 */ "ATOMIC_LOAD8_U_I64_A64\000" |
| 4661 | /* 6228 */ "MEMORY_ATOMIC_WAIT64_A64\000" |
| 4662 | /* 6253 */ "LOAD_LANE_64_A64\000" |
| 4663 | /* 6270 */ "LOAD_ZERO_64_A64\000" |
| 4664 | /* 6287 */ "STORE_LANE_I32x4_A64\000" |
| 4665 | /* 6308 */ "LOAD_EXTEND_S_I32x4_A64\000" |
| 4666 | /* 6332 */ "LOAD_EXTEND_U_I32x4_A64\000" |
| 4667 | /* 6356 */ "LOAD_LANE_16_A64\000" |
| 4668 | /* 6373 */ "STORE_LANE_I8x16_A64\000" |
| 4669 | /* 6394 */ "LOAD_V128_A64\000" |
| 4670 | /* 6408 */ "STORE_V128_A64\000" |
| 4671 | /* 6423 */ "LOAD_LANE_8_A64\000" |
| 4672 | /* 6439 */ "STORE_LANE_I16x8_A64\000" |
| 4673 | /* 6460 */ "LOAD_EXTEND_S_I16x8_A64\000" |
| 4674 | /* 6484 */ "LOAD_EXTEND_U_I16x8_A64\000" |
| 4675 | /* 6508 */ "anonymous_14794MEMORY_SIZE_A64\000" |
| 4676 | /* 6539 */ "MEMORY_FILL_A64\000" |
| 4677 | /* 6555 */ "LOAD32_SPLAT_A64\000" |
| 4678 | /* 6572 */ "LOAD64_SPLAT_A64\000" |
| 4679 | /* 6589 */ "LOAD16_SPLAT_A64\000" |
| 4680 | /* 6606 */ "LOAD8_SPLAT_A64\000" |
| 4681 | /* 6622 */ "MEMSET_A64\000" |
| 4682 | /* 6633 */ "MEMORY_INIT_A64\000" |
| 4683 | /* 6649 */ "anonymous_14794MEMORY_GROW_A64\000" |
| 4684 | /* 6680 */ "MEMORY_ATOMIC_NOTIFY_A64\000" |
| 4685 | /* 6705 */ "MEMCPY_A64\000" |
| 4686 | /* 6716 */ "MEMORY_COPY_A64\000" |
| 4687 | /* 6732 */ "FP_TO_SINT_I32_F64\000" |
| 4688 | /* 6751 */ "FP_TO_UINT_I32_F64\000" |
| 4689 | /* 6770 */ "FP_TO_SINT_I64_F64\000" |
| 4690 | /* 6789 */ "FP_TO_UINT_I64_F64\000" |
| 4691 | /* 6808 */ "SUB_F64\000" |
| 4692 | /* 6816 */ "TRUNC_F64\000" |
| 4693 | /* 6826 */ "ADD_F64\000" |
| 4694 | /* 6834 */ "LOCAL_TEE_F64\000" |
| 4695 | /* 6848 */ "GE_F64\000" |
| 4696 | /* 6855 */ "LE_F64\000" |
| 4697 | /* 6862 */ "NE_F64\000" |
| 4698 | /* 6869 */ "F32_DEMOTE_F64\000" |
| 4699 | /* 6884 */ "NEG_F64\000" |
| 4700 | /* 6892 */ "CEIL_F64\000" |
| 4701 | /* 6901 */ "MUL_F64\000" |
| 4702 | /* 6909 */ "COPYSIGN_F64\000" |
| 4703 | /* 6922 */ "MIN_F64\000" |
| 4704 | /* 6930 */ "DROP_F64\000" |
| 4705 | /* 6939 */ "EQ_F64\000" |
| 4706 | /* 6946 */ "FLOOR_F64\000" |
| 4707 | /* 6956 */ "ABS_F64\000" |
| 4708 | /* 6964 */ "I32_TRUNC_S_F64\000" |
| 4709 | /* 6980 */ "I64_TRUNC_S_F64\000" |
| 4710 | /* 6996 */ "I32_TRUNC_S_SAT_F64\000" |
| 4711 | /* 7016 */ "I64_TRUNC_S_SAT_F64\000" |
| 4712 | /* 7036 */ "I32_TRUNC_U_SAT_F64\000" |
| 4713 | /* 7056 */ "I64_TRUNC_U_SAT_F64\000" |
| 4714 | /* 7076 */ "SELECT_F64\000" |
| 4715 | /* 7087 */ "GLOBAL_GET_F64\000" |
| 4716 | /* 7102 */ "LOCAL_GET_F64\000" |
| 4717 | /* 7116 */ "I64_REINTERPRET_F64\000" |
| 4718 | /* 7136 */ "GLOBAL_SET_F64\000" |
| 4719 | /* 7151 */ "LOCAL_SET_F64\000" |
| 4720 | /* 7165 */ "GT_F64\000" |
| 4721 | /* 7172 */ "LT_F64\000" |
| 4722 | /* 7179 */ "SQRT_F64\000" |
| 4723 | /* 7188 */ "NEAREST_F64\000" |
| 4724 | /* 7200 */ "CONST_F64\000" |
| 4725 | /* 7210 */ "I32_TRUNC_U_F64\000" |
| 4726 | /* 7226 */ "I64_TRUNC_U_F64\000" |
| 4727 | /* 7242 */ "DIV_F64\000" |
| 4728 | /* 7250 */ "MAX_F64\000" |
| 4729 | /* 7258 */ "COPY_F64\000" |
| 4730 | /* 7267 */ "SUB_I64\000" |
| 4731 | /* 7275 */ "ADD_I64\000" |
| 4732 | /* 7283 */ "AND_I64\000" |
| 4733 | /* 7291 */ "LOCAL_TEE_I64\000" |
| 4734 | /* 7305 */ "BR_TABLE_I64\000" |
| 4735 | /* 7318 */ "NE_I64\000" |
| 4736 | /* 7325 */ "SHL_I64\000" |
| 4737 | /* 7333 */ "ROTL_I64\000" |
| 4738 | /* 7342 */ "MUL_I64\000" |
| 4739 | /* 7350 */ "I32_WRAP_I64\000" |
| 4740 | /* 7363 */ "DROP_I64\000" |
| 4741 | /* 7372 */ "EQ_I64\000" |
| 4742 | /* 7379 */ "XOR_I64\000" |
| 4743 | /* 7387 */ "ROTR_I64\000" |
| 4744 | /* 7396 */ "I64_EXTEND32_S_I64\000" |
| 4745 | /* 7415 */ "I64_EXTEND16_S_I64\000" |
| 4746 | /* 7434 */ "I64_EXTEND8_S_I64\000" |
| 4747 | /* 7452 */ "GE_S_I64\000" |
| 4748 | /* 7461 */ "LE_S_I64\000" |
| 4749 | /* 7470 */ "REM_S_I64\000" |
| 4750 | /* 7480 */ "SHR_S_I64\000" |
| 4751 | /* 7490 */ "GT_S_I64\000" |
| 4752 | /* 7499 */ "LT_S_I64\000" |
| 4753 | /* 7508 */ "F32_CONVERT_S_I64\000" |
| 4754 | /* 7526 */ "F64_CONVERT_S_I64\000" |
| 4755 | /* 7544 */ "DIV_S_I64\000" |
| 4756 | /* 7554 */ "SELECT_I64\000" |
| 4757 | /* 7565 */ "GLOBAL_GET_I64\000" |
| 4758 | /* 7580 */ "LOCAL_GET_I64\000" |
| 4759 | /* 7594 */ "F64_REINTERPRET_I64\000" |
| 4760 | /* 7614 */ "GLOBAL_SET_I64\000" |
| 4761 | /* 7629 */ "LOCAL_SET_I64\000" |
| 4762 | /* 7643 */ "POPCNT_I64\000" |
| 4763 | /* 7654 */ "CONST_I64\000" |
| 4764 | /* 7664 */ "GE_U_I64\000" |
| 4765 | /* 7673 */ "LE_U_I64\000" |
| 4766 | /* 7682 */ "REM_U_I64\000" |
| 4767 | /* 7692 */ "SHR_U_I64\000" |
| 4768 | /* 7702 */ "GT_U_I64\000" |
| 4769 | /* 7711 */ "LT_U_I64\000" |
| 4770 | /* 7720 */ "F32_CONVERT_U_I64\000" |
| 4771 | /* 7738 */ "F64_CONVERT_U_I64\000" |
| 4772 | /* 7756 */ "DIV_U_I64\000" |
| 4773 | /* 7766 */ "COPY_I64\000" |
| 4774 | /* 7775 */ "CLZ_I64\000" |
| 4775 | /* 7783 */ "EQZ_I64\000" |
| 4776 | /* 7791 */ "CTZ_I64\000" |
| 4777 | /* 7799 */ "ARGUMENT_v2f64\000" |
| 4778 | /* 7814 */ "ARGUMENT_f64\000" |
| 4779 | /* 7827 */ "ARGUMENT_v2i64\000" |
| 4780 | /* 7842 */ "ARGUMENT_i64\000" |
| 4781 | /* 7855 */ "CONST_V128_F32x4\000" |
| 4782 | /* 7872 */ "SUB_F32x4\000" |
| 4783 | /* 7882 */ "TRUNC_F32x4\000" |
| 4784 | /* 7894 */ "NMADD_F32x4\000" |
| 4785 | /* 7906 */ "GE_F32x4\000" |
| 4786 | /* 7915 */ "LE_F32x4\000" |
| 4787 | /* 7924 */ "REPLACE_LANE_F32x4\000" |
| 4788 | /* 7943 */ "EXTRACT_LANE_F32x4\000" |
| 4789 | /* 7962 */ "NEG_F32x4\000" |
| 4790 | /* 7972 */ "CEIL_F32x4\000" |
| 4791 | /* 7983 */ "MUL_F32x4\000" |
| 4792 | /* 7993 */ "SIMD_RELAXED_FMIN_F32x4\000" |
| 4793 | /* 8017 */ "PMIN_F32x4\000" |
| 4794 | /* 8028 */ "EQ_F32x4\000" |
| 4795 | /* 8037 */ "FLOOR_F32x4\000" |
| 4796 | /* 8049 */ "ABS_F32x4\000" |
| 4797 | /* 8059 */ "SPLAT_F32x4\000" |
| 4798 | /* 8071 */ "GT_F32x4\000" |
| 4799 | /* 8080 */ "LT_F32x4\000" |
| 4800 | /* 8089 */ "SQRT_F32x4\000" |
| 4801 | /* 8100 */ "NEAREST_F32x4\000" |
| 4802 | /* 8114 */ "DIV_F32x4\000" |
| 4803 | /* 8124 */ "SIMD_RELAXED_FMAX_F32x4\000" |
| 4804 | /* 8148 */ "PMAX_F32x4\000" |
| 4805 | /* 8159 */ "demote_zero_F32x4\000" |
| 4806 | /* 8177 */ "sint_to_fp_F32x4\000" |
| 4807 | /* 8194 */ "uint_to_fp_F32x4\000" |
| 4808 | /* 8211 */ "promote_low_F32x4\000" |
| 4809 | /* 8229 */ "CONST_V128_I32x4\000" |
| 4810 | /* 8246 */ "SUB_I32x4\000" |
| 4811 | /* 8256 */ "ADD_I32x4\000" |
| 4812 | /* 8266 */ "REPLACE_LANE_I32x4\000" |
| 4813 | /* 8285 */ "EXTRACT_LANE_I32x4\000" |
| 4814 | /* 8304 */ "ALLTRUE_I32x4\000" |
| 4815 | /* 8318 */ "NEG_I32x4\000" |
| 4816 | /* 8328 */ "BITMASK_I32x4\000" |
| 4817 | /* 8342 */ "SHL_I32x4\000" |
| 4818 | /* 8352 */ "MUL_I32x4\000" |
| 4819 | /* 8362 */ "EQ_I32x4\000" |
| 4820 | /* 8371 */ "ABS_I32x4\000" |
| 4821 | /* 8381 */ "GE_S_I32x4\000" |
| 4822 | /* 8392 */ "LE_S_I32x4\000" |
| 4823 | /* 8403 */ "EXTMUL_HIGH_S_I32x4\000" |
| 4824 | /* 8423 */ "MIN_S_I32x4\000" |
| 4825 | /* 8435 */ "SHR_S_I32x4\000" |
| 4826 | /* 8447 */ "GT_S_I32x4\000" |
| 4827 | /* 8458 */ "LT_S_I32x4\000" |
| 4828 | /* 8469 */ "EXTMUL_LOW_S_I32x4\000" |
| 4829 | /* 8488 */ "MAX_S_I32x4\000" |
| 4830 | /* 8500 */ "SPLAT_I32x4\000" |
| 4831 | /* 8512 */ "LANESELECT_I32x4\000" |
| 4832 | /* 8529 */ "GE_U_I32x4\000" |
| 4833 | /* 8540 */ "LE_U_I32x4\000" |
| 4834 | /* 8551 */ "EXTMUL_HIGH_U_I32x4\000" |
| 4835 | /* 8571 */ "MIN_U_I32x4\000" |
| 4836 | /* 8583 */ "SHR_U_I32x4\000" |
| 4837 | /* 8595 */ "GT_U_I32x4\000" |
| 4838 | /* 8606 */ "LT_U_I32x4\000" |
| 4839 | /* 8617 */ "EXTMUL_LOW_U_I32x4\000" |
| 4840 | /* 8636 */ "MAX_U_I32x4\000" |
| 4841 | /* 8648 */ "int_wasm_relaxed_trunc_signed_I32x4\000" |
| 4842 | /* 8684 */ "int_wasm_relaxed_trunc_unsigned_I32x4\000" |
| 4843 | /* 8722 */ "int_wasm_relaxed_trunc_signed_zero_I32x4\000" |
| 4844 | /* 8763 */ "int_wasm_relaxed_trunc_unsigned_zero_I32x4\000" |
| 4845 | /* 8806 */ "extadd_pairwise_s_I32x4\000" |
| 4846 | /* 8830 */ "extend_high_s_I32x4\000" |
| 4847 | /* 8850 */ "trunc_sat_zero_s_I32x4\000" |
| 4848 | /* 8873 */ "extend_low_s_I32x4\000" |
| 4849 | /* 8892 */ "fp_to_sint_I32x4\000" |
| 4850 | /* 8909 */ "fp_to_uint_I32x4\000" |
| 4851 | /* 8926 */ "extadd_pairwise_u_I32x4\000" |
| 4852 | /* 8950 */ "extend_high_u_I32x4\000" |
| 4853 | /* 8970 */ "trunc_sat_zero_u_I32x4\000" |
| 4854 | /* 8993 */ "extend_low_u_I32x4\000" |
| 4855 | /* 9012 */ "ARGUMENT_v8f16\000" |
| 4856 | /* 9027 */ "ARGUMENT_v8i16\000" |
| 4857 | /* 9042 */ "CONST_V128_I8x16\000" |
| 4858 | /* 9059 */ "SUB_I8x16\000" |
| 4859 | /* 9069 */ "ADD_I8x16\000" |
| 4860 | /* 9079 */ "REPLACE_LANE_I8x16\000" |
| 4861 | /* 9098 */ "ALLTRUE_I8x16\000" |
| 4862 | /* 9112 */ "NEG_I8x16\000" |
| 4863 | /* 9122 */ "BITMASK_I8x16\000" |
| 4864 | /* 9136 */ "SHL_I8x16\000" |
| 4865 | /* 9146 */ "EQ_I8x16\000" |
| 4866 | /* 9155 */ "ABS_I8x16\000" |
| 4867 | /* 9165 */ "GE_S_I8x16\000" |
| 4868 | /* 9176 */ "LE_S_I8x16\000" |
| 4869 | /* 9187 */ "MIN_S_I8x16\000" |
| 4870 | /* 9199 */ "SHR_S_I8x16\000" |
| 4871 | /* 9211 */ "SUB_SAT_S_I8x16\000" |
| 4872 | /* 9227 */ "ADD_SAT_S_I8x16\000" |
| 4873 | /* 9243 */ "GT_S_I8x16\000" |
| 4874 | /* 9254 */ "LT_S_I8x16\000" |
| 4875 | /* 9265 */ "NARROW_S_I8x16\000" |
| 4876 | /* 9280 */ "MAX_S_I8x16\000" |
| 4877 | /* 9292 */ "SPLAT_I8x16\000" |
| 4878 | /* 9304 */ "LANESELECT_I8x16\000" |
| 4879 | /* 9321 */ "POPCNT_I8x16\000" |
| 4880 | /* 9334 */ "GE_U_I8x16\000" |
| 4881 | /* 9345 */ "LE_U_I8x16\000" |
| 4882 | /* 9356 */ "MIN_U_I8x16\000" |
| 4883 | /* 9368 */ "AVGR_U_I8x16\000" |
| 4884 | /* 9381 */ "SHR_U_I8x16\000" |
| 4885 | /* 9393 */ "SUB_SAT_U_I8x16\000" |
| 4886 | /* 9409 */ "ADD_SAT_U_I8x16\000" |
| 4887 | /* 9425 */ "GT_U_I8x16\000" |
| 4888 | /* 9436 */ "LT_U_I8x16\000" |
| 4889 | /* 9447 */ "NARROW_U_I8x16\000" |
| 4890 | /* 9462 */ "MAX_U_I8x16\000" |
| 4891 | /* 9474 */ "I64_SUB128\000" |
| 4892 | /* 9485 */ "I64_ADD128\000" |
| 4893 | /* 9496 */ "LOCAL_TEE_V128\000" |
| 4894 | /* 9511 */ "DROP_V128\000" |
| 4895 | /* 9521 */ "SELECT_V128\000" |
| 4896 | /* 9533 */ "GLOBAL_GET_V128\000" |
| 4897 | /* 9549 */ "LOCAL_GET_V128\000" |
| 4898 | /* 9564 */ "GLOBAL_SET_V128\000" |
| 4899 | /* 9580 */ "LOCAL_SET_V128\000" |
| 4900 | /* 9595 */ "COPY_V128\000" |
| 4901 | /* 9605 */ "ARGUMENT_v16i8\000" |
| 4902 | /* 9620 */ "SUB_F16x8\000" |
| 4903 | /* 9630 */ "TRUNC_F16x8\000" |
| 4904 | /* 9642 */ "NMADD_F16x8\000" |
| 4905 | /* 9654 */ "GE_F16x8\000" |
| 4906 | /* 9663 */ "LE_F16x8\000" |
| 4907 | /* 9672 */ "REPLACE_LANE_F16x8\000" |
| 4908 | /* 9691 */ "EXTRACT_LANE_F16x8\000" |
| 4909 | /* 9710 */ "NEG_F16x8\000" |
| 4910 | /* 9720 */ "CEIL_F16x8\000" |
| 4911 | /* 9731 */ "MUL_F16x8\000" |
| 4912 | /* 9741 */ "PMIN_F16x8\000" |
| 4913 | /* 9752 */ "EQ_F16x8\000" |
| 4914 | /* 9761 */ "FLOOR_F16x8\000" |
| 4915 | /* 9773 */ "ABS_F16x8\000" |
| 4916 | /* 9783 */ "SPLAT_F16x8\000" |
| 4917 | /* 9795 */ "GT_F16x8\000" |
| 4918 | /* 9804 */ "LT_F16x8\000" |
| 4919 | /* 9813 */ "SQRT_F16x8\000" |
| 4920 | /* 9824 */ "NEAREST_F16x8\000" |
| 4921 | /* 9838 */ "DIV_F16x8\000" |
| 4922 | /* 9848 */ "PMAX_F16x8\000" |
| 4923 | /* 9859 */ "demote_zero_F16x8\000" |
| 4924 | /* 9877 */ "sint_to_fp_F16x8\000" |
| 4925 | /* 9894 */ "uint_to_fp_F16x8\000" |
| 4926 | /* 9911 */ "CONST_V128_I16x8\000" |
| 4927 | /* 9928 */ "SUB_I16x8\000" |
| 4928 | /* 9938 */ "ADD_I16x8\000" |
| 4929 | /* 9948 */ "REPLACE_LANE_I16x8\000" |
| 4930 | /* 9967 */ "ALLTRUE_I16x8\000" |
| 4931 | /* 9981 */ "NEG_I16x8\000" |
| 4932 | /* 9991 */ "BITMASK_I16x8\000" |
| 4933 | /* 10005 */ "SHL_I16x8\000" |
| 4934 | /* 10015 */ "MUL_I16x8\000" |
| 4935 | /* 10025 */ "EQ_I16x8\000" |
| 4936 | /* 10034 */ "ABS_I16x8\000" |
| 4937 | /* 10044 */ "GE_S_I16x8\000" |
| 4938 | /* 10055 */ "LE_S_I16x8\000" |
| 4939 | /* 10066 */ "EXTMUL_HIGH_S_I16x8\000" |
| 4940 | /* 10086 */ "MIN_S_I16x8\000" |
| 4941 | /* 10098 */ "SHR_S_I16x8\000" |
| 4942 | /* 10110 */ "RELAXED_Q15MULR_S_I16x8\000" |
| 4943 | /* 10134 */ "SUB_SAT_S_I16x8\000" |
| 4944 | /* 10150 */ "ADD_SAT_S_I16x8\000" |
| 4945 | /* 10166 */ "Q15MULR_SAT_S_I16x8\000" |
| 4946 | /* 10186 */ "GT_S_I16x8\000" |
| 4947 | /* 10197 */ "LT_S_I16x8\000" |
| 4948 | /* 10208 */ "EXTMUL_LOW_S_I16x8\000" |
| 4949 | /* 10227 */ "NARROW_S_I16x8\000" |
| 4950 | /* 10242 */ "MAX_S_I16x8\000" |
| 4951 | /* 10254 */ "SPLAT_I16x8\000" |
| 4952 | /* 10266 */ "LANESELECT_I16x8\000" |
| 4953 | /* 10283 */ "GE_U_I16x8\000" |
| 4954 | /* 10294 */ "LE_U_I16x8\000" |
| 4955 | /* 10305 */ "EXTMUL_HIGH_U_I16x8\000" |
| 4956 | /* 10325 */ "MIN_U_I16x8\000" |
| 4957 | /* 10337 */ "AVGR_U_I16x8\000" |
| 4958 | /* 10350 */ "SHR_U_I16x8\000" |
| 4959 | /* 10362 */ "SUB_SAT_U_I16x8\000" |
| 4960 | /* 10378 */ "ADD_SAT_U_I16x8\000" |
| 4961 | /* 10394 */ "GT_U_I16x8\000" |
| 4962 | /* 10405 */ "LT_U_I16x8\000" |
| 4963 | /* 10416 */ "EXTMUL_LOW_U_I16x8\000" |
| 4964 | /* 10435 */ "NARROW_U_I16x8\000" |
| 4965 | /* 10450 */ "MAX_U_I16x8\000" |
| 4966 | /* 10462 */ "extadd_pairwise_s_I16x8\000" |
| 4967 | /* 10486 */ "extend_high_s_I16x8\000" |
| 4968 | /* 10506 */ "extend_low_s_I16x8\000" |
| 4969 | /* 10525 */ "fp_to_sint_I16x8\000" |
| 4970 | /* 10542 */ "fp_to_uint_I16x8\000" |
| 4971 | /* 10559 */ "extadd_pairwise_u_I16x8\000" |
| 4972 | /* 10583 */ "extend_high_u_I16x8\000" |
| 4973 | /* 10603 */ "extend_low_u_I16x8\000" |
| 4974 | /* 10622 */ "G_FMA\000" |
| 4975 | /* 10628 */ "G_STRICT_FMA\000" |
| 4976 | /* 10641 */ "G_FSUB\000" |
| 4977 | /* 10648 */ "G_STRICT_FSUB\000" |
| 4978 | /* 10662 */ "G_ATOMICRMW_FSUB\000" |
| 4979 | /* 10679 */ "G_SUB\000" |
| 4980 | /* 10685 */ "G_ATOMICRMW_SUB\000" |
| 4981 | /* 10701 */ "G_INTRINSIC\000" |
| 4982 | /* 10713 */ "REF_FUNC\000" |
| 4983 | /* 10722 */ "G_FPTRUNC\000" |
| 4984 | /* 10732 */ "G_INTRINSIC_TRUNC\000" |
| 4985 | /* 10750 */ "G_TRUNC\000" |
| 4986 | /* 10758 */ "G_BUILD_VECTOR_TRUNC\000" |
| 4987 | /* 10779 */ "G_DYN_STACKALLOC\000" |
| 4988 | /* 10796 */ "G_FMAD\000" |
| 4989 | /* 10803 */ "G_FPEXTLOAD\000" |
| 4990 | /* 10815 */ "G_INDEXED_SEXTLOAD\000" |
| 4991 | /* 10834 */ "G_SEXTLOAD\000" |
| 4992 | /* 10845 */ "G_INDEXED_ZEXTLOAD\000" |
| 4993 | /* 10864 */ "G_ZEXTLOAD\000" |
| 4994 | /* 10875 */ "G_INDEXED_LOAD\000" |
| 4995 | /* 10890 */ "G_LOAD\000" |
| 4996 | /* 10897 */ "G_VECREDUCE_FADD\000" |
| 4997 | /* 10914 */ "G_FADD\000" |
| 4998 | /* 10921 */ "G_VECREDUCE_SEQ_FADD\000" |
| 4999 | /* 10942 */ "G_STRICT_FADD\000" |
| 5000 | /* 10956 */ "G_ATOMICRMW_FADD\000" |
| 5001 | /* 10973 */ "G_VECREDUCE_ADD\000" |
| 5002 | /* 10989 */ "G_ADD\000" |
| 5003 | /* 10995 */ "G_PTR_ADD\000" |
| 5004 | /* 11005 */ "RELAXED_DOT_ADD\000" |
| 5005 | /* 11021 */ "G_ATOMICRMW_ADD\000" |
| 5006 | /* 11037 */ "G_ATOMICRMW_NAND\000" |
| 5007 | /* 11054 */ "G_VECREDUCE_AND\000" |
| 5008 | /* 11070 */ "G_AND\000" |
| 5009 | /* 11076 */ "G_ATOMICRMW_AND\000" |
| 5010 | /* 11092 */ "LIFETIME_END\000" |
| 5011 | /* 11105 */ "G_BRCOND\000" |
| 5012 | /* 11114 */ "G_ATOMICRMW_USUB_COND\000" |
| 5013 | /* 11136 */ "G_LLROUND\000" |
| 5014 | /* 11146 */ "G_LROUND\000" |
| 5015 | /* 11155 */ "G_INTRINSIC_ROUND\000" |
| 5016 | /* 11173 */ "G_INTRINSIC_FPTRUNC_ROUND\000" |
| 5017 | /* 11199 */ "LOAD_STACK_GUARD\000" |
| 5018 | /* 11216 */ "PSEUDO_PROBE\000" |
| 5019 | /* 11229 */ "G_SSUBE\000" |
| 5020 | /* 11237 */ "G_USUBE\000" |
| 5021 | /* 11245 */ "ATOMIC_FENCE\000" |
| 5022 | /* 11258 */ "G_FENCE\000" |
| 5023 | /* 11266 */ "ARITH_FENCE\000" |
| 5024 | /* 11278 */ "COMPILER_FENCE\000" |
| 5025 | /* 11293 */ "REG_SEQUENCE\000" |
| 5026 | /* 11306 */ "G_SADDE\000" |
| 5027 | /* 11314 */ "G_UADDE\000" |
| 5028 | /* 11322 */ "G_GET_FPMODE\000" |
| 5029 | /* 11335 */ "G_RESET_FPMODE\000" |
| 5030 | /* 11350 */ "G_SET_FPMODE\000" |
| 5031 | /* 11363 */ "G_FMINNUM_IEEE\000" |
| 5032 | /* 11378 */ "G_FMAXNUM_IEEE\000" |
| 5033 | /* 11393 */ "G_VSCALE\000" |
| 5034 | /* 11402 */ "DEBUG_UNREACHABLE\000" |
| 5035 | /* 11420 */ "G_JUMP_TABLE\000" |
| 5036 | /* 11433 */ "END_TRY_TABLE\000" |
| 5037 | /* 11447 */ "BUNDLE\000" |
| 5038 | /* 11454 */ "SHUFFLE\000" |
| 5039 | /* 11462 */ "RELAXED_SWIZZLE\000" |
| 5040 | /* 11478 */ "G_MEMSET_INLINE\000" |
| 5041 | /* 11494 */ "G_MEMCPY_INLINE\000" |
| 5042 | /* 11510 */ "RELOC_NONE\000" |
| 5043 | /* 11521 */ "LOCAL_ESCAPE\000" |
| 5044 | /* 11534 */ "G_FPTRUNCSTORE\000" |
| 5045 | /* 11549 */ "G_STACKRESTORE\000" |
| 5046 | /* 11564 */ "G_INDEXED_STORE\000" |
| 5047 | /* 11580 */ "G_STORE\000" |
| 5048 | /* 11588 */ "ELSE\000" |
| 5049 | /* 11593 */ "G_BITREVERSE\000" |
| 5050 | /* 11606 */ "FAKE_USE\000" |
| 5051 | /* 11615 */ "DELEGATE\000" |
| 5052 | /* 11624 */ "DBG_VALUE\000" |
| 5053 | /* 11634 */ "G_GLOBAL_VALUE\000" |
| 5054 | /* 11649 */ "G_PTRAUTH_GLOBAL_VALUE\000" |
| 5055 | /* 11672 */ "CONVERGENCECTRL_GLUE\000" |
| 5056 | /* 11693 */ "ANYTRUE\000" |
| 5057 | /* 11701 */ "G_STACKSAVE\000" |
| 5058 | /* 11713 */ "G_MEMMOVE\000" |
| 5059 | /* 11723 */ "G_FREEZE\000" |
| 5060 | /* 11732 */ "G_FCANONICALIZE\000" |
| 5061 | /* 11748 */ "TABLE_SIZE\000" |
| 5062 | /* 11759 */ "G_FMODF\000" |
| 5063 | /* 11767 */ "INIT_UNDEF\000" |
| 5064 | /* 11778 */ "G_IMPLICIT_DEF\000" |
| 5065 | /* 11793 */ "LOCAL_TEE_FUNCREF\000" |
| 5066 | /* 11811 */ "TABLE_FILL_FUNCREF\000" |
| 5067 | /* 11830 */ "REF_NULL_FUNCREF\000" |
| 5068 | /* 11847 */ "REF_IS_NULL_FUNCREF\000" |
| 5069 | /* 11867 */ "DROP_FUNCREF\000" |
| 5070 | /* 11880 */ "SELECT_FUNCREF\000" |
| 5071 | /* 11895 */ "TABLE_GET_FUNCREF\000" |
| 5072 | /* 11913 */ "GLOBAL_GET_FUNCREF\000" |
| 5073 | /* 11932 */ "LOCAL_GET_FUNCREF\000" |
| 5074 | /* 11950 */ "TABLE_SET_FUNCREF\000" |
| 5075 | /* 11968 */ "GLOBAL_SET_FUNCREF\000" |
| 5076 | /* 11987 */ "LOCAL_SET_FUNCREF\000" |
| 5077 | /* 12005 */ "REF_CAST_FUNCREF\000" |
| 5078 | /* 12022 */ "REF_TEST_FUNCREF\000" |
| 5079 | /* 12039 */ "TABLE_GROW_FUNCREF\000" |
| 5080 | /* 12058 */ "COPY_FUNCREF\000" |
| 5081 | /* 12071 */ "LOCAL_TEE_EXTERNREF\000" |
| 5082 | /* 12091 */ "TABLE_FILL_EXTERNREF\000" |
| 5083 | /* 12112 */ "REF_NULL_EXTERNREF\000" |
| 5084 | /* 12131 */ "REF_IS_NULL_EXTERNREF\000" |
| 5085 | /* 12153 */ "DROP_EXTERNREF\000" |
| 5086 | /* 12168 */ "SELECT_EXTERNREF\000" |
| 5087 | /* 12185 */ "TABLE_GET_EXTERNREF\000" |
| 5088 | /* 12205 */ "GLOBAL_GET_EXTERNREF\000" |
| 5089 | /* 12226 */ "LOCAL_GET_EXTERNREF\000" |
| 5090 | /* 12246 */ "TABLE_SET_EXTERNREF\000" |
| 5091 | /* 12266 */ "GLOBAL_SET_EXTERNREF\000" |
| 5092 | /* 12287 */ "LOCAL_SET_EXTERNREF\000" |
| 5093 | /* 12307 */ "TABLE_GROW_EXTERNREF\000" |
| 5094 | /* 12328 */ "COPY_EXTERNREF\000" |
| 5095 | /* 12343 */ "LOCAL_TEE_EXNREF\000" |
| 5096 | /* 12360 */ "TABLE_FILL_EXNREF\000" |
| 5097 | /* 12378 */ "REF_NULL_EXNREF\000" |
| 5098 | /* 12394 */ "REF_IS_NULL_EXNREF\000" |
| 5099 | /* 12413 */ "DROP_EXNREF\000" |
| 5100 | /* 12425 */ "SELECT_EXNREF\000" |
| 5101 | /* 12439 */ "TABLE_GET_EXNREF\000" |
| 5102 | /* 12456 */ "GLOBAL_GET_EXNREF\000" |
| 5103 | /* 12474 */ "LOCAL_GET_EXNREF\000" |
| 5104 | /* 12491 */ "TABLE_SET_EXNREF\000" |
| 5105 | /* 12508 */ "GLOBAL_SET_EXNREF\000" |
| 5106 | /* 12526 */ "LOCAL_SET_EXNREF\000" |
| 5107 | /* 12543 */ "TABLE_GROW_EXNREF\000" |
| 5108 | /* 12561 */ "COPY_EXNREF\000" |
| 5109 | /* 12573 */ "CATCH_REF\000" |
| 5110 | /* 12583 */ "RET_CALL_REF\000" |
| 5111 | /* 12596 */ "CATCH_ALL_REF\000" |
| 5112 | /* 12610 */ "DBG_INSTR_REF\000" |
| 5113 | /* 12624 */ "THROW_REF\000" |
| 5114 | /* 12634 */ "END_IF\000" |
| 5115 | /* 12641 */ "BR_IF\000" |
| 5116 | /* 12647 */ "G_FNEG\000" |
| 5117 | /* 12654 */ "EXTRACT_SUBREG\000" |
| 5118 | /* 12669 */ "INSERT_SUBREG\000" |
| 5119 | /* 12683 */ "G_SEXT_INREG\000" |
| 5120 | /* 12696 */ "SUBREG_TO_REG\000" |
| 5121 | /* 12710 */ "G_ATOMIC_CMPXCHG\000" |
| 5122 | /* 12727 */ "G_ATOMICRMW_XCHG\000" |
| 5123 | /* 12744 */ "G_GET_ROUNDING\000" |
| 5124 | /* 12759 */ "G_SET_ROUNDING\000" |
| 5125 | /* 12774 */ "G_FLOG\000" |
| 5126 | /* 12781 */ "G_VAARG\000" |
| 5127 | /* 12789 */ "PREALLOCATED_ARG\000" |
| 5128 | /* 12806 */ "CATCH\000" |
| 5129 | /* 12812 */ "G_PREFETCH\000" |
| 5130 | /* 12823 */ "G_CLMULH\000" |
| 5131 | /* 12832 */ "G_SMULH\000" |
| 5132 | /* 12840 */ "G_UMULH\000" |
| 5133 | /* 12848 */ "G_FTANH\000" |
| 5134 | /* 12856 */ "G_FSINH\000" |
| 5135 | /* 12864 */ "G_FCOSH\000" |
| 5136 | /* 12872 */ "DBG_PHI\000" |
| 5137 | /* 12880 */ "G_FPTOSI\000" |
| 5138 | /* 12889 */ "G_FPTOUI\000" |
| 5139 | /* 12898 */ "G_FPOWI\000" |
| 5140 | /* 12906 */ "END_BLOCK\000" |
| 5141 | /* 12916 */ "COPY_LANEMASK\000" |
| 5142 | /* 12930 */ "G_PTRMASK\000" |
| 5143 | /* 12940 */ "GC_LABEL\000" |
| 5144 | /* 12949 */ "DBG_LABEL\000" |
| 5145 | /* 12959 */ "EH_LABEL\000" |
| 5146 | /* 12968 */ "ANNOTATION_LABEL\000" |
| 5147 | /* 12985 */ "ICALL_BRANCH_FUNNEL\000" |
| 5148 | /* 13005 */ "G_FSHL\000" |
| 5149 | /* 13012 */ "G_SHL\000" |
| 5150 | /* 13018 */ "G_FCEIL\000" |
| 5151 | /* 13026 */ "G_SAVGCEIL\000" |
| 5152 | /* 13037 */ "G_UAVGCEIL\000" |
| 5153 | /* 13048 */ "PATCHABLE_TAIL_CALL\000" |
| 5154 | /* 13068 */ "RET_CALL\000" |
| 5155 | /* 13077 */ "PATCHABLE_TYPED_EVENT_CALL\000" |
| 5156 | /* 13104 */ "PATCHABLE_EVENT_CALL\000" |
| 5157 | /* 13125 */ "FENTRY_CALL\000" |
| 5158 | /* 13137 */ "CATCH_ALL\000" |
| 5159 | /* 13147 */ "KILL\000" |
| 5160 | /* 13152 */ "G_CONSTANT_POOL\000" |
| 5161 | /* 13168 */ "G_ROTL\000" |
| 5162 | /* 13175 */ "G_VECREDUCE_FMUL\000" |
| 5163 | /* 13192 */ "G_FMUL\000" |
| 5164 | /* 13199 */ "G_VECREDUCE_SEQ_FMUL\000" |
| 5165 | /* 13220 */ "G_STRICT_FMUL\000" |
| 5166 | /* 13234 */ "G_CLMUL\000" |
| 5167 | /* 13242 */ "G_VECREDUCE_MUL\000" |
| 5168 | /* 13258 */ "G_MUL\000" |
| 5169 | /* 13264 */ "G_FREM\000" |
| 5170 | /* 13271 */ "G_STRICT_FREM\000" |
| 5171 | /* 13285 */ "G_SREM\000" |
| 5172 | /* 13292 */ "G_UREM\000" |
| 5173 | /* 13299 */ "G_SDIVREM\000" |
| 5174 | /* 13309 */ "G_UDIVREM\000" |
| 5175 | /* 13319 */ "INLINEASM\000" |
| 5176 | /* 13329 */ "G_VECREDUCE_FMINIMUM\000" |
| 5177 | /* 13350 */ "G_FMINIMUM\000" |
| 5178 | /* 13361 */ "G_ATOMICRMW_FMINIMUM\000" |
| 5179 | /* 13382 */ "G_VECREDUCE_FMAXIMUM\000" |
| 5180 | /* 13403 */ "G_FMAXIMUM\000" |
| 5181 | /* 13414 */ "G_ATOMICRMW_FMAXIMUM\000" |
| 5182 | /* 13435 */ "G_VECREDUCE_FMINIMUMNUM\000" |
| 5183 | /* 13459 */ "G_FMINIMUMNUM\000" |
| 5184 | /* 13473 */ "G_ATOMICRMW_FMINIMUMNUM\000" |
| 5185 | /* 13497 */ "G_VECREDUCE_FMAXIMUMNUM\000" |
| 5186 | /* 13521 */ "G_FMAXIMUMNUM\000" |
| 5187 | /* 13535 */ "G_ATOMICRMW_FMAXIMUMNUM\000" |
| 5188 | /* 13559 */ "G_FMINNUM\000" |
| 5189 | /* 13569 */ "G_FMAXNUM\000" |
| 5190 | /* 13579 */ "G_FATAN\000" |
| 5191 | /* 13587 */ "G_FTAN\000" |
| 5192 | /* 13594 */ "G_INTRINSIC_ROUNDEVEN\000" |
| 5193 | /* 13616 */ "G_ASSERT_ALIGN\000" |
| 5194 | /* 13631 */ "G_FCOPYSIGN\000" |
| 5195 | /* 13643 */ "G_VECREDUCE_FMIN\000" |
| 5196 | /* 13660 */ "G_ATOMICRMW_FMIN\000" |
| 5197 | /* 13677 */ "G_VECREDUCE_SMIN\000" |
| 5198 | /* 13694 */ "G_SMIN\000" |
| 5199 | /* 13701 */ "G_VECREDUCE_UMIN\000" |
| 5200 | /* 13718 */ "G_UMIN\000" |
| 5201 | /* 13725 */ "G_ATOMICRMW_UMIN\000" |
| 5202 | /* 13742 */ "G_ATOMICRMW_MIN\000" |
| 5203 | /* 13758 */ "G_FASIN\000" |
| 5204 | /* 13766 */ "G_FSIN\000" |
| 5205 | /* 13773 */ "END_FUNCTION\000" |
| 5206 | /* 13786 */ "CFI_INSTRUCTION\000" |
| 5207 | /* 13802 */ "G_CTLZ_ZERO_POISON\000" |
| 5208 | /* 13821 */ "G_CTTZ_ZERO_POISON\000" |
| 5209 | /* 13840 */ "FALLTHROUGH_RETURN\000" |
| 5210 | /* 13859 */ "ADJCALLSTACKDOWN\000" |
| 5211 | /* 13876 */ "G_SSUBO\000" |
| 5212 | /* 13884 */ "G_USUBO\000" |
| 5213 | /* 13892 */ "G_SADDO\000" |
| 5214 | /* 13900 */ "G_UADDO\000" |
| 5215 | /* 13908 */ "JUMP_TABLE_DEBUG_INFO\000" |
| 5216 | /* 13930 */ "G_SMULO\000" |
| 5217 | /* 13938 */ "G_UMULO\000" |
| 5218 | /* 13946 */ "G_BZERO\000" |
| 5219 | /* 13954 */ "STACKMAP\000" |
| 5220 | /* 13963 */ "G_DEBUGTRAP\000" |
| 5221 | /* 13975 */ "G_UBSANTRAP\000" |
| 5222 | /* 13987 */ "G_TRAP\000" |
| 5223 | /* 13994 */ "G_ATOMICRMW_UDEC_WRAP\000" |
| 5224 | /* 14016 */ "G_ATOMICRMW_UINC_WRAP\000" |
| 5225 | /* 14038 */ "G_BSWAP\000" |
| 5226 | /* 14046 */ "G_SITOFP\000" |
| 5227 | /* 14055 */ "G_UITOFP\000" |
| 5228 | /* 14064 */ "G_FCMP\000" |
| 5229 | /* 14071 */ "G_STRICT_FCMP\000" |
| 5230 | /* 14085 */ "G_ICMP\000" |
| 5231 | /* 14092 */ "G_SCMP\000" |
| 5232 | /* 14099 */ "G_UCMP\000" |
| 5233 | /* 14106 */ "NOP\000" |
| 5234 | /* 14110 */ "END_LOOP\000" |
| 5235 | /* 14119 */ "CONVERGENCECTRL_LOOP\000" |
| 5236 | /* 14140 */ "G_CTPOP\000" |
| 5237 | /* 14148 */ "DATA_DROP\000" |
| 5238 | /* 14158 */ "PATCHABLE_OP\000" |
| 5239 | /* 14171 */ "FAULTING_OP\000" |
| 5240 | /* 14183 */ "ADJCALLSTACKUP\000" |
| 5241 | /* 14198 */ "PREALLOCATED_SETUP\000" |
| 5242 | /* 14217 */ "G_FLDEXP\000" |
| 5243 | /* 14226 */ "G_STRICT_FLDEXP\000" |
| 5244 | /* 14242 */ "G_FEXP\000" |
| 5245 | /* 14249 */ "G_FFREXP\000" |
| 5246 | /* 14258 */ "G_BR\000" |
| 5247 | /* 14263 */ "INLINEASM_BR\000" |
| 5248 | /* 14276 */ "G_BLOCK_ADDR\000" |
| 5249 | /* 14289 */ "MEMBARRIER\000" |
| 5250 | /* 14300 */ "G_CONSTANT_FOLD_BARRIER\000" |
| 5251 | /* 14324 */ "PATCHABLE_FUNCTION_ENTER\000" |
| 5252 | /* 14349 */ "G_READCYCLECOUNTER\000" |
| 5253 | /* 14368 */ "G_READSTEADYCOUNTER\000" |
| 5254 | /* 14388 */ "G_READ_REGISTER\000" |
| 5255 | /* 14404 */ "G_WRITE_REGISTER\000" |
| 5256 | /* 14421 */ "G_ASHR\000" |
| 5257 | /* 14428 */ "G_FSHR\000" |
| 5258 | /* 14435 */ "G_LSHR\000" |
| 5259 | /* 14442 */ "CONVERGENCECTRL_ANCHOR\000" |
| 5260 | /* 14465 */ "G_FFLOOR\000" |
| 5261 | /* 14474 */ "G_SAVGFLOOR\000" |
| 5262 | /* 14486 */ "G_UAVGFLOOR\000" |
| 5263 | /* 14498 */ "G_EXTRACT_SUBVECTOR\000" |
| 5264 | /* 14518 */ "G_INSERT_SUBVECTOR\000" |
| 5265 | /* 14537 */ "G_BUILD_VECTOR\000" |
| 5266 | /* 14552 */ "G_SHUFFLE_VECTOR\000" |
| 5267 | /* 14569 */ "G_STEP_VECTOR\000" |
| 5268 | /* 14583 */ "G_SPLAT_VECTOR\000" |
| 5269 | /* 14598 */ "G_VECREDUCE_XOR\000" |
| 5270 | /* 14614 */ "G_XOR\000" |
| 5271 | /* 14620 */ "G_ATOMICRMW_XOR\000" |
| 5272 | /* 14636 */ "G_VECREDUCE_OR\000" |
| 5273 | /* 14651 */ "G_OR\000" |
| 5274 | /* 14656 */ "G_ATOMICRMW_OR\000" |
| 5275 | /* 14671 */ "G_ROTR\000" |
| 5276 | /* 14678 */ "G_INTTOPTR\000" |
| 5277 | /* 14689 */ "G_FABS\000" |
| 5278 | /* 14696 */ "G_ABS\000" |
| 5279 | /* 14702 */ "G_ABDS\000" |
| 5280 | /* 14709 */ "G_UNMERGE_VALUES\000" |
| 5281 | /* 14726 */ "G_MERGE_VALUES\000" |
| 5282 | /* 14741 */ "G_CTLS\000" |
| 5283 | /* 14748 */ "CALL_PARAMS\000" |
| 5284 | /* 14760 */ "G_FACOS\000" |
| 5285 | /* 14768 */ "G_FCOS\000" |
| 5286 | /* 14775 */ "G_FSINCOS\000" |
| 5287 | /* 14785 */ "G_STRICT_FCMPS\000" |
| 5288 | /* 14800 */ "G_CONCAT_VECTORS\000" |
| 5289 | /* 14817 */ "COPY_TO_REGCLASS\000" |
| 5290 | /* 14834 */ "G_IS_FPCLASS\000" |
| 5291 | /* 14847 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000" |
| 5292 | /* 14877 */ "BR_UNLESS\000" |
| 5293 | /* 14887 */ "G_VECTOR_COMPRESS\000" |
| 5294 | /* 14905 */ "G_INTRINSIC_W_SIDE_EFFECTS\000" |
| 5295 | /* 14932 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000" |
| 5296 | /* 14970 */ "RET_CALL_RESULTS\000" |
| 5297 | /* 14987 */ "LOAD_F16_F32_A32_S\000" |
| 5298 | /* 15006 */ "STORE_F16_F32_A32_S\000" |
| 5299 | /* 15026 */ "LOAD_F32_A32_S\000" |
| 5300 | /* 15041 */ "STORE_F32_A32_S\000" |
| 5301 | /* 15057 */ "ATOMIC_STORE16_I32_A32_S\000" |
| 5302 | /* 15082 */ "ATOMIC_STORE8_I32_A32_S\000" |
| 5303 | /* 15106 */ "ATOMIC_RMW16_U_SUB_I32_A32_S\000" |
| 5304 | /* 15135 */ "ATOMIC_RMW8_U_SUB_I32_A32_S\000" |
| 5305 | /* 15163 */ "ATOMIC_RMW_SUB_I32_A32_S\000" |
| 5306 | /* 15188 */ "ATOMIC_LOAD_I32_A32_S\000" |
| 5307 | /* 15210 */ "ATOMIC_RMW16_U_ADD_I32_A32_S\000" |
| 5308 | /* 15239 */ "ATOMIC_RMW8_U_ADD_I32_A32_S\000" |
| 5309 | /* 15267 */ "ATOMIC_RMW_ADD_I32_A32_S\000" |
| 5310 | /* 15292 */ "ATOMIC_RMW16_U_AND_I32_A32_S\000" |
| 5311 | /* 15321 */ "ATOMIC_RMW8_U_AND_I32_A32_S\000" |
| 5312 | /* 15349 */ "ATOMIC_RMW_AND_I32_A32_S\000" |
| 5313 | /* 15374 */ "ATOMIC_STORE_I32_A32_S\000" |
| 5314 | /* 15397 */ "ATOMIC_RMW16_U_CMPXCHG_I32_A32_S\000" |
| 5315 | /* 15430 */ "ATOMIC_RMW8_U_CMPXCHG_I32_A32_S\000" |
| 5316 | /* 15462 */ "ATOMIC_RMW_CMPXCHG_I32_A32_S\000" |
| 5317 | /* 15491 */ "ATOMIC_RMW16_U_XCHG_I32_A32_S\000" |
| 5318 | /* 15521 */ "ATOMIC_RMW8_U_XCHG_I32_A32_S\000" |
| 5319 | /* 15550 */ "ATOMIC_RMW_XCHG_I32_A32_S\000" |
| 5320 | /* 15576 */ "ATOMIC_RMW16_U_XOR_I32_A32_S\000" |
| 5321 | /* 15605 */ "ATOMIC_RMW8_U_XOR_I32_A32_S\000" |
| 5322 | /* 15633 */ "ATOMIC_RMW_XOR_I32_A32_S\000" |
| 5323 | /* 15658 */ "ATOMIC_RMW16_U_OR_I32_A32_S\000" |
| 5324 | /* 15686 */ "ATOMIC_RMW8_U_OR_I32_A32_S\000" |
| 5325 | /* 15713 */ "ATOMIC_RMW_OR_I32_A32_S\000" |
| 5326 | /* 15737 */ "LOAD16_S_I32_A32_S\000" |
| 5327 | /* 15756 */ "LOAD8_S_I32_A32_S\000" |
| 5328 | /* 15774 */ "ATOMIC_LOAD16_U_I32_A32_S\000" |
| 5329 | /* 15800 */ "ATOMIC_LOAD8_U_I32_A32_S\000" |
| 5330 | /* 15825 */ "MEMORY_ATOMIC_WAIT32_A32_S\000" |
| 5331 | /* 15852 */ "LOAD_LANE_32_A32_S\000" |
| 5332 | /* 15871 */ "LOAD_ZERO_32_A32_S\000" |
| 5333 | /* 15890 */ "STORE_LANE_I64x2_A32_S\000" |
| 5334 | /* 15913 */ "LOAD_EXTEND_S_I64x2_A32_S\000" |
| 5335 | /* 15939 */ "LOAD_EXTEND_U_I64x2_A32_S\000" |
| 5336 | /* 15965 */ "LOAD_F64_A32_S\000" |
| 5337 | /* 15980 */ "STORE_F64_A32_S\000" |
| 5338 | /* 15996 */ "ATOMIC_STORE32_I64_A32_S\000" |
| 5339 | /* 16021 */ "ATOMIC_STORE16_I64_A32_S\000" |
| 5340 | /* 16046 */ "ATOMIC_STORE8_I64_A32_S\000" |
| 5341 | /* 16070 */ "ATOMIC_RMW32_U_SUB_I64_A32_S\000" |
| 5342 | /* 16099 */ "ATOMIC_RMW16_U_SUB_I64_A32_S\000" |
| 5343 | /* 16128 */ "ATOMIC_RMW8_U_SUB_I64_A32_S\000" |
| 5344 | /* 16156 */ "ATOMIC_RMW_SUB_I64_A32_S\000" |
| 5345 | /* 16181 */ "ATOMIC_LOAD_I64_A32_S\000" |
| 5346 | /* 16203 */ "ATOMIC_RMW32_U_ADD_I64_A32_S\000" |
| 5347 | /* 16232 */ "ATOMIC_RMW16_U_ADD_I64_A32_S\000" |
| 5348 | /* 16261 */ "ATOMIC_RMW8_U_ADD_I64_A32_S\000" |
| 5349 | /* 16289 */ "ATOMIC_RMW_ADD_I64_A32_S\000" |
| 5350 | /* 16314 */ "ATOMIC_RMW32_U_AND_I64_A32_S\000" |
| 5351 | /* 16343 */ "ATOMIC_RMW16_U_AND_I64_A32_S\000" |
| 5352 | /* 16372 */ "ATOMIC_RMW8_U_AND_I64_A32_S\000" |
| 5353 | /* 16400 */ "ATOMIC_RMW_AND_I64_A32_S\000" |
| 5354 | /* 16425 */ "ATOMIC_STORE_I64_A32_S\000" |
| 5355 | /* 16448 */ "ATOMIC_RMW32_U_CMPXCHG_I64_A32_S\000" |
| 5356 | /* 16481 */ "ATOMIC_RMW16_U_CMPXCHG_I64_A32_S\000" |
| 5357 | /* 16514 */ "ATOMIC_RMW8_U_CMPXCHG_I64_A32_S\000" |
| 5358 | /* 16546 */ "ATOMIC_RMW_CMPXCHG_I64_A32_S\000" |
| 5359 | /* 16575 */ "ATOMIC_RMW32_U_XCHG_I64_A32_S\000" |
| 5360 | /* 16605 */ "ATOMIC_RMW16_U_XCHG_I64_A32_S\000" |
| 5361 | /* 16635 */ "ATOMIC_RMW8_U_XCHG_I64_A32_S\000" |
| 5362 | /* 16664 */ "ATOMIC_RMW_XCHG_I64_A32_S\000" |
| 5363 | /* 16690 */ "ATOMIC_RMW32_U_XOR_I64_A32_S\000" |
| 5364 | /* 16719 */ "ATOMIC_RMW16_U_XOR_I64_A32_S\000" |
| 5365 | /* 16748 */ "ATOMIC_RMW8_U_XOR_I64_A32_S\000" |
| 5366 | /* 16776 */ "ATOMIC_RMW_XOR_I64_A32_S\000" |
| 5367 | /* 16801 */ "ATOMIC_RMW32_U_OR_I64_A32_S\000" |
| 5368 | /* 16829 */ "ATOMIC_RMW16_U_OR_I64_A32_S\000" |
| 5369 | /* 16857 */ "ATOMIC_RMW8_U_OR_I64_A32_S\000" |
| 5370 | /* 16884 */ "ATOMIC_RMW_OR_I64_A32_S\000" |
| 5371 | /* 16908 */ "LOAD32_S_I64_A32_S\000" |
| 5372 | /* 16927 */ "LOAD16_S_I64_A32_S\000" |
| 5373 | /* 16946 */ "LOAD8_S_I64_A32_S\000" |
| 5374 | /* 16964 */ "ATOMIC_LOAD32_U_I64_A32_S\000" |
| 5375 | /* 16990 */ "ATOMIC_LOAD16_U_I64_A32_S\000" |
| 5376 | /* 17016 */ "ATOMIC_LOAD8_U_I64_A32_S\000" |
| 5377 | /* 17041 */ "MEMORY_ATOMIC_WAIT64_A32_S\000" |
| 5378 | /* 17068 */ "LOAD_LANE_64_A32_S\000" |
| 5379 | /* 17087 */ "LOAD_ZERO_64_A32_S\000" |
| 5380 | /* 17106 */ "STORE_LANE_I32x4_A32_S\000" |
| 5381 | /* 17129 */ "LOAD_EXTEND_S_I32x4_A32_S\000" |
| 5382 | /* 17155 */ "LOAD_EXTEND_U_I32x4_A32_S\000" |
| 5383 | /* 17181 */ "LOAD_LANE_16_A32_S\000" |
| 5384 | /* 17200 */ "STORE_LANE_I8x16_A32_S\000" |
| 5385 | /* 17223 */ "LOAD_V128_A32_S\000" |
| 5386 | /* 17239 */ "STORE_V128_A32_S\000" |
| 5387 | /* 17256 */ "LOAD_LANE_8_A32_S\000" |
| 5388 | /* 17274 */ "STORE_LANE_I16x8_A32_S\000" |
| 5389 | /* 17297 */ "LOAD_EXTEND_S_I16x8_A32_S\000" |
| 5390 | /* 17323 */ "LOAD_EXTEND_U_I16x8_A32_S\000" |
| 5391 | /* 17349 */ "anonymous_14793MEMORY_SIZE_A32_S\000" |
| 5392 | /* 17382 */ "MEMORY_FILL_A32_S\000" |
| 5393 | /* 17400 */ "LOAD32_SPLAT_A32_S\000" |
| 5394 | /* 17419 */ "LOAD64_SPLAT_A32_S\000" |
| 5395 | /* 17438 */ "LOAD16_SPLAT_A32_S\000" |
| 5396 | /* 17457 */ "LOAD8_SPLAT_A32_S\000" |
| 5397 | /* 17475 */ "MEMSET_A32_S\000" |
| 5398 | /* 17488 */ "MEMORY_INIT_A32_S\000" |
| 5399 | /* 17506 */ "anonymous_14793MEMORY_GROW_A32_S\000" |
| 5400 | /* 17539 */ "MEMORY_ATOMIC_NOTIFY_A32_S\000" |
| 5401 | /* 17566 */ "MEMCPY_A32_S\000" |
| 5402 | /* 17579 */ "MEMORY_COPY_A32_S\000" |
| 5403 | /* 17597 */ "FP_TO_SINT_I32_F32_S\000" |
| 5404 | /* 17618 */ "FP_TO_UINT_I32_F32_S\000" |
| 5405 | /* 17639 */ "FP_TO_SINT_I64_F32_S\000" |
| 5406 | /* 17660 */ "FP_TO_UINT_I64_F32_S\000" |
| 5407 | /* 17681 */ "SUB_F32_S\000" |
| 5408 | /* 17691 */ "TRUNC_F32_S\000" |
| 5409 | /* 17703 */ "ADD_F32_S\000" |
| 5410 | /* 17713 */ "LOCAL_TEE_F32_S\000" |
| 5411 | /* 17729 */ "GE_F32_S\000" |
| 5412 | /* 17738 */ "LE_F32_S\000" |
| 5413 | /* 17747 */ "NE_F32_S\000" |
| 5414 | /* 17756 */ "F64_PROMOTE_F32_S\000" |
| 5415 | /* 17774 */ "NEG_F32_S\000" |
| 5416 | /* 17784 */ "CEIL_F32_S\000" |
| 5417 | /* 17795 */ "MUL_F32_S\000" |
| 5418 | /* 17805 */ "COPYSIGN_F32_S\000" |
| 5419 | /* 17820 */ "MIN_F32_S\000" |
| 5420 | /* 17830 */ "DROP_F32_S\000" |
| 5421 | /* 17841 */ "EQ_F32_S\000" |
| 5422 | /* 17850 */ "FLOOR_F32_S\000" |
| 5423 | /* 17862 */ "ABS_F32_S\000" |
| 5424 | /* 17872 */ "I32_TRUNC_S_F32_S\000" |
| 5425 | /* 17890 */ "I64_TRUNC_S_F32_S\000" |
| 5426 | /* 17908 */ "I32_TRUNC_S_SAT_F32_S\000" |
| 5427 | /* 17930 */ "I64_TRUNC_S_SAT_F32_S\000" |
| 5428 | /* 17952 */ "I32_TRUNC_U_SAT_F32_S\000" |
| 5429 | /* 17974 */ "I64_TRUNC_U_SAT_F32_S\000" |
| 5430 | /* 17996 */ "SELECT_F32_S\000" |
| 5431 | /* 18009 */ "GLOBAL_GET_F32_S\000" |
| 5432 | /* 18026 */ "LOCAL_GET_F32_S\000" |
| 5433 | /* 18042 */ "I32_REINTERPRET_F32_S\000" |
| 5434 | /* 18064 */ "GLOBAL_SET_F32_S\000" |
| 5435 | /* 18081 */ "LOCAL_SET_F32_S\000" |
| 5436 | /* 18097 */ "GT_F32_S\000" |
| 5437 | /* 18106 */ "LT_F32_S\000" |
| 5438 | /* 18115 */ "SQRT_F32_S\000" |
| 5439 | /* 18126 */ "NEAREST_F32_S\000" |
| 5440 | /* 18140 */ "CONST_F32_S\000" |
| 5441 | /* 18152 */ "I32_TRUNC_U_F32_S\000" |
| 5442 | /* 18170 */ "I64_TRUNC_U_F32_S\000" |
| 5443 | /* 18188 */ "DIV_F32_S\000" |
| 5444 | /* 18198 */ "MAX_F32_S\000" |
| 5445 | /* 18208 */ "COPY_F32_S\000" |
| 5446 | /* 18219 */ "SUB_I32_S\000" |
| 5447 | /* 18229 */ "ADD_I32_S\000" |
| 5448 | /* 18239 */ "AND_I32_S\000" |
| 5449 | /* 18249 */ "LOCAL_TEE_I32_S\000" |
| 5450 | /* 18265 */ "BR_TABLE_I32_S\000" |
| 5451 | /* 18280 */ "NE_I32_S\000" |
| 5452 | /* 18289 */ "SHL_I32_S\000" |
| 5453 | /* 18299 */ "ROTL_I32_S\000" |
| 5454 | /* 18310 */ "MUL_I32_S\000" |
| 5455 | /* 18320 */ "DROP_I32_S\000" |
| 5456 | /* 18331 */ "EQ_I32_S\000" |
| 5457 | /* 18340 */ "XOR_I32_S\000" |
| 5458 | /* 18350 */ "ROTR_I32_S\000" |
| 5459 | /* 18361 */ "I32_EXTEND16_S_I32_S\000" |
| 5460 | /* 18382 */ "I32_EXTEND8_S_I32_S\000" |
| 5461 | /* 18402 */ "I64_EXTEND_S_I32_S\000" |
| 5462 | /* 18421 */ "GE_S_I32_S\000" |
| 5463 | /* 18432 */ "LE_S_I32_S\000" |
| 5464 | /* 18443 */ "REM_S_I32_S\000" |
| 5465 | /* 18455 */ "SHR_S_I32_S\000" |
| 5466 | /* 18467 */ "GT_S_I32_S\000" |
| 5467 | /* 18478 */ "LT_S_I32_S\000" |
| 5468 | /* 18489 */ "F32_CONVERT_S_I32_S\000" |
| 5469 | /* 18509 */ "F64_CONVERT_S_I32_S\000" |
| 5470 | /* 18529 */ "DIV_S_I32_S\000" |
| 5471 | /* 18541 */ "SELECT_I32_S\000" |
| 5472 | /* 18554 */ "GLOBAL_GET_I32_S\000" |
| 5473 | /* 18571 */ "LOCAL_GET_I32_S\000" |
| 5474 | /* 18587 */ "F32_REINTERPRET_I32_S\000" |
| 5475 | /* 18609 */ "GLOBAL_SET_I32_S\000" |
| 5476 | /* 18626 */ "LOCAL_SET_I32_S\000" |
| 5477 | /* 18642 */ "POPCNT_I32_S\000" |
| 5478 | /* 18655 */ "CONST_I32_S\000" |
| 5479 | /* 18667 */ "I64_EXTEND_U_I32_S\000" |
| 5480 | /* 18686 */ "GE_U_I32_S\000" |
| 5481 | /* 18697 */ "LE_U_I32_S\000" |
| 5482 | /* 18708 */ "REM_U_I32_S\000" |
| 5483 | /* 18720 */ "SHR_U_I32_S\000" |
| 5484 | /* 18732 */ "GT_U_I32_S\000" |
| 5485 | /* 18743 */ "LT_U_I32_S\000" |
| 5486 | /* 18754 */ "F32_CONVERT_U_I32_S\000" |
| 5487 | /* 18774 */ "F64_CONVERT_U_I32_S\000" |
| 5488 | /* 18794 */ "DIV_U_I32_S\000" |
| 5489 | /* 18806 */ "COPY_I32_S\000" |
| 5490 | /* 18817 */ "CLZ_I32_S\000" |
| 5491 | /* 18827 */ "EQZ_I32_S\000" |
| 5492 | /* 18837 */ "CTZ_I32_S\000" |
| 5493 | /* 18847 */ "ARGUMENT_v4f32_S\000" |
| 5494 | /* 18864 */ "ARGUMENT_f32_S\000" |
| 5495 | /* 18879 */ "ARGUMENT_v4i32_S\000" |
| 5496 | /* 18896 */ "ARGUMENT_i32_S\000" |
| 5497 | /* 18911 */ "CONST_V128_F64x2_S\000" |
| 5498 | /* 18930 */ "SUB_F64x2_S\000" |
| 5499 | /* 18942 */ "TRUNC_F64x2_S\000" |
| 5500 | /* 18956 */ "NMADD_F64x2_S\000" |
| 5501 | /* 18970 */ "GE_F64x2_S\000" |
| 5502 | /* 18981 */ "LE_F64x2_S\000" |
| 5503 | /* 18992 */ "REPLACE_LANE_F64x2_S\000" |
| 5504 | /* 19013 */ "EXTRACT_LANE_F64x2_S\000" |
| 5505 | /* 19034 */ "NEG_F64x2_S\000" |
| 5506 | /* 19046 */ "CEIL_F64x2_S\000" |
| 5507 | /* 19059 */ "MUL_F64x2_S\000" |
| 5508 | /* 19071 */ "SIMD_RELAXED_FMIN_F64x2_S\000" |
| 5509 | /* 19097 */ "PMIN_F64x2_S\000" |
| 5510 | /* 19110 */ "EQ_F64x2_S\000" |
| 5511 | /* 19121 */ "FLOOR_F64x2_S\000" |
| 5512 | /* 19135 */ "ABS_F64x2_S\000" |
| 5513 | /* 19147 */ "SPLAT_F64x2_S\000" |
| 5514 | /* 19161 */ "GT_F64x2_S\000" |
| 5515 | /* 19172 */ "LT_F64x2_S\000" |
| 5516 | /* 19183 */ "SQRT_F64x2_S\000" |
| 5517 | /* 19196 */ "NEAREST_F64x2_S\000" |
| 5518 | /* 19212 */ "DIV_F64x2_S\000" |
| 5519 | /* 19224 */ "SIMD_RELAXED_FMAX_F64x2_S\000" |
| 5520 | /* 19250 */ "PMAX_F64x2_S\000" |
| 5521 | /* 19263 */ "convert_low_s_F64x2_S\000" |
| 5522 | /* 19285 */ "convert_low_u_F64x2_S\000" |
| 5523 | /* 19307 */ "promote_low_F64x2_S\000" |
| 5524 | /* 19327 */ "CONST_V128_I64x2_S\000" |
| 5525 | /* 19346 */ "SUB_I64x2_S\000" |
| 5526 | /* 19358 */ "ADD_I64x2_S\000" |
| 5527 | /* 19370 */ "REPLACE_LANE_I64x2_S\000" |
| 5528 | /* 19391 */ "EXTRACT_LANE_I64x2_S\000" |
| 5529 | /* 19412 */ "ALLTRUE_I64x2_S\000" |
| 5530 | /* 19428 */ "NEG_I64x2_S\000" |
| 5531 | /* 19440 */ "BITMASK_I64x2_S\000" |
| 5532 | /* 19456 */ "SHL_I64x2_S\000" |
| 5533 | /* 19468 */ "MUL_I64x2_S\000" |
| 5534 | /* 19480 */ "EQ_I64x2_S\000" |
| 5535 | /* 19491 */ "ABS_I64x2_S\000" |
| 5536 | /* 19503 */ "GE_S_I64x2_S\000" |
| 5537 | /* 19516 */ "LE_S_I64x2_S\000" |
| 5538 | /* 19529 */ "EXTMUL_HIGH_S_I64x2_S\000" |
| 5539 | /* 19551 */ "SHR_S_I64x2_S\000" |
| 5540 | /* 19565 */ "GT_S_I64x2_S\000" |
| 5541 | /* 19578 */ "LT_S_I64x2_S\000" |
| 5542 | /* 19591 */ "EXTMUL_LOW_S_I64x2_S\000" |
| 5543 | /* 19612 */ "SPLAT_I64x2_S\000" |
| 5544 | /* 19626 */ "LANESELECT_I64x2_S\000" |
| 5545 | /* 19645 */ "EXTMUL_HIGH_U_I64x2_S\000" |
| 5546 | /* 19667 */ "SHR_U_I64x2_S\000" |
| 5547 | /* 19681 */ "EXTMUL_LOW_U_I64x2_S\000" |
| 5548 | /* 19702 */ "extend_high_s_I64x2_S\000" |
| 5549 | /* 19724 */ "extend_low_s_I64x2_S\000" |
| 5550 | /* 19745 */ "extend_high_u_I64x2_S\000" |
| 5551 | /* 19767 */ "extend_low_u_I64x2_S\000" |
| 5552 | /* 19788 */ "LOAD_F16_F32_A64_S\000" |
| 5553 | /* 19807 */ "STORE_F16_F32_A64_S\000" |
| 5554 | /* 19827 */ "LOAD_F32_A64_S\000" |
| 5555 | /* 19842 */ "STORE_F32_A64_S\000" |
| 5556 | /* 19858 */ "ATOMIC_STORE16_I32_A64_S\000" |
| 5557 | /* 19883 */ "ATOMIC_STORE8_I32_A64_S\000" |
| 5558 | /* 19907 */ "ATOMIC_RMW16_U_SUB_I32_A64_S\000" |
| 5559 | /* 19936 */ "ATOMIC_RMW8_U_SUB_I32_A64_S\000" |
| 5560 | /* 19964 */ "ATOMIC_RMW_SUB_I32_A64_S\000" |
| 5561 | /* 19989 */ "ATOMIC_LOAD_I32_A64_S\000" |
| 5562 | /* 20011 */ "ATOMIC_RMW16_U_ADD_I32_A64_S\000" |
| 5563 | /* 20040 */ "ATOMIC_RMW8_U_ADD_I32_A64_S\000" |
| 5564 | /* 20068 */ "ATOMIC_RMW_ADD_I32_A64_S\000" |
| 5565 | /* 20093 */ "ATOMIC_RMW16_U_AND_I32_A64_S\000" |
| 5566 | /* 20122 */ "ATOMIC_RMW8_U_AND_I32_A64_S\000" |
| 5567 | /* 20150 */ "ATOMIC_RMW_AND_I32_A64_S\000" |
| 5568 | /* 20175 */ "ATOMIC_STORE_I32_A64_S\000" |
| 5569 | /* 20198 */ "ATOMIC_RMW16_U_CMPXCHG_I32_A64_S\000" |
| 5570 | /* 20231 */ "ATOMIC_RMW8_U_CMPXCHG_I32_A64_S\000" |
| 5571 | /* 20263 */ "ATOMIC_RMW_CMPXCHG_I32_A64_S\000" |
| 5572 | /* 20292 */ "ATOMIC_RMW16_U_XCHG_I32_A64_S\000" |
| 5573 | /* 20322 */ "ATOMIC_RMW8_U_XCHG_I32_A64_S\000" |
| 5574 | /* 20351 */ "ATOMIC_RMW_XCHG_I32_A64_S\000" |
| 5575 | /* 20377 */ "ATOMIC_RMW16_U_XOR_I32_A64_S\000" |
| 5576 | /* 20406 */ "ATOMIC_RMW8_U_XOR_I32_A64_S\000" |
| 5577 | /* 20434 */ "ATOMIC_RMW_XOR_I32_A64_S\000" |
| 5578 | /* 20459 */ "ATOMIC_RMW16_U_OR_I32_A64_S\000" |
| 5579 | /* 20487 */ "ATOMIC_RMW8_U_OR_I32_A64_S\000" |
| 5580 | /* 20514 */ "ATOMIC_RMW_OR_I32_A64_S\000" |
| 5581 | /* 20538 */ "LOAD16_S_I32_A64_S\000" |
| 5582 | /* 20557 */ "LOAD8_S_I32_A64_S\000" |
| 5583 | /* 20575 */ "ATOMIC_LOAD16_U_I32_A64_S\000" |
| 5584 | /* 20601 */ "ATOMIC_LOAD8_U_I32_A64_S\000" |
| 5585 | /* 20626 */ "MEMORY_ATOMIC_WAIT32_A64_S\000" |
| 5586 | /* 20653 */ "LOAD_LANE_32_A64_S\000" |
| 5587 | /* 20672 */ "LOAD_ZERO_32_A64_S\000" |
| 5588 | /* 20691 */ "STORE_LANE_I64x2_A64_S\000" |
| 5589 | /* 20714 */ "LOAD_EXTEND_S_I64x2_A64_S\000" |
| 5590 | /* 20740 */ "LOAD_EXTEND_U_I64x2_A64_S\000" |
| 5591 | /* 20766 */ "LOAD_F64_A64_S\000" |
| 5592 | /* 20781 */ "STORE_F64_A64_S\000" |
| 5593 | /* 20797 */ "ATOMIC_STORE32_I64_A64_S\000" |
| 5594 | /* 20822 */ "ATOMIC_STORE16_I64_A64_S\000" |
| 5595 | /* 20847 */ "ATOMIC_STORE8_I64_A64_S\000" |
| 5596 | /* 20871 */ "ATOMIC_RMW32_U_SUB_I64_A64_S\000" |
| 5597 | /* 20900 */ "ATOMIC_RMW16_U_SUB_I64_A64_S\000" |
| 5598 | /* 20929 */ "ATOMIC_RMW8_U_SUB_I64_A64_S\000" |
| 5599 | /* 20957 */ "ATOMIC_RMW_SUB_I64_A64_S\000" |
| 5600 | /* 20982 */ "ATOMIC_LOAD_I64_A64_S\000" |
| 5601 | /* 21004 */ "ATOMIC_RMW32_U_ADD_I64_A64_S\000" |
| 5602 | /* 21033 */ "ATOMIC_RMW16_U_ADD_I64_A64_S\000" |
| 5603 | /* 21062 */ "ATOMIC_RMW8_U_ADD_I64_A64_S\000" |
| 5604 | /* 21090 */ "ATOMIC_RMW_ADD_I64_A64_S\000" |
| 5605 | /* 21115 */ "ATOMIC_RMW32_U_AND_I64_A64_S\000" |
| 5606 | /* 21144 */ "ATOMIC_RMW16_U_AND_I64_A64_S\000" |
| 5607 | /* 21173 */ "ATOMIC_RMW8_U_AND_I64_A64_S\000" |
| 5608 | /* 21201 */ "ATOMIC_RMW_AND_I64_A64_S\000" |
| 5609 | /* 21226 */ "ATOMIC_STORE_I64_A64_S\000" |
| 5610 | /* 21249 */ "ATOMIC_RMW32_U_CMPXCHG_I64_A64_S\000" |
| 5611 | /* 21282 */ "ATOMIC_RMW16_U_CMPXCHG_I64_A64_S\000" |
| 5612 | /* 21315 */ "ATOMIC_RMW8_U_CMPXCHG_I64_A64_S\000" |
| 5613 | /* 21347 */ "ATOMIC_RMW_CMPXCHG_I64_A64_S\000" |
| 5614 | /* 21376 */ "ATOMIC_RMW32_U_XCHG_I64_A64_S\000" |
| 5615 | /* 21406 */ "ATOMIC_RMW16_U_XCHG_I64_A64_S\000" |
| 5616 | /* 21436 */ "ATOMIC_RMW8_U_XCHG_I64_A64_S\000" |
| 5617 | /* 21465 */ "ATOMIC_RMW_XCHG_I64_A64_S\000" |
| 5618 | /* 21491 */ "ATOMIC_RMW32_U_XOR_I64_A64_S\000" |
| 5619 | /* 21520 */ "ATOMIC_RMW16_U_XOR_I64_A64_S\000" |
| 5620 | /* 21549 */ "ATOMIC_RMW8_U_XOR_I64_A64_S\000" |
| 5621 | /* 21577 */ "ATOMIC_RMW_XOR_I64_A64_S\000" |
| 5622 | /* 21602 */ "ATOMIC_RMW32_U_OR_I64_A64_S\000" |
| 5623 | /* 21630 */ "ATOMIC_RMW16_U_OR_I64_A64_S\000" |
| 5624 | /* 21658 */ "ATOMIC_RMW8_U_OR_I64_A64_S\000" |
| 5625 | /* 21685 */ "ATOMIC_RMW_OR_I64_A64_S\000" |
| 5626 | /* 21709 */ "LOAD32_S_I64_A64_S\000" |
| 5627 | /* 21728 */ "LOAD16_S_I64_A64_S\000" |
| 5628 | /* 21747 */ "LOAD8_S_I64_A64_S\000" |
| 5629 | /* 21765 */ "ATOMIC_LOAD32_U_I64_A64_S\000" |
| 5630 | /* 21791 */ "ATOMIC_LOAD16_U_I64_A64_S\000" |
| 5631 | /* 21817 */ "ATOMIC_LOAD8_U_I64_A64_S\000" |
| 5632 | /* 21842 */ "MEMORY_ATOMIC_WAIT64_A64_S\000" |
| 5633 | /* 21869 */ "LOAD_LANE_64_A64_S\000" |
| 5634 | /* 21888 */ "LOAD_ZERO_64_A64_S\000" |
| 5635 | /* 21907 */ "STORE_LANE_I32x4_A64_S\000" |
| 5636 | /* 21930 */ "LOAD_EXTEND_S_I32x4_A64_S\000" |
| 5637 | /* 21956 */ "LOAD_EXTEND_U_I32x4_A64_S\000" |
| 5638 | /* 21982 */ "LOAD_LANE_16_A64_S\000" |
| 5639 | /* 22001 */ "STORE_LANE_I8x16_A64_S\000" |
| 5640 | /* 22024 */ "LOAD_V128_A64_S\000" |
| 5641 | /* 22040 */ "STORE_V128_A64_S\000" |
| 5642 | /* 22057 */ "LOAD_LANE_8_A64_S\000" |
| 5643 | /* 22075 */ "STORE_LANE_I16x8_A64_S\000" |
| 5644 | /* 22098 */ "LOAD_EXTEND_S_I16x8_A64_S\000" |
| 5645 | /* 22124 */ "LOAD_EXTEND_U_I16x8_A64_S\000" |
| 5646 | /* 22150 */ "anonymous_14794MEMORY_SIZE_A64_S\000" |
| 5647 | /* 22183 */ "MEMORY_FILL_A64_S\000" |
| 5648 | /* 22201 */ "LOAD32_SPLAT_A64_S\000" |
| 5649 | /* 22220 */ "LOAD64_SPLAT_A64_S\000" |
| 5650 | /* 22239 */ "LOAD16_SPLAT_A64_S\000" |
| 5651 | /* 22258 */ "LOAD8_SPLAT_A64_S\000" |
| 5652 | /* 22276 */ "MEMSET_A64_S\000" |
| 5653 | /* 22289 */ "MEMORY_INIT_A64_S\000" |
| 5654 | /* 22307 */ "anonymous_14794MEMORY_GROW_A64_S\000" |
| 5655 | /* 22340 */ "MEMORY_ATOMIC_NOTIFY_A64_S\000" |
| 5656 | /* 22367 */ "MEMCPY_A64_S\000" |
| 5657 | /* 22380 */ "MEMORY_COPY_A64_S\000" |
| 5658 | /* 22398 */ "FP_TO_SINT_I32_F64_S\000" |
| 5659 | /* 22419 */ "FP_TO_UINT_I32_F64_S\000" |
| 5660 | /* 22440 */ "FP_TO_SINT_I64_F64_S\000" |
| 5661 | /* 22461 */ "FP_TO_UINT_I64_F64_S\000" |
| 5662 | /* 22482 */ "SUB_F64_S\000" |
| 5663 | /* 22492 */ "TRUNC_F64_S\000" |
| 5664 | /* 22504 */ "ADD_F64_S\000" |
| 5665 | /* 22514 */ "LOCAL_TEE_F64_S\000" |
| 5666 | /* 22530 */ "GE_F64_S\000" |
| 5667 | /* 22539 */ "LE_F64_S\000" |
| 5668 | /* 22548 */ "NE_F64_S\000" |
| 5669 | /* 22557 */ "F32_DEMOTE_F64_S\000" |
| 5670 | /* 22574 */ "NEG_F64_S\000" |
| 5671 | /* 22584 */ "CEIL_F64_S\000" |
| 5672 | /* 22595 */ "MUL_F64_S\000" |
| 5673 | /* 22605 */ "COPYSIGN_F64_S\000" |
| 5674 | /* 22620 */ "MIN_F64_S\000" |
| 5675 | /* 22630 */ "DROP_F64_S\000" |
| 5676 | /* 22641 */ "EQ_F64_S\000" |
| 5677 | /* 22650 */ "FLOOR_F64_S\000" |
| 5678 | /* 22662 */ "ABS_F64_S\000" |
| 5679 | /* 22672 */ "I32_TRUNC_S_F64_S\000" |
| 5680 | /* 22690 */ "I64_TRUNC_S_F64_S\000" |
| 5681 | /* 22708 */ "I32_TRUNC_S_SAT_F64_S\000" |
| 5682 | /* 22730 */ "I64_TRUNC_S_SAT_F64_S\000" |
| 5683 | /* 22752 */ "I32_TRUNC_U_SAT_F64_S\000" |
| 5684 | /* 22774 */ "I64_TRUNC_U_SAT_F64_S\000" |
| 5685 | /* 22796 */ "SELECT_F64_S\000" |
| 5686 | /* 22809 */ "GLOBAL_GET_F64_S\000" |
| 5687 | /* 22826 */ "LOCAL_GET_F64_S\000" |
| 5688 | /* 22842 */ "I64_REINTERPRET_F64_S\000" |
| 5689 | /* 22864 */ "GLOBAL_SET_F64_S\000" |
| 5690 | /* 22881 */ "LOCAL_SET_F64_S\000" |
| 5691 | /* 22897 */ "GT_F64_S\000" |
| 5692 | /* 22906 */ "LT_F64_S\000" |
| 5693 | /* 22915 */ "SQRT_F64_S\000" |
| 5694 | /* 22926 */ "NEAREST_F64_S\000" |
| 5695 | /* 22940 */ "CONST_F64_S\000" |
| 5696 | /* 22952 */ "I32_TRUNC_U_F64_S\000" |
| 5697 | /* 22970 */ "I64_TRUNC_U_F64_S\000" |
| 5698 | /* 22988 */ "DIV_F64_S\000" |
| 5699 | /* 22998 */ "MAX_F64_S\000" |
| 5700 | /* 23008 */ "COPY_F64_S\000" |
| 5701 | /* 23019 */ "SUB_I64_S\000" |
| 5702 | /* 23029 */ "ADD_I64_S\000" |
| 5703 | /* 23039 */ "AND_I64_S\000" |
| 5704 | /* 23049 */ "LOCAL_TEE_I64_S\000" |
| 5705 | /* 23065 */ "BR_TABLE_I64_S\000" |
| 5706 | /* 23080 */ "NE_I64_S\000" |
| 5707 | /* 23089 */ "SHL_I64_S\000" |
| 5708 | /* 23099 */ "ROTL_I64_S\000" |
| 5709 | /* 23110 */ "MUL_I64_S\000" |
| 5710 | /* 23120 */ "I32_WRAP_I64_S\000" |
| 5711 | /* 23135 */ "DROP_I64_S\000" |
| 5712 | /* 23146 */ "EQ_I64_S\000" |
| 5713 | /* 23155 */ "XOR_I64_S\000" |
| 5714 | /* 23165 */ "ROTR_I64_S\000" |
| 5715 | /* 23176 */ "I64_EXTEND32_S_I64_S\000" |
| 5716 | /* 23197 */ "I64_EXTEND16_S_I64_S\000" |
| 5717 | /* 23218 */ "I64_EXTEND8_S_I64_S\000" |
| 5718 | /* 23238 */ "GE_S_I64_S\000" |
| 5719 | /* 23249 */ "LE_S_I64_S\000" |
| 5720 | /* 23260 */ "REM_S_I64_S\000" |
| 5721 | /* 23272 */ "SHR_S_I64_S\000" |
| 5722 | /* 23284 */ "GT_S_I64_S\000" |
| 5723 | /* 23295 */ "LT_S_I64_S\000" |
| 5724 | /* 23306 */ "F32_CONVERT_S_I64_S\000" |
| 5725 | /* 23326 */ "F64_CONVERT_S_I64_S\000" |
| 5726 | /* 23346 */ "DIV_S_I64_S\000" |
| 5727 | /* 23358 */ "SELECT_I64_S\000" |
| 5728 | /* 23371 */ "GLOBAL_GET_I64_S\000" |
| 5729 | /* 23388 */ "LOCAL_GET_I64_S\000" |
| 5730 | /* 23404 */ "F64_REINTERPRET_I64_S\000" |
| 5731 | /* 23426 */ "GLOBAL_SET_I64_S\000" |
| 5732 | /* 23443 */ "LOCAL_SET_I64_S\000" |
| 5733 | /* 23459 */ "POPCNT_I64_S\000" |
| 5734 | /* 23472 */ "CONST_I64_S\000" |
| 5735 | /* 23484 */ "GE_U_I64_S\000" |
| 5736 | /* 23495 */ "LE_U_I64_S\000" |
| 5737 | /* 23506 */ "REM_U_I64_S\000" |
| 5738 | /* 23518 */ "SHR_U_I64_S\000" |
| 5739 | /* 23530 */ "GT_U_I64_S\000" |
| 5740 | /* 23541 */ "LT_U_I64_S\000" |
| 5741 | /* 23552 */ "F32_CONVERT_U_I64_S\000" |
| 5742 | /* 23572 */ "F64_CONVERT_U_I64_S\000" |
| 5743 | /* 23592 */ "DIV_U_I64_S\000" |
| 5744 | /* 23604 */ "COPY_I64_S\000" |
| 5745 | /* 23615 */ "CLZ_I64_S\000" |
| 5746 | /* 23625 */ "EQZ_I64_S\000" |
| 5747 | /* 23635 */ "CTZ_I64_S\000" |
| 5748 | /* 23645 */ "ARGUMENT_v2f64_S\000" |
| 5749 | /* 23662 */ "ARGUMENT_f64_S\000" |
| 5750 | /* 23677 */ "ARGUMENT_v2i64_S\000" |
| 5751 | /* 23694 */ "ARGUMENT_i64_S\000" |
| 5752 | /* 23709 */ "CONST_V128_F32x4_S\000" |
| 5753 | /* 23728 */ "SUB_F32x4_S\000" |
| 5754 | /* 23740 */ "TRUNC_F32x4_S\000" |
| 5755 | /* 23754 */ "NMADD_F32x4_S\000" |
| 5756 | /* 23768 */ "GE_F32x4_S\000" |
| 5757 | /* 23779 */ "LE_F32x4_S\000" |
| 5758 | /* 23790 */ "REPLACE_LANE_F32x4_S\000" |
| 5759 | /* 23811 */ "EXTRACT_LANE_F32x4_S\000" |
| 5760 | /* 23832 */ "NEG_F32x4_S\000" |
| 5761 | /* 23844 */ "CEIL_F32x4_S\000" |
| 5762 | /* 23857 */ "MUL_F32x4_S\000" |
| 5763 | /* 23869 */ "SIMD_RELAXED_FMIN_F32x4_S\000" |
| 5764 | /* 23895 */ "PMIN_F32x4_S\000" |
| 5765 | /* 23908 */ "EQ_F32x4_S\000" |
| 5766 | /* 23919 */ "FLOOR_F32x4_S\000" |
| 5767 | /* 23933 */ "ABS_F32x4_S\000" |
| 5768 | /* 23945 */ "SPLAT_F32x4_S\000" |
| 5769 | /* 23959 */ "GT_F32x4_S\000" |
| 5770 | /* 23970 */ "LT_F32x4_S\000" |
| 5771 | /* 23981 */ "SQRT_F32x4_S\000" |
| 5772 | /* 23994 */ "NEAREST_F32x4_S\000" |
| 5773 | /* 24010 */ "DIV_F32x4_S\000" |
| 5774 | /* 24022 */ "SIMD_RELAXED_FMAX_F32x4_S\000" |
| 5775 | /* 24048 */ "PMAX_F32x4_S\000" |
| 5776 | /* 24061 */ "demote_zero_F32x4_S\000" |
| 5777 | /* 24081 */ "sint_to_fp_F32x4_S\000" |
| 5778 | /* 24100 */ "uint_to_fp_F32x4_S\000" |
| 5779 | /* 24119 */ "promote_low_F32x4_S\000" |
| 5780 | /* 24139 */ "CONST_V128_I32x4_S\000" |
| 5781 | /* 24158 */ "SUB_I32x4_S\000" |
| 5782 | /* 24170 */ "ADD_I32x4_S\000" |
| 5783 | /* 24182 */ "REPLACE_LANE_I32x4_S\000" |
| 5784 | /* 24203 */ "EXTRACT_LANE_I32x4_S\000" |
| 5785 | /* 24224 */ "ALLTRUE_I32x4_S\000" |
| 5786 | /* 24240 */ "NEG_I32x4_S\000" |
| 5787 | /* 24252 */ "BITMASK_I32x4_S\000" |
| 5788 | /* 24268 */ "SHL_I32x4_S\000" |
| 5789 | /* 24280 */ "MUL_I32x4_S\000" |
| 5790 | /* 24292 */ "EQ_I32x4_S\000" |
| 5791 | /* 24303 */ "ABS_I32x4_S\000" |
| 5792 | /* 24315 */ "GE_S_I32x4_S\000" |
| 5793 | /* 24328 */ "LE_S_I32x4_S\000" |
| 5794 | /* 24341 */ "EXTMUL_HIGH_S_I32x4_S\000" |
| 5795 | /* 24363 */ "MIN_S_I32x4_S\000" |
| 5796 | /* 24377 */ "SHR_S_I32x4_S\000" |
| 5797 | /* 24391 */ "GT_S_I32x4_S\000" |
| 5798 | /* 24404 */ "LT_S_I32x4_S\000" |
| 5799 | /* 24417 */ "EXTMUL_LOW_S_I32x4_S\000" |
| 5800 | /* 24438 */ "MAX_S_I32x4_S\000" |
| 5801 | /* 24452 */ "SPLAT_I32x4_S\000" |
| 5802 | /* 24466 */ "LANESELECT_I32x4_S\000" |
| 5803 | /* 24485 */ "GE_U_I32x4_S\000" |
| 5804 | /* 24498 */ "LE_U_I32x4_S\000" |
| 5805 | /* 24511 */ "EXTMUL_HIGH_U_I32x4_S\000" |
| 5806 | /* 24533 */ "MIN_U_I32x4_S\000" |
| 5807 | /* 24547 */ "SHR_U_I32x4_S\000" |
| 5808 | /* 24561 */ "GT_U_I32x4_S\000" |
| 5809 | /* 24574 */ "LT_U_I32x4_S\000" |
| 5810 | /* 24587 */ "EXTMUL_LOW_U_I32x4_S\000" |
| 5811 | /* 24608 */ "MAX_U_I32x4_S\000" |
| 5812 | /* 24622 */ "int_wasm_relaxed_trunc_signed_I32x4_S\000" |
| 5813 | /* 24660 */ "int_wasm_relaxed_trunc_unsigned_I32x4_S\000" |
| 5814 | /* 24700 */ "int_wasm_relaxed_trunc_signed_zero_I32x4_S\000" |
| 5815 | /* 24743 */ "int_wasm_relaxed_trunc_unsigned_zero_I32x4_S\000" |
| 5816 | /* 24788 */ "extadd_pairwise_s_I32x4_S\000" |
| 5817 | /* 24814 */ "extend_high_s_I32x4_S\000" |
| 5818 | /* 24836 */ "trunc_sat_zero_s_I32x4_S\000" |
| 5819 | /* 24861 */ "extend_low_s_I32x4_S\000" |
| 5820 | /* 24882 */ "fp_to_sint_I32x4_S\000" |
| 5821 | /* 24901 */ "fp_to_uint_I32x4_S\000" |
| 5822 | /* 24920 */ "extadd_pairwise_u_I32x4_S\000" |
| 5823 | /* 24946 */ "extend_high_u_I32x4_S\000" |
| 5824 | /* 24968 */ "trunc_sat_zero_u_I32x4_S\000" |
| 5825 | /* 24993 */ "extend_low_u_I32x4_S\000" |
| 5826 | /* 25014 */ "ARGUMENT_v8f16_S\000" |
| 5827 | /* 25031 */ "ARGUMENT_v8i16_S\000" |
| 5828 | /* 25048 */ "CONST_V128_I8x16_S\000" |
| 5829 | /* 25067 */ "SUB_I8x16_S\000" |
| 5830 | /* 25079 */ "ADD_I8x16_S\000" |
| 5831 | /* 25091 */ "REPLACE_LANE_I8x16_S\000" |
| 5832 | /* 25112 */ "ALLTRUE_I8x16_S\000" |
| 5833 | /* 25128 */ "NEG_I8x16_S\000" |
| 5834 | /* 25140 */ "BITMASK_I8x16_S\000" |
| 5835 | /* 25156 */ "SHL_I8x16_S\000" |
| 5836 | /* 25168 */ "EQ_I8x16_S\000" |
| 5837 | /* 25179 */ "ABS_I8x16_S\000" |
| 5838 | /* 25191 */ "GE_S_I8x16_S\000" |
| 5839 | /* 25204 */ "LE_S_I8x16_S\000" |
| 5840 | /* 25217 */ "MIN_S_I8x16_S\000" |
| 5841 | /* 25231 */ "SHR_S_I8x16_S\000" |
| 5842 | /* 25245 */ "SUB_SAT_S_I8x16_S\000" |
| 5843 | /* 25263 */ "ADD_SAT_S_I8x16_S\000" |
| 5844 | /* 25281 */ "GT_S_I8x16_S\000" |
| 5845 | /* 25294 */ "LT_S_I8x16_S\000" |
| 5846 | /* 25307 */ "NARROW_S_I8x16_S\000" |
| 5847 | /* 25324 */ "MAX_S_I8x16_S\000" |
| 5848 | /* 25338 */ "SPLAT_I8x16_S\000" |
| 5849 | /* 25352 */ "LANESELECT_I8x16_S\000" |
| 5850 | /* 25371 */ "POPCNT_I8x16_S\000" |
| 5851 | /* 25386 */ "GE_U_I8x16_S\000" |
| 5852 | /* 25399 */ "LE_U_I8x16_S\000" |
| 5853 | /* 25412 */ "MIN_U_I8x16_S\000" |
| 5854 | /* 25426 */ "AVGR_U_I8x16_S\000" |
| 5855 | /* 25441 */ "SHR_U_I8x16_S\000" |
| 5856 | /* 25455 */ "SUB_SAT_U_I8x16_S\000" |
| 5857 | /* 25473 */ "ADD_SAT_U_I8x16_S\000" |
| 5858 | /* 25491 */ "GT_U_I8x16_S\000" |
| 5859 | /* 25504 */ "LT_U_I8x16_S\000" |
| 5860 | /* 25517 */ "NARROW_U_I8x16_S\000" |
| 5861 | /* 25534 */ "MAX_U_I8x16_S\000" |
| 5862 | /* 25548 */ "I64_SUB128_S\000" |
| 5863 | /* 25561 */ "I64_ADD128_S\000" |
| 5864 | /* 25574 */ "LOCAL_TEE_V128_S\000" |
| 5865 | /* 25591 */ "DROP_V128_S\000" |
| 5866 | /* 25603 */ "SELECT_V128_S\000" |
| 5867 | /* 25617 */ "GLOBAL_GET_V128_S\000" |
| 5868 | /* 25635 */ "LOCAL_GET_V128_S\000" |
| 5869 | /* 25652 */ "GLOBAL_SET_V128_S\000" |
| 5870 | /* 25670 */ "LOCAL_SET_V128_S\000" |
| 5871 | /* 25687 */ "COPY_V128_S\000" |
| 5872 | /* 25699 */ "ARGUMENT_v16i8_S\000" |
| 5873 | /* 25716 */ "SUB_F16x8_S\000" |
| 5874 | /* 25728 */ "TRUNC_F16x8_S\000" |
| 5875 | /* 25742 */ "NMADD_F16x8_S\000" |
| 5876 | /* 25756 */ "GE_F16x8_S\000" |
| 5877 | /* 25767 */ "LE_F16x8_S\000" |
| 5878 | /* 25778 */ "REPLACE_LANE_F16x8_S\000" |
| 5879 | /* 25799 */ "EXTRACT_LANE_F16x8_S\000" |
| 5880 | /* 25820 */ "NEG_F16x8_S\000" |
| 5881 | /* 25832 */ "CEIL_F16x8_S\000" |
| 5882 | /* 25845 */ "MUL_F16x8_S\000" |
| 5883 | /* 25857 */ "PMIN_F16x8_S\000" |
| 5884 | /* 25870 */ "EQ_F16x8_S\000" |
| 5885 | /* 25881 */ "FLOOR_F16x8_S\000" |
| 5886 | /* 25895 */ "ABS_F16x8_S\000" |
| 5887 | /* 25907 */ "SPLAT_F16x8_S\000" |
| 5888 | /* 25921 */ "GT_F16x8_S\000" |
| 5889 | /* 25932 */ "LT_F16x8_S\000" |
| 5890 | /* 25943 */ "SQRT_F16x8_S\000" |
| 5891 | /* 25956 */ "NEAREST_F16x8_S\000" |
| 5892 | /* 25972 */ "DIV_F16x8_S\000" |
| 5893 | /* 25984 */ "PMAX_F16x8_S\000" |
| 5894 | /* 25997 */ "demote_zero_F16x8_S\000" |
| 5895 | /* 26017 */ "sint_to_fp_F16x8_S\000" |
| 5896 | /* 26036 */ "uint_to_fp_F16x8_S\000" |
| 5897 | /* 26055 */ "CONST_V128_I16x8_S\000" |
| 5898 | /* 26074 */ "SUB_I16x8_S\000" |
| 5899 | /* 26086 */ "ADD_I16x8_S\000" |
| 5900 | /* 26098 */ "REPLACE_LANE_I16x8_S\000" |
| 5901 | /* 26119 */ "ALLTRUE_I16x8_S\000" |
| 5902 | /* 26135 */ "NEG_I16x8_S\000" |
| 5903 | /* 26147 */ "BITMASK_I16x8_S\000" |
| 5904 | /* 26163 */ "SHL_I16x8_S\000" |
| 5905 | /* 26175 */ "MUL_I16x8_S\000" |
| 5906 | /* 26187 */ "EQ_I16x8_S\000" |
| 5907 | /* 26198 */ "ABS_I16x8_S\000" |
| 5908 | /* 26210 */ "GE_S_I16x8_S\000" |
| 5909 | /* 26223 */ "LE_S_I16x8_S\000" |
| 5910 | /* 26236 */ "EXTMUL_HIGH_S_I16x8_S\000" |
| 5911 | /* 26258 */ "MIN_S_I16x8_S\000" |
| 5912 | /* 26272 */ "SHR_S_I16x8_S\000" |
| 5913 | /* 26286 */ "RELAXED_Q15MULR_S_I16x8_S\000" |
| 5914 | /* 26312 */ "SUB_SAT_S_I16x8_S\000" |
| 5915 | /* 26330 */ "ADD_SAT_S_I16x8_S\000" |
| 5916 | /* 26348 */ "Q15MULR_SAT_S_I16x8_S\000" |
| 5917 | /* 26370 */ "GT_S_I16x8_S\000" |
| 5918 | /* 26383 */ "LT_S_I16x8_S\000" |
| 5919 | /* 26396 */ "EXTMUL_LOW_S_I16x8_S\000" |
| 5920 | /* 26417 */ "NARROW_S_I16x8_S\000" |
| 5921 | /* 26434 */ "MAX_S_I16x8_S\000" |
| 5922 | /* 26448 */ "SPLAT_I16x8_S\000" |
| 5923 | /* 26462 */ "LANESELECT_I16x8_S\000" |
| 5924 | /* 26481 */ "GE_U_I16x8_S\000" |
| 5925 | /* 26494 */ "LE_U_I16x8_S\000" |
| 5926 | /* 26507 */ "EXTMUL_HIGH_U_I16x8_S\000" |
| 5927 | /* 26529 */ "MIN_U_I16x8_S\000" |
| 5928 | /* 26543 */ "AVGR_U_I16x8_S\000" |
| 5929 | /* 26558 */ "SHR_U_I16x8_S\000" |
| 5930 | /* 26572 */ "SUB_SAT_U_I16x8_S\000" |
| 5931 | /* 26590 */ "ADD_SAT_U_I16x8_S\000" |
| 5932 | /* 26608 */ "GT_U_I16x8_S\000" |
| 5933 | /* 26621 */ "LT_U_I16x8_S\000" |
| 5934 | /* 26634 */ "EXTMUL_LOW_U_I16x8_S\000" |
| 5935 | /* 26655 */ "NARROW_U_I16x8_S\000" |
| 5936 | /* 26672 */ "MAX_U_I16x8_S\000" |
| 5937 | /* 26686 */ "extadd_pairwise_s_I16x8_S\000" |
| 5938 | /* 26712 */ "extend_high_s_I16x8_S\000" |
| 5939 | /* 26734 */ "extend_low_s_I16x8_S\000" |
| 5940 | /* 26755 */ "fp_to_sint_I16x8_S\000" |
| 5941 | /* 26774 */ "fp_to_uint_I16x8_S\000" |
| 5942 | /* 26793 */ "extadd_pairwise_u_I16x8_S\000" |
| 5943 | /* 26819 */ "extend_high_u_I16x8_S\000" |
| 5944 | /* 26841 */ "extend_low_u_I16x8_S\000" |
| 5945 | /* 26862 */ "REF_FUNC_S\000" |
| 5946 | /* 26873 */ "RELAXED_DOT_ADD_S\000" |
| 5947 | /* 26891 */ "AND_S\000" |
| 5948 | /* 26897 */ "END_S\000" |
| 5949 | /* 26903 */ "ATOMIC_FENCE_S\000" |
| 5950 | /* 26918 */ "COMPILER_FENCE_S\000" |
| 5951 | /* 26935 */ "I64_MUL_WIDE_S\000" |
| 5952 | /* 26950 */ "DEBUG_UNREACHABLE_S\000" |
| 5953 | /* 26970 */ "END_TRY_TABLE_S\000" |
| 5954 | /* 26986 */ "SHUFFLE_S\000" |
| 5955 | /* 26996 */ "RELAXED_SWIZZLE_S\000" |
| 5956 | /* 27014 */ "ELSE_S\000" |
| 5957 | /* 27021 */ "DELEGATE_S\000" |
| 5958 | /* 27032 */ "ANYTRUE_S\000" |
| 5959 | /* 27042 */ "TABLE_SIZE_S\000" |
| 5960 | /* 27055 */ "LOCAL_TEE_FUNCREF_S\000" |
| 5961 | /* 27075 */ "TABLE_FILL_FUNCREF_S\000" |
| 5962 | /* 27096 */ "REF_NULL_FUNCREF_S\000" |
| 5963 | /* 27115 */ "REF_IS_NULL_FUNCREF_S\000" |
| 5964 | /* 27137 */ "DROP_FUNCREF_S\000" |
| 5965 | /* 27152 */ "SELECT_FUNCREF_S\000" |
| 5966 | /* 27169 */ "TABLE_GET_FUNCREF_S\000" |
| 5967 | /* 27189 */ "GLOBAL_GET_FUNCREF_S\000" |
| 5968 | /* 27210 */ "LOCAL_GET_FUNCREF_S\000" |
| 5969 | /* 27230 */ "TABLE_SET_FUNCREF_S\000" |
| 5970 | /* 27250 */ "GLOBAL_SET_FUNCREF_S\000" |
| 5971 | /* 27271 */ "LOCAL_SET_FUNCREF_S\000" |
| 5972 | /* 27291 */ "REF_CAST_FUNCREF_S\000" |
| 5973 | /* 27310 */ "REF_TEST_FUNCREF_S\000" |
| 5974 | /* 27329 */ "TABLE_GROW_FUNCREF_S\000" |
| 5975 | /* 27350 */ "COPY_FUNCREF_S\000" |
| 5976 | /* 27365 */ "LOCAL_TEE_EXTERNREF_S\000" |
| 5977 | /* 27387 */ "TABLE_FILL_EXTERNREF_S\000" |
| 5978 | /* 27410 */ "REF_NULL_EXTERNREF_S\000" |
| 5979 | /* 27431 */ "REF_IS_NULL_EXTERNREF_S\000" |
| 5980 | /* 27455 */ "DROP_EXTERNREF_S\000" |
| 5981 | /* 27472 */ "SELECT_EXTERNREF_S\000" |
| 5982 | /* 27491 */ "TABLE_GET_EXTERNREF_S\000" |
| 5983 | /* 27513 */ "GLOBAL_GET_EXTERNREF_S\000" |
| 5984 | /* 27536 */ "LOCAL_GET_EXTERNREF_S\000" |
| 5985 | /* 27558 */ "TABLE_SET_EXTERNREF_S\000" |
| 5986 | /* 27580 */ "GLOBAL_SET_EXTERNREF_S\000" |
| 5987 | /* 27603 */ "LOCAL_SET_EXTERNREF_S\000" |
| 5988 | /* 27625 */ "TABLE_GROW_EXTERNREF_S\000" |
| 5989 | /* 27648 */ "COPY_EXTERNREF_S\000" |
| 5990 | /* 27665 */ "LOCAL_TEE_EXNREF_S\000" |
| 5991 | /* 27684 */ "TABLE_FILL_EXNREF_S\000" |
| 5992 | /* 27704 */ "REF_NULL_EXNREF_S\000" |
| 5993 | /* 27722 */ "REF_IS_NULL_EXNREF_S\000" |
| 5994 | /* 27743 */ "DROP_EXNREF_S\000" |
| 5995 | /* 27757 */ "SELECT_EXNREF_S\000" |
| 5996 | /* 27773 */ "TABLE_GET_EXNREF_S\000" |
| 5997 | /* 27792 */ "GLOBAL_GET_EXNREF_S\000" |
| 5998 | /* 27812 */ "LOCAL_GET_EXNREF_S\000" |
| 5999 | /* 27831 */ "TABLE_SET_EXNREF_S\000" |
| 6000 | /* 27850 */ "GLOBAL_SET_EXNREF_S\000" |
| 6001 | /* 27870 */ "LOCAL_SET_EXNREF_S\000" |
| 6002 | /* 27889 */ "TABLE_GROW_EXNREF_S\000" |
| 6003 | /* 27909 */ "COPY_EXNREF_S\000" |
| 6004 | /* 27923 */ "CATCH_REF_S\000" |
| 6005 | /* 27935 */ "RET_CALL_REF_S\000" |
| 6006 | /* 27950 */ "CATCH_ALL_REF_S\000" |
| 6007 | /* 27966 */ "THROW_REF_S\000" |
| 6008 | /* 27978 */ "END_IF_S\000" |
| 6009 | /* 27987 */ "BR_IF_S\000" |
| 6010 | /* 27995 */ "CATCH_S\000" |
| 6011 | /* 28003 */ "END_BLOCK_S\000" |
| 6012 | /* 28015 */ "RET_CALL_S\000" |
| 6013 | /* 28026 */ "CATCH_ALL_S\000" |
| 6014 | /* 28038 */ "END_FUNCTION_S\000" |
| 6015 | /* 28053 */ "FALLTHROUGH_RETURN_S\000" |
| 6016 | /* 28074 */ "ADJCALLSTACKDOWN_S\000" |
| 6017 | /* 28093 */ "NOP_S\000" |
| 6018 | /* 28099 */ "END_LOOP_S\000" |
| 6019 | /* 28110 */ "DATA_DROP_S\000" |
| 6020 | /* 28122 */ "ADJCALLSTACKUP_S\000" |
| 6021 | /* 28139 */ "BR_S\000" |
| 6022 | /* 28144 */ "XOR_S\000" |
| 6023 | /* 28150 */ "CALL_PARAMS_S\000" |
| 6024 | /* 28164 */ "BR_UNLESS_S\000" |
| 6025 | /* 28176 */ "RET_CALL_RESULTS_S\000" |
| 6026 | /* 28195 */ "I64_MUL_WIDE_S_S\000" |
| 6027 | /* 28212 */ "RELAXED_DOT_BFLOAT_S\000" |
| 6028 | /* 28233 */ "G_TRUNC_SSAT_S\000" |
| 6029 | /* 28248 */ "BITSELECT_S\000" |
| 6030 | /* 28260 */ "RET_CALL_INDIRECT_S\000" |
| 6031 | /* 28280 */ "CATCHRET_S\000" |
| 6032 | /* 28291 */ "CLEANUPRET_S\000" |
| 6033 | /* 28304 */ "RELAXED_DOT_S\000" |
| 6034 | /* 28318 */ "ANDNOT_S\000" |
| 6035 | /* 28327 */ "SELECT_T_S\000" |
| 6036 | /* 28338 */ "I64_MUL_WIDE_U_S\000" |
| 6037 | /* 28355 */ "RETHROW_S\000" |
| 6038 | /* 28365 */ "CATCH_LEGACY_S\000" |
| 6039 | /* 28380 */ "CATCH_ALL_LEGACY_S\000" |
| 6040 | /* 28399 */ "TABLE_COPY_S\000" |
| 6041 | /* 28412 */ "END_TRY_S\000" |
| 6042 | /* 28422 */ "ARGUMENT_funcref_S\000" |
| 6043 | /* 28441 */ "ARGUMENT_externref_S\000" |
| 6044 | /* 28462 */ "ARGUMENT_exnref_S\000" |
| 6045 | /* 28480 */ "EXTRACT_LANE_I8x16_s_S\000" |
| 6046 | /* 28503 */ "EXTRACT_LANE_I16x8_s_S\000" |
| 6047 | /* 28526 */ "EXTRACT_LANE_I8x16_u_S\000" |
| 6048 | /* 28549 */ "EXTRACT_LANE_I16x8_u_S\000" |
| 6049 | /* 28572 */ "RELAXED_DOT_BFLOAT\000" |
| 6050 | /* 28591 */ "G_SSUBSAT\000" |
| 6051 | /* 28601 */ "G_USUBSAT\000" |
| 6052 | /* 28611 */ "G_SADDSAT\000" |
| 6053 | /* 28621 */ "G_UADDSAT\000" |
| 6054 | /* 28631 */ "G_SSHLSAT\000" |
| 6055 | /* 28641 */ "G_USHLSAT\000" |
| 6056 | /* 28651 */ "G_SMULFIXSAT\000" |
| 6057 | /* 28664 */ "G_UMULFIXSAT\000" |
| 6058 | /* 28677 */ "G_SDIVFIXSAT\000" |
| 6059 | /* 28690 */ "G_UDIVFIXSAT\000" |
| 6060 | /* 28703 */ "G_ATOMICRMW_USUB_SAT\000" |
| 6061 | /* 28724 */ "G_FPTOSI_SAT\000" |
| 6062 | /* 28737 */ "G_FPTOUI_SAT\000" |
| 6063 | /* 28750 */ "G_EXTRACT\000" |
| 6064 | /* 28760 */ "BITSELECT\000" |
| 6065 | /* 28770 */ "G_SELECT\000" |
| 6066 | /* 28779 */ "G_BRINDIRECT\000" |
| 6067 | /* 28792 */ "RET_CALL_INDIRECT\000" |
| 6068 | /* 28810 */ "CATCHRET\000" |
| 6069 | /* 28819 */ "CLEANUPRET\000" |
| 6070 | /* 28830 */ "PATCHABLE_RET\000" |
| 6071 | /* 28844 */ "G_MEMSET\000" |
| 6072 | /* 28853 */ "PATCHABLE_FUNCTION_EXIT\000" |
| 6073 | /* 28877 */ "G_BRJT\000" |
| 6074 | /* 28884 */ "G_EXTRACT_VECTOR_ELT\000" |
| 6075 | /* 28905 */ "G_INSERT_VECTOR_ELT\000" |
| 6076 | /* 28925 */ "G_FCONSTANT\000" |
| 6077 | /* 28937 */ "G_CONSTANT\000" |
| 6078 | /* 28948 */ "G_INTRINSIC_CONVERGENT\000" |
| 6079 | /* 28971 */ "STATEPOINT\000" |
| 6080 | /* 28982 */ "PATCHPOINT\000" |
| 6081 | /* 28993 */ "G_PTRTOINT\000" |
| 6082 | /* 29004 */ "G_FRINT\000" |
| 6083 | /* 29012 */ "G_INTRINSIC_LLRINT\000" |
| 6084 | /* 29031 */ "G_INTRINSIC_LRINT\000" |
| 6085 | /* 29049 */ "G_FNEARBYINT\000" |
| 6086 | /* 29062 */ "RELAXED_DOT\000" |
| 6087 | /* 29074 */ "ANDNOT\000" |
| 6088 | /* 29081 */ "G_VASTART\000" |
| 6089 | /* 29091 */ "LIFETIME_START\000" |
| 6090 | /* 29106 */ "G_INVOKE_REGION_START\000" |
| 6091 | /* 29128 */ "G_INSERT\000" |
| 6092 | /* 29137 */ "G_FSQRT\000" |
| 6093 | /* 29145 */ "G_STRICT_FSQRT\000" |
| 6094 | /* 29160 */ "G_BITCAST\000" |
| 6095 | /* 29170 */ "G_ADDRSPACE_CAST\000" |
| 6096 | /* 29187 */ "DBG_VALUE_LIST\000" |
| 6097 | /* 29202 */ "G_FPEXT\000" |
| 6098 | /* 29210 */ "G_SEXT\000" |
| 6099 | /* 29217 */ "G_ASSERT_SEXT\000" |
| 6100 | /* 29231 */ "G_ANYEXT\000" |
| 6101 | /* 29240 */ "G_ZEXT\000" |
| 6102 | /* 29247 */ "G_ASSERT_ZEXT\000" |
| 6103 | /* 29261 */ "SELECT_T\000" |
| 6104 | /* 29270 */ "G_ABDU\000" |
| 6105 | /* 29277 */ "I64_MUL_WIDE_U\000" |
| 6106 | /* 29292 */ "G_TRUNC_SSAT_U\000" |
| 6107 | /* 29307 */ "G_TRUNC_USAT_U\000" |
| 6108 | /* 29322 */ "G_FDIV\000" |
| 6109 | /* 29329 */ "G_STRICT_FDIV\000" |
| 6110 | /* 29343 */ "G_SDIV\000" |
| 6111 | /* 29350 */ "G_UDIV\000" |
| 6112 | /* 29357 */ "G_GET_FPENV\000" |
| 6113 | /* 29369 */ "G_RESET_FPENV\000" |
| 6114 | /* 29383 */ "G_SET_FPENV\000" |
| 6115 | /* 29395 */ "G_FPOW\000" |
| 6116 | /* 29402 */ "RETHROW\000" |
| 6117 | /* 29410 */ "G_VECREDUCE_FMAX\000" |
| 6118 | /* 29427 */ "G_ATOMICRMW_FMAX\000" |
| 6119 | /* 29444 */ "G_VECREDUCE_SMAX\000" |
| 6120 | /* 29461 */ "G_SMAX\000" |
| 6121 | /* 29468 */ "G_VECREDUCE_UMAX\000" |
| 6122 | /* 29485 */ "G_UMAX\000" |
| 6123 | /* 29492 */ "G_ATOMICRMW_UMAX\000" |
| 6124 | /* 29509 */ "G_ATOMICRMW_MAX\000" |
| 6125 | /* 29525 */ "G_FRAME_INDEX\000" |
| 6126 | /* 29539 */ "G_SBFX\000" |
| 6127 | /* 29546 */ "G_UBFX\000" |
| 6128 | /* 29553 */ "G_SMULFIX\000" |
| 6129 | /* 29563 */ "G_UMULFIX\000" |
| 6130 | /* 29573 */ "G_SDIVFIX\000" |
| 6131 | /* 29583 */ "G_UDIVFIX\000" |
| 6132 | /* 29593 */ "CATCH_LEGACY\000" |
| 6133 | /* 29606 */ "CATCH_ALL_LEGACY\000" |
| 6134 | /* 29623 */ "G_MEMCPY\000" |
| 6135 | /* 29632 */ "TABLE_COPY\000" |
| 6136 | /* 29643 */ "CONVERGENCECTRL_ENTRY\000" |
| 6137 | /* 29665 */ "END_TRY\000" |
| 6138 | /* 29673 */ "G_CTLZ\000" |
| 6139 | /* 29680 */ "G_CTTZ\000" |
| 6140 | /* 29687 */ "ARGUMENT_funcref\000" |
| 6141 | /* 29704 */ "ARGUMENT_externref\000" |
| 6142 | /* 29723 */ "ARGUMENT_exnref\000" |
| 6143 | /* 29739 */ "EXTRACT_LANE_I8x16_s\000" |
| 6144 | /* 29760 */ "EXTRACT_LANE_I16x8_s\000" |
| 6145 | /* 29781 */ "EXTRACT_LANE_I8x16_u\000" |
| 6146 | /* 29802 */ "EXTRACT_LANE_I16x8_u\000" |
| 6147 | }; |
| 6148 | #ifdef __GNUC__ |
| 6149 | #pragma GCC diagnostic pop |
| 6150 | #endif |
| 6151 | |
| 6152 | extern const unsigned WebAssemblyInstrNameIndices[] = { |
| 6153 | 12876U, 13319U, 14263U, 13786U, 12959U, 12940U, 12968U, 13147U, |
| 6154 | 12654U, 12669U, 11780U, 11767U, 12696U, 14817U, 11624U, 29187U, |
| 6155 | 12610U, 12872U, 12949U, 11293U, 29638U, 12916U, 11447U, 29091U, |
| 6156 | 11092U, 11216U, 11266U, 13954U, 13125U, 28982U, 11199U, 14198U, |
| 6157 | 12789U, 28971U, 11521U, 14171U, 14158U, 14324U, 28830U, 28853U, |
| 6158 | 13048U, 13104U, 13077U, 12985U, 11606U, 14289U, 13908U, 11510U, |
| 6159 | 29643U, 14442U, 14119U, 11672U, 29217U, 29247U, 13616U, 10989U, |
| 6160 | 10679U, 13258U, 29343U, 29350U, 13285U, 13292U, 13299U, 13309U, |
| 6161 | 11070U, 14651U, 14614U, 14702U, 29270U, 14486U, 13037U, 14474U, |
| 6162 | 13026U, 11778U, 12874U, 29525U, 11634U, 11649U, 13152U, 28750U, |
| 6163 | 14709U, 29128U, 14726U, 14537U, 10758U, 14800U, 28993U, 14678U, |
| 6164 | 29160U, 11723U, 14300U, 11173U, 10732U, 11155U, 29031U, 29012U, |
| 6165 | 13594U, 14349U, 14368U, 10890U, 10834U, 10864U, 10803U, 10875U, |
| 6166 | 10815U, 10845U, 11580U, 11534U, 11564U, 14847U, 12710U, 12727U, |
| 6167 | 11021U, 10685U, 11076U, 11037U, 14656U, 14620U, 29509U, 13742U, |
| 6168 | 29492U, 13725U, 10956U, 10662U, 29427U, 13660U, 13414U, 13361U, |
| 6169 | 13535U, 13473U, 14016U, 13994U, 11114U, 28703U, 11258U, 12812U, |
| 6170 | 11105U, 28779U, 29106U, 10701U, 14905U, 28948U, 14932U, 29231U, |
| 6171 | 10750U, 28233U, 29292U, 29307U, 28937U, 28925U, 29081U, 12781U, |
| 6172 | 29210U, 12683U, 29240U, 13012U, 14435U, 14421U, 13005U, 14428U, |
| 6173 | 14671U, 13168U, 14085U, 14064U, 14092U, 14099U, 28770U, 13900U, |
| 6174 | 11314U, 13884U, 11237U, 13892U, 11306U, 13876U, 11229U, 13938U, |
| 6175 | 13930U, 12840U, 12832U, 28621U, 28611U, 28601U, 28591U, 28641U, |
| 6176 | 28631U, 29553U, 29563U, 28651U, 28664U, 29573U, 29583U, 28677U, |
| 6177 | 28690U, 10914U, 10641U, 13192U, 10622U, 10796U, 29322U, 13264U, |
| 6178 | 11759U, 29395U, 12898U, 14242U, 3559U, 9U, 12774U, 3542U, |
| 6179 | 0U, 14217U, 14249U, 12647U, 29202U, 10722U, 12880U, 12889U, |
| 6180 | 14046U, 14055U, 28724U, 28737U, 14689U, 13631U, 14834U, 11732U, |
| 6181 | 13559U, 13569U, 11363U, 11378U, 13350U, 13403U, 13459U, 13521U, |
| 6182 | 29357U, 29383U, 29369U, 11322U, 11350U, 11335U, 12744U, 12759U, |
| 6183 | 10995U, 12930U, 13694U, 29461U, 13718U, 29485U, 14696U, 11146U, |
| 6184 | 11136U, 14258U, 28877U, 11393U, 14518U, 14498U, 28905U, 28884U, |
| 6185 | 14552U, 14583U, 14569U, 14887U, 29680U, 13821U, 29673U, 13802U, |
| 6186 | 14741U, 14140U, 14038U, 11593U, 13234U, 12823U, 13018U, 14768U, |
| 6187 | 13766U, 14775U, 13587U, 14760U, 13758U, 13579U, 3550U, 12864U, |
| 6188 | 12856U, 12848U, 29137U, 14465U, 29004U, 29049U, 29170U, 14276U, |
| 6189 | 11420U, 10779U, 11701U, 11549U, 10942U, 10648U, 13220U, 29329U, |
| 6190 | 13271U, 10628U, 29145U, 14226U, 14071U, 14785U, 14388U, 14404U, |
| 6191 | 29623U, 11494U, 11713U, 28844U, 13946U, 11478U, 13987U, 13963U, |
| 6192 | 13975U, 10921U, 13199U, 10897U, 13175U, 29410U, 13643U, 13382U, |
| 6193 | 13329U, 13497U, 13435U, 10973U, 13242U, 11054U, 14636U, 14598U, |
| 6194 | 29444U, 13677U, 29468U, 13701U, 29539U, 29546U, 14748U, 28150U, |
| 6195 | 14974U, 28180U, 28810U, 28280U, 28819U, 28291U, 11278U, 26918U, |
| 6196 | 14970U, 28176U, 9773U, 25895U, 2641U, 17862U, 8049U, 23933U, |
| 6197 | 6956U, 22662U, 3761U, 19135U, 10034U, 26198U, 8371U, 24303U, |
| 6198 | 4071U, 19491U, 9155U, 25179U, 9644U, 25744U, 2510U, 17703U, |
| 6199 | 7896U, 23756U, 6826U, 22504U, 3608U, 18958U, 9938U, 26086U, |
| 6200 | 2960U, 18229U, 8256U, 24170U, 7275U, 23029U, 3956U, 19358U, |
| 6201 | 9069U, 25079U, 10150U, 26330U, 9227U, 25263U, 10378U, 26590U, |
| 6202 | 9409U, 25473U, 13859U, 28074U, 14183U, 28122U, 9967U, 26119U, |
| 6203 | 8304U, 24224U, 4004U, 19412U, 9098U, 25112U, 11050U, 29074U, |
| 6204 | 28318U, 2968U, 18239U, 7283U, 23039U, 26891U, 11693U, 27032U, |
| 6205 | 29723U, 28462U, 29704U, 28441U, 3501U, 18864U, 7814U, 23662U, |
| 6206 | 29687U, 28422U, 3529U, 18896U, 7842U, 23694U, 9605U, 25699U, |
| 6207 | 7799U, 23645U, 7827U, 23677U, 3486U, 18847U, 3514U, 18879U, |
| 6208 | 9012U, 25014U, 9027U, 25031U, 11245U, 26903U, 743U, 15774U, |
| 6209 | 5059U, 20575U, 1865U, 16990U, 6181U, 21791U, 1841U, 16964U, |
| 6210 | 6157U, 21765U, 767U, 15800U, 5083U, 20601U, 1889U, 17016U, |
| 6211 | 6205U, 21817U, 201U, 15188U, 4517U, 19989U, 1116U, 16181U, |
| 6212 | 5432U, 20982U, 221U, 15210U, 4537U, 20011U, 1163U, 16232U, |
| 6213 | 5479U, 21033U, 297U, 15292U, 4613U, 20093U, 1266U, 16343U, |
| 6214 | 5582U, 21144U, 394U, 15397U, 4710U, 20198U, 1394U, 16481U, |
| 6215 | 5710U, 21282U, 637U, 15658U, 4953U, 20459U, 1718U, 16829U, |
| 6216 | 6034U, 21630U, 125U, 15106U, 4441U, 19907U, 1040U, 16099U, |
| 6217 | 5356U, 20900U, 482U, 15491U, 4798U, 20292U, 1510U, 16605U, |
| 6218 | 5826U, 21406U, 561U, 15576U, 4877U, 20377U, 1616U, 16719U, |
| 6219 | 5932U, 21520U, 1136U, 16203U, 5452U, 21004U, 1239U, 16314U, |
| 6220 | 5555U, 21115U, 1363U, 16448U, 5679U, 21249U, 1692U, 16801U, |
| 6221 | 6008U, 21602U, 1013U, 16070U, 5329U, 20871U, 1482U, 16575U, |
| 6222 | 5798U, 21376U, 1589U, 16690U, 5905U, 21491U, 248U, 15239U, |
| 6223 | 4564U, 20040U, 1190U, 16261U, 5506U, 21062U, 324U, 15321U, |
| 6224 | 4640U, 20122U, 1293U, 16372U, 5609U, 21173U, 425U, 15430U, |
| 6225 | 4741U, 20231U, 1425U, 16514U, 5741U, 21315U, 663U, 15686U, |
| 6226 | 4979U, 20487U, 1744U, 16857U, 6060U, 21658U, 152U, 15135U, |
| 6227 | 4468U, 19936U, 1067U, 16128U, 5383U, 20929U, 510U, 15521U, |
| 6228 | 4826U, 20322U, 1538U, 16635U, 5854U, 21436U, 588U, 15605U, |
| 6229 | 4904U, 20406U, 1643U, 16748U, 5959U, 21549U, 274U, 15267U, |
| 6230 | 4590U, 20068U, 1216U, 16289U, 5532U, 21090U, 350U, 15349U, |
| 6231 | 4666U, 20150U, 1319U, 16400U, 5635U, 21201U, 455U, 15462U, |
| 6232 | 4771U, 20263U, 1455U, 16546U, 5771U, 21347U, 688U, 15713U, |
| 6233 | 5004U, 20514U, 1769U, 16884U, 6085U, 21685U, 178U, 15163U, |
| 6234 | 4494U, 19964U, 1093U, 16156U, 5409U, 20957U, 537U, 15550U, |
| 6235 | 4853U, 20351U, 1565U, 16664U, 5881U, 21465U, 614U, 15633U, |
| 6236 | 4930U, 20434U, 1669U, 16776U, 5985U, 21577U, 80U, 15057U, |
| 6237 | 4396U, 19858U, 968U, 16021U, 5284U, 20822U, 945U, 15996U, |
| 6238 | 5261U, 20797U, 103U, 15082U, 4419U, 19883U, 991U, 16046U, |
| 6239 | 5307U, 20847U, 373U, 15374U, 4689U, 20175U, 1342U, 16425U, |
| 6240 | 5658U, 21226U, 10337U, 26543U, 9368U, 25426U, 9991U, 26147U, |
| 6241 | 8328U, 24252U, 4028U, 19440U, 9122U, 25140U, 28760U, 28248U, |
| 6242 | 12910U, 28007U, 14260U, 12641U, 27987U, 28139U, 2990U, 18265U, |
| 6243 | 7305U, 23065U, 14877U, 28164U, 13063U, 28796U, 28264U, 12587U, |
| 6244 | 27939U, 28019U, 12806U, 13137U, 29606U, 28380U, 12596U, 27950U, |
| 6245 | 28026U, 29593U, 28365U, 12573U, 27923U, 27995U, 9720U, 25832U, |
| 6246 | 2577U, 17784U, 7972U, 23844U, 6892U, 22584U, 3684U, 19046U, |
| 6247 | 3462U, 18817U, 7775U, 23615U, 2885U, 18140U, 7200U, 22940U, |
| 6248 | 3324U, 18655U, 7654U, 23472U, 7855U, 23709U, 3567U, 18911U, |
| 6249 | 9911U, 26055U, 8229U, 24139U, 3929U, 19327U, 9042U, 25048U, |
| 6250 | 2594U, 17805U, 6909U, 22605U, 12561U, 27909U, 12328U, 27648U, |
| 6251 | 2943U, 18208U, 7258U, 23008U, 12058U, 27350U, 3453U, 18806U, |
| 6252 | 7766U, 23604U, 9595U, 25687U, 3478U, 18837U, 7791U, 23635U, |
| 6253 | 14148U, 28110U, 11402U, 26950U, 11615U, 27021U, 9838U, 25972U, |
| 6254 | 2927U, 18188U, 8114U, 24010U, 7242U, 22988U, 3826U, 19212U, |
| 6255 | 3214U, 18529U, 7544U, 23346U, 3443U, 18794U, 7756U, 23592U, |
| 6256 | 29070U, 28312U, 12413U, 27743U, 12153U, 27455U, 2615U, 17830U, |
| 6257 | 6930U, 22630U, 11867U, 27137U, 3035U, 18320U, 7363U, 23135U, |
| 6258 | 9511U, 25591U, 11588U, 27014U, 11101U, 12906U, 28003U, 13773U, |
| 6259 | 28038U, 12634U, 27978U, 14110U, 28099U, 26897U, 29665U, 28412U, |
| 6260 | 11433U, 26970U, 3470U, 18827U, 7783U, 23625U, 9752U, 25870U, |
| 6261 | 2624U, 17841U, 8028U, 23908U, 6939U, 22641U, 3740U, 19110U, |
| 6262 | 10025U, 26187U, 3044U, 18331U, 8362U, 24292U, 7372U, 23146U, |
| 6263 | 4062U, 19480U, 9146U, 25168U, 10066U, 26236U, 8403U, 24341U, |
| 6264 | 4103U, 19529U, 10305U, 26507U, 8551U, 24511U, 4205U, 19645U, |
| 6265 | 10208U, 26396U, 8469U, 24417U, 4157U, 19591U, 10416U, 26634U, |
| 6266 | 8617U, 24587U, 4237U, 19681U, 9691U, 25799U, 7943U, 23811U, |
| 6267 | 3655U, 19013U, 29760U, 28503U, 29802U, 28549U, 8285U, 24203U, |
| 6268 | 3985U, 19391U, 29739U, 28480U, 29781U, 28526U, 3178U, 18489U, |
| 6269 | 7508U, 23306U, 3407U, 18754U, 7720U, 23552U, 6869U, 22557U, |
| 6270 | 3264U, 18587U, 3196U, 18509U, 7526U, 23326U, 3425U, 18774U, |
| 6271 | 7738U, 23572U, 2553U, 17756U, 7594U, 23404U, 13840U, 28053U, |
| 6272 | 9761U, 25881U, 2631U, 17850U, 8037U, 23919U, 6946U, 22650U, |
| 6273 | 3749U, 19121U, 2416U, 17597U, 6732U, 22398U, 2454U, 17639U, |
| 6274 | 6770U, 22440U, 2435U, 17618U, 6751U, 22419U, 2473U, 17660U, |
| 6275 | 6789U, 22461U, 9654U, 25756U, 2532U, 17729U, 7906U, 23768U, |
| 6276 | 6848U, 22530U, 3618U, 18970U, 10044U, 26210U, 3122U, 18421U, |
| 6277 | 8381U, 24315U, 7452U, 23238U, 4081U, 19503U, 9165U, 25191U, |
| 6278 | 10283U, 26481U, 3351U, 18686U, 8529U, 24485U, 7664U, 23484U, |
| 6279 | 9334U, 25386U, 12456U, 27792U, 12205U, 27513U, 2772U, 18009U, |
| 6280 | 7087U, 22809U, 11913U, 27189U, 3235U, 18554U, 7565U, 23371U, |
| 6281 | 9533U, 25617U, 12508U, 27850U, 12266U, 27580U, 2821U, 18064U, |
| 6282 | 7136U, 22864U, 11968U, 27250U, 3284U, 18609U, 7614U, 23426U, |
| 6283 | 9564U, 25652U, 9795U, 25921U, 2850U, 18097U, 8071U, 23959U, |
| 6284 | 7165U, 22897U, 3783U, 19161U, 10186U, 26370U, 3160U, 18467U, |
| 6285 | 8447U, 24391U, 7490U, 23284U, 4135U, 19565U, 9243U, 25281U, |
| 6286 | 10394U, 26608U, 3389U, 18732U, 8595U, 24561U, 7702U, 23530U, |
| 6287 | 9425U, 25491U, 3068U, 18361U, 3087U, 18382U, 2801U, 18042U, |
| 6288 | 2649U, 17872U, 6964U, 22672U, 2681U, 17908U, 6996U, 22708U, |
| 6289 | 2895U, 18152U, 7210U, 22952U, 2721U, 17952U, 7036U, 22752U, |
| 6290 | 7350U, 23120U, 9485U, 25561U, 7415U, 23197U, 7396U, 23176U, |
| 6291 | 7434U, 23218U, 3105U, 18402U, 3334U, 18667U, 26935U, 28195U, |
| 6292 | 29277U, 28338U, 7116U, 22842U, 9474U, 25548U, 2665U, 17890U, |
| 6293 | 6980U, 22690U, 2701U, 17930U, 7016U, 22730U, 2911U, 18170U, |
| 6294 | 7226U, 22970U, 2741U, 17974U, 7056U, 22774U, 12638U, 27982U, |
| 6295 | 10266U, 26462U, 8512U, 24466U, 4188U, 19626U, 9304U, 25352U, |
| 6296 | 9663U, 25767U, 2539U, 17738U, 7915U, 23779U, 6855U, 22539U, |
| 6297 | 3627U, 18981U, 10055U, 26223U, 3131U, 18432U, 8392U, 24328U, |
| 6298 | 7461U, 23249U, 4092U, 19516U, 9176U, 25204U, 10294U, 26494U, |
| 6299 | 3360U, 18697U, 8540U, 24498U, 7673U, 23495U, 9345U, 25399U, |
| 6300 | 2273U, 17438U, 6589U, 22239U, 710U, 15737U, 5026U, 20538U, |
| 6301 | 1808U, 16927U, 6124U, 21728U, 750U, 15781U, 5066U, 20582U, |
| 6302 | 1872U, 16997U, 6188U, 21798U, 2239U, 17400U, 6555U, 22201U, |
| 6303 | 1791U, 16908U, 6107U, 21709U, 1848U, 16971U, 6164U, 21772U, |
| 6304 | 2256U, 17419U, 6572U, 22220U, 2290U, 17457U, 6606U, 22258U, |
| 6305 | 727U, 15756U, 5043U, 20557U, 1825U, 16946U, 6141U, 21747U, |
| 6306 | 774U, 15807U, 5090U, 20608U, 1896U, 17023U, 6212U, 21824U, |
| 6307 | 2144U, 17297U, 6460U, 22098U, 1992U, 17129U, 6308U, 21930U, |
| 6308 | 870U, 15913U, 5186U, 20714U, 2168U, 17323U, 6484U, 22124U, |
| 6309 | 2016U, 17155U, 6332U, 21956U, 894U, 15939U, 5210U, 20740U, |
| 6310 | 18U, 14987U, 4334U, 19788U, 53U, 15026U, 4369U, 19827U, |
| 6311 | 918U, 15965U, 5234U, 20766U, 208U, 15195U, 4524U, 19996U, |
| 6312 | 1123U, 16188U, 5439U, 20989U, 2040U, 17181U, 6356U, 21982U, |
| 6313 | 815U, 15852U, 5131U, 20653U, 1937U, 17068U, 6253U, 21869U, |
| 6314 | 2107U, 17256U, 6423U, 22057U, 2078U, 17223U, 6394U, 22024U, |
| 6315 | 832U, 15871U, 5148U, 20672U, 1954U, 17087U, 6270U, 21888U, |
| 6316 | 12474U, 27812U, 12226U, 27536U, 2787U, 18026U, 7102U, 22826U, |
| 6317 | 11932U, 27210U, 3250U, 18571U, 7580U, 23388U, 9549U, 25635U, |
| 6318 | 12526U, 27870U, 12287U, 27603U, 2836U, 18081U, 7151U, 22881U, |
| 6319 | 11987U, 27271U, 3299U, 18626U, 7629U, 23443U, 9580U, 25670U, |
| 6320 | 12343U, 27665U, 12071U, 27365U, 2518U, 17713U, 6834U, 22514U, |
| 6321 | 11793U, 27055U, 2976U, 18249U, 7291U, 23049U, 9496U, 25574U, |
| 6322 | 14114U, 28103U, 9804U, 25932U, 2857U, 18106U, 8080U, 23970U, |
| 6323 | 7172U, 22906U, 3792U, 19172U, 10197U, 26383U, 3169U, 18478U, |
| 6324 | 8458U, 24404U, 7499U, 23295U, 4146U, 19578U, 9254U, 25294U, |
| 6325 | 10405U, 26621U, 3398U, 18743U, 8606U, 24574U, 7711U, 23541U, |
| 6326 | 9436U, 25504U, 9643U, 25743U, 7895U, 23755U, 3607U, 18957U, |
| 6327 | 9849U, 25985U, 2935U, 18198U, 8138U, 24036U, 7250U, 22998U, |
| 6328 | 3850U, 19238U, 10242U, 26434U, 8488U, 24438U, 9280U, 25324U, |
| 6329 | 10450U, 26672U, 8636U, 24608U, 9462U, 25534U, 2389U, 17566U, |
| 6330 | 6705U, 22367U, 2364U, 17539U, 6680U, 22340U, 790U, 15825U, |
| 6331 | 5106U, 20626U, 1912U, 17041U, 6228U, 21842U, 2400U, 17579U, |
| 6332 | 6716U, 22380U, 2223U, 17382U, 6539U, 22183U, 2317U, 17488U, |
| 6333 | 6633U, 22289U, 2306U, 17475U, 6622U, 22276U, 9742U, 25858U, |
| 6334 | 2607U, 17820U, 8007U, 23883U, 6922U, 22620U, 3719U, 19085U, |
| 6335 | 10086U, 26258U, 8423U, 24363U, 9187U, 25217U, 10325U, 26529U, |
| 6336 | 8571U, 24533U, 9356U, 25412U, 9731U, 25845U, 2586U, 17795U, |
| 6337 | 7983U, 23857U, 6901U, 22595U, 3695U, 19059U, 10015U, 26175U, |
| 6338 | 3027U, 18310U, 8352U, 24280U, 7342U, 23110U, 4052U, 19468U, |
| 6339 | 10227U, 26417U, 9265U, 25307U, 10435U, 26655U, 9447U, 25517U, |
| 6340 | 9824U, 25956U, 2873U, 18126U, 8100U, 23994U, 7188U, 22926U, |
| 6341 | 3812U, 19196U, 9710U, 25820U, 2569U, 17774U, 7962U, 23832U, |
| 6342 | 6884U, 22574U, 3674U, 19034U, 9981U, 26135U, 8318U, 24240U, |
| 6343 | 4018U, 19428U, 9112U, 25128U, 9682U, 25788U, 2546U, 17747U, |
| 6344 | 7934U, 23800U, 6862U, 22548U, 3646U, 19002U, 9958U, 26108U, |
| 6345 | 3003U, 18280U, 8276U, 24192U, 7318U, 23080U, 3976U, 19380U, |
| 6346 | 9089U, 25101U, 9642U, 25742U, 7894U, 23754U, 3606U, 18956U, |
| 6347 | 14106U, 28093U, 29077U, 28321U, 14462U, 3052U, 18341U, 7380U, |
| 6348 | 23156U, 28145U, 9848U, 25984U, 8148U, 24048U, 3860U, 19250U, |
| 6349 | 9741U, 25857U, 8017U, 23895U, 3729U, 19097U, 3313U, 18642U, |
| 6350 | 7643U, 23459U, 9321U, 25371U, 10166U, 26348U, 12005U, 27291U, |
| 6351 | 10713U, 26862U, 12394U, 27722U, 12131U, 27431U, 11847U, 27115U, |
| 6352 | 12378U, 27704U, 12112U, 27410U, 11830U, 27096U, 12022U, 27310U, |
| 6353 | 29062U, 11005U, 26873U, 28572U, 28212U, 28304U, 10110U, 26286U, |
| 6354 | 11462U, 26996U, 3140U, 18443U, 7470U, 23260U, 3369U, 18708U, |
| 6355 | 7682U, 23506U, 9672U, 25778U, 7924U, 23790U, 3636U, 18992U, |
| 6356 | 9948U, 26098U, 8266U, 24182U, 3966U, 19370U, 9079U, 25091U, |
| 6357 | 29402U, 28355U, 13852U, 28065U, 13068U, 28792U, 28260U, 12583U, |
| 6358 | 27935U, 28015U, 3018U, 18299U, 7333U, 23099U, 3059U, 18350U, |
| 6359 | 7387U, 23165U, 12425U, 27757U, 12168U, 27472U, 2761U, 17996U, |
| 6360 | 7076U, 22796U, 11880U, 27152U, 3224U, 18541U, 7554U, 23358U, |
| 6361 | 29261U, 28327U, 9521U, 25603U, 10005U, 26163U, 3010U, 18289U, |
| 6362 | 8342U, 24268U, 7325U, 23089U, 4042U, 19456U, 9136U, 25156U, |
| 6363 | 10098U, 26272U, 3150U, 18455U, 8435U, 24377U, 7480U, 23272U, |
| 6364 | 4123U, 19551U, 9199U, 25231U, 10350U, 26558U, 3379U, 18720U, |
| 6365 | 8583U, 24547U, 7692U, 23518U, 4225U, 19667U, 9381U, 25441U, |
| 6366 | 11454U, 26986U, 8124U, 24022U, 3836U, 19224U, 7993U, 23869U, |
| 6367 | 3705U, 19071U, 9783U, 25907U, 8059U, 23945U, 3771U, 19147U, |
| 6368 | 10254U, 26448U, 8500U, 24452U, 4176U, 19612U, 9292U, 25338U, |
| 6369 | 9813U, 25943U, 2864U, 18115U, 8089U, 23981U, 7179U, 22915U, |
| 6370 | 3801U, 19183U, 87U, 15064U, 4403U, 19865U, 975U, 16028U, |
| 6371 | 5291U, 20829U, 952U, 16003U, 5268U, 20804U, 110U, 15089U, |
| 6372 | 4426U, 19890U, 998U, 16053U, 5314U, 20854U, 35U, 15006U, |
| 6373 | 4351U, 19807U, 66U, 15041U, 4382U, 19842U, 931U, 15980U, |
| 6374 | 5247U, 20781U, 380U, 15381U, 4696U, 20182U, 1349U, 16432U, |
| 6375 | 5665U, 21233U, 2123U, 17274U, 6439U, 22075U, 1971U, 17106U, |
| 6376 | 6287U, 21907U, 849U, 15890U, 5165U, 20691U, 2057U, 17200U, |
| 6377 | 6373U, 22001U, 2092U, 17239U, 6408U, 22040U, 9620U, 25716U, |
| 6378 | 2492U, 17681U, 7872U, 23728U, 6808U, 22482U, 3584U, 18930U, |
| 6379 | 9928U, 26074U, 2952U, 18219U, 8246U, 24158U, 7267U, 23019U, |
| 6380 | 3946U, 19346U, 9059U, 25067U, 10134U, 26312U, 9211U, 25245U, |
| 6381 | 10362U, 26572U, 9393U, 25455U, 11470U, 27004U, 29632U, 28399U, |
| 6382 | 12360U, 27684U, 12091U, 27387U, 11811U, 27075U, 12439U, 27773U, |
| 6383 | 12185U, 27491U, 11895U, 27169U, 12543U, 27889U, 12307U, 27625U, |
| 6384 | 12039U, 27329U, 12491U, 27831U, 12246U, 27558U, 11950U, 27230U, |
| 6385 | 11748U, 27042U, 12349U, 27671U, 12077U, 27371U, 2524U, 17719U, |
| 6386 | 6840U, 22520U, 11799U, 27061U, 2982U, 18255U, 7297U, 23055U, |
| 6387 | 9502U, 25580U, 29404U, 12624U, 27966U, 28357U, 9630U, 25728U, |
| 6388 | 2500U, 17691U, 7882U, 23740U, 6816U, 22492U, 3594U, 18942U, |
| 6389 | 29661U, 28416U, 11437U, 26974U, 11408U, 26956U, 14610U, 3051U, |
| 6390 | 18340U, 7379U, 23155U, 28144U, 2333U, 17506U, 2192U, 17349U, |
| 6391 | 6649U, 22307U, 6508U, 22150U, 3871U, 19263U, 3891U, 19285U, |
| 6392 | 9859U, 25997U, 8159U, 24061U, 10462U, 26686U, 8806U, 24788U, |
| 6393 | 10559U, 26793U, 8926U, 24920U, 10486U, 26712U, 8830U, 24814U, |
| 6394 | 4256U, 19702U, 10583U, 26819U, 8950U, 24946U, 4295U, 19745U, |
| 6395 | 10506U, 26734U, 8873U, 24861U, 4276U, 19724U, 10603U, 26841U, |
| 6396 | 8993U, 24993U, 4315U, 19767U, 10525U, 26755U, 8892U, 24882U, |
| 6397 | 10542U, 26774U, 8909U, 24901U, 8648U, 24622U, 8722U, 24700U, |
| 6398 | 8684U, 24660U, 8763U, 24743U, 8211U, 24119U, 3911U, 19307U, |
| 6399 | 9877U, 26017U, 8177U, 24081U, 8850U, 24836U, 8970U, 24968U, |
| 6400 | 9894U, 26036U, 8194U, 24100U, |
| 6401 | }; |
| 6402 | |
| 6403 | extern const int16_t WebAssemblyRegClassByHwModeTables[2][1] = { |
| 6404 | { // DefaultMode |
| 6405 | WebAssembly::I32RegClassID, // wasm_ptr_rc |
| 6406 | }, |
| 6407 | { // WASM64 |
| 6408 | WebAssembly::I64RegClassID, // wasm_ptr_rc |
| 6409 | }, |
| 6410 | }; |
| 6411 | |
| 6412 | static inline void InitWebAssemblyMCInstrInfo(MCInstrInfo *II) { |
| 6413 | II->InitMCInstrInfo(WebAssemblyDescs.Insts, WebAssemblyInstrNameIndices, WebAssemblyInstrNameData, nullptr, nullptr, 1980, &WebAssemblyRegClassByHwModeTables[0][0], 1); |
| 6414 | } |
| 6415 | |
| 6416 | |
| 6417 | } // namespace llvm |
| 6418 | |
| 6419 | #endif // GET_INSTRINFO_MC_DESC |
| 6420 | |
| 6421 | #ifdef GET_INSTRINFO_HEADER |
| 6422 | #undef GET_INSTRINFO_HEADER |
| 6423 | |
| 6424 | namespace llvm { |
| 6425 | |
| 6426 | struct WebAssemblyGenInstrInfo : public TargetInstrInfo { |
| 6427 | explicit WebAssemblyGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u); |
| 6428 | ~WebAssemblyGenInstrInfo() override = default; |
| 6429 | }; |
| 6430 | extern const int16_t WebAssemblyRegClassByHwModeTables[2][1]; |
| 6431 | |
| 6432 | } // namespace llvm |
| 6433 | |
| 6434 | namespace llvm::WebAssembly { |
| 6435 | |
| 6436 | |
| 6437 | } // namespace llvm::WebAssembly |
| 6438 | |
| 6439 | #endif // GET_INSTRINFO_HEADER |
| 6440 | |
| 6441 | #ifdef GET_INSTRINFO_HELPER_DECLS |
| 6442 | #undef GET_INSTRINFO_HELPER_DECLS |
| 6443 | |
| 6444 | |
| 6445 | #endif // GET_INSTRINFO_HELPER_DECLS |
| 6446 | |
| 6447 | #ifdef GET_INSTRINFO_HELPERS |
| 6448 | #undef GET_INSTRINFO_HELPERS |
| 6449 | |
| 6450 | |
| 6451 | #endif // GET_INSTRINFO_HELPERS |
| 6452 | |
| 6453 | #ifdef GET_INSTRINFO_CTOR_DTOR |
| 6454 | #undef GET_INSTRINFO_CTOR_DTOR |
| 6455 | |
| 6456 | namespace llvm { |
| 6457 | |
| 6458 | extern const WebAssemblyInstrTable WebAssemblyDescs; |
| 6459 | extern const unsigned WebAssemblyInstrNameIndices[]; |
| 6460 | extern const char WebAssemblyInstrNameData[]; |
| 6461 | WebAssemblyGenInstrInfo::WebAssemblyGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode) |
| 6462 | : TargetInstrInfo(TRI, CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode, WebAssemblyRegClassByHwModeTables[STI.getHwMode(MCSubtargetInfo::HwMode_RegInfo)]) { |
| 6463 | InitMCInstrInfo(WebAssemblyDescs.Insts, WebAssemblyInstrNameIndices, WebAssemblyInstrNameData, nullptr, nullptr, 1980, &WebAssemblyRegClassByHwModeTables[0][0], 1); |
| 6464 | } |
| 6465 | |
| 6466 | } // namespace llvm |
| 6467 | |
| 6468 | #endif // GET_INSTRINFO_CTOR_DTOR |
| 6469 | |
| 6470 | #ifdef GET_INSTRINFO_OPERAND_ENUM |
| 6471 | #undef GET_INSTRINFO_OPERAND_ENUM |
| 6472 | |
| 6473 | namespace llvm::WebAssembly { |
| 6474 | |
| 6475 | enum class OpName : uint8_t { |
| 6476 | dst = 0, |
| 6477 | order = 1, |
| 6478 | p2align = 2, |
| 6479 | off = 3, |
| 6480 | addr = 4, |
| 6481 | val = 5, |
| 6482 | exp = 6, |
| 6483 | new_ = 7, |
| 6484 | idx = 8, |
| 6485 | vec = 9, |
| 6486 | count = 10, |
| 6487 | timeout = 11, |
| 6488 | NUM_OPERAND_NAMES = 12, |
| 6489 | }; // enum class OpName |
| 6490 | |
| 6491 | LLVM_READONLY int16_t getNamedOperandIdx(uint32_t Opcode, OpName Name); |
| 6492 | LLVM_READONLY OpName getOperandIdxName(uint32_t Opcode, int16_t Idx); |
| 6493 | |
| 6494 | } // namespace llvm::WebAssembly |
| 6495 | |
| 6496 | #endif // GET_INSTRINFO_OPERAND_ENUM |
| 6497 | |
| 6498 | #ifdef GET_INSTRINFO_NAMED_OPS |
| 6499 | #undef GET_INSTRINFO_NAMED_OPS |
| 6500 | |
| 6501 | namespace llvm::WebAssembly { |
| 6502 | |
| 6503 | LLVM_READONLY static uint8_t getInstructionIndexForOpLookup(uint32_t Opcode) { |
| 6504 | static constexpr uint8_t InstructionIndex[] = { |
| 6505 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6506 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6507 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6508 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6509 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6510 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6511 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6512 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6513 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6514 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6515 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6516 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6517 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6518 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6519 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6520 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6521 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6522 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6523 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6524 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6525 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6526 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6527 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6528 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6529 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6530 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6531 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6532 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, |
| 6533 | 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, |
| 6534 | 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 3, 2, 3, 2, 3, 2, |
| 6535 | 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 4, 2, 4, 2, 4, 2, |
| 6536 | 4, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, |
| 6537 | 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, |
| 6538 | 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 4, 2, 4, 2, 3, 2, |
| 6539 | 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, |
| 6540 | 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 4, 2, |
| 6541 | 4, 2, 4, 2, 4, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, |
| 6542 | 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, |
| 6543 | 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, |
| 6544 | 3, 2, 3, 2, 3, 2, 4, 2, 4, 2, 4, 2, 4, 2, 3, 2, |
| 6545 | 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, |
| 6546 | 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 5, 2, |
| 6547 | 5, 2, 5, 2, 5, 2, 5, 2, 5, 2, 5, 2, 5, 2, 5, 2, |
| 6548 | 5, 2, 5, 2, 5, 2, 5, 2, 5, 2, 0, 0, 0, 0, 0, 0, |
| 6549 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6550 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6551 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6552 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6553 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6554 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6555 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6556 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6557 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6558 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6559 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6560 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6561 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6562 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6563 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6564 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6565 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6566 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6567 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6568 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6569 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6570 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6571 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6572 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6573 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6574 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6575 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6576 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6577 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6578 | 0, 0, 0, 0, 0, 0, 0, 0, 6, 7, 6, 7, 6, 7, 6, 7, |
| 6579 | 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, |
| 6580 | 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, |
| 6581 | 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, |
| 6582 | 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, |
| 6583 | 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, |
| 6584 | 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 8, 9, 8, 9, |
| 6585 | 8, 9, 8, 9, 8, 9, 8, 9, 8, 9, 8, 9, 6, 7, 6, 7, |
| 6586 | 6, 7, 6, 7, 6, 7, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6587 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6588 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6589 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6590 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6591 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6592 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6593 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 2, 10, 2, 11, 2, |
| 6594 | 11, 2, 11, 2, 11, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6595 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6596 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6597 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6598 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6599 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6600 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6601 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6602 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6603 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6604 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6605 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6606 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6607 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6608 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6609 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6610 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6611 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6612 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6613 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 12, 7, 12, 7, 12, 7, |
| 6614 | 12, 7, 12, 7, 12, 7, 12, 7, 12, 7, 12, 7, 12, 7, 12, 7, |
| 6615 | 12, 7, 12, 7, 12, 7, 12, 7, 12, 7, 12, 7, 12, 7, 12, 7, |
| 6616 | 12, 7, 13, 9, 13, 9, 13, 9, 13, 9, 13, 9, 13, 9, 13, 9, |
| 6617 | 13, 9, 14, 7, 14, 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6618 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6619 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6620 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6621 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6622 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6623 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6624 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6625 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6626 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6627 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6628 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 6629 | }; |
| 6630 | return InstructionIndex[Opcode]; |
| 6631 | } |
| 6632 | LLVM_READONLY int16_t getNamedOperandIdx(uint32_t Opcode, OpName Name) { |
| 6633 | assert(Name != OpName::NUM_OPERAND_NAMES); |
| 6634 | static constexpr int8_t OperandMap[][12] = { |
| 6635 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, }, |
| 6636 | {0, 1, 2, 3, 4, -1, -1, -1, -1, -1, -1, -1, }, |
| 6637 | {-1, 0, 1, 2, -1, -1, -1, -1, -1, -1, -1, -1, }, |
| 6638 | {0, 1, 2, 3, 4, 5, -1, -1, -1, -1, -1, -1, }, |
| 6639 | {0, 1, 2, 3, 4, -1, 5, 6, -1, -1, -1, -1, }, |
| 6640 | {-1, 0, 1, 2, 3, 4, -1, -1, -1, -1, -1, -1, }, |
| 6641 | {0, -1, 1, 2, 3, -1, -1, -1, -1, -1, -1, -1, }, |
| 6642 | {-1, -1, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, }, |
| 6643 | {0, -1, 1, 2, 4, -1, -1, -1, 3, 5, -1, -1, }, |
| 6644 | {-1, -1, 0, 1, -1, -1, -1, -1, 2, -1, -1, -1, }, |
| 6645 | {0, 1, 2, 3, 4, -1, -1, -1, -1, -1, 5, -1, }, |
| 6646 | {0, 1, 2, 3, 4, -1, 5, -1, -1, -1, -1, 6, }, |
| 6647 | {-1, -1, 0, 1, 2, 3, -1, -1, -1, -1, -1, -1, }, |
| 6648 | {-1, -1, 0, 1, 3, -1, -1, -1, 2, 4, -1, -1, }, |
| 6649 | {-1, -1, 0, 1, 2, -1, -1, -1, -1, 3, -1, -1, }, |
| 6650 | }; |
| 6651 | unsigned InstrIdx = getInstructionIndexForOpLookup(Opcode); |
| 6652 | return OperandMap[InstrIdx][(unsigned)Name]; |
| 6653 | } |
| 6654 | LLVM_READONLY OpName getOperandIdxName(uint32_t Opcode, int16_t Idx) { |
| 6655 | assert(Idx >= 0 && Idx < 7); |
| 6656 | static constexpr OpName OperandMap[][7] = { |
| 6657 | {OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, }, |
| 6658 | {OpName::dst, OpName::order, OpName::p2align, OpName::off, OpName::addr, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, }, |
| 6659 | {OpName::order, OpName::p2align, OpName::off, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, }, |
| 6660 | {OpName::dst, OpName::order, OpName::p2align, OpName::off, OpName::addr, OpName::val, OpName::NUM_OPERAND_NAMES, }, |
| 6661 | {OpName::dst, OpName::order, OpName::p2align, OpName::off, OpName::addr, OpName::exp, OpName::new_, }, |
| 6662 | {OpName::order, OpName::p2align, OpName::off, OpName::addr, OpName::val, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, }, |
| 6663 | {OpName::dst, OpName::p2align, OpName::off, OpName::addr, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, }, |
| 6664 | {OpName::p2align, OpName::off, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, }, |
| 6665 | {OpName::dst, OpName::p2align, OpName::off, OpName::idx, OpName::addr, OpName::vec, OpName::NUM_OPERAND_NAMES, }, |
| 6666 | {OpName::p2align, OpName::off, OpName::idx, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, }, |
| 6667 | {OpName::dst, OpName::order, OpName::p2align, OpName::off, OpName::addr, OpName::count, OpName::NUM_OPERAND_NAMES, }, |
| 6668 | {OpName::dst, OpName::order, OpName::p2align, OpName::off, OpName::addr, OpName::exp, OpName::timeout, }, |
| 6669 | {OpName::p2align, OpName::off, OpName::addr, OpName::val, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, }, |
| 6670 | {OpName::p2align, OpName::off, OpName::idx, OpName::addr, OpName::vec, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, }, |
| 6671 | {OpName::p2align, OpName::off, OpName::addr, OpName::vec, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, }, |
| 6672 | }; |
| 6673 | unsigned InstrIdx = getInstructionIndexForOpLookup(Opcode); |
| 6674 | return OperandMap[InstrIdx][(unsigned)Idx]; |
| 6675 | } |
| 6676 | |
| 6677 | } // namespace llvm::WebAssembly |
| 6678 | |
| 6679 | #endif // GET_INSTRINFO_NAMED_OPS |
| 6680 | |
| 6681 | #ifdef GET_INSTRINFO_MC_HELPER_DECLS |
| 6682 | #undef GET_INSTRINFO_MC_HELPER_DECLS |
| 6683 | |
| 6684 | namespace llvm { |
| 6685 | |
| 6686 | class MCInst; |
| 6687 | class FeatureBitset; |
| 6688 | |
| 6689 | extern const int16_t WebAssemblyRegClassByHwModeTables[2][1]; |
| 6690 | |
| 6691 | namespace WebAssembly_MC { |
| 6692 | |
| 6693 | void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features); |
| 6694 | |
| 6695 | } // namespace WebAssembly_MC |
| 6696 | |
| 6697 | } // namespace llvm |
| 6698 | |
| 6699 | #endif // GET_INSTRINFO_MC_HELPER_DECLS |
| 6700 | |
| 6701 | #ifdef GET_INSTRINFO_MC_HELPERS |
| 6702 | #undef GET_INSTRINFO_MC_HELPERS |
| 6703 | |
| 6704 | namespace llvm::WebAssembly_MC { |
| 6705 | |
| 6706 | |
| 6707 | } // namespace llvm::WebAssembly_MC |
| 6708 | |
| 6709 | #endif // GET_INSTRINFO_MC_HELPERS |
| 6710 | |
| 6711 | #if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\ |
| 6712 | defined(GET_AVAILABLE_OPCODE_CHECKER) |
| 6713 | #define GET_COMPUTE_FEATURES |
| 6714 | #endif |
| 6715 | #ifdef GET_COMPUTE_FEATURES |
| 6716 | #undef GET_COMPUTE_FEATURES |
| 6717 | |
| 6718 | namespace llvm::WebAssembly_MC { |
| 6719 | |
| 6720 | // Bits for subtarget features that participate in instruction matching. |
| 6721 | enum SubtargetFeatureBits : uint8_t { |
| 6722 | Feature_HasAtomicsBit = 0, |
| 6723 | Feature_HasBulkMemoryBit = 1, |
| 6724 | Feature_HasBulkMemoryOptBit = 2, |
| 6725 | Feature_HasCallIndirectOverlongBit = 3, |
| 6726 | Feature_HasExceptionHandlingBit = 4, |
| 6727 | Feature_HasExtendedConstBit = 5, |
| 6728 | Feature_HasFP16Bit = 6, |
| 6729 | Feature_HasGCBit = 7, |
| 6730 | Feature_HasMultiMemoryBit = 8, |
| 6731 | Feature_HasMultivalueBit = 9, |
| 6732 | Feature_HasMutableGlobalsBit = 10, |
| 6733 | Feature_HasNontrappingFPToIntBit = 11, |
| 6734 | Feature_NotHasNontrappingFPToIntBit = 19, |
| 6735 | Feature_HasReferenceTypesBit = 12, |
| 6736 | Feature_HasRelaxedAtomicsBit = 13, |
| 6737 | Feature_HasRelaxedSIMDBit = 14, |
| 6738 | Feature_HasSignExtBit = 16, |
| 6739 | Feature_HasSIMD128Bit = 15, |
| 6740 | Feature_HasTailCallBit = 17, |
| 6741 | Feature_HasWideArithmeticBit = 18, |
| 6742 | }; |
| 6743 | |
| 6744 | inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) { |
| 6745 | FeatureBitset Features; |
| 6746 | if (FB[WebAssembly::FeatureAtomics]) |
| 6747 | Features.set(Feature_HasAtomicsBit); |
| 6748 | if (FB[WebAssembly::FeatureBulkMemory]) |
| 6749 | Features.set(Feature_HasBulkMemoryBit); |
| 6750 | if (FB[WebAssembly::FeatureBulkMemoryOpt]) |
| 6751 | Features.set(Feature_HasBulkMemoryOptBit); |
| 6752 | if (FB[WebAssembly::FeatureCallIndirectOverlong]) |
| 6753 | Features.set(Feature_HasCallIndirectOverlongBit); |
| 6754 | if (FB[WebAssembly::FeatureExceptionHandling]) |
| 6755 | Features.set(Feature_HasExceptionHandlingBit); |
| 6756 | if (FB[WebAssembly::FeatureExtendedConst]) |
| 6757 | Features.set(Feature_HasExtendedConstBit); |
| 6758 | if (FB[WebAssembly::FeatureFP16]) |
| 6759 | Features.set(Feature_HasFP16Bit); |
| 6760 | if (FB[WebAssembly::FeatureGC]) |
| 6761 | Features.set(Feature_HasGCBit); |
| 6762 | if (FB[WebAssembly::FeatureMultiMemory]) |
| 6763 | Features.set(Feature_HasMultiMemoryBit); |
| 6764 | if (FB[WebAssembly::FeatureMultivalue]) |
| 6765 | Features.set(Feature_HasMultivalueBit); |
| 6766 | if (FB[WebAssembly::FeatureMutableGlobals]) |
| 6767 | Features.set(Feature_HasMutableGlobalsBit); |
| 6768 | if (FB[WebAssembly::FeatureNontrappingFPToInt]) |
| 6769 | Features.set(Feature_HasNontrappingFPToIntBit); |
| 6770 | if (!(FB[WebAssembly::FeatureNontrappingFPToInt])) |
| 6771 | Features.set(Feature_NotHasNontrappingFPToIntBit); |
| 6772 | if (FB[WebAssembly::FeatureReferenceTypes]) |
| 6773 | Features.set(Feature_HasReferenceTypesBit); |
| 6774 | if (FB[WebAssembly::FeatureRelaxedAtomics]) |
| 6775 | Features.set(Feature_HasRelaxedAtomicsBit); |
| 6776 | if (FB[WebAssembly::FeatureRelaxedSIMD]) |
| 6777 | Features.set(Feature_HasRelaxedSIMDBit); |
| 6778 | if (FB[WebAssembly::FeatureSignExt]) |
| 6779 | Features.set(Feature_HasSignExtBit); |
| 6780 | if (FB[WebAssembly::FeatureSIMD128] || FB[WebAssembly::FeatureRelaxedSIMD]) |
| 6781 | Features.set(Feature_HasSIMD128Bit); |
| 6782 | if (FB[WebAssembly::FeatureTailCall]) |
| 6783 | Features.set(Feature_HasTailCallBit); |
| 6784 | if (FB[WebAssembly::FeatureWideArithmetic]) |
| 6785 | Features.set(Feature_HasWideArithmeticBit); |
| 6786 | return Features; |
| 6787 | } |
| 6788 | |
| 6789 | inline FeatureBitset computeRequiredFeatures(unsigned Opcode) { |
| 6790 | enum : uint8_t { |
| 6791 | CEFBS_None, |
| 6792 | CEFBS_HasAtomics, |
| 6793 | CEFBS_HasBulkMemoryOpt, |
| 6794 | CEFBS_HasExceptionHandling, |
| 6795 | CEFBS_HasFP16, |
| 6796 | CEFBS_HasGC, |
| 6797 | CEFBS_HasNontrappingFPToInt, |
| 6798 | CEFBS_HasReferenceTypes, |
| 6799 | CEFBS_HasRelaxedSIMD, |
| 6800 | CEFBS_HasSIMD128, |
| 6801 | CEFBS_HasSignExt, |
| 6802 | CEFBS_HasTailCall, |
| 6803 | CEFBS_HasWideArithmetic, |
| 6804 | CEFBS_NotHasNontrappingFPToInt, |
| 6805 | CEFBS_HasReferenceTypes_HasExceptionHandling, |
| 6806 | CEFBS_HasSIMD128_HasFP16, |
| 6807 | CEFBS_HasSIMD128_HasRelaxedSIMD, |
| 6808 | CEFBS_HasTailCall_HasGC, |
| 6809 | }; |
| 6810 | |
| 6811 | static constexpr FeatureBitset FeatureBitsets[] = { |
| 6812 | {}, // CEFBS_None |
| 6813 | {Feature_HasAtomicsBit, }, |
| 6814 | {Feature_HasBulkMemoryOptBit, }, |
| 6815 | {Feature_HasExceptionHandlingBit, }, |
| 6816 | {Feature_HasFP16Bit, }, |
| 6817 | {Feature_HasGCBit, }, |
| 6818 | {Feature_HasNontrappingFPToIntBit, }, |
| 6819 | {Feature_HasReferenceTypesBit, }, |
| 6820 | {Feature_HasRelaxedSIMDBit, }, |
| 6821 | {Feature_HasSIMD128Bit, }, |
| 6822 | {Feature_HasSignExtBit, }, |
| 6823 | {Feature_HasTailCallBit, }, |
| 6824 | {Feature_HasWideArithmeticBit, }, |
| 6825 | {Feature_NotHasNontrappingFPToIntBit, }, |
| 6826 | {Feature_HasReferenceTypesBit, Feature_HasExceptionHandlingBit, }, |
| 6827 | {Feature_HasSIMD128Bit, Feature_HasFP16Bit, }, |
| 6828 | {Feature_HasSIMD128Bit, Feature_HasRelaxedSIMDBit, }, |
| 6829 | {Feature_HasTailCallBit, Feature_HasGCBit, }, |
| 6830 | }; |
| 6831 | static constexpr uint8_t RequiredFeaturesRefs[] = { |
| 6832 | CEFBS_None, // PHI |
| 6833 | CEFBS_None, // INLINEASM |
| 6834 | CEFBS_None, // INLINEASM_BR |
| 6835 | CEFBS_None, // CFI_INSTRUCTION |
| 6836 | CEFBS_None, // EH_LABEL |
| 6837 | CEFBS_None, // GC_LABEL |
| 6838 | CEFBS_None, // ANNOTATION_LABEL |
| 6839 | CEFBS_None, // KILL |
| 6840 | CEFBS_None, // EXTRACT_SUBREG |
| 6841 | CEFBS_None, // INSERT_SUBREG |
| 6842 | CEFBS_None, // IMPLICIT_DEF |
| 6843 | CEFBS_None, // INIT_UNDEF |
| 6844 | CEFBS_None, // SUBREG_TO_REG |
| 6845 | CEFBS_None, // COPY_TO_REGCLASS |
| 6846 | CEFBS_None, // DBG_VALUE |
| 6847 | CEFBS_None, // DBG_VALUE_LIST |
| 6848 | CEFBS_None, // DBG_INSTR_REF |
| 6849 | CEFBS_None, // DBG_PHI |
| 6850 | CEFBS_None, // DBG_LABEL |
| 6851 | CEFBS_None, // REG_SEQUENCE |
| 6852 | CEFBS_None, // COPY |
| 6853 | CEFBS_None, // COPY_LANEMASK |
| 6854 | CEFBS_None, // BUNDLE |
| 6855 | CEFBS_None, // LIFETIME_START |
| 6856 | CEFBS_None, // LIFETIME_END |
| 6857 | CEFBS_None, // PSEUDO_PROBE |
| 6858 | CEFBS_None, // ARITH_FENCE |
| 6859 | CEFBS_None, // STACKMAP |
| 6860 | CEFBS_None, // FENTRY_CALL |
| 6861 | CEFBS_None, // PATCHPOINT |
| 6862 | CEFBS_None, // LOAD_STACK_GUARD |
| 6863 | CEFBS_None, // PREALLOCATED_SETUP |
| 6864 | CEFBS_None, // PREALLOCATED_ARG |
| 6865 | CEFBS_None, // STATEPOINT |
| 6866 | CEFBS_None, // LOCAL_ESCAPE |
| 6867 | CEFBS_None, // FAULTING_OP |
| 6868 | CEFBS_None, // PATCHABLE_OP |
| 6869 | CEFBS_None, // PATCHABLE_FUNCTION_ENTER |
| 6870 | CEFBS_None, // PATCHABLE_RET |
| 6871 | CEFBS_None, // PATCHABLE_FUNCTION_EXIT |
| 6872 | CEFBS_None, // PATCHABLE_TAIL_CALL |
| 6873 | CEFBS_None, // PATCHABLE_EVENT_CALL |
| 6874 | CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL |
| 6875 | CEFBS_None, // ICALL_BRANCH_FUNNEL |
| 6876 | CEFBS_None, // FAKE_USE |
| 6877 | CEFBS_None, // MEMBARRIER |
| 6878 | CEFBS_None, // JUMP_TABLE_DEBUG_INFO |
| 6879 | CEFBS_None, // RELOC_NONE |
| 6880 | CEFBS_None, // CONVERGENCECTRL_ENTRY |
| 6881 | CEFBS_None, // CONVERGENCECTRL_ANCHOR |
| 6882 | CEFBS_None, // CONVERGENCECTRL_LOOP |
| 6883 | CEFBS_None, // CONVERGENCECTRL_GLUE |
| 6884 | CEFBS_None, // G_ASSERT_SEXT |
| 6885 | CEFBS_None, // G_ASSERT_ZEXT |
| 6886 | CEFBS_None, // G_ASSERT_ALIGN |
| 6887 | CEFBS_None, // G_ADD |
| 6888 | CEFBS_None, // G_SUB |
| 6889 | CEFBS_None, // G_MUL |
| 6890 | CEFBS_None, // G_SDIV |
| 6891 | CEFBS_None, // G_UDIV |
| 6892 | CEFBS_None, // G_SREM |
| 6893 | CEFBS_None, // G_UREM |
| 6894 | CEFBS_None, // G_SDIVREM |
| 6895 | CEFBS_None, // G_UDIVREM |
| 6896 | CEFBS_None, // G_AND |
| 6897 | CEFBS_None, // G_OR |
| 6898 | CEFBS_None, // G_XOR |
| 6899 | CEFBS_None, // G_ABDS |
| 6900 | CEFBS_None, // G_ABDU |
| 6901 | CEFBS_None, // G_UAVGFLOOR |
| 6902 | CEFBS_None, // G_UAVGCEIL |
| 6903 | CEFBS_None, // G_SAVGFLOOR |
| 6904 | CEFBS_None, // G_SAVGCEIL |
| 6905 | CEFBS_None, // G_IMPLICIT_DEF |
| 6906 | CEFBS_None, // G_PHI |
| 6907 | CEFBS_None, // G_FRAME_INDEX |
| 6908 | CEFBS_None, // G_GLOBAL_VALUE |
| 6909 | CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE |
| 6910 | CEFBS_None, // G_CONSTANT_POOL |
| 6911 | CEFBS_None, // G_EXTRACT |
| 6912 | CEFBS_None, // G_UNMERGE_VALUES |
| 6913 | CEFBS_None, // G_INSERT |
| 6914 | CEFBS_None, // G_MERGE_VALUES |
| 6915 | CEFBS_None, // G_BUILD_VECTOR |
| 6916 | CEFBS_None, // G_BUILD_VECTOR_TRUNC |
| 6917 | CEFBS_None, // G_CONCAT_VECTORS |
| 6918 | CEFBS_None, // G_PTRTOINT |
| 6919 | CEFBS_None, // G_INTTOPTR |
| 6920 | CEFBS_None, // G_BITCAST |
| 6921 | CEFBS_None, // G_FREEZE |
| 6922 | CEFBS_None, // G_CONSTANT_FOLD_BARRIER |
| 6923 | CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND |
| 6924 | CEFBS_None, // G_INTRINSIC_TRUNC |
| 6925 | CEFBS_None, // G_INTRINSIC_ROUND |
| 6926 | CEFBS_None, // G_INTRINSIC_LRINT |
| 6927 | CEFBS_None, // G_INTRINSIC_LLRINT |
| 6928 | CEFBS_None, // G_INTRINSIC_ROUNDEVEN |
| 6929 | CEFBS_None, // G_READCYCLECOUNTER |
| 6930 | CEFBS_None, // G_READSTEADYCOUNTER |
| 6931 | CEFBS_None, // G_LOAD |
| 6932 | CEFBS_None, // G_SEXTLOAD |
| 6933 | CEFBS_None, // G_ZEXTLOAD |
| 6934 | CEFBS_None, // G_FPEXTLOAD |
| 6935 | CEFBS_None, // G_INDEXED_LOAD |
| 6936 | CEFBS_None, // G_INDEXED_SEXTLOAD |
| 6937 | CEFBS_None, // G_INDEXED_ZEXTLOAD |
| 6938 | CEFBS_None, // G_STORE |
| 6939 | CEFBS_None, // G_FPTRUNCSTORE |
| 6940 | CEFBS_None, // G_INDEXED_STORE |
| 6941 | CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS |
| 6942 | CEFBS_None, // G_ATOMIC_CMPXCHG |
| 6943 | CEFBS_None, // G_ATOMICRMW_XCHG |
| 6944 | CEFBS_None, // G_ATOMICRMW_ADD |
| 6945 | CEFBS_None, // G_ATOMICRMW_SUB |
| 6946 | CEFBS_None, // G_ATOMICRMW_AND |
| 6947 | CEFBS_None, // G_ATOMICRMW_NAND |
| 6948 | CEFBS_None, // G_ATOMICRMW_OR |
| 6949 | CEFBS_None, // G_ATOMICRMW_XOR |
| 6950 | CEFBS_None, // G_ATOMICRMW_MAX |
| 6951 | CEFBS_None, // G_ATOMICRMW_MIN |
| 6952 | CEFBS_None, // G_ATOMICRMW_UMAX |
| 6953 | CEFBS_None, // G_ATOMICRMW_UMIN |
| 6954 | CEFBS_None, // G_ATOMICRMW_FADD |
| 6955 | CEFBS_None, // G_ATOMICRMW_FSUB |
| 6956 | CEFBS_None, // G_ATOMICRMW_FMAX |
| 6957 | CEFBS_None, // G_ATOMICRMW_FMIN |
| 6958 | CEFBS_None, // G_ATOMICRMW_FMAXIMUM |
| 6959 | CEFBS_None, // G_ATOMICRMW_FMINIMUM |
| 6960 | CEFBS_None, // G_ATOMICRMW_FMAXIMUMNUM |
| 6961 | CEFBS_None, // G_ATOMICRMW_FMINIMUMNUM |
| 6962 | CEFBS_None, // G_ATOMICRMW_UINC_WRAP |
| 6963 | CEFBS_None, // G_ATOMICRMW_UDEC_WRAP |
| 6964 | CEFBS_None, // G_ATOMICRMW_USUB_COND |
| 6965 | CEFBS_None, // G_ATOMICRMW_USUB_SAT |
| 6966 | CEFBS_None, // G_FENCE |
| 6967 | CEFBS_None, // G_PREFETCH |
| 6968 | CEFBS_None, // G_BRCOND |
| 6969 | CEFBS_None, // G_BRINDIRECT |
| 6970 | CEFBS_None, // G_INVOKE_REGION_START |
| 6971 | CEFBS_None, // G_INTRINSIC |
| 6972 | CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS |
| 6973 | CEFBS_None, // G_INTRINSIC_CONVERGENT |
| 6974 | CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS |
| 6975 | CEFBS_None, // G_ANYEXT |
| 6976 | CEFBS_None, // G_TRUNC |
| 6977 | CEFBS_None, // G_TRUNC_SSAT_S |
| 6978 | CEFBS_None, // G_TRUNC_SSAT_U |
| 6979 | CEFBS_None, // G_TRUNC_USAT_U |
| 6980 | CEFBS_None, // G_CONSTANT |
| 6981 | CEFBS_None, // G_FCONSTANT |
| 6982 | CEFBS_None, // G_VASTART |
| 6983 | CEFBS_None, // G_VAARG |
| 6984 | CEFBS_None, // G_SEXT |
| 6985 | CEFBS_None, // G_SEXT_INREG |
| 6986 | CEFBS_None, // G_ZEXT |
| 6987 | CEFBS_None, // G_SHL |
| 6988 | CEFBS_None, // G_LSHR |
| 6989 | CEFBS_None, // G_ASHR |
| 6990 | CEFBS_None, // G_FSHL |
| 6991 | CEFBS_None, // G_FSHR |
| 6992 | CEFBS_None, // G_ROTR |
| 6993 | CEFBS_None, // G_ROTL |
| 6994 | CEFBS_None, // G_ICMP |
| 6995 | CEFBS_None, // G_FCMP |
| 6996 | CEFBS_None, // G_SCMP |
| 6997 | CEFBS_None, // G_UCMP |
| 6998 | CEFBS_None, // G_SELECT |
| 6999 | CEFBS_None, // G_UADDO |
| 7000 | CEFBS_None, // G_UADDE |
| 7001 | CEFBS_None, // G_USUBO |
| 7002 | CEFBS_None, // G_USUBE |
| 7003 | CEFBS_None, // G_SADDO |
| 7004 | CEFBS_None, // G_SADDE |
| 7005 | CEFBS_None, // G_SSUBO |
| 7006 | CEFBS_None, // G_SSUBE |
| 7007 | CEFBS_None, // G_UMULO |
| 7008 | CEFBS_None, // G_SMULO |
| 7009 | CEFBS_None, // G_UMULH |
| 7010 | CEFBS_None, // G_SMULH |
| 7011 | CEFBS_None, // G_UADDSAT |
| 7012 | CEFBS_None, // G_SADDSAT |
| 7013 | CEFBS_None, // G_USUBSAT |
| 7014 | CEFBS_None, // G_SSUBSAT |
| 7015 | CEFBS_None, // G_USHLSAT |
| 7016 | CEFBS_None, // G_SSHLSAT |
| 7017 | CEFBS_None, // G_SMULFIX |
| 7018 | CEFBS_None, // G_UMULFIX |
| 7019 | CEFBS_None, // G_SMULFIXSAT |
| 7020 | CEFBS_None, // G_UMULFIXSAT |
| 7021 | CEFBS_None, // G_SDIVFIX |
| 7022 | CEFBS_None, // G_UDIVFIX |
| 7023 | CEFBS_None, // G_SDIVFIXSAT |
| 7024 | CEFBS_None, // G_UDIVFIXSAT |
| 7025 | CEFBS_None, // G_FADD |
| 7026 | CEFBS_None, // G_FSUB |
| 7027 | CEFBS_None, // G_FMUL |
| 7028 | CEFBS_None, // G_FMA |
| 7029 | CEFBS_None, // G_FMAD |
| 7030 | CEFBS_None, // G_FDIV |
| 7031 | CEFBS_None, // G_FREM |
| 7032 | CEFBS_None, // G_FMODF |
| 7033 | CEFBS_None, // G_FPOW |
| 7034 | CEFBS_None, // G_FPOWI |
| 7035 | CEFBS_None, // G_FEXP |
| 7036 | CEFBS_None, // G_FEXP2 |
| 7037 | CEFBS_None, // G_FEXP10 |
| 7038 | CEFBS_None, // G_FLOG |
| 7039 | CEFBS_None, // G_FLOG2 |
| 7040 | CEFBS_None, // G_FLOG10 |
| 7041 | CEFBS_None, // G_FLDEXP |
| 7042 | CEFBS_None, // G_FFREXP |
| 7043 | CEFBS_None, // G_FNEG |
| 7044 | CEFBS_None, // G_FPEXT |
| 7045 | CEFBS_None, // G_FPTRUNC |
| 7046 | CEFBS_None, // G_FPTOSI |
| 7047 | CEFBS_None, // G_FPTOUI |
| 7048 | CEFBS_None, // G_SITOFP |
| 7049 | CEFBS_None, // G_UITOFP |
| 7050 | CEFBS_None, // G_FPTOSI_SAT |
| 7051 | CEFBS_None, // G_FPTOUI_SAT |
| 7052 | CEFBS_None, // G_FABS |
| 7053 | CEFBS_None, // G_FCOPYSIGN |
| 7054 | CEFBS_None, // G_IS_FPCLASS |
| 7055 | CEFBS_None, // G_FCANONICALIZE |
| 7056 | CEFBS_None, // G_FMINNUM |
| 7057 | CEFBS_None, // G_FMAXNUM |
| 7058 | CEFBS_None, // G_FMINNUM_IEEE |
| 7059 | CEFBS_None, // G_FMAXNUM_IEEE |
| 7060 | CEFBS_None, // G_FMINIMUM |
| 7061 | CEFBS_None, // G_FMAXIMUM |
| 7062 | CEFBS_None, // G_FMINIMUMNUM |
| 7063 | CEFBS_None, // G_FMAXIMUMNUM |
| 7064 | CEFBS_None, // G_GET_FPENV |
| 7065 | CEFBS_None, // G_SET_FPENV |
| 7066 | CEFBS_None, // G_RESET_FPENV |
| 7067 | CEFBS_None, // G_GET_FPMODE |
| 7068 | CEFBS_None, // G_SET_FPMODE |
| 7069 | CEFBS_None, // G_RESET_FPMODE |
| 7070 | CEFBS_None, // G_GET_ROUNDING |
| 7071 | CEFBS_None, // G_SET_ROUNDING |
| 7072 | CEFBS_None, // G_PTR_ADD |
| 7073 | CEFBS_None, // G_PTRMASK |
| 7074 | CEFBS_None, // G_SMIN |
| 7075 | CEFBS_None, // G_SMAX |
| 7076 | CEFBS_None, // G_UMIN |
| 7077 | CEFBS_None, // G_UMAX |
| 7078 | CEFBS_None, // G_ABS |
| 7079 | CEFBS_None, // G_LROUND |
| 7080 | CEFBS_None, // G_LLROUND |
| 7081 | CEFBS_None, // G_BR |
| 7082 | CEFBS_None, // G_BRJT |
| 7083 | CEFBS_None, // G_VSCALE |
| 7084 | CEFBS_None, // G_INSERT_SUBVECTOR |
| 7085 | CEFBS_None, // G_EXTRACT_SUBVECTOR |
| 7086 | CEFBS_None, // G_INSERT_VECTOR_ELT |
| 7087 | CEFBS_None, // G_EXTRACT_VECTOR_ELT |
| 7088 | CEFBS_None, // G_SHUFFLE_VECTOR |
| 7089 | CEFBS_None, // G_SPLAT_VECTOR |
| 7090 | CEFBS_None, // G_STEP_VECTOR |
| 7091 | CEFBS_None, // G_VECTOR_COMPRESS |
| 7092 | CEFBS_None, // G_CTTZ |
| 7093 | CEFBS_None, // G_CTTZ_ZERO_POISON |
| 7094 | CEFBS_None, // G_CTLZ |
| 7095 | CEFBS_None, // G_CTLZ_ZERO_POISON |
| 7096 | CEFBS_None, // G_CTLS |
| 7097 | CEFBS_None, // G_CTPOP |
| 7098 | CEFBS_None, // G_BSWAP |
| 7099 | CEFBS_None, // G_BITREVERSE |
| 7100 | CEFBS_None, // G_CLMUL |
| 7101 | CEFBS_None, // G_CLMULH |
| 7102 | CEFBS_None, // G_FCEIL |
| 7103 | CEFBS_None, // G_FCOS |
| 7104 | CEFBS_None, // G_FSIN |
| 7105 | CEFBS_None, // G_FSINCOS |
| 7106 | CEFBS_None, // G_FTAN |
| 7107 | CEFBS_None, // G_FACOS |
| 7108 | CEFBS_None, // G_FASIN |
| 7109 | CEFBS_None, // G_FATAN |
| 7110 | CEFBS_None, // G_FATAN2 |
| 7111 | CEFBS_None, // G_FCOSH |
| 7112 | CEFBS_None, // G_FSINH |
| 7113 | CEFBS_None, // G_FTANH |
| 7114 | CEFBS_None, // G_FSQRT |
| 7115 | CEFBS_None, // G_FFLOOR |
| 7116 | CEFBS_None, // G_FRINT |
| 7117 | CEFBS_None, // G_FNEARBYINT |
| 7118 | CEFBS_None, // G_ADDRSPACE_CAST |
| 7119 | CEFBS_None, // G_BLOCK_ADDR |
| 7120 | CEFBS_None, // G_JUMP_TABLE |
| 7121 | CEFBS_None, // G_DYN_STACKALLOC |
| 7122 | CEFBS_None, // G_STACKSAVE |
| 7123 | CEFBS_None, // G_STACKRESTORE |
| 7124 | CEFBS_None, // G_STRICT_FADD |
| 7125 | CEFBS_None, // G_STRICT_FSUB |
| 7126 | CEFBS_None, // G_STRICT_FMUL |
| 7127 | CEFBS_None, // G_STRICT_FDIV |
| 7128 | CEFBS_None, // G_STRICT_FREM |
| 7129 | CEFBS_None, // G_STRICT_FMA |
| 7130 | CEFBS_None, // G_STRICT_FSQRT |
| 7131 | CEFBS_None, // G_STRICT_FLDEXP |
| 7132 | CEFBS_None, // G_STRICT_FCMP |
| 7133 | CEFBS_None, // G_STRICT_FCMPS |
| 7134 | CEFBS_None, // G_READ_REGISTER |
| 7135 | CEFBS_None, // G_WRITE_REGISTER |
| 7136 | CEFBS_None, // G_MEMCPY |
| 7137 | CEFBS_None, // G_MEMCPY_INLINE |
| 7138 | CEFBS_None, // G_MEMMOVE |
| 7139 | CEFBS_None, // G_MEMSET |
| 7140 | CEFBS_None, // G_BZERO |
| 7141 | CEFBS_None, // G_MEMSET_INLINE |
| 7142 | CEFBS_None, // G_TRAP |
| 7143 | CEFBS_None, // G_DEBUGTRAP |
| 7144 | CEFBS_None, // G_UBSANTRAP |
| 7145 | CEFBS_None, // G_VECREDUCE_SEQ_FADD |
| 7146 | CEFBS_None, // G_VECREDUCE_SEQ_FMUL |
| 7147 | CEFBS_None, // G_VECREDUCE_FADD |
| 7148 | CEFBS_None, // G_VECREDUCE_FMUL |
| 7149 | CEFBS_None, // G_VECREDUCE_FMAX |
| 7150 | CEFBS_None, // G_VECREDUCE_FMIN |
| 7151 | CEFBS_None, // G_VECREDUCE_FMAXIMUM |
| 7152 | CEFBS_None, // G_VECREDUCE_FMINIMUM |
| 7153 | CEFBS_None, // G_VECREDUCE_FMAXIMUMNUM |
| 7154 | CEFBS_None, // G_VECREDUCE_FMINIMUMNUM |
| 7155 | CEFBS_None, // G_VECREDUCE_ADD |
| 7156 | CEFBS_None, // G_VECREDUCE_MUL |
| 7157 | CEFBS_None, // G_VECREDUCE_AND |
| 7158 | CEFBS_None, // G_VECREDUCE_OR |
| 7159 | CEFBS_None, // G_VECREDUCE_XOR |
| 7160 | CEFBS_None, // G_VECREDUCE_SMAX |
| 7161 | CEFBS_None, // G_VECREDUCE_SMIN |
| 7162 | CEFBS_None, // G_VECREDUCE_UMAX |
| 7163 | CEFBS_None, // G_VECREDUCE_UMIN |
| 7164 | CEFBS_None, // G_SBFX |
| 7165 | CEFBS_None, // G_UBFX |
| 7166 | CEFBS_None, // CALL_PARAMS |
| 7167 | CEFBS_None, // CALL_PARAMS_S |
| 7168 | CEFBS_None, // CALL_RESULTS |
| 7169 | CEFBS_None, // CALL_RESULTS_S |
| 7170 | CEFBS_HasExceptionHandling, // CATCHRET |
| 7171 | CEFBS_HasExceptionHandling, // CATCHRET_S |
| 7172 | CEFBS_HasExceptionHandling, // CLEANUPRET |
| 7173 | CEFBS_HasExceptionHandling, // CLEANUPRET_S |
| 7174 | CEFBS_HasAtomics, // COMPILER_FENCE |
| 7175 | CEFBS_HasAtomics, // COMPILER_FENCE_S |
| 7176 | CEFBS_None, // RET_CALL_RESULTS |
| 7177 | CEFBS_None, // RET_CALL_RESULTS_S |
| 7178 | CEFBS_HasSIMD128_HasFP16, // ABS_F16x8 |
| 7179 | CEFBS_HasSIMD128_HasFP16, // ABS_F16x8_S |
| 7180 | CEFBS_None, // ABS_F32 |
| 7181 | CEFBS_None, // ABS_F32_S |
| 7182 | CEFBS_HasSIMD128, // ABS_F32x4 |
| 7183 | CEFBS_HasSIMD128, // ABS_F32x4_S |
| 7184 | CEFBS_None, // ABS_F64 |
| 7185 | CEFBS_None, // ABS_F64_S |
| 7186 | CEFBS_HasSIMD128, // ABS_F64x2 |
| 7187 | CEFBS_HasSIMD128, // ABS_F64x2_S |
| 7188 | CEFBS_HasSIMD128, // ABS_I16x8 |
| 7189 | CEFBS_HasSIMD128, // ABS_I16x8_S |
| 7190 | CEFBS_HasSIMD128, // ABS_I32x4 |
| 7191 | CEFBS_HasSIMD128, // ABS_I32x4_S |
| 7192 | CEFBS_HasSIMD128, // ABS_I64x2 |
| 7193 | CEFBS_HasSIMD128, // ABS_I64x2_S |
| 7194 | CEFBS_HasSIMD128, // ABS_I8x16 |
| 7195 | CEFBS_HasSIMD128, // ABS_I8x16_S |
| 7196 | CEFBS_HasSIMD128_HasFP16, // ADD_F16x8 |
| 7197 | CEFBS_HasSIMD128_HasFP16, // ADD_F16x8_S |
| 7198 | CEFBS_None, // ADD_F32 |
| 7199 | CEFBS_None, // ADD_F32_S |
| 7200 | CEFBS_HasSIMD128, // ADD_F32x4 |
| 7201 | CEFBS_HasSIMD128, // ADD_F32x4_S |
| 7202 | CEFBS_None, // ADD_F64 |
| 7203 | CEFBS_None, // ADD_F64_S |
| 7204 | CEFBS_HasSIMD128, // ADD_F64x2 |
| 7205 | CEFBS_HasSIMD128, // ADD_F64x2_S |
| 7206 | CEFBS_HasSIMD128, // ADD_I16x8 |
| 7207 | CEFBS_HasSIMD128, // ADD_I16x8_S |
| 7208 | CEFBS_None, // ADD_I32 |
| 7209 | CEFBS_None, // ADD_I32_S |
| 7210 | CEFBS_HasSIMD128, // ADD_I32x4 |
| 7211 | CEFBS_HasSIMD128, // ADD_I32x4_S |
| 7212 | CEFBS_None, // ADD_I64 |
| 7213 | CEFBS_None, // ADD_I64_S |
| 7214 | CEFBS_HasSIMD128, // ADD_I64x2 |
| 7215 | CEFBS_HasSIMD128, // ADD_I64x2_S |
| 7216 | CEFBS_HasSIMD128, // ADD_I8x16 |
| 7217 | CEFBS_HasSIMD128, // ADD_I8x16_S |
| 7218 | CEFBS_HasSIMD128, // ADD_SAT_S_I16x8 |
| 7219 | CEFBS_HasSIMD128, // ADD_SAT_S_I16x8_S |
| 7220 | CEFBS_HasSIMD128, // ADD_SAT_S_I8x16 |
| 7221 | CEFBS_HasSIMD128, // ADD_SAT_S_I8x16_S |
| 7222 | CEFBS_HasSIMD128, // ADD_SAT_U_I16x8 |
| 7223 | CEFBS_HasSIMD128, // ADD_SAT_U_I16x8_S |
| 7224 | CEFBS_HasSIMD128, // ADD_SAT_U_I8x16 |
| 7225 | CEFBS_HasSIMD128, // ADD_SAT_U_I8x16_S |
| 7226 | CEFBS_None, // ADJCALLSTACKDOWN |
| 7227 | CEFBS_None, // ADJCALLSTACKDOWN_S |
| 7228 | CEFBS_None, // ADJCALLSTACKUP |
| 7229 | CEFBS_None, // ADJCALLSTACKUP_S |
| 7230 | CEFBS_HasSIMD128, // ALLTRUE_I16x8 |
| 7231 | CEFBS_HasSIMD128, // ALLTRUE_I16x8_S |
| 7232 | CEFBS_HasSIMD128, // ALLTRUE_I32x4 |
| 7233 | CEFBS_HasSIMD128, // ALLTRUE_I32x4_S |
| 7234 | CEFBS_HasSIMD128, // ALLTRUE_I64x2 |
| 7235 | CEFBS_HasSIMD128, // ALLTRUE_I64x2_S |
| 7236 | CEFBS_HasSIMD128, // ALLTRUE_I8x16 |
| 7237 | CEFBS_HasSIMD128, // ALLTRUE_I8x16_S |
| 7238 | CEFBS_HasSIMD128, // AND |
| 7239 | CEFBS_HasSIMD128, // ANDNOT |
| 7240 | CEFBS_HasSIMD128, // ANDNOT_S |
| 7241 | CEFBS_None, // AND_I32 |
| 7242 | CEFBS_None, // AND_I32_S |
| 7243 | CEFBS_None, // AND_I64 |
| 7244 | CEFBS_None, // AND_I64_S |
| 7245 | CEFBS_HasSIMD128, // AND_S |
| 7246 | CEFBS_HasSIMD128, // ANYTRUE |
| 7247 | CEFBS_HasSIMD128, // ANYTRUE_S |
| 7248 | CEFBS_None, // ARGUMENT_exnref |
| 7249 | CEFBS_None, // ARGUMENT_exnref_S |
| 7250 | CEFBS_None, // ARGUMENT_externref |
| 7251 | CEFBS_None, // ARGUMENT_externref_S |
| 7252 | CEFBS_None, // ARGUMENT_f32 |
| 7253 | CEFBS_None, // ARGUMENT_f32_S |
| 7254 | CEFBS_None, // ARGUMENT_f64 |
| 7255 | CEFBS_None, // ARGUMENT_f64_S |
| 7256 | CEFBS_None, // ARGUMENT_funcref |
| 7257 | CEFBS_None, // ARGUMENT_funcref_S |
| 7258 | CEFBS_None, // ARGUMENT_i32 |
| 7259 | CEFBS_None, // ARGUMENT_i32_S |
| 7260 | CEFBS_None, // ARGUMENT_i64 |
| 7261 | CEFBS_None, // ARGUMENT_i64_S |
| 7262 | CEFBS_None, // ARGUMENT_v16i8 |
| 7263 | CEFBS_None, // ARGUMENT_v16i8_S |
| 7264 | CEFBS_None, // ARGUMENT_v2f64 |
| 7265 | CEFBS_None, // ARGUMENT_v2f64_S |
| 7266 | CEFBS_None, // ARGUMENT_v2i64 |
| 7267 | CEFBS_None, // ARGUMENT_v2i64_S |
| 7268 | CEFBS_None, // ARGUMENT_v4f32 |
| 7269 | CEFBS_None, // ARGUMENT_v4f32_S |
| 7270 | CEFBS_None, // ARGUMENT_v4i32 |
| 7271 | CEFBS_None, // ARGUMENT_v4i32_S |
| 7272 | CEFBS_None, // ARGUMENT_v8f16 |
| 7273 | CEFBS_None, // ARGUMENT_v8f16_S |
| 7274 | CEFBS_None, // ARGUMENT_v8i16 |
| 7275 | CEFBS_None, // ARGUMENT_v8i16_S |
| 7276 | CEFBS_HasAtomics, // ATOMIC_FENCE |
| 7277 | CEFBS_HasAtomics, // ATOMIC_FENCE_S |
| 7278 | CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I32_A32 |
| 7279 | CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I32_A32_S |
| 7280 | CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I32_A64 |
| 7281 | CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I32_A64_S |
| 7282 | CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I64_A32 |
| 7283 | CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I64_A32_S |
| 7284 | CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I64_A64 |
| 7285 | CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I64_A64_S |
| 7286 | CEFBS_HasAtomics, // ATOMIC_LOAD32_U_I64_A32 |
| 7287 | CEFBS_HasAtomics, // ATOMIC_LOAD32_U_I64_A32_S |
| 7288 | CEFBS_HasAtomics, // ATOMIC_LOAD32_U_I64_A64 |
| 7289 | CEFBS_HasAtomics, // ATOMIC_LOAD32_U_I64_A64_S |
| 7290 | CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I32_A32 |
| 7291 | CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I32_A32_S |
| 7292 | CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I32_A64 |
| 7293 | CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I32_A64_S |
| 7294 | CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I64_A32 |
| 7295 | CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I64_A32_S |
| 7296 | CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I64_A64 |
| 7297 | CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I64_A64_S |
| 7298 | CEFBS_HasAtomics, // ATOMIC_LOAD_I32_A32 |
| 7299 | CEFBS_HasAtomics, // ATOMIC_LOAD_I32_A32_S |
| 7300 | CEFBS_HasAtomics, // ATOMIC_LOAD_I32_A64 |
| 7301 | CEFBS_HasAtomics, // ATOMIC_LOAD_I32_A64_S |
| 7302 | CEFBS_HasAtomics, // ATOMIC_LOAD_I64_A32 |
| 7303 | CEFBS_HasAtomics, // ATOMIC_LOAD_I64_A32_S |
| 7304 | CEFBS_HasAtomics, // ATOMIC_LOAD_I64_A64 |
| 7305 | CEFBS_HasAtomics, // ATOMIC_LOAD_I64_A64_S |
| 7306 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I32_A32 |
| 7307 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I32_A32_S |
| 7308 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I32_A64 |
| 7309 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I32_A64_S |
| 7310 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I64_A32 |
| 7311 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I64_A32_S |
| 7312 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I64_A64 |
| 7313 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I64_A64_S |
| 7314 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I32_A32 |
| 7315 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I32_A32_S |
| 7316 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I32_A64 |
| 7317 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I32_A64_S |
| 7318 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I64_A32 |
| 7319 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I64_A32_S |
| 7320 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I64_A64 |
| 7321 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I64_A64_S |
| 7322 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I32_A32 |
| 7323 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I32_A32_S |
| 7324 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I32_A64 |
| 7325 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I32_A64_S |
| 7326 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I64_A32 |
| 7327 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I64_A32_S |
| 7328 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I64_A64 |
| 7329 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I64_A64_S |
| 7330 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I32_A32 |
| 7331 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I32_A32_S |
| 7332 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I32_A64 |
| 7333 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I32_A64_S |
| 7334 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I64_A32 |
| 7335 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I64_A32_S |
| 7336 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I64_A64 |
| 7337 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I64_A64_S |
| 7338 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I32_A32 |
| 7339 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I32_A32_S |
| 7340 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I32_A64 |
| 7341 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I32_A64_S |
| 7342 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I64_A32 |
| 7343 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I64_A32_S |
| 7344 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I64_A64 |
| 7345 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I64_A64_S |
| 7346 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I32_A32 |
| 7347 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I32_A32_S |
| 7348 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I32_A64 |
| 7349 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I32_A64_S |
| 7350 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I64_A32 |
| 7351 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I64_A32_S |
| 7352 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I64_A64 |
| 7353 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I64_A64_S |
| 7354 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I32_A32 |
| 7355 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I32_A32_S |
| 7356 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I32_A64 |
| 7357 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I32_A64_S |
| 7358 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I64_A32 |
| 7359 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I64_A32_S |
| 7360 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I64_A64 |
| 7361 | CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I64_A64_S |
| 7362 | CEFBS_HasAtomics, // ATOMIC_RMW32_U_ADD_I64_A32 |
| 7363 | CEFBS_HasAtomics, // ATOMIC_RMW32_U_ADD_I64_A32_S |
| 7364 | CEFBS_HasAtomics, // ATOMIC_RMW32_U_ADD_I64_A64 |
| 7365 | CEFBS_HasAtomics, // ATOMIC_RMW32_U_ADD_I64_A64_S |
| 7366 | CEFBS_HasAtomics, // ATOMIC_RMW32_U_AND_I64_A32 |
| 7367 | CEFBS_HasAtomics, // ATOMIC_RMW32_U_AND_I64_A32_S |
| 7368 | CEFBS_HasAtomics, // ATOMIC_RMW32_U_AND_I64_A64 |
| 7369 | CEFBS_HasAtomics, // ATOMIC_RMW32_U_AND_I64_A64_S |
| 7370 | CEFBS_HasAtomics, // ATOMIC_RMW32_U_CMPXCHG_I64_A32 |
| 7371 | CEFBS_HasAtomics, // ATOMIC_RMW32_U_CMPXCHG_I64_A32_S |
| 7372 | CEFBS_HasAtomics, // ATOMIC_RMW32_U_CMPXCHG_I64_A64 |
| 7373 | CEFBS_HasAtomics, // ATOMIC_RMW32_U_CMPXCHG_I64_A64_S |
| 7374 | CEFBS_HasAtomics, // ATOMIC_RMW32_U_OR_I64_A32 |
| 7375 | CEFBS_HasAtomics, // ATOMIC_RMW32_U_OR_I64_A32_S |
| 7376 | CEFBS_HasAtomics, // ATOMIC_RMW32_U_OR_I64_A64 |
| 7377 | CEFBS_HasAtomics, // ATOMIC_RMW32_U_OR_I64_A64_S |
| 7378 | CEFBS_HasAtomics, // ATOMIC_RMW32_U_SUB_I64_A32 |
| 7379 | CEFBS_HasAtomics, // ATOMIC_RMW32_U_SUB_I64_A32_S |
| 7380 | CEFBS_HasAtomics, // ATOMIC_RMW32_U_SUB_I64_A64 |
| 7381 | CEFBS_HasAtomics, // ATOMIC_RMW32_U_SUB_I64_A64_S |
| 7382 | CEFBS_HasAtomics, // ATOMIC_RMW32_U_XCHG_I64_A32 |
| 7383 | CEFBS_HasAtomics, // ATOMIC_RMW32_U_XCHG_I64_A32_S |
| 7384 | CEFBS_HasAtomics, // ATOMIC_RMW32_U_XCHG_I64_A64 |
| 7385 | CEFBS_HasAtomics, // ATOMIC_RMW32_U_XCHG_I64_A64_S |
| 7386 | CEFBS_HasAtomics, // ATOMIC_RMW32_U_XOR_I64_A32 |
| 7387 | CEFBS_HasAtomics, // ATOMIC_RMW32_U_XOR_I64_A32_S |
| 7388 | CEFBS_HasAtomics, // ATOMIC_RMW32_U_XOR_I64_A64 |
| 7389 | CEFBS_HasAtomics, // ATOMIC_RMW32_U_XOR_I64_A64_S |
| 7390 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I32_A32 |
| 7391 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I32_A32_S |
| 7392 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I32_A64 |
| 7393 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I32_A64_S |
| 7394 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I64_A32 |
| 7395 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I64_A32_S |
| 7396 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I64_A64 |
| 7397 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I64_A64_S |
| 7398 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I32_A32 |
| 7399 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I32_A32_S |
| 7400 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I32_A64 |
| 7401 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I32_A64_S |
| 7402 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I64_A32 |
| 7403 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I64_A32_S |
| 7404 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I64_A64 |
| 7405 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I64_A64_S |
| 7406 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I32_A32 |
| 7407 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I32_A32_S |
| 7408 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I32_A64 |
| 7409 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I32_A64_S |
| 7410 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I64_A32 |
| 7411 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I64_A32_S |
| 7412 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I64_A64 |
| 7413 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I64_A64_S |
| 7414 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I32_A32 |
| 7415 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I32_A32_S |
| 7416 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I32_A64 |
| 7417 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I32_A64_S |
| 7418 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I64_A32 |
| 7419 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I64_A32_S |
| 7420 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I64_A64 |
| 7421 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I64_A64_S |
| 7422 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I32_A32 |
| 7423 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I32_A32_S |
| 7424 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I32_A64 |
| 7425 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I32_A64_S |
| 7426 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I64_A32 |
| 7427 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I64_A32_S |
| 7428 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I64_A64 |
| 7429 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I64_A64_S |
| 7430 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I32_A32 |
| 7431 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I32_A32_S |
| 7432 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I32_A64 |
| 7433 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I32_A64_S |
| 7434 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I64_A32 |
| 7435 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I64_A32_S |
| 7436 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I64_A64 |
| 7437 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I64_A64_S |
| 7438 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I32_A32 |
| 7439 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I32_A32_S |
| 7440 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I32_A64 |
| 7441 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I32_A64_S |
| 7442 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I64_A32 |
| 7443 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I64_A32_S |
| 7444 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I64_A64 |
| 7445 | CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I64_A64_S |
| 7446 | CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I32_A32 |
| 7447 | CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I32_A32_S |
| 7448 | CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I32_A64 |
| 7449 | CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I32_A64_S |
| 7450 | CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I64_A32 |
| 7451 | CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I64_A32_S |
| 7452 | CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I64_A64 |
| 7453 | CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I64_A64_S |
| 7454 | CEFBS_HasAtomics, // ATOMIC_RMW_AND_I32_A32 |
| 7455 | CEFBS_HasAtomics, // ATOMIC_RMW_AND_I32_A32_S |
| 7456 | CEFBS_HasAtomics, // ATOMIC_RMW_AND_I32_A64 |
| 7457 | CEFBS_HasAtomics, // ATOMIC_RMW_AND_I32_A64_S |
| 7458 | CEFBS_HasAtomics, // ATOMIC_RMW_AND_I64_A32 |
| 7459 | CEFBS_HasAtomics, // ATOMIC_RMW_AND_I64_A32_S |
| 7460 | CEFBS_HasAtomics, // ATOMIC_RMW_AND_I64_A64 |
| 7461 | CEFBS_HasAtomics, // ATOMIC_RMW_AND_I64_A64_S |
| 7462 | CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I32_A32 |
| 7463 | CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I32_A32_S |
| 7464 | CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I32_A64 |
| 7465 | CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I32_A64_S |
| 7466 | CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I64_A32 |
| 7467 | CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I64_A32_S |
| 7468 | CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I64_A64 |
| 7469 | CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I64_A64_S |
| 7470 | CEFBS_HasAtomics, // ATOMIC_RMW_OR_I32_A32 |
| 7471 | CEFBS_HasAtomics, // ATOMIC_RMW_OR_I32_A32_S |
| 7472 | CEFBS_HasAtomics, // ATOMIC_RMW_OR_I32_A64 |
| 7473 | CEFBS_HasAtomics, // ATOMIC_RMW_OR_I32_A64_S |
| 7474 | CEFBS_HasAtomics, // ATOMIC_RMW_OR_I64_A32 |
| 7475 | CEFBS_HasAtomics, // ATOMIC_RMW_OR_I64_A32_S |
| 7476 | CEFBS_HasAtomics, // ATOMIC_RMW_OR_I64_A64 |
| 7477 | CEFBS_HasAtomics, // ATOMIC_RMW_OR_I64_A64_S |
| 7478 | CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I32_A32 |
| 7479 | CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I32_A32_S |
| 7480 | CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I32_A64 |
| 7481 | CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I32_A64_S |
| 7482 | CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I64_A32 |
| 7483 | CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I64_A32_S |
| 7484 | CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I64_A64 |
| 7485 | CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I64_A64_S |
| 7486 | CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I32_A32 |
| 7487 | CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I32_A32_S |
| 7488 | CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I32_A64 |
| 7489 | CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I32_A64_S |
| 7490 | CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I64_A32 |
| 7491 | CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I64_A32_S |
| 7492 | CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I64_A64 |
| 7493 | CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I64_A64_S |
| 7494 | CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I32_A32 |
| 7495 | CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I32_A32_S |
| 7496 | CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I32_A64 |
| 7497 | CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I32_A64_S |
| 7498 | CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I64_A32 |
| 7499 | CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I64_A32_S |
| 7500 | CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I64_A64 |
| 7501 | CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I64_A64_S |
| 7502 | CEFBS_HasAtomics, // ATOMIC_STORE16_I32_A32 |
| 7503 | CEFBS_HasAtomics, // ATOMIC_STORE16_I32_A32_S |
| 7504 | CEFBS_HasAtomics, // ATOMIC_STORE16_I32_A64 |
| 7505 | CEFBS_HasAtomics, // ATOMIC_STORE16_I32_A64_S |
| 7506 | CEFBS_HasAtomics, // ATOMIC_STORE16_I64_A32 |
| 7507 | CEFBS_HasAtomics, // ATOMIC_STORE16_I64_A32_S |
| 7508 | CEFBS_HasAtomics, // ATOMIC_STORE16_I64_A64 |
| 7509 | CEFBS_HasAtomics, // ATOMIC_STORE16_I64_A64_S |
| 7510 | CEFBS_HasAtomics, // ATOMIC_STORE32_I64_A32 |
| 7511 | CEFBS_HasAtomics, // ATOMIC_STORE32_I64_A32_S |
| 7512 | CEFBS_HasAtomics, // ATOMIC_STORE32_I64_A64 |
| 7513 | CEFBS_HasAtomics, // ATOMIC_STORE32_I64_A64_S |
| 7514 | CEFBS_HasAtomics, // ATOMIC_STORE8_I32_A32 |
| 7515 | CEFBS_HasAtomics, // ATOMIC_STORE8_I32_A32_S |
| 7516 | CEFBS_HasAtomics, // ATOMIC_STORE8_I32_A64 |
| 7517 | CEFBS_HasAtomics, // ATOMIC_STORE8_I32_A64_S |
| 7518 | CEFBS_HasAtomics, // ATOMIC_STORE8_I64_A32 |
| 7519 | CEFBS_HasAtomics, // ATOMIC_STORE8_I64_A32_S |
| 7520 | CEFBS_HasAtomics, // ATOMIC_STORE8_I64_A64 |
| 7521 | CEFBS_HasAtomics, // ATOMIC_STORE8_I64_A64_S |
| 7522 | CEFBS_HasAtomics, // ATOMIC_STORE_I32_A32 |
| 7523 | CEFBS_HasAtomics, // ATOMIC_STORE_I32_A32_S |
| 7524 | CEFBS_HasAtomics, // ATOMIC_STORE_I32_A64 |
| 7525 | CEFBS_HasAtomics, // ATOMIC_STORE_I32_A64_S |
| 7526 | CEFBS_HasAtomics, // ATOMIC_STORE_I64_A32 |
| 7527 | CEFBS_HasAtomics, // ATOMIC_STORE_I64_A32_S |
| 7528 | CEFBS_HasAtomics, // ATOMIC_STORE_I64_A64 |
| 7529 | CEFBS_HasAtomics, // ATOMIC_STORE_I64_A64_S |
| 7530 | CEFBS_HasSIMD128, // AVGR_U_I16x8 |
| 7531 | CEFBS_HasSIMD128, // AVGR_U_I16x8_S |
| 7532 | CEFBS_HasSIMD128, // AVGR_U_I8x16 |
| 7533 | CEFBS_HasSIMD128, // AVGR_U_I8x16_S |
| 7534 | CEFBS_HasSIMD128, // BITMASK_I16x8 |
| 7535 | CEFBS_HasSIMD128, // BITMASK_I16x8_S |
| 7536 | CEFBS_HasSIMD128, // BITMASK_I32x4 |
| 7537 | CEFBS_HasSIMD128, // BITMASK_I32x4_S |
| 7538 | CEFBS_HasSIMD128, // BITMASK_I64x2 |
| 7539 | CEFBS_HasSIMD128, // BITMASK_I64x2_S |
| 7540 | CEFBS_HasSIMD128, // BITMASK_I8x16 |
| 7541 | CEFBS_HasSIMD128, // BITMASK_I8x16_S |
| 7542 | CEFBS_HasSIMD128, // BITSELECT |
| 7543 | CEFBS_HasSIMD128, // BITSELECT_S |
| 7544 | CEFBS_None, // BLOCK |
| 7545 | CEFBS_None, // BLOCK_S |
| 7546 | CEFBS_None, // BR |
| 7547 | CEFBS_None, // BR_IF |
| 7548 | CEFBS_None, // BR_IF_S |
| 7549 | CEFBS_None, // BR_S |
| 7550 | CEFBS_None, // BR_TABLE_I32 |
| 7551 | CEFBS_None, // BR_TABLE_I32_S |
| 7552 | CEFBS_None, // BR_TABLE_I64 |
| 7553 | CEFBS_None, // BR_TABLE_I64_S |
| 7554 | CEFBS_None, // BR_UNLESS |
| 7555 | CEFBS_None, // BR_UNLESS_S |
| 7556 | CEFBS_None, // CALL |
| 7557 | CEFBS_None, // CALL_INDIRECT |
| 7558 | CEFBS_None, // CALL_INDIRECT_S |
| 7559 | CEFBS_HasGC, // CALL_REF |
| 7560 | CEFBS_HasGC, // CALL_REF_S |
| 7561 | CEFBS_None, // CALL_S |
| 7562 | CEFBS_HasExceptionHandling, // CATCH |
| 7563 | CEFBS_HasExceptionHandling, // CATCH_ALL |
| 7564 | CEFBS_HasExceptionHandling, // CATCH_ALL_LEGACY |
| 7565 | CEFBS_HasExceptionHandling, // CATCH_ALL_LEGACY_S |
| 7566 | CEFBS_HasExceptionHandling, // CATCH_ALL_REF |
| 7567 | CEFBS_HasExceptionHandling, // CATCH_ALL_REF_S |
| 7568 | CEFBS_HasExceptionHandling, // CATCH_ALL_S |
| 7569 | CEFBS_HasExceptionHandling, // CATCH_LEGACY |
| 7570 | CEFBS_HasExceptionHandling, // CATCH_LEGACY_S |
| 7571 | CEFBS_HasExceptionHandling, // CATCH_REF |
| 7572 | CEFBS_HasExceptionHandling, // CATCH_REF_S |
| 7573 | CEFBS_HasExceptionHandling, // CATCH_S |
| 7574 | CEFBS_HasSIMD128_HasFP16, // CEIL_F16x8 |
| 7575 | CEFBS_HasSIMD128_HasFP16, // CEIL_F16x8_S |
| 7576 | CEFBS_None, // CEIL_F32 |
| 7577 | CEFBS_None, // CEIL_F32_S |
| 7578 | CEFBS_HasSIMD128, // CEIL_F32x4 |
| 7579 | CEFBS_HasSIMD128, // CEIL_F32x4_S |
| 7580 | CEFBS_None, // CEIL_F64 |
| 7581 | CEFBS_None, // CEIL_F64_S |
| 7582 | CEFBS_HasSIMD128, // CEIL_F64x2 |
| 7583 | CEFBS_HasSIMD128, // CEIL_F64x2_S |
| 7584 | CEFBS_None, // CLZ_I32 |
| 7585 | CEFBS_None, // CLZ_I32_S |
| 7586 | CEFBS_None, // CLZ_I64 |
| 7587 | CEFBS_None, // CLZ_I64_S |
| 7588 | CEFBS_None, // CONST_F32 |
| 7589 | CEFBS_None, // CONST_F32_S |
| 7590 | CEFBS_None, // CONST_F64 |
| 7591 | CEFBS_None, // CONST_F64_S |
| 7592 | CEFBS_None, // CONST_I32 |
| 7593 | CEFBS_None, // CONST_I32_S |
| 7594 | CEFBS_None, // CONST_I64 |
| 7595 | CEFBS_None, // CONST_I64_S |
| 7596 | CEFBS_HasSIMD128, // CONST_V128_F32x4 |
| 7597 | CEFBS_HasSIMD128, // CONST_V128_F32x4_S |
| 7598 | CEFBS_HasSIMD128, // CONST_V128_F64x2 |
| 7599 | CEFBS_HasSIMD128, // CONST_V128_F64x2_S |
| 7600 | CEFBS_HasSIMD128, // CONST_V128_I16x8 |
| 7601 | CEFBS_HasSIMD128, // CONST_V128_I16x8_S |
| 7602 | CEFBS_HasSIMD128, // CONST_V128_I32x4 |
| 7603 | CEFBS_HasSIMD128, // CONST_V128_I32x4_S |
| 7604 | CEFBS_HasSIMD128, // CONST_V128_I64x2 |
| 7605 | CEFBS_HasSIMD128, // CONST_V128_I64x2_S |
| 7606 | CEFBS_HasSIMD128, // CONST_V128_I8x16 |
| 7607 | CEFBS_HasSIMD128, // CONST_V128_I8x16_S |
| 7608 | CEFBS_None, // COPYSIGN_F32 |
| 7609 | CEFBS_None, // COPYSIGN_F32_S |
| 7610 | CEFBS_None, // COPYSIGN_F64 |
| 7611 | CEFBS_None, // COPYSIGN_F64_S |
| 7612 | CEFBS_HasReferenceTypes_HasExceptionHandling, // COPY_EXNREF |
| 7613 | CEFBS_HasReferenceTypes_HasExceptionHandling, // COPY_EXNREF_S |
| 7614 | CEFBS_HasReferenceTypes, // COPY_EXTERNREF |
| 7615 | CEFBS_HasReferenceTypes, // COPY_EXTERNREF_S |
| 7616 | CEFBS_None, // COPY_F32 |
| 7617 | CEFBS_None, // COPY_F32_S |
| 7618 | CEFBS_None, // COPY_F64 |
| 7619 | CEFBS_None, // COPY_F64_S |
| 7620 | CEFBS_HasReferenceTypes, // COPY_FUNCREF |
| 7621 | CEFBS_HasReferenceTypes, // COPY_FUNCREF_S |
| 7622 | CEFBS_None, // COPY_I32 |
| 7623 | CEFBS_None, // COPY_I32_S |
| 7624 | CEFBS_None, // COPY_I64 |
| 7625 | CEFBS_None, // COPY_I64_S |
| 7626 | CEFBS_HasSIMD128, // COPY_V128 |
| 7627 | CEFBS_HasSIMD128, // COPY_V128_S |
| 7628 | CEFBS_None, // CTZ_I32 |
| 7629 | CEFBS_None, // CTZ_I32_S |
| 7630 | CEFBS_None, // CTZ_I64 |
| 7631 | CEFBS_None, // CTZ_I64_S |
| 7632 | CEFBS_HasBulkMemoryOpt, // DATA_DROP |
| 7633 | CEFBS_HasBulkMemoryOpt, // DATA_DROP_S |
| 7634 | CEFBS_None, // DEBUG_UNREACHABLE |
| 7635 | CEFBS_None, // DEBUG_UNREACHABLE_S |
| 7636 | CEFBS_HasExceptionHandling, // DELEGATE |
| 7637 | CEFBS_HasExceptionHandling, // DELEGATE_S |
| 7638 | CEFBS_HasSIMD128_HasFP16, // DIV_F16x8 |
| 7639 | CEFBS_HasSIMD128_HasFP16, // DIV_F16x8_S |
| 7640 | CEFBS_None, // DIV_F32 |
| 7641 | CEFBS_None, // DIV_F32_S |
| 7642 | CEFBS_HasSIMD128, // DIV_F32x4 |
| 7643 | CEFBS_HasSIMD128, // DIV_F32x4_S |
| 7644 | CEFBS_None, // DIV_F64 |
| 7645 | CEFBS_None, // DIV_F64_S |
| 7646 | CEFBS_HasSIMD128, // DIV_F64x2 |
| 7647 | CEFBS_HasSIMD128, // DIV_F64x2_S |
| 7648 | CEFBS_None, // DIV_S_I32 |
| 7649 | CEFBS_None, // DIV_S_I32_S |
| 7650 | CEFBS_None, // DIV_S_I64 |
| 7651 | CEFBS_None, // DIV_S_I64_S |
| 7652 | CEFBS_None, // DIV_U_I32 |
| 7653 | CEFBS_None, // DIV_U_I32_S |
| 7654 | CEFBS_None, // DIV_U_I64 |
| 7655 | CEFBS_None, // DIV_U_I64_S |
| 7656 | CEFBS_HasSIMD128, // DOT |
| 7657 | CEFBS_HasSIMD128, // DOT_S |
| 7658 | CEFBS_HasReferenceTypes_HasExceptionHandling, // DROP_EXNREF |
| 7659 | CEFBS_HasReferenceTypes_HasExceptionHandling, // DROP_EXNREF_S |
| 7660 | CEFBS_HasReferenceTypes, // DROP_EXTERNREF |
| 7661 | CEFBS_HasReferenceTypes, // DROP_EXTERNREF_S |
| 7662 | CEFBS_None, // DROP_F32 |
| 7663 | CEFBS_None, // DROP_F32_S |
| 7664 | CEFBS_None, // DROP_F64 |
| 7665 | CEFBS_None, // DROP_F64_S |
| 7666 | CEFBS_HasReferenceTypes, // DROP_FUNCREF |
| 7667 | CEFBS_HasReferenceTypes, // DROP_FUNCREF_S |
| 7668 | CEFBS_None, // DROP_I32 |
| 7669 | CEFBS_None, // DROP_I32_S |
| 7670 | CEFBS_None, // DROP_I64 |
| 7671 | CEFBS_None, // DROP_I64_S |
| 7672 | CEFBS_HasSIMD128, // DROP_V128 |
| 7673 | CEFBS_HasSIMD128, // DROP_V128_S |
| 7674 | CEFBS_None, // ELSE |
| 7675 | CEFBS_None, // ELSE_S |
| 7676 | CEFBS_None, // END |
| 7677 | CEFBS_None, // END_BLOCK |
| 7678 | CEFBS_None, // END_BLOCK_S |
| 7679 | CEFBS_None, // END_FUNCTION |
| 7680 | CEFBS_None, // END_FUNCTION_S |
| 7681 | CEFBS_None, // END_IF |
| 7682 | CEFBS_None, // END_IF_S |
| 7683 | CEFBS_None, // END_LOOP |
| 7684 | CEFBS_None, // END_LOOP_S |
| 7685 | CEFBS_None, // END_S |
| 7686 | CEFBS_HasExceptionHandling, // END_TRY |
| 7687 | CEFBS_HasExceptionHandling, // END_TRY_S |
| 7688 | CEFBS_HasExceptionHandling, // END_TRY_TABLE |
| 7689 | CEFBS_HasExceptionHandling, // END_TRY_TABLE_S |
| 7690 | CEFBS_None, // EQZ_I32 |
| 7691 | CEFBS_None, // EQZ_I32_S |
| 7692 | CEFBS_None, // EQZ_I64 |
| 7693 | CEFBS_None, // EQZ_I64_S |
| 7694 | CEFBS_HasSIMD128_HasFP16, // EQ_F16x8 |
| 7695 | CEFBS_HasSIMD128_HasFP16, // EQ_F16x8_S |
| 7696 | CEFBS_None, // EQ_F32 |
| 7697 | CEFBS_None, // EQ_F32_S |
| 7698 | CEFBS_HasSIMD128, // EQ_F32x4 |
| 7699 | CEFBS_HasSIMD128, // EQ_F32x4_S |
| 7700 | CEFBS_None, // EQ_F64 |
| 7701 | CEFBS_None, // EQ_F64_S |
| 7702 | CEFBS_HasSIMD128, // EQ_F64x2 |
| 7703 | CEFBS_HasSIMD128, // EQ_F64x2_S |
| 7704 | CEFBS_HasSIMD128, // EQ_I16x8 |
| 7705 | CEFBS_HasSIMD128, // EQ_I16x8_S |
| 7706 | CEFBS_None, // EQ_I32 |
| 7707 | CEFBS_None, // EQ_I32_S |
| 7708 | CEFBS_HasSIMD128, // EQ_I32x4 |
| 7709 | CEFBS_HasSIMD128, // EQ_I32x4_S |
| 7710 | CEFBS_None, // EQ_I64 |
| 7711 | CEFBS_None, // EQ_I64_S |
| 7712 | CEFBS_HasSIMD128, // EQ_I64x2 |
| 7713 | CEFBS_HasSIMD128, // EQ_I64x2_S |
| 7714 | CEFBS_HasSIMD128, // EQ_I8x16 |
| 7715 | CEFBS_HasSIMD128, // EQ_I8x16_S |
| 7716 | CEFBS_HasSIMD128, // EXTMUL_HIGH_S_I16x8 |
| 7717 | CEFBS_HasSIMD128, // EXTMUL_HIGH_S_I16x8_S |
| 7718 | CEFBS_HasSIMD128, // EXTMUL_HIGH_S_I32x4 |
| 7719 | CEFBS_HasSIMD128, // EXTMUL_HIGH_S_I32x4_S |
| 7720 | CEFBS_HasSIMD128, // EXTMUL_HIGH_S_I64x2 |
| 7721 | CEFBS_HasSIMD128, // EXTMUL_HIGH_S_I64x2_S |
| 7722 | CEFBS_HasSIMD128, // EXTMUL_HIGH_U_I16x8 |
| 7723 | CEFBS_HasSIMD128, // EXTMUL_HIGH_U_I16x8_S |
| 7724 | CEFBS_HasSIMD128, // EXTMUL_HIGH_U_I32x4 |
| 7725 | CEFBS_HasSIMD128, // EXTMUL_HIGH_U_I32x4_S |
| 7726 | CEFBS_HasSIMD128, // EXTMUL_HIGH_U_I64x2 |
| 7727 | CEFBS_HasSIMD128, // EXTMUL_HIGH_U_I64x2_S |
| 7728 | CEFBS_HasSIMD128, // EXTMUL_LOW_S_I16x8 |
| 7729 | CEFBS_HasSIMD128, // EXTMUL_LOW_S_I16x8_S |
| 7730 | CEFBS_HasSIMD128, // EXTMUL_LOW_S_I32x4 |
| 7731 | CEFBS_HasSIMD128, // EXTMUL_LOW_S_I32x4_S |
| 7732 | CEFBS_HasSIMD128, // EXTMUL_LOW_S_I64x2 |
| 7733 | CEFBS_HasSIMD128, // EXTMUL_LOW_S_I64x2_S |
| 7734 | CEFBS_HasSIMD128, // EXTMUL_LOW_U_I16x8 |
| 7735 | CEFBS_HasSIMD128, // EXTMUL_LOW_U_I16x8_S |
| 7736 | CEFBS_HasSIMD128, // EXTMUL_LOW_U_I32x4 |
| 7737 | CEFBS_HasSIMD128, // EXTMUL_LOW_U_I32x4_S |
| 7738 | CEFBS_HasSIMD128, // EXTMUL_LOW_U_I64x2 |
| 7739 | CEFBS_HasSIMD128, // EXTMUL_LOW_U_I64x2_S |
| 7740 | CEFBS_HasFP16, // EXTRACT_LANE_F16x8 |
| 7741 | CEFBS_HasFP16, // EXTRACT_LANE_F16x8_S |
| 7742 | CEFBS_HasSIMD128, // EXTRACT_LANE_F32x4 |
| 7743 | CEFBS_HasSIMD128, // EXTRACT_LANE_F32x4_S |
| 7744 | CEFBS_HasSIMD128, // EXTRACT_LANE_F64x2 |
| 7745 | CEFBS_HasSIMD128, // EXTRACT_LANE_F64x2_S |
| 7746 | CEFBS_HasSIMD128, // EXTRACT_LANE_I16x8_s |
| 7747 | CEFBS_HasSIMD128, // EXTRACT_LANE_I16x8_s_S |
| 7748 | CEFBS_HasSIMD128, // EXTRACT_LANE_I16x8_u |
| 7749 | CEFBS_HasSIMD128, // EXTRACT_LANE_I16x8_u_S |
| 7750 | CEFBS_HasSIMD128, // EXTRACT_LANE_I32x4 |
| 7751 | CEFBS_HasSIMD128, // EXTRACT_LANE_I32x4_S |
| 7752 | CEFBS_HasSIMD128, // EXTRACT_LANE_I64x2 |
| 7753 | CEFBS_HasSIMD128, // EXTRACT_LANE_I64x2_S |
| 7754 | CEFBS_HasSIMD128, // EXTRACT_LANE_I8x16_s |
| 7755 | CEFBS_HasSIMD128, // EXTRACT_LANE_I8x16_s_S |
| 7756 | CEFBS_HasSIMD128, // EXTRACT_LANE_I8x16_u |
| 7757 | CEFBS_HasSIMD128, // EXTRACT_LANE_I8x16_u_S |
| 7758 | CEFBS_None, // F32_CONVERT_S_I32 |
| 7759 | CEFBS_None, // F32_CONVERT_S_I32_S |
| 7760 | CEFBS_None, // F32_CONVERT_S_I64 |
| 7761 | CEFBS_None, // F32_CONVERT_S_I64_S |
| 7762 | CEFBS_None, // F32_CONVERT_U_I32 |
| 7763 | CEFBS_None, // F32_CONVERT_U_I32_S |
| 7764 | CEFBS_None, // F32_CONVERT_U_I64 |
| 7765 | CEFBS_None, // F32_CONVERT_U_I64_S |
| 7766 | CEFBS_None, // F32_DEMOTE_F64 |
| 7767 | CEFBS_None, // F32_DEMOTE_F64_S |
| 7768 | CEFBS_None, // F32_REINTERPRET_I32 |
| 7769 | CEFBS_None, // F32_REINTERPRET_I32_S |
| 7770 | CEFBS_None, // F64_CONVERT_S_I32 |
| 7771 | CEFBS_None, // F64_CONVERT_S_I32_S |
| 7772 | CEFBS_None, // F64_CONVERT_S_I64 |
| 7773 | CEFBS_None, // F64_CONVERT_S_I64_S |
| 7774 | CEFBS_None, // F64_CONVERT_U_I32 |
| 7775 | CEFBS_None, // F64_CONVERT_U_I32_S |
| 7776 | CEFBS_None, // F64_CONVERT_U_I64 |
| 7777 | CEFBS_None, // F64_CONVERT_U_I64_S |
| 7778 | CEFBS_None, // F64_PROMOTE_F32 |
| 7779 | CEFBS_None, // F64_PROMOTE_F32_S |
| 7780 | CEFBS_None, // F64_REINTERPRET_I64 |
| 7781 | CEFBS_None, // F64_REINTERPRET_I64_S |
| 7782 | CEFBS_None, // FALLTHROUGH_RETURN |
| 7783 | CEFBS_None, // FALLTHROUGH_RETURN_S |
| 7784 | CEFBS_HasSIMD128_HasFP16, // FLOOR_F16x8 |
| 7785 | CEFBS_HasSIMD128_HasFP16, // FLOOR_F16x8_S |
| 7786 | CEFBS_None, // FLOOR_F32 |
| 7787 | CEFBS_None, // FLOOR_F32_S |
| 7788 | CEFBS_HasSIMD128, // FLOOR_F32x4 |
| 7789 | CEFBS_HasSIMD128, // FLOOR_F32x4_S |
| 7790 | CEFBS_None, // FLOOR_F64 |
| 7791 | CEFBS_None, // FLOOR_F64_S |
| 7792 | CEFBS_HasSIMD128, // FLOOR_F64x2 |
| 7793 | CEFBS_HasSIMD128, // FLOOR_F64x2_S |
| 7794 | CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I32_F32 |
| 7795 | CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I32_F32_S |
| 7796 | CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I32_F64 |
| 7797 | CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I32_F64_S |
| 7798 | CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I64_F32 |
| 7799 | CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I64_F32_S |
| 7800 | CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I64_F64 |
| 7801 | CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I64_F64_S |
| 7802 | CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I32_F32 |
| 7803 | CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I32_F32_S |
| 7804 | CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I32_F64 |
| 7805 | CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I32_F64_S |
| 7806 | CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I64_F32 |
| 7807 | CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I64_F32_S |
| 7808 | CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I64_F64 |
| 7809 | CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I64_F64_S |
| 7810 | CEFBS_HasSIMD128_HasFP16, // GE_F16x8 |
| 7811 | CEFBS_HasSIMD128_HasFP16, // GE_F16x8_S |
| 7812 | CEFBS_None, // GE_F32 |
| 7813 | CEFBS_None, // GE_F32_S |
| 7814 | CEFBS_HasSIMD128, // GE_F32x4 |
| 7815 | CEFBS_HasSIMD128, // GE_F32x4_S |
| 7816 | CEFBS_None, // GE_F64 |
| 7817 | CEFBS_None, // GE_F64_S |
| 7818 | CEFBS_HasSIMD128, // GE_F64x2 |
| 7819 | CEFBS_HasSIMD128, // GE_F64x2_S |
| 7820 | CEFBS_HasSIMD128, // GE_S_I16x8 |
| 7821 | CEFBS_HasSIMD128, // GE_S_I16x8_S |
| 7822 | CEFBS_None, // GE_S_I32 |
| 7823 | CEFBS_None, // GE_S_I32_S |
| 7824 | CEFBS_HasSIMD128, // GE_S_I32x4 |
| 7825 | CEFBS_HasSIMD128, // GE_S_I32x4_S |
| 7826 | CEFBS_None, // GE_S_I64 |
| 7827 | CEFBS_None, // GE_S_I64_S |
| 7828 | CEFBS_HasSIMD128, // GE_S_I64x2 |
| 7829 | CEFBS_HasSIMD128, // GE_S_I64x2_S |
| 7830 | CEFBS_HasSIMD128, // GE_S_I8x16 |
| 7831 | CEFBS_HasSIMD128, // GE_S_I8x16_S |
| 7832 | CEFBS_HasSIMD128, // GE_U_I16x8 |
| 7833 | CEFBS_HasSIMD128, // GE_U_I16x8_S |
| 7834 | CEFBS_None, // GE_U_I32 |
| 7835 | CEFBS_None, // GE_U_I32_S |
| 7836 | CEFBS_HasSIMD128, // GE_U_I32x4 |
| 7837 | CEFBS_HasSIMD128, // GE_U_I32x4_S |
| 7838 | CEFBS_None, // GE_U_I64 |
| 7839 | CEFBS_None, // GE_U_I64_S |
| 7840 | CEFBS_HasSIMD128, // GE_U_I8x16 |
| 7841 | CEFBS_HasSIMD128, // GE_U_I8x16_S |
| 7842 | CEFBS_HasReferenceTypes_HasExceptionHandling, // GLOBAL_GET_EXNREF |
| 7843 | CEFBS_HasReferenceTypes_HasExceptionHandling, // GLOBAL_GET_EXNREF_S |
| 7844 | CEFBS_HasReferenceTypes, // GLOBAL_GET_EXTERNREF |
| 7845 | CEFBS_HasReferenceTypes, // GLOBAL_GET_EXTERNREF_S |
| 7846 | CEFBS_None, // GLOBAL_GET_F32 |
| 7847 | CEFBS_None, // GLOBAL_GET_F32_S |
| 7848 | CEFBS_None, // GLOBAL_GET_F64 |
| 7849 | CEFBS_None, // GLOBAL_GET_F64_S |
| 7850 | CEFBS_HasReferenceTypes, // GLOBAL_GET_FUNCREF |
| 7851 | CEFBS_HasReferenceTypes, // GLOBAL_GET_FUNCREF_S |
| 7852 | CEFBS_None, // GLOBAL_GET_I32 |
| 7853 | CEFBS_None, // GLOBAL_GET_I32_S |
| 7854 | CEFBS_None, // GLOBAL_GET_I64 |
| 7855 | CEFBS_None, // GLOBAL_GET_I64_S |
| 7856 | CEFBS_HasSIMD128, // GLOBAL_GET_V128 |
| 7857 | CEFBS_HasSIMD128, // GLOBAL_GET_V128_S |
| 7858 | CEFBS_HasReferenceTypes_HasExceptionHandling, // GLOBAL_SET_EXNREF |
| 7859 | CEFBS_HasReferenceTypes_HasExceptionHandling, // GLOBAL_SET_EXNREF_S |
| 7860 | CEFBS_HasReferenceTypes, // GLOBAL_SET_EXTERNREF |
| 7861 | CEFBS_HasReferenceTypes, // GLOBAL_SET_EXTERNREF_S |
| 7862 | CEFBS_None, // GLOBAL_SET_F32 |
| 7863 | CEFBS_None, // GLOBAL_SET_F32_S |
| 7864 | CEFBS_None, // GLOBAL_SET_F64 |
| 7865 | CEFBS_None, // GLOBAL_SET_F64_S |
| 7866 | CEFBS_HasReferenceTypes, // GLOBAL_SET_FUNCREF |
| 7867 | CEFBS_HasReferenceTypes, // GLOBAL_SET_FUNCREF_S |
| 7868 | CEFBS_None, // GLOBAL_SET_I32 |
| 7869 | CEFBS_None, // GLOBAL_SET_I32_S |
| 7870 | CEFBS_None, // GLOBAL_SET_I64 |
| 7871 | CEFBS_None, // GLOBAL_SET_I64_S |
| 7872 | CEFBS_HasSIMD128, // GLOBAL_SET_V128 |
| 7873 | CEFBS_HasSIMD128, // GLOBAL_SET_V128_S |
| 7874 | CEFBS_HasSIMD128_HasFP16, // GT_F16x8 |
| 7875 | CEFBS_HasSIMD128_HasFP16, // GT_F16x8_S |
| 7876 | CEFBS_None, // GT_F32 |
| 7877 | CEFBS_None, // GT_F32_S |
| 7878 | CEFBS_HasSIMD128, // GT_F32x4 |
| 7879 | CEFBS_HasSIMD128, // GT_F32x4_S |
| 7880 | CEFBS_None, // GT_F64 |
| 7881 | CEFBS_None, // GT_F64_S |
| 7882 | CEFBS_HasSIMD128, // GT_F64x2 |
| 7883 | CEFBS_HasSIMD128, // GT_F64x2_S |
| 7884 | CEFBS_HasSIMD128, // GT_S_I16x8 |
| 7885 | CEFBS_HasSIMD128, // GT_S_I16x8_S |
| 7886 | CEFBS_None, // GT_S_I32 |
| 7887 | CEFBS_None, // GT_S_I32_S |
| 7888 | CEFBS_HasSIMD128, // GT_S_I32x4 |
| 7889 | CEFBS_HasSIMD128, // GT_S_I32x4_S |
| 7890 | CEFBS_None, // GT_S_I64 |
| 7891 | CEFBS_None, // GT_S_I64_S |
| 7892 | CEFBS_HasSIMD128, // GT_S_I64x2 |
| 7893 | CEFBS_HasSIMD128, // GT_S_I64x2_S |
| 7894 | CEFBS_HasSIMD128, // GT_S_I8x16 |
| 7895 | CEFBS_HasSIMD128, // GT_S_I8x16_S |
| 7896 | CEFBS_HasSIMD128, // GT_U_I16x8 |
| 7897 | CEFBS_HasSIMD128, // GT_U_I16x8_S |
| 7898 | CEFBS_None, // GT_U_I32 |
| 7899 | CEFBS_None, // GT_U_I32_S |
| 7900 | CEFBS_HasSIMD128, // GT_U_I32x4 |
| 7901 | CEFBS_HasSIMD128, // GT_U_I32x4_S |
| 7902 | CEFBS_None, // GT_U_I64 |
| 7903 | CEFBS_None, // GT_U_I64_S |
| 7904 | CEFBS_HasSIMD128, // GT_U_I8x16 |
| 7905 | CEFBS_HasSIMD128, // GT_U_I8x16_S |
| 7906 | CEFBS_HasSignExt, // I32_EXTEND16_S_I32 |
| 7907 | CEFBS_HasSignExt, // I32_EXTEND16_S_I32_S |
| 7908 | CEFBS_HasSignExt, // I32_EXTEND8_S_I32 |
| 7909 | CEFBS_HasSignExt, // I32_EXTEND8_S_I32_S |
| 7910 | CEFBS_None, // I32_REINTERPRET_F32 |
| 7911 | CEFBS_None, // I32_REINTERPRET_F32_S |
| 7912 | CEFBS_None, // I32_TRUNC_S_F32 |
| 7913 | CEFBS_None, // I32_TRUNC_S_F32_S |
| 7914 | CEFBS_None, // I32_TRUNC_S_F64 |
| 7915 | CEFBS_None, // I32_TRUNC_S_F64_S |
| 7916 | CEFBS_HasNontrappingFPToInt, // I32_TRUNC_S_SAT_F32 |
| 7917 | CEFBS_HasNontrappingFPToInt, // I32_TRUNC_S_SAT_F32_S |
| 7918 | CEFBS_HasNontrappingFPToInt, // I32_TRUNC_S_SAT_F64 |
| 7919 | CEFBS_HasNontrappingFPToInt, // I32_TRUNC_S_SAT_F64_S |
| 7920 | CEFBS_None, // I32_TRUNC_U_F32 |
| 7921 | CEFBS_None, // I32_TRUNC_U_F32_S |
| 7922 | CEFBS_None, // I32_TRUNC_U_F64 |
| 7923 | CEFBS_None, // I32_TRUNC_U_F64_S |
| 7924 | CEFBS_HasNontrappingFPToInt, // I32_TRUNC_U_SAT_F32 |
| 7925 | CEFBS_HasNontrappingFPToInt, // I32_TRUNC_U_SAT_F32_S |
| 7926 | CEFBS_HasNontrappingFPToInt, // I32_TRUNC_U_SAT_F64 |
| 7927 | CEFBS_HasNontrappingFPToInt, // I32_TRUNC_U_SAT_F64_S |
| 7928 | CEFBS_None, // I32_WRAP_I64 |
| 7929 | CEFBS_None, // I32_WRAP_I64_S |
| 7930 | CEFBS_HasWideArithmetic, // I64_ADD128 |
| 7931 | CEFBS_HasWideArithmetic, // I64_ADD128_S |
| 7932 | CEFBS_HasSignExt, // I64_EXTEND16_S_I64 |
| 7933 | CEFBS_HasSignExt, // I64_EXTEND16_S_I64_S |
| 7934 | CEFBS_HasSignExt, // I64_EXTEND32_S_I64 |
| 7935 | CEFBS_HasSignExt, // I64_EXTEND32_S_I64_S |
| 7936 | CEFBS_HasSignExt, // I64_EXTEND8_S_I64 |
| 7937 | CEFBS_HasSignExt, // I64_EXTEND8_S_I64_S |
| 7938 | CEFBS_None, // I64_EXTEND_S_I32 |
| 7939 | CEFBS_None, // I64_EXTEND_S_I32_S |
| 7940 | CEFBS_None, // I64_EXTEND_U_I32 |
| 7941 | CEFBS_None, // I64_EXTEND_U_I32_S |
| 7942 | CEFBS_HasWideArithmetic, // I64_MUL_WIDE_S |
| 7943 | CEFBS_HasWideArithmetic, // I64_MUL_WIDE_S_S |
| 7944 | CEFBS_HasWideArithmetic, // I64_MUL_WIDE_U |
| 7945 | CEFBS_HasWideArithmetic, // I64_MUL_WIDE_U_S |
| 7946 | CEFBS_None, // I64_REINTERPRET_F64 |
| 7947 | CEFBS_None, // I64_REINTERPRET_F64_S |
| 7948 | CEFBS_HasWideArithmetic, // I64_SUB128 |
| 7949 | CEFBS_HasWideArithmetic, // I64_SUB128_S |
| 7950 | CEFBS_None, // I64_TRUNC_S_F32 |
| 7951 | CEFBS_None, // I64_TRUNC_S_F32_S |
| 7952 | CEFBS_None, // I64_TRUNC_S_F64 |
| 7953 | CEFBS_None, // I64_TRUNC_S_F64_S |
| 7954 | CEFBS_HasNontrappingFPToInt, // I64_TRUNC_S_SAT_F32 |
| 7955 | CEFBS_HasNontrappingFPToInt, // I64_TRUNC_S_SAT_F32_S |
| 7956 | CEFBS_HasNontrappingFPToInt, // I64_TRUNC_S_SAT_F64 |
| 7957 | CEFBS_HasNontrappingFPToInt, // I64_TRUNC_S_SAT_F64_S |
| 7958 | CEFBS_None, // I64_TRUNC_U_F32 |
| 7959 | CEFBS_None, // I64_TRUNC_U_F32_S |
| 7960 | CEFBS_None, // I64_TRUNC_U_F64 |
| 7961 | CEFBS_None, // I64_TRUNC_U_F64_S |
| 7962 | CEFBS_HasNontrappingFPToInt, // I64_TRUNC_U_SAT_F32 |
| 7963 | CEFBS_HasNontrappingFPToInt, // I64_TRUNC_U_SAT_F32_S |
| 7964 | CEFBS_HasNontrappingFPToInt, // I64_TRUNC_U_SAT_F64 |
| 7965 | CEFBS_HasNontrappingFPToInt, // I64_TRUNC_U_SAT_F64_S |
| 7966 | CEFBS_None, // IF |
| 7967 | CEFBS_None, // IF_S |
| 7968 | CEFBS_HasRelaxedSIMD, // LANESELECT_I16x8 |
| 7969 | CEFBS_HasRelaxedSIMD, // LANESELECT_I16x8_S |
| 7970 | CEFBS_HasRelaxedSIMD, // LANESELECT_I32x4 |
| 7971 | CEFBS_HasRelaxedSIMD, // LANESELECT_I32x4_S |
| 7972 | CEFBS_HasRelaxedSIMD, // LANESELECT_I64x2 |
| 7973 | CEFBS_HasRelaxedSIMD, // LANESELECT_I64x2_S |
| 7974 | CEFBS_HasRelaxedSIMD, // LANESELECT_I8x16 |
| 7975 | CEFBS_HasRelaxedSIMD, // LANESELECT_I8x16_S |
| 7976 | CEFBS_HasSIMD128_HasFP16, // LE_F16x8 |
| 7977 | CEFBS_HasSIMD128_HasFP16, // LE_F16x8_S |
| 7978 | CEFBS_None, // LE_F32 |
| 7979 | CEFBS_None, // LE_F32_S |
| 7980 | CEFBS_HasSIMD128, // LE_F32x4 |
| 7981 | CEFBS_HasSIMD128, // LE_F32x4_S |
| 7982 | CEFBS_None, // LE_F64 |
| 7983 | CEFBS_None, // LE_F64_S |
| 7984 | CEFBS_HasSIMD128, // LE_F64x2 |
| 7985 | CEFBS_HasSIMD128, // LE_F64x2_S |
| 7986 | CEFBS_HasSIMD128, // LE_S_I16x8 |
| 7987 | CEFBS_HasSIMD128, // LE_S_I16x8_S |
| 7988 | CEFBS_None, // LE_S_I32 |
| 7989 | CEFBS_None, // LE_S_I32_S |
| 7990 | CEFBS_HasSIMD128, // LE_S_I32x4 |
| 7991 | CEFBS_HasSIMD128, // LE_S_I32x4_S |
| 7992 | CEFBS_None, // LE_S_I64 |
| 7993 | CEFBS_None, // LE_S_I64_S |
| 7994 | CEFBS_HasSIMD128, // LE_S_I64x2 |
| 7995 | CEFBS_HasSIMD128, // LE_S_I64x2_S |
| 7996 | CEFBS_HasSIMD128, // LE_S_I8x16 |
| 7997 | CEFBS_HasSIMD128, // LE_S_I8x16_S |
| 7998 | CEFBS_HasSIMD128, // LE_U_I16x8 |
| 7999 | CEFBS_HasSIMD128, // LE_U_I16x8_S |
| 8000 | CEFBS_None, // LE_U_I32 |
| 8001 | CEFBS_None, // LE_U_I32_S |
| 8002 | CEFBS_HasSIMD128, // LE_U_I32x4 |
| 8003 | CEFBS_HasSIMD128, // LE_U_I32x4_S |
| 8004 | CEFBS_None, // LE_U_I64 |
| 8005 | CEFBS_None, // LE_U_I64_S |
| 8006 | CEFBS_HasSIMD128, // LE_U_I8x16 |
| 8007 | CEFBS_HasSIMD128, // LE_U_I8x16_S |
| 8008 | CEFBS_HasSIMD128, // LOAD16_SPLAT_A32 |
| 8009 | CEFBS_HasSIMD128, // LOAD16_SPLAT_A32_S |
| 8010 | CEFBS_HasSIMD128, // LOAD16_SPLAT_A64 |
| 8011 | CEFBS_HasSIMD128, // LOAD16_SPLAT_A64_S |
| 8012 | CEFBS_None, // LOAD16_S_I32_A32 |
| 8013 | CEFBS_None, // LOAD16_S_I32_A32_S |
| 8014 | CEFBS_None, // LOAD16_S_I32_A64 |
| 8015 | CEFBS_None, // LOAD16_S_I32_A64_S |
| 8016 | CEFBS_None, // LOAD16_S_I64_A32 |
| 8017 | CEFBS_None, // LOAD16_S_I64_A32_S |
| 8018 | CEFBS_None, // LOAD16_S_I64_A64 |
| 8019 | CEFBS_None, // LOAD16_S_I64_A64_S |
| 8020 | CEFBS_None, // LOAD16_U_I32_A32 |
| 8021 | CEFBS_None, // LOAD16_U_I32_A32_S |
| 8022 | CEFBS_None, // LOAD16_U_I32_A64 |
| 8023 | CEFBS_None, // LOAD16_U_I32_A64_S |
| 8024 | CEFBS_None, // LOAD16_U_I64_A32 |
| 8025 | CEFBS_None, // LOAD16_U_I64_A32_S |
| 8026 | CEFBS_None, // LOAD16_U_I64_A64 |
| 8027 | CEFBS_None, // LOAD16_U_I64_A64_S |
| 8028 | CEFBS_HasSIMD128, // LOAD32_SPLAT_A32 |
| 8029 | CEFBS_HasSIMD128, // LOAD32_SPLAT_A32_S |
| 8030 | CEFBS_HasSIMD128, // LOAD32_SPLAT_A64 |
| 8031 | CEFBS_HasSIMD128, // LOAD32_SPLAT_A64_S |
| 8032 | CEFBS_None, // LOAD32_S_I64_A32 |
| 8033 | CEFBS_None, // LOAD32_S_I64_A32_S |
| 8034 | CEFBS_None, // LOAD32_S_I64_A64 |
| 8035 | CEFBS_None, // LOAD32_S_I64_A64_S |
| 8036 | CEFBS_None, // LOAD32_U_I64_A32 |
| 8037 | CEFBS_None, // LOAD32_U_I64_A32_S |
| 8038 | CEFBS_None, // LOAD32_U_I64_A64 |
| 8039 | CEFBS_None, // LOAD32_U_I64_A64_S |
| 8040 | CEFBS_HasSIMD128, // LOAD64_SPLAT_A32 |
| 8041 | CEFBS_HasSIMD128, // LOAD64_SPLAT_A32_S |
| 8042 | CEFBS_HasSIMD128, // LOAD64_SPLAT_A64 |
| 8043 | CEFBS_HasSIMD128, // LOAD64_SPLAT_A64_S |
| 8044 | CEFBS_HasSIMD128, // LOAD8_SPLAT_A32 |
| 8045 | CEFBS_HasSIMD128, // LOAD8_SPLAT_A32_S |
| 8046 | CEFBS_HasSIMD128, // LOAD8_SPLAT_A64 |
| 8047 | CEFBS_HasSIMD128, // LOAD8_SPLAT_A64_S |
| 8048 | CEFBS_None, // LOAD8_S_I32_A32 |
| 8049 | CEFBS_None, // LOAD8_S_I32_A32_S |
| 8050 | CEFBS_None, // LOAD8_S_I32_A64 |
| 8051 | CEFBS_None, // LOAD8_S_I32_A64_S |
| 8052 | CEFBS_None, // LOAD8_S_I64_A32 |
| 8053 | CEFBS_None, // LOAD8_S_I64_A32_S |
| 8054 | CEFBS_None, // LOAD8_S_I64_A64 |
| 8055 | CEFBS_None, // LOAD8_S_I64_A64_S |
| 8056 | CEFBS_None, // LOAD8_U_I32_A32 |
| 8057 | CEFBS_None, // LOAD8_U_I32_A32_S |
| 8058 | CEFBS_None, // LOAD8_U_I32_A64 |
| 8059 | CEFBS_None, // LOAD8_U_I32_A64_S |
| 8060 | CEFBS_None, // LOAD8_U_I64_A32 |
| 8061 | CEFBS_None, // LOAD8_U_I64_A32_S |
| 8062 | CEFBS_None, // LOAD8_U_I64_A64 |
| 8063 | CEFBS_None, // LOAD8_U_I64_A64_S |
| 8064 | CEFBS_HasSIMD128, // LOAD_EXTEND_S_I16x8_A32 |
| 8065 | CEFBS_HasSIMD128, // LOAD_EXTEND_S_I16x8_A32_S |
| 8066 | CEFBS_HasSIMD128, // LOAD_EXTEND_S_I16x8_A64 |
| 8067 | CEFBS_HasSIMD128, // LOAD_EXTEND_S_I16x8_A64_S |
| 8068 | CEFBS_HasSIMD128, // LOAD_EXTEND_S_I32x4_A32 |
| 8069 | CEFBS_HasSIMD128, // LOAD_EXTEND_S_I32x4_A32_S |
| 8070 | CEFBS_HasSIMD128, // LOAD_EXTEND_S_I32x4_A64 |
| 8071 | CEFBS_HasSIMD128, // LOAD_EXTEND_S_I32x4_A64_S |
| 8072 | CEFBS_HasSIMD128, // LOAD_EXTEND_S_I64x2_A32 |
| 8073 | CEFBS_HasSIMD128, // LOAD_EXTEND_S_I64x2_A32_S |
| 8074 | CEFBS_HasSIMD128, // LOAD_EXTEND_S_I64x2_A64 |
| 8075 | CEFBS_HasSIMD128, // LOAD_EXTEND_S_I64x2_A64_S |
| 8076 | CEFBS_HasSIMD128, // LOAD_EXTEND_U_I16x8_A32 |
| 8077 | CEFBS_HasSIMD128, // LOAD_EXTEND_U_I16x8_A32_S |
| 8078 | CEFBS_HasSIMD128, // LOAD_EXTEND_U_I16x8_A64 |
| 8079 | CEFBS_HasSIMD128, // LOAD_EXTEND_U_I16x8_A64_S |
| 8080 | CEFBS_HasSIMD128, // LOAD_EXTEND_U_I32x4_A32 |
| 8081 | CEFBS_HasSIMD128, // LOAD_EXTEND_U_I32x4_A32_S |
| 8082 | CEFBS_HasSIMD128, // LOAD_EXTEND_U_I32x4_A64 |
| 8083 | CEFBS_HasSIMD128, // LOAD_EXTEND_U_I32x4_A64_S |
| 8084 | CEFBS_HasSIMD128, // LOAD_EXTEND_U_I64x2_A32 |
| 8085 | CEFBS_HasSIMD128, // LOAD_EXTEND_U_I64x2_A32_S |
| 8086 | CEFBS_HasSIMD128, // LOAD_EXTEND_U_I64x2_A64 |
| 8087 | CEFBS_HasSIMD128, // LOAD_EXTEND_U_I64x2_A64_S |
| 8088 | CEFBS_HasFP16, // LOAD_F16_F32_A32 |
| 8089 | CEFBS_HasFP16, // LOAD_F16_F32_A32_S |
| 8090 | CEFBS_HasFP16, // LOAD_F16_F32_A64 |
| 8091 | CEFBS_HasFP16, // LOAD_F16_F32_A64_S |
| 8092 | CEFBS_None, // LOAD_F32_A32 |
| 8093 | CEFBS_None, // LOAD_F32_A32_S |
| 8094 | CEFBS_None, // LOAD_F32_A64 |
| 8095 | CEFBS_None, // LOAD_F32_A64_S |
| 8096 | CEFBS_None, // LOAD_F64_A32 |
| 8097 | CEFBS_None, // LOAD_F64_A32_S |
| 8098 | CEFBS_None, // LOAD_F64_A64 |
| 8099 | CEFBS_None, // LOAD_F64_A64_S |
| 8100 | CEFBS_None, // LOAD_I32_A32 |
| 8101 | CEFBS_None, // LOAD_I32_A32_S |
| 8102 | CEFBS_None, // LOAD_I32_A64 |
| 8103 | CEFBS_None, // LOAD_I32_A64_S |
| 8104 | CEFBS_None, // LOAD_I64_A32 |
| 8105 | CEFBS_None, // LOAD_I64_A32_S |
| 8106 | CEFBS_None, // LOAD_I64_A64 |
| 8107 | CEFBS_None, // LOAD_I64_A64_S |
| 8108 | CEFBS_HasSIMD128, // LOAD_LANE_16_A32 |
| 8109 | CEFBS_HasSIMD128, // LOAD_LANE_16_A32_S |
| 8110 | CEFBS_HasSIMD128, // LOAD_LANE_16_A64 |
| 8111 | CEFBS_HasSIMD128, // LOAD_LANE_16_A64_S |
| 8112 | CEFBS_HasSIMD128, // LOAD_LANE_32_A32 |
| 8113 | CEFBS_HasSIMD128, // LOAD_LANE_32_A32_S |
| 8114 | CEFBS_HasSIMD128, // LOAD_LANE_32_A64 |
| 8115 | CEFBS_HasSIMD128, // LOAD_LANE_32_A64_S |
| 8116 | CEFBS_HasSIMD128, // LOAD_LANE_64_A32 |
| 8117 | CEFBS_HasSIMD128, // LOAD_LANE_64_A32_S |
| 8118 | CEFBS_HasSIMD128, // LOAD_LANE_64_A64 |
| 8119 | CEFBS_HasSIMD128, // LOAD_LANE_64_A64_S |
| 8120 | CEFBS_HasSIMD128, // LOAD_LANE_8_A32 |
| 8121 | CEFBS_HasSIMD128, // LOAD_LANE_8_A32_S |
| 8122 | CEFBS_HasSIMD128, // LOAD_LANE_8_A64 |
| 8123 | CEFBS_HasSIMD128, // LOAD_LANE_8_A64_S |
| 8124 | CEFBS_HasSIMD128, // LOAD_V128_A32 |
| 8125 | CEFBS_HasSIMD128, // LOAD_V128_A32_S |
| 8126 | CEFBS_HasSIMD128, // LOAD_V128_A64 |
| 8127 | CEFBS_HasSIMD128, // LOAD_V128_A64_S |
| 8128 | CEFBS_HasSIMD128, // LOAD_ZERO_32_A32 |
| 8129 | CEFBS_HasSIMD128, // LOAD_ZERO_32_A32_S |
| 8130 | CEFBS_HasSIMD128, // LOAD_ZERO_32_A64 |
| 8131 | CEFBS_HasSIMD128, // LOAD_ZERO_32_A64_S |
| 8132 | CEFBS_HasSIMD128, // LOAD_ZERO_64_A32 |
| 8133 | CEFBS_HasSIMD128, // LOAD_ZERO_64_A32_S |
| 8134 | CEFBS_HasSIMD128, // LOAD_ZERO_64_A64 |
| 8135 | CEFBS_HasSIMD128, // LOAD_ZERO_64_A64_S |
| 8136 | CEFBS_HasReferenceTypes_HasExceptionHandling, // LOCAL_GET_EXNREF |
| 8137 | CEFBS_HasReferenceTypes_HasExceptionHandling, // LOCAL_GET_EXNREF_S |
| 8138 | CEFBS_HasReferenceTypes, // LOCAL_GET_EXTERNREF |
| 8139 | CEFBS_HasReferenceTypes, // LOCAL_GET_EXTERNREF_S |
| 8140 | CEFBS_None, // LOCAL_GET_F32 |
| 8141 | CEFBS_None, // LOCAL_GET_F32_S |
| 8142 | CEFBS_None, // LOCAL_GET_F64 |
| 8143 | CEFBS_None, // LOCAL_GET_F64_S |
| 8144 | CEFBS_HasReferenceTypes, // LOCAL_GET_FUNCREF |
| 8145 | CEFBS_HasReferenceTypes, // LOCAL_GET_FUNCREF_S |
| 8146 | CEFBS_None, // LOCAL_GET_I32 |
| 8147 | CEFBS_None, // LOCAL_GET_I32_S |
| 8148 | CEFBS_None, // LOCAL_GET_I64 |
| 8149 | CEFBS_None, // LOCAL_GET_I64_S |
| 8150 | CEFBS_HasSIMD128, // LOCAL_GET_V128 |
| 8151 | CEFBS_HasSIMD128, // LOCAL_GET_V128_S |
| 8152 | CEFBS_HasReferenceTypes_HasExceptionHandling, // LOCAL_SET_EXNREF |
| 8153 | CEFBS_HasReferenceTypes_HasExceptionHandling, // LOCAL_SET_EXNREF_S |
| 8154 | CEFBS_HasReferenceTypes, // LOCAL_SET_EXTERNREF |
| 8155 | CEFBS_HasReferenceTypes, // LOCAL_SET_EXTERNREF_S |
| 8156 | CEFBS_None, // LOCAL_SET_F32 |
| 8157 | CEFBS_None, // LOCAL_SET_F32_S |
| 8158 | CEFBS_None, // LOCAL_SET_F64 |
| 8159 | CEFBS_None, // LOCAL_SET_F64_S |
| 8160 | CEFBS_HasReferenceTypes, // LOCAL_SET_FUNCREF |
| 8161 | CEFBS_HasReferenceTypes, // LOCAL_SET_FUNCREF_S |
| 8162 | CEFBS_None, // LOCAL_SET_I32 |
| 8163 | CEFBS_None, // LOCAL_SET_I32_S |
| 8164 | CEFBS_None, // LOCAL_SET_I64 |
| 8165 | CEFBS_None, // LOCAL_SET_I64_S |
| 8166 | CEFBS_HasSIMD128, // LOCAL_SET_V128 |
| 8167 | CEFBS_HasSIMD128, // LOCAL_SET_V128_S |
| 8168 | CEFBS_HasReferenceTypes_HasExceptionHandling, // LOCAL_TEE_EXNREF |
| 8169 | CEFBS_HasReferenceTypes_HasExceptionHandling, // LOCAL_TEE_EXNREF_S |
| 8170 | CEFBS_HasReferenceTypes, // LOCAL_TEE_EXTERNREF |
| 8171 | CEFBS_HasReferenceTypes, // LOCAL_TEE_EXTERNREF_S |
| 8172 | CEFBS_None, // LOCAL_TEE_F32 |
| 8173 | CEFBS_None, // LOCAL_TEE_F32_S |
| 8174 | CEFBS_None, // LOCAL_TEE_F64 |
| 8175 | CEFBS_None, // LOCAL_TEE_F64_S |
| 8176 | CEFBS_HasReferenceTypes, // LOCAL_TEE_FUNCREF |
| 8177 | CEFBS_HasReferenceTypes, // LOCAL_TEE_FUNCREF_S |
| 8178 | CEFBS_None, // LOCAL_TEE_I32 |
| 8179 | CEFBS_None, // LOCAL_TEE_I32_S |
| 8180 | CEFBS_None, // LOCAL_TEE_I64 |
| 8181 | CEFBS_None, // LOCAL_TEE_I64_S |
| 8182 | CEFBS_HasSIMD128, // LOCAL_TEE_V128 |
| 8183 | CEFBS_HasSIMD128, // LOCAL_TEE_V128_S |
| 8184 | CEFBS_None, // LOOP |
| 8185 | CEFBS_None, // LOOP_S |
| 8186 | CEFBS_HasSIMD128_HasFP16, // LT_F16x8 |
| 8187 | CEFBS_HasSIMD128_HasFP16, // LT_F16x8_S |
| 8188 | CEFBS_None, // LT_F32 |
| 8189 | CEFBS_None, // LT_F32_S |
| 8190 | CEFBS_HasSIMD128, // LT_F32x4 |
| 8191 | CEFBS_HasSIMD128, // LT_F32x4_S |
| 8192 | CEFBS_None, // LT_F64 |
| 8193 | CEFBS_None, // LT_F64_S |
| 8194 | CEFBS_HasSIMD128, // LT_F64x2 |
| 8195 | CEFBS_HasSIMD128, // LT_F64x2_S |
| 8196 | CEFBS_HasSIMD128, // LT_S_I16x8 |
| 8197 | CEFBS_HasSIMD128, // LT_S_I16x8_S |
| 8198 | CEFBS_None, // LT_S_I32 |
| 8199 | CEFBS_None, // LT_S_I32_S |
| 8200 | CEFBS_HasSIMD128, // LT_S_I32x4 |
| 8201 | CEFBS_HasSIMD128, // LT_S_I32x4_S |
| 8202 | CEFBS_None, // LT_S_I64 |
| 8203 | CEFBS_None, // LT_S_I64_S |
| 8204 | CEFBS_HasSIMD128, // LT_S_I64x2 |
| 8205 | CEFBS_HasSIMD128, // LT_S_I64x2_S |
| 8206 | CEFBS_HasSIMD128, // LT_S_I8x16 |
| 8207 | CEFBS_HasSIMD128, // LT_S_I8x16_S |
| 8208 | CEFBS_HasSIMD128, // LT_U_I16x8 |
| 8209 | CEFBS_HasSIMD128, // LT_U_I16x8_S |
| 8210 | CEFBS_None, // LT_U_I32 |
| 8211 | CEFBS_None, // LT_U_I32_S |
| 8212 | CEFBS_HasSIMD128, // LT_U_I32x4 |
| 8213 | CEFBS_HasSIMD128, // LT_U_I32x4_S |
| 8214 | CEFBS_None, // LT_U_I64 |
| 8215 | CEFBS_None, // LT_U_I64_S |
| 8216 | CEFBS_HasSIMD128, // LT_U_I8x16 |
| 8217 | CEFBS_HasSIMD128, // LT_U_I8x16_S |
| 8218 | CEFBS_HasSIMD128_HasFP16, // MADD_F16x8 |
| 8219 | CEFBS_HasSIMD128_HasFP16, // MADD_F16x8_S |
| 8220 | CEFBS_HasSIMD128_HasRelaxedSIMD, // MADD_F32x4 |
| 8221 | CEFBS_HasSIMD128_HasRelaxedSIMD, // MADD_F32x4_S |
| 8222 | CEFBS_HasSIMD128_HasRelaxedSIMD, // MADD_F64x2 |
| 8223 | CEFBS_HasSIMD128_HasRelaxedSIMD, // MADD_F64x2_S |
| 8224 | CEFBS_HasSIMD128_HasFP16, // MAX_F16x8 |
| 8225 | CEFBS_HasSIMD128_HasFP16, // MAX_F16x8_S |
| 8226 | CEFBS_None, // MAX_F32 |
| 8227 | CEFBS_None, // MAX_F32_S |
| 8228 | CEFBS_HasSIMD128, // MAX_F32x4 |
| 8229 | CEFBS_HasSIMD128, // MAX_F32x4_S |
| 8230 | CEFBS_None, // MAX_F64 |
| 8231 | CEFBS_None, // MAX_F64_S |
| 8232 | CEFBS_HasSIMD128, // MAX_F64x2 |
| 8233 | CEFBS_HasSIMD128, // MAX_F64x2_S |
| 8234 | CEFBS_HasSIMD128, // MAX_S_I16x8 |
| 8235 | CEFBS_HasSIMD128, // MAX_S_I16x8_S |
| 8236 | CEFBS_HasSIMD128, // MAX_S_I32x4 |
| 8237 | CEFBS_HasSIMD128, // MAX_S_I32x4_S |
| 8238 | CEFBS_HasSIMD128, // MAX_S_I8x16 |
| 8239 | CEFBS_HasSIMD128, // MAX_S_I8x16_S |
| 8240 | CEFBS_HasSIMD128, // MAX_U_I16x8 |
| 8241 | CEFBS_HasSIMD128, // MAX_U_I16x8_S |
| 8242 | CEFBS_HasSIMD128, // MAX_U_I32x4 |
| 8243 | CEFBS_HasSIMD128, // MAX_U_I32x4_S |
| 8244 | CEFBS_HasSIMD128, // MAX_U_I8x16 |
| 8245 | CEFBS_HasSIMD128, // MAX_U_I8x16_S |
| 8246 | CEFBS_HasBulkMemoryOpt, // MEMCPY_A32 |
| 8247 | CEFBS_HasBulkMemoryOpt, // MEMCPY_A32_S |
| 8248 | CEFBS_HasBulkMemoryOpt, // MEMCPY_A64 |
| 8249 | CEFBS_HasBulkMemoryOpt, // MEMCPY_A64_S |
| 8250 | CEFBS_HasAtomics, // MEMORY_ATOMIC_NOTIFY_A32 |
| 8251 | CEFBS_HasAtomics, // MEMORY_ATOMIC_NOTIFY_A32_S |
| 8252 | CEFBS_HasAtomics, // MEMORY_ATOMIC_NOTIFY_A64 |
| 8253 | CEFBS_HasAtomics, // MEMORY_ATOMIC_NOTIFY_A64_S |
| 8254 | CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT32_A32 |
| 8255 | CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT32_A32_S |
| 8256 | CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT32_A64 |
| 8257 | CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT32_A64_S |
| 8258 | CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT64_A32 |
| 8259 | CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT64_A32_S |
| 8260 | CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT64_A64 |
| 8261 | CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT64_A64_S |
| 8262 | CEFBS_HasBulkMemoryOpt, // MEMORY_COPY_A32 |
| 8263 | CEFBS_HasBulkMemoryOpt, // MEMORY_COPY_A32_S |
| 8264 | CEFBS_HasBulkMemoryOpt, // MEMORY_COPY_A64 |
| 8265 | CEFBS_HasBulkMemoryOpt, // MEMORY_COPY_A64_S |
| 8266 | CEFBS_HasBulkMemoryOpt, // MEMORY_FILL_A32 |
| 8267 | CEFBS_HasBulkMemoryOpt, // MEMORY_FILL_A32_S |
| 8268 | CEFBS_HasBulkMemoryOpt, // MEMORY_FILL_A64 |
| 8269 | CEFBS_HasBulkMemoryOpt, // MEMORY_FILL_A64_S |
| 8270 | CEFBS_HasBulkMemoryOpt, // MEMORY_INIT_A32 |
| 8271 | CEFBS_HasBulkMemoryOpt, // MEMORY_INIT_A32_S |
| 8272 | CEFBS_HasBulkMemoryOpt, // MEMORY_INIT_A64 |
| 8273 | CEFBS_HasBulkMemoryOpt, // MEMORY_INIT_A64_S |
| 8274 | CEFBS_HasBulkMemoryOpt, // MEMSET_A32 |
| 8275 | CEFBS_HasBulkMemoryOpt, // MEMSET_A32_S |
| 8276 | CEFBS_HasBulkMemoryOpt, // MEMSET_A64 |
| 8277 | CEFBS_HasBulkMemoryOpt, // MEMSET_A64_S |
| 8278 | CEFBS_HasSIMD128_HasFP16, // MIN_F16x8 |
| 8279 | CEFBS_HasSIMD128_HasFP16, // MIN_F16x8_S |
| 8280 | CEFBS_None, // MIN_F32 |
| 8281 | CEFBS_None, // MIN_F32_S |
| 8282 | CEFBS_HasSIMD128, // MIN_F32x4 |
| 8283 | CEFBS_HasSIMD128, // MIN_F32x4_S |
| 8284 | CEFBS_None, // MIN_F64 |
| 8285 | CEFBS_None, // MIN_F64_S |
| 8286 | CEFBS_HasSIMD128, // MIN_F64x2 |
| 8287 | CEFBS_HasSIMD128, // MIN_F64x2_S |
| 8288 | CEFBS_HasSIMD128, // MIN_S_I16x8 |
| 8289 | CEFBS_HasSIMD128, // MIN_S_I16x8_S |
| 8290 | CEFBS_HasSIMD128, // MIN_S_I32x4 |
| 8291 | CEFBS_HasSIMD128, // MIN_S_I32x4_S |
| 8292 | CEFBS_HasSIMD128, // MIN_S_I8x16 |
| 8293 | CEFBS_HasSIMD128, // MIN_S_I8x16_S |
| 8294 | CEFBS_HasSIMD128, // MIN_U_I16x8 |
| 8295 | CEFBS_HasSIMD128, // MIN_U_I16x8_S |
| 8296 | CEFBS_HasSIMD128, // MIN_U_I32x4 |
| 8297 | CEFBS_HasSIMD128, // MIN_U_I32x4_S |
| 8298 | CEFBS_HasSIMD128, // MIN_U_I8x16 |
| 8299 | CEFBS_HasSIMD128, // MIN_U_I8x16_S |
| 8300 | CEFBS_HasSIMD128_HasFP16, // MUL_F16x8 |
| 8301 | CEFBS_HasSIMD128_HasFP16, // MUL_F16x8_S |
| 8302 | CEFBS_None, // MUL_F32 |
| 8303 | CEFBS_None, // MUL_F32_S |
| 8304 | CEFBS_HasSIMD128, // MUL_F32x4 |
| 8305 | CEFBS_HasSIMD128, // MUL_F32x4_S |
| 8306 | CEFBS_None, // MUL_F64 |
| 8307 | CEFBS_None, // MUL_F64_S |
| 8308 | CEFBS_HasSIMD128, // MUL_F64x2 |
| 8309 | CEFBS_HasSIMD128, // MUL_F64x2_S |
| 8310 | CEFBS_HasSIMD128, // MUL_I16x8 |
| 8311 | CEFBS_HasSIMD128, // MUL_I16x8_S |
| 8312 | CEFBS_None, // MUL_I32 |
| 8313 | CEFBS_None, // MUL_I32_S |
| 8314 | CEFBS_HasSIMD128, // MUL_I32x4 |
| 8315 | CEFBS_HasSIMD128, // MUL_I32x4_S |
| 8316 | CEFBS_None, // MUL_I64 |
| 8317 | CEFBS_None, // MUL_I64_S |
| 8318 | CEFBS_HasSIMD128, // MUL_I64x2 |
| 8319 | CEFBS_HasSIMD128, // MUL_I64x2_S |
| 8320 | CEFBS_HasSIMD128, // NARROW_S_I16x8 |
| 8321 | CEFBS_HasSIMD128, // NARROW_S_I16x8_S |
| 8322 | CEFBS_HasSIMD128, // NARROW_S_I8x16 |
| 8323 | CEFBS_HasSIMD128, // NARROW_S_I8x16_S |
| 8324 | CEFBS_HasSIMD128, // NARROW_U_I16x8 |
| 8325 | CEFBS_HasSIMD128, // NARROW_U_I16x8_S |
| 8326 | CEFBS_HasSIMD128, // NARROW_U_I8x16 |
| 8327 | CEFBS_HasSIMD128, // NARROW_U_I8x16_S |
| 8328 | CEFBS_HasSIMD128_HasFP16, // NEAREST_F16x8 |
| 8329 | CEFBS_HasSIMD128_HasFP16, // NEAREST_F16x8_S |
| 8330 | CEFBS_None, // NEAREST_F32 |
| 8331 | CEFBS_None, // NEAREST_F32_S |
| 8332 | CEFBS_HasSIMD128, // NEAREST_F32x4 |
| 8333 | CEFBS_HasSIMD128, // NEAREST_F32x4_S |
| 8334 | CEFBS_None, // NEAREST_F64 |
| 8335 | CEFBS_None, // NEAREST_F64_S |
| 8336 | CEFBS_HasSIMD128, // NEAREST_F64x2 |
| 8337 | CEFBS_HasSIMD128, // NEAREST_F64x2_S |
| 8338 | CEFBS_HasSIMD128_HasFP16, // NEG_F16x8 |
| 8339 | CEFBS_HasSIMD128_HasFP16, // NEG_F16x8_S |
| 8340 | CEFBS_None, // NEG_F32 |
| 8341 | CEFBS_None, // NEG_F32_S |
| 8342 | CEFBS_HasSIMD128, // NEG_F32x4 |
| 8343 | CEFBS_HasSIMD128, // NEG_F32x4_S |
| 8344 | CEFBS_None, // NEG_F64 |
| 8345 | CEFBS_None, // NEG_F64_S |
| 8346 | CEFBS_HasSIMD128, // NEG_F64x2 |
| 8347 | CEFBS_HasSIMD128, // NEG_F64x2_S |
| 8348 | CEFBS_HasSIMD128, // NEG_I16x8 |
| 8349 | CEFBS_HasSIMD128, // NEG_I16x8_S |
| 8350 | CEFBS_HasSIMD128, // NEG_I32x4 |
| 8351 | CEFBS_HasSIMD128, // NEG_I32x4_S |
| 8352 | CEFBS_HasSIMD128, // NEG_I64x2 |
| 8353 | CEFBS_HasSIMD128, // NEG_I64x2_S |
| 8354 | CEFBS_HasSIMD128, // NEG_I8x16 |
| 8355 | CEFBS_HasSIMD128, // NEG_I8x16_S |
| 8356 | CEFBS_HasSIMD128_HasFP16, // NE_F16x8 |
| 8357 | CEFBS_HasSIMD128_HasFP16, // NE_F16x8_S |
| 8358 | CEFBS_None, // NE_F32 |
| 8359 | CEFBS_None, // NE_F32_S |
| 8360 | CEFBS_HasSIMD128, // NE_F32x4 |
| 8361 | CEFBS_HasSIMD128, // NE_F32x4_S |
| 8362 | CEFBS_None, // NE_F64 |
| 8363 | CEFBS_None, // NE_F64_S |
| 8364 | CEFBS_HasSIMD128, // NE_F64x2 |
| 8365 | CEFBS_HasSIMD128, // NE_F64x2_S |
| 8366 | CEFBS_HasSIMD128, // NE_I16x8 |
| 8367 | CEFBS_HasSIMD128, // NE_I16x8_S |
| 8368 | CEFBS_None, // NE_I32 |
| 8369 | CEFBS_None, // NE_I32_S |
| 8370 | CEFBS_HasSIMD128, // NE_I32x4 |
| 8371 | CEFBS_HasSIMD128, // NE_I32x4_S |
| 8372 | CEFBS_None, // NE_I64 |
| 8373 | CEFBS_None, // NE_I64_S |
| 8374 | CEFBS_HasSIMD128, // NE_I64x2 |
| 8375 | CEFBS_HasSIMD128, // NE_I64x2_S |
| 8376 | CEFBS_HasSIMD128, // NE_I8x16 |
| 8377 | CEFBS_HasSIMD128, // NE_I8x16_S |
| 8378 | CEFBS_HasSIMD128_HasFP16, // NMADD_F16x8 |
| 8379 | CEFBS_HasSIMD128_HasFP16, // NMADD_F16x8_S |
| 8380 | CEFBS_HasSIMD128_HasRelaxedSIMD, // NMADD_F32x4 |
| 8381 | CEFBS_HasSIMD128_HasRelaxedSIMD, // NMADD_F32x4_S |
| 8382 | CEFBS_HasSIMD128_HasRelaxedSIMD, // NMADD_F64x2 |
| 8383 | CEFBS_HasSIMD128_HasRelaxedSIMD, // NMADD_F64x2_S |
| 8384 | CEFBS_None, // NOP |
| 8385 | CEFBS_None, // NOP_S |
| 8386 | CEFBS_HasSIMD128, // NOT |
| 8387 | CEFBS_HasSIMD128, // NOT_S |
| 8388 | CEFBS_HasSIMD128, // OR |
| 8389 | CEFBS_None, // OR_I32 |
| 8390 | CEFBS_None, // OR_I32_S |
| 8391 | CEFBS_None, // OR_I64 |
| 8392 | CEFBS_None, // OR_I64_S |
| 8393 | CEFBS_HasSIMD128, // OR_S |
| 8394 | CEFBS_HasSIMD128_HasFP16, // PMAX_F16x8 |
| 8395 | CEFBS_HasSIMD128_HasFP16, // PMAX_F16x8_S |
| 8396 | CEFBS_HasSIMD128, // PMAX_F32x4 |
| 8397 | CEFBS_HasSIMD128, // PMAX_F32x4_S |
| 8398 | CEFBS_HasSIMD128, // PMAX_F64x2 |
| 8399 | CEFBS_HasSIMD128, // PMAX_F64x2_S |
| 8400 | CEFBS_HasSIMD128_HasFP16, // PMIN_F16x8 |
| 8401 | CEFBS_HasSIMD128_HasFP16, // PMIN_F16x8_S |
| 8402 | CEFBS_HasSIMD128, // PMIN_F32x4 |
| 8403 | CEFBS_HasSIMD128, // PMIN_F32x4_S |
| 8404 | CEFBS_HasSIMD128, // PMIN_F64x2 |
| 8405 | CEFBS_HasSIMD128, // PMIN_F64x2_S |
| 8406 | CEFBS_None, // POPCNT_I32 |
| 8407 | CEFBS_None, // POPCNT_I32_S |
| 8408 | CEFBS_None, // POPCNT_I64 |
| 8409 | CEFBS_None, // POPCNT_I64_S |
| 8410 | CEFBS_HasSIMD128, // POPCNT_I8x16 |
| 8411 | CEFBS_HasSIMD128, // POPCNT_I8x16_S |
| 8412 | CEFBS_HasSIMD128, // Q15MULR_SAT_S_I16x8 |
| 8413 | CEFBS_HasSIMD128, // Q15MULR_SAT_S_I16x8_S |
| 8414 | CEFBS_HasGC, // REF_CAST_FUNCREF |
| 8415 | CEFBS_HasGC, // REF_CAST_FUNCREF_S |
| 8416 | CEFBS_HasReferenceTypes, // REF_FUNC |
| 8417 | CEFBS_HasReferenceTypes, // REF_FUNC_S |
| 8418 | CEFBS_HasReferenceTypes, // REF_IS_NULL_EXNREF |
| 8419 | CEFBS_HasReferenceTypes, // REF_IS_NULL_EXNREF_S |
| 8420 | CEFBS_HasReferenceTypes, // REF_IS_NULL_EXTERNREF |
| 8421 | CEFBS_HasReferenceTypes, // REF_IS_NULL_EXTERNREF_S |
| 8422 | CEFBS_HasReferenceTypes, // REF_IS_NULL_FUNCREF |
| 8423 | CEFBS_HasReferenceTypes, // REF_IS_NULL_FUNCREF_S |
| 8424 | CEFBS_HasReferenceTypes, // REF_NULL_EXNREF |
| 8425 | CEFBS_HasReferenceTypes, // REF_NULL_EXNREF_S |
| 8426 | CEFBS_HasReferenceTypes, // REF_NULL_EXTERNREF |
| 8427 | CEFBS_HasReferenceTypes, // REF_NULL_EXTERNREF_S |
| 8428 | CEFBS_HasReferenceTypes, // REF_NULL_FUNCREF |
| 8429 | CEFBS_HasReferenceTypes, // REF_NULL_FUNCREF_S |
| 8430 | CEFBS_HasGC, // REF_TEST_FUNCREF |
| 8431 | CEFBS_HasGC, // REF_TEST_FUNCREF_S |
| 8432 | CEFBS_HasRelaxedSIMD, // RELAXED_DOT |
| 8433 | CEFBS_HasRelaxedSIMD, // RELAXED_DOT_ADD |
| 8434 | CEFBS_HasRelaxedSIMD, // RELAXED_DOT_ADD_S |
| 8435 | CEFBS_HasRelaxedSIMD, // RELAXED_DOT_BFLOAT |
| 8436 | CEFBS_HasRelaxedSIMD, // RELAXED_DOT_BFLOAT_S |
| 8437 | CEFBS_HasRelaxedSIMD, // RELAXED_DOT_S |
| 8438 | CEFBS_HasRelaxedSIMD, // RELAXED_Q15MULR_S_I16x8 |
| 8439 | CEFBS_HasRelaxedSIMD, // RELAXED_Q15MULR_S_I16x8_S |
| 8440 | CEFBS_HasRelaxedSIMD, // RELAXED_SWIZZLE |
| 8441 | CEFBS_HasRelaxedSIMD, // RELAXED_SWIZZLE_S |
| 8442 | CEFBS_None, // REM_S_I32 |
| 8443 | CEFBS_None, // REM_S_I32_S |
| 8444 | CEFBS_None, // REM_S_I64 |
| 8445 | CEFBS_None, // REM_S_I64_S |
| 8446 | CEFBS_None, // REM_U_I32 |
| 8447 | CEFBS_None, // REM_U_I32_S |
| 8448 | CEFBS_None, // REM_U_I64 |
| 8449 | CEFBS_None, // REM_U_I64_S |
| 8450 | CEFBS_HasFP16, // REPLACE_LANE_F16x8 |
| 8451 | CEFBS_HasFP16, // REPLACE_LANE_F16x8_S |
| 8452 | CEFBS_HasSIMD128, // REPLACE_LANE_F32x4 |
| 8453 | CEFBS_HasSIMD128, // REPLACE_LANE_F32x4_S |
| 8454 | CEFBS_HasSIMD128, // REPLACE_LANE_F64x2 |
| 8455 | CEFBS_HasSIMD128, // REPLACE_LANE_F64x2_S |
| 8456 | CEFBS_HasSIMD128, // REPLACE_LANE_I16x8 |
| 8457 | CEFBS_HasSIMD128, // REPLACE_LANE_I16x8_S |
| 8458 | CEFBS_HasSIMD128, // REPLACE_LANE_I32x4 |
| 8459 | CEFBS_HasSIMD128, // REPLACE_LANE_I32x4_S |
| 8460 | CEFBS_HasSIMD128, // REPLACE_LANE_I64x2 |
| 8461 | CEFBS_HasSIMD128, // REPLACE_LANE_I64x2_S |
| 8462 | CEFBS_HasSIMD128, // REPLACE_LANE_I8x16 |
| 8463 | CEFBS_HasSIMD128, // REPLACE_LANE_I8x16_S |
| 8464 | CEFBS_HasExceptionHandling, // RETHROW |
| 8465 | CEFBS_HasExceptionHandling, // RETHROW_S |
| 8466 | CEFBS_None, // RETURN |
| 8467 | CEFBS_None, // RETURN_S |
| 8468 | CEFBS_HasTailCall, // RET_CALL |
| 8469 | CEFBS_HasTailCall, // RET_CALL_INDIRECT |
| 8470 | CEFBS_HasTailCall, // RET_CALL_INDIRECT_S |
| 8471 | CEFBS_HasTailCall_HasGC, // RET_CALL_REF |
| 8472 | CEFBS_HasTailCall_HasGC, // RET_CALL_REF_S |
| 8473 | CEFBS_HasTailCall, // RET_CALL_S |
| 8474 | CEFBS_None, // ROTL_I32 |
| 8475 | CEFBS_None, // ROTL_I32_S |
| 8476 | CEFBS_None, // ROTL_I64 |
| 8477 | CEFBS_None, // ROTL_I64_S |
| 8478 | CEFBS_None, // ROTR_I32 |
| 8479 | CEFBS_None, // ROTR_I32_S |
| 8480 | CEFBS_None, // ROTR_I64 |
| 8481 | CEFBS_None, // ROTR_I64_S |
| 8482 | CEFBS_HasReferenceTypes, // SELECT_EXNREF |
| 8483 | CEFBS_HasReferenceTypes, // SELECT_EXNREF_S |
| 8484 | CEFBS_HasReferenceTypes, // SELECT_EXTERNREF |
| 8485 | CEFBS_HasReferenceTypes, // SELECT_EXTERNREF_S |
| 8486 | CEFBS_None, // SELECT_F32 |
| 8487 | CEFBS_None, // SELECT_F32_S |
| 8488 | CEFBS_None, // SELECT_F64 |
| 8489 | CEFBS_None, // SELECT_F64_S |
| 8490 | CEFBS_HasReferenceTypes, // SELECT_FUNCREF |
| 8491 | CEFBS_HasReferenceTypes, // SELECT_FUNCREF_S |
| 8492 | CEFBS_None, // SELECT_I32 |
| 8493 | CEFBS_None, // SELECT_I32_S |
| 8494 | CEFBS_None, // SELECT_I64 |
| 8495 | CEFBS_None, // SELECT_I64_S |
| 8496 | CEFBS_HasReferenceTypes, // SELECT_T |
| 8497 | CEFBS_HasReferenceTypes, // SELECT_T_S |
| 8498 | CEFBS_None, // SELECT_V128 |
| 8499 | CEFBS_None, // SELECT_V128_S |
| 8500 | CEFBS_HasSIMD128, // SHL_I16x8 |
| 8501 | CEFBS_HasSIMD128, // SHL_I16x8_S |
| 8502 | CEFBS_None, // SHL_I32 |
| 8503 | CEFBS_None, // SHL_I32_S |
| 8504 | CEFBS_HasSIMD128, // SHL_I32x4 |
| 8505 | CEFBS_HasSIMD128, // SHL_I32x4_S |
| 8506 | CEFBS_None, // SHL_I64 |
| 8507 | CEFBS_None, // SHL_I64_S |
| 8508 | CEFBS_HasSIMD128, // SHL_I64x2 |
| 8509 | CEFBS_HasSIMD128, // SHL_I64x2_S |
| 8510 | CEFBS_HasSIMD128, // SHL_I8x16 |
| 8511 | CEFBS_HasSIMD128, // SHL_I8x16_S |
| 8512 | CEFBS_HasSIMD128, // SHR_S_I16x8 |
| 8513 | CEFBS_HasSIMD128, // SHR_S_I16x8_S |
| 8514 | CEFBS_None, // SHR_S_I32 |
| 8515 | CEFBS_None, // SHR_S_I32_S |
| 8516 | CEFBS_HasSIMD128, // SHR_S_I32x4 |
| 8517 | CEFBS_HasSIMD128, // SHR_S_I32x4_S |
| 8518 | CEFBS_None, // SHR_S_I64 |
| 8519 | CEFBS_None, // SHR_S_I64_S |
| 8520 | CEFBS_HasSIMD128, // SHR_S_I64x2 |
| 8521 | CEFBS_HasSIMD128, // SHR_S_I64x2_S |
| 8522 | CEFBS_HasSIMD128, // SHR_S_I8x16 |
| 8523 | CEFBS_HasSIMD128, // SHR_S_I8x16_S |
| 8524 | CEFBS_HasSIMD128, // SHR_U_I16x8 |
| 8525 | CEFBS_HasSIMD128, // SHR_U_I16x8_S |
| 8526 | CEFBS_None, // SHR_U_I32 |
| 8527 | CEFBS_None, // SHR_U_I32_S |
| 8528 | CEFBS_HasSIMD128, // SHR_U_I32x4 |
| 8529 | CEFBS_HasSIMD128, // SHR_U_I32x4_S |
| 8530 | CEFBS_None, // SHR_U_I64 |
| 8531 | CEFBS_None, // SHR_U_I64_S |
| 8532 | CEFBS_HasSIMD128, // SHR_U_I64x2 |
| 8533 | CEFBS_HasSIMD128, // SHR_U_I64x2_S |
| 8534 | CEFBS_HasSIMD128, // SHR_U_I8x16 |
| 8535 | CEFBS_HasSIMD128, // SHR_U_I8x16_S |
| 8536 | CEFBS_HasSIMD128, // SHUFFLE |
| 8537 | CEFBS_HasSIMD128, // SHUFFLE_S |
| 8538 | CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMAX_F32x4 |
| 8539 | CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMAX_F32x4_S |
| 8540 | CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMAX_F64x2 |
| 8541 | CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMAX_F64x2_S |
| 8542 | CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMIN_F32x4 |
| 8543 | CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMIN_F32x4_S |
| 8544 | CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMIN_F64x2 |
| 8545 | CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMIN_F64x2_S |
| 8546 | CEFBS_HasFP16, // SPLAT_F16x8 |
| 8547 | CEFBS_HasFP16, // SPLAT_F16x8_S |
| 8548 | CEFBS_HasSIMD128, // SPLAT_F32x4 |
| 8549 | CEFBS_HasSIMD128, // SPLAT_F32x4_S |
| 8550 | CEFBS_HasSIMD128, // SPLAT_F64x2 |
| 8551 | CEFBS_HasSIMD128, // SPLAT_F64x2_S |
| 8552 | CEFBS_HasSIMD128, // SPLAT_I16x8 |
| 8553 | CEFBS_HasSIMD128, // SPLAT_I16x8_S |
| 8554 | CEFBS_HasSIMD128, // SPLAT_I32x4 |
| 8555 | CEFBS_HasSIMD128, // SPLAT_I32x4_S |
| 8556 | CEFBS_HasSIMD128, // SPLAT_I64x2 |
| 8557 | CEFBS_HasSIMD128, // SPLAT_I64x2_S |
| 8558 | CEFBS_HasSIMD128, // SPLAT_I8x16 |
| 8559 | CEFBS_HasSIMD128, // SPLAT_I8x16_S |
| 8560 | CEFBS_HasSIMD128_HasFP16, // SQRT_F16x8 |
| 8561 | CEFBS_HasSIMD128_HasFP16, // SQRT_F16x8_S |
| 8562 | CEFBS_None, // SQRT_F32 |
| 8563 | CEFBS_None, // SQRT_F32_S |
| 8564 | CEFBS_HasSIMD128, // SQRT_F32x4 |
| 8565 | CEFBS_HasSIMD128, // SQRT_F32x4_S |
| 8566 | CEFBS_None, // SQRT_F64 |
| 8567 | CEFBS_None, // SQRT_F64_S |
| 8568 | CEFBS_HasSIMD128, // SQRT_F64x2 |
| 8569 | CEFBS_HasSIMD128, // SQRT_F64x2_S |
| 8570 | CEFBS_None, // STORE16_I32_A32 |
| 8571 | CEFBS_None, // STORE16_I32_A32_S |
| 8572 | CEFBS_None, // STORE16_I32_A64 |
| 8573 | CEFBS_None, // STORE16_I32_A64_S |
| 8574 | CEFBS_None, // STORE16_I64_A32 |
| 8575 | CEFBS_None, // STORE16_I64_A32_S |
| 8576 | CEFBS_None, // STORE16_I64_A64 |
| 8577 | CEFBS_None, // STORE16_I64_A64_S |
| 8578 | CEFBS_None, // STORE32_I64_A32 |
| 8579 | CEFBS_None, // STORE32_I64_A32_S |
| 8580 | CEFBS_None, // STORE32_I64_A64 |
| 8581 | CEFBS_None, // STORE32_I64_A64_S |
| 8582 | CEFBS_None, // STORE8_I32_A32 |
| 8583 | CEFBS_None, // STORE8_I32_A32_S |
| 8584 | CEFBS_None, // STORE8_I32_A64 |
| 8585 | CEFBS_None, // STORE8_I32_A64_S |
| 8586 | CEFBS_None, // STORE8_I64_A32 |
| 8587 | CEFBS_None, // STORE8_I64_A32_S |
| 8588 | CEFBS_None, // STORE8_I64_A64 |
| 8589 | CEFBS_None, // STORE8_I64_A64_S |
| 8590 | CEFBS_HasFP16, // STORE_F16_F32_A32 |
| 8591 | CEFBS_HasFP16, // STORE_F16_F32_A32_S |
| 8592 | CEFBS_HasFP16, // STORE_F16_F32_A64 |
| 8593 | CEFBS_HasFP16, // STORE_F16_F32_A64_S |
| 8594 | CEFBS_None, // STORE_F32_A32 |
| 8595 | CEFBS_None, // STORE_F32_A32_S |
| 8596 | CEFBS_None, // STORE_F32_A64 |
| 8597 | CEFBS_None, // STORE_F32_A64_S |
| 8598 | CEFBS_None, // STORE_F64_A32 |
| 8599 | CEFBS_None, // STORE_F64_A32_S |
| 8600 | CEFBS_None, // STORE_F64_A64 |
| 8601 | CEFBS_None, // STORE_F64_A64_S |
| 8602 | CEFBS_None, // STORE_I32_A32 |
| 8603 | CEFBS_None, // STORE_I32_A32_S |
| 8604 | CEFBS_None, // STORE_I32_A64 |
| 8605 | CEFBS_None, // STORE_I32_A64_S |
| 8606 | CEFBS_None, // STORE_I64_A32 |
| 8607 | CEFBS_None, // STORE_I64_A32_S |
| 8608 | CEFBS_None, // STORE_I64_A64 |
| 8609 | CEFBS_None, // STORE_I64_A64_S |
| 8610 | CEFBS_HasSIMD128, // STORE_LANE_I16x8_A32 |
| 8611 | CEFBS_HasSIMD128, // STORE_LANE_I16x8_A32_S |
| 8612 | CEFBS_HasSIMD128, // STORE_LANE_I16x8_A64 |
| 8613 | CEFBS_HasSIMD128, // STORE_LANE_I16x8_A64_S |
| 8614 | CEFBS_HasSIMD128, // STORE_LANE_I32x4_A32 |
| 8615 | CEFBS_HasSIMD128, // STORE_LANE_I32x4_A32_S |
| 8616 | CEFBS_HasSIMD128, // STORE_LANE_I32x4_A64 |
| 8617 | CEFBS_HasSIMD128, // STORE_LANE_I32x4_A64_S |
| 8618 | CEFBS_HasSIMD128, // STORE_LANE_I64x2_A32 |
| 8619 | CEFBS_HasSIMD128, // STORE_LANE_I64x2_A32_S |
| 8620 | CEFBS_HasSIMD128, // STORE_LANE_I64x2_A64 |
| 8621 | CEFBS_HasSIMD128, // STORE_LANE_I64x2_A64_S |
| 8622 | CEFBS_HasSIMD128, // STORE_LANE_I8x16_A32 |
| 8623 | CEFBS_HasSIMD128, // STORE_LANE_I8x16_A32_S |
| 8624 | CEFBS_HasSIMD128, // STORE_LANE_I8x16_A64 |
| 8625 | CEFBS_HasSIMD128, // STORE_LANE_I8x16_A64_S |
| 8626 | CEFBS_HasSIMD128, // STORE_V128_A32 |
| 8627 | CEFBS_HasSIMD128, // STORE_V128_A32_S |
| 8628 | CEFBS_HasSIMD128, // STORE_V128_A64 |
| 8629 | CEFBS_HasSIMD128, // STORE_V128_A64_S |
| 8630 | CEFBS_HasSIMD128_HasFP16, // SUB_F16x8 |
| 8631 | CEFBS_HasSIMD128_HasFP16, // SUB_F16x8_S |
| 8632 | CEFBS_None, // SUB_F32 |
| 8633 | CEFBS_None, // SUB_F32_S |
| 8634 | CEFBS_HasSIMD128, // SUB_F32x4 |
| 8635 | CEFBS_HasSIMD128, // SUB_F32x4_S |
| 8636 | CEFBS_None, // SUB_F64 |
| 8637 | CEFBS_None, // SUB_F64_S |
| 8638 | CEFBS_HasSIMD128, // SUB_F64x2 |
| 8639 | CEFBS_HasSIMD128, // SUB_F64x2_S |
| 8640 | CEFBS_HasSIMD128, // SUB_I16x8 |
| 8641 | CEFBS_HasSIMD128, // SUB_I16x8_S |
| 8642 | CEFBS_None, // SUB_I32 |
| 8643 | CEFBS_None, // SUB_I32_S |
| 8644 | CEFBS_HasSIMD128, // SUB_I32x4 |
| 8645 | CEFBS_HasSIMD128, // SUB_I32x4_S |
| 8646 | CEFBS_None, // SUB_I64 |
| 8647 | CEFBS_None, // SUB_I64_S |
| 8648 | CEFBS_HasSIMD128, // SUB_I64x2 |
| 8649 | CEFBS_HasSIMD128, // SUB_I64x2_S |
| 8650 | CEFBS_HasSIMD128, // SUB_I8x16 |
| 8651 | CEFBS_HasSIMD128, // SUB_I8x16_S |
| 8652 | CEFBS_HasSIMD128, // SUB_SAT_S_I16x8 |
| 8653 | CEFBS_HasSIMD128, // SUB_SAT_S_I16x8_S |
| 8654 | CEFBS_HasSIMD128, // SUB_SAT_S_I8x16 |
| 8655 | CEFBS_HasSIMD128, // SUB_SAT_S_I8x16_S |
| 8656 | CEFBS_HasSIMD128, // SUB_SAT_U_I16x8 |
| 8657 | CEFBS_HasSIMD128, // SUB_SAT_U_I16x8_S |
| 8658 | CEFBS_HasSIMD128, // SUB_SAT_U_I8x16 |
| 8659 | CEFBS_HasSIMD128, // SUB_SAT_U_I8x16_S |
| 8660 | CEFBS_HasSIMD128, // SWIZZLE |
| 8661 | CEFBS_HasSIMD128, // SWIZZLE_S |
| 8662 | CEFBS_HasReferenceTypes, // TABLE_COPY |
| 8663 | CEFBS_HasReferenceTypes, // TABLE_COPY_S |
| 8664 | CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_FILL_EXNREF |
| 8665 | CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_FILL_EXNREF_S |
| 8666 | CEFBS_HasReferenceTypes, // TABLE_FILL_EXTERNREF |
| 8667 | CEFBS_HasReferenceTypes, // TABLE_FILL_EXTERNREF_S |
| 8668 | CEFBS_HasReferenceTypes, // TABLE_FILL_FUNCREF |
| 8669 | CEFBS_HasReferenceTypes, // TABLE_FILL_FUNCREF_S |
| 8670 | CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_GET_EXNREF |
| 8671 | CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_GET_EXNREF_S |
| 8672 | CEFBS_HasReferenceTypes, // TABLE_GET_EXTERNREF |
| 8673 | CEFBS_HasReferenceTypes, // TABLE_GET_EXTERNREF_S |
| 8674 | CEFBS_HasReferenceTypes, // TABLE_GET_FUNCREF |
| 8675 | CEFBS_HasReferenceTypes, // TABLE_GET_FUNCREF_S |
| 8676 | CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_GROW_EXNREF |
| 8677 | CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_GROW_EXNREF_S |
| 8678 | CEFBS_HasReferenceTypes, // TABLE_GROW_EXTERNREF |
| 8679 | CEFBS_HasReferenceTypes, // TABLE_GROW_EXTERNREF_S |
| 8680 | CEFBS_HasReferenceTypes, // TABLE_GROW_FUNCREF |
| 8681 | CEFBS_HasReferenceTypes, // TABLE_GROW_FUNCREF_S |
| 8682 | CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_SET_EXNREF |
| 8683 | CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_SET_EXNREF_S |
| 8684 | CEFBS_HasReferenceTypes, // TABLE_SET_EXTERNREF |
| 8685 | CEFBS_HasReferenceTypes, // TABLE_SET_EXTERNREF_S |
| 8686 | CEFBS_HasReferenceTypes, // TABLE_SET_FUNCREF |
| 8687 | CEFBS_HasReferenceTypes, // TABLE_SET_FUNCREF_S |
| 8688 | CEFBS_HasReferenceTypes, // TABLE_SIZE |
| 8689 | CEFBS_HasReferenceTypes, // TABLE_SIZE_S |
| 8690 | CEFBS_HasReferenceTypes_HasExceptionHandling, // TEE_EXNREF |
| 8691 | CEFBS_HasReferenceTypes_HasExceptionHandling, // TEE_EXNREF_S |
| 8692 | CEFBS_HasReferenceTypes, // TEE_EXTERNREF |
| 8693 | CEFBS_HasReferenceTypes, // TEE_EXTERNREF_S |
| 8694 | CEFBS_None, // TEE_F32 |
| 8695 | CEFBS_None, // TEE_F32_S |
| 8696 | CEFBS_None, // TEE_F64 |
| 8697 | CEFBS_None, // TEE_F64_S |
| 8698 | CEFBS_HasReferenceTypes, // TEE_FUNCREF |
| 8699 | CEFBS_HasReferenceTypes, // TEE_FUNCREF_S |
| 8700 | CEFBS_None, // TEE_I32 |
| 8701 | CEFBS_None, // TEE_I32_S |
| 8702 | CEFBS_None, // TEE_I64 |
| 8703 | CEFBS_None, // TEE_I64_S |
| 8704 | CEFBS_HasSIMD128, // TEE_V128 |
| 8705 | CEFBS_HasSIMD128, // TEE_V128_S |
| 8706 | CEFBS_HasExceptionHandling, // THROW |
| 8707 | CEFBS_HasExceptionHandling, // THROW_REF |
| 8708 | CEFBS_HasExceptionHandling, // THROW_REF_S |
| 8709 | CEFBS_HasExceptionHandling, // THROW_S |
| 8710 | CEFBS_HasSIMD128_HasFP16, // TRUNC_F16x8 |
| 8711 | CEFBS_HasSIMD128_HasFP16, // TRUNC_F16x8_S |
| 8712 | CEFBS_None, // TRUNC_F32 |
| 8713 | CEFBS_None, // TRUNC_F32_S |
| 8714 | CEFBS_HasSIMD128, // TRUNC_F32x4 |
| 8715 | CEFBS_HasSIMD128, // TRUNC_F32x4_S |
| 8716 | CEFBS_None, // TRUNC_F64 |
| 8717 | CEFBS_None, // TRUNC_F64_S |
| 8718 | CEFBS_HasSIMD128, // TRUNC_F64x2 |
| 8719 | CEFBS_HasSIMD128, // TRUNC_F64x2_S |
| 8720 | CEFBS_HasExceptionHandling, // TRY |
| 8721 | CEFBS_HasExceptionHandling, // TRY_S |
| 8722 | CEFBS_HasExceptionHandling, // TRY_TABLE |
| 8723 | CEFBS_HasExceptionHandling, // TRY_TABLE_S |
| 8724 | CEFBS_None, // UNREACHABLE |
| 8725 | CEFBS_None, // UNREACHABLE_S |
| 8726 | CEFBS_HasSIMD128, // XOR |
| 8727 | CEFBS_None, // XOR_I32 |
| 8728 | CEFBS_None, // XOR_I32_S |
| 8729 | CEFBS_None, // XOR_I64 |
| 8730 | CEFBS_None, // XOR_I64_S |
| 8731 | CEFBS_HasSIMD128, // XOR_S |
| 8732 | CEFBS_None, // anonymous_14793MEMORY_GROW_A32 |
| 8733 | CEFBS_None, // anonymous_14793MEMORY_GROW_A32_S |
| 8734 | CEFBS_None, // anonymous_14793MEMORY_SIZE_A32 |
| 8735 | CEFBS_None, // anonymous_14793MEMORY_SIZE_A32_S |
| 8736 | CEFBS_None, // anonymous_14794MEMORY_GROW_A64 |
| 8737 | CEFBS_None, // anonymous_14794MEMORY_GROW_A64_S |
| 8738 | CEFBS_None, // anonymous_14794MEMORY_SIZE_A64 |
| 8739 | CEFBS_None, // anonymous_14794MEMORY_SIZE_A64_S |
| 8740 | CEFBS_HasSIMD128, // convert_low_s_F64x2 |
| 8741 | CEFBS_HasSIMD128, // convert_low_s_F64x2_S |
| 8742 | CEFBS_HasSIMD128, // convert_low_u_F64x2 |
| 8743 | CEFBS_HasSIMD128, // convert_low_u_F64x2_S |
| 8744 | CEFBS_HasSIMD128_HasFP16, // demote_zero_F16x8 |
| 8745 | CEFBS_HasSIMD128_HasFP16, // demote_zero_F16x8_S |
| 8746 | CEFBS_HasSIMD128, // demote_zero_F32x4 |
| 8747 | CEFBS_HasSIMD128, // demote_zero_F32x4_S |
| 8748 | CEFBS_HasSIMD128, // extadd_pairwise_s_I16x8 |
| 8749 | CEFBS_HasSIMD128, // extadd_pairwise_s_I16x8_S |
| 8750 | CEFBS_HasSIMD128, // extadd_pairwise_s_I32x4 |
| 8751 | CEFBS_HasSIMD128, // extadd_pairwise_s_I32x4_S |
| 8752 | CEFBS_HasSIMD128, // extadd_pairwise_u_I16x8 |
| 8753 | CEFBS_HasSIMD128, // extadd_pairwise_u_I16x8_S |
| 8754 | CEFBS_HasSIMD128, // extadd_pairwise_u_I32x4 |
| 8755 | CEFBS_HasSIMD128, // extadd_pairwise_u_I32x4_S |
| 8756 | CEFBS_HasSIMD128, // extend_high_s_I16x8 |
| 8757 | CEFBS_HasSIMD128, // extend_high_s_I16x8_S |
| 8758 | CEFBS_HasSIMD128, // extend_high_s_I32x4 |
| 8759 | CEFBS_HasSIMD128, // extend_high_s_I32x4_S |
| 8760 | CEFBS_HasSIMD128, // extend_high_s_I64x2 |
| 8761 | CEFBS_HasSIMD128, // extend_high_s_I64x2_S |
| 8762 | CEFBS_HasSIMD128, // extend_high_u_I16x8 |
| 8763 | CEFBS_HasSIMD128, // extend_high_u_I16x8_S |
| 8764 | CEFBS_HasSIMD128, // extend_high_u_I32x4 |
| 8765 | CEFBS_HasSIMD128, // extend_high_u_I32x4_S |
| 8766 | CEFBS_HasSIMD128, // extend_high_u_I64x2 |
| 8767 | CEFBS_HasSIMD128, // extend_high_u_I64x2_S |
| 8768 | CEFBS_HasSIMD128, // extend_low_s_I16x8 |
| 8769 | CEFBS_HasSIMD128, // extend_low_s_I16x8_S |
| 8770 | CEFBS_HasSIMD128, // extend_low_s_I32x4 |
| 8771 | CEFBS_HasSIMD128, // extend_low_s_I32x4_S |
| 8772 | CEFBS_HasSIMD128, // extend_low_s_I64x2 |
| 8773 | CEFBS_HasSIMD128, // extend_low_s_I64x2_S |
| 8774 | CEFBS_HasSIMD128, // extend_low_u_I16x8 |
| 8775 | CEFBS_HasSIMD128, // extend_low_u_I16x8_S |
| 8776 | CEFBS_HasSIMD128, // extend_low_u_I32x4 |
| 8777 | CEFBS_HasSIMD128, // extend_low_u_I32x4_S |
| 8778 | CEFBS_HasSIMD128, // extend_low_u_I64x2 |
| 8779 | CEFBS_HasSIMD128, // extend_low_u_I64x2_S |
| 8780 | CEFBS_HasSIMD128_HasFP16, // fp_to_sint_I16x8 |
| 8781 | CEFBS_HasSIMD128_HasFP16, // fp_to_sint_I16x8_S |
| 8782 | CEFBS_HasSIMD128, // fp_to_sint_I32x4 |
| 8783 | CEFBS_HasSIMD128, // fp_to_sint_I32x4_S |
| 8784 | CEFBS_HasSIMD128_HasFP16, // fp_to_uint_I16x8 |
| 8785 | CEFBS_HasSIMD128_HasFP16, // fp_to_uint_I16x8_S |
| 8786 | CEFBS_HasSIMD128, // fp_to_uint_I32x4 |
| 8787 | CEFBS_HasSIMD128, // fp_to_uint_I32x4_S |
| 8788 | CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_signed_I32x4 |
| 8789 | CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_signed_I32x4_S |
| 8790 | CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_signed_zero_I32x4 |
| 8791 | CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_signed_zero_I32x4_S |
| 8792 | CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_unsigned_I32x4 |
| 8793 | CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_unsigned_I32x4_S |
| 8794 | CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_unsigned_zero_I32x4 |
| 8795 | CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_unsigned_zero_I32x4_S |
| 8796 | CEFBS_HasSIMD128_HasFP16, // promote_low_F32x4 |
| 8797 | CEFBS_HasSIMD128_HasFP16, // promote_low_F32x4_S |
| 8798 | CEFBS_HasSIMD128, // promote_low_F64x2 |
| 8799 | CEFBS_HasSIMD128, // promote_low_F64x2_S |
| 8800 | CEFBS_HasSIMD128_HasFP16, // sint_to_fp_F16x8 |
| 8801 | CEFBS_HasSIMD128_HasFP16, // sint_to_fp_F16x8_S |
| 8802 | CEFBS_HasSIMD128, // sint_to_fp_F32x4 |
| 8803 | CEFBS_HasSIMD128, // sint_to_fp_F32x4_S |
| 8804 | CEFBS_HasSIMD128, // trunc_sat_zero_s_I32x4 |
| 8805 | CEFBS_HasSIMD128, // trunc_sat_zero_s_I32x4_S |
| 8806 | CEFBS_HasSIMD128, // trunc_sat_zero_u_I32x4 |
| 8807 | CEFBS_HasSIMD128, // trunc_sat_zero_u_I32x4_S |
| 8808 | CEFBS_HasSIMD128_HasFP16, // uint_to_fp_F16x8 |
| 8809 | CEFBS_HasSIMD128_HasFP16, // uint_to_fp_F16x8_S |
| 8810 | CEFBS_HasSIMD128, // uint_to_fp_F32x4 |
| 8811 | CEFBS_HasSIMD128, // uint_to_fp_F32x4_S |
| 8812 | }; |
| 8813 | |
| 8814 | assert(Opcode < 1980); |
| 8815 | return FeatureBitsets[RequiredFeaturesRefs[Opcode]]; |
| 8816 | } |
| 8817 | |
| 8818 | |
| 8819 | } // namespace llvm::WebAssembly_MC |
| 8820 | |
| 8821 | #endif // GET_COMPUTE_FEATURES |
| 8822 | |
| 8823 | #ifdef GET_AVAILABLE_OPCODE_CHECKER |
| 8824 | #undef GET_AVAILABLE_OPCODE_CHECKER |
| 8825 | |
| 8826 | namespace llvm::WebAssembly_MC { |
| 8827 | |
| 8828 | bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) { |
| 8829 | FeatureBitset AvailableFeatures = computeAvailableFeatures(Features); |
| 8830 | FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode); |
| 8831 | FeatureBitset MissingFeatures = |
| 8832 | (AvailableFeatures & RequiredFeatures) ^ |
| 8833 | RequiredFeatures; |
| 8834 | return !MissingFeatures.any(); |
| 8835 | } |
| 8836 | |
| 8837 | } // namespace llvm::WebAssembly_MC |
| 8838 | |
| 8839 | #endif // GET_AVAILABLE_OPCODE_CHECKER |
| 8840 | |
| 8841 | #ifdef ENABLE_INSTR_PREDICATE_VERIFIER |
| 8842 | #undef ENABLE_INSTR_PREDICATE_VERIFIER |
| 8843 | |
| 8844 | #include <sstream> |
| 8845 | |
| 8846 | namespace llvm::WebAssembly_MC { |
| 8847 | |
| 8848 | #ifndef NDEBUG |
| 8849 | static const char *SubtargetFeatureNames[] = { |
| 8850 | "Feature_HasAtomics", |
| 8851 | "Feature_HasBulkMemory", |
| 8852 | "Feature_HasBulkMemoryOpt", |
| 8853 | "Feature_HasCallIndirectOverlong", |
| 8854 | "Feature_HasExceptionHandling", |
| 8855 | "Feature_HasExtendedConst", |
| 8856 | "Feature_HasFP16", |
| 8857 | "Feature_HasGC", |
| 8858 | "Feature_HasMultiMemory", |
| 8859 | "Feature_HasMultivalue", |
| 8860 | "Feature_HasMutableGlobals", |
| 8861 | "Feature_HasNontrappingFPToInt", |
| 8862 | "Feature_HasReferenceTypes", |
| 8863 | "Feature_HasRelaxedAtomics", |
| 8864 | "Feature_HasRelaxedSIMD", |
| 8865 | "Feature_HasSIMD128", |
| 8866 | "Feature_HasSignExt", |
| 8867 | "Feature_HasTailCall", |
| 8868 | "Feature_HasWideArithmetic", |
| 8869 | "Feature_NotHasNontrappingFPToInt", |
| 8870 | nullptr |
| 8871 | }; |
| 8872 | |
| 8873 | #endif // NDEBUG |
| 8874 | |
| 8875 | void verifyInstructionPredicates( |
| 8876 | unsigned Opcode, const FeatureBitset &Features) { |
| 8877 | #ifndef NDEBUG |
| 8878 | FeatureBitset AvailableFeatures = computeAvailableFeatures(Features); |
| 8879 | FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode); |
| 8880 | FeatureBitset MissingFeatures = |
| 8881 | (AvailableFeatures & RequiredFeatures) ^ |
| 8882 | RequiredFeatures; |
| 8883 | if (MissingFeatures.any()) { |
| 8884 | std::ostringstream Msg; |
| 8885 | Msg << "Attempting to emit "<< &WebAssemblyInstrNameData[WebAssemblyInstrNameIndices[Opcode]] |
| 8886 | << " instruction but the "; |
| 8887 | for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i) |
| 8888 | if (MissingFeatures.test(i)) |
| 8889 | Msg << SubtargetFeatureNames[i] << " "; |
| 8890 | Msg << "predicate(s) are not met"; |
| 8891 | report_fatal_error(Msg.str().c_str()); |
| 8892 | } |
| 8893 | #endif // NDEBUG |
| 8894 | } |
| 8895 | |
| 8896 | } // namespace llvm::WebAssembly_MC |
| 8897 | |
| 8898 | #endif // ENABLE_INSTR_PREDICATE_VERIFIER |
| 8899 | |
| 8900 | #ifdef GET_INSTRMAP_INFO |
| 8901 | #undef GET_INSTRMAP_INFO |
| 8902 | |
| 8903 | namespace llvm::WebAssembly { |
| 8904 | |
| 8905 | enum IsWasm64 { |
| 8906 | IsWasm64_1 |
| 8907 | }; |
| 8908 | |
| 8909 | enum StackBased { |
| 8910 | StackBased_0, |
| 8911 | StackBased_1 |
| 8912 | }; |
| 8913 | |
| 8914 | // getRegisterOpcode |
| 8915 | LLVM_READONLY |
| 8916 | int32_t getRegisterOpcode(uint32_t Opcode) { |
| 8917 | using namespace WebAssembly; |
| 8918 | static constexpr uint32_t Table[][2] = { |
| 8919 | { CALL_PARAMS_S, CALL_PARAMS }, |
| 8920 | { CALL_RESULTS_S, CALL_RESULTS }, |
| 8921 | { CATCHRET_S, CATCHRET }, |
| 8922 | { CLEANUPRET_S, CLEANUPRET }, |
| 8923 | { COMPILER_FENCE_S, COMPILER_FENCE }, |
| 8924 | { RET_CALL_RESULTS_S, RET_CALL_RESULTS }, |
| 8925 | { ABS_F16x8_S, ABS_F16x8 }, |
| 8926 | { ABS_F32_S, ABS_F32 }, |
| 8927 | { ABS_F32x4_S, ABS_F32x4 }, |
| 8928 | { ABS_F64_S, ABS_F64 }, |
| 8929 | { ABS_F64x2_S, ABS_F64x2 }, |
| 8930 | { ABS_I16x8_S, ABS_I16x8 }, |
| 8931 | { ABS_I32x4_S, ABS_I32x4 }, |
| 8932 | { ABS_I64x2_S, ABS_I64x2 }, |
| 8933 | { ABS_I8x16_S, ABS_I8x16 }, |
| 8934 | { ADD_F16x8_S, ADD_F16x8 }, |
| 8935 | { ADD_F32_S, ADD_F32 }, |
| 8936 | { ADD_F32x4_S, ADD_F32x4 }, |
| 8937 | { ADD_F64_S, ADD_F64 }, |
| 8938 | { ADD_F64x2_S, ADD_F64x2 }, |
| 8939 | { ADD_I16x8_S, ADD_I16x8 }, |
| 8940 | { ADD_I32_S, ADD_I32 }, |
| 8941 | { ADD_I32x4_S, ADD_I32x4 }, |
| 8942 | { ADD_I64_S, ADD_I64 }, |
| 8943 | { ADD_I64x2_S, ADD_I64x2 }, |
| 8944 | { ADD_I8x16_S, ADD_I8x16 }, |
| 8945 | { ADD_SAT_S_I16x8_S, ADD_SAT_S_I16x8 }, |
| 8946 | { ADD_SAT_S_I8x16_S, ADD_SAT_S_I8x16 }, |
| 8947 | { ADD_SAT_U_I16x8_S, ADD_SAT_U_I16x8 }, |
| 8948 | { ADD_SAT_U_I8x16_S, ADD_SAT_U_I8x16 }, |
| 8949 | { ADJCALLSTACKDOWN_S, ADJCALLSTACKDOWN }, |
| 8950 | { ADJCALLSTACKUP_S, ADJCALLSTACKUP }, |
| 8951 | { ALLTRUE_I16x8_S, ALLTRUE_I16x8 }, |
| 8952 | { ALLTRUE_I32x4_S, ALLTRUE_I32x4 }, |
| 8953 | { ALLTRUE_I64x2_S, ALLTRUE_I64x2 }, |
| 8954 | { ALLTRUE_I8x16_S, ALLTRUE_I8x16 }, |
| 8955 | { ANDNOT_S, ANDNOT }, |
| 8956 | { AND_I32_S, AND_I32 }, |
| 8957 | { AND_I64_S, AND_I64 }, |
| 8958 | { AND_S, AND }, |
| 8959 | { ANYTRUE_S, ANYTRUE }, |
| 8960 | { ARGUMENT_exnref_S, ARGUMENT_exnref }, |
| 8961 | { ARGUMENT_externref_S, ARGUMENT_externref }, |
| 8962 | { ARGUMENT_f32_S, ARGUMENT_f32 }, |
| 8963 | { ARGUMENT_f64_S, ARGUMENT_f64 }, |
| 8964 | { ARGUMENT_funcref_S, ARGUMENT_funcref }, |
| 8965 | { ARGUMENT_i32_S, ARGUMENT_i32 }, |
| 8966 | { ARGUMENT_i64_S, ARGUMENT_i64 }, |
| 8967 | { ARGUMENT_v16i8_S, ARGUMENT_v16i8 }, |
| 8968 | { ARGUMENT_v2f64_S, ARGUMENT_v2f64 }, |
| 8969 | { ARGUMENT_v2i64_S, ARGUMENT_v2i64 }, |
| 8970 | { ARGUMENT_v4f32_S, ARGUMENT_v4f32 }, |
| 8971 | { ARGUMENT_v4i32_S, ARGUMENT_v4i32 }, |
| 8972 | { ARGUMENT_v8f16_S, ARGUMENT_v8f16 }, |
| 8973 | { ARGUMENT_v8i16_S, ARGUMENT_v8i16 }, |
| 8974 | { ATOMIC_FENCE_S, ATOMIC_FENCE }, |
| 8975 | { ATOMIC_LOAD16_U_I32_A32_S, ATOMIC_LOAD16_U_I32_A32 }, |
| 8976 | { ATOMIC_LOAD16_U_I32_A64_S, ATOMIC_LOAD16_U_I32_A64 }, |
| 8977 | { ATOMIC_LOAD16_U_I64_A32_S, ATOMIC_LOAD16_U_I64_A32 }, |
| 8978 | { ATOMIC_LOAD16_U_I64_A64_S, ATOMIC_LOAD16_U_I64_A64 }, |
| 8979 | { ATOMIC_LOAD32_U_I64_A32_S, ATOMIC_LOAD32_U_I64_A32 }, |
| 8980 | { ATOMIC_LOAD32_U_I64_A64_S, ATOMIC_LOAD32_U_I64_A64 }, |
| 8981 | { ATOMIC_LOAD8_U_I32_A32_S, ATOMIC_LOAD8_U_I32_A32 }, |
| 8982 | { ATOMIC_LOAD8_U_I32_A64_S, ATOMIC_LOAD8_U_I32_A64 }, |
| 8983 | { ATOMIC_LOAD8_U_I64_A32_S, ATOMIC_LOAD8_U_I64_A32 }, |
| 8984 | { ATOMIC_LOAD8_U_I64_A64_S, ATOMIC_LOAD8_U_I64_A64 }, |
| 8985 | { ATOMIC_LOAD_I32_A32_S, ATOMIC_LOAD_I32_A32 }, |
| 8986 | { ATOMIC_LOAD_I32_A64_S, ATOMIC_LOAD_I32_A64 }, |
| 8987 | { ATOMIC_LOAD_I64_A32_S, ATOMIC_LOAD_I64_A32 }, |
| 8988 | { ATOMIC_LOAD_I64_A64_S, ATOMIC_LOAD_I64_A64 }, |
| 8989 | { ATOMIC_RMW16_U_ADD_I32_A32_S, ATOMIC_RMW16_U_ADD_I32_A32 }, |
| 8990 | { ATOMIC_RMW16_U_ADD_I32_A64_S, ATOMIC_RMW16_U_ADD_I32_A64 }, |
| 8991 | { ATOMIC_RMW16_U_ADD_I64_A32_S, ATOMIC_RMW16_U_ADD_I64_A32 }, |
| 8992 | { ATOMIC_RMW16_U_ADD_I64_A64_S, ATOMIC_RMW16_U_ADD_I64_A64 }, |
| 8993 | { ATOMIC_RMW16_U_AND_I32_A32_S, ATOMIC_RMW16_U_AND_I32_A32 }, |
| 8994 | { ATOMIC_RMW16_U_AND_I32_A64_S, ATOMIC_RMW16_U_AND_I32_A64 }, |
| 8995 | { ATOMIC_RMW16_U_AND_I64_A32_S, ATOMIC_RMW16_U_AND_I64_A32 }, |
| 8996 | { ATOMIC_RMW16_U_AND_I64_A64_S, ATOMIC_RMW16_U_AND_I64_A64 }, |
| 8997 | { ATOMIC_RMW16_U_CMPXCHG_I32_A32_S, ATOMIC_RMW16_U_CMPXCHG_I32_A32 }, |
| 8998 | { ATOMIC_RMW16_U_CMPXCHG_I32_A64_S, ATOMIC_RMW16_U_CMPXCHG_I32_A64 }, |
| 8999 | { ATOMIC_RMW16_U_CMPXCHG_I64_A32_S, ATOMIC_RMW16_U_CMPXCHG_I64_A32 }, |
| 9000 | { ATOMIC_RMW16_U_CMPXCHG_I64_A64_S, ATOMIC_RMW16_U_CMPXCHG_I64_A64 }, |
| 9001 | { ATOMIC_RMW16_U_OR_I32_A32_S, ATOMIC_RMW16_U_OR_I32_A32 }, |
| 9002 | { ATOMIC_RMW16_U_OR_I32_A64_S, ATOMIC_RMW16_U_OR_I32_A64 }, |
| 9003 | { ATOMIC_RMW16_U_OR_I64_A32_S, ATOMIC_RMW16_U_OR_I64_A32 }, |
| 9004 | { ATOMIC_RMW16_U_OR_I64_A64_S, ATOMIC_RMW16_U_OR_I64_A64 }, |
| 9005 | { ATOMIC_RMW16_U_SUB_I32_A32_S, ATOMIC_RMW16_U_SUB_I32_A32 }, |
| 9006 | { ATOMIC_RMW16_U_SUB_I32_A64_S, ATOMIC_RMW16_U_SUB_I32_A64 }, |
| 9007 | { ATOMIC_RMW16_U_SUB_I64_A32_S, ATOMIC_RMW16_U_SUB_I64_A32 }, |
| 9008 | { ATOMIC_RMW16_U_SUB_I64_A64_S, ATOMIC_RMW16_U_SUB_I64_A64 }, |
| 9009 | { ATOMIC_RMW16_U_XCHG_I32_A32_S, ATOMIC_RMW16_U_XCHG_I32_A32 }, |
| 9010 | { ATOMIC_RMW16_U_XCHG_I32_A64_S, ATOMIC_RMW16_U_XCHG_I32_A64 }, |
| 9011 | { ATOMIC_RMW16_U_XCHG_I64_A32_S, ATOMIC_RMW16_U_XCHG_I64_A32 }, |
| 9012 | { ATOMIC_RMW16_U_XCHG_I64_A64_S, ATOMIC_RMW16_U_XCHG_I64_A64 }, |
| 9013 | { ATOMIC_RMW16_U_XOR_I32_A32_S, ATOMIC_RMW16_U_XOR_I32_A32 }, |
| 9014 | { ATOMIC_RMW16_U_XOR_I32_A64_S, ATOMIC_RMW16_U_XOR_I32_A64 }, |
| 9015 | { ATOMIC_RMW16_U_XOR_I64_A32_S, ATOMIC_RMW16_U_XOR_I64_A32 }, |
| 9016 | { ATOMIC_RMW16_U_XOR_I64_A64_S, ATOMIC_RMW16_U_XOR_I64_A64 }, |
| 9017 | { ATOMIC_RMW32_U_ADD_I64_A32_S, ATOMIC_RMW32_U_ADD_I64_A32 }, |
| 9018 | { ATOMIC_RMW32_U_ADD_I64_A64_S, ATOMIC_RMW32_U_ADD_I64_A64 }, |
| 9019 | { ATOMIC_RMW32_U_AND_I64_A32_S, ATOMIC_RMW32_U_AND_I64_A32 }, |
| 9020 | { ATOMIC_RMW32_U_AND_I64_A64_S, ATOMIC_RMW32_U_AND_I64_A64 }, |
| 9021 | { ATOMIC_RMW32_U_CMPXCHG_I64_A32_S, ATOMIC_RMW32_U_CMPXCHG_I64_A32 }, |
| 9022 | { ATOMIC_RMW32_U_CMPXCHG_I64_A64_S, ATOMIC_RMW32_U_CMPXCHG_I64_A64 }, |
| 9023 | { ATOMIC_RMW32_U_OR_I64_A32_S, ATOMIC_RMW32_U_OR_I64_A32 }, |
| 9024 | { ATOMIC_RMW32_U_OR_I64_A64_S, ATOMIC_RMW32_U_OR_I64_A64 }, |
| 9025 | { ATOMIC_RMW32_U_SUB_I64_A32_S, ATOMIC_RMW32_U_SUB_I64_A32 }, |
| 9026 | { ATOMIC_RMW32_U_SUB_I64_A64_S, ATOMIC_RMW32_U_SUB_I64_A64 }, |
| 9027 | { ATOMIC_RMW32_U_XCHG_I64_A32_S, ATOMIC_RMW32_U_XCHG_I64_A32 }, |
| 9028 | { ATOMIC_RMW32_U_XCHG_I64_A64_S, ATOMIC_RMW32_U_XCHG_I64_A64 }, |
| 9029 | { ATOMIC_RMW32_U_XOR_I64_A32_S, ATOMIC_RMW32_U_XOR_I64_A32 }, |
| 9030 | { ATOMIC_RMW32_U_XOR_I64_A64_S, ATOMIC_RMW32_U_XOR_I64_A64 }, |
| 9031 | { ATOMIC_RMW8_U_ADD_I32_A32_S, ATOMIC_RMW8_U_ADD_I32_A32 }, |
| 9032 | { ATOMIC_RMW8_U_ADD_I32_A64_S, ATOMIC_RMW8_U_ADD_I32_A64 }, |
| 9033 | { ATOMIC_RMW8_U_ADD_I64_A32_S, ATOMIC_RMW8_U_ADD_I64_A32 }, |
| 9034 | { ATOMIC_RMW8_U_ADD_I64_A64_S, ATOMIC_RMW8_U_ADD_I64_A64 }, |
| 9035 | { ATOMIC_RMW8_U_AND_I32_A32_S, ATOMIC_RMW8_U_AND_I32_A32 }, |
| 9036 | { ATOMIC_RMW8_U_AND_I32_A64_S, ATOMIC_RMW8_U_AND_I32_A64 }, |
| 9037 | { ATOMIC_RMW8_U_AND_I64_A32_S, ATOMIC_RMW8_U_AND_I64_A32 }, |
| 9038 | { ATOMIC_RMW8_U_AND_I64_A64_S, ATOMIC_RMW8_U_AND_I64_A64 }, |
| 9039 | { ATOMIC_RMW8_U_CMPXCHG_I32_A32_S, ATOMIC_RMW8_U_CMPXCHG_I32_A32 }, |
| 9040 | { ATOMIC_RMW8_U_CMPXCHG_I32_A64_S, ATOMIC_RMW8_U_CMPXCHG_I32_A64 }, |
| 9041 | { ATOMIC_RMW8_U_CMPXCHG_I64_A32_S, ATOMIC_RMW8_U_CMPXCHG_I64_A32 }, |
| 9042 | { ATOMIC_RMW8_U_CMPXCHG_I64_A64_S, ATOMIC_RMW8_U_CMPXCHG_I64_A64 }, |
| 9043 | { ATOMIC_RMW8_U_OR_I32_A32_S, ATOMIC_RMW8_U_OR_I32_A32 }, |
| 9044 | { ATOMIC_RMW8_U_OR_I32_A64_S, ATOMIC_RMW8_U_OR_I32_A64 }, |
| 9045 | { ATOMIC_RMW8_U_OR_I64_A32_S, ATOMIC_RMW8_U_OR_I64_A32 }, |
| 9046 | { ATOMIC_RMW8_U_OR_I64_A64_S, ATOMIC_RMW8_U_OR_I64_A64 }, |
| 9047 | { ATOMIC_RMW8_U_SUB_I32_A32_S, ATOMIC_RMW8_U_SUB_I32_A32 }, |
| 9048 | { ATOMIC_RMW8_U_SUB_I32_A64_S, ATOMIC_RMW8_U_SUB_I32_A64 }, |
| 9049 | { ATOMIC_RMW8_U_SUB_I64_A32_S, ATOMIC_RMW8_U_SUB_I64_A32 }, |
| 9050 | { ATOMIC_RMW8_U_SUB_I64_A64_S, ATOMIC_RMW8_U_SUB_I64_A64 }, |
| 9051 | { ATOMIC_RMW8_U_XCHG_I32_A32_S, ATOMIC_RMW8_U_XCHG_I32_A32 }, |
| 9052 | { ATOMIC_RMW8_U_XCHG_I32_A64_S, ATOMIC_RMW8_U_XCHG_I32_A64 }, |
| 9053 | { ATOMIC_RMW8_U_XCHG_I64_A32_S, ATOMIC_RMW8_U_XCHG_I64_A32 }, |
| 9054 | { ATOMIC_RMW8_U_XCHG_I64_A64_S, ATOMIC_RMW8_U_XCHG_I64_A64 }, |
| 9055 | { ATOMIC_RMW8_U_XOR_I32_A32_S, ATOMIC_RMW8_U_XOR_I32_A32 }, |
| 9056 | { ATOMIC_RMW8_U_XOR_I32_A64_S, ATOMIC_RMW8_U_XOR_I32_A64 }, |
| 9057 | { ATOMIC_RMW8_U_XOR_I64_A32_S, ATOMIC_RMW8_U_XOR_I64_A32 }, |
| 9058 | { ATOMIC_RMW8_U_XOR_I64_A64_S, ATOMIC_RMW8_U_XOR_I64_A64 }, |
| 9059 | { ATOMIC_RMW_ADD_I32_A32_S, ATOMIC_RMW_ADD_I32_A32 }, |
| 9060 | { ATOMIC_RMW_ADD_I32_A64_S, ATOMIC_RMW_ADD_I32_A64 }, |
| 9061 | { ATOMIC_RMW_ADD_I64_A32_S, ATOMIC_RMW_ADD_I64_A32 }, |
| 9062 | { ATOMIC_RMW_ADD_I64_A64_S, ATOMIC_RMW_ADD_I64_A64 }, |
| 9063 | { ATOMIC_RMW_AND_I32_A32_S, ATOMIC_RMW_AND_I32_A32 }, |
| 9064 | { ATOMIC_RMW_AND_I32_A64_S, ATOMIC_RMW_AND_I32_A64 }, |
| 9065 | { ATOMIC_RMW_AND_I64_A32_S, ATOMIC_RMW_AND_I64_A32 }, |
| 9066 | { ATOMIC_RMW_AND_I64_A64_S, ATOMIC_RMW_AND_I64_A64 }, |
| 9067 | { ATOMIC_RMW_CMPXCHG_I32_A32_S, ATOMIC_RMW_CMPXCHG_I32_A32 }, |
| 9068 | { ATOMIC_RMW_CMPXCHG_I32_A64_S, ATOMIC_RMW_CMPXCHG_I32_A64 }, |
| 9069 | { ATOMIC_RMW_CMPXCHG_I64_A32_S, ATOMIC_RMW_CMPXCHG_I64_A32 }, |
| 9070 | { ATOMIC_RMW_CMPXCHG_I64_A64_S, ATOMIC_RMW_CMPXCHG_I64_A64 }, |
| 9071 | { ATOMIC_RMW_OR_I32_A32_S, ATOMIC_RMW_OR_I32_A32 }, |
| 9072 | { ATOMIC_RMW_OR_I32_A64_S, ATOMIC_RMW_OR_I32_A64 }, |
| 9073 | { ATOMIC_RMW_OR_I64_A32_S, ATOMIC_RMW_OR_I64_A32 }, |
| 9074 | { ATOMIC_RMW_OR_I64_A64_S, ATOMIC_RMW_OR_I64_A64 }, |
| 9075 | { ATOMIC_RMW_SUB_I32_A32_S, ATOMIC_RMW_SUB_I32_A32 }, |
| 9076 | { ATOMIC_RMW_SUB_I32_A64_S, ATOMIC_RMW_SUB_I32_A64 }, |
| 9077 | { ATOMIC_RMW_SUB_I64_A32_S, ATOMIC_RMW_SUB_I64_A32 }, |
| 9078 | { ATOMIC_RMW_SUB_I64_A64_S, ATOMIC_RMW_SUB_I64_A64 }, |
| 9079 | { ATOMIC_RMW_XCHG_I32_A32_S, ATOMIC_RMW_XCHG_I32_A32 }, |
| 9080 | { ATOMIC_RMW_XCHG_I32_A64_S, ATOMIC_RMW_XCHG_I32_A64 }, |
| 9081 | { ATOMIC_RMW_XCHG_I64_A32_S, ATOMIC_RMW_XCHG_I64_A32 }, |
| 9082 | { ATOMIC_RMW_XCHG_I64_A64_S, ATOMIC_RMW_XCHG_I64_A64 }, |
| 9083 | { ATOMIC_RMW_XOR_I32_A32_S, ATOMIC_RMW_XOR_I32_A32 }, |
| 9084 | { ATOMIC_RMW_XOR_I32_A64_S, ATOMIC_RMW_XOR_I32_A64 }, |
| 9085 | { ATOMIC_RMW_XOR_I64_A32_S, ATOMIC_RMW_XOR_I64_A32 }, |
| 9086 | { ATOMIC_RMW_XOR_I64_A64_S, ATOMIC_RMW_XOR_I64_A64 }, |
| 9087 | { ATOMIC_STORE16_I32_A32_S, ATOMIC_STORE16_I32_A32 }, |
| 9088 | { ATOMIC_STORE16_I32_A64_S, ATOMIC_STORE16_I32_A64 }, |
| 9089 | { ATOMIC_STORE16_I64_A32_S, ATOMIC_STORE16_I64_A32 }, |
| 9090 | { ATOMIC_STORE16_I64_A64_S, ATOMIC_STORE16_I64_A64 }, |
| 9091 | { ATOMIC_STORE32_I64_A32_S, ATOMIC_STORE32_I64_A32 }, |
| 9092 | { ATOMIC_STORE32_I64_A64_S, ATOMIC_STORE32_I64_A64 }, |
| 9093 | { ATOMIC_STORE8_I32_A32_S, ATOMIC_STORE8_I32_A32 }, |
| 9094 | { ATOMIC_STORE8_I32_A64_S, ATOMIC_STORE8_I32_A64 }, |
| 9095 | { ATOMIC_STORE8_I64_A32_S, ATOMIC_STORE8_I64_A32 }, |
| 9096 | { ATOMIC_STORE8_I64_A64_S, ATOMIC_STORE8_I64_A64 }, |
| 9097 | { ATOMIC_STORE_I32_A32_S, ATOMIC_STORE_I32_A32 }, |
| 9098 | { ATOMIC_STORE_I32_A64_S, ATOMIC_STORE_I32_A64 }, |
| 9099 | { ATOMIC_STORE_I64_A32_S, ATOMIC_STORE_I64_A32 }, |
| 9100 | { ATOMIC_STORE_I64_A64_S, ATOMIC_STORE_I64_A64 }, |
| 9101 | { AVGR_U_I16x8_S, AVGR_U_I16x8 }, |
| 9102 | { AVGR_U_I8x16_S, AVGR_U_I8x16 }, |
| 9103 | { BITMASK_I16x8_S, BITMASK_I16x8 }, |
| 9104 | { BITMASK_I32x4_S, BITMASK_I32x4 }, |
| 9105 | { BITMASK_I64x2_S, BITMASK_I64x2 }, |
| 9106 | { BITMASK_I8x16_S, BITMASK_I8x16 }, |
| 9107 | { BITSELECT_S, BITSELECT }, |
| 9108 | { BLOCK_S, BLOCK }, |
| 9109 | { BR_IF_S, BR_IF }, |
| 9110 | { BR_S, BR }, |
| 9111 | { BR_TABLE_I32_S, BR_TABLE_I32 }, |
| 9112 | { BR_TABLE_I64_S, BR_TABLE_I64 }, |
| 9113 | { BR_UNLESS_S, BR_UNLESS }, |
| 9114 | { CALL_INDIRECT_S, CALL_INDIRECT }, |
| 9115 | { CALL_REF_S, CALL_REF }, |
| 9116 | { CALL_S, CALL }, |
| 9117 | { CATCH_ALL_LEGACY_S, CATCH_ALL_LEGACY }, |
| 9118 | { CATCH_ALL_REF_S, CATCH_ALL_REF }, |
| 9119 | { CATCH_ALL_S, CATCH_ALL }, |
| 9120 | { CATCH_LEGACY_S, CATCH_LEGACY }, |
| 9121 | { CATCH_REF_S, CATCH_REF }, |
| 9122 | { CATCH_S, CATCH }, |
| 9123 | { CEIL_F16x8_S, CEIL_F16x8 }, |
| 9124 | { CEIL_F32_S, CEIL_F32 }, |
| 9125 | { CEIL_F32x4_S, CEIL_F32x4 }, |
| 9126 | { CEIL_F64_S, CEIL_F64 }, |
| 9127 | { CEIL_F64x2_S, CEIL_F64x2 }, |
| 9128 | { CLZ_I32_S, CLZ_I32 }, |
| 9129 | { CLZ_I64_S, CLZ_I64 }, |
| 9130 | { CONST_F32_S, CONST_F32 }, |
| 9131 | { CONST_F64_S, CONST_F64 }, |
| 9132 | { CONST_I32_S, CONST_I32 }, |
| 9133 | { CONST_I64_S, CONST_I64 }, |
| 9134 | { CONST_V128_F32x4_S, CONST_V128_F32x4 }, |
| 9135 | { CONST_V128_F64x2_S, CONST_V128_F64x2 }, |
| 9136 | { CONST_V128_I16x8_S, CONST_V128_I16x8 }, |
| 9137 | { CONST_V128_I32x4_S, CONST_V128_I32x4 }, |
| 9138 | { CONST_V128_I64x2_S, CONST_V128_I64x2 }, |
| 9139 | { CONST_V128_I8x16_S, CONST_V128_I8x16 }, |
| 9140 | { COPYSIGN_F32_S, COPYSIGN_F32 }, |
| 9141 | { COPYSIGN_F64_S, COPYSIGN_F64 }, |
| 9142 | { COPY_EXNREF_S, COPY_EXNREF }, |
| 9143 | { COPY_EXTERNREF_S, COPY_EXTERNREF }, |
| 9144 | { COPY_F32_S, COPY_F32 }, |
| 9145 | { COPY_F64_S, COPY_F64 }, |
| 9146 | { COPY_FUNCREF_S, COPY_FUNCREF }, |
| 9147 | { COPY_I32_S, COPY_I32 }, |
| 9148 | { COPY_I64_S, COPY_I64 }, |
| 9149 | { COPY_V128_S, COPY_V128 }, |
| 9150 | { CTZ_I32_S, CTZ_I32 }, |
| 9151 | { CTZ_I64_S, CTZ_I64 }, |
| 9152 | { DATA_DROP_S, DATA_DROP }, |
| 9153 | { DEBUG_UNREACHABLE_S, DEBUG_UNREACHABLE }, |
| 9154 | { DELEGATE_S, DELEGATE }, |
| 9155 | { DIV_F16x8_S, DIV_F16x8 }, |
| 9156 | { DIV_F32_S, DIV_F32 }, |
| 9157 | { DIV_F32x4_S, DIV_F32x4 }, |
| 9158 | { DIV_F64_S, DIV_F64 }, |
| 9159 | { DIV_F64x2_S, DIV_F64x2 }, |
| 9160 | { DIV_S_I32_S, DIV_S_I32 }, |
| 9161 | { DIV_S_I64_S, DIV_S_I64 }, |
| 9162 | { DIV_U_I32_S, DIV_U_I32 }, |
| 9163 | { DIV_U_I64_S, DIV_U_I64 }, |
| 9164 | { DOT_S, DOT }, |
| 9165 | { DROP_EXNREF_S, DROP_EXNREF }, |
| 9166 | { DROP_EXTERNREF_S, DROP_EXTERNREF }, |
| 9167 | { DROP_F32_S, DROP_F32 }, |
| 9168 | { DROP_F64_S, DROP_F64 }, |
| 9169 | { DROP_FUNCREF_S, DROP_FUNCREF }, |
| 9170 | { DROP_I32_S, DROP_I32 }, |
| 9171 | { DROP_I64_S, DROP_I64 }, |
| 9172 | { DROP_V128_S, DROP_V128 }, |
| 9173 | { ELSE_S, ELSE }, |
| 9174 | { END_BLOCK_S, END_BLOCK }, |
| 9175 | { END_FUNCTION_S, END_FUNCTION }, |
| 9176 | { END_IF_S, END_IF }, |
| 9177 | { END_LOOP_S, END_LOOP }, |
| 9178 | { END_S, END }, |
| 9179 | { END_TRY_S, END_TRY }, |
| 9180 | { END_TRY_TABLE_S, END_TRY_TABLE }, |
| 9181 | { EQZ_I32_S, EQZ_I32 }, |
| 9182 | { EQZ_I64_S, EQZ_I64 }, |
| 9183 | { EQ_F16x8_S, EQ_F16x8 }, |
| 9184 | { EQ_F32_S, EQ_F32 }, |
| 9185 | { EQ_F32x4_S, EQ_F32x4 }, |
| 9186 | { EQ_F64_S, EQ_F64 }, |
| 9187 | { EQ_F64x2_S, EQ_F64x2 }, |
| 9188 | { EQ_I16x8_S, EQ_I16x8 }, |
| 9189 | { EQ_I32_S, EQ_I32 }, |
| 9190 | { EQ_I32x4_S, EQ_I32x4 }, |
| 9191 | { EQ_I64_S, EQ_I64 }, |
| 9192 | { EQ_I64x2_S, EQ_I64x2 }, |
| 9193 | { EQ_I8x16_S, EQ_I8x16 }, |
| 9194 | { EXTMUL_HIGH_S_I16x8_S, EXTMUL_HIGH_S_I16x8 }, |
| 9195 | { EXTMUL_HIGH_S_I32x4_S, EXTMUL_HIGH_S_I32x4 }, |
| 9196 | { EXTMUL_HIGH_S_I64x2_S, EXTMUL_HIGH_S_I64x2 }, |
| 9197 | { EXTMUL_HIGH_U_I16x8_S, EXTMUL_HIGH_U_I16x8 }, |
| 9198 | { EXTMUL_HIGH_U_I32x4_S, EXTMUL_HIGH_U_I32x4 }, |
| 9199 | { EXTMUL_HIGH_U_I64x2_S, EXTMUL_HIGH_U_I64x2 }, |
| 9200 | { EXTMUL_LOW_S_I16x8_S, EXTMUL_LOW_S_I16x8 }, |
| 9201 | { EXTMUL_LOW_S_I32x4_S, EXTMUL_LOW_S_I32x4 }, |
| 9202 | { EXTMUL_LOW_S_I64x2_S, EXTMUL_LOW_S_I64x2 }, |
| 9203 | { EXTMUL_LOW_U_I16x8_S, EXTMUL_LOW_U_I16x8 }, |
| 9204 | { EXTMUL_LOW_U_I32x4_S, EXTMUL_LOW_U_I32x4 }, |
| 9205 | { EXTMUL_LOW_U_I64x2_S, EXTMUL_LOW_U_I64x2 }, |
| 9206 | { EXTRACT_LANE_F16x8_S, EXTRACT_LANE_F16x8 }, |
| 9207 | { EXTRACT_LANE_F32x4_S, EXTRACT_LANE_F32x4 }, |
| 9208 | { EXTRACT_LANE_F64x2_S, EXTRACT_LANE_F64x2 }, |
| 9209 | { EXTRACT_LANE_I16x8_s_S, EXTRACT_LANE_I16x8_s }, |
| 9210 | { EXTRACT_LANE_I16x8_u_S, EXTRACT_LANE_I16x8_u }, |
| 9211 | { EXTRACT_LANE_I32x4_S, EXTRACT_LANE_I32x4 }, |
| 9212 | { EXTRACT_LANE_I64x2_S, EXTRACT_LANE_I64x2 }, |
| 9213 | { EXTRACT_LANE_I8x16_s_S, EXTRACT_LANE_I8x16_s }, |
| 9214 | { EXTRACT_LANE_I8x16_u_S, EXTRACT_LANE_I8x16_u }, |
| 9215 | { F32_CONVERT_S_I32_S, F32_CONVERT_S_I32 }, |
| 9216 | { F32_CONVERT_S_I64_S, F32_CONVERT_S_I64 }, |
| 9217 | { F32_CONVERT_U_I32_S, F32_CONVERT_U_I32 }, |
| 9218 | { F32_CONVERT_U_I64_S, F32_CONVERT_U_I64 }, |
| 9219 | { F32_DEMOTE_F64_S, F32_DEMOTE_F64 }, |
| 9220 | { F32_REINTERPRET_I32_S, F32_REINTERPRET_I32 }, |
| 9221 | { F64_CONVERT_S_I32_S, F64_CONVERT_S_I32 }, |
| 9222 | { F64_CONVERT_S_I64_S, F64_CONVERT_S_I64 }, |
| 9223 | { F64_CONVERT_U_I32_S, F64_CONVERT_U_I32 }, |
| 9224 | { F64_CONVERT_U_I64_S, F64_CONVERT_U_I64 }, |
| 9225 | { F64_PROMOTE_F32_S, F64_PROMOTE_F32 }, |
| 9226 | { F64_REINTERPRET_I64_S, F64_REINTERPRET_I64 }, |
| 9227 | { FALLTHROUGH_RETURN_S, FALLTHROUGH_RETURN }, |
| 9228 | { FLOOR_F16x8_S, FLOOR_F16x8 }, |
| 9229 | { FLOOR_F32_S, FLOOR_F32 }, |
| 9230 | { FLOOR_F32x4_S, FLOOR_F32x4 }, |
| 9231 | { FLOOR_F64_S, FLOOR_F64 }, |
| 9232 | { FLOOR_F64x2_S, FLOOR_F64x2 }, |
| 9233 | { FP_TO_SINT_I32_F32_S, FP_TO_SINT_I32_F32 }, |
| 9234 | { FP_TO_SINT_I32_F64_S, FP_TO_SINT_I32_F64 }, |
| 9235 | { FP_TO_SINT_I64_F32_S, FP_TO_SINT_I64_F32 }, |
| 9236 | { FP_TO_SINT_I64_F64_S, FP_TO_SINT_I64_F64 }, |
| 9237 | { FP_TO_UINT_I32_F32_S, FP_TO_UINT_I32_F32 }, |
| 9238 | { FP_TO_UINT_I32_F64_S, FP_TO_UINT_I32_F64 }, |
| 9239 | { FP_TO_UINT_I64_F32_S, FP_TO_UINT_I64_F32 }, |
| 9240 | { FP_TO_UINT_I64_F64_S, FP_TO_UINT_I64_F64 }, |
| 9241 | { GE_F16x8_S, GE_F16x8 }, |
| 9242 | { GE_F32_S, GE_F32 }, |
| 9243 | { GE_F32x4_S, GE_F32x4 }, |
| 9244 | { GE_F64_S, GE_F64 }, |
| 9245 | { GE_F64x2_S, GE_F64x2 }, |
| 9246 | { GE_S_I16x8_S, GE_S_I16x8 }, |
| 9247 | { GE_S_I32_S, GE_S_I32 }, |
| 9248 | { GE_S_I32x4_S, GE_S_I32x4 }, |
| 9249 | { GE_S_I64_S, GE_S_I64 }, |
| 9250 | { GE_S_I64x2_S, GE_S_I64x2 }, |
| 9251 | { GE_S_I8x16_S, GE_S_I8x16 }, |
| 9252 | { GE_U_I16x8_S, GE_U_I16x8 }, |
| 9253 | { GE_U_I32_S, GE_U_I32 }, |
| 9254 | { GE_U_I32x4_S, GE_U_I32x4 }, |
| 9255 | { GE_U_I64_S, GE_U_I64 }, |
| 9256 | { GE_U_I8x16_S, GE_U_I8x16 }, |
| 9257 | { GLOBAL_GET_EXNREF_S, GLOBAL_GET_EXNREF }, |
| 9258 | { GLOBAL_GET_EXTERNREF_S, GLOBAL_GET_EXTERNREF }, |
| 9259 | { GLOBAL_GET_F32_S, GLOBAL_GET_F32 }, |
| 9260 | { GLOBAL_GET_F64_S, GLOBAL_GET_F64 }, |
| 9261 | { GLOBAL_GET_FUNCREF_S, GLOBAL_GET_FUNCREF }, |
| 9262 | { GLOBAL_GET_I32_S, GLOBAL_GET_I32 }, |
| 9263 | { GLOBAL_GET_I64_S, GLOBAL_GET_I64 }, |
| 9264 | { GLOBAL_GET_V128_S, GLOBAL_GET_V128 }, |
| 9265 | { GLOBAL_SET_EXNREF_S, GLOBAL_SET_EXNREF }, |
| 9266 | { GLOBAL_SET_EXTERNREF_S, GLOBAL_SET_EXTERNREF }, |
| 9267 | { GLOBAL_SET_F32_S, GLOBAL_SET_F32 }, |
| 9268 | { GLOBAL_SET_F64_S, GLOBAL_SET_F64 }, |
| 9269 | { GLOBAL_SET_FUNCREF_S, GLOBAL_SET_FUNCREF }, |
| 9270 | { GLOBAL_SET_I32_S, GLOBAL_SET_I32 }, |
| 9271 | { GLOBAL_SET_I64_S, GLOBAL_SET_I64 }, |
| 9272 | { GLOBAL_SET_V128_S, GLOBAL_SET_V128 }, |
| 9273 | { GT_F16x8_S, GT_F16x8 }, |
| 9274 | { GT_F32_S, GT_F32 }, |
| 9275 | { GT_F32x4_S, GT_F32x4 }, |
| 9276 | { GT_F64_S, GT_F64 }, |
| 9277 | { GT_F64x2_S, GT_F64x2 }, |
| 9278 | { GT_S_I16x8_S, GT_S_I16x8 }, |
| 9279 | { GT_S_I32_S, GT_S_I32 }, |
| 9280 | { GT_S_I32x4_S, GT_S_I32x4 }, |
| 9281 | { GT_S_I64_S, GT_S_I64 }, |
| 9282 | { GT_S_I64x2_S, GT_S_I64x2 }, |
| 9283 | { GT_S_I8x16_S, GT_S_I8x16 }, |
| 9284 | { GT_U_I16x8_S, GT_U_I16x8 }, |
| 9285 | { GT_U_I32_S, GT_U_I32 }, |
| 9286 | { GT_U_I32x4_S, GT_U_I32x4 }, |
| 9287 | { GT_U_I64_S, GT_U_I64 }, |
| 9288 | { GT_U_I8x16_S, GT_U_I8x16 }, |
| 9289 | { I32_EXTEND16_S_I32_S, I32_EXTEND16_S_I32 }, |
| 9290 | { I32_EXTEND8_S_I32_S, I32_EXTEND8_S_I32 }, |
| 9291 | { I32_REINTERPRET_F32_S, I32_REINTERPRET_F32 }, |
| 9292 | { I32_TRUNC_S_F32_S, I32_TRUNC_S_F32 }, |
| 9293 | { I32_TRUNC_S_F64_S, I32_TRUNC_S_F64 }, |
| 9294 | { I32_TRUNC_S_SAT_F32_S, I32_TRUNC_S_SAT_F32 }, |
| 9295 | { I32_TRUNC_S_SAT_F64_S, I32_TRUNC_S_SAT_F64 }, |
| 9296 | { I32_TRUNC_U_F32_S, I32_TRUNC_U_F32 }, |
| 9297 | { I32_TRUNC_U_F64_S, I32_TRUNC_U_F64 }, |
| 9298 | { I32_TRUNC_U_SAT_F32_S, I32_TRUNC_U_SAT_F32 }, |
| 9299 | { I32_TRUNC_U_SAT_F64_S, I32_TRUNC_U_SAT_F64 }, |
| 9300 | { I32_WRAP_I64_S, I32_WRAP_I64 }, |
| 9301 | { I64_ADD128_S, I64_ADD128 }, |
| 9302 | { I64_EXTEND16_S_I64_S, I64_EXTEND16_S_I64 }, |
| 9303 | { I64_EXTEND32_S_I64_S, I64_EXTEND32_S_I64 }, |
| 9304 | { I64_EXTEND8_S_I64_S, I64_EXTEND8_S_I64 }, |
| 9305 | { I64_EXTEND_S_I32_S, I64_EXTEND_S_I32 }, |
| 9306 | { I64_EXTEND_U_I32_S, I64_EXTEND_U_I32 }, |
| 9307 | { I64_MUL_WIDE_S_S, I64_MUL_WIDE_S }, |
| 9308 | { I64_MUL_WIDE_U_S, I64_MUL_WIDE_U }, |
| 9309 | { I64_REINTERPRET_F64_S, I64_REINTERPRET_F64 }, |
| 9310 | { I64_SUB128_S, I64_SUB128 }, |
| 9311 | { I64_TRUNC_S_F32_S, I64_TRUNC_S_F32 }, |
| 9312 | { I64_TRUNC_S_F64_S, I64_TRUNC_S_F64 }, |
| 9313 | { I64_TRUNC_S_SAT_F32_S, I64_TRUNC_S_SAT_F32 }, |
| 9314 | { I64_TRUNC_S_SAT_F64_S, I64_TRUNC_S_SAT_F64 }, |
| 9315 | { I64_TRUNC_U_F32_S, I64_TRUNC_U_F32 }, |
| 9316 | { I64_TRUNC_U_F64_S, I64_TRUNC_U_F64 }, |
| 9317 | { I64_TRUNC_U_SAT_F32_S, I64_TRUNC_U_SAT_F32 }, |
| 9318 | { I64_TRUNC_U_SAT_F64_S, I64_TRUNC_U_SAT_F64 }, |
| 9319 | { IF_S, IF }, |
| 9320 | { LANESELECT_I16x8_S, LANESELECT_I16x8 }, |
| 9321 | { LANESELECT_I32x4_S, LANESELECT_I32x4 }, |
| 9322 | { LANESELECT_I64x2_S, LANESELECT_I64x2 }, |
| 9323 | { LANESELECT_I8x16_S, LANESELECT_I8x16 }, |
| 9324 | { LE_F16x8_S, LE_F16x8 }, |
| 9325 | { LE_F32_S, LE_F32 }, |
| 9326 | { LE_F32x4_S, LE_F32x4 }, |
| 9327 | { LE_F64_S, LE_F64 }, |
| 9328 | { LE_F64x2_S, LE_F64x2 }, |
| 9329 | { LE_S_I16x8_S, LE_S_I16x8 }, |
| 9330 | { LE_S_I32_S, LE_S_I32 }, |
| 9331 | { LE_S_I32x4_S, LE_S_I32x4 }, |
| 9332 | { LE_S_I64_S, LE_S_I64 }, |
| 9333 | { LE_S_I64x2_S, LE_S_I64x2 }, |
| 9334 | { LE_S_I8x16_S, LE_S_I8x16 }, |
| 9335 | { LE_U_I16x8_S, LE_U_I16x8 }, |
| 9336 | { LE_U_I32_S, LE_U_I32 }, |
| 9337 | { LE_U_I32x4_S, LE_U_I32x4 }, |
| 9338 | { LE_U_I64_S, LE_U_I64 }, |
| 9339 | { LE_U_I8x16_S, LE_U_I8x16 }, |
| 9340 | { LOAD16_SPLAT_A32_S, LOAD16_SPLAT_A32 }, |
| 9341 | { LOAD16_SPLAT_A64_S, LOAD16_SPLAT_A64 }, |
| 9342 | { LOAD16_S_I32_A32_S, LOAD16_S_I32_A32 }, |
| 9343 | { LOAD16_S_I32_A64_S, LOAD16_S_I32_A64 }, |
| 9344 | { LOAD16_S_I64_A32_S, LOAD16_S_I64_A32 }, |
| 9345 | { LOAD16_S_I64_A64_S, LOAD16_S_I64_A64 }, |
| 9346 | { LOAD16_U_I32_A32_S, LOAD16_U_I32_A32 }, |
| 9347 | { LOAD16_U_I32_A64_S, LOAD16_U_I32_A64 }, |
| 9348 | { LOAD16_U_I64_A32_S, LOAD16_U_I64_A32 }, |
| 9349 | { LOAD16_U_I64_A64_S, LOAD16_U_I64_A64 }, |
| 9350 | { LOAD32_SPLAT_A32_S, LOAD32_SPLAT_A32 }, |
| 9351 | { LOAD32_SPLAT_A64_S, LOAD32_SPLAT_A64 }, |
| 9352 | { LOAD32_S_I64_A32_S, LOAD32_S_I64_A32 }, |
| 9353 | { LOAD32_S_I64_A64_S, LOAD32_S_I64_A64 }, |
| 9354 | { LOAD32_U_I64_A32_S, LOAD32_U_I64_A32 }, |
| 9355 | { LOAD32_U_I64_A64_S, LOAD32_U_I64_A64 }, |
| 9356 | { LOAD64_SPLAT_A32_S, LOAD64_SPLAT_A32 }, |
| 9357 | { LOAD64_SPLAT_A64_S, LOAD64_SPLAT_A64 }, |
| 9358 | { LOAD8_SPLAT_A32_S, LOAD8_SPLAT_A32 }, |
| 9359 | { LOAD8_SPLAT_A64_S, LOAD8_SPLAT_A64 }, |
| 9360 | { LOAD8_S_I32_A32_S, LOAD8_S_I32_A32 }, |
| 9361 | { LOAD8_S_I32_A64_S, LOAD8_S_I32_A64 }, |
| 9362 | { LOAD8_S_I64_A32_S, LOAD8_S_I64_A32 }, |
| 9363 | { LOAD8_S_I64_A64_S, LOAD8_S_I64_A64 }, |
| 9364 | { LOAD8_U_I32_A32_S, LOAD8_U_I32_A32 }, |
| 9365 | { LOAD8_U_I32_A64_S, LOAD8_U_I32_A64 }, |
| 9366 | { LOAD8_U_I64_A32_S, LOAD8_U_I64_A32 }, |
| 9367 | { LOAD8_U_I64_A64_S, LOAD8_U_I64_A64 }, |
| 9368 | { LOAD_EXTEND_S_I16x8_A32_S, LOAD_EXTEND_S_I16x8_A32 }, |
| 9369 | { LOAD_EXTEND_S_I16x8_A64_S, LOAD_EXTEND_S_I16x8_A64 }, |
| 9370 | { LOAD_EXTEND_S_I32x4_A32_S, LOAD_EXTEND_S_I32x4_A32 }, |
| 9371 | { LOAD_EXTEND_S_I32x4_A64_S, LOAD_EXTEND_S_I32x4_A64 }, |
| 9372 | { LOAD_EXTEND_S_I64x2_A32_S, LOAD_EXTEND_S_I64x2_A32 }, |
| 9373 | { LOAD_EXTEND_S_I64x2_A64_S, LOAD_EXTEND_S_I64x2_A64 }, |
| 9374 | { LOAD_EXTEND_U_I16x8_A32_S, LOAD_EXTEND_U_I16x8_A32 }, |
| 9375 | { LOAD_EXTEND_U_I16x8_A64_S, LOAD_EXTEND_U_I16x8_A64 }, |
| 9376 | { LOAD_EXTEND_U_I32x4_A32_S, LOAD_EXTEND_U_I32x4_A32 }, |
| 9377 | { LOAD_EXTEND_U_I32x4_A64_S, LOAD_EXTEND_U_I32x4_A64 }, |
| 9378 | { LOAD_EXTEND_U_I64x2_A32_S, LOAD_EXTEND_U_I64x2_A32 }, |
| 9379 | { LOAD_EXTEND_U_I64x2_A64_S, LOAD_EXTEND_U_I64x2_A64 }, |
| 9380 | { LOAD_F16_F32_A32_S, LOAD_F16_F32_A32 }, |
| 9381 | { LOAD_F16_F32_A64_S, LOAD_F16_F32_A64 }, |
| 9382 | { LOAD_F32_A32_S, LOAD_F32_A32 }, |
| 9383 | { LOAD_F32_A64_S, LOAD_F32_A64 }, |
| 9384 | { LOAD_F64_A32_S, LOAD_F64_A32 }, |
| 9385 | { LOAD_F64_A64_S, LOAD_F64_A64 }, |
| 9386 | { LOAD_I32_A32_S, LOAD_I32_A32 }, |
| 9387 | { LOAD_I32_A64_S, LOAD_I32_A64 }, |
| 9388 | { LOAD_I64_A32_S, LOAD_I64_A32 }, |
| 9389 | { LOAD_I64_A64_S, LOAD_I64_A64 }, |
| 9390 | { LOAD_LANE_16_A32_S, LOAD_LANE_16_A32 }, |
| 9391 | { LOAD_LANE_16_A64_S, LOAD_LANE_16_A64 }, |
| 9392 | { LOAD_LANE_32_A32_S, LOAD_LANE_32_A32 }, |
| 9393 | { LOAD_LANE_32_A64_S, LOAD_LANE_32_A64 }, |
| 9394 | { LOAD_LANE_64_A32_S, LOAD_LANE_64_A32 }, |
| 9395 | { LOAD_LANE_64_A64_S, LOAD_LANE_64_A64 }, |
| 9396 | { LOAD_LANE_8_A32_S, LOAD_LANE_8_A32 }, |
| 9397 | { LOAD_LANE_8_A64_S, LOAD_LANE_8_A64 }, |
| 9398 | { LOAD_V128_A32_S, LOAD_V128_A32 }, |
| 9399 | { LOAD_V128_A64_S, LOAD_V128_A64 }, |
| 9400 | { LOAD_ZERO_32_A32_S, LOAD_ZERO_32_A32 }, |
| 9401 | { LOAD_ZERO_32_A64_S, LOAD_ZERO_32_A64 }, |
| 9402 | { LOAD_ZERO_64_A32_S, LOAD_ZERO_64_A32 }, |
| 9403 | { LOAD_ZERO_64_A64_S, LOAD_ZERO_64_A64 }, |
| 9404 | { LOCAL_GET_EXNREF_S, LOCAL_GET_EXNREF }, |
| 9405 | { LOCAL_GET_EXTERNREF_S, LOCAL_GET_EXTERNREF }, |
| 9406 | { LOCAL_GET_F32_S, LOCAL_GET_F32 }, |
| 9407 | { LOCAL_GET_F64_S, LOCAL_GET_F64 }, |
| 9408 | { LOCAL_GET_FUNCREF_S, LOCAL_GET_FUNCREF }, |
| 9409 | { LOCAL_GET_I32_S, LOCAL_GET_I32 }, |
| 9410 | { LOCAL_GET_I64_S, LOCAL_GET_I64 }, |
| 9411 | { LOCAL_GET_V128_S, LOCAL_GET_V128 }, |
| 9412 | { LOCAL_SET_EXNREF_S, LOCAL_SET_EXNREF }, |
| 9413 | { LOCAL_SET_EXTERNREF_S, LOCAL_SET_EXTERNREF }, |
| 9414 | { LOCAL_SET_F32_S, LOCAL_SET_F32 }, |
| 9415 | { LOCAL_SET_F64_S, LOCAL_SET_F64 }, |
| 9416 | { LOCAL_SET_FUNCREF_S, LOCAL_SET_FUNCREF }, |
| 9417 | { LOCAL_SET_I32_S, LOCAL_SET_I32 }, |
| 9418 | { LOCAL_SET_I64_S, LOCAL_SET_I64 }, |
| 9419 | { LOCAL_SET_V128_S, LOCAL_SET_V128 }, |
| 9420 | { LOCAL_TEE_EXNREF_S, LOCAL_TEE_EXNREF }, |
| 9421 | { LOCAL_TEE_EXTERNREF_S, LOCAL_TEE_EXTERNREF }, |
| 9422 | { LOCAL_TEE_F32_S, LOCAL_TEE_F32 }, |
| 9423 | { LOCAL_TEE_F64_S, LOCAL_TEE_F64 }, |
| 9424 | { LOCAL_TEE_FUNCREF_S, LOCAL_TEE_FUNCREF }, |
| 9425 | { LOCAL_TEE_I32_S, LOCAL_TEE_I32 }, |
| 9426 | { LOCAL_TEE_I64_S, LOCAL_TEE_I64 }, |
| 9427 | { LOCAL_TEE_V128_S, LOCAL_TEE_V128 }, |
| 9428 | { LOOP_S, LOOP }, |
| 9429 | { LT_F16x8_S, LT_F16x8 }, |
| 9430 | { LT_F32_S, LT_F32 }, |
| 9431 | { LT_F32x4_S, LT_F32x4 }, |
| 9432 | { LT_F64_S, LT_F64 }, |
| 9433 | { LT_F64x2_S, LT_F64x2 }, |
| 9434 | { LT_S_I16x8_S, LT_S_I16x8 }, |
| 9435 | { LT_S_I32_S, LT_S_I32 }, |
| 9436 | { LT_S_I32x4_S, LT_S_I32x4 }, |
| 9437 | { LT_S_I64_S, LT_S_I64 }, |
| 9438 | { LT_S_I64x2_S, LT_S_I64x2 }, |
| 9439 | { LT_S_I8x16_S, LT_S_I8x16 }, |
| 9440 | { LT_U_I16x8_S, LT_U_I16x8 }, |
| 9441 | { LT_U_I32_S, LT_U_I32 }, |
| 9442 | { LT_U_I32x4_S, LT_U_I32x4 }, |
| 9443 | { LT_U_I64_S, LT_U_I64 }, |
| 9444 | { LT_U_I8x16_S, LT_U_I8x16 }, |
| 9445 | { MADD_F16x8_S, MADD_F16x8 }, |
| 9446 | { MADD_F32x4_S, MADD_F32x4 }, |
| 9447 | { MADD_F64x2_S, MADD_F64x2 }, |
| 9448 | { MAX_F16x8_S, MAX_F16x8 }, |
| 9449 | { MAX_F32_S, MAX_F32 }, |
| 9450 | { MAX_F32x4_S, MAX_F32x4 }, |
| 9451 | { MAX_F64_S, MAX_F64 }, |
| 9452 | { MAX_F64x2_S, MAX_F64x2 }, |
| 9453 | { MAX_S_I16x8_S, MAX_S_I16x8 }, |
| 9454 | { MAX_S_I32x4_S, MAX_S_I32x4 }, |
| 9455 | { MAX_S_I8x16_S, MAX_S_I8x16 }, |
| 9456 | { MAX_U_I16x8_S, MAX_U_I16x8 }, |
| 9457 | { MAX_U_I32x4_S, MAX_U_I32x4 }, |
| 9458 | { MAX_U_I8x16_S, MAX_U_I8x16 }, |
| 9459 | { MEMCPY_A32_S, MEMCPY_A32 }, |
| 9460 | { MEMCPY_A64_S, MEMCPY_A64 }, |
| 9461 | { MEMORY_ATOMIC_NOTIFY_A32_S, MEMORY_ATOMIC_NOTIFY_A32 }, |
| 9462 | { MEMORY_ATOMIC_NOTIFY_A64_S, MEMORY_ATOMIC_NOTIFY_A64 }, |
| 9463 | { MEMORY_ATOMIC_WAIT32_A32_S, MEMORY_ATOMIC_WAIT32_A32 }, |
| 9464 | { MEMORY_ATOMIC_WAIT32_A64_S, MEMORY_ATOMIC_WAIT32_A64 }, |
| 9465 | { MEMORY_ATOMIC_WAIT64_A32_S, MEMORY_ATOMIC_WAIT64_A32 }, |
| 9466 | { MEMORY_ATOMIC_WAIT64_A64_S, MEMORY_ATOMIC_WAIT64_A64 }, |
| 9467 | { MEMORY_COPY_A32_S, MEMORY_COPY_A32 }, |
| 9468 | { MEMORY_COPY_A64_S, MEMORY_COPY_A64 }, |
| 9469 | { MEMORY_FILL_A32_S, MEMORY_FILL_A32 }, |
| 9470 | { MEMORY_FILL_A64_S, MEMORY_FILL_A64 }, |
| 9471 | { MEMORY_INIT_A32_S, MEMORY_INIT_A32 }, |
| 9472 | { MEMORY_INIT_A64_S, MEMORY_INIT_A64 }, |
| 9473 | { MEMSET_A32_S, MEMSET_A32 }, |
| 9474 | { MEMSET_A64_S, MEMSET_A64 }, |
| 9475 | { MIN_F16x8_S, MIN_F16x8 }, |
| 9476 | { MIN_F32_S, MIN_F32 }, |
| 9477 | { MIN_F32x4_S, MIN_F32x4 }, |
| 9478 | { MIN_F64_S, MIN_F64 }, |
| 9479 | { MIN_F64x2_S, MIN_F64x2 }, |
| 9480 | { MIN_S_I16x8_S, MIN_S_I16x8 }, |
| 9481 | { MIN_S_I32x4_S, MIN_S_I32x4 }, |
| 9482 | { MIN_S_I8x16_S, MIN_S_I8x16 }, |
| 9483 | { MIN_U_I16x8_S, MIN_U_I16x8 }, |
| 9484 | { MIN_U_I32x4_S, MIN_U_I32x4 }, |
| 9485 | { MIN_U_I8x16_S, MIN_U_I8x16 }, |
| 9486 | { MUL_F16x8_S, MUL_F16x8 }, |
| 9487 | { MUL_F32_S, MUL_F32 }, |
| 9488 | { MUL_F32x4_S, MUL_F32x4 }, |
| 9489 | { MUL_F64_S, MUL_F64 }, |
| 9490 | { MUL_F64x2_S, MUL_F64x2 }, |
| 9491 | { MUL_I16x8_S, MUL_I16x8 }, |
| 9492 | { MUL_I32_S, MUL_I32 }, |
| 9493 | { MUL_I32x4_S, MUL_I32x4 }, |
| 9494 | { MUL_I64_S, MUL_I64 }, |
| 9495 | { MUL_I64x2_S, MUL_I64x2 }, |
| 9496 | { NARROW_S_I16x8_S, NARROW_S_I16x8 }, |
| 9497 | { NARROW_S_I8x16_S, NARROW_S_I8x16 }, |
| 9498 | { NARROW_U_I16x8_S, NARROW_U_I16x8 }, |
| 9499 | { NARROW_U_I8x16_S, NARROW_U_I8x16 }, |
| 9500 | { NEAREST_F16x8_S, NEAREST_F16x8 }, |
| 9501 | { NEAREST_F32_S, NEAREST_F32 }, |
| 9502 | { NEAREST_F32x4_S, NEAREST_F32x4 }, |
| 9503 | { NEAREST_F64_S, NEAREST_F64 }, |
| 9504 | { NEAREST_F64x2_S, NEAREST_F64x2 }, |
| 9505 | { NEG_F16x8_S, NEG_F16x8 }, |
| 9506 | { NEG_F32_S, NEG_F32 }, |
| 9507 | { NEG_F32x4_S, NEG_F32x4 }, |
| 9508 | { NEG_F64_S, NEG_F64 }, |
| 9509 | { NEG_F64x2_S, NEG_F64x2 }, |
| 9510 | { NEG_I16x8_S, NEG_I16x8 }, |
| 9511 | { NEG_I32x4_S, NEG_I32x4 }, |
| 9512 | { NEG_I64x2_S, NEG_I64x2 }, |
| 9513 | { NEG_I8x16_S, NEG_I8x16 }, |
| 9514 | { NE_F16x8_S, NE_F16x8 }, |
| 9515 | { NE_F32_S, NE_F32 }, |
| 9516 | { NE_F32x4_S, NE_F32x4 }, |
| 9517 | { NE_F64_S, NE_F64 }, |
| 9518 | { NE_F64x2_S, NE_F64x2 }, |
| 9519 | { NE_I16x8_S, NE_I16x8 }, |
| 9520 | { NE_I32_S, NE_I32 }, |
| 9521 | { NE_I32x4_S, NE_I32x4 }, |
| 9522 | { NE_I64_S, NE_I64 }, |
| 9523 | { NE_I64x2_S, NE_I64x2 }, |
| 9524 | { NE_I8x16_S, NE_I8x16 }, |
| 9525 | { NMADD_F16x8_S, NMADD_F16x8 }, |
| 9526 | { NMADD_F32x4_S, NMADD_F32x4 }, |
| 9527 | { NMADD_F64x2_S, NMADD_F64x2 }, |
| 9528 | { NOP_S, NOP }, |
| 9529 | { NOT_S, NOT }, |
| 9530 | { OR_I32_S, OR_I32 }, |
| 9531 | { OR_I64_S, OR_I64 }, |
| 9532 | { OR_S, OR }, |
| 9533 | { PMAX_F16x8_S, PMAX_F16x8 }, |
| 9534 | { PMAX_F32x4_S, PMAX_F32x4 }, |
| 9535 | { PMAX_F64x2_S, PMAX_F64x2 }, |
| 9536 | { PMIN_F16x8_S, PMIN_F16x8 }, |
| 9537 | { PMIN_F32x4_S, PMIN_F32x4 }, |
| 9538 | { PMIN_F64x2_S, PMIN_F64x2 }, |
| 9539 | { POPCNT_I32_S, POPCNT_I32 }, |
| 9540 | { POPCNT_I64_S, POPCNT_I64 }, |
| 9541 | { POPCNT_I8x16_S, POPCNT_I8x16 }, |
| 9542 | { Q15MULR_SAT_S_I16x8_S, Q15MULR_SAT_S_I16x8 }, |
| 9543 | { REF_CAST_FUNCREF_S, REF_CAST_FUNCREF }, |
| 9544 | { REF_FUNC_S, REF_FUNC }, |
| 9545 | { REF_IS_NULL_EXNREF_S, REF_IS_NULL_EXNREF }, |
| 9546 | { REF_IS_NULL_EXTERNREF_S, REF_IS_NULL_EXTERNREF }, |
| 9547 | { REF_IS_NULL_FUNCREF_S, REF_IS_NULL_FUNCREF }, |
| 9548 | { REF_NULL_EXNREF_S, REF_NULL_EXNREF }, |
| 9549 | { REF_NULL_EXTERNREF_S, REF_NULL_EXTERNREF }, |
| 9550 | { REF_NULL_FUNCREF_S, REF_NULL_FUNCREF }, |
| 9551 | { REF_TEST_FUNCREF_S, REF_TEST_FUNCREF }, |
| 9552 | { RELAXED_DOT_ADD_S, RELAXED_DOT_ADD }, |
| 9553 | { RELAXED_DOT_BFLOAT_S, RELAXED_DOT_BFLOAT }, |
| 9554 | { RELAXED_DOT_S, RELAXED_DOT }, |
| 9555 | { RELAXED_Q15MULR_S_I16x8_S, RELAXED_Q15MULR_S_I16x8 }, |
| 9556 | { RELAXED_SWIZZLE_S, RELAXED_SWIZZLE }, |
| 9557 | { REM_S_I32_S, REM_S_I32 }, |
| 9558 | { REM_S_I64_S, REM_S_I64 }, |
| 9559 | { REM_U_I32_S, REM_U_I32 }, |
| 9560 | { REM_U_I64_S, REM_U_I64 }, |
| 9561 | { REPLACE_LANE_F16x8_S, REPLACE_LANE_F16x8 }, |
| 9562 | { REPLACE_LANE_F32x4_S, REPLACE_LANE_F32x4 }, |
| 9563 | { REPLACE_LANE_F64x2_S, REPLACE_LANE_F64x2 }, |
| 9564 | { REPLACE_LANE_I16x8_S, REPLACE_LANE_I16x8 }, |
| 9565 | { REPLACE_LANE_I32x4_S, REPLACE_LANE_I32x4 }, |
| 9566 | { REPLACE_LANE_I64x2_S, REPLACE_LANE_I64x2 }, |
| 9567 | { REPLACE_LANE_I8x16_S, REPLACE_LANE_I8x16 }, |
| 9568 | { RETHROW_S, RETHROW }, |
| 9569 | { RETURN_S, RETURN }, |
| 9570 | { RET_CALL_INDIRECT_S, RET_CALL_INDIRECT }, |
| 9571 | { RET_CALL_REF_S, RET_CALL_REF }, |
| 9572 | { RET_CALL_S, RET_CALL }, |
| 9573 | { ROTL_I32_S, ROTL_I32 }, |
| 9574 | { ROTL_I64_S, ROTL_I64 }, |
| 9575 | { ROTR_I32_S, ROTR_I32 }, |
| 9576 | { ROTR_I64_S, ROTR_I64 }, |
| 9577 | { SELECT_EXNREF_S, SELECT_EXNREF }, |
| 9578 | { SELECT_EXTERNREF_S, SELECT_EXTERNREF }, |
| 9579 | { SELECT_F32_S, SELECT_F32 }, |
| 9580 | { SELECT_F64_S, SELECT_F64 }, |
| 9581 | { SELECT_FUNCREF_S, SELECT_FUNCREF }, |
| 9582 | { SELECT_I32_S, SELECT_I32 }, |
| 9583 | { SELECT_I64_S, SELECT_I64 }, |
| 9584 | { SELECT_T_S, SELECT_T }, |
| 9585 | { SELECT_V128_S, SELECT_V128 }, |
| 9586 | { SHL_I16x8_S, SHL_I16x8 }, |
| 9587 | { SHL_I32_S, SHL_I32 }, |
| 9588 | { SHL_I32x4_S, SHL_I32x4 }, |
| 9589 | { SHL_I64_S, SHL_I64 }, |
| 9590 | { SHL_I64x2_S, SHL_I64x2 }, |
| 9591 | { SHL_I8x16_S, SHL_I8x16 }, |
| 9592 | { SHR_S_I16x8_S, SHR_S_I16x8 }, |
| 9593 | { SHR_S_I32_S, SHR_S_I32 }, |
| 9594 | { SHR_S_I32x4_S, SHR_S_I32x4 }, |
| 9595 | { SHR_S_I64_S, SHR_S_I64 }, |
| 9596 | { SHR_S_I64x2_S, SHR_S_I64x2 }, |
| 9597 | { SHR_S_I8x16_S, SHR_S_I8x16 }, |
| 9598 | { SHR_U_I16x8_S, SHR_U_I16x8 }, |
| 9599 | { SHR_U_I32_S, SHR_U_I32 }, |
| 9600 | { SHR_U_I32x4_S, SHR_U_I32x4 }, |
| 9601 | { SHR_U_I64_S, SHR_U_I64 }, |
| 9602 | { SHR_U_I64x2_S, SHR_U_I64x2 }, |
| 9603 | { SHR_U_I8x16_S, SHR_U_I8x16 }, |
| 9604 | { SHUFFLE_S, SHUFFLE }, |
| 9605 | { SIMD_RELAXED_FMAX_F32x4_S, SIMD_RELAXED_FMAX_F32x4 }, |
| 9606 | { SIMD_RELAXED_FMAX_F64x2_S, SIMD_RELAXED_FMAX_F64x2 }, |
| 9607 | { SIMD_RELAXED_FMIN_F32x4_S, SIMD_RELAXED_FMIN_F32x4 }, |
| 9608 | { SIMD_RELAXED_FMIN_F64x2_S, SIMD_RELAXED_FMIN_F64x2 }, |
| 9609 | { SPLAT_F16x8_S, SPLAT_F16x8 }, |
| 9610 | { SPLAT_F32x4_S, SPLAT_F32x4 }, |
| 9611 | { SPLAT_F64x2_S, SPLAT_F64x2 }, |
| 9612 | { SPLAT_I16x8_S, SPLAT_I16x8 }, |
| 9613 | { SPLAT_I32x4_S, SPLAT_I32x4 }, |
| 9614 | { SPLAT_I64x2_S, SPLAT_I64x2 }, |
| 9615 | { SPLAT_I8x16_S, SPLAT_I8x16 }, |
| 9616 | { SQRT_F16x8_S, SQRT_F16x8 }, |
| 9617 | { SQRT_F32_S, SQRT_F32 }, |
| 9618 | { SQRT_F32x4_S, SQRT_F32x4 }, |
| 9619 | { SQRT_F64_S, SQRT_F64 }, |
| 9620 | { SQRT_F64x2_S, SQRT_F64x2 }, |
| 9621 | { STORE16_I32_A32_S, STORE16_I32_A32 }, |
| 9622 | { STORE16_I32_A64_S, STORE16_I32_A64 }, |
| 9623 | { STORE16_I64_A32_S, STORE16_I64_A32 }, |
| 9624 | { STORE16_I64_A64_S, STORE16_I64_A64 }, |
| 9625 | { STORE32_I64_A32_S, STORE32_I64_A32 }, |
| 9626 | { STORE32_I64_A64_S, STORE32_I64_A64 }, |
| 9627 | { STORE8_I32_A32_S, STORE8_I32_A32 }, |
| 9628 | { STORE8_I32_A64_S, STORE8_I32_A64 }, |
| 9629 | { STORE8_I64_A32_S, STORE8_I64_A32 }, |
| 9630 | { STORE8_I64_A64_S, STORE8_I64_A64 }, |
| 9631 | { STORE_F16_F32_A32_S, STORE_F16_F32_A32 }, |
| 9632 | { STORE_F16_F32_A64_S, STORE_F16_F32_A64 }, |
| 9633 | { STORE_F32_A32_S, STORE_F32_A32 }, |
| 9634 | { STORE_F32_A64_S, STORE_F32_A64 }, |
| 9635 | { STORE_F64_A32_S, STORE_F64_A32 }, |
| 9636 | { STORE_F64_A64_S, STORE_F64_A64 }, |
| 9637 | { STORE_I32_A32_S, STORE_I32_A32 }, |
| 9638 | { STORE_I32_A64_S, STORE_I32_A64 }, |
| 9639 | { STORE_I64_A32_S, STORE_I64_A32 }, |
| 9640 | { STORE_I64_A64_S, STORE_I64_A64 }, |
| 9641 | { STORE_LANE_I16x8_A32_S, STORE_LANE_I16x8_A32 }, |
| 9642 | { STORE_LANE_I16x8_A64_S, STORE_LANE_I16x8_A64 }, |
| 9643 | { STORE_LANE_I32x4_A32_S, STORE_LANE_I32x4_A32 }, |
| 9644 | { STORE_LANE_I32x4_A64_S, STORE_LANE_I32x4_A64 }, |
| 9645 | { STORE_LANE_I64x2_A32_S, STORE_LANE_I64x2_A32 }, |
| 9646 | { STORE_LANE_I64x2_A64_S, STORE_LANE_I64x2_A64 }, |
| 9647 | { STORE_LANE_I8x16_A32_S, STORE_LANE_I8x16_A32 }, |
| 9648 | { STORE_LANE_I8x16_A64_S, STORE_LANE_I8x16_A64 }, |
| 9649 | { STORE_V128_A32_S, STORE_V128_A32 }, |
| 9650 | { STORE_V128_A64_S, STORE_V128_A64 }, |
| 9651 | { SUB_F16x8_S, SUB_F16x8 }, |
| 9652 | { SUB_F32_S, SUB_F32 }, |
| 9653 | { SUB_F32x4_S, SUB_F32x4 }, |
| 9654 | { SUB_F64_S, SUB_F64 }, |
| 9655 | { SUB_F64x2_S, SUB_F64x2 }, |
| 9656 | { SUB_I16x8_S, SUB_I16x8 }, |
| 9657 | { SUB_I32_S, SUB_I32 }, |
| 9658 | { SUB_I32x4_S, SUB_I32x4 }, |
| 9659 | { SUB_I64_S, SUB_I64 }, |
| 9660 | { SUB_I64x2_S, SUB_I64x2 }, |
| 9661 | { SUB_I8x16_S, SUB_I8x16 }, |
| 9662 | { SUB_SAT_S_I16x8_S, SUB_SAT_S_I16x8 }, |
| 9663 | { SUB_SAT_S_I8x16_S, SUB_SAT_S_I8x16 }, |
| 9664 | { SUB_SAT_U_I16x8_S, SUB_SAT_U_I16x8 }, |
| 9665 | { SUB_SAT_U_I8x16_S, SUB_SAT_U_I8x16 }, |
| 9666 | { SWIZZLE_S, SWIZZLE }, |
| 9667 | { TABLE_COPY_S, TABLE_COPY }, |
| 9668 | { TABLE_FILL_EXNREF_S, TABLE_FILL_EXNREF }, |
| 9669 | { TABLE_FILL_EXTERNREF_S, TABLE_FILL_EXTERNREF }, |
| 9670 | { TABLE_FILL_FUNCREF_S, TABLE_FILL_FUNCREF }, |
| 9671 | { TABLE_GET_EXNREF_S, TABLE_GET_EXNREF }, |
| 9672 | { TABLE_GET_EXTERNREF_S, TABLE_GET_EXTERNREF }, |
| 9673 | { TABLE_GET_FUNCREF_S, TABLE_GET_FUNCREF }, |
| 9674 | { TABLE_GROW_EXNREF_S, TABLE_GROW_EXNREF }, |
| 9675 | { TABLE_GROW_EXTERNREF_S, TABLE_GROW_EXTERNREF }, |
| 9676 | { TABLE_GROW_FUNCREF_S, TABLE_GROW_FUNCREF }, |
| 9677 | { TABLE_SET_EXNREF_S, TABLE_SET_EXNREF }, |
| 9678 | { TABLE_SET_EXTERNREF_S, TABLE_SET_EXTERNREF }, |
| 9679 | { TABLE_SET_FUNCREF_S, TABLE_SET_FUNCREF }, |
| 9680 | { TABLE_SIZE_S, TABLE_SIZE }, |
| 9681 | { TEE_EXNREF_S, TEE_EXNREF }, |
| 9682 | { TEE_EXTERNREF_S, TEE_EXTERNREF }, |
| 9683 | { TEE_F32_S, TEE_F32 }, |
| 9684 | { TEE_F64_S, TEE_F64 }, |
| 9685 | { TEE_FUNCREF_S, TEE_FUNCREF }, |
| 9686 | { TEE_I32_S, TEE_I32 }, |
| 9687 | { TEE_I64_S, TEE_I64 }, |
| 9688 | { TEE_V128_S, TEE_V128 }, |
| 9689 | { THROW_REF_S, THROW_REF }, |
| 9690 | { THROW_S, THROW }, |
| 9691 | { TRUNC_F16x8_S, TRUNC_F16x8 }, |
| 9692 | { TRUNC_F32_S, TRUNC_F32 }, |
| 9693 | { TRUNC_F32x4_S, TRUNC_F32x4 }, |
| 9694 | { TRUNC_F64_S, TRUNC_F64 }, |
| 9695 | { TRUNC_F64x2_S, TRUNC_F64x2 }, |
| 9696 | { TRY_S, TRY }, |
| 9697 | { TRY_TABLE_S, TRY_TABLE }, |
| 9698 | { UNREACHABLE_S, UNREACHABLE }, |
| 9699 | { XOR_I32_S, XOR_I32 }, |
| 9700 | { XOR_I64_S, XOR_I64 }, |
| 9701 | { XOR_S, XOR }, |
| 9702 | { anonymous_14793MEMORY_GROW_A32_S, anonymous_14793MEMORY_GROW_A32 }, |
| 9703 | { anonymous_14793MEMORY_SIZE_A32_S, anonymous_14793MEMORY_SIZE_A32 }, |
| 9704 | { anonymous_14794MEMORY_GROW_A64_S, anonymous_14794MEMORY_GROW_A64 }, |
| 9705 | { anonymous_14794MEMORY_SIZE_A64_S, anonymous_14794MEMORY_SIZE_A64 }, |
| 9706 | { convert_low_s_F64x2_S, convert_low_s_F64x2 }, |
| 9707 | { convert_low_u_F64x2_S, convert_low_u_F64x2 }, |
| 9708 | { demote_zero_F16x8_S, demote_zero_F16x8 }, |
| 9709 | { demote_zero_F32x4_S, demote_zero_F32x4 }, |
| 9710 | { extadd_pairwise_s_I16x8_S, extadd_pairwise_s_I16x8 }, |
| 9711 | { extadd_pairwise_s_I32x4_S, extadd_pairwise_s_I32x4 }, |
| 9712 | { extadd_pairwise_u_I16x8_S, extadd_pairwise_u_I16x8 }, |
| 9713 | { extadd_pairwise_u_I32x4_S, extadd_pairwise_u_I32x4 }, |
| 9714 | { extend_high_s_I16x8_S, extend_high_s_I16x8 }, |
| 9715 | { extend_high_s_I32x4_S, extend_high_s_I32x4 }, |
| 9716 | { extend_high_s_I64x2_S, extend_high_s_I64x2 }, |
| 9717 | { extend_high_u_I16x8_S, extend_high_u_I16x8 }, |
| 9718 | { extend_high_u_I32x4_S, extend_high_u_I32x4 }, |
| 9719 | { extend_high_u_I64x2_S, extend_high_u_I64x2 }, |
| 9720 | { extend_low_s_I16x8_S, extend_low_s_I16x8 }, |
| 9721 | { extend_low_s_I32x4_S, extend_low_s_I32x4 }, |
| 9722 | { extend_low_s_I64x2_S, extend_low_s_I64x2 }, |
| 9723 | { extend_low_u_I16x8_S, extend_low_u_I16x8 }, |
| 9724 | { extend_low_u_I32x4_S, extend_low_u_I32x4 }, |
| 9725 | { extend_low_u_I64x2_S, extend_low_u_I64x2 }, |
| 9726 | { fp_to_sint_I16x8_S, fp_to_sint_I16x8 }, |
| 9727 | { fp_to_sint_I32x4_S, fp_to_sint_I32x4 }, |
| 9728 | { fp_to_uint_I16x8_S, fp_to_uint_I16x8 }, |
| 9729 | { fp_to_uint_I32x4_S, fp_to_uint_I32x4 }, |
| 9730 | { int_wasm_relaxed_trunc_signed_I32x4_S, int_wasm_relaxed_trunc_signed_I32x4 }, |
| 9731 | { int_wasm_relaxed_trunc_signed_zero_I32x4_S, int_wasm_relaxed_trunc_signed_zero_I32x4 }, |
| 9732 | { int_wasm_relaxed_trunc_unsigned_I32x4_S, int_wasm_relaxed_trunc_unsigned_I32x4 }, |
| 9733 | { int_wasm_relaxed_trunc_unsigned_zero_I32x4_S, int_wasm_relaxed_trunc_unsigned_zero_I32x4 }, |
| 9734 | { promote_low_F32x4_S, promote_low_F32x4 }, |
| 9735 | { promote_low_F64x2_S, promote_low_F64x2 }, |
| 9736 | { sint_to_fp_F16x8_S, sint_to_fp_F16x8 }, |
| 9737 | { sint_to_fp_F32x4_S, sint_to_fp_F32x4 }, |
| 9738 | { trunc_sat_zero_s_I32x4_S, trunc_sat_zero_s_I32x4 }, |
| 9739 | { trunc_sat_zero_u_I32x4_S, trunc_sat_zero_u_I32x4 }, |
| 9740 | { uint_to_fp_F16x8_S, uint_to_fp_F16x8 }, |
| 9741 | { uint_to_fp_F32x4_S, uint_to_fp_F32x4 }, |
| 9742 | }; // End of Table |
| 9743 | |
| 9744 | unsigned mid; |
| 9745 | unsigned start = 0; |
| 9746 | unsigned end = 823; |
| 9747 | while (start < end) { |
| 9748 | mid = start + (end - start) / 2; |
| 9749 | if (Opcode == Table[mid][0]) |
| 9750 | break; |
| 9751 | if (Opcode < Table[mid][0]) |
| 9752 | end = mid; |
| 9753 | else |
| 9754 | start = mid + 1; |
| 9755 | } |
| 9756 | if (start == end) |
| 9757 | return -1; // Instruction doesn't exist in this table. |
| 9758 | |
| 9759 | return Table[mid][1]; |
| 9760 | } |
| 9761 | |
| 9762 | // getStackOpcode |
| 9763 | LLVM_READONLY |
| 9764 | int32_t getStackOpcode(uint32_t Opcode) { |
| 9765 | using namespace WebAssembly; |
| 9766 | static constexpr uint32_t Table[][2] = { |
| 9767 | { CALL_PARAMS, CALL_PARAMS_S }, |
| 9768 | { CALL_RESULTS, CALL_RESULTS_S }, |
| 9769 | { CATCHRET, CATCHRET_S }, |
| 9770 | { CLEANUPRET, CLEANUPRET_S }, |
| 9771 | { COMPILER_FENCE, COMPILER_FENCE_S }, |
| 9772 | { RET_CALL_RESULTS, RET_CALL_RESULTS_S }, |
| 9773 | { ABS_F16x8, ABS_F16x8_S }, |
| 9774 | { ABS_F32, ABS_F32_S }, |
| 9775 | { ABS_F32x4, ABS_F32x4_S }, |
| 9776 | { ABS_F64, ABS_F64_S }, |
| 9777 | { ABS_F64x2, ABS_F64x2_S }, |
| 9778 | { ABS_I16x8, ABS_I16x8_S }, |
| 9779 | { ABS_I32x4, ABS_I32x4_S }, |
| 9780 | { ABS_I64x2, ABS_I64x2_S }, |
| 9781 | { ABS_I8x16, ABS_I8x16_S }, |
| 9782 | { ADD_F16x8, ADD_F16x8_S }, |
| 9783 | { ADD_F32, ADD_F32_S }, |
| 9784 | { ADD_F32x4, ADD_F32x4_S }, |
| 9785 | { ADD_F64, ADD_F64_S }, |
| 9786 | { ADD_F64x2, ADD_F64x2_S }, |
| 9787 | { ADD_I16x8, ADD_I16x8_S }, |
| 9788 | { ADD_I32, ADD_I32_S }, |
| 9789 | { ADD_I32x4, ADD_I32x4_S }, |
| 9790 | { ADD_I64, ADD_I64_S }, |
| 9791 | { ADD_I64x2, ADD_I64x2_S }, |
| 9792 | { ADD_I8x16, ADD_I8x16_S }, |
| 9793 | { ADD_SAT_S_I16x8, ADD_SAT_S_I16x8_S }, |
| 9794 | { ADD_SAT_S_I8x16, ADD_SAT_S_I8x16_S }, |
| 9795 | { ADD_SAT_U_I16x8, ADD_SAT_U_I16x8_S }, |
| 9796 | { ADD_SAT_U_I8x16, ADD_SAT_U_I8x16_S }, |
| 9797 | { ADJCALLSTACKDOWN, ADJCALLSTACKDOWN_S }, |
| 9798 | { ADJCALLSTACKUP, ADJCALLSTACKUP_S }, |
| 9799 | { ALLTRUE_I16x8, ALLTRUE_I16x8_S }, |
| 9800 | { ALLTRUE_I32x4, ALLTRUE_I32x4_S }, |
| 9801 | { ALLTRUE_I64x2, ALLTRUE_I64x2_S }, |
| 9802 | { ALLTRUE_I8x16, ALLTRUE_I8x16_S }, |
| 9803 | { AND, AND_S }, |
| 9804 | { ANDNOT, ANDNOT_S }, |
| 9805 | { AND_I32, AND_I32_S }, |
| 9806 | { AND_I64, AND_I64_S }, |
| 9807 | { ANYTRUE, ANYTRUE_S }, |
| 9808 | { ARGUMENT_exnref, ARGUMENT_exnref_S }, |
| 9809 | { ARGUMENT_externref, ARGUMENT_externref_S }, |
| 9810 | { ARGUMENT_f32, ARGUMENT_f32_S }, |
| 9811 | { ARGUMENT_f64, ARGUMENT_f64_S }, |
| 9812 | { ARGUMENT_funcref, ARGUMENT_funcref_S }, |
| 9813 | { ARGUMENT_i32, ARGUMENT_i32_S }, |
| 9814 | { ARGUMENT_i64, ARGUMENT_i64_S }, |
| 9815 | { ARGUMENT_v16i8, ARGUMENT_v16i8_S }, |
| 9816 | { ARGUMENT_v2f64, ARGUMENT_v2f64_S }, |
| 9817 | { ARGUMENT_v2i64, ARGUMENT_v2i64_S }, |
| 9818 | { ARGUMENT_v4f32, ARGUMENT_v4f32_S }, |
| 9819 | { ARGUMENT_v4i32, ARGUMENT_v4i32_S }, |
| 9820 | { ARGUMENT_v8f16, ARGUMENT_v8f16_S }, |
| 9821 | { ARGUMENT_v8i16, ARGUMENT_v8i16_S }, |
| 9822 | { ATOMIC_FENCE, ATOMIC_FENCE_S }, |
| 9823 | { ATOMIC_LOAD16_U_I32_A32, ATOMIC_LOAD16_U_I32_A32_S }, |
| 9824 | { ATOMIC_LOAD16_U_I32_A64, ATOMIC_LOAD16_U_I32_A64_S }, |
| 9825 | { ATOMIC_LOAD16_U_I64_A32, ATOMIC_LOAD16_U_I64_A32_S }, |
| 9826 | { ATOMIC_LOAD16_U_I64_A64, ATOMIC_LOAD16_U_I64_A64_S }, |
| 9827 | { ATOMIC_LOAD32_U_I64_A32, ATOMIC_LOAD32_U_I64_A32_S }, |
| 9828 | { ATOMIC_LOAD32_U_I64_A64, ATOMIC_LOAD32_U_I64_A64_S }, |
| 9829 | { ATOMIC_LOAD8_U_I32_A32, ATOMIC_LOAD8_U_I32_A32_S }, |
| 9830 | { ATOMIC_LOAD8_U_I32_A64, ATOMIC_LOAD8_U_I32_A64_S }, |
| 9831 | { ATOMIC_LOAD8_U_I64_A32, ATOMIC_LOAD8_U_I64_A32_S }, |
| 9832 | { ATOMIC_LOAD8_U_I64_A64, ATOMIC_LOAD8_U_I64_A64_S }, |
| 9833 | { ATOMIC_LOAD_I32_A32, ATOMIC_LOAD_I32_A32_S }, |
| 9834 | { ATOMIC_LOAD_I32_A64, ATOMIC_LOAD_I32_A64_S }, |
| 9835 | { ATOMIC_LOAD_I64_A32, ATOMIC_LOAD_I64_A32_S }, |
| 9836 | { ATOMIC_LOAD_I64_A64, ATOMIC_LOAD_I64_A64_S }, |
| 9837 | { ATOMIC_RMW16_U_ADD_I32_A32, ATOMIC_RMW16_U_ADD_I32_A32_S }, |
| 9838 | { ATOMIC_RMW16_U_ADD_I32_A64, ATOMIC_RMW16_U_ADD_I32_A64_S }, |
| 9839 | { ATOMIC_RMW16_U_ADD_I64_A32, ATOMIC_RMW16_U_ADD_I64_A32_S }, |
| 9840 | { ATOMIC_RMW16_U_ADD_I64_A64, ATOMIC_RMW16_U_ADD_I64_A64_S }, |
| 9841 | { ATOMIC_RMW16_U_AND_I32_A32, ATOMIC_RMW16_U_AND_I32_A32_S }, |
| 9842 | { ATOMIC_RMW16_U_AND_I32_A64, ATOMIC_RMW16_U_AND_I32_A64_S }, |
| 9843 | { ATOMIC_RMW16_U_AND_I64_A32, ATOMIC_RMW16_U_AND_I64_A32_S }, |
| 9844 | { ATOMIC_RMW16_U_AND_I64_A64, ATOMIC_RMW16_U_AND_I64_A64_S }, |
| 9845 | { ATOMIC_RMW16_U_CMPXCHG_I32_A32, ATOMIC_RMW16_U_CMPXCHG_I32_A32_S }, |
| 9846 | { ATOMIC_RMW16_U_CMPXCHG_I32_A64, ATOMIC_RMW16_U_CMPXCHG_I32_A64_S }, |
| 9847 | { ATOMIC_RMW16_U_CMPXCHG_I64_A32, ATOMIC_RMW16_U_CMPXCHG_I64_A32_S }, |
| 9848 | { ATOMIC_RMW16_U_CMPXCHG_I64_A64, ATOMIC_RMW16_U_CMPXCHG_I64_A64_S }, |
| 9849 | { ATOMIC_RMW16_U_OR_I32_A32, ATOMIC_RMW16_U_OR_I32_A32_S }, |
| 9850 | { ATOMIC_RMW16_U_OR_I32_A64, ATOMIC_RMW16_U_OR_I32_A64_S }, |
| 9851 | { ATOMIC_RMW16_U_OR_I64_A32, ATOMIC_RMW16_U_OR_I64_A32_S }, |
| 9852 | { ATOMIC_RMW16_U_OR_I64_A64, ATOMIC_RMW16_U_OR_I64_A64_S }, |
| 9853 | { ATOMIC_RMW16_U_SUB_I32_A32, ATOMIC_RMW16_U_SUB_I32_A32_S }, |
| 9854 | { ATOMIC_RMW16_U_SUB_I32_A64, ATOMIC_RMW16_U_SUB_I32_A64_S }, |
| 9855 | { ATOMIC_RMW16_U_SUB_I64_A32, ATOMIC_RMW16_U_SUB_I64_A32_S }, |
| 9856 | { ATOMIC_RMW16_U_SUB_I64_A64, ATOMIC_RMW16_U_SUB_I64_A64_S }, |
| 9857 | { ATOMIC_RMW16_U_XCHG_I32_A32, ATOMIC_RMW16_U_XCHG_I32_A32_S }, |
| 9858 | { ATOMIC_RMW16_U_XCHG_I32_A64, ATOMIC_RMW16_U_XCHG_I32_A64_S }, |
| 9859 | { ATOMIC_RMW16_U_XCHG_I64_A32, ATOMIC_RMW16_U_XCHG_I64_A32_S }, |
| 9860 | { ATOMIC_RMW16_U_XCHG_I64_A64, ATOMIC_RMW16_U_XCHG_I64_A64_S }, |
| 9861 | { ATOMIC_RMW16_U_XOR_I32_A32, ATOMIC_RMW16_U_XOR_I32_A32_S }, |
| 9862 | { ATOMIC_RMW16_U_XOR_I32_A64, ATOMIC_RMW16_U_XOR_I32_A64_S }, |
| 9863 | { ATOMIC_RMW16_U_XOR_I64_A32, ATOMIC_RMW16_U_XOR_I64_A32_S }, |
| 9864 | { ATOMIC_RMW16_U_XOR_I64_A64, ATOMIC_RMW16_U_XOR_I64_A64_S }, |
| 9865 | { ATOMIC_RMW32_U_ADD_I64_A32, ATOMIC_RMW32_U_ADD_I64_A32_S }, |
| 9866 | { ATOMIC_RMW32_U_ADD_I64_A64, ATOMIC_RMW32_U_ADD_I64_A64_S }, |
| 9867 | { ATOMIC_RMW32_U_AND_I64_A32, ATOMIC_RMW32_U_AND_I64_A32_S }, |
| 9868 | { ATOMIC_RMW32_U_AND_I64_A64, ATOMIC_RMW32_U_AND_I64_A64_S }, |
| 9869 | { ATOMIC_RMW32_U_CMPXCHG_I64_A32, ATOMIC_RMW32_U_CMPXCHG_I64_A32_S }, |
| 9870 | { ATOMIC_RMW32_U_CMPXCHG_I64_A64, ATOMIC_RMW32_U_CMPXCHG_I64_A64_S }, |
| 9871 | { ATOMIC_RMW32_U_OR_I64_A32, ATOMIC_RMW32_U_OR_I64_A32_S }, |
| 9872 | { ATOMIC_RMW32_U_OR_I64_A64, ATOMIC_RMW32_U_OR_I64_A64_S }, |
| 9873 | { ATOMIC_RMW32_U_SUB_I64_A32, ATOMIC_RMW32_U_SUB_I64_A32_S }, |
| 9874 | { ATOMIC_RMW32_U_SUB_I64_A64, ATOMIC_RMW32_U_SUB_I64_A64_S }, |
| 9875 | { ATOMIC_RMW32_U_XCHG_I64_A32, ATOMIC_RMW32_U_XCHG_I64_A32_S }, |
| 9876 | { ATOMIC_RMW32_U_XCHG_I64_A64, ATOMIC_RMW32_U_XCHG_I64_A64_S }, |
| 9877 | { ATOMIC_RMW32_U_XOR_I64_A32, ATOMIC_RMW32_U_XOR_I64_A32_S }, |
| 9878 | { ATOMIC_RMW32_U_XOR_I64_A64, ATOMIC_RMW32_U_XOR_I64_A64_S }, |
| 9879 | { ATOMIC_RMW8_U_ADD_I32_A32, ATOMIC_RMW8_U_ADD_I32_A32_S }, |
| 9880 | { ATOMIC_RMW8_U_ADD_I32_A64, ATOMIC_RMW8_U_ADD_I32_A64_S }, |
| 9881 | { ATOMIC_RMW8_U_ADD_I64_A32, ATOMIC_RMW8_U_ADD_I64_A32_S }, |
| 9882 | { ATOMIC_RMW8_U_ADD_I64_A64, ATOMIC_RMW8_U_ADD_I64_A64_S }, |
| 9883 | { ATOMIC_RMW8_U_AND_I32_A32, ATOMIC_RMW8_U_AND_I32_A32_S }, |
| 9884 | { ATOMIC_RMW8_U_AND_I32_A64, ATOMIC_RMW8_U_AND_I32_A64_S }, |
| 9885 | { ATOMIC_RMW8_U_AND_I64_A32, ATOMIC_RMW8_U_AND_I64_A32_S }, |
| 9886 | { ATOMIC_RMW8_U_AND_I64_A64, ATOMIC_RMW8_U_AND_I64_A64_S }, |
| 9887 | { ATOMIC_RMW8_U_CMPXCHG_I32_A32, ATOMIC_RMW8_U_CMPXCHG_I32_A32_S }, |
| 9888 | { ATOMIC_RMW8_U_CMPXCHG_I32_A64, ATOMIC_RMW8_U_CMPXCHG_I32_A64_S }, |
| 9889 | { ATOMIC_RMW8_U_CMPXCHG_I64_A32, ATOMIC_RMW8_U_CMPXCHG_I64_A32_S }, |
| 9890 | { ATOMIC_RMW8_U_CMPXCHG_I64_A64, ATOMIC_RMW8_U_CMPXCHG_I64_A64_S }, |
| 9891 | { ATOMIC_RMW8_U_OR_I32_A32, ATOMIC_RMW8_U_OR_I32_A32_S }, |
| 9892 | { ATOMIC_RMW8_U_OR_I32_A64, ATOMIC_RMW8_U_OR_I32_A64_S }, |
| 9893 | { ATOMIC_RMW8_U_OR_I64_A32, ATOMIC_RMW8_U_OR_I64_A32_S }, |
| 9894 | { ATOMIC_RMW8_U_OR_I64_A64, ATOMIC_RMW8_U_OR_I64_A64_S }, |
| 9895 | { ATOMIC_RMW8_U_SUB_I32_A32, ATOMIC_RMW8_U_SUB_I32_A32_S }, |
| 9896 | { ATOMIC_RMW8_U_SUB_I32_A64, ATOMIC_RMW8_U_SUB_I32_A64_S }, |
| 9897 | { ATOMIC_RMW8_U_SUB_I64_A32, ATOMIC_RMW8_U_SUB_I64_A32_S }, |
| 9898 | { ATOMIC_RMW8_U_SUB_I64_A64, ATOMIC_RMW8_U_SUB_I64_A64_S }, |
| 9899 | { ATOMIC_RMW8_U_XCHG_I32_A32, ATOMIC_RMW8_U_XCHG_I32_A32_S }, |
| 9900 | { ATOMIC_RMW8_U_XCHG_I32_A64, ATOMIC_RMW8_U_XCHG_I32_A64_S }, |
| 9901 | { ATOMIC_RMW8_U_XCHG_I64_A32, ATOMIC_RMW8_U_XCHG_I64_A32_S }, |
| 9902 | { ATOMIC_RMW8_U_XCHG_I64_A64, ATOMIC_RMW8_U_XCHG_I64_A64_S }, |
| 9903 | { ATOMIC_RMW8_U_XOR_I32_A32, ATOMIC_RMW8_U_XOR_I32_A32_S }, |
| 9904 | { ATOMIC_RMW8_U_XOR_I32_A64, ATOMIC_RMW8_U_XOR_I32_A64_S }, |
| 9905 | { ATOMIC_RMW8_U_XOR_I64_A32, ATOMIC_RMW8_U_XOR_I64_A32_S }, |
| 9906 | { ATOMIC_RMW8_U_XOR_I64_A64, ATOMIC_RMW8_U_XOR_I64_A64_S }, |
| 9907 | { ATOMIC_RMW_ADD_I32_A32, ATOMIC_RMW_ADD_I32_A32_S }, |
| 9908 | { ATOMIC_RMW_ADD_I32_A64, ATOMIC_RMW_ADD_I32_A64_S }, |
| 9909 | { ATOMIC_RMW_ADD_I64_A32, ATOMIC_RMW_ADD_I64_A32_S }, |
| 9910 | { ATOMIC_RMW_ADD_I64_A64, ATOMIC_RMW_ADD_I64_A64_S }, |
| 9911 | { ATOMIC_RMW_AND_I32_A32, ATOMIC_RMW_AND_I32_A32_S }, |
| 9912 | { ATOMIC_RMW_AND_I32_A64, ATOMIC_RMW_AND_I32_A64_S }, |
| 9913 | { ATOMIC_RMW_AND_I64_A32, ATOMIC_RMW_AND_I64_A32_S }, |
| 9914 | { ATOMIC_RMW_AND_I64_A64, ATOMIC_RMW_AND_I64_A64_S }, |
| 9915 | { ATOMIC_RMW_CMPXCHG_I32_A32, ATOMIC_RMW_CMPXCHG_I32_A32_S }, |
| 9916 | { ATOMIC_RMW_CMPXCHG_I32_A64, ATOMIC_RMW_CMPXCHG_I32_A64_S }, |
| 9917 | { ATOMIC_RMW_CMPXCHG_I64_A32, ATOMIC_RMW_CMPXCHG_I64_A32_S }, |
| 9918 | { ATOMIC_RMW_CMPXCHG_I64_A64, ATOMIC_RMW_CMPXCHG_I64_A64_S }, |
| 9919 | { ATOMIC_RMW_OR_I32_A32, ATOMIC_RMW_OR_I32_A32_S }, |
| 9920 | { ATOMIC_RMW_OR_I32_A64, ATOMIC_RMW_OR_I32_A64_S }, |
| 9921 | { ATOMIC_RMW_OR_I64_A32, ATOMIC_RMW_OR_I64_A32_S }, |
| 9922 | { ATOMIC_RMW_OR_I64_A64, ATOMIC_RMW_OR_I64_A64_S }, |
| 9923 | { ATOMIC_RMW_SUB_I32_A32, ATOMIC_RMW_SUB_I32_A32_S }, |
| 9924 | { ATOMIC_RMW_SUB_I32_A64, ATOMIC_RMW_SUB_I32_A64_S }, |
| 9925 | { ATOMIC_RMW_SUB_I64_A32, ATOMIC_RMW_SUB_I64_A32_S }, |
| 9926 | { ATOMIC_RMW_SUB_I64_A64, ATOMIC_RMW_SUB_I64_A64_S }, |
| 9927 | { ATOMIC_RMW_XCHG_I32_A32, ATOMIC_RMW_XCHG_I32_A32_S }, |
| 9928 | { ATOMIC_RMW_XCHG_I32_A64, ATOMIC_RMW_XCHG_I32_A64_S }, |
| 9929 | { ATOMIC_RMW_XCHG_I64_A32, ATOMIC_RMW_XCHG_I64_A32_S }, |
| 9930 | { ATOMIC_RMW_XCHG_I64_A64, ATOMIC_RMW_XCHG_I64_A64_S }, |
| 9931 | { ATOMIC_RMW_XOR_I32_A32, ATOMIC_RMW_XOR_I32_A32_S }, |
| 9932 | { ATOMIC_RMW_XOR_I32_A64, ATOMIC_RMW_XOR_I32_A64_S }, |
| 9933 | { ATOMIC_RMW_XOR_I64_A32, ATOMIC_RMW_XOR_I64_A32_S }, |
| 9934 | { ATOMIC_RMW_XOR_I64_A64, ATOMIC_RMW_XOR_I64_A64_S }, |
| 9935 | { ATOMIC_STORE16_I32_A32, ATOMIC_STORE16_I32_A32_S }, |
| 9936 | { ATOMIC_STORE16_I32_A64, ATOMIC_STORE16_I32_A64_S }, |
| 9937 | { ATOMIC_STORE16_I64_A32, ATOMIC_STORE16_I64_A32_S }, |
| 9938 | { ATOMIC_STORE16_I64_A64, ATOMIC_STORE16_I64_A64_S }, |
| 9939 | { ATOMIC_STORE32_I64_A32, ATOMIC_STORE32_I64_A32_S }, |
| 9940 | { ATOMIC_STORE32_I64_A64, ATOMIC_STORE32_I64_A64_S }, |
| 9941 | { ATOMIC_STORE8_I32_A32, ATOMIC_STORE8_I32_A32_S }, |
| 9942 | { ATOMIC_STORE8_I32_A64, ATOMIC_STORE8_I32_A64_S }, |
| 9943 | { ATOMIC_STORE8_I64_A32, ATOMIC_STORE8_I64_A32_S }, |
| 9944 | { ATOMIC_STORE8_I64_A64, ATOMIC_STORE8_I64_A64_S }, |
| 9945 | { ATOMIC_STORE_I32_A32, ATOMIC_STORE_I32_A32_S }, |
| 9946 | { ATOMIC_STORE_I32_A64, ATOMIC_STORE_I32_A64_S }, |
| 9947 | { ATOMIC_STORE_I64_A32, ATOMIC_STORE_I64_A32_S }, |
| 9948 | { ATOMIC_STORE_I64_A64, ATOMIC_STORE_I64_A64_S }, |
| 9949 | { AVGR_U_I16x8, AVGR_U_I16x8_S }, |
| 9950 | { AVGR_U_I8x16, AVGR_U_I8x16_S }, |
| 9951 | { BITMASK_I16x8, BITMASK_I16x8_S }, |
| 9952 | { BITMASK_I32x4, BITMASK_I32x4_S }, |
| 9953 | { BITMASK_I64x2, BITMASK_I64x2_S }, |
| 9954 | { BITMASK_I8x16, BITMASK_I8x16_S }, |
| 9955 | { BITSELECT, BITSELECT_S }, |
| 9956 | { BLOCK, BLOCK_S }, |
| 9957 | { BR, BR_S }, |
| 9958 | { BR_IF, BR_IF_S }, |
| 9959 | { BR_TABLE_I32, BR_TABLE_I32_S }, |
| 9960 | { BR_TABLE_I64, BR_TABLE_I64_S }, |
| 9961 | { BR_UNLESS, BR_UNLESS_S }, |
| 9962 | { CALL, CALL_S }, |
| 9963 | { CALL_INDIRECT, CALL_INDIRECT_S }, |
| 9964 | { CALL_REF, CALL_REF_S }, |
| 9965 | { CATCH, CATCH_S }, |
| 9966 | { CATCH_ALL, CATCH_ALL_S }, |
| 9967 | { CATCH_ALL_LEGACY, CATCH_ALL_LEGACY_S }, |
| 9968 | { CATCH_ALL_REF, CATCH_ALL_REF_S }, |
| 9969 | { CATCH_LEGACY, CATCH_LEGACY_S }, |
| 9970 | { CATCH_REF, CATCH_REF_S }, |
| 9971 | { CEIL_F16x8, CEIL_F16x8_S }, |
| 9972 | { CEIL_F32, CEIL_F32_S }, |
| 9973 | { CEIL_F32x4, CEIL_F32x4_S }, |
| 9974 | { CEIL_F64, CEIL_F64_S }, |
| 9975 | { CEIL_F64x2, CEIL_F64x2_S }, |
| 9976 | { CLZ_I32, CLZ_I32_S }, |
| 9977 | { CLZ_I64, CLZ_I64_S }, |
| 9978 | { CONST_F32, CONST_F32_S }, |
| 9979 | { CONST_F64, CONST_F64_S }, |
| 9980 | { CONST_I32, CONST_I32_S }, |
| 9981 | { CONST_I64, CONST_I64_S }, |
| 9982 | { CONST_V128_F32x4, CONST_V128_F32x4_S }, |
| 9983 | { CONST_V128_F64x2, CONST_V128_F64x2_S }, |
| 9984 | { CONST_V128_I16x8, CONST_V128_I16x8_S }, |
| 9985 | { CONST_V128_I32x4, CONST_V128_I32x4_S }, |
| 9986 | { CONST_V128_I64x2, CONST_V128_I64x2_S }, |
| 9987 | { CONST_V128_I8x16, CONST_V128_I8x16_S }, |
| 9988 | { COPYSIGN_F32, COPYSIGN_F32_S }, |
| 9989 | { COPYSIGN_F64, COPYSIGN_F64_S }, |
| 9990 | { COPY_EXNREF, COPY_EXNREF_S }, |
| 9991 | { COPY_EXTERNREF, COPY_EXTERNREF_S }, |
| 9992 | { COPY_F32, COPY_F32_S }, |
| 9993 | { COPY_F64, COPY_F64_S }, |
| 9994 | { COPY_FUNCREF, COPY_FUNCREF_S }, |
| 9995 | { COPY_I32, COPY_I32_S }, |
| 9996 | { COPY_I64, COPY_I64_S }, |
| 9997 | { COPY_V128, COPY_V128_S }, |
| 9998 | { CTZ_I32, CTZ_I32_S }, |
| 9999 | { CTZ_I64, CTZ_I64_S }, |
| 10000 | { DATA_DROP, DATA_DROP_S }, |
| 10001 | { DEBUG_UNREACHABLE, DEBUG_UNREACHABLE_S }, |
| 10002 | { DELEGATE, DELEGATE_S }, |
| 10003 | { DIV_F16x8, DIV_F16x8_S }, |
| 10004 | { DIV_F32, DIV_F32_S }, |
| 10005 | { DIV_F32x4, DIV_F32x4_S }, |
| 10006 | { DIV_F64, DIV_F64_S }, |
| 10007 | { DIV_F64x2, DIV_F64x2_S }, |
| 10008 | { DIV_S_I32, DIV_S_I32_S }, |
| 10009 | { DIV_S_I64, DIV_S_I64_S }, |
| 10010 | { DIV_U_I32, DIV_U_I32_S }, |
| 10011 | { DIV_U_I64, DIV_U_I64_S }, |
| 10012 | { DOT, DOT_S }, |
| 10013 | { DROP_EXNREF, DROP_EXNREF_S }, |
| 10014 | { DROP_EXTERNREF, DROP_EXTERNREF_S }, |
| 10015 | { DROP_F32, DROP_F32_S }, |
| 10016 | { DROP_F64, DROP_F64_S }, |
| 10017 | { DROP_FUNCREF, DROP_FUNCREF_S }, |
| 10018 | { DROP_I32, DROP_I32_S }, |
| 10019 | { DROP_I64, DROP_I64_S }, |
| 10020 | { DROP_V128, DROP_V128_S }, |
| 10021 | { ELSE, ELSE_S }, |
| 10022 | { END, END_S }, |
| 10023 | { END_BLOCK, END_BLOCK_S }, |
| 10024 | { END_FUNCTION, END_FUNCTION_S }, |
| 10025 | { END_IF, END_IF_S }, |
| 10026 | { END_LOOP, END_LOOP_S }, |
| 10027 | { END_TRY, END_TRY_S }, |
| 10028 | { END_TRY_TABLE, END_TRY_TABLE_S }, |
| 10029 | { EQZ_I32, EQZ_I32_S }, |
| 10030 | { EQZ_I64, EQZ_I64_S }, |
| 10031 | { EQ_F16x8, EQ_F16x8_S }, |
| 10032 | { EQ_F32, EQ_F32_S }, |
| 10033 | { EQ_F32x4, EQ_F32x4_S }, |
| 10034 | { EQ_F64, EQ_F64_S }, |
| 10035 | { EQ_F64x2, EQ_F64x2_S }, |
| 10036 | { EQ_I16x8, EQ_I16x8_S }, |
| 10037 | { EQ_I32, EQ_I32_S }, |
| 10038 | { EQ_I32x4, EQ_I32x4_S }, |
| 10039 | { EQ_I64, EQ_I64_S }, |
| 10040 | { EQ_I64x2, EQ_I64x2_S }, |
| 10041 | { EQ_I8x16, EQ_I8x16_S }, |
| 10042 | { EXTMUL_HIGH_S_I16x8, EXTMUL_HIGH_S_I16x8_S }, |
| 10043 | { EXTMUL_HIGH_S_I32x4, EXTMUL_HIGH_S_I32x4_S }, |
| 10044 | { EXTMUL_HIGH_S_I64x2, EXTMUL_HIGH_S_I64x2_S }, |
| 10045 | { EXTMUL_HIGH_U_I16x8, EXTMUL_HIGH_U_I16x8_S }, |
| 10046 | { EXTMUL_HIGH_U_I32x4, EXTMUL_HIGH_U_I32x4_S }, |
| 10047 | { EXTMUL_HIGH_U_I64x2, EXTMUL_HIGH_U_I64x2_S }, |
| 10048 | { EXTMUL_LOW_S_I16x8, EXTMUL_LOW_S_I16x8_S }, |
| 10049 | { EXTMUL_LOW_S_I32x4, EXTMUL_LOW_S_I32x4_S }, |
| 10050 | { EXTMUL_LOW_S_I64x2, EXTMUL_LOW_S_I64x2_S }, |
| 10051 | { EXTMUL_LOW_U_I16x8, EXTMUL_LOW_U_I16x8_S }, |
| 10052 | { EXTMUL_LOW_U_I32x4, EXTMUL_LOW_U_I32x4_S }, |
| 10053 | { EXTMUL_LOW_U_I64x2, EXTMUL_LOW_U_I64x2_S }, |
| 10054 | { EXTRACT_LANE_F16x8, EXTRACT_LANE_F16x8_S }, |
| 10055 | { EXTRACT_LANE_F32x4, EXTRACT_LANE_F32x4_S }, |
| 10056 | { EXTRACT_LANE_F64x2, EXTRACT_LANE_F64x2_S }, |
| 10057 | { EXTRACT_LANE_I16x8_s, EXTRACT_LANE_I16x8_s_S }, |
| 10058 | { EXTRACT_LANE_I16x8_u, EXTRACT_LANE_I16x8_u_S }, |
| 10059 | { EXTRACT_LANE_I32x4, EXTRACT_LANE_I32x4_S }, |
| 10060 | { EXTRACT_LANE_I64x2, EXTRACT_LANE_I64x2_S }, |
| 10061 | { EXTRACT_LANE_I8x16_s, EXTRACT_LANE_I8x16_s_S }, |
| 10062 | { EXTRACT_LANE_I8x16_u, EXTRACT_LANE_I8x16_u_S }, |
| 10063 | { F32_CONVERT_S_I32, F32_CONVERT_S_I32_S }, |
| 10064 | { F32_CONVERT_S_I64, F32_CONVERT_S_I64_S }, |
| 10065 | { F32_CONVERT_U_I32, F32_CONVERT_U_I32_S }, |
| 10066 | { F32_CONVERT_U_I64, F32_CONVERT_U_I64_S }, |
| 10067 | { F32_DEMOTE_F64, F32_DEMOTE_F64_S }, |
| 10068 | { F32_REINTERPRET_I32, F32_REINTERPRET_I32_S }, |
| 10069 | { F64_CONVERT_S_I32, F64_CONVERT_S_I32_S }, |
| 10070 | { F64_CONVERT_S_I64, F64_CONVERT_S_I64_S }, |
| 10071 | { F64_CONVERT_U_I32, F64_CONVERT_U_I32_S }, |
| 10072 | { F64_CONVERT_U_I64, F64_CONVERT_U_I64_S }, |
| 10073 | { F64_PROMOTE_F32, F64_PROMOTE_F32_S }, |
| 10074 | { F64_REINTERPRET_I64, F64_REINTERPRET_I64_S }, |
| 10075 | { FALLTHROUGH_RETURN, FALLTHROUGH_RETURN_S }, |
| 10076 | { FLOOR_F16x8, FLOOR_F16x8_S }, |
| 10077 | { FLOOR_F32, FLOOR_F32_S }, |
| 10078 | { FLOOR_F32x4, FLOOR_F32x4_S }, |
| 10079 | { FLOOR_F64, FLOOR_F64_S }, |
| 10080 | { FLOOR_F64x2, FLOOR_F64x2_S }, |
| 10081 | { FP_TO_SINT_I32_F32, FP_TO_SINT_I32_F32_S }, |
| 10082 | { FP_TO_SINT_I32_F64, FP_TO_SINT_I32_F64_S }, |
| 10083 | { FP_TO_SINT_I64_F32, FP_TO_SINT_I64_F32_S }, |
| 10084 | { FP_TO_SINT_I64_F64, FP_TO_SINT_I64_F64_S }, |
| 10085 | { FP_TO_UINT_I32_F32, FP_TO_UINT_I32_F32_S }, |
| 10086 | { FP_TO_UINT_I32_F64, FP_TO_UINT_I32_F64_S }, |
| 10087 | { FP_TO_UINT_I64_F32, FP_TO_UINT_I64_F32_S }, |
| 10088 | { FP_TO_UINT_I64_F64, FP_TO_UINT_I64_F64_S }, |
| 10089 | { GE_F16x8, GE_F16x8_S }, |
| 10090 | { GE_F32, GE_F32_S }, |
| 10091 | { GE_F32x4, GE_F32x4_S }, |
| 10092 | { GE_F64, GE_F64_S }, |
| 10093 | { GE_F64x2, GE_F64x2_S }, |
| 10094 | { GE_S_I16x8, GE_S_I16x8_S }, |
| 10095 | { GE_S_I32, GE_S_I32_S }, |
| 10096 | { GE_S_I32x4, GE_S_I32x4_S }, |
| 10097 | { GE_S_I64, GE_S_I64_S }, |
| 10098 | { GE_S_I64x2, GE_S_I64x2_S }, |
| 10099 | { GE_S_I8x16, GE_S_I8x16_S }, |
| 10100 | { GE_U_I16x8, GE_U_I16x8_S }, |
| 10101 | { GE_U_I32, GE_U_I32_S }, |
| 10102 | { GE_U_I32x4, GE_U_I32x4_S }, |
| 10103 | { GE_U_I64, GE_U_I64_S }, |
| 10104 | { GE_U_I8x16, GE_U_I8x16_S }, |
| 10105 | { GLOBAL_GET_EXNREF, GLOBAL_GET_EXNREF_S }, |
| 10106 | { GLOBAL_GET_EXTERNREF, GLOBAL_GET_EXTERNREF_S }, |
| 10107 | { GLOBAL_GET_F32, GLOBAL_GET_F32_S }, |
| 10108 | { GLOBAL_GET_F64, GLOBAL_GET_F64_S }, |
| 10109 | { GLOBAL_GET_FUNCREF, GLOBAL_GET_FUNCREF_S }, |
| 10110 | { GLOBAL_GET_I32, GLOBAL_GET_I32_S }, |
| 10111 | { GLOBAL_GET_I64, GLOBAL_GET_I64_S }, |
| 10112 | { GLOBAL_GET_V128, GLOBAL_GET_V128_S }, |
| 10113 | { GLOBAL_SET_EXNREF, GLOBAL_SET_EXNREF_S }, |
| 10114 | { GLOBAL_SET_EXTERNREF, GLOBAL_SET_EXTERNREF_S }, |
| 10115 | { GLOBAL_SET_F32, GLOBAL_SET_F32_S }, |
| 10116 | { GLOBAL_SET_F64, GLOBAL_SET_F64_S }, |
| 10117 | { GLOBAL_SET_FUNCREF, GLOBAL_SET_FUNCREF_S }, |
| 10118 | { GLOBAL_SET_I32, GLOBAL_SET_I32_S }, |
| 10119 | { GLOBAL_SET_I64, GLOBAL_SET_I64_S }, |
| 10120 | { GLOBAL_SET_V128, GLOBAL_SET_V128_S }, |
| 10121 | { GT_F16x8, GT_F16x8_S }, |
| 10122 | { GT_F32, GT_F32_S }, |
| 10123 | { GT_F32x4, GT_F32x4_S }, |
| 10124 | { GT_F64, GT_F64_S }, |
| 10125 | { GT_F64x2, GT_F64x2_S }, |
| 10126 | { GT_S_I16x8, GT_S_I16x8_S }, |
| 10127 | { GT_S_I32, GT_S_I32_S }, |
| 10128 | { GT_S_I32x4, GT_S_I32x4_S }, |
| 10129 | { GT_S_I64, GT_S_I64_S }, |
| 10130 | { GT_S_I64x2, GT_S_I64x2_S }, |
| 10131 | { GT_S_I8x16, GT_S_I8x16_S }, |
| 10132 | { GT_U_I16x8, GT_U_I16x8_S }, |
| 10133 | { GT_U_I32, GT_U_I32_S }, |
| 10134 | { GT_U_I32x4, GT_U_I32x4_S }, |
| 10135 | { GT_U_I64, GT_U_I64_S }, |
| 10136 | { GT_U_I8x16, GT_U_I8x16_S }, |
| 10137 | { I32_EXTEND16_S_I32, I32_EXTEND16_S_I32_S }, |
| 10138 | { I32_EXTEND8_S_I32, I32_EXTEND8_S_I32_S }, |
| 10139 | { I32_REINTERPRET_F32, I32_REINTERPRET_F32_S }, |
| 10140 | { I32_TRUNC_S_F32, I32_TRUNC_S_F32_S }, |
| 10141 | { I32_TRUNC_S_F64, I32_TRUNC_S_F64_S }, |
| 10142 | { I32_TRUNC_S_SAT_F32, I32_TRUNC_S_SAT_F32_S }, |
| 10143 | { I32_TRUNC_S_SAT_F64, I32_TRUNC_S_SAT_F64_S }, |
| 10144 | { I32_TRUNC_U_F32, I32_TRUNC_U_F32_S }, |
| 10145 | { I32_TRUNC_U_F64, I32_TRUNC_U_F64_S }, |
| 10146 | { I32_TRUNC_U_SAT_F32, I32_TRUNC_U_SAT_F32_S }, |
| 10147 | { I32_TRUNC_U_SAT_F64, I32_TRUNC_U_SAT_F64_S }, |
| 10148 | { I32_WRAP_I64, I32_WRAP_I64_S }, |
| 10149 | { I64_ADD128, I64_ADD128_S }, |
| 10150 | { I64_EXTEND16_S_I64, I64_EXTEND16_S_I64_S }, |
| 10151 | { I64_EXTEND32_S_I64, I64_EXTEND32_S_I64_S }, |
| 10152 | { I64_EXTEND8_S_I64, I64_EXTEND8_S_I64_S }, |
| 10153 | { I64_EXTEND_S_I32, I64_EXTEND_S_I32_S }, |
| 10154 | { I64_EXTEND_U_I32, I64_EXTEND_U_I32_S }, |
| 10155 | { I64_MUL_WIDE_S, I64_MUL_WIDE_S_S }, |
| 10156 | { I64_MUL_WIDE_U, I64_MUL_WIDE_U_S }, |
| 10157 | { I64_REINTERPRET_F64, I64_REINTERPRET_F64_S }, |
| 10158 | { I64_SUB128, I64_SUB128_S }, |
| 10159 | { I64_TRUNC_S_F32, I64_TRUNC_S_F32_S }, |
| 10160 | { I64_TRUNC_S_F64, I64_TRUNC_S_F64_S }, |
| 10161 | { I64_TRUNC_S_SAT_F32, I64_TRUNC_S_SAT_F32_S }, |
| 10162 | { I64_TRUNC_S_SAT_F64, I64_TRUNC_S_SAT_F64_S }, |
| 10163 | { I64_TRUNC_U_F32, I64_TRUNC_U_F32_S }, |
| 10164 | { I64_TRUNC_U_F64, I64_TRUNC_U_F64_S }, |
| 10165 | { I64_TRUNC_U_SAT_F32, I64_TRUNC_U_SAT_F32_S }, |
| 10166 | { I64_TRUNC_U_SAT_F64, I64_TRUNC_U_SAT_F64_S }, |
| 10167 | { IF, IF_S }, |
| 10168 | { LANESELECT_I16x8, LANESELECT_I16x8_S }, |
| 10169 | { LANESELECT_I32x4, LANESELECT_I32x4_S }, |
| 10170 | { LANESELECT_I64x2, LANESELECT_I64x2_S }, |
| 10171 | { LANESELECT_I8x16, LANESELECT_I8x16_S }, |
| 10172 | { LE_F16x8, LE_F16x8_S }, |
| 10173 | { LE_F32, LE_F32_S }, |
| 10174 | { LE_F32x4, LE_F32x4_S }, |
| 10175 | { LE_F64, LE_F64_S }, |
| 10176 | { LE_F64x2, LE_F64x2_S }, |
| 10177 | { LE_S_I16x8, LE_S_I16x8_S }, |
| 10178 | { LE_S_I32, LE_S_I32_S }, |
| 10179 | { LE_S_I32x4, LE_S_I32x4_S }, |
| 10180 | { LE_S_I64, LE_S_I64_S }, |
| 10181 | { LE_S_I64x2, LE_S_I64x2_S }, |
| 10182 | { LE_S_I8x16, LE_S_I8x16_S }, |
| 10183 | { LE_U_I16x8, LE_U_I16x8_S }, |
| 10184 | { LE_U_I32, LE_U_I32_S }, |
| 10185 | { LE_U_I32x4, LE_U_I32x4_S }, |
| 10186 | { LE_U_I64, LE_U_I64_S }, |
| 10187 | { LE_U_I8x16, LE_U_I8x16_S }, |
| 10188 | { LOAD16_SPLAT_A32, LOAD16_SPLAT_A32_S }, |
| 10189 | { LOAD16_SPLAT_A64, LOAD16_SPLAT_A64_S }, |
| 10190 | { LOAD16_S_I32_A32, LOAD16_S_I32_A32_S }, |
| 10191 | { LOAD16_S_I32_A64, LOAD16_S_I32_A64_S }, |
| 10192 | { LOAD16_S_I64_A32, LOAD16_S_I64_A32_S }, |
| 10193 | { LOAD16_S_I64_A64, LOAD16_S_I64_A64_S }, |
| 10194 | { LOAD16_U_I32_A32, LOAD16_U_I32_A32_S }, |
| 10195 | { LOAD16_U_I32_A64, LOAD16_U_I32_A64_S }, |
| 10196 | { LOAD16_U_I64_A32, LOAD16_U_I64_A32_S }, |
| 10197 | { LOAD16_U_I64_A64, LOAD16_U_I64_A64_S }, |
| 10198 | { LOAD32_SPLAT_A32, LOAD32_SPLAT_A32_S }, |
| 10199 | { LOAD32_SPLAT_A64, LOAD32_SPLAT_A64_S }, |
| 10200 | { LOAD32_S_I64_A32, LOAD32_S_I64_A32_S }, |
| 10201 | { LOAD32_S_I64_A64, LOAD32_S_I64_A64_S }, |
| 10202 | { LOAD32_U_I64_A32, LOAD32_U_I64_A32_S }, |
| 10203 | { LOAD32_U_I64_A64, LOAD32_U_I64_A64_S }, |
| 10204 | { LOAD64_SPLAT_A32, LOAD64_SPLAT_A32_S }, |
| 10205 | { LOAD64_SPLAT_A64, LOAD64_SPLAT_A64_S }, |
| 10206 | { LOAD8_SPLAT_A32, LOAD8_SPLAT_A32_S }, |
| 10207 | { LOAD8_SPLAT_A64, LOAD8_SPLAT_A64_S }, |
| 10208 | { LOAD8_S_I32_A32, LOAD8_S_I32_A32_S }, |
| 10209 | { LOAD8_S_I32_A64, LOAD8_S_I32_A64_S }, |
| 10210 | { LOAD8_S_I64_A32, LOAD8_S_I64_A32_S }, |
| 10211 | { LOAD8_S_I64_A64, LOAD8_S_I64_A64_S }, |
| 10212 | { LOAD8_U_I32_A32, LOAD8_U_I32_A32_S }, |
| 10213 | { LOAD8_U_I32_A64, LOAD8_U_I32_A64_S }, |
| 10214 | { LOAD8_U_I64_A32, LOAD8_U_I64_A32_S }, |
| 10215 | { LOAD8_U_I64_A64, LOAD8_U_I64_A64_S }, |
| 10216 | { LOAD_EXTEND_S_I16x8_A32, LOAD_EXTEND_S_I16x8_A32_S }, |
| 10217 | { LOAD_EXTEND_S_I16x8_A64, LOAD_EXTEND_S_I16x8_A64_S }, |
| 10218 | { LOAD_EXTEND_S_I32x4_A32, LOAD_EXTEND_S_I32x4_A32_S }, |
| 10219 | { LOAD_EXTEND_S_I32x4_A64, LOAD_EXTEND_S_I32x4_A64_S }, |
| 10220 | { LOAD_EXTEND_S_I64x2_A32, LOAD_EXTEND_S_I64x2_A32_S }, |
| 10221 | { LOAD_EXTEND_S_I64x2_A64, LOAD_EXTEND_S_I64x2_A64_S }, |
| 10222 | { LOAD_EXTEND_U_I16x8_A32, LOAD_EXTEND_U_I16x8_A32_S }, |
| 10223 | { LOAD_EXTEND_U_I16x8_A64, LOAD_EXTEND_U_I16x8_A64_S }, |
| 10224 | { LOAD_EXTEND_U_I32x4_A32, LOAD_EXTEND_U_I32x4_A32_S }, |
| 10225 | { LOAD_EXTEND_U_I32x4_A64, LOAD_EXTEND_U_I32x4_A64_S }, |
| 10226 | { LOAD_EXTEND_U_I64x2_A32, LOAD_EXTEND_U_I64x2_A32_S }, |
| 10227 | { LOAD_EXTEND_U_I64x2_A64, LOAD_EXTEND_U_I64x2_A64_S }, |
| 10228 | { LOAD_F16_F32_A32, LOAD_F16_F32_A32_S }, |
| 10229 | { LOAD_F16_F32_A64, LOAD_F16_F32_A64_S }, |
| 10230 | { LOAD_F32_A32, LOAD_F32_A32_S }, |
| 10231 | { LOAD_F32_A64, LOAD_F32_A64_S }, |
| 10232 | { LOAD_F64_A32, LOAD_F64_A32_S }, |
| 10233 | { LOAD_F64_A64, LOAD_F64_A64_S }, |
| 10234 | { LOAD_I32_A32, LOAD_I32_A32_S }, |
| 10235 | { LOAD_I32_A64, LOAD_I32_A64_S }, |
| 10236 | { LOAD_I64_A32, LOAD_I64_A32_S }, |
| 10237 | { LOAD_I64_A64, LOAD_I64_A64_S }, |
| 10238 | { LOAD_LANE_16_A32, LOAD_LANE_16_A32_S }, |
| 10239 | { LOAD_LANE_16_A64, LOAD_LANE_16_A64_S }, |
| 10240 | { LOAD_LANE_32_A32, LOAD_LANE_32_A32_S }, |
| 10241 | { LOAD_LANE_32_A64, LOAD_LANE_32_A64_S }, |
| 10242 | { LOAD_LANE_64_A32, LOAD_LANE_64_A32_S }, |
| 10243 | { LOAD_LANE_64_A64, LOAD_LANE_64_A64_S }, |
| 10244 | { LOAD_LANE_8_A32, LOAD_LANE_8_A32_S }, |
| 10245 | { LOAD_LANE_8_A64, LOAD_LANE_8_A64_S }, |
| 10246 | { LOAD_V128_A32, LOAD_V128_A32_S }, |
| 10247 | { LOAD_V128_A64, LOAD_V128_A64_S }, |
| 10248 | { LOAD_ZERO_32_A32, LOAD_ZERO_32_A32_S }, |
| 10249 | { LOAD_ZERO_32_A64, LOAD_ZERO_32_A64_S }, |
| 10250 | { LOAD_ZERO_64_A32, LOAD_ZERO_64_A32_S }, |
| 10251 | { LOAD_ZERO_64_A64, LOAD_ZERO_64_A64_S }, |
| 10252 | { LOCAL_GET_EXNREF, LOCAL_GET_EXNREF_S }, |
| 10253 | { LOCAL_GET_EXTERNREF, LOCAL_GET_EXTERNREF_S }, |
| 10254 | { LOCAL_GET_F32, LOCAL_GET_F32_S }, |
| 10255 | { LOCAL_GET_F64, LOCAL_GET_F64_S }, |
| 10256 | { LOCAL_GET_FUNCREF, LOCAL_GET_FUNCREF_S }, |
| 10257 | { LOCAL_GET_I32, LOCAL_GET_I32_S }, |
| 10258 | { LOCAL_GET_I64, LOCAL_GET_I64_S }, |
| 10259 | { LOCAL_GET_V128, LOCAL_GET_V128_S }, |
| 10260 | { LOCAL_SET_EXNREF, LOCAL_SET_EXNREF_S }, |
| 10261 | { LOCAL_SET_EXTERNREF, LOCAL_SET_EXTERNREF_S }, |
| 10262 | { LOCAL_SET_F32, LOCAL_SET_F32_S }, |
| 10263 | { LOCAL_SET_F64, LOCAL_SET_F64_S }, |
| 10264 | { LOCAL_SET_FUNCREF, LOCAL_SET_FUNCREF_S }, |
| 10265 | { LOCAL_SET_I32, LOCAL_SET_I32_S }, |
| 10266 | { LOCAL_SET_I64, LOCAL_SET_I64_S }, |
| 10267 | { LOCAL_SET_V128, LOCAL_SET_V128_S }, |
| 10268 | { LOCAL_TEE_EXNREF, LOCAL_TEE_EXNREF_S }, |
| 10269 | { LOCAL_TEE_EXTERNREF, LOCAL_TEE_EXTERNREF_S }, |
| 10270 | { LOCAL_TEE_F32, LOCAL_TEE_F32_S }, |
| 10271 | { LOCAL_TEE_F64, LOCAL_TEE_F64_S }, |
| 10272 | { LOCAL_TEE_FUNCREF, LOCAL_TEE_FUNCREF_S }, |
| 10273 | { LOCAL_TEE_I32, LOCAL_TEE_I32_S }, |
| 10274 | { LOCAL_TEE_I64, LOCAL_TEE_I64_S }, |
| 10275 | { LOCAL_TEE_V128, LOCAL_TEE_V128_S }, |
| 10276 | { LOOP, LOOP_S }, |
| 10277 | { LT_F16x8, LT_F16x8_S }, |
| 10278 | { LT_F32, LT_F32_S }, |
| 10279 | { LT_F32x4, LT_F32x4_S }, |
| 10280 | { LT_F64, LT_F64_S }, |
| 10281 | { LT_F64x2, LT_F64x2_S }, |
| 10282 | { LT_S_I16x8, LT_S_I16x8_S }, |
| 10283 | { LT_S_I32, LT_S_I32_S }, |
| 10284 | { LT_S_I32x4, LT_S_I32x4_S }, |
| 10285 | { LT_S_I64, LT_S_I64_S }, |
| 10286 | { LT_S_I64x2, LT_S_I64x2_S }, |
| 10287 | { LT_S_I8x16, LT_S_I8x16_S }, |
| 10288 | { LT_U_I16x8, LT_U_I16x8_S }, |
| 10289 | { LT_U_I32, LT_U_I32_S }, |
| 10290 | { LT_U_I32x4, LT_U_I32x4_S }, |
| 10291 | { LT_U_I64, LT_U_I64_S }, |
| 10292 | { LT_U_I8x16, LT_U_I8x16_S }, |
| 10293 | { MADD_F16x8, MADD_F16x8_S }, |
| 10294 | { MADD_F32x4, MADD_F32x4_S }, |
| 10295 | { MADD_F64x2, MADD_F64x2_S }, |
| 10296 | { MAX_F16x8, MAX_F16x8_S }, |
| 10297 | { MAX_F32, MAX_F32_S }, |
| 10298 | { MAX_F32x4, MAX_F32x4_S }, |
| 10299 | { MAX_F64, MAX_F64_S }, |
| 10300 | { MAX_F64x2, MAX_F64x2_S }, |
| 10301 | { MAX_S_I16x8, MAX_S_I16x8_S }, |
| 10302 | { MAX_S_I32x4, MAX_S_I32x4_S }, |
| 10303 | { MAX_S_I8x16, MAX_S_I8x16_S }, |
| 10304 | { MAX_U_I16x8, MAX_U_I16x8_S }, |
| 10305 | { MAX_U_I32x4, MAX_U_I32x4_S }, |
| 10306 | { MAX_U_I8x16, MAX_U_I8x16_S }, |
| 10307 | { MEMCPY_A32, MEMCPY_A32_S }, |
| 10308 | { MEMCPY_A64, MEMCPY_A64_S }, |
| 10309 | { MEMORY_ATOMIC_NOTIFY_A32, MEMORY_ATOMIC_NOTIFY_A32_S }, |
| 10310 | { MEMORY_ATOMIC_NOTIFY_A64, MEMORY_ATOMIC_NOTIFY_A64_S }, |
| 10311 | { MEMORY_ATOMIC_WAIT32_A32, MEMORY_ATOMIC_WAIT32_A32_S }, |
| 10312 | { MEMORY_ATOMIC_WAIT32_A64, MEMORY_ATOMIC_WAIT32_A64_S }, |
| 10313 | { MEMORY_ATOMIC_WAIT64_A32, MEMORY_ATOMIC_WAIT64_A32_S }, |
| 10314 | { MEMORY_ATOMIC_WAIT64_A64, MEMORY_ATOMIC_WAIT64_A64_S }, |
| 10315 | { MEMORY_COPY_A32, MEMORY_COPY_A32_S }, |
| 10316 | { MEMORY_COPY_A64, MEMORY_COPY_A64_S }, |
| 10317 | { MEMORY_FILL_A32, MEMORY_FILL_A32_S }, |
| 10318 | { MEMORY_FILL_A64, MEMORY_FILL_A64_S }, |
| 10319 | { MEMORY_INIT_A32, MEMORY_INIT_A32_S }, |
| 10320 | { MEMORY_INIT_A64, MEMORY_INIT_A64_S }, |
| 10321 | { MEMSET_A32, MEMSET_A32_S }, |
| 10322 | { MEMSET_A64, MEMSET_A64_S }, |
| 10323 | { MIN_F16x8, MIN_F16x8_S }, |
| 10324 | { MIN_F32, MIN_F32_S }, |
| 10325 | { MIN_F32x4, MIN_F32x4_S }, |
| 10326 | { MIN_F64, MIN_F64_S }, |
| 10327 | { MIN_F64x2, MIN_F64x2_S }, |
| 10328 | { MIN_S_I16x8, MIN_S_I16x8_S }, |
| 10329 | { MIN_S_I32x4, MIN_S_I32x4_S }, |
| 10330 | { MIN_S_I8x16, MIN_S_I8x16_S }, |
| 10331 | { MIN_U_I16x8, MIN_U_I16x8_S }, |
| 10332 | { MIN_U_I32x4, MIN_U_I32x4_S }, |
| 10333 | { MIN_U_I8x16, MIN_U_I8x16_S }, |
| 10334 | { MUL_F16x8, MUL_F16x8_S }, |
| 10335 | { MUL_F32, MUL_F32_S }, |
| 10336 | { MUL_F32x4, MUL_F32x4_S }, |
| 10337 | { MUL_F64, MUL_F64_S }, |
| 10338 | { MUL_F64x2, MUL_F64x2_S }, |
| 10339 | { MUL_I16x8, MUL_I16x8_S }, |
| 10340 | { MUL_I32, MUL_I32_S }, |
| 10341 | { MUL_I32x4, MUL_I32x4_S }, |
| 10342 | { MUL_I64, MUL_I64_S }, |
| 10343 | { MUL_I64x2, MUL_I64x2_S }, |
| 10344 | { NARROW_S_I16x8, NARROW_S_I16x8_S }, |
| 10345 | { NARROW_S_I8x16, NARROW_S_I8x16_S }, |
| 10346 | { NARROW_U_I16x8, NARROW_U_I16x8_S }, |
| 10347 | { NARROW_U_I8x16, NARROW_U_I8x16_S }, |
| 10348 | { NEAREST_F16x8, NEAREST_F16x8_S }, |
| 10349 | { NEAREST_F32, NEAREST_F32_S }, |
| 10350 | { NEAREST_F32x4, NEAREST_F32x4_S }, |
| 10351 | { NEAREST_F64, NEAREST_F64_S }, |
| 10352 | { NEAREST_F64x2, NEAREST_F64x2_S }, |
| 10353 | { NEG_F16x8, NEG_F16x8_S }, |
| 10354 | { NEG_F32, NEG_F32_S }, |
| 10355 | { NEG_F32x4, NEG_F32x4_S }, |
| 10356 | { NEG_F64, NEG_F64_S }, |
| 10357 | { NEG_F64x2, NEG_F64x2_S }, |
| 10358 | { NEG_I16x8, NEG_I16x8_S }, |
| 10359 | { NEG_I32x4, NEG_I32x4_S }, |
| 10360 | { NEG_I64x2, NEG_I64x2_S }, |
| 10361 | { NEG_I8x16, NEG_I8x16_S }, |
| 10362 | { NE_F16x8, NE_F16x8_S }, |
| 10363 | { NE_F32, NE_F32_S }, |
| 10364 | { NE_F32x4, NE_F32x4_S }, |
| 10365 | { NE_F64, NE_F64_S }, |
| 10366 | { NE_F64x2, NE_F64x2_S }, |
| 10367 | { NE_I16x8, NE_I16x8_S }, |
| 10368 | { NE_I32, NE_I32_S }, |
| 10369 | { NE_I32x4, NE_I32x4_S }, |
| 10370 | { NE_I64, NE_I64_S }, |
| 10371 | { NE_I64x2, NE_I64x2_S }, |
| 10372 | { NE_I8x16, NE_I8x16_S }, |
| 10373 | { NMADD_F16x8, NMADD_F16x8_S }, |
| 10374 | { NMADD_F32x4, NMADD_F32x4_S }, |
| 10375 | { NMADD_F64x2, NMADD_F64x2_S }, |
| 10376 | { NOP, NOP_S }, |
| 10377 | { NOT, NOT_S }, |
| 10378 | { OR, OR_S }, |
| 10379 | { OR_I32, OR_I32_S }, |
| 10380 | { OR_I64, OR_I64_S }, |
| 10381 | { PMAX_F16x8, PMAX_F16x8_S }, |
| 10382 | { PMAX_F32x4, PMAX_F32x4_S }, |
| 10383 | { PMAX_F64x2, PMAX_F64x2_S }, |
| 10384 | { PMIN_F16x8, PMIN_F16x8_S }, |
| 10385 | { PMIN_F32x4, PMIN_F32x4_S }, |
| 10386 | { PMIN_F64x2, PMIN_F64x2_S }, |
| 10387 | { POPCNT_I32, POPCNT_I32_S }, |
| 10388 | { POPCNT_I64, POPCNT_I64_S }, |
| 10389 | { POPCNT_I8x16, POPCNT_I8x16_S }, |
| 10390 | { Q15MULR_SAT_S_I16x8, Q15MULR_SAT_S_I16x8_S }, |
| 10391 | { REF_CAST_FUNCREF, REF_CAST_FUNCREF_S }, |
| 10392 | { REF_FUNC, REF_FUNC_S }, |
| 10393 | { REF_IS_NULL_EXNREF, REF_IS_NULL_EXNREF_S }, |
| 10394 | { REF_IS_NULL_EXTERNREF, REF_IS_NULL_EXTERNREF_S }, |
| 10395 | { REF_IS_NULL_FUNCREF, REF_IS_NULL_FUNCREF_S }, |
| 10396 | { REF_NULL_EXNREF, REF_NULL_EXNREF_S }, |
| 10397 | { REF_NULL_EXTERNREF, REF_NULL_EXTERNREF_S }, |
| 10398 | { REF_NULL_FUNCREF, REF_NULL_FUNCREF_S }, |
| 10399 | { REF_TEST_FUNCREF, REF_TEST_FUNCREF_S }, |
| 10400 | { RELAXED_DOT, RELAXED_DOT_S }, |
| 10401 | { RELAXED_DOT_ADD, RELAXED_DOT_ADD_S }, |
| 10402 | { RELAXED_DOT_BFLOAT, RELAXED_DOT_BFLOAT_S }, |
| 10403 | { RELAXED_Q15MULR_S_I16x8, RELAXED_Q15MULR_S_I16x8_S }, |
| 10404 | { RELAXED_SWIZZLE, RELAXED_SWIZZLE_S }, |
| 10405 | { REM_S_I32, REM_S_I32_S }, |
| 10406 | { REM_S_I64, REM_S_I64_S }, |
| 10407 | { REM_U_I32, REM_U_I32_S }, |
| 10408 | { REM_U_I64, REM_U_I64_S }, |
| 10409 | { REPLACE_LANE_F16x8, REPLACE_LANE_F16x8_S }, |
| 10410 | { REPLACE_LANE_F32x4, REPLACE_LANE_F32x4_S }, |
| 10411 | { REPLACE_LANE_F64x2, REPLACE_LANE_F64x2_S }, |
| 10412 | { REPLACE_LANE_I16x8, REPLACE_LANE_I16x8_S }, |
| 10413 | { REPLACE_LANE_I32x4, REPLACE_LANE_I32x4_S }, |
| 10414 | { REPLACE_LANE_I64x2, REPLACE_LANE_I64x2_S }, |
| 10415 | { REPLACE_LANE_I8x16, REPLACE_LANE_I8x16_S }, |
| 10416 | { RETHROW, RETHROW_S }, |
| 10417 | { RETURN, RETURN_S }, |
| 10418 | { RET_CALL, RET_CALL_S }, |
| 10419 | { RET_CALL_INDIRECT, RET_CALL_INDIRECT_S }, |
| 10420 | { RET_CALL_REF, RET_CALL_REF_S }, |
| 10421 | { ROTL_I32, ROTL_I32_S }, |
| 10422 | { ROTL_I64, ROTL_I64_S }, |
| 10423 | { ROTR_I32, ROTR_I32_S }, |
| 10424 | { ROTR_I64, ROTR_I64_S }, |
| 10425 | { SELECT_EXNREF, SELECT_EXNREF_S }, |
| 10426 | { SELECT_EXTERNREF, SELECT_EXTERNREF_S }, |
| 10427 | { SELECT_F32, SELECT_F32_S }, |
| 10428 | { SELECT_F64, SELECT_F64_S }, |
| 10429 | { SELECT_FUNCREF, SELECT_FUNCREF_S }, |
| 10430 | { SELECT_I32, SELECT_I32_S }, |
| 10431 | { SELECT_I64, SELECT_I64_S }, |
| 10432 | { SELECT_T, SELECT_T_S }, |
| 10433 | { SELECT_V128, SELECT_V128_S }, |
| 10434 | { SHL_I16x8, SHL_I16x8_S }, |
| 10435 | { SHL_I32, SHL_I32_S }, |
| 10436 | { SHL_I32x4, SHL_I32x4_S }, |
| 10437 | { SHL_I64, SHL_I64_S }, |
| 10438 | { SHL_I64x2, SHL_I64x2_S }, |
| 10439 | { SHL_I8x16, SHL_I8x16_S }, |
| 10440 | { SHR_S_I16x8, SHR_S_I16x8_S }, |
| 10441 | { SHR_S_I32, SHR_S_I32_S }, |
| 10442 | { SHR_S_I32x4, SHR_S_I32x4_S }, |
| 10443 | { SHR_S_I64, SHR_S_I64_S }, |
| 10444 | { SHR_S_I64x2, SHR_S_I64x2_S }, |
| 10445 | { SHR_S_I8x16, SHR_S_I8x16_S }, |
| 10446 | { SHR_U_I16x8, SHR_U_I16x8_S }, |
| 10447 | { SHR_U_I32, SHR_U_I32_S }, |
| 10448 | { SHR_U_I32x4, SHR_U_I32x4_S }, |
| 10449 | { SHR_U_I64, SHR_U_I64_S }, |
| 10450 | { SHR_U_I64x2, SHR_U_I64x2_S }, |
| 10451 | { SHR_U_I8x16, SHR_U_I8x16_S }, |
| 10452 | { SHUFFLE, SHUFFLE_S }, |
| 10453 | { SIMD_RELAXED_FMAX_F32x4, SIMD_RELAXED_FMAX_F32x4_S }, |
| 10454 | { SIMD_RELAXED_FMAX_F64x2, SIMD_RELAXED_FMAX_F64x2_S }, |
| 10455 | { SIMD_RELAXED_FMIN_F32x4, SIMD_RELAXED_FMIN_F32x4_S }, |
| 10456 | { SIMD_RELAXED_FMIN_F64x2, SIMD_RELAXED_FMIN_F64x2_S }, |
| 10457 | { SPLAT_F16x8, SPLAT_F16x8_S }, |
| 10458 | { SPLAT_F32x4, SPLAT_F32x4_S }, |
| 10459 | { SPLAT_F64x2, SPLAT_F64x2_S }, |
| 10460 | { SPLAT_I16x8, SPLAT_I16x8_S }, |
| 10461 | { SPLAT_I32x4, SPLAT_I32x4_S }, |
| 10462 | { SPLAT_I64x2, SPLAT_I64x2_S }, |
| 10463 | { SPLAT_I8x16, SPLAT_I8x16_S }, |
| 10464 | { SQRT_F16x8, SQRT_F16x8_S }, |
| 10465 | { SQRT_F32, SQRT_F32_S }, |
| 10466 | { SQRT_F32x4, SQRT_F32x4_S }, |
| 10467 | { SQRT_F64, SQRT_F64_S }, |
| 10468 | { SQRT_F64x2, SQRT_F64x2_S }, |
| 10469 | { STORE16_I32_A32, STORE16_I32_A32_S }, |
| 10470 | { STORE16_I32_A64, STORE16_I32_A64_S }, |
| 10471 | { STORE16_I64_A32, STORE16_I64_A32_S }, |
| 10472 | { STORE16_I64_A64, STORE16_I64_A64_S }, |
| 10473 | { STORE32_I64_A32, STORE32_I64_A32_S }, |
| 10474 | { STORE32_I64_A64, STORE32_I64_A64_S }, |
| 10475 | { STORE8_I32_A32, STORE8_I32_A32_S }, |
| 10476 | { STORE8_I32_A64, STORE8_I32_A64_S }, |
| 10477 | { STORE8_I64_A32, STORE8_I64_A32_S }, |
| 10478 | { STORE8_I64_A64, STORE8_I64_A64_S }, |
| 10479 | { STORE_F16_F32_A32, STORE_F16_F32_A32_S }, |
| 10480 | { STORE_F16_F32_A64, STORE_F16_F32_A64_S }, |
| 10481 | { STORE_F32_A32, STORE_F32_A32_S }, |
| 10482 | { STORE_F32_A64, STORE_F32_A64_S }, |
| 10483 | { STORE_F64_A32, STORE_F64_A32_S }, |
| 10484 | { STORE_F64_A64, STORE_F64_A64_S }, |
| 10485 | { STORE_I32_A32, STORE_I32_A32_S }, |
| 10486 | { STORE_I32_A64, STORE_I32_A64_S }, |
| 10487 | { STORE_I64_A32, STORE_I64_A32_S }, |
| 10488 | { STORE_I64_A64, STORE_I64_A64_S }, |
| 10489 | { STORE_LANE_I16x8_A32, STORE_LANE_I16x8_A32_S }, |
| 10490 | { STORE_LANE_I16x8_A64, STORE_LANE_I16x8_A64_S }, |
| 10491 | { STORE_LANE_I32x4_A32, STORE_LANE_I32x4_A32_S }, |
| 10492 | { STORE_LANE_I32x4_A64, STORE_LANE_I32x4_A64_S }, |
| 10493 | { STORE_LANE_I64x2_A32, STORE_LANE_I64x2_A32_S }, |
| 10494 | { STORE_LANE_I64x2_A64, STORE_LANE_I64x2_A64_S }, |
| 10495 | { STORE_LANE_I8x16_A32, STORE_LANE_I8x16_A32_S }, |
| 10496 | { STORE_LANE_I8x16_A64, STORE_LANE_I8x16_A64_S }, |
| 10497 | { STORE_V128_A32, STORE_V128_A32_S }, |
| 10498 | { STORE_V128_A64, STORE_V128_A64_S }, |
| 10499 | { SUB_F16x8, SUB_F16x8_S }, |
| 10500 | { SUB_F32, SUB_F32_S }, |
| 10501 | { SUB_F32x4, SUB_F32x4_S }, |
| 10502 | { SUB_F64, SUB_F64_S }, |
| 10503 | { SUB_F64x2, SUB_F64x2_S }, |
| 10504 | { SUB_I16x8, SUB_I16x8_S }, |
| 10505 | { SUB_I32, SUB_I32_S }, |
| 10506 | { SUB_I32x4, SUB_I32x4_S }, |
| 10507 | { SUB_I64, SUB_I64_S }, |
| 10508 | { SUB_I64x2, SUB_I64x2_S }, |
| 10509 | { SUB_I8x16, SUB_I8x16_S }, |
| 10510 | { SUB_SAT_S_I16x8, SUB_SAT_S_I16x8_S }, |
| 10511 | { SUB_SAT_S_I8x16, SUB_SAT_S_I8x16_S }, |
| 10512 | { SUB_SAT_U_I16x8, SUB_SAT_U_I16x8_S }, |
| 10513 | { SUB_SAT_U_I8x16, SUB_SAT_U_I8x16_S }, |
| 10514 | { SWIZZLE, SWIZZLE_S }, |
| 10515 | { TABLE_COPY, TABLE_COPY_S }, |
| 10516 | { TABLE_FILL_EXNREF, TABLE_FILL_EXNREF_S }, |
| 10517 | { TABLE_FILL_EXTERNREF, TABLE_FILL_EXTERNREF_S }, |
| 10518 | { TABLE_FILL_FUNCREF, TABLE_FILL_FUNCREF_S }, |
| 10519 | { TABLE_GET_EXNREF, TABLE_GET_EXNREF_S }, |
| 10520 | { TABLE_GET_EXTERNREF, TABLE_GET_EXTERNREF_S }, |
| 10521 | { TABLE_GET_FUNCREF, TABLE_GET_FUNCREF_S }, |
| 10522 | { TABLE_GROW_EXNREF, TABLE_GROW_EXNREF_S }, |
| 10523 | { TABLE_GROW_EXTERNREF, TABLE_GROW_EXTERNREF_S }, |
| 10524 | { TABLE_GROW_FUNCREF, TABLE_GROW_FUNCREF_S }, |
| 10525 | { TABLE_SET_EXNREF, TABLE_SET_EXNREF_S }, |
| 10526 | { TABLE_SET_EXTERNREF, TABLE_SET_EXTERNREF_S }, |
| 10527 | { TABLE_SET_FUNCREF, TABLE_SET_FUNCREF_S }, |
| 10528 | { TABLE_SIZE, TABLE_SIZE_S }, |
| 10529 | { TEE_EXNREF, TEE_EXNREF_S }, |
| 10530 | { TEE_EXTERNREF, TEE_EXTERNREF_S }, |
| 10531 | { TEE_F32, TEE_F32_S }, |
| 10532 | { TEE_F64, TEE_F64_S }, |
| 10533 | { TEE_FUNCREF, TEE_FUNCREF_S }, |
| 10534 | { TEE_I32, TEE_I32_S }, |
| 10535 | { TEE_I64, TEE_I64_S }, |
| 10536 | { TEE_V128, TEE_V128_S }, |
| 10537 | { THROW, THROW_S }, |
| 10538 | { THROW_REF, THROW_REF_S }, |
| 10539 | { TRUNC_F16x8, TRUNC_F16x8_S }, |
| 10540 | { TRUNC_F32, TRUNC_F32_S }, |
| 10541 | { TRUNC_F32x4, TRUNC_F32x4_S }, |
| 10542 | { TRUNC_F64, TRUNC_F64_S }, |
| 10543 | { TRUNC_F64x2, TRUNC_F64x2_S }, |
| 10544 | { TRY, TRY_S }, |
| 10545 | { TRY_TABLE, TRY_TABLE_S }, |
| 10546 | { UNREACHABLE, UNREACHABLE_S }, |
| 10547 | { XOR, XOR_S }, |
| 10548 | { XOR_I32, XOR_I32_S }, |
| 10549 | { XOR_I64, XOR_I64_S }, |
| 10550 | { anonymous_14793MEMORY_GROW_A32, anonymous_14793MEMORY_GROW_A32_S }, |
| 10551 | { anonymous_14793MEMORY_SIZE_A32, anonymous_14793MEMORY_SIZE_A32_S }, |
| 10552 | { anonymous_14794MEMORY_GROW_A64, anonymous_14794MEMORY_GROW_A64_S }, |
| 10553 | { anonymous_14794MEMORY_SIZE_A64, anonymous_14794MEMORY_SIZE_A64_S }, |
| 10554 | { convert_low_s_F64x2, convert_low_s_F64x2_S }, |
| 10555 | { convert_low_u_F64x2, convert_low_u_F64x2_S }, |
| 10556 | { demote_zero_F16x8, demote_zero_F16x8_S }, |
| 10557 | { demote_zero_F32x4, demote_zero_F32x4_S }, |
| 10558 | { extadd_pairwise_s_I16x8, extadd_pairwise_s_I16x8_S }, |
| 10559 | { extadd_pairwise_s_I32x4, extadd_pairwise_s_I32x4_S }, |
| 10560 | { extadd_pairwise_u_I16x8, extadd_pairwise_u_I16x8_S }, |
| 10561 | { extadd_pairwise_u_I32x4, extadd_pairwise_u_I32x4_S }, |
| 10562 | { extend_high_s_I16x8, extend_high_s_I16x8_S }, |
| 10563 | { extend_high_s_I32x4, extend_high_s_I32x4_S }, |
| 10564 | { extend_high_s_I64x2, extend_high_s_I64x2_S }, |
| 10565 | { extend_high_u_I16x8, extend_high_u_I16x8_S }, |
| 10566 | { extend_high_u_I32x4, extend_high_u_I32x4_S }, |
| 10567 | { extend_high_u_I64x2, extend_high_u_I64x2_S }, |
| 10568 | { extend_low_s_I16x8, extend_low_s_I16x8_S }, |
| 10569 | { extend_low_s_I32x4, extend_low_s_I32x4_S }, |
| 10570 | { extend_low_s_I64x2, extend_low_s_I64x2_S }, |
| 10571 | { extend_low_u_I16x8, extend_low_u_I16x8_S }, |
| 10572 | { extend_low_u_I32x4, extend_low_u_I32x4_S }, |
| 10573 | { extend_low_u_I64x2, extend_low_u_I64x2_S }, |
| 10574 | { fp_to_sint_I16x8, fp_to_sint_I16x8_S }, |
| 10575 | { fp_to_sint_I32x4, fp_to_sint_I32x4_S }, |
| 10576 | { fp_to_uint_I16x8, fp_to_uint_I16x8_S }, |
| 10577 | { fp_to_uint_I32x4, fp_to_uint_I32x4_S }, |
| 10578 | { int_wasm_relaxed_trunc_signed_I32x4, int_wasm_relaxed_trunc_signed_I32x4_S }, |
| 10579 | { int_wasm_relaxed_trunc_signed_zero_I32x4, int_wasm_relaxed_trunc_signed_zero_I32x4_S }, |
| 10580 | { int_wasm_relaxed_trunc_unsigned_I32x4, int_wasm_relaxed_trunc_unsigned_I32x4_S }, |
| 10581 | { int_wasm_relaxed_trunc_unsigned_zero_I32x4, int_wasm_relaxed_trunc_unsigned_zero_I32x4_S }, |
| 10582 | { promote_low_F32x4, promote_low_F32x4_S }, |
| 10583 | { promote_low_F64x2, promote_low_F64x2_S }, |
| 10584 | { sint_to_fp_F16x8, sint_to_fp_F16x8_S }, |
| 10585 | { sint_to_fp_F32x4, sint_to_fp_F32x4_S }, |
| 10586 | { trunc_sat_zero_s_I32x4, trunc_sat_zero_s_I32x4_S }, |
| 10587 | { trunc_sat_zero_u_I32x4, trunc_sat_zero_u_I32x4_S }, |
| 10588 | { uint_to_fp_F16x8, uint_to_fp_F16x8_S }, |
| 10589 | { uint_to_fp_F32x4, uint_to_fp_F32x4_S }, |
| 10590 | }; // End of Table |
| 10591 | |
| 10592 | unsigned mid; |
| 10593 | unsigned start = 0; |
| 10594 | unsigned end = 823; |
| 10595 | while (start < end) { |
| 10596 | mid = start + (end - start) / 2; |
| 10597 | if (Opcode == Table[mid][0]) |
| 10598 | break; |
| 10599 | if (Opcode < Table[mid][0]) |
| 10600 | end = mid; |
| 10601 | else |
| 10602 | start = mid + 1; |
| 10603 | } |
| 10604 | if (start == end) |
| 10605 | return -1; // Instruction doesn't exist in this table. |
| 10606 | |
| 10607 | return Table[mid][1]; |
| 10608 | } |
| 10609 | |
| 10610 | // getWasm64Opcode |
| 10611 | LLVM_READONLY |
| 10612 | int32_t getWasm64Opcode(uint32_t Opcode) { |
| 10613 | using namespace WebAssembly; |
| 10614 | static constexpr uint32_t Table[][2] = { |
| 10615 | { ATOMIC_LOAD16_U_I32_A32, ATOMIC_LOAD16_U_I32_A64 }, |
| 10616 | { ATOMIC_LOAD16_U_I32_A32_S, ATOMIC_LOAD16_U_I32_A64_S }, |
| 10617 | { ATOMIC_LOAD16_U_I64_A32, ATOMIC_LOAD16_U_I64_A64 }, |
| 10618 | { ATOMIC_LOAD16_U_I64_A32_S, ATOMIC_LOAD16_U_I64_A64_S }, |
| 10619 | { ATOMIC_LOAD32_U_I64_A32, ATOMIC_LOAD32_U_I64_A64 }, |
| 10620 | { ATOMIC_LOAD32_U_I64_A32_S, ATOMIC_LOAD32_U_I64_A64_S }, |
| 10621 | { ATOMIC_LOAD8_U_I32_A32, ATOMIC_LOAD8_U_I32_A64 }, |
| 10622 | { ATOMIC_LOAD8_U_I32_A32_S, ATOMIC_LOAD8_U_I32_A64_S }, |
| 10623 | { ATOMIC_LOAD8_U_I64_A32, ATOMIC_LOAD8_U_I64_A64 }, |
| 10624 | { ATOMIC_LOAD8_U_I64_A32_S, ATOMIC_LOAD8_U_I64_A64_S }, |
| 10625 | { ATOMIC_LOAD_I32_A32, ATOMIC_LOAD_I32_A64 }, |
| 10626 | { ATOMIC_LOAD_I32_A32_S, ATOMIC_LOAD_I32_A64_S }, |
| 10627 | { ATOMIC_LOAD_I64_A32, ATOMIC_LOAD_I64_A64 }, |
| 10628 | { ATOMIC_LOAD_I64_A32_S, ATOMIC_LOAD_I64_A64_S }, |
| 10629 | { ATOMIC_RMW16_U_ADD_I32_A32, ATOMIC_RMW16_U_ADD_I32_A64 }, |
| 10630 | { ATOMIC_RMW16_U_ADD_I32_A32_S, ATOMIC_RMW16_U_ADD_I32_A64_S }, |
| 10631 | { ATOMIC_RMW16_U_ADD_I64_A32, ATOMIC_RMW16_U_ADD_I64_A64 }, |
| 10632 | { ATOMIC_RMW16_U_ADD_I64_A32_S, ATOMIC_RMW16_U_ADD_I64_A64_S }, |
| 10633 | { ATOMIC_RMW16_U_AND_I32_A32, ATOMIC_RMW16_U_AND_I32_A64 }, |
| 10634 | { ATOMIC_RMW16_U_AND_I32_A32_S, ATOMIC_RMW16_U_AND_I32_A64_S }, |
| 10635 | { ATOMIC_RMW16_U_AND_I64_A32, ATOMIC_RMW16_U_AND_I64_A64 }, |
| 10636 | { ATOMIC_RMW16_U_AND_I64_A32_S, ATOMIC_RMW16_U_AND_I64_A64_S }, |
| 10637 | { ATOMIC_RMW16_U_CMPXCHG_I32_A32, ATOMIC_RMW16_U_CMPXCHG_I32_A64 }, |
| 10638 | { ATOMIC_RMW16_U_CMPXCHG_I32_A32_S, ATOMIC_RMW16_U_CMPXCHG_I32_A64_S }, |
| 10639 | { ATOMIC_RMW16_U_CMPXCHG_I64_A32, ATOMIC_RMW16_U_CMPXCHG_I64_A64 }, |
| 10640 | { ATOMIC_RMW16_U_CMPXCHG_I64_A32_S, ATOMIC_RMW16_U_CMPXCHG_I64_A64_S }, |
| 10641 | { ATOMIC_RMW16_U_OR_I32_A32, ATOMIC_RMW16_U_OR_I32_A64 }, |
| 10642 | { ATOMIC_RMW16_U_OR_I32_A32_S, ATOMIC_RMW16_U_OR_I32_A64_S }, |
| 10643 | { ATOMIC_RMW16_U_OR_I64_A32, ATOMIC_RMW16_U_OR_I64_A64 }, |
| 10644 | { ATOMIC_RMW16_U_OR_I64_A32_S, ATOMIC_RMW16_U_OR_I64_A64_S }, |
| 10645 | { ATOMIC_RMW16_U_SUB_I32_A32, ATOMIC_RMW16_U_SUB_I32_A64 }, |
| 10646 | { ATOMIC_RMW16_U_SUB_I32_A32_S, ATOMIC_RMW16_U_SUB_I32_A64_S }, |
| 10647 | { ATOMIC_RMW16_U_SUB_I64_A32, ATOMIC_RMW16_U_SUB_I64_A64 }, |
| 10648 | { ATOMIC_RMW16_U_SUB_I64_A32_S, ATOMIC_RMW16_U_SUB_I64_A64_S }, |
| 10649 | { ATOMIC_RMW16_U_XCHG_I32_A32, ATOMIC_RMW16_U_XCHG_I32_A64 }, |
| 10650 | { ATOMIC_RMW16_U_XCHG_I32_A32_S, ATOMIC_RMW16_U_XCHG_I32_A64_S }, |
| 10651 | { ATOMIC_RMW16_U_XCHG_I64_A32, ATOMIC_RMW16_U_XCHG_I64_A64 }, |
| 10652 | { ATOMIC_RMW16_U_XCHG_I64_A32_S, ATOMIC_RMW16_U_XCHG_I64_A64_S }, |
| 10653 | { ATOMIC_RMW16_U_XOR_I32_A32, ATOMIC_RMW16_U_XOR_I32_A64 }, |
| 10654 | { ATOMIC_RMW16_U_XOR_I32_A32_S, ATOMIC_RMW16_U_XOR_I32_A64_S }, |
| 10655 | { ATOMIC_RMW16_U_XOR_I64_A32, ATOMIC_RMW16_U_XOR_I64_A64 }, |
| 10656 | { ATOMIC_RMW16_U_XOR_I64_A32_S, ATOMIC_RMW16_U_XOR_I64_A64_S }, |
| 10657 | { ATOMIC_RMW32_U_ADD_I64_A32, ATOMIC_RMW32_U_ADD_I64_A64 }, |
| 10658 | { ATOMIC_RMW32_U_ADD_I64_A32_S, ATOMIC_RMW32_U_ADD_I64_A64_S }, |
| 10659 | { ATOMIC_RMW32_U_AND_I64_A32, ATOMIC_RMW32_U_AND_I64_A64 }, |
| 10660 | { ATOMIC_RMW32_U_AND_I64_A32_S, ATOMIC_RMW32_U_AND_I64_A64_S }, |
| 10661 | { ATOMIC_RMW32_U_CMPXCHG_I64_A32, ATOMIC_RMW32_U_CMPXCHG_I64_A64 }, |
| 10662 | { ATOMIC_RMW32_U_CMPXCHG_I64_A32_S, ATOMIC_RMW32_U_CMPXCHG_I64_A64_S }, |
| 10663 | { ATOMIC_RMW32_U_OR_I64_A32, ATOMIC_RMW32_U_OR_I64_A64 }, |
| 10664 | { ATOMIC_RMW32_U_OR_I64_A32_S, ATOMIC_RMW32_U_OR_I64_A64_S }, |
| 10665 | { ATOMIC_RMW32_U_SUB_I64_A32, ATOMIC_RMW32_U_SUB_I64_A64 }, |
| 10666 | { ATOMIC_RMW32_U_SUB_I64_A32_S, ATOMIC_RMW32_U_SUB_I64_A64_S }, |
| 10667 | { ATOMIC_RMW32_U_XCHG_I64_A32, ATOMIC_RMW32_U_XCHG_I64_A64 }, |
| 10668 | { ATOMIC_RMW32_U_XCHG_I64_A32_S, ATOMIC_RMW32_U_XCHG_I64_A64_S }, |
| 10669 | { ATOMIC_RMW32_U_XOR_I64_A32, ATOMIC_RMW32_U_XOR_I64_A64 }, |
| 10670 | { ATOMIC_RMW32_U_XOR_I64_A32_S, ATOMIC_RMW32_U_XOR_I64_A64_S }, |
| 10671 | { ATOMIC_RMW8_U_ADD_I32_A32, ATOMIC_RMW8_U_ADD_I32_A64 }, |
| 10672 | { ATOMIC_RMW8_U_ADD_I32_A32_S, ATOMIC_RMW8_U_ADD_I32_A64_S }, |
| 10673 | { ATOMIC_RMW8_U_ADD_I64_A32, ATOMIC_RMW8_U_ADD_I64_A64 }, |
| 10674 | { ATOMIC_RMW8_U_ADD_I64_A32_S, ATOMIC_RMW8_U_ADD_I64_A64_S }, |
| 10675 | { ATOMIC_RMW8_U_AND_I32_A32, ATOMIC_RMW8_U_AND_I32_A64 }, |
| 10676 | { ATOMIC_RMW8_U_AND_I32_A32_S, ATOMIC_RMW8_U_AND_I32_A64_S }, |
| 10677 | { ATOMIC_RMW8_U_AND_I64_A32, ATOMIC_RMW8_U_AND_I64_A64 }, |
| 10678 | { ATOMIC_RMW8_U_AND_I64_A32_S, ATOMIC_RMW8_U_AND_I64_A64_S }, |
| 10679 | { ATOMIC_RMW8_U_CMPXCHG_I32_A32, ATOMIC_RMW8_U_CMPXCHG_I32_A64 }, |
| 10680 | { ATOMIC_RMW8_U_CMPXCHG_I32_A32_S, ATOMIC_RMW8_U_CMPXCHG_I32_A64_S }, |
| 10681 | { ATOMIC_RMW8_U_CMPXCHG_I64_A32, ATOMIC_RMW8_U_CMPXCHG_I64_A64 }, |
| 10682 | { ATOMIC_RMW8_U_CMPXCHG_I64_A32_S, ATOMIC_RMW8_U_CMPXCHG_I64_A64_S }, |
| 10683 | { ATOMIC_RMW8_U_OR_I32_A32, ATOMIC_RMW8_U_OR_I32_A64 }, |
| 10684 | { ATOMIC_RMW8_U_OR_I32_A32_S, ATOMIC_RMW8_U_OR_I32_A64_S }, |
| 10685 | { ATOMIC_RMW8_U_OR_I64_A32, ATOMIC_RMW8_U_OR_I64_A64 }, |
| 10686 | { ATOMIC_RMW8_U_OR_I64_A32_S, ATOMIC_RMW8_U_OR_I64_A64_S }, |
| 10687 | { ATOMIC_RMW8_U_SUB_I32_A32, ATOMIC_RMW8_U_SUB_I32_A64 }, |
| 10688 | { ATOMIC_RMW8_U_SUB_I32_A32_S, ATOMIC_RMW8_U_SUB_I32_A64_S }, |
| 10689 | { ATOMIC_RMW8_U_SUB_I64_A32, ATOMIC_RMW8_U_SUB_I64_A64 }, |
| 10690 | { ATOMIC_RMW8_U_SUB_I64_A32_S, ATOMIC_RMW8_U_SUB_I64_A64_S }, |
| 10691 | { ATOMIC_RMW8_U_XCHG_I32_A32, ATOMIC_RMW8_U_XCHG_I32_A64 }, |
| 10692 | { ATOMIC_RMW8_U_XCHG_I32_A32_S, ATOMIC_RMW8_U_XCHG_I32_A64_S }, |
| 10693 | { ATOMIC_RMW8_U_XCHG_I64_A32, ATOMIC_RMW8_U_XCHG_I64_A64 }, |
| 10694 | { ATOMIC_RMW8_U_XCHG_I64_A32_S, ATOMIC_RMW8_U_XCHG_I64_A64_S }, |
| 10695 | { ATOMIC_RMW8_U_XOR_I32_A32, ATOMIC_RMW8_U_XOR_I32_A64 }, |
| 10696 | { ATOMIC_RMW8_U_XOR_I32_A32_S, ATOMIC_RMW8_U_XOR_I32_A64_S }, |
| 10697 | { ATOMIC_RMW8_U_XOR_I64_A32, ATOMIC_RMW8_U_XOR_I64_A64 }, |
| 10698 | { ATOMIC_RMW8_U_XOR_I64_A32_S, ATOMIC_RMW8_U_XOR_I64_A64_S }, |
| 10699 | { ATOMIC_RMW_ADD_I32_A32, ATOMIC_RMW_ADD_I32_A64 }, |
| 10700 | { ATOMIC_RMW_ADD_I32_A32_S, ATOMIC_RMW_ADD_I32_A64_S }, |
| 10701 | { ATOMIC_RMW_ADD_I64_A32, ATOMIC_RMW_ADD_I64_A64 }, |
| 10702 | { ATOMIC_RMW_ADD_I64_A32_S, ATOMIC_RMW_ADD_I64_A64_S }, |
| 10703 | { ATOMIC_RMW_AND_I32_A32, ATOMIC_RMW_AND_I32_A64 }, |
| 10704 | { ATOMIC_RMW_AND_I32_A32_S, ATOMIC_RMW_AND_I32_A64_S }, |
| 10705 | { ATOMIC_RMW_AND_I64_A32, ATOMIC_RMW_AND_I64_A64 }, |
| 10706 | { ATOMIC_RMW_AND_I64_A32_S, ATOMIC_RMW_AND_I64_A64_S }, |
| 10707 | { ATOMIC_RMW_CMPXCHG_I32_A32, ATOMIC_RMW_CMPXCHG_I32_A64 }, |
| 10708 | { ATOMIC_RMW_CMPXCHG_I32_A32_S, ATOMIC_RMW_CMPXCHG_I32_A64_S }, |
| 10709 | { ATOMIC_RMW_CMPXCHG_I64_A32, ATOMIC_RMW_CMPXCHG_I64_A64 }, |
| 10710 | { ATOMIC_RMW_CMPXCHG_I64_A32_S, ATOMIC_RMW_CMPXCHG_I64_A64_S }, |
| 10711 | { ATOMIC_RMW_OR_I32_A32, ATOMIC_RMW_OR_I32_A64 }, |
| 10712 | { ATOMIC_RMW_OR_I32_A32_S, ATOMIC_RMW_OR_I32_A64_S }, |
| 10713 | { ATOMIC_RMW_OR_I64_A32, ATOMIC_RMW_OR_I64_A64 }, |
| 10714 | { ATOMIC_RMW_OR_I64_A32_S, ATOMIC_RMW_OR_I64_A64_S }, |
| 10715 | { ATOMIC_RMW_SUB_I32_A32, ATOMIC_RMW_SUB_I32_A64 }, |
| 10716 | { ATOMIC_RMW_SUB_I32_A32_S, ATOMIC_RMW_SUB_I32_A64_S }, |
| 10717 | { ATOMIC_RMW_SUB_I64_A32, ATOMIC_RMW_SUB_I64_A64 }, |
| 10718 | { ATOMIC_RMW_SUB_I64_A32_S, ATOMIC_RMW_SUB_I64_A64_S }, |
| 10719 | { ATOMIC_RMW_XCHG_I32_A32, ATOMIC_RMW_XCHG_I32_A64 }, |
| 10720 | { ATOMIC_RMW_XCHG_I32_A32_S, ATOMIC_RMW_XCHG_I32_A64_S }, |
| 10721 | { ATOMIC_RMW_XCHG_I64_A32, ATOMIC_RMW_XCHG_I64_A64 }, |
| 10722 | { ATOMIC_RMW_XCHG_I64_A32_S, ATOMIC_RMW_XCHG_I64_A64_S }, |
| 10723 | { ATOMIC_RMW_XOR_I32_A32, ATOMIC_RMW_XOR_I32_A64 }, |
| 10724 | { ATOMIC_RMW_XOR_I32_A32_S, ATOMIC_RMW_XOR_I32_A64_S }, |
| 10725 | { ATOMIC_RMW_XOR_I64_A32, ATOMIC_RMW_XOR_I64_A64 }, |
| 10726 | { ATOMIC_RMW_XOR_I64_A32_S, ATOMIC_RMW_XOR_I64_A64_S }, |
| 10727 | { ATOMIC_STORE16_I32_A32, ATOMIC_STORE16_I32_A64 }, |
| 10728 | { ATOMIC_STORE16_I32_A32_S, ATOMIC_STORE16_I32_A64_S }, |
| 10729 | { ATOMIC_STORE16_I64_A32, ATOMIC_STORE16_I64_A64 }, |
| 10730 | { ATOMIC_STORE16_I64_A32_S, ATOMIC_STORE16_I64_A64_S }, |
| 10731 | { ATOMIC_STORE32_I64_A32, ATOMIC_STORE32_I64_A64 }, |
| 10732 | { ATOMIC_STORE32_I64_A32_S, ATOMIC_STORE32_I64_A64_S }, |
| 10733 | { ATOMIC_STORE8_I32_A32, ATOMIC_STORE8_I32_A64 }, |
| 10734 | { ATOMIC_STORE8_I32_A32_S, ATOMIC_STORE8_I32_A64_S }, |
| 10735 | { ATOMIC_STORE8_I64_A32, ATOMIC_STORE8_I64_A64 }, |
| 10736 | { ATOMIC_STORE8_I64_A32_S, ATOMIC_STORE8_I64_A64_S }, |
| 10737 | { ATOMIC_STORE_I32_A32, ATOMIC_STORE_I32_A64 }, |
| 10738 | { ATOMIC_STORE_I32_A32_S, ATOMIC_STORE_I32_A64_S }, |
| 10739 | { ATOMIC_STORE_I64_A32, ATOMIC_STORE_I64_A64 }, |
| 10740 | { ATOMIC_STORE_I64_A32_S, ATOMIC_STORE_I64_A64_S }, |
| 10741 | { LOAD16_S_I32_A32, LOAD16_S_I32_A64 }, |
| 10742 | { LOAD16_S_I32_A32_S, LOAD16_S_I32_A64_S }, |
| 10743 | { LOAD16_S_I64_A32, LOAD16_S_I64_A64 }, |
| 10744 | { LOAD16_S_I64_A32_S, LOAD16_S_I64_A64_S }, |
| 10745 | { LOAD16_U_I32_A32, LOAD16_U_I32_A64 }, |
| 10746 | { LOAD16_U_I32_A32_S, LOAD16_U_I32_A64_S }, |
| 10747 | { LOAD16_U_I64_A32, LOAD16_U_I64_A64 }, |
| 10748 | { LOAD16_U_I64_A32_S, LOAD16_U_I64_A64_S }, |
| 10749 | { LOAD32_S_I64_A32, LOAD32_S_I64_A64 }, |
| 10750 | { LOAD32_S_I64_A32_S, LOAD32_S_I64_A64_S }, |
| 10751 | { LOAD32_U_I64_A32, LOAD32_U_I64_A64 }, |
| 10752 | { LOAD32_U_I64_A32_S, LOAD32_U_I64_A64_S }, |
| 10753 | { LOAD8_S_I32_A32, LOAD8_S_I32_A64 }, |
| 10754 | { LOAD8_S_I32_A32_S, LOAD8_S_I32_A64_S }, |
| 10755 | { LOAD8_S_I64_A32, LOAD8_S_I64_A64 }, |
| 10756 | { LOAD8_S_I64_A32_S, LOAD8_S_I64_A64_S }, |
| 10757 | { LOAD8_U_I32_A32, LOAD8_U_I32_A64 }, |
| 10758 | { LOAD8_U_I32_A32_S, LOAD8_U_I32_A64_S }, |
| 10759 | { LOAD8_U_I64_A32, LOAD8_U_I64_A64 }, |
| 10760 | { LOAD8_U_I64_A32_S, LOAD8_U_I64_A64_S }, |
| 10761 | { LOAD_F16_F32_A32, LOAD_F16_F32_A64 }, |
| 10762 | { LOAD_F16_F32_A32_S, LOAD_F16_F32_A64_S }, |
| 10763 | { LOAD_F32_A32, LOAD_F32_A64 }, |
| 10764 | { LOAD_F32_A32_S, LOAD_F32_A64_S }, |
| 10765 | { LOAD_F64_A32, LOAD_F64_A64 }, |
| 10766 | { LOAD_F64_A32_S, LOAD_F64_A64_S }, |
| 10767 | { LOAD_I32_A32, LOAD_I32_A64 }, |
| 10768 | { LOAD_I32_A32_S, LOAD_I32_A64_S }, |
| 10769 | { LOAD_I64_A32, LOAD_I64_A64 }, |
| 10770 | { LOAD_I64_A32_S, LOAD_I64_A64_S }, |
| 10771 | { MEMORY_ATOMIC_NOTIFY_A32, MEMORY_ATOMIC_NOTIFY_A64 }, |
| 10772 | { MEMORY_ATOMIC_NOTIFY_A32_S, MEMORY_ATOMIC_NOTIFY_A64_S }, |
| 10773 | { MEMORY_ATOMIC_WAIT32_A32, MEMORY_ATOMIC_WAIT32_A64 }, |
| 10774 | { MEMORY_ATOMIC_WAIT32_A32_S, MEMORY_ATOMIC_WAIT32_A64_S }, |
| 10775 | { MEMORY_ATOMIC_WAIT64_A32, MEMORY_ATOMIC_WAIT64_A64 }, |
| 10776 | { MEMORY_ATOMIC_WAIT64_A32_S, MEMORY_ATOMIC_WAIT64_A64_S }, |
| 10777 | { STORE16_I32_A32, STORE16_I32_A64 }, |
| 10778 | { STORE16_I32_A32_S, STORE16_I32_A64_S }, |
| 10779 | { STORE16_I64_A32, STORE16_I64_A64 }, |
| 10780 | { STORE16_I64_A32_S, STORE16_I64_A64_S }, |
| 10781 | { STORE32_I64_A32, STORE32_I64_A64 }, |
| 10782 | { STORE32_I64_A32_S, STORE32_I64_A64_S }, |
| 10783 | { STORE8_I32_A32, STORE8_I32_A64 }, |
| 10784 | { STORE8_I32_A32_S, STORE8_I32_A64_S }, |
| 10785 | { STORE8_I64_A32, STORE8_I64_A64 }, |
| 10786 | { STORE8_I64_A32_S, STORE8_I64_A64_S }, |
| 10787 | { STORE_F16_F32_A32, STORE_F16_F32_A64 }, |
| 10788 | { STORE_F16_F32_A32_S, STORE_F16_F32_A64_S }, |
| 10789 | { STORE_F32_A32, STORE_F32_A64 }, |
| 10790 | { STORE_F32_A32_S, STORE_F32_A64_S }, |
| 10791 | { STORE_F64_A32, STORE_F64_A64 }, |
| 10792 | { STORE_F64_A32_S, STORE_F64_A64_S }, |
| 10793 | { STORE_I32_A32, STORE_I32_A64 }, |
| 10794 | { STORE_I32_A32_S, STORE_I32_A64_S }, |
| 10795 | { STORE_I64_A32, STORE_I64_A64 }, |
| 10796 | { STORE_I64_A32_S, STORE_I64_A64_S }, |
| 10797 | }; // End of Table |
| 10798 | |
| 10799 | unsigned mid; |
| 10800 | unsigned start = 0; |
| 10801 | unsigned end = 182; |
| 10802 | while (start < end) { |
| 10803 | mid = start + (end - start) / 2; |
| 10804 | if (Opcode == Table[mid][0]) |
| 10805 | break; |
| 10806 | if (Opcode < Table[mid][0]) |
| 10807 | end = mid; |
| 10808 | else |
| 10809 | start = mid + 1; |
| 10810 | } |
| 10811 | if (start == end) |
| 10812 | return -1; // Instruction doesn't exist in this table. |
| 10813 | |
| 10814 | return Table[mid][1]; |
| 10815 | } |
| 10816 | |
| 10817 | |
| 10818 | } // namespace llvm::WebAssembly |
| 10819 | |
| 10820 | #endif // GET_INSTRMAP_INFO |
| 10821 | |
| 10822 |
Generated while processing llvm_projects/llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
Generated on 2026-Sep-19 from project llvm_projects revision 8c8740bd9
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