1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11
12namespace llvm::WebAssembly {
13
14 enum {
15 PHI = 0, // Target.td:1200
16 INLINEASM = 1, // Target.td:1206
17 INLINEASM_BR = 2, // Target.td:1212
18 CFI_INSTRUCTION = 3, // Target.td:1221
19 EH_LABEL = 4, // Target.td:1230
20 GC_LABEL = 5, // Target.td:1239
21 ANNOTATION_LABEL = 6, // Target.td:1248
22 KILL = 7, // Target.td:1256
23 EXTRACT_SUBREG = 8, // Target.td:1263
24 INSERT_SUBREG = 9, // Target.td:1269
25 IMPLICIT_DEF = 10, // Target.td:1276
26 INIT_UNDEF = 11, // Target.td:1285
27 SUBREG_TO_REG = 12, // Target.td:1292
28 COPY_TO_REGCLASS = 13, // Target.td:1298
29 DBG_VALUE = 14, // Target.td:1305
30 DBG_VALUE_LIST = 15, // Target.td:1312
31 DBG_INSTR_REF = 16, // Target.td:1319
32 DBG_PHI = 17, // Target.td:1326
33 DBG_LABEL = 18, // Target.td:1333
34 REG_SEQUENCE = 19, // Target.td:1340
35 COPY = 20, // Target.td:1347
36 COPY_LANEMASK = 21, // Target.td:1355
37 BUNDLE = 22, // Target.td:1362
38 LIFETIME_START = 23, // Target.td:1368
39 LIFETIME_END = 24, // Target.td:1375
40 PSEUDO_PROBE = 25, // Target.td:1382
41 ARITH_FENCE = 26, // Target.td:1389
42 STACKMAP = 27, // Target.td:1398
43 FENTRY_CALL = 28, // Target.td:1533
44 PATCHPOINT = 29, // Target.td:1406
45 LOAD_STACK_GUARD = 30, // Target.td:1424
46 PREALLOCATED_SETUP = 31, // Target.td:1432
47 PREALLOCATED_ARG = 32, // Target.td:1438
48 STATEPOINT = 33, // Target.td:1415
49 LOCAL_ESCAPE = 34, // Target.td:1444
50 FAULTING_OP = 35, // Target.td:1453
51 PATCHABLE_OP = 36, // Target.td:1473
52 PATCHABLE_FUNCTION_ENTER = 37, // Target.td:1481
53 PATCHABLE_RET = 38, // Target.td:1488
54 PATCHABLE_FUNCTION_EXIT = 39, // Target.td:1497
55 PATCHABLE_TAIL_CALL = 40, // Target.td:1505
56 PATCHABLE_EVENT_CALL = 41, // Target.td:1513
57 PATCHABLE_TYPED_EVENT_CALL = 42, // Target.td:1523
58 ICALL_BRANCH_FUNNEL = 43, // Target.td:1543
59 FAKE_USE = 44, // Target.td:1463
60 MEMBARRIER = 45, // Target.td:1549
61 JUMP_TABLE_DEBUG_INFO = 46, // Target.td:1557
62 RELOC_NONE = 47, // Target.td:1565
63 CONVERGENCECTRL_ENTRY = 48, // Target.td:1576
64 CONVERGENCECTRL_ANCHOR = 49, // Target.td:1572
65 CONVERGENCECTRL_LOOP = 50, // Target.td:1580
66 CONVERGENCECTRL_GLUE = 51, // Target.td:1584
67 G_ASSERT_SEXT = 52, // GenericOpcodes.td:1865
68 G_ASSERT_ZEXT = 53, // GenericOpcodes.td:1857
69 G_ASSERT_ALIGN = 54, // GenericOpcodes.td:1872
70 G_ADD = 55, // GenericOpcodes.td:300
71 G_SUB = 56, // GenericOpcodes.td:308
72 G_MUL = 57, // GenericOpcodes.td:316
73 G_SDIV = 58, // GenericOpcodes.td:324
74 G_UDIV = 59, // GenericOpcodes.td:332
75 G_SREM = 60, // GenericOpcodes.td:340
76 G_UREM = 61, // GenericOpcodes.td:348
77 G_SDIVREM = 62, // GenericOpcodes.td:356
78 G_UDIVREM = 63, // GenericOpcodes.td:364
79 G_AND = 64, // GenericOpcodes.td:372
80 G_OR = 65, // GenericOpcodes.td:380
81 G_XOR = 66, // GenericOpcodes.td:388
82 G_ABDS = 67, // GenericOpcodes.td:417
83 G_ABDU = 68, // GenericOpcodes.td:425
84 G_UAVGFLOOR = 69, // GenericOpcodes.td:433
85 G_UAVGCEIL = 70, // GenericOpcodes.td:440
86 G_SAVGFLOOR = 71, // GenericOpcodes.td:447
87 G_SAVGCEIL = 72, // GenericOpcodes.td:454
88 G_IMPLICIT_DEF = 73, // GenericOpcodes.td:110
89 G_PHI = 74, // GenericOpcodes.td:116
90 G_FRAME_INDEX = 75, // GenericOpcodes.td:122
91 G_GLOBAL_VALUE = 76, // GenericOpcodes.td:128
92 G_PTRAUTH_GLOBAL_VALUE = 77, // GenericOpcodes.td:134
93 G_CONSTANT_POOL = 78, // GenericOpcodes.td:140
94 G_EXTRACT = 79, // GenericOpcodes.td:1472
95 G_UNMERGE_VALUES = 80, // GenericOpcodes.td:1484
96 G_INSERT = 81, // GenericOpcodes.td:1492
97 G_MERGE_VALUES = 82, // GenericOpcodes.td:1502
98 G_BUILD_VECTOR = 83, // GenericOpcodes.td:1521
99 G_BUILD_VECTOR_TRUNC = 84, // GenericOpcodes.td:1530
100 G_CONCAT_VECTORS = 85, // GenericOpcodes.td:1537
101 G_PTRTOINT = 86, // GenericOpcodes.td:152
102 G_INTTOPTR = 87, // GenericOpcodes.td:146
103 G_BITCAST = 88, // GenericOpcodes.td:158
104 G_FREEZE = 89, // GenericOpcodes.td:277
105 G_CONSTANT_FOLD_BARRIER = 90, // GenericOpcodes.td:1879
106 G_INTRINSIC_FPTRUNC_ROUND = 91, // GenericOpcodes.td:1263
107 G_INTRINSIC_TRUNC = 92, // GenericOpcodes.td:1269
108 G_INTRINSIC_ROUND = 93, // GenericOpcodes.td:1275
109 G_INTRINSIC_LRINT = 94, // GenericOpcodes.td:1281
110 G_INTRINSIC_LLRINT = 95, // GenericOpcodes.td:1287
111 G_INTRINSIC_ROUNDEVEN = 96, // GenericOpcodes.td:1293
112 G_READCYCLECOUNTER = 97, // GenericOpcodes.td:1299
113 G_READSTEADYCOUNTER = 98, // GenericOpcodes.td:1305
114 G_LOAD = 99, // GenericOpcodes.td:1332
115 G_SEXTLOAD = 100, // GenericOpcodes.td:1340
116 G_ZEXTLOAD = 101, // GenericOpcodes.td:1348
117 G_INDEXED_LOAD = 102, // GenericOpcodes.td:1358
118 G_INDEXED_SEXTLOAD = 103, // GenericOpcodes.td:1366
119 G_INDEXED_ZEXTLOAD = 104, // GenericOpcodes.td:1374
120 G_STORE = 105, // GenericOpcodes.td:1382
121 G_INDEXED_STORE = 106, // GenericOpcodes.td:1390
122 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 107, // GenericOpcodes.td:1400
123 G_ATOMIC_CMPXCHG = 108, // GenericOpcodes.td:1410
124 G_ATOMICRMW_XCHG = 109, // GenericOpcodes.td:1428
125 G_ATOMICRMW_ADD = 110, // GenericOpcodes.td:1429
126 G_ATOMICRMW_SUB = 111, // GenericOpcodes.td:1430
127 G_ATOMICRMW_AND = 112, // GenericOpcodes.td:1431
128 G_ATOMICRMW_NAND = 113, // GenericOpcodes.td:1432
129 G_ATOMICRMW_OR = 114, // GenericOpcodes.td:1433
130 G_ATOMICRMW_XOR = 115, // GenericOpcodes.td:1434
131 G_ATOMICRMW_MAX = 116, // GenericOpcodes.td:1435
132 G_ATOMICRMW_MIN = 117, // GenericOpcodes.td:1436
133 G_ATOMICRMW_UMAX = 118, // GenericOpcodes.td:1437
134 G_ATOMICRMW_UMIN = 119, // GenericOpcodes.td:1438
135 G_ATOMICRMW_FADD = 120, // GenericOpcodes.td:1439
136 G_ATOMICRMW_FSUB = 121, // GenericOpcodes.td:1440
137 G_ATOMICRMW_FMAX = 122, // GenericOpcodes.td:1441
138 G_ATOMICRMW_FMIN = 123, // GenericOpcodes.td:1442
139 G_ATOMICRMW_FMAXIMUM = 124, // GenericOpcodes.td:1443
140 G_ATOMICRMW_FMINIMUM = 125, // GenericOpcodes.td:1444
141 G_ATOMICRMW_UINC_WRAP = 126, // GenericOpcodes.td:1445
142 G_ATOMICRMW_UDEC_WRAP = 127, // GenericOpcodes.td:1446
143 G_ATOMICRMW_USUB_COND = 128, // GenericOpcodes.td:1447
144 G_ATOMICRMW_USUB_SAT = 129, // GenericOpcodes.td:1448
145 G_FENCE = 130, // GenericOpcodes.td:1450
146 G_PREFETCH = 131, // GenericOpcodes.td:1457
147 G_BRCOND = 132, // GenericOpcodes.td:1592
148 G_BRINDIRECT = 133, // GenericOpcodes.td:1601
149 G_INVOKE_REGION_START = 134, // GenericOpcodes.td:1624
150 G_INTRINSIC = 135, // GenericOpcodes.td:1544
151 G_INTRINSIC_W_SIDE_EFFECTS = 136, // GenericOpcodes.td:1551
152 G_INTRINSIC_CONVERGENT = 137, // GenericOpcodes.td:1560
153 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 138, // GenericOpcodes.td:1568
154 G_ANYEXT = 139, // GenericOpcodes.td:44
155 G_TRUNC = 140, // GenericOpcodes.td:83
156 G_TRUNC_SSAT_S = 141, // GenericOpcodes.td:90
157 G_TRUNC_SSAT_U = 142, // GenericOpcodes.td:97
158 G_TRUNC_USAT_U = 143, // GenericOpcodes.td:104
159 G_CONSTANT = 144, // GenericOpcodes.td:165
160 G_FCONSTANT = 145, // GenericOpcodes.td:172
161 G_VASTART = 146, // GenericOpcodes.td:178
162 G_VAARG = 147, // GenericOpcodes.td:185
163 G_SEXT = 148, // GenericOpcodes.td:52
164 G_SEXT_INREG = 149, // GenericOpcodes.td:66
165 G_ZEXT = 150, // GenericOpcodes.td:74
166 G_SHL = 151, // GenericOpcodes.td:396
167 G_LSHR = 152, // GenericOpcodes.td:403
168 G_ASHR = 153, // GenericOpcodes.td:410
169 G_FSHL = 154, // GenericOpcodes.td:462
170 G_FSHR = 155, // GenericOpcodes.td:470
171 G_ROTR = 156, // GenericOpcodes.td:477
172 G_ROTL = 157, // GenericOpcodes.td:484
173 G_ICMP = 158, // GenericOpcodes.td:491
174 G_FCMP = 159, // GenericOpcodes.td:498
175 G_SCMP = 160, // GenericOpcodes.td:505
176 G_UCMP = 161, // GenericOpcodes.td:512
177 G_SELECT = 162, // GenericOpcodes.td:519
178 G_UADDO = 163, // GenericOpcodes.td:584
179 G_UADDE = 164, // GenericOpcodes.td:592
180 G_USUBO = 165, // GenericOpcodes.td:614
181 G_USUBE = 166, // GenericOpcodes.td:620
182 G_SADDO = 167, // GenericOpcodes.td:599
183 G_SADDE = 168, // GenericOpcodes.td:607
184 G_SSUBO = 169, // GenericOpcodes.td:627
185 G_SSUBE = 170, // GenericOpcodes.td:634
186 G_UMULO = 171, // GenericOpcodes.td:641
187 G_SMULO = 172, // GenericOpcodes.td:649
188 G_UMULH = 173, // GenericOpcodes.td:658
189 G_SMULH = 174, // GenericOpcodes.td:667
190 G_UADDSAT = 175, // GenericOpcodes.td:679
191 G_SADDSAT = 176, // GenericOpcodes.td:687
192 G_USUBSAT = 177, // GenericOpcodes.td:695
193 G_SSUBSAT = 178, // GenericOpcodes.td:703
194 G_USHLSAT = 179, // GenericOpcodes.td:711
195 G_SSHLSAT = 180, // GenericOpcodes.td:719
196 G_SMULFIX = 181, // GenericOpcodes.td:731
197 G_UMULFIX = 182, // GenericOpcodes.td:738
198 G_SMULFIXSAT = 183, // GenericOpcodes.td:748
199 G_UMULFIXSAT = 184, // GenericOpcodes.td:755
200 G_SDIVFIX = 185, // GenericOpcodes.td:766
201 G_UDIVFIX = 186, // GenericOpcodes.td:773
202 G_SDIVFIXSAT = 187, // GenericOpcodes.td:783
203 G_UDIVFIXSAT = 188, // GenericOpcodes.td:790
204 G_FADD = 189, // GenericOpcodes.td:963
205 G_FSUB = 190, // GenericOpcodes.td:971
206 G_FMUL = 191, // GenericOpcodes.td:979
207 G_FMA = 192, // GenericOpcodes.td:988
208 G_FMAD = 193, // GenericOpcodes.td:997
209 G_FDIV = 194, // GenericOpcodes.td:1005
210 G_FREM = 195, // GenericOpcodes.td:1012
211 G_FMODF = 196, // GenericOpcodes.td:1019
212 G_FPOW = 197, // GenericOpcodes.td:1026
213 G_FPOWI = 198, // GenericOpcodes.td:1033
214 G_FEXP = 199, // GenericOpcodes.td:1040
215 G_FEXP2 = 200, // GenericOpcodes.td:1047
216 G_FEXP10 = 201, // GenericOpcodes.td:1054
217 G_FLOG = 202, // GenericOpcodes.td:1061
218 G_FLOG2 = 203, // GenericOpcodes.td:1068
219 G_FLOG10 = 204, // GenericOpcodes.td:1075
220 G_FLDEXP = 205, // GenericOpcodes.td:1082
221 G_FFREXP = 206, // GenericOpcodes.td:1089
222 G_FNEG = 207, // GenericOpcodes.td:801
223 G_FPEXT = 208, // GenericOpcodes.td:807
224 G_FPTRUNC = 209, // GenericOpcodes.td:813
225 G_FPTOSI = 210, // GenericOpcodes.td:819
226 G_FPTOUI = 211, // GenericOpcodes.td:825
227 G_SITOFP = 212, // GenericOpcodes.td:831
228 G_UITOFP = 213, // GenericOpcodes.td:837
229 G_FPTOSI_SAT = 214, // GenericOpcodes.td:843
230 G_FPTOUI_SAT = 215, // GenericOpcodes.td:849
231 G_FABS = 216, // GenericOpcodes.td:855
232 G_FCOPYSIGN = 217, // GenericOpcodes.td:861
233 G_IS_FPCLASS = 218, // GenericOpcodes.td:874
234 G_FCANONICALIZE = 219, // GenericOpcodes.td:867
235 G_FMINNUM = 220, // GenericOpcodes.td:887
236 G_FMAXNUM = 221, // GenericOpcodes.td:894
237 G_FMINNUM_IEEE = 222, // GenericOpcodes.td:912
238 G_FMAXNUM_IEEE = 223, // GenericOpcodes.td:919
239 G_FMINIMUM = 224, // GenericOpcodes.td:929
240 G_FMAXIMUM = 225, // GenericOpcodes.td:936
241 G_FMINIMUMNUM = 226, // GenericOpcodes.td:944
242 G_FMAXIMUMNUM = 227, // GenericOpcodes.td:951
243 G_GET_FPENV = 228, // GenericOpcodes.td:1219
244 G_SET_FPENV = 229, // GenericOpcodes.td:1226
245 G_RESET_FPENV = 230, // GenericOpcodes.td:1233
246 G_GET_FPMODE = 231, // GenericOpcodes.td:1240
247 G_SET_FPMODE = 232, // GenericOpcodes.td:1247
248 G_RESET_FPMODE = 233, // GenericOpcodes.td:1254
249 G_GET_ROUNDING = 234, // GenericOpcodes.td:1311
250 G_SET_ROUNDING = 235, // GenericOpcodes.td:1317
251 G_PTR_ADD = 236, // GenericOpcodes.td:526
252 G_PTRMASK = 237, // GenericOpcodes.td:534
253 G_SMIN = 238, // GenericOpcodes.td:541
254 G_SMAX = 239, // GenericOpcodes.td:549
255 G_UMIN = 240, // GenericOpcodes.td:557
256 G_UMAX = 241, // GenericOpcodes.td:565
257 G_ABS = 242, // GenericOpcodes.td:573
258 G_LROUND = 243, // GenericOpcodes.td:283
259 G_LLROUND = 244, // GenericOpcodes.td:289
260 G_BR = 245, // GenericOpcodes.td:1582
261 G_BRJT = 246, // GenericOpcodes.td:1612
262 G_VSCALE = 247, // GenericOpcodes.td:1512
263 G_INSERT_SUBVECTOR = 248, // GenericOpcodes.td:1656
264 G_EXTRACT_SUBVECTOR = 249, // GenericOpcodes.td:1663
265 G_INSERT_VECTOR_ELT = 250, // GenericOpcodes.td:1670
266 G_EXTRACT_VECTOR_ELT = 251, // GenericOpcodes.td:1677
267 G_SHUFFLE_VECTOR = 252, // GenericOpcodes.td:1687
268 G_SPLAT_VECTOR = 253, // GenericOpcodes.td:1694
269 G_STEP_VECTOR = 254, // GenericOpcodes.td:1701
270 G_VECTOR_COMPRESS = 255, // GenericOpcodes.td:1708
271 G_CTTZ = 256, // GenericOpcodes.td:205
272 G_CTTZ_ZERO_UNDEF = 257, // GenericOpcodes.td:211
273 G_CTLZ = 258, // GenericOpcodes.td:193
274 G_CTLZ_ZERO_UNDEF = 259, // GenericOpcodes.td:199
275 G_CTLS = 260, // GenericOpcodes.td:217
276 G_CTPOP = 261, // GenericOpcodes.td:223
277 G_BSWAP = 262, // GenericOpcodes.td:229
278 G_BITREVERSE = 263, // GenericOpcodes.td:235
279 G_FCEIL = 264, // GenericOpcodes.td:1096
280 G_FCOS = 265, // GenericOpcodes.td:1103
281 G_FSIN = 266, // GenericOpcodes.td:1110
282 G_FSINCOS = 267, // GenericOpcodes.td:1117
283 G_FTAN = 268, // GenericOpcodes.td:1124
284 G_FACOS = 269, // GenericOpcodes.td:1131
285 G_FASIN = 270, // GenericOpcodes.td:1138
286 G_FATAN = 271, // GenericOpcodes.td:1145
287 G_FATAN2 = 272, // GenericOpcodes.td:1152
288 G_FCOSH = 273, // GenericOpcodes.td:1159
289 G_FSINH = 274, // GenericOpcodes.td:1166
290 G_FTANH = 275, // GenericOpcodes.td:1173
291 G_FSQRT = 276, // GenericOpcodes.td:1183
292 G_FFLOOR = 277, // GenericOpcodes.td:1190
293 G_FRINT = 278, // GenericOpcodes.td:1197
294 G_FNEARBYINT = 279, // GenericOpcodes.td:1204
295 G_ADDRSPACE_CAST = 280, // GenericOpcodes.td:241
296 G_BLOCK_ADDR = 281, // GenericOpcodes.td:247
297 G_JUMP_TABLE = 282, // GenericOpcodes.td:253
298 G_DYN_STACKALLOC = 283, // GenericOpcodes.td:259
299 G_STACKSAVE = 284, // GenericOpcodes.td:265
300 G_STACKRESTORE = 285, // GenericOpcodes.td:271
301 G_STRICT_FADD = 286, // GenericOpcodes.td:1758
302 G_STRICT_FSUB = 287, // GenericOpcodes.td:1759
303 G_STRICT_FMUL = 288, // GenericOpcodes.td:1760
304 G_STRICT_FDIV = 289, // GenericOpcodes.td:1761
305 G_STRICT_FREM = 290, // GenericOpcodes.td:1762
306 G_STRICT_FMA = 291, // GenericOpcodes.td:1763
307 G_STRICT_FSQRT = 292, // GenericOpcodes.td:1764
308 G_STRICT_FLDEXP = 293, // GenericOpcodes.td:1765
309 G_READ_REGISTER = 294, // GenericOpcodes.td:1631
310 G_WRITE_REGISTER = 295, // GenericOpcodes.td:1641
311 G_MEMCPY = 296, // GenericOpcodes.td:1771
312 G_MEMCPY_INLINE = 297, // GenericOpcodes.td:1779
313 G_MEMMOVE = 298, // GenericOpcodes.td:1787
314 G_MEMSET = 299, // GenericOpcodes.td:1795
315 G_BZERO = 300, // GenericOpcodes.td:1802
316 G_TRAP = 301, // GenericOpcodes.td:1812
317 G_DEBUGTRAP = 302, // GenericOpcodes.td:1819
318 G_UBSANTRAP = 303, // GenericOpcodes.td:1825
319 G_VECREDUCE_SEQ_FADD = 304, // GenericOpcodes.td:1724
320 G_VECREDUCE_SEQ_FMUL = 305, // GenericOpcodes.td:1730
321 G_VECREDUCE_FADD = 306, // GenericOpcodes.td:1736
322 G_VECREDUCE_FMUL = 307, // GenericOpcodes.td:1737
323 G_VECREDUCE_FMAX = 308, // GenericOpcodes.td:1739
324 G_VECREDUCE_FMIN = 309, // GenericOpcodes.td:1740
325 G_VECREDUCE_FMAXIMUM = 310, // GenericOpcodes.td:1741
326 G_VECREDUCE_FMINIMUM = 311, // GenericOpcodes.td:1742
327 G_VECREDUCE_ADD = 312, // GenericOpcodes.td:1744
328 G_VECREDUCE_MUL = 313, // GenericOpcodes.td:1745
329 G_VECREDUCE_AND = 314, // GenericOpcodes.td:1746
330 G_VECREDUCE_OR = 315, // GenericOpcodes.td:1747
331 G_VECREDUCE_XOR = 316, // GenericOpcodes.td:1748
332 G_VECREDUCE_SMAX = 317, // GenericOpcodes.td:1749
333 G_VECREDUCE_SMIN = 318, // GenericOpcodes.td:1750
334 G_VECREDUCE_UMAX = 319, // GenericOpcodes.td:1751
335 G_VECREDUCE_UMIN = 320, // GenericOpcodes.td:1752
336 G_SBFX = 321, // GenericOpcodes.td:1837
337 G_UBFX = 322, // GenericOpcodes.td:1845
338 CALL_PARAMS = 323, // WebAssemblyInstrFormats.td:59
339 CALL_PARAMS_S = 324, // WebAssemblyInstrFormats.td:61
340 CALL_RESULTS = 325, // WebAssemblyInstrFormats.td:59
341 CALL_RESULTS_S = 326, // WebAssemblyInstrFormats.td:61
342 CATCHRET = 327, // WebAssemblyInstrFormats.td:59
343 CATCHRET_S = 328, // WebAssemblyInstrFormats.td:61
344 CLEANUPRET = 329, // WebAssemblyInstrFormats.td:59
345 CLEANUPRET_S = 330, // WebAssemblyInstrFormats.td:61
346 COMPILER_FENCE = 331, // WebAssemblyInstrFormats.td:59
347 COMPILER_FENCE_S = 332, // WebAssemblyInstrFormats.td:61
348 RET_CALL_RESULTS = 333, // WebAssemblyInstrFormats.td:59
349 RET_CALL_RESULTS_S = 334, // WebAssemblyInstrFormats.td:61
350 ABS_F16x8 = 335, // WebAssemblyInstrFormats.td:59
351 ABS_F16x8_S = 336, // WebAssemblyInstrFormats.td:61
352 ABS_F32 = 337, // WebAssemblyInstrFormats.td:59
353 ABS_F32_S = 338, // WebAssemblyInstrFormats.td:61
354 ABS_F32x4 = 339, // WebAssemblyInstrFormats.td:59
355 ABS_F32x4_S = 340, // WebAssemblyInstrFormats.td:61
356 ABS_F64 = 341, // WebAssemblyInstrFormats.td:59
357 ABS_F64_S = 342, // WebAssemblyInstrFormats.td:61
358 ABS_F64x2 = 343, // WebAssemblyInstrFormats.td:59
359 ABS_F64x2_S = 344, // WebAssemblyInstrFormats.td:61
360 ABS_I16x8 = 345, // WebAssemblyInstrFormats.td:59
361 ABS_I16x8_S = 346, // WebAssemblyInstrFormats.td:61
362 ABS_I32x4 = 347, // WebAssemblyInstrFormats.td:59
363 ABS_I32x4_S = 348, // WebAssemblyInstrFormats.td:61
364 ABS_I64x2 = 349, // WebAssemblyInstrFormats.td:59
365 ABS_I64x2_S = 350, // WebAssemblyInstrFormats.td:61
366 ABS_I8x16 = 351, // WebAssemblyInstrFormats.td:59
367 ABS_I8x16_S = 352, // WebAssemblyInstrFormats.td:61
368 ADD_F16x8 = 353, // WebAssemblyInstrFormats.td:59
369 ADD_F16x8_S = 354, // WebAssemblyInstrFormats.td:61
370 ADD_F32 = 355, // WebAssemblyInstrFormats.td:59
371 ADD_F32_S = 356, // WebAssemblyInstrFormats.td:61
372 ADD_F32x4 = 357, // WebAssemblyInstrFormats.td:59
373 ADD_F32x4_S = 358, // WebAssemblyInstrFormats.td:61
374 ADD_F64 = 359, // WebAssemblyInstrFormats.td:59
375 ADD_F64_S = 360, // WebAssemblyInstrFormats.td:61
376 ADD_F64x2 = 361, // WebAssemblyInstrFormats.td:59
377 ADD_F64x2_S = 362, // WebAssemblyInstrFormats.td:61
378 ADD_I16x8 = 363, // WebAssemblyInstrFormats.td:59
379 ADD_I16x8_S = 364, // WebAssemblyInstrFormats.td:61
380 ADD_I32 = 365, // WebAssemblyInstrFormats.td:59
381 ADD_I32_S = 366, // WebAssemblyInstrFormats.td:61
382 ADD_I32x4 = 367, // WebAssemblyInstrFormats.td:59
383 ADD_I32x4_S = 368, // WebAssemblyInstrFormats.td:61
384 ADD_I64 = 369, // WebAssemblyInstrFormats.td:59
385 ADD_I64_S = 370, // WebAssemblyInstrFormats.td:61
386 ADD_I64x2 = 371, // WebAssemblyInstrFormats.td:59
387 ADD_I64x2_S = 372, // WebAssemblyInstrFormats.td:61
388 ADD_I8x16 = 373, // WebAssemblyInstrFormats.td:59
389 ADD_I8x16_S = 374, // WebAssemblyInstrFormats.td:61
390 ADD_SAT_S_I16x8 = 375, // WebAssemblyInstrFormats.td:59
391 ADD_SAT_S_I16x8_S = 376, // WebAssemblyInstrFormats.td:61
392 ADD_SAT_S_I8x16 = 377, // WebAssemblyInstrFormats.td:59
393 ADD_SAT_S_I8x16_S = 378, // WebAssemblyInstrFormats.td:61
394 ADD_SAT_U_I16x8 = 379, // WebAssemblyInstrFormats.td:59
395 ADD_SAT_U_I16x8_S = 380, // WebAssemblyInstrFormats.td:61
396 ADD_SAT_U_I8x16 = 381, // WebAssemblyInstrFormats.td:59
397 ADD_SAT_U_I8x16_S = 382, // WebAssemblyInstrFormats.td:61
398 ADJCALLSTACKDOWN = 383, // WebAssemblyInstrFormats.td:59
399 ADJCALLSTACKDOWN_S = 384, // WebAssemblyInstrFormats.td:61
400 ADJCALLSTACKUP = 385, // WebAssemblyInstrFormats.td:59
401 ADJCALLSTACKUP_S = 386, // WebAssemblyInstrFormats.td:61
402 ALLTRUE_I16x8 = 387, // WebAssemblyInstrFormats.td:59
403 ALLTRUE_I16x8_S = 388, // WebAssemblyInstrFormats.td:61
404 ALLTRUE_I32x4 = 389, // WebAssemblyInstrFormats.td:59
405 ALLTRUE_I32x4_S = 390, // WebAssemblyInstrFormats.td:61
406 ALLTRUE_I64x2 = 391, // WebAssemblyInstrFormats.td:59
407 ALLTRUE_I64x2_S = 392, // WebAssemblyInstrFormats.td:61
408 ALLTRUE_I8x16 = 393, // WebAssemblyInstrFormats.td:59
409 ALLTRUE_I8x16_S = 394, // WebAssemblyInstrFormats.td:61
410 AND = 395, // WebAssemblyInstrFormats.td:59
411 ANDNOT = 396, // WebAssemblyInstrFormats.td:59
412 ANDNOT_S = 397, // WebAssemblyInstrFormats.td:61
413 AND_I32 = 398, // WebAssemblyInstrFormats.td:59
414 AND_I32_S = 399, // WebAssemblyInstrFormats.td:61
415 AND_I64 = 400, // WebAssemblyInstrFormats.td:59
416 AND_I64_S = 401, // WebAssemblyInstrFormats.td:61
417 AND_S = 402, // WebAssemblyInstrFormats.td:61
418 ANYTRUE = 403, // WebAssemblyInstrFormats.td:59
419 ANYTRUE_S = 404, // WebAssemblyInstrFormats.td:61
420 ARGUMENT_exnref = 405, // WebAssemblyInstrFormats.td:59
421 ARGUMENT_exnref_S = 406, // WebAssemblyInstrFormats.td:61
422 ARGUMENT_externref = 407, // WebAssemblyInstrFormats.td:59
423 ARGUMENT_externref_S = 408, // WebAssemblyInstrFormats.td:61
424 ARGUMENT_f32 = 409, // WebAssemblyInstrFormats.td:59
425 ARGUMENT_f32_S = 410, // WebAssemblyInstrFormats.td:61
426 ARGUMENT_f64 = 411, // WebAssemblyInstrFormats.td:59
427 ARGUMENT_f64_S = 412, // WebAssemblyInstrFormats.td:61
428 ARGUMENT_funcref = 413, // WebAssemblyInstrFormats.td:59
429 ARGUMENT_funcref_S = 414, // WebAssemblyInstrFormats.td:61
430 ARGUMENT_i32 = 415, // WebAssemblyInstrFormats.td:59
431 ARGUMENT_i32_S = 416, // WebAssemblyInstrFormats.td:61
432 ARGUMENT_i64 = 417, // WebAssemblyInstrFormats.td:59
433 ARGUMENT_i64_S = 418, // WebAssemblyInstrFormats.td:61
434 ARGUMENT_v16i8 = 419, // WebAssemblyInstrFormats.td:59
435 ARGUMENT_v16i8_S = 420, // WebAssemblyInstrFormats.td:61
436 ARGUMENT_v2f64 = 421, // WebAssemblyInstrFormats.td:59
437 ARGUMENT_v2f64_S = 422, // WebAssemblyInstrFormats.td:61
438 ARGUMENT_v2i64 = 423, // WebAssemblyInstrFormats.td:59
439 ARGUMENT_v2i64_S = 424, // WebAssemblyInstrFormats.td:61
440 ARGUMENT_v4f32 = 425, // WebAssemblyInstrFormats.td:59
441 ARGUMENT_v4f32_S = 426, // WebAssemblyInstrFormats.td:61
442 ARGUMENT_v4i32 = 427, // WebAssemblyInstrFormats.td:59
443 ARGUMENT_v4i32_S = 428, // WebAssemblyInstrFormats.td:61
444 ARGUMENT_v8f16 = 429, // WebAssemblyInstrFormats.td:59
445 ARGUMENT_v8f16_S = 430, // WebAssemblyInstrFormats.td:61
446 ARGUMENT_v8i16 = 431, // WebAssemblyInstrFormats.td:59
447 ARGUMENT_v8i16_S = 432, // WebAssemblyInstrFormats.td:61
448 ATOMIC_FENCE = 433, // WebAssemblyInstrFormats.td:59
449 ATOMIC_FENCE_S = 434, // WebAssemblyInstrFormats.td:61
450 ATOMIC_LOAD16_U_I32_A32 = 435, // WebAssemblyInstrFormats.td:59
451 ATOMIC_LOAD16_U_I32_A32_S = 436, // WebAssemblyInstrFormats.td:61
452 ATOMIC_LOAD16_U_I32_A64 = 437, // WebAssemblyInstrFormats.td:59
453 ATOMIC_LOAD16_U_I32_A64_S = 438, // WebAssemblyInstrFormats.td:61
454 ATOMIC_LOAD16_U_I64_A32 = 439, // WebAssemblyInstrFormats.td:59
455 ATOMIC_LOAD16_U_I64_A32_S = 440, // WebAssemblyInstrFormats.td:61
456 ATOMIC_LOAD16_U_I64_A64 = 441, // WebAssemblyInstrFormats.td:59
457 ATOMIC_LOAD16_U_I64_A64_S = 442, // WebAssemblyInstrFormats.td:61
458 ATOMIC_LOAD32_U_I64_A32 = 443, // WebAssemblyInstrFormats.td:59
459 ATOMIC_LOAD32_U_I64_A32_S = 444, // WebAssemblyInstrFormats.td:61
460 ATOMIC_LOAD32_U_I64_A64 = 445, // WebAssemblyInstrFormats.td:59
461 ATOMIC_LOAD32_U_I64_A64_S = 446, // WebAssemblyInstrFormats.td:61
462 ATOMIC_LOAD8_U_I32_A32 = 447, // WebAssemblyInstrFormats.td:59
463 ATOMIC_LOAD8_U_I32_A32_S = 448, // WebAssemblyInstrFormats.td:61
464 ATOMIC_LOAD8_U_I32_A64 = 449, // WebAssemblyInstrFormats.td:59
465 ATOMIC_LOAD8_U_I32_A64_S = 450, // WebAssemblyInstrFormats.td:61
466 ATOMIC_LOAD8_U_I64_A32 = 451, // WebAssemblyInstrFormats.td:59
467 ATOMIC_LOAD8_U_I64_A32_S = 452, // WebAssemblyInstrFormats.td:61
468 ATOMIC_LOAD8_U_I64_A64 = 453, // WebAssemblyInstrFormats.td:59
469 ATOMIC_LOAD8_U_I64_A64_S = 454, // WebAssemblyInstrFormats.td:61
470 ATOMIC_LOAD_I32_A32 = 455, // WebAssemblyInstrFormats.td:59
471 ATOMIC_LOAD_I32_A32_S = 456, // WebAssemblyInstrFormats.td:61
472 ATOMIC_LOAD_I32_A64 = 457, // WebAssemblyInstrFormats.td:59
473 ATOMIC_LOAD_I32_A64_S = 458, // WebAssemblyInstrFormats.td:61
474 ATOMIC_LOAD_I64_A32 = 459, // WebAssemblyInstrFormats.td:59
475 ATOMIC_LOAD_I64_A32_S = 460, // WebAssemblyInstrFormats.td:61
476 ATOMIC_LOAD_I64_A64 = 461, // WebAssemblyInstrFormats.td:59
477 ATOMIC_LOAD_I64_A64_S = 462, // WebAssemblyInstrFormats.td:61
478 ATOMIC_RMW16_U_ADD_I32_A32 = 463, // WebAssemblyInstrFormats.td:59
479 ATOMIC_RMW16_U_ADD_I32_A32_S = 464, // WebAssemblyInstrFormats.td:61
480 ATOMIC_RMW16_U_ADD_I32_A64 = 465, // WebAssemblyInstrFormats.td:59
481 ATOMIC_RMW16_U_ADD_I32_A64_S = 466, // WebAssemblyInstrFormats.td:61
482 ATOMIC_RMW16_U_ADD_I64_A32 = 467, // WebAssemblyInstrFormats.td:59
483 ATOMIC_RMW16_U_ADD_I64_A32_S = 468, // WebAssemblyInstrFormats.td:61
484 ATOMIC_RMW16_U_ADD_I64_A64 = 469, // WebAssemblyInstrFormats.td:59
485 ATOMIC_RMW16_U_ADD_I64_A64_S = 470, // WebAssemblyInstrFormats.td:61
486 ATOMIC_RMW16_U_AND_I32_A32 = 471, // WebAssemblyInstrFormats.td:59
487 ATOMIC_RMW16_U_AND_I32_A32_S = 472, // WebAssemblyInstrFormats.td:61
488 ATOMIC_RMW16_U_AND_I32_A64 = 473, // WebAssemblyInstrFormats.td:59
489 ATOMIC_RMW16_U_AND_I32_A64_S = 474, // WebAssemblyInstrFormats.td:61
490 ATOMIC_RMW16_U_AND_I64_A32 = 475, // WebAssemblyInstrFormats.td:59
491 ATOMIC_RMW16_U_AND_I64_A32_S = 476, // WebAssemblyInstrFormats.td:61
492 ATOMIC_RMW16_U_AND_I64_A64 = 477, // WebAssemblyInstrFormats.td:59
493 ATOMIC_RMW16_U_AND_I64_A64_S = 478, // WebAssemblyInstrFormats.td:61
494 ATOMIC_RMW16_U_CMPXCHG_I32_A32 = 479, // WebAssemblyInstrFormats.td:59
495 ATOMIC_RMW16_U_CMPXCHG_I32_A32_S = 480, // WebAssemblyInstrFormats.td:61
496 ATOMIC_RMW16_U_CMPXCHG_I32_A64 = 481, // WebAssemblyInstrFormats.td:59
497 ATOMIC_RMW16_U_CMPXCHG_I32_A64_S = 482, // WebAssemblyInstrFormats.td:61
498 ATOMIC_RMW16_U_CMPXCHG_I64_A32 = 483, // WebAssemblyInstrFormats.td:59
499 ATOMIC_RMW16_U_CMPXCHG_I64_A32_S = 484, // WebAssemblyInstrFormats.td:61
500 ATOMIC_RMW16_U_CMPXCHG_I64_A64 = 485, // WebAssemblyInstrFormats.td:59
501 ATOMIC_RMW16_U_CMPXCHG_I64_A64_S = 486, // WebAssemblyInstrFormats.td:61
502 ATOMIC_RMW16_U_OR_I32_A32 = 487, // WebAssemblyInstrFormats.td:59
503 ATOMIC_RMW16_U_OR_I32_A32_S = 488, // WebAssemblyInstrFormats.td:61
504 ATOMIC_RMW16_U_OR_I32_A64 = 489, // WebAssemblyInstrFormats.td:59
505 ATOMIC_RMW16_U_OR_I32_A64_S = 490, // WebAssemblyInstrFormats.td:61
506 ATOMIC_RMW16_U_OR_I64_A32 = 491, // WebAssemblyInstrFormats.td:59
507 ATOMIC_RMW16_U_OR_I64_A32_S = 492, // WebAssemblyInstrFormats.td:61
508 ATOMIC_RMW16_U_OR_I64_A64 = 493, // WebAssemblyInstrFormats.td:59
509 ATOMIC_RMW16_U_OR_I64_A64_S = 494, // WebAssemblyInstrFormats.td:61
510 ATOMIC_RMW16_U_SUB_I32_A32 = 495, // WebAssemblyInstrFormats.td:59
511 ATOMIC_RMW16_U_SUB_I32_A32_S = 496, // WebAssemblyInstrFormats.td:61
512 ATOMIC_RMW16_U_SUB_I32_A64 = 497, // WebAssemblyInstrFormats.td:59
513 ATOMIC_RMW16_U_SUB_I32_A64_S = 498, // WebAssemblyInstrFormats.td:61
514 ATOMIC_RMW16_U_SUB_I64_A32 = 499, // WebAssemblyInstrFormats.td:59
515 ATOMIC_RMW16_U_SUB_I64_A32_S = 500, // WebAssemblyInstrFormats.td:61
516 ATOMIC_RMW16_U_SUB_I64_A64 = 501, // WebAssemblyInstrFormats.td:59
517 ATOMIC_RMW16_U_SUB_I64_A64_S = 502, // WebAssemblyInstrFormats.td:61
518 ATOMIC_RMW16_U_XCHG_I32_A32 = 503, // WebAssemblyInstrFormats.td:59
519 ATOMIC_RMW16_U_XCHG_I32_A32_S = 504, // WebAssemblyInstrFormats.td:61
520 ATOMIC_RMW16_U_XCHG_I32_A64 = 505, // WebAssemblyInstrFormats.td:59
521 ATOMIC_RMW16_U_XCHG_I32_A64_S = 506, // WebAssemblyInstrFormats.td:61
522 ATOMIC_RMW16_U_XCHG_I64_A32 = 507, // WebAssemblyInstrFormats.td:59
523 ATOMIC_RMW16_U_XCHG_I64_A32_S = 508, // WebAssemblyInstrFormats.td:61
524 ATOMIC_RMW16_U_XCHG_I64_A64 = 509, // WebAssemblyInstrFormats.td:59
525 ATOMIC_RMW16_U_XCHG_I64_A64_S = 510, // WebAssemblyInstrFormats.td:61
526 ATOMIC_RMW16_U_XOR_I32_A32 = 511, // WebAssemblyInstrFormats.td:59
527 ATOMIC_RMW16_U_XOR_I32_A32_S = 512, // WebAssemblyInstrFormats.td:61
528 ATOMIC_RMW16_U_XOR_I32_A64 = 513, // WebAssemblyInstrFormats.td:59
529 ATOMIC_RMW16_U_XOR_I32_A64_S = 514, // WebAssemblyInstrFormats.td:61
530 ATOMIC_RMW16_U_XOR_I64_A32 = 515, // WebAssemblyInstrFormats.td:59
531 ATOMIC_RMW16_U_XOR_I64_A32_S = 516, // WebAssemblyInstrFormats.td:61
532 ATOMIC_RMW16_U_XOR_I64_A64 = 517, // WebAssemblyInstrFormats.td:59
533 ATOMIC_RMW16_U_XOR_I64_A64_S = 518, // WebAssemblyInstrFormats.td:61
534 ATOMIC_RMW32_U_ADD_I64_A32 = 519, // WebAssemblyInstrFormats.td:59
535 ATOMIC_RMW32_U_ADD_I64_A32_S = 520, // WebAssemblyInstrFormats.td:61
536 ATOMIC_RMW32_U_ADD_I64_A64 = 521, // WebAssemblyInstrFormats.td:59
537 ATOMIC_RMW32_U_ADD_I64_A64_S = 522, // WebAssemblyInstrFormats.td:61
538 ATOMIC_RMW32_U_AND_I64_A32 = 523, // WebAssemblyInstrFormats.td:59
539 ATOMIC_RMW32_U_AND_I64_A32_S = 524, // WebAssemblyInstrFormats.td:61
540 ATOMIC_RMW32_U_AND_I64_A64 = 525, // WebAssemblyInstrFormats.td:59
541 ATOMIC_RMW32_U_AND_I64_A64_S = 526, // WebAssemblyInstrFormats.td:61
542 ATOMIC_RMW32_U_CMPXCHG_I64_A32 = 527, // WebAssemblyInstrFormats.td:59
543 ATOMIC_RMW32_U_CMPXCHG_I64_A32_S = 528, // WebAssemblyInstrFormats.td:61
544 ATOMIC_RMW32_U_CMPXCHG_I64_A64 = 529, // WebAssemblyInstrFormats.td:59
545 ATOMIC_RMW32_U_CMPXCHG_I64_A64_S = 530, // WebAssemblyInstrFormats.td:61
546 ATOMIC_RMW32_U_OR_I64_A32 = 531, // WebAssemblyInstrFormats.td:59
547 ATOMIC_RMW32_U_OR_I64_A32_S = 532, // WebAssemblyInstrFormats.td:61
548 ATOMIC_RMW32_U_OR_I64_A64 = 533, // WebAssemblyInstrFormats.td:59
549 ATOMIC_RMW32_U_OR_I64_A64_S = 534, // WebAssemblyInstrFormats.td:61
550 ATOMIC_RMW32_U_SUB_I64_A32 = 535, // WebAssemblyInstrFormats.td:59
551 ATOMIC_RMW32_U_SUB_I64_A32_S = 536, // WebAssemblyInstrFormats.td:61
552 ATOMIC_RMW32_U_SUB_I64_A64 = 537, // WebAssemblyInstrFormats.td:59
553 ATOMIC_RMW32_U_SUB_I64_A64_S = 538, // WebAssemblyInstrFormats.td:61
554 ATOMIC_RMW32_U_XCHG_I64_A32 = 539, // WebAssemblyInstrFormats.td:59
555 ATOMIC_RMW32_U_XCHG_I64_A32_S = 540, // WebAssemblyInstrFormats.td:61
556 ATOMIC_RMW32_U_XCHG_I64_A64 = 541, // WebAssemblyInstrFormats.td:59
557 ATOMIC_RMW32_U_XCHG_I64_A64_S = 542, // WebAssemblyInstrFormats.td:61
558 ATOMIC_RMW32_U_XOR_I64_A32 = 543, // WebAssemblyInstrFormats.td:59
559 ATOMIC_RMW32_U_XOR_I64_A32_S = 544, // WebAssemblyInstrFormats.td:61
560 ATOMIC_RMW32_U_XOR_I64_A64 = 545, // WebAssemblyInstrFormats.td:59
561 ATOMIC_RMW32_U_XOR_I64_A64_S = 546, // WebAssemblyInstrFormats.td:61
562 ATOMIC_RMW8_U_ADD_I32_A32 = 547, // WebAssemblyInstrFormats.td:59
563 ATOMIC_RMW8_U_ADD_I32_A32_S = 548, // WebAssemblyInstrFormats.td:61
564 ATOMIC_RMW8_U_ADD_I32_A64 = 549, // WebAssemblyInstrFormats.td:59
565 ATOMIC_RMW8_U_ADD_I32_A64_S = 550, // WebAssemblyInstrFormats.td:61
566 ATOMIC_RMW8_U_ADD_I64_A32 = 551, // WebAssemblyInstrFormats.td:59
567 ATOMIC_RMW8_U_ADD_I64_A32_S = 552, // WebAssemblyInstrFormats.td:61
568 ATOMIC_RMW8_U_ADD_I64_A64 = 553, // WebAssemblyInstrFormats.td:59
569 ATOMIC_RMW8_U_ADD_I64_A64_S = 554, // WebAssemblyInstrFormats.td:61
570 ATOMIC_RMW8_U_AND_I32_A32 = 555, // WebAssemblyInstrFormats.td:59
571 ATOMIC_RMW8_U_AND_I32_A32_S = 556, // WebAssemblyInstrFormats.td:61
572 ATOMIC_RMW8_U_AND_I32_A64 = 557, // WebAssemblyInstrFormats.td:59
573 ATOMIC_RMW8_U_AND_I32_A64_S = 558, // WebAssemblyInstrFormats.td:61
574 ATOMIC_RMW8_U_AND_I64_A32 = 559, // WebAssemblyInstrFormats.td:59
575 ATOMIC_RMW8_U_AND_I64_A32_S = 560, // WebAssemblyInstrFormats.td:61
576 ATOMIC_RMW8_U_AND_I64_A64 = 561, // WebAssemblyInstrFormats.td:59
577 ATOMIC_RMW8_U_AND_I64_A64_S = 562, // WebAssemblyInstrFormats.td:61
578 ATOMIC_RMW8_U_CMPXCHG_I32_A32 = 563, // WebAssemblyInstrFormats.td:59
579 ATOMIC_RMW8_U_CMPXCHG_I32_A32_S = 564, // WebAssemblyInstrFormats.td:61
580 ATOMIC_RMW8_U_CMPXCHG_I32_A64 = 565, // WebAssemblyInstrFormats.td:59
581 ATOMIC_RMW8_U_CMPXCHG_I32_A64_S = 566, // WebAssemblyInstrFormats.td:61
582 ATOMIC_RMW8_U_CMPXCHG_I64_A32 = 567, // WebAssemblyInstrFormats.td:59
583 ATOMIC_RMW8_U_CMPXCHG_I64_A32_S = 568, // WebAssemblyInstrFormats.td:61
584 ATOMIC_RMW8_U_CMPXCHG_I64_A64 = 569, // WebAssemblyInstrFormats.td:59
585 ATOMIC_RMW8_U_CMPXCHG_I64_A64_S = 570, // WebAssemblyInstrFormats.td:61
586 ATOMIC_RMW8_U_OR_I32_A32 = 571, // WebAssemblyInstrFormats.td:59
587 ATOMIC_RMW8_U_OR_I32_A32_S = 572, // WebAssemblyInstrFormats.td:61
588 ATOMIC_RMW8_U_OR_I32_A64 = 573, // WebAssemblyInstrFormats.td:59
589 ATOMIC_RMW8_U_OR_I32_A64_S = 574, // WebAssemblyInstrFormats.td:61
590 ATOMIC_RMW8_U_OR_I64_A32 = 575, // WebAssemblyInstrFormats.td:59
591 ATOMIC_RMW8_U_OR_I64_A32_S = 576, // WebAssemblyInstrFormats.td:61
592 ATOMIC_RMW8_U_OR_I64_A64 = 577, // WebAssemblyInstrFormats.td:59
593 ATOMIC_RMW8_U_OR_I64_A64_S = 578, // WebAssemblyInstrFormats.td:61
594 ATOMIC_RMW8_U_SUB_I32_A32 = 579, // WebAssemblyInstrFormats.td:59
595 ATOMIC_RMW8_U_SUB_I32_A32_S = 580, // WebAssemblyInstrFormats.td:61
596 ATOMIC_RMW8_U_SUB_I32_A64 = 581, // WebAssemblyInstrFormats.td:59
597 ATOMIC_RMW8_U_SUB_I32_A64_S = 582, // WebAssemblyInstrFormats.td:61
598 ATOMIC_RMW8_U_SUB_I64_A32 = 583, // WebAssemblyInstrFormats.td:59
599 ATOMIC_RMW8_U_SUB_I64_A32_S = 584, // WebAssemblyInstrFormats.td:61
600 ATOMIC_RMW8_U_SUB_I64_A64 = 585, // WebAssemblyInstrFormats.td:59
601 ATOMIC_RMW8_U_SUB_I64_A64_S = 586, // WebAssemblyInstrFormats.td:61
602 ATOMIC_RMW8_U_XCHG_I32_A32 = 587, // WebAssemblyInstrFormats.td:59
603 ATOMIC_RMW8_U_XCHG_I32_A32_S = 588, // WebAssemblyInstrFormats.td:61
604 ATOMIC_RMW8_U_XCHG_I32_A64 = 589, // WebAssemblyInstrFormats.td:59
605 ATOMIC_RMW8_U_XCHG_I32_A64_S = 590, // WebAssemblyInstrFormats.td:61
606 ATOMIC_RMW8_U_XCHG_I64_A32 = 591, // WebAssemblyInstrFormats.td:59
607 ATOMIC_RMW8_U_XCHG_I64_A32_S = 592, // WebAssemblyInstrFormats.td:61
608 ATOMIC_RMW8_U_XCHG_I64_A64 = 593, // WebAssemblyInstrFormats.td:59
609 ATOMIC_RMW8_U_XCHG_I64_A64_S = 594, // WebAssemblyInstrFormats.td:61
610 ATOMIC_RMW8_U_XOR_I32_A32 = 595, // WebAssemblyInstrFormats.td:59
611 ATOMIC_RMW8_U_XOR_I32_A32_S = 596, // WebAssemblyInstrFormats.td:61
612 ATOMIC_RMW8_U_XOR_I32_A64 = 597, // WebAssemblyInstrFormats.td:59
613 ATOMIC_RMW8_U_XOR_I32_A64_S = 598, // WebAssemblyInstrFormats.td:61
614 ATOMIC_RMW8_U_XOR_I64_A32 = 599, // WebAssemblyInstrFormats.td:59
615 ATOMIC_RMW8_U_XOR_I64_A32_S = 600, // WebAssemblyInstrFormats.td:61
616 ATOMIC_RMW8_U_XOR_I64_A64 = 601, // WebAssemblyInstrFormats.td:59
617 ATOMIC_RMW8_U_XOR_I64_A64_S = 602, // WebAssemblyInstrFormats.td:61
618 ATOMIC_RMW_ADD_I32_A32 = 603, // WebAssemblyInstrFormats.td:59
619 ATOMIC_RMW_ADD_I32_A32_S = 604, // WebAssemblyInstrFormats.td:61
620 ATOMIC_RMW_ADD_I32_A64 = 605, // WebAssemblyInstrFormats.td:59
621 ATOMIC_RMW_ADD_I32_A64_S = 606, // WebAssemblyInstrFormats.td:61
622 ATOMIC_RMW_ADD_I64_A32 = 607, // WebAssemblyInstrFormats.td:59
623 ATOMIC_RMW_ADD_I64_A32_S = 608, // WebAssemblyInstrFormats.td:61
624 ATOMIC_RMW_ADD_I64_A64 = 609, // WebAssemblyInstrFormats.td:59
625 ATOMIC_RMW_ADD_I64_A64_S = 610, // WebAssemblyInstrFormats.td:61
626 ATOMIC_RMW_AND_I32_A32 = 611, // WebAssemblyInstrFormats.td:59
627 ATOMIC_RMW_AND_I32_A32_S = 612, // WebAssemblyInstrFormats.td:61
628 ATOMIC_RMW_AND_I32_A64 = 613, // WebAssemblyInstrFormats.td:59
629 ATOMIC_RMW_AND_I32_A64_S = 614, // WebAssemblyInstrFormats.td:61
630 ATOMIC_RMW_AND_I64_A32 = 615, // WebAssemblyInstrFormats.td:59
631 ATOMIC_RMW_AND_I64_A32_S = 616, // WebAssemblyInstrFormats.td:61
632 ATOMIC_RMW_AND_I64_A64 = 617, // WebAssemblyInstrFormats.td:59
633 ATOMIC_RMW_AND_I64_A64_S = 618, // WebAssemblyInstrFormats.td:61
634 ATOMIC_RMW_CMPXCHG_I32_A32 = 619, // WebAssemblyInstrFormats.td:59
635 ATOMIC_RMW_CMPXCHG_I32_A32_S = 620, // WebAssemblyInstrFormats.td:61
636 ATOMIC_RMW_CMPXCHG_I32_A64 = 621, // WebAssemblyInstrFormats.td:59
637 ATOMIC_RMW_CMPXCHG_I32_A64_S = 622, // WebAssemblyInstrFormats.td:61
638 ATOMIC_RMW_CMPXCHG_I64_A32 = 623, // WebAssemblyInstrFormats.td:59
639 ATOMIC_RMW_CMPXCHG_I64_A32_S = 624, // WebAssemblyInstrFormats.td:61
640 ATOMIC_RMW_CMPXCHG_I64_A64 = 625, // WebAssemblyInstrFormats.td:59
641 ATOMIC_RMW_CMPXCHG_I64_A64_S = 626, // WebAssemblyInstrFormats.td:61
642 ATOMIC_RMW_OR_I32_A32 = 627, // WebAssemblyInstrFormats.td:59
643 ATOMIC_RMW_OR_I32_A32_S = 628, // WebAssemblyInstrFormats.td:61
644 ATOMIC_RMW_OR_I32_A64 = 629, // WebAssemblyInstrFormats.td:59
645 ATOMIC_RMW_OR_I32_A64_S = 630, // WebAssemblyInstrFormats.td:61
646 ATOMIC_RMW_OR_I64_A32 = 631, // WebAssemblyInstrFormats.td:59
647 ATOMIC_RMW_OR_I64_A32_S = 632, // WebAssemblyInstrFormats.td:61
648 ATOMIC_RMW_OR_I64_A64 = 633, // WebAssemblyInstrFormats.td:59
649 ATOMIC_RMW_OR_I64_A64_S = 634, // WebAssemblyInstrFormats.td:61
650 ATOMIC_RMW_SUB_I32_A32 = 635, // WebAssemblyInstrFormats.td:59
651 ATOMIC_RMW_SUB_I32_A32_S = 636, // WebAssemblyInstrFormats.td:61
652 ATOMIC_RMW_SUB_I32_A64 = 637, // WebAssemblyInstrFormats.td:59
653 ATOMIC_RMW_SUB_I32_A64_S = 638, // WebAssemblyInstrFormats.td:61
654 ATOMIC_RMW_SUB_I64_A32 = 639, // WebAssemblyInstrFormats.td:59
655 ATOMIC_RMW_SUB_I64_A32_S = 640, // WebAssemblyInstrFormats.td:61
656 ATOMIC_RMW_SUB_I64_A64 = 641, // WebAssemblyInstrFormats.td:59
657 ATOMIC_RMW_SUB_I64_A64_S = 642, // WebAssemblyInstrFormats.td:61
658 ATOMIC_RMW_XCHG_I32_A32 = 643, // WebAssemblyInstrFormats.td:59
659 ATOMIC_RMW_XCHG_I32_A32_S = 644, // WebAssemblyInstrFormats.td:61
660 ATOMIC_RMW_XCHG_I32_A64 = 645, // WebAssemblyInstrFormats.td:59
661 ATOMIC_RMW_XCHG_I32_A64_S = 646, // WebAssemblyInstrFormats.td:61
662 ATOMIC_RMW_XCHG_I64_A32 = 647, // WebAssemblyInstrFormats.td:59
663 ATOMIC_RMW_XCHG_I64_A32_S = 648, // WebAssemblyInstrFormats.td:61
664 ATOMIC_RMW_XCHG_I64_A64 = 649, // WebAssemblyInstrFormats.td:59
665 ATOMIC_RMW_XCHG_I64_A64_S = 650, // WebAssemblyInstrFormats.td:61
666 ATOMIC_RMW_XOR_I32_A32 = 651, // WebAssemblyInstrFormats.td:59
667 ATOMIC_RMW_XOR_I32_A32_S = 652, // WebAssemblyInstrFormats.td:61
668 ATOMIC_RMW_XOR_I32_A64 = 653, // WebAssemblyInstrFormats.td:59
669 ATOMIC_RMW_XOR_I32_A64_S = 654, // WebAssemblyInstrFormats.td:61
670 ATOMIC_RMW_XOR_I64_A32 = 655, // WebAssemblyInstrFormats.td:59
671 ATOMIC_RMW_XOR_I64_A32_S = 656, // WebAssemblyInstrFormats.td:61
672 ATOMIC_RMW_XOR_I64_A64 = 657, // WebAssemblyInstrFormats.td:59
673 ATOMIC_RMW_XOR_I64_A64_S = 658, // WebAssemblyInstrFormats.td:61
674 ATOMIC_STORE16_I32_A32 = 659, // WebAssemblyInstrFormats.td:59
675 ATOMIC_STORE16_I32_A32_S = 660, // WebAssemblyInstrFormats.td:61
676 ATOMIC_STORE16_I32_A64 = 661, // WebAssemblyInstrFormats.td:59
677 ATOMIC_STORE16_I32_A64_S = 662, // WebAssemblyInstrFormats.td:61
678 ATOMIC_STORE16_I64_A32 = 663, // WebAssemblyInstrFormats.td:59
679 ATOMIC_STORE16_I64_A32_S = 664, // WebAssemblyInstrFormats.td:61
680 ATOMIC_STORE16_I64_A64 = 665, // WebAssemblyInstrFormats.td:59
681 ATOMIC_STORE16_I64_A64_S = 666, // WebAssemblyInstrFormats.td:61
682 ATOMIC_STORE32_I64_A32 = 667, // WebAssemblyInstrFormats.td:59
683 ATOMIC_STORE32_I64_A32_S = 668, // WebAssemblyInstrFormats.td:61
684 ATOMIC_STORE32_I64_A64 = 669, // WebAssemblyInstrFormats.td:59
685 ATOMIC_STORE32_I64_A64_S = 670, // WebAssemblyInstrFormats.td:61
686 ATOMIC_STORE8_I32_A32 = 671, // WebAssemblyInstrFormats.td:59
687 ATOMIC_STORE8_I32_A32_S = 672, // WebAssemblyInstrFormats.td:61
688 ATOMIC_STORE8_I32_A64 = 673, // WebAssemblyInstrFormats.td:59
689 ATOMIC_STORE8_I32_A64_S = 674, // WebAssemblyInstrFormats.td:61
690 ATOMIC_STORE8_I64_A32 = 675, // WebAssemblyInstrFormats.td:59
691 ATOMIC_STORE8_I64_A32_S = 676, // WebAssemblyInstrFormats.td:61
692 ATOMIC_STORE8_I64_A64 = 677, // WebAssemblyInstrFormats.td:59
693 ATOMIC_STORE8_I64_A64_S = 678, // WebAssemblyInstrFormats.td:61
694 ATOMIC_STORE_I32_A32 = 679, // WebAssemblyInstrFormats.td:59
695 ATOMIC_STORE_I32_A32_S = 680, // WebAssemblyInstrFormats.td:61
696 ATOMIC_STORE_I32_A64 = 681, // WebAssemblyInstrFormats.td:59
697 ATOMIC_STORE_I32_A64_S = 682, // WebAssemblyInstrFormats.td:61
698 ATOMIC_STORE_I64_A32 = 683, // WebAssemblyInstrFormats.td:59
699 ATOMIC_STORE_I64_A32_S = 684, // WebAssemblyInstrFormats.td:61
700 ATOMIC_STORE_I64_A64 = 685, // WebAssemblyInstrFormats.td:59
701 ATOMIC_STORE_I64_A64_S = 686, // WebAssemblyInstrFormats.td:61
702 AVGR_U_I16x8 = 687, // WebAssemblyInstrFormats.td:59
703 AVGR_U_I16x8_S = 688, // WebAssemblyInstrFormats.td:61
704 AVGR_U_I8x16 = 689, // WebAssemblyInstrFormats.td:59
705 AVGR_U_I8x16_S = 690, // WebAssemblyInstrFormats.td:61
706 BITMASK_I16x8 = 691, // WebAssemblyInstrFormats.td:59
707 BITMASK_I16x8_S = 692, // WebAssemblyInstrFormats.td:61
708 BITMASK_I32x4 = 693, // WebAssemblyInstrFormats.td:59
709 BITMASK_I32x4_S = 694, // WebAssemblyInstrFormats.td:61
710 BITMASK_I64x2 = 695, // WebAssemblyInstrFormats.td:59
711 BITMASK_I64x2_S = 696, // WebAssemblyInstrFormats.td:61
712 BITMASK_I8x16 = 697, // WebAssemblyInstrFormats.td:59
713 BITMASK_I8x16_S = 698, // WebAssemblyInstrFormats.td:61
714 BITSELECT = 699, // WebAssemblyInstrFormats.td:59
715 BITSELECT_S = 700, // WebAssemblyInstrFormats.td:61
716 BLOCK = 701, // WebAssemblyInstrFormats.td:59
717 BLOCK_S = 702, // WebAssemblyInstrFormats.td:61
718 BR = 703, // WebAssemblyInstrFormats.td:59
719 BR_IF = 704, // WebAssemblyInstrFormats.td:59
720 BR_IF_S = 705, // WebAssemblyInstrFormats.td:61
721 BR_S = 706, // WebAssemblyInstrFormats.td:61
722 BR_TABLE_I32 = 707, // WebAssemblyInstrFormats.td:59
723 BR_TABLE_I32_S = 708, // WebAssemblyInstrFormats.td:61
724 BR_TABLE_I64 = 709, // WebAssemblyInstrFormats.td:59
725 BR_TABLE_I64_S = 710, // WebAssemblyInstrFormats.td:61
726 BR_UNLESS = 711, // WebAssemblyInstrFormats.td:59
727 BR_UNLESS_S = 712, // WebAssemblyInstrFormats.td:61
728 CALL = 713, // WebAssemblyInstrFormats.td:59
729 CALL_INDIRECT = 714, // WebAssemblyInstrFormats.td:59
730 CALL_INDIRECT_S = 715, // WebAssemblyInstrFormats.td:61
731 CALL_S = 716, // WebAssemblyInstrFormats.td:61
732 CATCH = 717, // WebAssemblyInstrFormats.td:59
733 CATCH_ALL = 718, // WebAssemblyInstrFormats.td:59
734 CATCH_ALL_LEGACY = 719, // WebAssemblyInstrFormats.td:59
735 CATCH_ALL_LEGACY_S = 720, // WebAssemblyInstrFormats.td:61
736 CATCH_ALL_REF = 721, // WebAssemblyInstrFormats.td:59
737 CATCH_ALL_REF_S = 722, // WebAssemblyInstrFormats.td:61
738 CATCH_ALL_S = 723, // WebAssemblyInstrFormats.td:61
739 CATCH_LEGACY = 724, // WebAssemblyInstrFormats.td:59
740 CATCH_LEGACY_S = 725, // WebAssemblyInstrFormats.td:61
741 CATCH_REF = 726, // WebAssemblyInstrFormats.td:59
742 CATCH_REF_S = 727, // WebAssemblyInstrFormats.td:61
743 CATCH_S = 728, // WebAssemblyInstrFormats.td:61
744 CEIL_F16x8 = 729, // WebAssemblyInstrFormats.td:59
745 CEIL_F16x8_S = 730, // WebAssemblyInstrFormats.td:61
746 CEIL_F32 = 731, // WebAssemblyInstrFormats.td:59
747 CEIL_F32_S = 732, // WebAssemblyInstrFormats.td:61
748 CEIL_F32x4 = 733, // WebAssemblyInstrFormats.td:59
749 CEIL_F32x4_S = 734, // WebAssemblyInstrFormats.td:61
750 CEIL_F64 = 735, // WebAssemblyInstrFormats.td:59
751 CEIL_F64_S = 736, // WebAssemblyInstrFormats.td:61
752 CEIL_F64x2 = 737, // WebAssemblyInstrFormats.td:59
753 CEIL_F64x2_S = 738, // WebAssemblyInstrFormats.td:61
754 CLZ_I32 = 739, // WebAssemblyInstrFormats.td:59
755 CLZ_I32_S = 740, // WebAssemblyInstrFormats.td:61
756 CLZ_I64 = 741, // WebAssemblyInstrFormats.td:59
757 CLZ_I64_S = 742, // WebAssemblyInstrFormats.td:61
758 CONST_F32 = 743, // WebAssemblyInstrFormats.td:59
759 CONST_F32_S = 744, // WebAssemblyInstrFormats.td:61
760 CONST_F64 = 745, // WebAssemblyInstrFormats.td:59
761 CONST_F64_S = 746, // WebAssemblyInstrFormats.td:61
762 CONST_I32 = 747, // WebAssemblyInstrFormats.td:59
763 CONST_I32_S = 748, // WebAssemblyInstrFormats.td:61
764 CONST_I64 = 749, // WebAssemblyInstrFormats.td:59
765 CONST_I64_S = 750, // WebAssemblyInstrFormats.td:61
766 CONST_V128_F32x4 = 751, // WebAssemblyInstrFormats.td:59
767 CONST_V128_F32x4_S = 752, // WebAssemblyInstrFormats.td:61
768 CONST_V128_F64x2 = 753, // WebAssemblyInstrFormats.td:59
769 CONST_V128_F64x2_S = 754, // WebAssemblyInstrFormats.td:61
770 CONST_V128_I16x8 = 755, // WebAssemblyInstrFormats.td:59
771 CONST_V128_I16x8_S = 756, // WebAssemblyInstrFormats.td:61
772 CONST_V128_I32x4 = 757, // WebAssemblyInstrFormats.td:59
773 CONST_V128_I32x4_S = 758, // WebAssemblyInstrFormats.td:61
774 CONST_V128_I64x2 = 759, // WebAssemblyInstrFormats.td:59
775 CONST_V128_I64x2_S = 760, // WebAssemblyInstrFormats.td:61
776 CONST_V128_I8x16 = 761, // WebAssemblyInstrFormats.td:59
777 CONST_V128_I8x16_S = 762, // WebAssemblyInstrFormats.td:61
778 COPYSIGN_F32 = 763, // WebAssemblyInstrFormats.td:59
779 COPYSIGN_F32_S = 764, // WebAssemblyInstrFormats.td:61
780 COPYSIGN_F64 = 765, // WebAssemblyInstrFormats.td:59
781 COPYSIGN_F64_S = 766, // WebAssemblyInstrFormats.td:61
782 COPY_EXNREF = 767, // WebAssemblyInstrFormats.td:59
783 COPY_EXNREF_S = 768, // WebAssemblyInstrFormats.td:61
784 COPY_EXTERNREF = 769, // WebAssemblyInstrFormats.td:59
785 COPY_EXTERNREF_S = 770, // WebAssemblyInstrFormats.td:61
786 COPY_F32 = 771, // WebAssemblyInstrFormats.td:59
787 COPY_F32_S = 772, // WebAssemblyInstrFormats.td:61
788 COPY_F64 = 773, // WebAssemblyInstrFormats.td:59
789 COPY_F64_S = 774, // WebAssemblyInstrFormats.td:61
790 COPY_FUNCREF = 775, // WebAssemblyInstrFormats.td:59
791 COPY_FUNCREF_S = 776, // WebAssemblyInstrFormats.td:61
792 COPY_I32 = 777, // WebAssemblyInstrFormats.td:59
793 COPY_I32_S = 778, // WebAssemblyInstrFormats.td:61
794 COPY_I64 = 779, // WebAssemblyInstrFormats.td:59
795 COPY_I64_S = 780, // WebAssemblyInstrFormats.td:61
796 COPY_V128 = 781, // WebAssemblyInstrFormats.td:59
797 COPY_V128_S = 782, // WebAssemblyInstrFormats.td:61
798 CTZ_I32 = 783, // WebAssemblyInstrFormats.td:59
799 CTZ_I32_S = 784, // WebAssemblyInstrFormats.td:61
800 CTZ_I64 = 785, // WebAssemblyInstrFormats.td:59
801 CTZ_I64_S = 786, // WebAssemblyInstrFormats.td:61
802 DATA_DROP = 787, // WebAssemblyInstrFormats.td:59
803 DATA_DROP_S = 788, // WebAssemblyInstrFormats.td:61
804 DEBUG_UNREACHABLE = 789, // WebAssemblyInstrFormats.td:59
805 DEBUG_UNREACHABLE_S = 790, // WebAssemblyInstrFormats.td:61
806 DELEGATE = 791, // WebAssemblyInstrFormats.td:59
807 DELEGATE_S = 792, // WebAssemblyInstrFormats.td:61
808 DIV_F16x8 = 793, // WebAssemblyInstrFormats.td:59
809 DIV_F16x8_S = 794, // WebAssemblyInstrFormats.td:61
810 DIV_F32 = 795, // WebAssemblyInstrFormats.td:59
811 DIV_F32_S = 796, // WebAssemblyInstrFormats.td:61
812 DIV_F32x4 = 797, // WebAssemblyInstrFormats.td:59
813 DIV_F32x4_S = 798, // WebAssemblyInstrFormats.td:61
814 DIV_F64 = 799, // WebAssemblyInstrFormats.td:59
815 DIV_F64_S = 800, // WebAssemblyInstrFormats.td:61
816 DIV_F64x2 = 801, // WebAssemblyInstrFormats.td:59
817 DIV_F64x2_S = 802, // WebAssemblyInstrFormats.td:61
818 DIV_S_I32 = 803, // WebAssemblyInstrFormats.td:59
819 DIV_S_I32_S = 804, // WebAssemblyInstrFormats.td:61
820 DIV_S_I64 = 805, // WebAssemblyInstrFormats.td:59
821 DIV_S_I64_S = 806, // WebAssemblyInstrFormats.td:61
822 DIV_U_I32 = 807, // WebAssemblyInstrFormats.td:59
823 DIV_U_I32_S = 808, // WebAssemblyInstrFormats.td:61
824 DIV_U_I64 = 809, // WebAssemblyInstrFormats.td:59
825 DIV_U_I64_S = 810, // WebAssemblyInstrFormats.td:61
826 DOT = 811, // WebAssemblyInstrFormats.td:59
827 DOT_S = 812, // WebAssemblyInstrFormats.td:61
828 DROP_EXNREF = 813, // WebAssemblyInstrFormats.td:59
829 DROP_EXNREF_S = 814, // WebAssemblyInstrFormats.td:61
830 DROP_EXTERNREF = 815, // WebAssemblyInstrFormats.td:59
831 DROP_EXTERNREF_S = 816, // WebAssemblyInstrFormats.td:61
832 DROP_F32 = 817, // WebAssemblyInstrFormats.td:59
833 DROP_F32_S = 818, // WebAssemblyInstrFormats.td:61
834 DROP_F64 = 819, // WebAssemblyInstrFormats.td:59
835 DROP_F64_S = 820, // WebAssemblyInstrFormats.td:61
836 DROP_FUNCREF = 821, // WebAssemblyInstrFormats.td:59
837 DROP_FUNCREF_S = 822, // WebAssemblyInstrFormats.td:61
838 DROP_I32 = 823, // WebAssemblyInstrFormats.td:59
839 DROP_I32_S = 824, // WebAssemblyInstrFormats.td:61
840 DROP_I64 = 825, // WebAssemblyInstrFormats.td:59
841 DROP_I64_S = 826, // WebAssemblyInstrFormats.td:61
842 DROP_V128 = 827, // WebAssemblyInstrFormats.td:59
843 DROP_V128_S = 828, // WebAssemblyInstrFormats.td:61
844 ELSE = 829, // WebAssemblyInstrFormats.td:59
845 ELSE_S = 830, // WebAssemblyInstrFormats.td:61
846 END = 831, // WebAssemblyInstrFormats.td:59
847 END_BLOCK = 832, // WebAssemblyInstrFormats.td:59
848 END_BLOCK_S = 833, // WebAssemblyInstrFormats.td:61
849 END_FUNCTION = 834, // WebAssemblyInstrFormats.td:59
850 END_FUNCTION_S = 835, // WebAssemblyInstrFormats.td:61
851 END_IF = 836, // WebAssemblyInstrFormats.td:59
852 END_IF_S = 837, // WebAssemblyInstrFormats.td:61
853 END_LOOP = 838, // WebAssemblyInstrFormats.td:59
854 END_LOOP_S = 839, // WebAssemblyInstrFormats.td:61
855 END_S = 840, // WebAssemblyInstrFormats.td:61
856 END_TRY = 841, // WebAssemblyInstrFormats.td:59
857 END_TRY_S = 842, // WebAssemblyInstrFormats.td:61
858 END_TRY_TABLE = 843, // WebAssemblyInstrFormats.td:59
859 END_TRY_TABLE_S = 844, // WebAssemblyInstrFormats.td:61
860 EQZ_I32 = 845, // WebAssemblyInstrFormats.td:59
861 EQZ_I32_S = 846, // WebAssemblyInstrFormats.td:61
862 EQZ_I64 = 847, // WebAssemblyInstrFormats.td:59
863 EQZ_I64_S = 848, // WebAssemblyInstrFormats.td:61
864 EQ_F16x8 = 849, // WebAssemblyInstrFormats.td:59
865 EQ_F16x8_S = 850, // WebAssemblyInstrFormats.td:61
866 EQ_F32 = 851, // WebAssemblyInstrFormats.td:59
867 EQ_F32_S = 852, // WebAssemblyInstrFormats.td:61
868 EQ_F32x4 = 853, // WebAssemblyInstrFormats.td:59
869 EQ_F32x4_S = 854, // WebAssemblyInstrFormats.td:61
870 EQ_F64 = 855, // WebAssemblyInstrFormats.td:59
871 EQ_F64_S = 856, // WebAssemblyInstrFormats.td:61
872 EQ_F64x2 = 857, // WebAssemblyInstrFormats.td:59
873 EQ_F64x2_S = 858, // WebAssemblyInstrFormats.td:61
874 EQ_I16x8 = 859, // WebAssemblyInstrFormats.td:59
875 EQ_I16x8_S = 860, // WebAssemblyInstrFormats.td:61
876 EQ_I32 = 861, // WebAssemblyInstrFormats.td:59
877 EQ_I32_S = 862, // WebAssemblyInstrFormats.td:61
878 EQ_I32x4 = 863, // WebAssemblyInstrFormats.td:59
879 EQ_I32x4_S = 864, // WebAssemblyInstrFormats.td:61
880 EQ_I64 = 865, // WebAssemblyInstrFormats.td:59
881 EQ_I64_S = 866, // WebAssemblyInstrFormats.td:61
882 EQ_I64x2 = 867, // WebAssemblyInstrFormats.td:59
883 EQ_I64x2_S = 868, // WebAssemblyInstrFormats.td:61
884 EQ_I8x16 = 869, // WebAssemblyInstrFormats.td:59
885 EQ_I8x16_S = 870, // WebAssemblyInstrFormats.td:61
886 EXTMUL_HIGH_S_I16x8 = 871, // WebAssemblyInstrFormats.td:59
887 EXTMUL_HIGH_S_I16x8_S = 872, // WebAssemblyInstrFormats.td:61
888 EXTMUL_HIGH_S_I32x4 = 873, // WebAssemblyInstrFormats.td:59
889 EXTMUL_HIGH_S_I32x4_S = 874, // WebAssemblyInstrFormats.td:61
890 EXTMUL_HIGH_S_I64x2 = 875, // WebAssemblyInstrFormats.td:59
891 EXTMUL_HIGH_S_I64x2_S = 876, // WebAssemblyInstrFormats.td:61
892 EXTMUL_HIGH_U_I16x8 = 877, // WebAssemblyInstrFormats.td:59
893 EXTMUL_HIGH_U_I16x8_S = 878, // WebAssemblyInstrFormats.td:61
894 EXTMUL_HIGH_U_I32x4 = 879, // WebAssemblyInstrFormats.td:59
895 EXTMUL_HIGH_U_I32x4_S = 880, // WebAssemblyInstrFormats.td:61
896 EXTMUL_HIGH_U_I64x2 = 881, // WebAssemblyInstrFormats.td:59
897 EXTMUL_HIGH_U_I64x2_S = 882, // WebAssemblyInstrFormats.td:61
898 EXTMUL_LOW_S_I16x8 = 883, // WebAssemblyInstrFormats.td:59
899 EXTMUL_LOW_S_I16x8_S = 884, // WebAssemblyInstrFormats.td:61
900 EXTMUL_LOW_S_I32x4 = 885, // WebAssemblyInstrFormats.td:59
901 EXTMUL_LOW_S_I32x4_S = 886, // WebAssemblyInstrFormats.td:61
902 EXTMUL_LOW_S_I64x2 = 887, // WebAssemblyInstrFormats.td:59
903 EXTMUL_LOW_S_I64x2_S = 888, // WebAssemblyInstrFormats.td:61
904 EXTMUL_LOW_U_I16x8 = 889, // WebAssemblyInstrFormats.td:59
905 EXTMUL_LOW_U_I16x8_S = 890, // WebAssemblyInstrFormats.td:61
906 EXTMUL_LOW_U_I32x4 = 891, // WebAssemblyInstrFormats.td:59
907 EXTMUL_LOW_U_I32x4_S = 892, // WebAssemblyInstrFormats.td:61
908 EXTMUL_LOW_U_I64x2 = 893, // WebAssemblyInstrFormats.td:59
909 EXTMUL_LOW_U_I64x2_S = 894, // WebAssemblyInstrFormats.td:61
910 EXTRACT_LANE_F16x8 = 895, // WebAssemblyInstrFormats.td:59
911 EXTRACT_LANE_F16x8_S = 896, // WebAssemblyInstrFormats.td:61
912 EXTRACT_LANE_F32x4 = 897, // WebAssemblyInstrFormats.td:59
913 EXTRACT_LANE_F32x4_S = 898, // WebAssemblyInstrFormats.td:61
914 EXTRACT_LANE_F64x2 = 899, // WebAssemblyInstrFormats.td:59
915 EXTRACT_LANE_F64x2_S = 900, // WebAssemblyInstrFormats.td:61
916 EXTRACT_LANE_I16x8_s = 901, // WebAssemblyInstrFormats.td:59
917 EXTRACT_LANE_I16x8_s_S = 902, // WebAssemblyInstrFormats.td:61
918 EXTRACT_LANE_I16x8_u = 903, // WebAssemblyInstrFormats.td:59
919 EXTRACT_LANE_I16x8_u_S = 904, // WebAssemblyInstrFormats.td:61
920 EXTRACT_LANE_I32x4 = 905, // WebAssemblyInstrFormats.td:59
921 EXTRACT_LANE_I32x4_S = 906, // WebAssemblyInstrFormats.td:61
922 EXTRACT_LANE_I64x2 = 907, // WebAssemblyInstrFormats.td:59
923 EXTRACT_LANE_I64x2_S = 908, // WebAssemblyInstrFormats.td:61
924 EXTRACT_LANE_I8x16_s = 909, // WebAssemblyInstrFormats.td:59
925 EXTRACT_LANE_I8x16_s_S = 910, // WebAssemblyInstrFormats.td:61
926 EXTRACT_LANE_I8x16_u = 911, // WebAssemblyInstrFormats.td:59
927 EXTRACT_LANE_I8x16_u_S = 912, // WebAssemblyInstrFormats.td:61
928 F32_CONVERT_S_I32 = 913, // WebAssemblyInstrFormats.td:59
929 F32_CONVERT_S_I32_S = 914, // WebAssemblyInstrFormats.td:61
930 F32_CONVERT_S_I64 = 915, // WebAssemblyInstrFormats.td:59
931 F32_CONVERT_S_I64_S = 916, // WebAssemblyInstrFormats.td:61
932 F32_CONVERT_U_I32 = 917, // WebAssemblyInstrFormats.td:59
933 F32_CONVERT_U_I32_S = 918, // WebAssemblyInstrFormats.td:61
934 F32_CONVERT_U_I64 = 919, // WebAssemblyInstrFormats.td:59
935 F32_CONVERT_U_I64_S = 920, // WebAssemblyInstrFormats.td:61
936 F32_DEMOTE_F64 = 921, // WebAssemblyInstrFormats.td:59
937 F32_DEMOTE_F64_S = 922, // WebAssemblyInstrFormats.td:61
938 F32_REINTERPRET_I32 = 923, // WebAssemblyInstrFormats.td:59
939 F32_REINTERPRET_I32_S = 924, // WebAssemblyInstrFormats.td:61
940 F64_CONVERT_S_I32 = 925, // WebAssemblyInstrFormats.td:59
941 F64_CONVERT_S_I32_S = 926, // WebAssemblyInstrFormats.td:61
942 F64_CONVERT_S_I64 = 927, // WebAssemblyInstrFormats.td:59
943 F64_CONVERT_S_I64_S = 928, // WebAssemblyInstrFormats.td:61
944 F64_CONVERT_U_I32 = 929, // WebAssemblyInstrFormats.td:59
945 F64_CONVERT_U_I32_S = 930, // WebAssemblyInstrFormats.td:61
946 F64_CONVERT_U_I64 = 931, // WebAssemblyInstrFormats.td:59
947 F64_CONVERT_U_I64_S = 932, // WebAssemblyInstrFormats.td:61
948 F64_PROMOTE_F32 = 933, // WebAssemblyInstrFormats.td:59
949 F64_PROMOTE_F32_S = 934, // WebAssemblyInstrFormats.td:61
950 F64_REINTERPRET_I64 = 935, // WebAssemblyInstrFormats.td:59
951 F64_REINTERPRET_I64_S = 936, // WebAssemblyInstrFormats.td:61
952 FALLTHROUGH_RETURN = 937, // WebAssemblyInstrFormats.td:59
953 FALLTHROUGH_RETURN_S = 938, // WebAssemblyInstrFormats.td:61
954 FLOOR_F16x8 = 939, // WebAssemblyInstrFormats.td:59
955 FLOOR_F16x8_S = 940, // WebAssemblyInstrFormats.td:61
956 FLOOR_F32 = 941, // WebAssemblyInstrFormats.td:59
957 FLOOR_F32_S = 942, // WebAssemblyInstrFormats.td:61
958 FLOOR_F32x4 = 943, // WebAssemblyInstrFormats.td:59
959 FLOOR_F32x4_S = 944, // WebAssemblyInstrFormats.td:61
960 FLOOR_F64 = 945, // WebAssemblyInstrFormats.td:59
961 FLOOR_F64_S = 946, // WebAssemblyInstrFormats.td:61
962 FLOOR_F64x2 = 947, // WebAssemblyInstrFormats.td:59
963 FLOOR_F64x2_S = 948, // WebAssemblyInstrFormats.td:61
964 FP_TO_SINT_I32_F32 = 949, // WebAssemblyInstrFormats.td:59
965 FP_TO_SINT_I32_F32_S = 950, // WebAssemblyInstrFormats.td:61
966 FP_TO_SINT_I32_F64 = 951, // WebAssemblyInstrFormats.td:59
967 FP_TO_SINT_I32_F64_S = 952, // WebAssemblyInstrFormats.td:61
968 FP_TO_SINT_I64_F32 = 953, // WebAssemblyInstrFormats.td:59
969 FP_TO_SINT_I64_F32_S = 954, // WebAssemblyInstrFormats.td:61
970 FP_TO_SINT_I64_F64 = 955, // WebAssemblyInstrFormats.td:59
971 FP_TO_SINT_I64_F64_S = 956, // WebAssemblyInstrFormats.td:61
972 FP_TO_UINT_I32_F32 = 957, // WebAssemblyInstrFormats.td:59
973 FP_TO_UINT_I32_F32_S = 958, // WebAssemblyInstrFormats.td:61
974 FP_TO_UINT_I32_F64 = 959, // WebAssemblyInstrFormats.td:59
975 FP_TO_UINT_I32_F64_S = 960, // WebAssemblyInstrFormats.td:61
976 FP_TO_UINT_I64_F32 = 961, // WebAssemblyInstrFormats.td:59
977 FP_TO_UINT_I64_F32_S = 962, // WebAssemblyInstrFormats.td:61
978 FP_TO_UINT_I64_F64 = 963, // WebAssemblyInstrFormats.td:59
979 FP_TO_UINT_I64_F64_S = 964, // WebAssemblyInstrFormats.td:61
980 GE_F16x8 = 965, // WebAssemblyInstrFormats.td:59
981 GE_F16x8_S = 966, // WebAssemblyInstrFormats.td:61
982 GE_F32 = 967, // WebAssemblyInstrFormats.td:59
983 GE_F32_S = 968, // WebAssemblyInstrFormats.td:61
984 GE_F32x4 = 969, // WebAssemblyInstrFormats.td:59
985 GE_F32x4_S = 970, // WebAssemblyInstrFormats.td:61
986 GE_F64 = 971, // WebAssemblyInstrFormats.td:59
987 GE_F64_S = 972, // WebAssemblyInstrFormats.td:61
988 GE_F64x2 = 973, // WebAssemblyInstrFormats.td:59
989 GE_F64x2_S = 974, // WebAssemblyInstrFormats.td:61
990 GE_S_I16x8 = 975, // WebAssemblyInstrFormats.td:59
991 GE_S_I16x8_S = 976, // WebAssemblyInstrFormats.td:61
992 GE_S_I32 = 977, // WebAssemblyInstrFormats.td:59
993 GE_S_I32_S = 978, // WebAssemblyInstrFormats.td:61
994 GE_S_I32x4 = 979, // WebAssemblyInstrFormats.td:59
995 GE_S_I32x4_S = 980, // WebAssemblyInstrFormats.td:61
996 GE_S_I64 = 981, // WebAssemblyInstrFormats.td:59
997 GE_S_I64_S = 982, // WebAssemblyInstrFormats.td:61
998 GE_S_I64x2 = 983, // WebAssemblyInstrFormats.td:59
999 GE_S_I64x2_S = 984, // WebAssemblyInstrFormats.td:61
1000 GE_S_I8x16 = 985, // WebAssemblyInstrFormats.td:59
1001 GE_S_I8x16_S = 986, // WebAssemblyInstrFormats.td:61
1002 GE_U_I16x8 = 987, // WebAssemblyInstrFormats.td:59
1003 GE_U_I16x8_S = 988, // WebAssemblyInstrFormats.td:61
1004 GE_U_I32 = 989, // WebAssemblyInstrFormats.td:59
1005 GE_U_I32_S = 990, // WebAssemblyInstrFormats.td:61
1006 GE_U_I32x4 = 991, // WebAssemblyInstrFormats.td:59
1007 GE_U_I32x4_S = 992, // WebAssemblyInstrFormats.td:61
1008 GE_U_I64 = 993, // WebAssemblyInstrFormats.td:59
1009 GE_U_I64_S = 994, // WebAssemblyInstrFormats.td:61
1010 GE_U_I8x16 = 995, // WebAssemblyInstrFormats.td:59
1011 GE_U_I8x16_S = 996, // WebAssemblyInstrFormats.td:61
1012 GLOBAL_GET_EXNREF = 997, // WebAssemblyInstrFormats.td:59
1013 GLOBAL_GET_EXNREF_S = 998, // WebAssemblyInstrFormats.td:61
1014 GLOBAL_GET_EXTERNREF = 999, // WebAssemblyInstrFormats.td:59
1015 GLOBAL_GET_EXTERNREF_S = 1000, // WebAssemblyInstrFormats.td:61
1016 GLOBAL_GET_F32 = 1001, // WebAssemblyInstrFormats.td:59
1017 GLOBAL_GET_F32_S = 1002, // WebAssemblyInstrFormats.td:61
1018 GLOBAL_GET_F64 = 1003, // WebAssemblyInstrFormats.td:59
1019 GLOBAL_GET_F64_S = 1004, // WebAssemblyInstrFormats.td:61
1020 GLOBAL_GET_FUNCREF = 1005, // WebAssemblyInstrFormats.td:59
1021 GLOBAL_GET_FUNCREF_S = 1006, // WebAssemblyInstrFormats.td:61
1022 GLOBAL_GET_I32 = 1007, // WebAssemblyInstrFormats.td:59
1023 GLOBAL_GET_I32_S = 1008, // WebAssemblyInstrFormats.td:61
1024 GLOBAL_GET_I64 = 1009, // WebAssemblyInstrFormats.td:59
1025 GLOBAL_GET_I64_S = 1010, // WebAssemblyInstrFormats.td:61
1026 GLOBAL_GET_V128 = 1011, // WebAssemblyInstrFormats.td:59
1027 GLOBAL_GET_V128_S = 1012, // WebAssemblyInstrFormats.td:61
1028 GLOBAL_SET_EXNREF = 1013, // WebAssemblyInstrFormats.td:59
1029 GLOBAL_SET_EXNREF_S = 1014, // WebAssemblyInstrFormats.td:61
1030 GLOBAL_SET_EXTERNREF = 1015, // WebAssemblyInstrFormats.td:59
1031 GLOBAL_SET_EXTERNREF_S = 1016, // WebAssemblyInstrFormats.td:61
1032 GLOBAL_SET_F32 = 1017, // WebAssemblyInstrFormats.td:59
1033 GLOBAL_SET_F32_S = 1018, // WebAssemblyInstrFormats.td:61
1034 GLOBAL_SET_F64 = 1019, // WebAssemblyInstrFormats.td:59
1035 GLOBAL_SET_F64_S = 1020, // WebAssemblyInstrFormats.td:61
1036 GLOBAL_SET_FUNCREF = 1021, // WebAssemblyInstrFormats.td:59
1037 GLOBAL_SET_FUNCREF_S = 1022, // WebAssemblyInstrFormats.td:61
1038 GLOBAL_SET_I32 = 1023, // WebAssemblyInstrFormats.td:59
1039 GLOBAL_SET_I32_S = 1024, // WebAssemblyInstrFormats.td:61
1040 GLOBAL_SET_I64 = 1025, // WebAssemblyInstrFormats.td:59
1041 GLOBAL_SET_I64_S = 1026, // WebAssemblyInstrFormats.td:61
1042 GLOBAL_SET_V128 = 1027, // WebAssemblyInstrFormats.td:59
1043 GLOBAL_SET_V128_S = 1028, // WebAssemblyInstrFormats.td:61
1044 GT_F16x8 = 1029, // WebAssemblyInstrFormats.td:59
1045 GT_F16x8_S = 1030, // WebAssemblyInstrFormats.td:61
1046 GT_F32 = 1031, // WebAssemblyInstrFormats.td:59
1047 GT_F32_S = 1032, // WebAssemblyInstrFormats.td:61
1048 GT_F32x4 = 1033, // WebAssemblyInstrFormats.td:59
1049 GT_F32x4_S = 1034, // WebAssemblyInstrFormats.td:61
1050 GT_F64 = 1035, // WebAssemblyInstrFormats.td:59
1051 GT_F64_S = 1036, // WebAssemblyInstrFormats.td:61
1052 GT_F64x2 = 1037, // WebAssemblyInstrFormats.td:59
1053 GT_F64x2_S = 1038, // WebAssemblyInstrFormats.td:61
1054 GT_S_I16x8 = 1039, // WebAssemblyInstrFormats.td:59
1055 GT_S_I16x8_S = 1040, // WebAssemblyInstrFormats.td:61
1056 GT_S_I32 = 1041, // WebAssemblyInstrFormats.td:59
1057 GT_S_I32_S = 1042, // WebAssemblyInstrFormats.td:61
1058 GT_S_I32x4 = 1043, // WebAssemblyInstrFormats.td:59
1059 GT_S_I32x4_S = 1044, // WebAssemblyInstrFormats.td:61
1060 GT_S_I64 = 1045, // WebAssemblyInstrFormats.td:59
1061 GT_S_I64_S = 1046, // WebAssemblyInstrFormats.td:61
1062 GT_S_I64x2 = 1047, // WebAssemblyInstrFormats.td:59
1063 GT_S_I64x2_S = 1048, // WebAssemblyInstrFormats.td:61
1064 GT_S_I8x16 = 1049, // WebAssemblyInstrFormats.td:59
1065 GT_S_I8x16_S = 1050, // WebAssemblyInstrFormats.td:61
1066 GT_U_I16x8 = 1051, // WebAssemblyInstrFormats.td:59
1067 GT_U_I16x8_S = 1052, // WebAssemblyInstrFormats.td:61
1068 GT_U_I32 = 1053, // WebAssemblyInstrFormats.td:59
1069 GT_U_I32_S = 1054, // WebAssemblyInstrFormats.td:61
1070 GT_U_I32x4 = 1055, // WebAssemblyInstrFormats.td:59
1071 GT_U_I32x4_S = 1056, // WebAssemblyInstrFormats.td:61
1072 GT_U_I64 = 1057, // WebAssemblyInstrFormats.td:59
1073 GT_U_I64_S = 1058, // WebAssemblyInstrFormats.td:61
1074 GT_U_I8x16 = 1059, // WebAssemblyInstrFormats.td:59
1075 GT_U_I8x16_S = 1060, // WebAssemblyInstrFormats.td:61
1076 I32_EXTEND16_S_I32 = 1061, // WebAssemblyInstrFormats.td:59
1077 I32_EXTEND16_S_I32_S = 1062, // WebAssemblyInstrFormats.td:61
1078 I32_EXTEND8_S_I32 = 1063, // WebAssemblyInstrFormats.td:59
1079 I32_EXTEND8_S_I32_S = 1064, // WebAssemblyInstrFormats.td:61
1080 I32_REINTERPRET_F32 = 1065, // WebAssemblyInstrFormats.td:59
1081 I32_REINTERPRET_F32_S = 1066, // WebAssemblyInstrFormats.td:61
1082 I32_TRUNC_S_F32 = 1067, // WebAssemblyInstrFormats.td:59
1083 I32_TRUNC_S_F32_S = 1068, // WebAssemblyInstrFormats.td:61
1084 I32_TRUNC_S_F64 = 1069, // WebAssemblyInstrFormats.td:59
1085 I32_TRUNC_S_F64_S = 1070, // WebAssemblyInstrFormats.td:61
1086 I32_TRUNC_S_SAT_F32 = 1071, // WebAssemblyInstrFormats.td:59
1087 I32_TRUNC_S_SAT_F32_S = 1072, // WebAssemblyInstrFormats.td:61
1088 I32_TRUNC_S_SAT_F64 = 1073, // WebAssemblyInstrFormats.td:59
1089 I32_TRUNC_S_SAT_F64_S = 1074, // WebAssemblyInstrFormats.td:61
1090 I32_TRUNC_U_F32 = 1075, // WebAssemblyInstrFormats.td:59
1091 I32_TRUNC_U_F32_S = 1076, // WebAssemblyInstrFormats.td:61
1092 I32_TRUNC_U_F64 = 1077, // WebAssemblyInstrFormats.td:59
1093 I32_TRUNC_U_F64_S = 1078, // WebAssemblyInstrFormats.td:61
1094 I32_TRUNC_U_SAT_F32 = 1079, // WebAssemblyInstrFormats.td:59
1095 I32_TRUNC_U_SAT_F32_S = 1080, // WebAssemblyInstrFormats.td:61
1096 I32_TRUNC_U_SAT_F64 = 1081, // WebAssemblyInstrFormats.td:59
1097 I32_TRUNC_U_SAT_F64_S = 1082, // WebAssemblyInstrFormats.td:61
1098 I32_WRAP_I64 = 1083, // WebAssemblyInstrFormats.td:59
1099 I32_WRAP_I64_S = 1084, // WebAssemblyInstrFormats.td:61
1100 I64_ADD128 = 1085, // WebAssemblyInstrFormats.td:59
1101 I64_ADD128_S = 1086, // WebAssemblyInstrFormats.td:61
1102 I64_EXTEND16_S_I64 = 1087, // WebAssemblyInstrFormats.td:59
1103 I64_EXTEND16_S_I64_S = 1088, // WebAssemblyInstrFormats.td:61
1104 I64_EXTEND32_S_I64 = 1089, // WebAssemblyInstrFormats.td:59
1105 I64_EXTEND32_S_I64_S = 1090, // WebAssemblyInstrFormats.td:61
1106 I64_EXTEND8_S_I64 = 1091, // WebAssemblyInstrFormats.td:59
1107 I64_EXTEND8_S_I64_S = 1092, // WebAssemblyInstrFormats.td:61
1108 I64_EXTEND_S_I32 = 1093, // WebAssemblyInstrFormats.td:59
1109 I64_EXTEND_S_I32_S = 1094, // WebAssemblyInstrFormats.td:61
1110 I64_EXTEND_U_I32 = 1095, // WebAssemblyInstrFormats.td:59
1111 I64_EXTEND_U_I32_S = 1096, // WebAssemblyInstrFormats.td:61
1112 I64_MUL_WIDE_S = 1097, // WebAssemblyInstrFormats.td:59
1113 I64_MUL_WIDE_S_S = 1098, // WebAssemblyInstrFormats.td:61
1114 I64_MUL_WIDE_U = 1099, // WebAssemblyInstrFormats.td:59
1115 I64_MUL_WIDE_U_S = 1100, // WebAssemblyInstrFormats.td:61
1116 I64_REINTERPRET_F64 = 1101, // WebAssemblyInstrFormats.td:59
1117 I64_REINTERPRET_F64_S = 1102, // WebAssemblyInstrFormats.td:61
1118 I64_SUB128 = 1103, // WebAssemblyInstrFormats.td:59
1119 I64_SUB128_S = 1104, // WebAssemblyInstrFormats.td:61
1120 I64_TRUNC_S_F32 = 1105, // WebAssemblyInstrFormats.td:59
1121 I64_TRUNC_S_F32_S = 1106, // WebAssemblyInstrFormats.td:61
1122 I64_TRUNC_S_F64 = 1107, // WebAssemblyInstrFormats.td:59
1123 I64_TRUNC_S_F64_S = 1108, // WebAssemblyInstrFormats.td:61
1124 I64_TRUNC_S_SAT_F32 = 1109, // WebAssemblyInstrFormats.td:59
1125 I64_TRUNC_S_SAT_F32_S = 1110, // WebAssemblyInstrFormats.td:61
1126 I64_TRUNC_S_SAT_F64 = 1111, // WebAssemblyInstrFormats.td:59
1127 I64_TRUNC_S_SAT_F64_S = 1112, // WebAssemblyInstrFormats.td:61
1128 I64_TRUNC_U_F32 = 1113, // WebAssemblyInstrFormats.td:59
1129 I64_TRUNC_U_F32_S = 1114, // WebAssemblyInstrFormats.td:61
1130 I64_TRUNC_U_F64 = 1115, // WebAssemblyInstrFormats.td:59
1131 I64_TRUNC_U_F64_S = 1116, // WebAssemblyInstrFormats.td:61
1132 I64_TRUNC_U_SAT_F32 = 1117, // WebAssemblyInstrFormats.td:59
1133 I64_TRUNC_U_SAT_F32_S = 1118, // WebAssemblyInstrFormats.td:61
1134 I64_TRUNC_U_SAT_F64 = 1119, // WebAssemblyInstrFormats.td:59
1135 I64_TRUNC_U_SAT_F64_S = 1120, // WebAssemblyInstrFormats.td:61
1136 IF = 1121, // WebAssemblyInstrFormats.td:59
1137 IF_S = 1122, // WebAssemblyInstrFormats.td:61
1138 LANESELECT_I16x8 = 1123, // WebAssemblyInstrFormats.td:59
1139 LANESELECT_I16x8_S = 1124, // WebAssemblyInstrFormats.td:61
1140 LANESELECT_I32x4 = 1125, // WebAssemblyInstrFormats.td:59
1141 LANESELECT_I32x4_S = 1126, // WebAssemblyInstrFormats.td:61
1142 LANESELECT_I64x2 = 1127, // WebAssemblyInstrFormats.td:59
1143 LANESELECT_I64x2_S = 1128, // WebAssemblyInstrFormats.td:61
1144 LANESELECT_I8x16 = 1129, // WebAssemblyInstrFormats.td:59
1145 LANESELECT_I8x16_S = 1130, // WebAssemblyInstrFormats.td:61
1146 LE_F16x8 = 1131, // WebAssemblyInstrFormats.td:59
1147 LE_F16x8_S = 1132, // WebAssemblyInstrFormats.td:61
1148 LE_F32 = 1133, // WebAssemblyInstrFormats.td:59
1149 LE_F32_S = 1134, // WebAssemblyInstrFormats.td:61
1150 LE_F32x4 = 1135, // WebAssemblyInstrFormats.td:59
1151 LE_F32x4_S = 1136, // WebAssemblyInstrFormats.td:61
1152 LE_F64 = 1137, // WebAssemblyInstrFormats.td:59
1153 LE_F64_S = 1138, // WebAssemblyInstrFormats.td:61
1154 LE_F64x2 = 1139, // WebAssemblyInstrFormats.td:59
1155 LE_F64x2_S = 1140, // WebAssemblyInstrFormats.td:61
1156 LE_S_I16x8 = 1141, // WebAssemblyInstrFormats.td:59
1157 LE_S_I16x8_S = 1142, // WebAssemblyInstrFormats.td:61
1158 LE_S_I32 = 1143, // WebAssemblyInstrFormats.td:59
1159 LE_S_I32_S = 1144, // WebAssemblyInstrFormats.td:61
1160 LE_S_I32x4 = 1145, // WebAssemblyInstrFormats.td:59
1161 LE_S_I32x4_S = 1146, // WebAssemblyInstrFormats.td:61
1162 LE_S_I64 = 1147, // WebAssemblyInstrFormats.td:59
1163 LE_S_I64_S = 1148, // WebAssemblyInstrFormats.td:61
1164 LE_S_I64x2 = 1149, // WebAssemblyInstrFormats.td:59
1165 LE_S_I64x2_S = 1150, // WebAssemblyInstrFormats.td:61
1166 LE_S_I8x16 = 1151, // WebAssemblyInstrFormats.td:59
1167 LE_S_I8x16_S = 1152, // WebAssemblyInstrFormats.td:61
1168 LE_U_I16x8 = 1153, // WebAssemblyInstrFormats.td:59
1169 LE_U_I16x8_S = 1154, // WebAssemblyInstrFormats.td:61
1170 LE_U_I32 = 1155, // WebAssemblyInstrFormats.td:59
1171 LE_U_I32_S = 1156, // WebAssemblyInstrFormats.td:61
1172 LE_U_I32x4 = 1157, // WebAssemblyInstrFormats.td:59
1173 LE_U_I32x4_S = 1158, // WebAssemblyInstrFormats.td:61
1174 LE_U_I64 = 1159, // WebAssemblyInstrFormats.td:59
1175 LE_U_I64_S = 1160, // WebAssemblyInstrFormats.td:61
1176 LE_U_I8x16 = 1161, // WebAssemblyInstrFormats.td:59
1177 LE_U_I8x16_S = 1162, // WebAssemblyInstrFormats.td:61
1178 LOAD16_SPLAT_A32 = 1163, // WebAssemblyInstrFormats.td:59
1179 LOAD16_SPLAT_A32_S = 1164, // WebAssemblyInstrFormats.td:61
1180 LOAD16_SPLAT_A64 = 1165, // WebAssemblyInstrFormats.td:59
1181 LOAD16_SPLAT_A64_S = 1166, // WebAssemblyInstrFormats.td:61
1182 LOAD16_S_I32_A32 = 1167, // WebAssemblyInstrFormats.td:59
1183 LOAD16_S_I32_A32_S = 1168, // WebAssemblyInstrFormats.td:61
1184 LOAD16_S_I32_A64 = 1169, // WebAssemblyInstrFormats.td:59
1185 LOAD16_S_I32_A64_S = 1170, // WebAssemblyInstrFormats.td:61
1186 LOAD16_S_I64_A32 = 1171, // WebAssemblyInstrFormats.td:59
1187 LOAD16_S_I64_A32_S = 1172, // WebAssemblyInstrFormats.td:61
1188 LOAD16_S_I64_A64 = 1173, // WebAssemblyInstrFormats.td:59
1189 LOAD16_S_I64_A64_S = 1174, // WebAssemblyInstrFormats.td:61
1190 LOAD16_U_I32_A32 = 1175, // WebAssemblyInstrFormats.td:59
1191 LOAD16_U_I32_A32_S = 1176, // WebAssemblyInstrFormats.td:61
1192 LOAD16_U_I32_A64 = 1177, // WebAssemblyInstrFormats.td:59
1193 LOAD16_U_I32_A64_S = 1178, // WebAssemblyInstrFormats.td:61
1194 LOAD16_U_I64_A32 = 1179, // WebAssemblyInstrFormats.td:59
1195 LOAD16_U_I64_A32_S = 1180, // WebAssemblyInstrFormats.td:61
1196 LOAD16_U_I64_A64 = 1181, // WebAssemblyInstrFormats.td:59
1197 LOAD16_U_I64_A64_S = 1182, // WebAssemblyInstrFormats.td:61
1198 LOAD32_SPLAT_A32 = 1183, // WebAssemblyInstrFormats.td:59
1199 LOAD32_SPLAT_A32_S = 1184, // WebAssemblyInstrFormats.td:61
1200 LOAD32_SPLAT_A64 = 1185, // WebAssemblyInstrFormats.td:59
1201 LOAD32_SPLAT_A64_S = 1186, // WebAssemblyInstrFormats.td:61
1202 LOAD32_S_I64_A32 = 1187, // WebAssemblyInstrFormats.td:59
1203 LOAD32_S_I64_A32_S = 1188, // WebAssemblyInstrFormats.td:61
1204 LOAD32_S_I64_A64 = 1189, // WebAssemblyInstrFormats.td:59
1205 LOAD32_S_I64_A64_S = 1190, // WebAssemblyInstrFormats.td:61
1206 LOAD32_U_I64_A32 = 1191, // WebAssemblyInstrFormats.td:59
1207 LOAD32_U_I64_A32_S = 1192, // WebAssemblyInstrFormats.td:61
1208 LOAD32_U_I64_A64 = 1193, // WebAssemblyInstrFormats.td:59
1209 LOAD32_U_I64_A64_S = 1194, // WebAssemblyInstrFormats.td:61
1210 LOAD64_SPLAT_A32 = 1195, // WebAssemblyInstrFormats.td:59
1211 LOAD64_SPLAT_A32_S = 1196, // WebAssemblyInstrFormats.td:61
1212 LOAD64_SPLAT_A64 = 1197, // WebAssemblyInstrFormats.td:59
1213 LOAD64_SPLAT_A64_S = 1198, // WebAssemblyInstrFormats.td:61
1214 LOAD8_SPLAT_A32 = 1199, // WebAssemblyInstrFormats.td:59
1215 LOAD8_SPLAT_A32_S = 1200, // WebAssemblyInstrFormats.td:61
1216 LOAD8_SPLAT_A64 = 1201, // WebAssemblyInstrFormats.td:59
1217 LOAD8_SPLAT_A64_S = 1202, // WebAssemblyInstrFormats.td:61
1218 LOAD8_S_I32_A32 = 1203, // WebAssemblyInstrFormats.td:59
1219 LOAD8_S_I32_A32_S = 1204, // WebAssemblyInstrFormats.td:61
1220 LOAD8_S_I32_A64 = 1205, // WebAssemblyInstrFormats.td:59
1221 LOAD8_S_I32_A64_S = 1206, // WebAssemblyInstrFormats.td:61
1222 LOAD8_S_I64_A32 = 1207, // WebAssemblyInstrFormats.td:59
1223 LOAD8_S_I64_A32_S = 1208, // WebAssemblyInstrFormats.td:61
1224 LOAD8_S_I64_A64 = 1209, // WebAssemblyInstrFormats.td:59
1225 LOAD8_S_I64_A64_S = 1210, // WebAssemblyInstrFormats.td:61
1226 LOAD8_U_I32_A32 = 1211, // WebAssemblyInstrFormats.td:59
1227 LOAD8_U_I32_A32_S = 1212, // WebAssemblyInstrFormats.td:61
1228 LOAD8_U_I32_A64 = 1213, // WebAssemblyInstrFormats.td:59
1229 LOAD8_U_I32_A64_S = 1214, // WebAssemblyInstrFormats.td:61
1230 LOAD8_U_I64_A32 = 1215, // WebAssemblyInstrFormats.td:59
1231 LOAD8_U_I64_A32_S = 1216, // WebAssemblyInstrFormats.td:61
1232 LOAD8_U_I64_A64 = 1217, // WebAssemblyInstrFormats.td:59
1233 LOAD8_U_I64_A64_S = 1218, // WebAssemblyInstrFormats.td:61
1234 LOAD_EXTEND_S_I16x8_A32 = 1219, // WebAssemblyInstrFormats.td:59
1235 LOAD_EXTEND_S_I16x8_A32_S = 1220, // WebAssemblyInstrFormats.td:61
1236 LOAD_EXTEND_S_I16x8_A64 = 1221, // WebAssemblyInstrFormats.td:59
1237 LOAD_EXTEND_S_I16x8_A64_S = 1222, // WebAssemblyInstrFormats.td:61
1238 LOAD_EXTEND_S_I32x4_A32 = 1223, // WebAssemblyInstrFormats.td:59
1239 LOAD_EXTEND_S_I32x4_A32_S = 1224, // WebAssemblyInstrFormats.td:61
1240 LOAD_EXTEND_S_I32x4_A64 = 1225, // WebAssemblyInstrFormats.td:59
1241 LOAD_EXTEND_S_I32x4_A64_S = 1226, // WebAssemblyInstrFormats.td:61
1242 LOAD_EXTEND_S_I64x2_A32 = 1227, // WebAssemblyInstrFormats.td:59
1243 LOAD_EXTEND_S_I64x2_A32_S = 1228, // WebAssemblyInstrFormats.td:61
1244 LOAD_EXTEND_S_I64x2_A64 = 1229, // WebAssemblyInstrFormats.td:59
1245 LOAD_EXTEND_S_I64x2_A64_S = 1230, // WebAssemblyInstrFormats.td:61
1246 LOAD_EXTEND_U_I16x8_A32 = 1231, // WebAssemblyInstrFormats.td:59
1247 LOAD_EXTEND_U_I16x8_A32_S = 1232, // WebAssemblyInstrFormats.td:61
1248 LOAD_EXTEND_U_I16x8_A64 = 1233, // WebAssemblyInstrFormats.td:59
1249 LOAD_EXTEND_U_I16x8_A64_S = 1234, // WebAssemblyInstrFormats.td:61
1250 LOAD_EXTEND_U_I32x4_A32 = 1235, // WebAssemblyInstrFormats.td:59
1251 LOAD_EXTEND_U_I32x4_A32_S = 1236, // WebAssemblyInstrFormats.td:61
1252 LOAD_EXTEND_U_I32x4_A64 = 1237, // WebAssemblyInstrFormats.td:59
1253 LOAD_EXTEND_U_I32x4_A64_S = 1238, // WebAssemblyInstrFormats.td:61
1254 LOAD_EXTEND_U_I64x2_A32 = 1239, // WebAssemblyInstrFormats.td:59
1255 LOAD_EXTEND_U_I64x2_A32_S = 1240, // WebAssemblyInstrFormats.td:61
1256 LOAD_EXTEND_U_I64x2_A64 = 1241, // WebAssemblyInstrFormats.td:59
1257 LOAD_EXTEND_U_I64x2_A64_S = 1242, // WebAssemblyInstrFormats.td:61
1258 LOAD_F16_F32_A32 = 1243, // WebAssemblyInstrFormats.td:59
1259 LOAD_F16_F32_A32_S = 1244, // WebAssemblyInstrFormats.td:61
1260 LOAD_F16_F32_A64 = 1245, // WebAssemblyInstrFormats.td:59
1261 LOAD_F16_F32_A64_S = 1246, // WebAssemblyInstrFormats.td:61
1262 LOAD_F32_A32 = 1247, // WebAssemblyInstrFormats.td:59
1263 LOAD_F32_A32_S = 1248, // WebAssemblyInstrFormats.td:61
1264 LOAD_F32_A64 = 1249, // WebAssemblyInstrFormats.td:59
1265 LOAD_F32_A64_S = 1250, // WebAssemblyInstrFormats.td:61
1266 LOAD_F64_A32 = 1251, // WebAssemblyInstrFormats.td:59
1267 LOAD_F64_A32_S = 1252, // WebAssemblyInstrFormats.td:61
1268 LOAD_F64_A64 = 1253, // WebAssemblyInstrFormats.td:59
1269 LOAD_F64_A64_S = 1254, // WebAssemblyInstrFormats.td:61
1270 LOAD_I32_A32 = 1255, // WebAssemblyInstrFormats.td:59
1271 LOAD_I32_A32_S = 1256, // WebAssemblyInstrFormats.td:61
1272 LOAD_I32_A64 = 1257, // WebAssemblyInstrFormats.td:59
1273 LOAD_I32_A64_S = 1258, // WebAssemblyInstrFormats.td:61
1274 LOAD_I64_A32 = 1259, // WebAssemblyInstrFormats.td:59
1275 LOAD_I64_A32_S = 1260, // WebAssemblyInstrFormats.td:61
1276 LOAD_I64_A64 = 1261, // WebAssemblyInstrFormats.td:59
1277 LOAD_I64_A64_S = 1262, // WebAssemblyInstrFormats.td:61
1278 LOAD_LANE_16_A32 = 1263, // WebAssemblyInstrFormats.td:59
1279 LOAD_LANE_16_A32_S = 1264, // WebAssemblyInstrFormats.td:61
1280 LOAD_LANE_16_A64 = 1265, // WebAssemblyInstrFormats.td:59
1281 LOAD_LANE_16_A64_S = 1266, // WebAssemblyInstrFormats.td:61
1282 LOAD_LANE_32_A32 = 1267, // WebAssemblyInstrFormats.td:59
1283 LOAD_LANE_32_A32_S = 1268, // WebAssemblyInstrFormats.td:61
1284 LOAD_LANE_32_A64 = 1269, // WebAssemblyInstrFormats.td:59
1285 LOAD_LANE_32_A64_S = 1270, // WebAssemblyInstrFormats.td:61
1286 LOAD_LANE_64_A32 = 1271, // WebAssemblyInstrFormats.td:59
1287 LOAD_LANE_64_A32_S = 1272, // WebAssemblyInstrFormats.td:61
1288 LOAD_LANE_64_A64 = 1273, // WebAssemblyInstrFormats.td:59
1289 LOAD_LANE_64_A64_S = 1274, // WebAssemblyInstrFormats.td:61
1290 LOAD_LANE_8_A32 = 1275, // WebAssemblyInstrFormats.td:59
1291 LOAD_LANE_8_A32_S = 1276, // WebAssemblyInstrFormats.td:61
1292 LOAD_LANE_8_A64 = 1277, // WebAssemblyInstrFormats.td:59
1293 LOAD_LANE_8_A64_S = 1278, // WebAssemblyInstrFormats.td:61
1294 LOAD_V128_A32 = 1279, // WebAssemblyInstrFormats.td:59
1295 LOAD_V128_A32_S = 1280, // WebAssemblyInstrFormats.td:61
1296 LOAD_V128_A64 = 1281, // WebAssemblyInstrFormats.td:59
1297 LOAD_V128_A64_S = 1282, // WebAssemblyInstrFormats.td:61
1298 LOAD_ZERO_32_A32 = 1283, // WebAssemblyInstrFormats.td:59
1299 LOAD_ZERO_32_A32_S = 1284, // WebAssemblyInstrFormats.td:61
1300 LOAD_ZERO_32_A64 = 1285, // WebAssemblyInstrFormats.td:59
1301 LOAD_ZERO_32_A64_S = 1286, // WebAssemblyInstrFormats.td:61
1302 LOAD_ZERO_64_A32 = 1287, // WebAssemblyInstrFormats.td:59
1303 LOAD_ZERO_64_A32_S = 1288, // WebAssemblyInstrFormats.td:61
1304 LOAD_ZERO_64_A64 = 1289, // WebAssemblyInstrFormats.td:59
1305 LOAD_ZERO_64_A64_S = 1290, // WebAssemblyInstrFormats.td:61
1306 LOCAL_GET_EXNREF = 1291, // WebAssemblyInstrFormats.td:59
1307 LOCAL_GET_EXNREF_S = 1292, // WebAssemblyInstrFormats.td:61
1308 LOCAL_GET_EXTERNREF = 1293, // WebAssemblyInstrFormats.td:59
1309 LOCAL_GET_EXTERNREF_S = 1294, // WebAssemblyInstrFormats.td:61
1310 LOCAL_GET_F32 = 1295, // WebAssemblyInstrFormats.td:59
1311 LOCAL_GET_F32_S = 1296, // WebAssemblyInstrFormats.td:61
1312 LOCAL_GET_F64 = 1297, // WebAssemblyInstrFormats.td:59
1313 LOCAL_GET_F64_S = 1298, // WebAssemblyInstrFormats.td:61
1314 LOCAL_GET_FUNCREF = 1299, // WebAssemblyInstrFormats.td:59
1315 LOCAL_GET_FUNCREF_S = 1300, // WebAssemblyInstrFormats.td:61
1316 LOCAL_GET_I32 = 1301, // WebAssemblyInstrFormats.td:59
1317 LOCAL_GET_I32_S = 1302, // WebAssemblyInstrFormats.td:61
1318 LOCAL_GET_I64 = 1303, // WebAssemblyInstrFormats.td:59
1319 LOCAL_GET_I64_S = 1304, // WebAssemblyInstrFormats.td:61
1320 LOCAL_GET_V128 = 1305, // WebAssemblyInstrFormats.td:59
1321 LOCAL_GET_V128_S = 1306, // WebAssemblyInstrFormats.td:61
1322 LOCAL_SET_EXNREF = 1307, // WebAssemblyInstrFormats.td:59
1323 LOCAL_SET_EXNREF_S = 1308, // WebAssemblyInstrFormats.td:61
1324 LOCAL_SET_EXTERNREF = 1309, // WebAssemblyInstrFormats.td:59
1325 LOCAL_SET_EXTERNREF_S = 1310, // WebAssemblyInstrFormats.td:61
1326 LOCAL_SET_F32 = 1311, // WebAssemblyInstrFormats.td:59
1327 LOCAL_SET_F32_S = 1312, // WebAssemblyInstrFormats.td:61
1328 LOCAL_SET_F64 = 1313, // WebAssemblyInstrFormats.td:59
1329 LOCAL_SET_F64_S = 1314, // WebAssemblyInstrFormats.td:61
1330 LOCAL_SET_FUNCREF = 1315, // WebAssemblyInstrFormats.td:59
1331 LOCAL_SET_FUNCREF_S = 1316, // WebAssemblyInstrFormats.td:61
1332 LOCAL_SET_I32 = 1317, // WebAssemblyInstrFormats.td:59
1333 LOCAL_SET_I32_S = 1318, // WebAssemblyInstrFormats.td:61
1334 LOCAL_SET_I64 = 1319, // WebAssemblyInstrFormats.td:59
1335 LOCAL_SET_I64_S = 1320, // WebAssemblyInstrFormats.td:61
1336 LOCAL_SET_V128 = 1321, // WebAssemblyInstrFormats.td:59
1337 LOCAL_SET_V128_S = 1322, // WebAssemblyInstrFormats.td:61
1338 LOCAL_TEE_EXNREF = 1323, // WebAssemblyInstrFormats.td:59
1339 LOCAL_TEE_EXNREF_S = 1324, // WebAssemblyInstrFormats.td:61
1340 LOCAL_TEE_EXTERNREF = 1325, // WebAssemblyInstrFormats.td:59
1341 LOCAL_TEE_EXTERNREF_S = 1326, // WebAssemblyInstrFormats.td:61
1342 LOCAL_TEE_F32 = 1327, // WebAssemblyInstrFormats.td:59
1343 LOCAL_TEE_F32_S = 1328, // WebAssemblyInstrFormats.td:61
1344 LOCAL_TEE_F64 = 1329, // WebAssemblyInstrFormats.td:59
1345 LOCAL_TEE_F64_S = 1330, // WebAssemblyInstrFormats.td:61
1346 LOCAL_TEE_FUNCREF = 1331, // WebAssemblyInstrFormats.td:59
1347 LOCAL_TEE_FUNCREF_S = 1332, // WebAssemblyInstrFormats.td:61
1348 LOCAL_TEE_I32 = 1333, // WebAssemblyInstrFormats.td:59
1349 LOCAL_TEE_I32_S = 1334, // WebAssemblyInstrFormats.td:61
1350 LOCAL_TEE_I64 = 1335, // WebAssemblyInstrFormats.td:59
1351 LOCAL_TEE_I64_S = 1336, // WebAssemblyInstrFormats.td:61
1352 LOCAL_TEE_V128 = 1337, // WebAssemblyInstrFormats.td:59
1353 LOCAL_TEE_V128_S = 1338, // WebAssemblyInstrFormats.td:61
1354 LOOP = 1339, // WebAssemblyInstrFormats.td:59
1355 LOOP_S = 1340, // WebAssemblyInstrFormats.td:61
1356 LT_F16x8 = 1341, // WebAssemblyInstrFormats.td:59
1357 LT_F16x8_S = 1342, // WebAssemblyInstrFormats.td:61
1358 LT_F32 = 1343, // WebAssemblyInstrFormats.td:59
1359 LT_F32_S = 1344, // WebAssemblyInstrFormats.td:61
1360 LT_F32x4 = 1345, // WebAssemblyInstrFormats.td:59
1361 LT_F32x4_S = 1346, // WebAssemblyInstrFormats.td:61
1362 LT_F64 = 1347, // WebAssemblyInstrFormats.td:59
1363 LT_F64_S = 1348, // WebAssemblyInstrFormats.td:61
1364 LT_F64x2 = 1349, // WebAssemblyInstrFormats.td:59
1365 LT_F64x2_S = 1350, // WebAssemblyInstrFormats.td:61
1366 LT_S_I16x8 = 1351, // WebAssemblyInstrFormats.td:59
1367 LT_S_I16x8_S = 1352, // WebAssemblyInstrFormats.td:61
1368 LT_S_I32 = 1353, // WebAssemblyInstrFormats.td:59
1369 LT_S_I32_S = 1354, // WebAssemblyInstrFormats.td:61
1370 LT_S_I32x4 = 1355, // WebAssemblyInstrFormats.td:59
1371 LT_S_I32x4_S = 1356, // WebAssemblyInstrFormats.td:61
1372 LT_S_I64 = 1357, // WebAssemblyInstrFormats.td:59
1373 LT_S_I64_S = 1358, // WebAssemblyInstrFormats.td:61
1374 LT_S_I64x2 = 1359, // WebAssemblyInstrFormats.td:59
1375 LT_S_I64x2_S = 1360, // WebAssemblyInstrFormats.td:61
1376 LT_S_I8x16 = 1361, // WebAssemblyInstrFormats.td:59
1377 LT_S_I8x16_S = 1362, // WebAssemblyInstrFormats.td:61
1378 LT_U_I16x8 = 1363, // WebAssemblyInstrFormats.td:59
1379 LT_U_I16x8_S = 1364, // WebAssemblyInstrFormats.td:61
1380 LT_U_I32 = 1365, // WebAssemblyInstrFormats.td:59
1381 LT_U_I32_S = 1366, // WebAssemblyInstrFormats.td:61
1382 LT_U_I32x4 = 1367, // WebAssemblyInstrFormats.td:59
1383 LT_U_I32x4_S = 1368, // WebAssemblyInstrFormats.td:61
1384 LT_U_I64 = 1369, // WebAssemblyInstrFormats.td:59
1385 LT_U_I64_S = 1370, // WebAssemblyInstrFormats.td:61
1386 LT_U_I8x16 = 1371, // WebAssemblyInstrFormats.td:59
1387 LT_U_I8x16_S = 1372, // WebAssemblyInstrFormats.td:61
1388 MADD_F16x8 = 1373, // WebAssemblyInstrFormats.td:59
1389 MADD_F16x8_S = 1374, // WebAssemblyInstrFormats.td:61
1390 MADD_F32x4 = 1375, // WebAssemblyInstrFormats.td:59
1391 MADD_F32x4_S = 1376, // WebAssemblyInstrFormats.td:61
1392 MADD_F64x2 = 1377, // WebAssemblyInstrFormats.td:59
1393 MADD_F64x2_S = 1378, // WebAssemblyInstrFormats.td:61
1394 MAX_F16x8 = 1379, // WebAssemblyInstrFormats.td:59
1395 MAX_F16x8_S = 1380, // WebAssemblyInstrFormats.td:61
1396 MAX_F32 = 1381, // WebAssemblyInstrFormats.td:59
1397 MAX_F32_S = 1382, // WebAssemblyInstrFormats.td:61
1398 MAX_F32x4 = 1383, // WebAssemblyInstrFormats.td:59
1399 MAX_F32x4_S = 1384, // WebAssemblyInstrFormats.td:61
1400 MAX_F64 = 1385, // WebAssemblyInstrFormats.td:59
1401 MAX_F64_S = 1386, // WebAssemblyInstrFormats.td:61
1402 MAX_F64x2 = 1387, // WebAssemblyInstrFormats.td:59
1403 MAX_F64x2_S = 1388, // WebAssemblyInstrFormats.td:61
1404 MAX_S_I16x8 = 1389, // WebAssemblyInstrFormats.td:59
1405 MAX_S_I16x8_S = 1390, // WebAssemblyInstrFormats.td:61
1406 MAX_S_I32x4 = 1391, // WebAssemblyInstrFormats.td:59
1407 MAX_S_I32x4_S = 1392, // WebAssemblyInstrFormats.td:61
1408 MAX_S_I8x16 = 1393, // WebAssemblyInstrFormats.td:59
1409 MAX_S_I8x16_S = 1394, // WebAssemblyInstrFormats.td:61
1410 MAX_U_I16x8 = 1395, // WebAssemblyInstrFormats.td:59
1411 MAX_U_I16x8_S = 1396, // WebAssemblyInstrFormats.td:61
1412 MAX_U_I32x4 = 1397, // WebAssemblyInstrFormats.td:59
1413 MAX_U_I32x4_S = 1398, // WebAssemblyInstrFormats.td:61
1414 MAX_U_I8x16 = 1399, // WebAssemblyInstrFormats.td:59
1415 MAX_U_I8x16_S = 1400, // WebAssemblyInstrFormats.td:61
1416 MEMCPY_A32 = 1401, // WebAssemblyInstrFormats.td:59
1417 MEMCPY_A32_S = 1402, // WebAssemblyInstrFormats.td:61
1418 MEMCPY_A64 = 1403, // WebAssemblyInstrFormats.td:59
1419 MEMCPY_A64_S = 1404, // WebAssemblyInstrFormats.td:61
1420 MEMORY_ATOMIC_NOTIFY_A32 = 1405, // WebAssemblyInstrFormats.td:59
1421 MEMORY_ATOMIC_NOTIFY_A32_S = 1406, // WebAssemblyInstrFormats.td:61
1422 MEMORY_ATOMIC_NOTIFY_A64 = 1407, // WebAssemblyInstrFormats.td:59
1423 MEMORY_ATOMIC_NOTIFY_A64_S = 1408, // WebAssemblyInstrFormats.td:61
1424 MEMORY_ATOMIC_WAIT32_A32 = 1409, // WebAssemblyInstrFormats.td:59
1425 MEMORY_ATOMIC_WAIT32_A32_S = 1410, // WebAssemblyInstrFormats.td:61
1426 MEMORY_ATOMIC_WAIT32_A64 = 1411, // WebAssemblyInstrFormats.td:59
1427 MEMORY_ATOMIC_WAIT32_A64_S = 1412, // WebAssemblyInstrFormats.td:61
1428 MEMORY_ATOMIC_WAIT64_A32 = 1413, // WebAssemblyInstrFormats.td:59
1429 MEMORY_ATOMIC_WAIT64_A32_S = 1414, // WebAssemblyInstrFormats.td:61
1430 MEMORY_ATOMIC_WAIT64_A64 = 1415, // WebAssemblyInstrFormats.td:59
1431 MEMORY_ATOMIC_WAIT64_A64_S = 1416, // WebAssemblyInstrFormats.td:61
1432 MEMORY_COPY_A32 = 1417, // WebAssemblyInstrFormats.td:59
1433 MEMORY_COPY_A32_S = 1418, // WebAssemblyInstrFormats.td:61
1434 MEMORY_COPY_A64 = 1419, // WebAssemblyInstrFormats.td:59
1435 MEMORY_COPY_A64_S = 1420, // WebAssemblyInstrFormats.td:61
1436 MEMORY_FILL_A32 = 1421, // WebAssemblyInstrFormats.td:59
1437 MEMORY_FILL_A32_S = 1422, // WebAssemblyInstrFormats.td:61
1438 MEMORY_FILL_A64 = 1423, // WebAssemblyInstrFormats.td:59
1439 MEMORY_FILL_A64_S = 1424, // WebAssemblyInstrFormats.td:61
1440 MEMORY_INIT_A32 = 1425, // WebAssemblyInstrFormats.td:59
1441 MEMORY_INIT_A32_S = 1426, // WebAssemblyInstrFormats.td:61
1442 MEMORY_INIT_A64 = 1427, // WebAssemblyInstrFormats.td:59
1443 MEMORY_INIT_A64_S = 1428, // WebAssemblyInstrFormats.td:61
1444 MEMSET_A32 = 1429, // WebAssemblyInstrFormats.td:59
1445 MEMSET_A32_S = 1430, // WebAssemblyInstrFormats.td:61
1446 MEMSET_A64 = 1431, // WebAssemblyInstrFormats.td:59
1447 MEMSET_A64_S = 1432, // WebAssemblyInstrFormats.td:61
1448 MIN_F16x8 = 1433, // WebAssemblyInstrFormats.td:59
1449 MIN_F16x8_S = 1434, // WebAssemblyInstrFormats.td:61
1450 MIN_F32 = 1435, // WebAssemblyInstrFormats.td:59
1451 MIN_F32_S = 1436, // WebAssemblyInstrFormats.td:61
1452 MIN_F32x4 = 1437, // WebAssemblyInstrFormats.td:59
1453 MIN_F32x4_S = 1438, // WebAssemblyInstrFormats.td:61
1454 MIN_F64 = 1439, // WebAssemblyInstrFormats.td:59
1455 MIN_F64_S = 1440, // WebAssemblyInstrFormats.td:61
1456 MIN_F64x2 = 1441, // WebAssemblyInstrFormats.td:59
1457 MIN_F64x2_S = 1442, // WebAssemblyInstrFormats.td:61
1458 MIN_S_I16x8 = 1443, // WebAssemblyInstrFormats.td:59
1459 MIN_S_I16x8_S = 1444, // WebAssemblyInstrFormats.td:61
1460 MIN_S_I32x4 = 1445, // WebAssemblyInstrFormats.td:59
1461 MIN_S_I32x4_S = 1446, // WebAssemblyInstrFormats.td:61
1462 MIN_S_I8x16 = 1447, // WebAssemblyInstrFormats.td:59
1463 MIN_S_I8x16_S = 1448, // WebAssemblyInstrFormats.td:61
1464 MIN_U_I16x8 = 1449, // WebAssemblyInstrFormats.td:59
1465 MIN_U_I16x8_S = 1450, // WebAssemblyInstrFormats.td:61
1466 MIN_U_I32x4 = 1451, // WebAssemblyInstrFormats.td:59
1467 MIN_U_I32x4_S = 1452, // WebAssemblyInstrFormats.td:61
1468 MIN_U_I8x16 = 1453, // WebAssemblyInstrFormats.td:59
1469 MIN_U_I8x16_S = 1454, // WebAssemblyInstrFormats.td:61
1470 MUL_F16x8 = 1455, // WebAssemblyInstrFormats.td:59
1471 MUL_F16x8_S = 1456, // WebAssemblyInstrFormats.td:61
1472 MUL_F32 = 1457, // WebAssemblyInstrFormats.td:59
1473 MUL_F32_S = 1458, // WebAssemblyInstrFormats.td:61
1474 MUL_F32x4 = 1459, // WebAssemblyInstrFormats.td:59
1475 MUL_F32x4_S = 1460, // WebAssemblyInstrFormats.td:61
1476 MUL_F64 = 1461, // WebAssemblyInstrFormats.td:59
1477 MUL_F64_S = 1462, // WebAssemblyInstrFormats.td:61
1478 MUL_F64x2 = 1463, // WebAssemblyInstrFormats.td:59
1479 MUL_F64x2_S = 1464, // WebAssemblyInstrFormats.td:61
1480 MUL_I16x8 = 1465, // WebAssemblyInstrFormats.td:59
1481 MUL_I16x8_S = 1466, // WebAssemblyInstrFormats.td:61
1482 MUL_I32 = 1467, // WebAssemblyInstrFormats.td:59
1483 MUL_I32_S = 1468, // WebAssemblyInstrFormats.td:61
1484 MUL_I32x4 = 1469, // WebAssemblyInstrFormats.td:59
1485 MUL_I32x4_S = 1470, // WebAssemblyInstrFormats.td:61
1486 MUL_I64 = 1471, // WebAssemblyInstrFormats.td:59
1487 MUL_I64_S = 1472, // WebAssemblyInstrFormats.td:61
1488 MUL_I64x2 = 1473, // WebAssemblyInstrFormats.td:59
1489 MUL_I64x2_S = 1474, // WebAssemblyInstrFormats.td:61
1490 NARROW_S_I16x8 = 1475, // WebAssemblyInstrFormats.td:59
1491 NARROW_S_I16x8_S = 1476, // WebAssemblyInstrFormats.td:61
1492 NARROW_S_I8x16 = 1477, // WebAssemblyInstrFormats.td:59
1493 NARROW_S_I8x16_S = 1478, // WebAssemblyInstrFormats.td:61
1494 NARROW_U_I16x8 = 1479, // WebAssemblyInstrFormats.td:59
1495 NARROW_U_I16x8_S = 1480, // WebAssemblyInstrFormats.td:61
1496 NARROW_U_I8x16 = 1481, // WebAssemblyInstrFormats.td:59
1497 NARROW_U_I8x16_S = 1482, // WebAssemblyInstrFormats.td:61
1498 NEAREST_F16x8 = 1483, // WebAssemblyInstrFormats.td:59
1499 NEAREST_F16x8_S = 1484, // WebAssemblyInstrFormats.td:61
1500 NEAREST_F32 = 1485, // WebAssemblyInstrFormats.td:59
1501 NEAREST_F32_S = 1486, // WebAssemblyInstrFormats.td:61
1502 NEAREST_F32x4 = 1487, // WebAssemblyInstrFormats.td:59
1503 NEAREST_F32x4_S = 1488, // WebAssemblyInstrFormats.td:61
1504 NEAREST_F64 = 1489, // WebAssemblyInstrFormats.td:59
1505 NEAREST_F64_S = 1490, // WebAssemblyInstrFormats.td:61
1506 NEAREST_F64x2 = 1491, // WebAssemblyInstrFormats.td:59
1507 NEAREST_F64x2_S = 1492, // WebAssemblyInstrFormats.td:61
1508 NEG_F16x8 = 1493, // WebAssemblyInstrFormats.td:59
1509 NEG_F16x8_S = 1494, // WebAssemblyInstrFormats.td:61
1510 NEG_F32 = 1495, // WebAssemblyInstrFormats.td:59
1511 NEG_F32_S = 1496, // WebAssemblyInstrFormats.td:61
1512 NEG_F32x4 = 1497, // WebAssemblyInstrFormats.td:59
1513 NEG_F32x4_S = 1498, // WebAssemblyInstrFormats.td:61
1514 NEG_F64 = 1499, // WebAssemblyInstrFormats.td:59
1515 NEG_F64_S = 1500, // WebAssemblyInstrFormats.td:61
1516 NEG_F64x2 = 1501, // WebAssemblyInstrFormats.td:59
1517 NEG_F64x2_S = 1502, // WebAssemblyInstrFormats.td:61
1518 NEG_I16x8 = 1503, // WebAssemblyInstrFormats.td:59
1519 NEG_I16x8_S = 1504, // WebAssemblyInstrFormats.td:61
1520 NEG_I32x4 = 1505, // WebAssemblyInstrFormats.td:59
1521 NEG_I32x4_S = 1506, // WebAssemblyInstrFormats.td:61
1522 NEG_I64x2 = 1507, // WebAssemblyInstrFormats.td:59
1523 NEG_I64x2_S = 1508, // WebAssemblyInstrFormats.td:61
1524 NEG_I8x16 = 1509, // WebAssemblyInstrFormats.td:59
1525 NEG_I8x16_S = 1510, // WebAssemblyInstrFormats.td:61
1526 NE_F16x8 = 1511, // WebAssemblyInstrFormats.td:59
1527 NE_F16x8_S = 1512, // WebAssemblyInstrFormats.td:61
1528 NE_F32 = 1513, // WebAssemblyInstrFormats.td:59
1529 NE_F32_S = 1514, // WebAssemblyInstrFormats.td:61
1530 NE_F32x4 = 1515, // WebAssemblyInstrFormats.td:59
1531 NE_F32x4_S = 1516, // WebAssemblyInstrFormats.td:61
1532 NE_F64 = 1517, // WebAssemblyInstrFormats.td:59
1533 NE_F64_S = 1518, // WebAssemblyInstrFormats.td:61
1534 NE_F64x2 = 1519, // WebAssemblyInstrFormats.td:59
1535 NE_F64x2_S = 1520, // WebAssemblyInstrFormats.td:61
1536 NE_I16x8 = 1521, // WebAssemblyInstrFormats.td:59
1537 NE_I16x8_S = 1522, // WebAssemblyInstrFormats.td:61
1538 NE_I32 = 1523, // WebAssemblyInstrFormats.td:59
1539 NE_I32_S = 1524, // WebAssemblyInstrFormats.td:61
1540 NE_I32x4 = 1525, // WebAssemblyInstrFormats.td:59
1541 NE_I32x4_S = 1526, // WebAssemblyInstrFormats.td:61
1542 NE_I64 = 1527, // WebAssemblyInstrFormats.td:59
1543 NE_I64_S = 1528, // WebAssemblyInstrFormats.td:61
1544 NE_I64x2 = 1529, // WebAssemblyInstrFormats.td:59
1545 NE_I64x2_S = 1530, // WebAssemblyInstrFormats.td:61
1546 NE_I8x16 = 1531, // WebAssemblyInstrFormats.td:59
1547 NE_I8x16_S = 1532, // WebAssemblyInstrFormats.td:61
1548 NMADD_F16x8 = 1533, // WebAssemblyInstrFormats.td:59
1549 NMADD_F16x8_S = 1534, // WebAssemblyInstrFormats.td:61
1550 NMADD_F32x4 = 1535, // WebAssemblyInstrFormats.td:59
1551 NMADD_F32x4_S = 1536, // WebAssemblyInstrFormats.td:61
1552 NMADD_F64x2 = 1537, // WebAssemblyInstrFormats.td:59
1553 NMADD_F64x2_S = 1538, // WebAssemblyInstrFormats.td:61
1554 NOP = 1539, // WebAssemblyInstrFormats.td:59
1555 NOP_S = 1540, // WebAssemblyInstrFormats.td:61
1556 NOT = 1541, // WebAssemblyInstrFormats.td:59
1557 NOT_S = 1542, // WebAssemblyInstrFormats.td:61
1558 OR = 1543, // WebAssemblyInstrFormats.td:59
1559 OR_I32 = 1544, // WebAssemblyInstrFormats.td:59
1560 OR_I32_S = 1545, // WebAssemblyInstrFormats.td:61
1561 OR_I64 = 1546, // WebAssemblyInstrFormats.td:59
1562 OR_I64_S = 1547, // WebAssemblyInstrFormats.td:61
1563 OR_S = 1548, // WebAssemblyInstrFormats.td:61
1564 PMAX_F16x8 = 1549, // WebAssemblyInstrFormats.td:59
1565 PMAX_F16x8_S = 1550, // WebAssemblyInstrFormats.td:61
1566 PMAX_F32x4 = 1551, // WebAssemblyInstrFormats.td:59
1567 PMAX_F32x4_S = 1552, // WebAssemblyInstrFormats.td:61
1568 PMAX_F64x2 = 1553, // WebAssemblyInstrFormats.td:59
1569 PMAX_F64x2_S = 1554, // WebAssemblyInstrFormats.td:61
1570 PMIN_F16x8 = 1555, // WebAssemblyInstrFormats.td:59
1571 PMIN_F16x8_S = 1556, // WebAssemblyInstrFormats.td:61
1572 PMIN_F32x4 = 1557, // WebAssemblyInstrFormats.td:59
1573 PMIN_F32x4_S = 1558, // WebAssemblyInstrFormats.td:61
1574 PMIN_F64x2 = 1559, // WebAssemblyInstrFormats.td:59
1575 PMIN_F64x2_S = 1560, // WebAssemblyInstrFormats.td:61
1576 POPCNT_I32 = 1561, // WebAssemblyInstrFormats.td:59
1577 POPCNT_I32_S = 1562, // WebAssemblyInstrFormats.td:61
1578 POPCNT_I64 = 1563, // WebAssemblyInstrFormats.td:59
1579 POPCNT_I64_S = 1564, // WebAssemblyInstrFormats.td:61
1580 POPCNT_I8x16 = 1565, // WebAssemblyInstrFormats.td:59
1581 POPCNT_I8x16_S = 1566, // WebAssemblyInstrFormats.td:61
1582 Q15MULR_SAT_S_I16x8 = 1567, // WebAssemblyInstrFormats.td:59
1583 Q15MULR_SAT_S_I16x8_S = 1568, // WebAssemblyInstrFormats.td:61
1584 REF_FUNC = 1569, // WebAssemblyInstrFormats.td:59
1585 REF_FUNC_S = 1570, // WebAssemblyInstrFormats.td:61
1586 REF_IS_NULL_EXNREF = 1571, // WebAssemblyInstrFormats.td:59
1587 REF_IS_NULL_EXNREF_S = 1572, // WebAssemblyInstrFormats.td:61
1588 REF_IS_NULL_EXTERNREF = 1573, // WebAssemblyInstrFormats.td:59
1589 REF_IS_NULL_EXTERNREF_S = 1574, // WebAssemblyInstrFormats.td:61
1590 REF_IS_NULL_FUNCREF = 1575, // WebAssemblyInstrFormats.td:59
1591 REF_IS_NULL_FUNCREF_S = 1576, // WebAssemblyInstrFormats.td:61
1592 REF_NULL_EXNREF = 1577, // WebAssemblyInstrFormats.td:59
1593 REF_NULL_EXNREF_S = 1578, // WebAssemblyInstrFormats.td:61
1594 REF_NULL_EXTERNREF = 1579, // WebAssemblyInstrFormats.td:59
1595 REF_NULL_EXTERNREF_S = 1580, // WebAssemblyInstrFormats.td:61
1596 REF_NULL_FUNCREF = 1581, // WebAssemblyInstrFormats.td:59
1597 REF_NULL_FUNCREF_S = 1582, // WebAssemblyInstrFormats.td:61
1598 REF_TEST_FUNCREF = 1583, // WebAssemblyInstrFormats.td:59
1599 REF_TEST_FUNCREF_S = 1584, // WebAssemblyInstrFormats.td:61
1600 RELAXED_DOT = 1585, // WebAssemblyInstrFormats.td:59
1601 RELAXED_DOT_ADD = 1586, // WebAssemblyInstrFormats.td:59
1602 RELAXED_DOT_ADD_S = 1587, // WebAssemblyInstrFormats.td:61
1603 RELAXED_DOT_BFLOAT = 1588, // WebAssemblyInstrFormats.td:59
1604 RELAXED_DOT_BFLOAT_S = 1589, // WebAssemblyInstrFormats.td:61
1605 RELAXED_DOT_S = 1590, // WebAssemblyInstrFormats.td:61
1606 RELAXED_Q15MULR_S_I16x8 = 1591, // WebAssemblyInstrFormats.td:59
1607 RELAXED_Q15MULR_S_I16x8_S = 1592, // WebAssemblyInstrFormats.td:61
1608 RELAXED_SWIZZLE = 1593, // WebAssemblyInstrFormats.td:59
1609 RELAXED_SWIZZLE_S = 1594, // WebAssemblyInstrFormats.td:61
1610 REM_S_I32 = 1595, // WebAssemblyInstrFormats.td:59
1611 REM_S_I32_S = 1596, // WebAssemblyInstrFormats.td:61
1612 REM_S_I64 = 1597, // WebAssemblyInstrFormats.td:59
1613 REM_S_I64_S = 1598, // WebAssemblyInstrFormats.td:61
1614 REM_U_I32 = 1599, // WebAssemblyInstrFormats.td:59
1615 REM_U_I32_S = 1600, // WebAssemblyInstrFormats.td:61
1616 REM_U_I64 = 1601, // WebAssemblyInstrFormats.td:59
1617 REM_U_I64_S = 1602, // WebAssemblyInstrFormats.td:61
1618 REPLACE_LANE_F16x8 = 1603, // WebAssemblyInstrFormats.td:59
1619 REPLACE_LANE_F16x8_S = 1604, // WebAssemblyInstrFormats.td:61
1620 REPLACE_LANE_F32x4 = 1605, // WebAssemblyInstrFormats.td:59
1621 REPLACE_LANE_F32x4_S = 1606, // WebAssemblyInstrFormats.td:61
1622 REPLACE_LANE_F64x2 = 1607, // WebAssemblyInstrFormats.td:59
1623 REPLACE_LANE_F64x2_S = 1608, // WebAssemblyInstrFormats.td:61
1624 REPLACE_LANE_I16x8 = 1609, // WebAssemblyInstrFormats.td:59
1625 REPLACE_LANE_I16x8_S = 1610, // WebAssemblyInstrFormats.td:61
1626 REPLACE_LANE_I32x4 = 1611, // WebAssemblyInstrFormats.td:59
1627 REPLACE_LANE_I32x4_S = 1612, // WebAssemblyInstrFormats.td:61
1628 REPLACE_LANE_I64x2 = 1613, // WebAssemblyInstrFormats.td:59
1629 REPLACE_LANE_I64x2_S = 1614, // WebAssemblyInstrFormats.td:61
1630 REPLACE_LANE_I8x16 = 1615, // WebAssemblyInstrFormats.td:59
1631 REPLACE_LANE_I8x16_S = 1616, // WebAssemblyInstrFormats.td:61
1632 RETHROW = 1617, // WebAssemblyInstrFormats.td:59
1633 RETHROW_S = 1618, // WebAssemblyInstrFormats.td:61
1634 RETURN = 1619, // WebAssemblyInstrFormats.td:59
1635 RETURN_S = 1620, // WebAssemblyInstrFormats.td:61
1636 RET_CALL = 1621, // WebAssemblyInstrFormats.td:59
1637 RET_CALL_INDIRECT = 1622, // WebAssemblyInstrFormats.td:59
1638 RET_CALL_INDIRECT_S = 1623, // WebAssemblyInstrFormats.td:61
1639 RET_CALL_S = 1624, // WebAssemblyInstrFormats.td:61
1640 ROTL_I32 = 1625, // WebAssemblyInstrFormats.td:59
1641 ROTL_I32_S = 1626, // WebAssemblyInstrFormats.td:61
1642 ROTL_I64 = 1627, // WebAssemblyInstrFormats.td:59
1643 ROTL_I64_S = 1628, // WebAssemblyInstrFormats.td:61
1644 ROTR_I32 = 1629, // WebAssemblyInstrFormats.td:59
1645 ROTR_I32_S = 1630, // WebAssemblyInstrFormats.td:61
1646 ROTR_I64 = 1631, // WebAssemblyInstrFormats.td:59
1647 ROTR_I64_S = 1632, // WebAssemblyInstrFormats.td:61
1648 SELECT_EXNREF = 1633, // WebAssemblyInstrFormats.td:59
1649 SELECT_EXNREF_S = 1634, // WebAssemblyInstrFormats.td:61
1650 SELECT_EXTERNREF = 1635, // WebAssemblyInstrFormats.td:59
1651 SELECT_EXTERNREF_S = 1636, // WebAssemblyInstrFormats.td:61
1652 SELECT_F32 = 1637, // WebAssemblyInstrFormats.td:59
1653 SELECT_F32_S = 1638, // WebAssemblyInstrFormats.td:61
1654 SELECT_F64 = 1639, // WebAssemblyInstrFormats.td:59
1655 SELECT_F64_S = 1640, // WebAssemblyInstrFormats.td:61
1656 SELECT_FUNCREF = 1641, // WebAssemblyInstrFormats.td:59
1657 SELECT_FUNCREF_S = 1642, // WebAssemblyInstrFormats.td:61
1658 SELECT_I32 = 1643, // WebAssemblyInstrFormats.td:59
1659 SELECT_I32_S = 1644, // WebAssemblyInstrFormats.td:61
1660 SELECT_I64 = 1645, // WebAssemblyInstrFormats.td:59
1661 SELECT_I64_S = 1646, // WebAssemblyInstrFormats.td:61
1662 SELECT_V128 = 1647, // WebAssemblyInstrFormats.td:59
1663 SELECT_V128_S = 1648, // WebAssemblyInstrFormats.td:61
1664 SHL_I16x8 = 1649, // WebAssemblyInstrFormats.td:59
1665 SHL_I16x8_S = 1650, // WebAssemblyInstrFormats.td:61
1666 SHL_I32 = 1651, // WebAssemblyInstrFormats.td:59
1667 SHL_I32_S = 1652, // WebAssemblyInstrFormats.td:61
1668 SHL_I32x4 = 1653, // WebAssemblyInstrFormats.td:59
1669 SHL_I32x4_S = 1654, // WebAssemblyInstrFormats.td:61
1670 SHL_I64 = 1655, // WebAssemblyInstrFormats.td:59
1671 SHL_I64_S = 1656, // WebAssemblyInstrFormats.td:61
1672 SHL_I64x2 = 1657, // WebAssemblyInstrFormats.td:59
1673 SHL_I64x2_S = 1658, // WebAssemblyInstrFormats.td:61
1674 SHL_I8x16 = 1659, // WebAssemblyInstrFormats.td:59
1675 SHL_I8x16_S = 1660, // WebAssemblyInstrFormats.td:61
1676 SHR_S_I16x8 = 1661, // WebAssemblyInstrFormats.td:59
1677 SHR_S_I16x8_S = 1662, // WebAssemblyInstrFormats.td:61
1678 SHR_S_I32 = 1663, // WebAssemblyInstrFormats.td:59
1679 SHR_S_I32_S = 1664, // WebAssemblyInstrFormats.td:61
1680 SHR_S_I32x4 = 1665, // WebAssemblyInstrFormats.td:59
1681 SHR_S_I32x4_S = 1666, // WebAssemblyInstrFormats.td:61
1682 SHR_S_I64 = 1667, // WebAssemblyInstrFormats.td:59
1683 SHR_S_I64_S = 1668, // WebAssemblyInstrFormats.td:61
1684 SHR_S_I64x2 = 1669, // WebAssemblyInstrFormats.td:59
1685 SHR_S_I64x2_S = 1670, // WebAssemblyInstrFormats.td:61
1686 SHR_S_I8x16 = 1671, // WebAssemblyInstrFormats.td:59
1687 SHR_S_I8x16_S = 1672, // WebAssemblyInstrFormats.td:61
1688 SHR_U_I16x8 = 1673, // WebAssemblyInstrFormats.td:59
1689 SHR_U_I16x8_S = 1674, // WebAssemblyInstrFormats.td:61
1690 SHR_U_I32 = 1675, // WebAssemblyInstrFormats.td:59
1691 SHR_U_I32_S = 1676, // WebAssemblyInstrFormats.td:61
1692 SHR_U_I32x4 = 1677, // WebAssemblyInstrFormats.td:59
1693 SHR_U_I32x4_S = 1678, // WebAssemblyInstrFormats.td:61
1694 SHR_U_I64 = 1679, // WebAssemblyInstrFormats.td:59
1695 SHR_U_I64_S = 1680, // WebAssemblyInstrFormats.td:61
1696 SHR_U_I64x2 = 1681, // WebAssemblyInstrFormats.td:59
1697 SHR_U_I64x2_S = 1682, // WebAssemblyInstrFormats.td:61
1698 SHR_U_I8x16 = 1683, // WebAssemblyInstrFormats.td:59
1699 SHR_U_I8x16_S = 1684, // WebAssemblyInstrFormats.td:61
1700 SHUFFLE = 1685, // WebAssemblyInstrFormats.td:59
1701 SHUFFLE_S = 1686, // WebAssemblyInstrFormats.td:61
1702 SIMD_RELAXED_FMAX_F32x4 = 1687, // WebAssemblyInstrFormats.td:59
1703 SIMD_RELAXED_FMAX_F32x4_S = 1688, // WebAssemblyInstrFormats.td:61
1704 SIMD_RELAXED_FMAX_F64x2 = 1689, // WebAssemblyInstrFormats.td:59
1705 SIMD_RELAXED_FMAX_F64x2_S = 1690, // WebAssemblyInstrFormats.td:61
1706 SIMD_RELAXED_FMIN_F32x4 = 1691, // WebAssemblyInstrFormats.td:59
1707 SIMD_RELAXED_FMIN_F32x4_S = 1692, // WebAssemblyInstrFormats.td:61
1708 SIMD_RELAXED_FMIN_F64x2 = 1693, // WebAssemblyInstrFormats.td:59
1709 SIMD_RELAXED_FMIN_F64x2_S = 1694, // WebAssemblyInstrFormats.td:61
1710 SPLAT_F16x8 = 1695, // WebAssemblyInstrFormats.td:59
1711 SPLAT_F16x8_S = 1696, // WebAssemblyInstrFormats.td:61
1712 SPLAT_F32x4 = 1697, // WebAssemblyInstrFormats.td:59
1713 SPLAT_F32x4_S = 1698, // WebAssemblyInstrFormats.td:61
1714 SPLAT_F64x2 = 1699, // WebAssemblyInstrFormats.td:59
1715 SPLAT_F64x2_S = 1700, // WebAssemblyInstrFormats.td:61
1716 SPLAT_I16x8 = 1701, // WebAssemblyInstrFormats.td:59
1717 SPLAT_I16x8_S = 1702, // WebAssemblyInstrFormats.td:61
1718 SPLAT_I32x4 = 1703, // WebAssemblyInstrFormats.td:59
1719 SPLAT_I32x4_S = 1704, // WebAssemblyInstrFormats.td:61
1720 SPLAT_I64x2 = 1705, // WebAssemblyInstrFormats.td:59
1721 SPLAT_I64x2_S = 1706, // WebAssemblyInstrFormats.td:61
1722 SPLAT_I8x16 = 1707, // WebAssemblyInstrFormats.td:59
1723 SPLAT_I8x16_S = 1708, // WebAssemblyInstrFormats.td:61
1724 SQRT_F16x8 = 1709, // WebAssemblyInstrFormats.td:59
1725 SQRT_F16x8_S = 1710, // WebAssemblyInstrFormats.td:61
1726 SQRT_F32 = 1711, // WebAssemblyInstrFormats.td:59
1727 SQRT_F32_S = 1712, // WebAssemblyInstrFormats.td:61
1728 SQRT_F32x4 = 1713, // WebAssemblyInstrFormats.td:59
1729 SQRT_F32x4_S = 1714, // WebAssemblyInstrFormats.td:61
1730 SQRT_F64 = 1715, // WebAssemblyInstrFormats.td:59
1731 SQRT_F64_S = 1716, // WebAssemblyInstrFormats.td:61
1732 SQRT_F64x2 = 1717, // WebAssemblyInstrFormats.td:59
1733 SQRT_F64x2_S = 1718, // WebAssemblyInstrFormats.td:61
1734 STORE16_I32_A32 = 1719, // WebAssemblyInstrFormats.td:59
1735 STORE16_I32_A32_S = 1720, // WebAssemblyInstrFormats.td:61
1736 STORE16_I32_A64 = 1721, // WebAssemblyInstrFormats.td:59
1737 STORE16_I32_A64_S = 1722, // WebAssemblyInstrFormats.td:61
1738 STORE16_I64_A32 = 1723, // WebAssemblyInstrFormats.td:59
1739 STORE16_I64_A32_S = 1724, // WebAssemblyInstrFormats.td:61
1740 STORE16_I64_A64 = 1725, // WebAssemblyInstrFormats.td:59
1741 STORE16_I64_A64_S = 1726, // WebAssemblyInstrFormats.td:61
1742 STORE32_I64_A32 = 1727, // WebAssemblyInstrFormats.td:59
1743 STORE32_I64_A32_S = 1728, // WebAssemblyInstrFormats.td:61
1744 STORE32_I64_A64 = 1729, // WebAssemblyInstrFormats.td:59
1745 STORE32_I64_A64_S = 1730, // WebAssemblyInstrFormats.td:61
1746 STORE8_I32_A32 = 1731, // WebAssemblyInstrFormats.td:59
1747 STORE8_I32_A32_S = 1732, // WebAssemblyInstrFormats.td:61
1748 STORE8_I32_A64 = 1733, // WebAssemblyInstrFormats.td:59
1749 STORE8_I32_A64_S = 1734, // WebAssemblyInstrFormats.td:61
1750 STORE8_I64_A32 = 1735, // WebAssemblyInstrFormats.td:59
1751 STORE8_I64_A32_S = 1736, // WebAssemblyInstrFormats.td:61
1752 STORE8_I64_A64 = 1737, // WebAssemblyInstrFormats.td:59
1753 STORE8_I64_A64_S = 1738, // WebAssemblyInstrFormats.td:61
1754 STORE_F16_F32_A32 = 1739, // WebAssemblyInstrFormats.td:59
1755 STORE_F16_F32_A32_S = 1740, // WebAssemblyInstrFormats.td:61
1756 STORE_F16_F32_A64 = 1741, // WebAssemblyInstrFormats.td:59
1757 STORE_F16_F32_A64_S = 1742, // WebAssemblyInstrFormats.td:61
1758 STORE_F32_A32 = 1743, // WebAssemblyInstrFormats.td:59
1759 STORE_F32_A32_S = 1744, // WebAssemblyInstrFormats.td:61
1760 STORE_F32_A64 = 1745, // WebAssemblyInstrFormats.td:59
1761 STORE_F32_A64_S = 1746, // WebAssemblyInstrFormats.td:61
1762 STORE_F64_A32 = 1747, // WebAssemblyInstrFormats.td:59
1763 STORE_F64_A32_S = 1748, // WebAssemblyInstrFormats.td:61
1764 STORE_F64_A64 = 1749, // WebAssemblyInstrFormats.td:59
1765 STORE_F64_A64_S = 1750, // WebAssemblyInstrFormats.td:61
1766 STORE_I32_A32 = 1751, // WebAssemblyInstrFormats.td:59
1767 STORE_I32_A32_S = 1752, // WebAssemblyInstrFormats.td:61
1768 STORE_I32_A64 = 1753, // WebAssemblyInstrFormats.td:59
1769 STORE_I32_A64_S = 1754, // WebAssemblyInstrFormats.td:61
1770 STORE_I64_A32 = 1755, // WebAssemblyInstrFormats.td:59
1771 STORE_I64_A32_S = 1756, // WebAssemblyInstrFormats.td:61
1772 STORE_I64_A64 = 1757, // WebAssemblyInstrFormats.td:59
1773 STORE_I64_A64_S = 1758, // WebAssemblyInstrFormats.td:61
1774 STORE_LANE_I16x8_A32 = 1759, // WebAssemblyInstrFormats.td:59
1775 STORE_LANE_I16x8_A32_S = 1760, // WebAssemblyInstrFormats.td:61
1776 STORE_LANE_I16x8_A64 = 1761, // WebAssemblyInstrFormats.td:59
1777 STORE_LANE_I16x8_A64_S = 1762, // WebAssemblyInstrFormats.td:61
1778 STORE_LANE_I32x4_A32 = 1763, // WebAssemblyInstrFormats.td:59
1779 STORE_LANE_I32x4_A32_S = 1764, // WebAssemblyInstrFormats.td:61
1780 STORE_LANE_I32x4_A64 = 1765, // WebAssemblyInstrFormats.td:59
1781 STORE_LANE_I32x4_A64_S = 1766, // WebAssemblyInstrFormats.td:61
1782 STORE_LANE_I64x2_A32 = 1767, // WebAssemblyInstrFormats.td:59
1783 STORE_LANE_I64x2_A32_S = 1768, // WebAssemblyInstrFormats.td:61
1784 STORE_LANE_I64x2_A64 = 1769, // WebAssemblyInstrFormats.td:59
1785 STORE_LANE_I64x2_A64_S = 1770, // WebAssemblyInstrFormats.td:61
1786 STORE_LANE_I8x16_A32 = 1771, // WebAssemblyInstrFormats.td:59
1787 STORE_LANE_I8x16_A32_S = 1772, // WebAssemblyInstrFormats.td:61
1788 STORE_LANE_I8x16_A64 = 1773, // WebAssemblyInstrFormats.td:59
1789 STORE_LANE_I8x16_A64_S = 1774, // WebAssemblyInstrFormats.td:61
1790 STORE_V128_A32 = 1775, // WebAssemblyInstrFormats.td:59
1791 STORE_V128_A32_S = 1776, // WebAssemblyInstrFormats.td:61
1792 STORE_V128_A64 = 1777, // WebAssemblyInstrFormats.td:59
1793 STORE_V128_A64_S = 1778, // WebAssemblyInstrFormats.td:61
1794 SUB_F16x8 = 1779, // WebAssemblyInstrFormats.td:59
1795 SUB_F16x8_S = 1780, // WebAssemblyInstrFormats.td:61
1796 SUB_F32 = 1781, // WebAssemblyInstrFormats.td:59
1797 SUB_F32_S = 1782, // WebAssemblyInstrFormats.td:61
1798 SUB_F32x4 = 1783, // WebAssemblyInstrFormats.td:59
1799 SUB_F32x4_S = 1784, // WebAssemblyInstrFormats.td:61
1800 SUB_F64 = 1785, // WebAssemblyInstrFormats.td:59
1801 SUB_F64_S = 1786, // WebAssemblyInstrFormats.td:61
1802 SUB_F64x2 = 1787, // WebAssemblyInstrFormats.td:59
1803 SUB_F64x2_S = 1788, // WebAssemblyInstrFormats.td:61
1804 SUB_I16x8 = 1789, // WebAssemblyInstrFormats.td:59
1805 SUB_I16x8_S = 1790, // WebAssemblyInstrFormats.td:61
1806 SUB_I32 = 1791, // WebAssemblyInstrFormats.td:59
1807 SUB_I32_S = 1792, // WebAssemblyInstrFormats.td:61
1808 SUB_I32x4 = 1793, // WebAssemblyInstrFormats.td:59
1809 SUB_I32x4_S = 1794, // WebAssemblyInstrFormats.td:61
1810 SUB_I64 = 1795, // WebAssemblyInstrFormats.td:59
1811 SUB_I64_S = 1796, // WebAssemblyInstrFormats.td:61
1812 SUB_I64x2 = 1797, // WebAssemblyInstrFormats.td:59
1813 SUB_I64x2_S = 1798, // WebAssemblyInstrFormats.td:61
1814 SUB_I8x16 = 1799, // WebAssemblyInstrFormats.td:59
1815 SUB_I8x16_S = 1800, // WebAssemblyInstrFormats.td:61
1816 SUB_SAT_S_I16x8 = 1801, // WebAssemblyInstrFormats.td:59
1817 SUB_SAT_S_I16x8_S = 1802, // WebAssemblyInstrFormats.td:61
1818 SUB_SAT_S_I8x16 = 1803, // WebAssemblyInstrFormats.td:59
1819 SUB_SAT_S_I8x16_S = 1804, // WebAssemblyInstrFormats.td:61
1820 SUB_SAT_U_I16x8 = 1805, // WebAssemblyInstrFormats.td:59
1821 SUB_SAT_U_I16x8_S = 1806, // WebAssemblyInstrFormats.td:61
1822 SUB_SAT_U_I8x16 = 1807, // WebAssemblyInstrFormats.td:59
1823 SUB_SAT_U_I8x16_S = 1808, // WebAssemblyInstrFormats.td:61
1824 SWIZZLE = 1809, // WebAssemblyInstrFormats.td:59
1825 SWIZZLE_S = 1810, // WebAssemblyInstrFormats.td:61
1826 TABLE_COPY = 1811, // WebAssemblyInstrFormats.td:59
1827 TABLE_COPY_S = 1812, // WebAssemblyInstrFormats.td:61
1828 TABLE_FILL_EXNREF = 1813, // WebAssemblyInstrFormats.td:59
1829 TABLE_FILL_EXNREF_S = 1814, // WebAssemblyInstrFormats.td:61
1830 TABLE_FILL_EXTERNREF = 1815, // WebAssemblyInstrFormats.td:59
1831 TABLE_FILL_EXTERNREF_S = 1816, // WebAssemblyInstrFormats.td:61
1832 TABLE_FILL_FUNCREF = 1817, // WebAssemblyInstrFormats.td:59
1833 TABLE_FILL_FUNCREF_S = 1818, // WebAssemblyInstrFormats.td:61
1834 TABLE_GET_EXNREF = 1819, // WebAssemblyInstrFormats.td:59
1835 TABLE_GET_EXNREF_S = 1820, // WebAssemblyInstrFormats.td:61
1836 TABLE_GET_EXTERNREF = 1821, // WebAssemblyInstrFormats.td:59
1837 TABLE_GET_EXTERNREF_S = 1822, // WebAssemblyInstrFormats.td:61
1838 TABLE_GET_FUNCREF = 1823, // WebAssemblyInstrFormats.td:59
1839 TABLE_GET_FUNCREF_S = 1824, // WebAssemblyInstrFormats.td:61
1840 TABLE_GROW_EXNREF = 1825, // WebAssemblyInstrFormats.td:59
1841 TABLE_GROW_EXNREF_S = 1826, // WebAssemblyInstrFormats.td:61
1842 TABLE_GROW_EXTERNREF = 1827, // WebAssemblyInstrFormats.td:59
1843 TABLE_GROW_EXTERNREF_S = 1828, // WebAssemblyInstrFormats.td:61
1844 TABLE_GROW_FUNCREF = 1829, // WebAssemblyInstrFormats.td:59
1845 TABLE_GROW_FUNCREF_S = 1830, // WebAssemblyInstrFormats.td:61
1846 TABLE_SET_EXNREF = 1831, // WebAssemblyInstrFormats.td:59
1847 TABLE_SET_EXNREF_S = 1832, // WebAssemblyInstrFormats.td:61
1848 TABLE_SET_EXTERNREF = 1833, // WebAssemblyInstrFormats.td:59
1849 TABLE_SET_EXTERNREF_S = 1834, // WebAssemblyInstrFormats.td:61
1850 TABLE_SET_FUNCREF = 1835, // WebAssemblyInstrFormats.td:59
1851 TABLE_SET_FUNCREF_S = 1836, // WebAssemblyInstrFormats.td:61
1852 TABLE_SIZE = 1837, // WebAssemblyInstrFormats.td:59
1853 TABLE_SIZE_S = 1838, // WebAssemblyInstrFormats.td:61
1854 TEE_EXNREF = 1839, // WebAssemblyInstrFormats.td:59
1855 TEE_EXNREF_S = 1840, // WebAssemblyInstrFormats.td:61
1856 TEE_EXTERNREF = 1841, // WebAssemblyInstrFormats.td:59
1857 TEE_EXTERNREF_S = 1842, // WebAssemblyInstrFormats.td:61
1858 TEE_F32 = 1843, // WebAssemblyInstrFormats.td:59
1859 TEE_F32_S = 1844, // WebAssemblyInstrFormats.td:61
1860 TEE_F64 = 1845, // WebAssemblyInstrFormats.td:59
1861 TEE_F64_S = 1846, // WebAssemblyInstrFormats.td:61
1862 TEE_FUNCREF = 1847, // WebAssemblyInstrFormats.td:59
1863 TEE_FUNCREF_S = 1848, // WebAssemblyInstrFormats.td:61
1864 TEE_I32 = 1849, // WebAssemblyInstrFormats.td:59
1865 TEE_I32_S = 1850, // WebAssemblyInstrFormats.td:61
1866 TEE_I64 = 1851, // WebAssemblyInstrFormats.td:59
1867 TEE_I64_S = 1852, // WebAssemblyInstrFormats.td:61
1868 TEE_V128 = 1853, // WebAssemblyInstrFormats.td:59
1869 TEE_V128_S = 1854, // WebAssemblyInstrFormats.td:61
1870 THROW = 1855, // WebAssemblyInstrFormats.td:59
1871 THROW_REF = 1856, // WebAssemblyInstrFormats.td:59
1872 THROW_REF_S = 1857, // WebAssemblyInstrFormats.td:61
1873 THROW_S = 1858, // WebAssemblyInstrFormats.td:61
1874 TRUNC_F16x8 = 1859, // WebAssemblyInstrFormats.td:59
1875 TRUNC_F16x8_S = 1860, // WebAssemblyInstrFormats.td:61
1876 TRUNC_F32 = 1861, // WebAssemblyInstrFormats.td:59
1877 TRUNC_F32_S = 1862, // WebAssemblyInstrFormats.td:61
1878 TRUNC_F32x4 = 1863, // WebAssemblyInstrFormats.td:59
1879 TRUNC_F32x4_S = 1864, // WebAssemblyInstrFormats.td:61
1880 TRUNC_F64 = 1865, // WebAssemblyInstrFormats.td:59
1881 TRUNC_F64_S = 1866, // WebAssemblyInstrFormats.td:61
1882 TRUNC_F64x2 = 1867, // WebAssemblyInstrFormats.td:59
1883 TRUNC_F64x2_S = 1868, // WebAssemblyInstrFormats.td:61
1884 TRY = 1869, // WebAssemblyInstrFormats.td:59
1885 TRY_S = 1870, // WebAssemblyInstrFormats.td:61
1886 TRY_TABLE = 1871, // WebAssemblyInstrFormats.td:59
1887 TRY_TABLE_S = 1872, // WebAssemblyInstrFormats.td:61
1888 UNREACHABLE = 1873, // WebAssemblyInstrFormats.td:59
1889 UNREACHABLE_S = 1874, // WebAssemblyInstrFormats.td:61
1890 XOR = 1875, // WebAssemblyInstrFormats.td:59
1891 XOR_I32 = 1876, // WebAssemblyInstrFormats.td:59
1892 XOR_I32_S = 1877, // WebAssemblyInstrFormats.td:61
1893 XOR_I64 = 1878, // WebAssemblyInstrFormats.td:59
1894 XOR_I64_S = 1879, // WebAssemblyInstrFormats.td:61
1895 XOR_S = 1880, // WebAssemblyInstrFormats.td:61
1896 anonymous_14734MEMORY_GROW_A32 = 1881, // WebAssemblyInstrFormats.td:59
1897 anonymous_14734MEMORY_GROW_A32_S = 1882, // WebAssemblyInstrFormats.td:61
1898 anonymous_14734MEMORY_SIZE_A32 = 1883, // WebAssemblyInstrFormats.td:59
1899 anonymous_14734MEMORY_SIZE_A32_S = 1884, // WebAssemblyInstrFormats.td:61
1900 anonymous_14735MEMORY_GROW_A64 = 1885, // WebAssemblyInstrFormats.td:59
1901 anonymous_14735MEMORY_GROW_A64_S = 1886, // WebAssemblyInstrFormats.td:61
1902 anonymous_14735MEMORY_SIZE_A64 = 1887, // WebAssemblyInstrFormats.td:59
1903 anonymous_14735MEMORY_SIZE_A64_S = 1888, // WebAssemblyInstrFormats.td:61
1904 convert_low_s_F64x2 = 1889, // WebAssemblyInstrFormats.td:59
1905 convert_low_s_F64x2_S = 1890, // WebAssemblyInstrFormats.td:61
1906 convert_low_u_F64x2 = 1891, // WebAssemblyInstrFormats.td:59
1907 convert_low_u_F64x2_S = 1892, // WebAssemblyInstrFormats.td:61
1908 demote_zero_F32x4 = 1893, // WebAssemblyInstrFormats.td:59
1909 demote_zero_F32x4_S = 1894, // WebAssemblyInstrFormats.td:61
1910 extadd_pairwise_s_I16x8 = 1895, // WebAssemblyInstrFormats.td:59
1911 extadd_pairwise_s_I16x8_S = 1896, // WebAssemblyInstrFormats.td:61
1912 extadd_pairwise_s_I32x4 = 1897, // WebAssemblyInstrFormats.td:59
1913 extadd_pairwise_s_I32x4_S = 1898, // WebAssemblyInstrFormats.td:61
1914 extadd_pairwise_u_I16x8 = 1899, // WebAssemblyInstrFormats.td:59
1915 extadd_pairwise_u_I16x8_S = 1900, // WebAssemblyInstrFormats.td:61
1916 extadd_pairwise_u_I32x4 = 1901, // WebAssemblyInstrFormats.td:59
1917 extadd_pairwise_u_I32x4_S = 1902, // WebAssemblyInstrFormats.td:61
1918 extend_high_s_I16x8 = 1903, // WebAssemblyInstrFormats.td:59
1919 extend_high_s_I16x8_S = 1904, // WebAssemblyInstrFormats.td:61
1920 extend_high_s_I32x4 = 1905, // WebAssemblyInstrFormats.td:59
1921 extend_high_s_I32x4_S = 1906, // WebAssemblyInstrFormats.td:61
1922 extend_high_s_I64x2 = 1907, // WebAssemblyInstrFormats.td:59
1923 extend_high_s_I64x2_S = 1908, // WebAssemblyInstrFormats.td:61
1924 extend_high_u_I16x8 = 1909, // WebAssemblyInstrFormats.td:59
1925 extend_high_u_I16x8_S = 1910, // WebAssemblyInstrFormats.td:61
1926 extend_high_u_I32x4 = 1911, // WebAssemblyInstrFormats.td:59
1927 extend_high_u_I32x4_S = 1912, // WebAssemblyInstrFormats.td:61
1928 extend_high_u_I64x2 = 1913, // WebAssemblyInstrFormats.td:59
1929 extend_high_u_I64x2_S = 1914, // WebAssemblyInstrFormats.td:61
1930 extend_low_s_I16x8 = 1915, // WebAssemblyInstrFormats.td:59
1931 extend_low_s_I16x8_S = 1916, // WebAssemblyInstrFormats.td:61
1932 extend_low_s_I32x4 = 1917, // WebAssemblyInstrFormats.td:59
1933 extend_low_s_I32x4_S = 1918, // WebAssemblyInstrFormats.td:61
1934 extend_low_s_I64x2 = 1919, // WebAssemblyInstrFormats.td:59
1935 extend_low_s_I64x2_S = 1920, // WebAssemblyInstrFormats.td:61
1936 extend_low_u_I16x8 = 1921, // WebAssemblyInstrFormats.td:59
1937 extend_low_u_I16x8_S = 1922, // WebAssemblyInstrFormats.td:61
1938 extend_low_u_I32x4 = 1923, // WebAssemblyInstrFormats.td:59
1939 extend_low_u_I32x4_S = 1924, // WebAssemblyInstrFormats.td:61
1940 extend_low_u_I64x2 = 1925, // WebAssemblyInstrFormats.td:59
1941 extend_low_u_I64x2_S = 1926, // WebAssemblyInstrFormats.td:61
1942 fp_to_sint_I16x8 = 1927, // WebAssemblyInstrFormats.td:59
1943 fp_to_sint_I16x8_S = 1928, // WebAssemblyInstrFormats.td:61
1944 fp_to_sint_I32x4 = 1929, // WebAssemblyInstrFormats.td:59
1945 fp_to_sint_I32x4_S = 1930, // WebAssemblyInstrFormats.td:61
1946 fp_to_uint_I16x8 = 1931, // WebAssemblyInstrFormats.td:59
1947 fp_to_uint_I16x8_S = 1932, // WebAssemblyInstrFormats.td:61
1948 fp_to_uint_I32x4 = 1933, // WebAssemblyInstrFormats.td:59
1949 fp_to_uint_I32x4_S = 1934, // WebAssemblyInstrFormats.td:61
1950 int_wasm_relaxed_trunc_signed_I32x4 = 1935, // WebAssemblyInstrFormats.td:59
1951 int_wasm_relaxed_trunc_signed_I32x4_S = 1936, // WebAssemblyInstrFormats.td:61
1952 int_wasm_relaxed_trunc_signed_zero_I32x4 = 1937, // WebAssemblyInstrFormats.td:59
1953 int_wasm_relaxed_trunc_signed_zero_I32x4_S = 1938, // WebAssemblyInstrFormats.td:61
1954 int_wasm_relaxed_trunc_unsigned_I32x4 = 1939, // WebAssemblyInstrFormats.td:59
1955 int_wasm_relaxed_trunc_unsigned_I32x4_S = 1940, // WebAssemblyInstrFormats.td:61
1956 int_wasm_relaxed_trunc_unsigned_zero_I32x4 = 1941, // WebAssemblyInstrFormats.td:59
1957 int_wasm_relaxed_trunc_unsigned_zero_I32x4_S = 1942, // WebAssemblyInstrFormats.td:61
1958 promote_low_F64x2 = 1943, // WebAssemblyInstrFormats.td:59
1959 promote_low_F64x2_S = 1944, // WebAssemblyInstrFormats.td:61
1960 sint_to_fp_F16x8 = 1945, // WebAssemblyInstrFormats.td:59
1961 sint_to_fp_F16x8_S = 1946, // WebAssemblyInstrFormats.td:61
1962 sint_to_fp_F32x4 = 1947, // WebAssemblyInstrFormats.td:59
1963 sint_to_fp_F32x4_S = 1948, // WebAssemblyInstrFormats.td:61
1964 trunc_sat_zero_s_I32x4 = 1949, // WebAssemblyInstrFormats.td:59
1965 trunc_sat_zero_s_I32x4_S = 1950, // WebAssemblyInstrFormats.td:61
1966 trunc_sat_zero_u_I32x4 = 1951, // WebAssemblyInstrFormats.td:59
1967 trunc_sat_zero_u_I32x4_S = 1952, // WebAssemblyInstrFormats.td:61
1968 uint_to_fp_F16x8 = 1953, // WebAssemblyInstrFormats.td:59
1969 uint_to_fp_F16x8_S = 1954, // WebAssemblyInstrFormats.td:61
1970 uint_to_fp_F32x4 = 1955, // WebAssemblyInstrFormats.td:59
1971 uint_to_fp_F32x4_S = 1956, // WebAssemblyInstrFormats.td:61
1972 INSTRUCTION_LIST_END = 1957
1973 };
1974 enum RegClassByHwModeUses : uint16_t {
1975 wasm_ptr_rc,
1976 };
1977
1978} // namespace llvm::WebAssembly
1979
1980#endif // GET_INSTRINFO_ENUM
1981
1982#ifdef GET_INSTRINFO_SCHED_ENUM
1983#undef GET_INSTRINFO_SCHED_ENUM
1984
1985namespace llvm::WebAssembly::Sched {
1986
1987 enum {
1988 NoInstrModel = 0,
1989 SCHED_LIST_END = 1
1990 };
1991
1992} // namespace llvm::WebAssembly::Sched
1993
1994#endif // GET_INSTRINFO_SCHED_ENUM
1995
1996#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
1997
1998namespace llvm {
1999
2000struct WebAssemblyInstrTable {
2001 MCInstrDesc Insts[1957];
2002 static_assert(alignof(MCInstrDesc) >= alignof(MCPhysReg), "Unwanted padding between Insts and ImplicitOps");
2003 MCPhysReg ImplicitOps[10];
2004 char Padding[sizeof(MCOperandInfo) - sizeof ImplicitOps % sizeof(MCOperandInfo)];
2005 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
2006 MCOperandInfo OperandInfo[829];
2007};
2008} // namespace llvm
2009
2010#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
2011
2012#ifdef GET_INSTRINFO_MC_DESC
2013#undef GET_INSTRINFO_MC_DESC
2014
2015namespace llvm {
2016
2017static_assert((sizeof WebAssemblyInstrTable::ImplicitOps + sizeof WebAssemblyInstrTable::Padding) % sizeof(MCOperandInfo) == 0);
2018static constexpr unsigned WebAssemblyOpInfoBase = (sizeof WebAssemblyInstrTable::ImplicitOps + sizeof WebAssemblyInstrTable::Padding) / sizeof(MCOperandInfo);
2019
2020extern const WebAssemblyInstrTable WebAssemblyDescs = {
2021 {
2022 { 1956, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // uint_to_fp_F32x4_S
2023 { 1955, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // uint_to_fp_F32x4
2024 { 1954, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // uint_to_fp_F16x8_S
2025 { 1953, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // uint_to_fp_F16x8
2026 { 1952, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // trunc_sat_zero_u_I32x4_S
2027 { 1951, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // trunc_sat_zero_u_I32x4
2028 { 1950, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // trunc_sat_zero_s_I32x4_S
2029 { 1949, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // trunc_sat_zero_s_I32x4
2030 { 1948, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // sint_to_fp_F32x4_S
2031 { 1947, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // sint_to_fp_F32x4
2032 { 1946, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // sint_to_fp_F16x8_S
2033 { 1945, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // sint_to_fp_F16x8
2034 { 1944, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // promote_low_F64x2_S
2035 { 1943, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // promote_low_F64x2
2036 { 1942, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // int_wasm_relaxed_trunc_unsigned_zero_I32x4_S
2037 { 1941, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // int_wasm_relaxed_trunc_unsigned_zero_I32x4
2038 { 1940, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // int_wasm_relaxed_trunc_unsigned_I32x4_S
2039 { 1939, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // int_wasm_relaxed_trunc_unsigned_I32x4
2040 { 1938, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // int_wasm_relaxed_trunc_signed_zero_I32x4_S
2041 { 1937, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // int_wasm_relaxed_trunc_signed_zero_I32x4
2042 { 1936, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // int_wasm_relaxed_trunc_signed_I32x4_S
2043 { 1935, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // int_wasm_relaxed_trunc_signed_I32x4
2044 { 1934, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // fp_to_uint_I32x4_S
2045 { 1933, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // fp_to_uint_I32x4
2046 { 1932, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // fp_to_uint_I16x8_S
2047 { 1931, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // fp_to_uint_I16x8
2048 { 1930, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // fp_to_sint_I32x4_S
2049 { 1929, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // fp_to_sint_I32x4
2050 { 1928, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // fp_to_sint_I16x8_S
2051 { 1927, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // fp_to_sint_I16x8
2052 { 1926, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_low_u_I64x2_S
2053 { 1925, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_low_u_I64x2
2054 { 1924, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_low_u_I32x4_S
2055 { 1923, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_low_u_I32x4
2056 { 1922, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_low_u_I16x8_S
2057 { 1921, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_low_u_I16x8
2058 { 1920, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_low_s_I64x2_S
2059 { 1919, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_low_s_I64x2
2060 { 1918, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_low_s_I32x4_S
2061 { 1917, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_low_s_I32x4
2062 { 1916, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_low_s_I16x8_S
2063 { 1915, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_low_s_I16x8
2064 { 1914, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_high_u_I64x2_S
2065 { 1913, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_high_u_I64x2
2066 { 1912, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_high_u_I32x4_S
2067 { 1911, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_high_u_I32x4
2068 { 1910, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_high_u_I16x8_S
2069 { 1909, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_high_u_I16x8
2070 { 1908, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_high_s_I64x2_S
2071 { 1907, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_high_s_I64x2
2072 { 1906, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_high_s_I32x4_S
2073 { 1905, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_high_s_I32x4
2074 { 1904, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_high_s_I16x8_S
2075 { 1903, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extend_high_s_I16x8
2076 { 1902, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extadd_pairwise_u_I32x4_S
2077 { 1901, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extadd_pairwise_u_I32x4
2078 { 1900, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extadd_pairwise_u_I16x8_S
2079 { 1899, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extadd_pairwise_u_I16x8
2080 { 1898, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extadd_pairwise_s_I32x4_S
2081 { 1897, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extadd_pairwise_s_I32x4
2082 { 1896, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extadd_pairwise_s_I16x8_S
2083 { 1895, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // extadd_pairwise_s_I16x8
2084 { 1894, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // demote_zero_F32x4_S
2085 { 1893, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // demote_zero_F32x4
2086 { 1892, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // convert_low_u_F64x2_S
2087 { 1891, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // convert_low_u_F64x2
2088 { 1890, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // convert_low_s_F64x2_S
2089 { 1889, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // convert_low_s_F64x2
2090 { 1888, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14735MEMORY_SIZE_A64_S
2091 { 1887, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 194, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14735MEMORY_SIZE_A64
2092 { 1886, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14735MEMORY_GROW_A64_S
2093 { 1885, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 826, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14735MEMORY_GROW_A64
2094 { 1884, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14734MEMORY_SIZE_A32_S
2095 { 1883, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 192, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14734MEMORY_SIZE_A32
2096 { 1882, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14734MEMORY_GROW_A32_S
2097 { 1881, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 823, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14734MEMORY_GROW_A32
2098 { 1880, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_S
2099 { 1879, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_I64_S
2100 { 1878, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 177, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_I64
2101 { 1877, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_I32_S
2102 { 1876, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 174, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_I32
2103 { 1875, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR
2104 { 1874, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Trap)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // UNREACHABLE_S
2105 { 1873, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Trap)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // UNREACHABLE
2106 { 1872, 2, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 821, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRY_TABLE_S
2107 { 1871, 1, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 282, 8, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRY_TABLE
2108 { 1870, 1, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 282, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRY_S
2109 { 1869, 1, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 282, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRY
2110 { 1868, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRUNC_F64x2_S
2111 { 1867, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRUNC_F64x2
2112 { 1866, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRUNC_F64_S
2113 { 1865, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 163, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRUNC_F64
2114 { 1864, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRUNC_F32x4_S
2115 { 1863, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRUNC_F32x4
2116 { 1862, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRUNC_F32_S
2117 { 1861, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRUNC_F32
2118 { 1860, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRUNC_F16x8_S
2119 { 1859, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TRUNC_F16x8
2120 { 1858, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 290, 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // THROW_S
2121 { 1857, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // THROW_REF_S
2122 { 1856, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 291, 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // THROW_REF
2123 { 1855, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 290, 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // THROW
2124 { 1854, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_V128_S
2125 { 1853, 3, 2, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_V128
2126 { 1852, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_I64_S
2127 { 1851, 3, 2, 0, 0, 0, 1, WebAssemblyOpInfoBase + 177, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_I64
2128 { 1850, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_I32_S
2129 { 1849, 3, 2, 0, 0, 0, 1, WebAssemblyOpInfoBase + 174, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_I32
2130 { 1848, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_FUNCREF_S
2131 { 1847, 3, 2, 0, 0, 0, 1, WebAssemblyOpInfoBase + 818, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_FUNCREF
2132 { 1846, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_F64_S
2133 { 1845, 3, 2, 0, 0, 0, 1, WebAssemblyOpInfoBase + 171, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_F64
2134 { 1844, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_F32_S
2135 { 1843, 3, 2, 0, 0, 0, 1, WebAssemblyOpInfoBase + 168, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_F32
2136 { 1842, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_EXTERNREF_S
2137 { 1841, 3, 2, 0, 0, 0, 1, WebAssemblyOpInfoBase + 815, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_EXTERNREF
2138 { 1840, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_EXNREF_S
2139 { 1839, 3, 2, 0, 0, 0, 1, WebAssemblyOpInfoBase + 812, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TEE_EXNREF
2140 { 1838, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 771, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_SIZE_S
2141 { 1837, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 810, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_SIZE
2142 { 1836, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 771, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_SET_FUNCREF_S
2143 { 1835, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 807, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_SET_FUNCREF
2144 { 1834, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 771, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_SET_EXTERNREF_S
2145 { 1833, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 804, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_SET_EXTERNREF
2146 { 1832, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 771, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_SET_EXNREF_S
2147 { 1831, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 801, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_SET_EXNREF
2148 { 1830, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 771, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_GROW_FUNCREF_S
2149 { 1829, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 797, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_GROW_FUNCREF
2150 { 1828, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 771, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_GROW_EXTERNREF_S
2151 { 1827, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 793, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_GROW_EXTERNREF
2152 { 1826, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 771, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_GROW_EXNREF_S
2153 { 1825, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 789, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_GROW_EXNREF
2154 { 1824, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 771, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_GET_FUNCREF_S
2155 { 1823, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 786, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_GET_FUNCREF
2156 { 1822, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 771, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_GET_EXTERNREF_S
2157 { 1821, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 783, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_GET_EXTERNREF
2158 { 1820, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 771, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_GET_EXNREF_S
2159 { 1819, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 780, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_GET_EXNREF
2160 { 1818, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 771, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_FILL_FUNCREF_S
2161 { 1817, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 776, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_FILL_FUNCREF
2162 { 1816, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 771, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_FILL_EXTERNREF_S
2163 { 1815, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 772, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_FILL_EXTERNREF
2164 { 1814, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 771, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_FILL_EXNREF_S
2165 { 1813, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 767, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_FILL_EXNREF
2166 { 1812, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 765, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_COPY_S
2167 { 1811, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 760, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // TABLE_COPY
2168 { 1810, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SWIZZLE_S
2169 { 1809, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SWIZZLE
2170 { 1808, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_SAT_U_I8x16_S
2171 { 1807, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_SAT_U_I8x16
2172 { 1806, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_SAT_U_I16x8_S
2173 { 1805, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_SAT_U_I16x8
2174 { 1804, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_SAT_S_I8x16_S
2175 { 1803, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_SAT_S_I8x16
2176 { 1802, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_SAT_S_I16x8_S
2177 { 1801, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_SAT_S_I16x8
2178 { 1800, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I8x16_S
2179 { 1799, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I8x16
2180 { 1798, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I64x2_S
2181 { 1797, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I64x2
2182 { 1796, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I64_S
2183 { 1795, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 177, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I64
2184 { 1794, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I32x4_S
2185 { 1793, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I32x4
2186 { 1792, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I32_S
2187 { 1791, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 174, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I32
2188 { 1790, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I16x8_S
2189 { 1789, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_I16x8
2190 { 1788, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F64x2_S
2191 { 1787, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F64x2
2192 { 1786, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F64_S
2193 { 1785, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 171, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F64
2194 { 1784, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F32x4_S
2195 { 1783, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F32x4
2196 { 1782, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F32_S
2197 { 1781, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 168, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F32
2198 { 1780, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F16x8_S
2199 { 1779, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_F16x8
2200 { 1778, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_V128_A64_S
2201 { 1777, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 756, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_V128_A64
2202 { 1776, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_V128_A32_S
2203 { 1775, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 752, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_V128_A32
2204 { 1774, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 527, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I8x16_A64_S
2205 { 1773, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 747, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I8x16_A64
2206 { 1772, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 518, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I8x16_A32_S
2207 { 1771, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 742, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I8x16_A32
2208 { 1770, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 527, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I64x2_A64_S
2209 { 1769, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 747, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I64x2_A64
2210 { 1768, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 518, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I64x2_A32_S
2211 { 1767, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 742, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I64x2_A32
2212 { 1766, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 527, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I32x4_A64_S
2213 { 1765, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 747, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I32x4_A64
2214 { 1764, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 518, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I32x4_A32_S
2215 { 1763, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 742, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I32x4_A32
2216 { 1762, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 527, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I16x8_A64_S
2217 { 1761, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 747, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I16x8_A64
2218 { 1760, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 518, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I16x8_A32_S
2219 { 1759, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 742, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_LANE_I16x8_A32
2220 { 1758, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_I64_A64_S
2221 { 1757, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 274, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_I64_A64
2222 { 1756, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_I64_A32_S
2223 { 1755, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 270, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_I64_A32
2224 { 1754, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_I32_A64_S
2225 { 1753, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 266, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_I32_A64
2226 { 1752, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_I32_A32_S
2227 { 1751, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 262, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_I32_A32
2228 { 1750, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_F64_A64_S
2229 { 1749, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 738, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_F64_A64
2230 { 1748, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_F64_A32_S
2231 { 1747, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 734, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_F64_A32
2232 { 1746, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_F32_A64_S
2233 { 1745, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 730, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_F32_A64
2234 { 1744, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_F32_A32_S
2235 { 1743, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 726, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_F32_A32
2236 { 1742, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_F16_F32_A64_S
2237 { 1741, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 730, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_F16_F32_A64
2238 { 1740, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_F16_F32_A32_S
2239 { 1739, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 726, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_F16_F32_A32
2240 { 1738, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE8_I64_A64_S
2241 { 1737, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 274, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE8_I64_A64
2242 { 1736, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE8_I64_A32_S
2243 { 1735, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 270, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE8_I64_A32
2244 { 1734, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE8_I32_A64_S
2245 { 1733, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 266, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE8_I32_A64
2246 { 1732, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE8_I32_A32_S
2247 { 1731, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 262, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE8_I32_A32
2248 { 1730, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE32_I64_A64_S
2249 { 1729, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 274, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE32_I64_A64
2250 { 1728, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE32_I64_A32_S
2251 { 1727, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 270, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE32_I64_A32
2252 { 1726, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE16_I64_A64_S
2253 { 1725, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 274, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE16_I64_A64
2254 { 1724, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE16_I64_A32_S
2255 { 1723, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 270, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE16_I64_A32
2256 { 1722, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE16_I32_A64_S
2257 { 1721, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 266, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE16_I32_A64
2258 { 1720, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE16_I32_A32_S
2259 { 1719, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 262, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE16_I32_A32
2260 { 1718, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SQRT_F64x2_S
2261 { 1717, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SQRT_F64x2
2262 { 1716, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SQRT_F64_S
2263 { 1715, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 163, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SQRT_F64
2264 { 1714, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SQRT_F32x4_S
2265 { 1713, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SQRT_F32x4
2266 { 1712, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SQRT_F32_S
2267 { 1711, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SQRT_F32
2268 { 1710, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SQRT_F16x8_S
2269 { 1709, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SQRT_F16x8
2270 { 1708, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_I8x16_S
2271 { 1707, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 722, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_I8x16
2272 { 1706, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_I64x2_S
2273 { 1705, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 724, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_I64x2
2274 { 1704, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_I32x4_S
2275 { 1703, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 722, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_I32x4
2276 { 1702, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_I16x8_S
2277 { 1701, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 722, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_I16x8
2278 { 1700, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_F64x2_S
2279 { 1699, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 720, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_F64x2
2280 { 1698, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_F32x4_S
2281 { 1697, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 718, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_F32x4
2282 { 1696, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_F16x8_S
2283 { 1695, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 718, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SPLAT_F16x8
2284 { 1694, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SIMD_RELAXED_FMIN_F64x2_S
2285 { 1693, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SIMD_RELAXED_FMIN_F64x2
2286 { 1692, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SIMD_RELAXED_FMIN_F32x4_S
2287 { 1691, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SIMD_RELAXED_FMIN_F32x4
2288 { 1690, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SIMD_RELAXED_FMAX_F64x2_S
2289 { 1689, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SIMD_RELAXED_FMAX_F64x2
2290 { 1688, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SIMD_RELAXED_FMAX_F32x4_S
2291 { 1687, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SIMD_RELAXED_FMAX_F32x4
2292 { 1686, 16, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 370, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHUFFLE_S
2293 { 1685, 19, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 699, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHUFFLE
2294 { 1684, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_U_I8x16_S
2295 { 1683, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 696, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_U_I8x16
2296 { 1682, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_U_I64x2_S
2297 { 1681, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 696, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_U_I64x2
2298 { 1680, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_U_I64_S
2299 { 1679, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 177, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_U_I64
2300 { 1678, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_U_I32x4_S
2301 { 1677, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 696, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_U_I32x4
2302 { 1676, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_U_I32_S
2303 { 1675, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 174, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_U_I32
2304 { 1674, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_U_I16x8_S
2305 { 1673, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 696, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_U_I16x8
2306 { 1672, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_S_I8x16_S
2307 { 1671, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 696, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_S_I8x16
2308 { 1670, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_S_I64x2_S
2309 { 1669, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 696, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_S_I64x2
2310 { 1668, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_S_I64_S
2311 { 1667, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 177, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_S_I64
2312 { 1666, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_S_I32x4_S
2313 { 1665, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 696, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_S_I32x4
2314 { 1664, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_S_I32_S
2315 { 1663, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 174, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_S_I32
2316 { 1662, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_S_I16x8_S
2317 { 1661, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 696, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHR_S_I16x8
2318 { 1660, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_I8x16_S
2319 { 1659, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 696, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_I8x16
2320 { 1658, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_I64x2_S
2321 { 1657, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 696, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_I64x2
2322 { 1656, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_I64_S
2323 { 1655, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 177, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_I64
2324 { 1654, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_I32x4_S
2325 { 1653, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 696, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_I32x4
2326 { 1652, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_I32_S
2327 { 1651, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 174, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_I32
2328 { 1650, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_I16x8_S
2329 { 1649, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 696, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SHL_I16x8
2330 { 1648, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_V128_S
2331 { 1647, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 692, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_V128
2332 { 1646, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_I64_S
2333 { 1645, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 688, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_I64
2334 { 1644, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_I32_S
2335 { 1643, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 684, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_I32
2336 { 1642, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_FUNCREF_S
2337 { 1641, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 680, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_FUNCREF
2338 { 1640, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_F64_S
2339 { 1639, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 676, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_F64
2340 { 1638, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_F32_S
2341 { 1637, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 672, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_F32
2342 { 1636, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_EXTERNREF_S
2343 { 1635, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 668, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_EXTERNREF
2344 { 1634, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_EXNREF_S
2345 { 1633, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 664, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SELECT_EXNREF
2346 { 1632, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ROTR_I64_S
2347 { 1631, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 177, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ROTR_I64
2348 { 1630, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ROTR_I32_S
2349 { 1629, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 174, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ROTR_I32
2350 { 1628, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ROTL_I64_S
2351 { 1627, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 177, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ROTL_I64
2352 { 1626, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ROTL_I32_S
2353 { 1625, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 174, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ROTL_I32
2354 { 1624, 1, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 155, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RET_CALL_S
2355 { 1623, 2, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 288, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RET_CALL_INDIRECT_S
2356 { 1622, 2, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 288, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RET_CALL_INDIRECT
2357 { 1621, 1, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 155, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RET_CALL
2358 { 1620, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RETURN_S
2359 { 1619, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RETURN
2360 { 1618, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 158, 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RETHROW_S
2361 { 1617, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 158, 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RETHROW
2362 { 1616, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 411, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_I8x16_S
2363 { 1615, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 656, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_I8x16
2364 { 1614, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 411, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_I64x2_S
2365 { 1613, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 660, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_I64x2
2366 { 1612, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 411, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_I32x4_S
2367 { 1611, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 656, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_I32x4
2368 { 1610, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 411, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_I16x8_S
2369 { 1609, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 656, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_I16x8
2370 { 1608, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 411, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_F64x2_S
2371 { 1607, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 652, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_F64x2
2372 { 1606, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 411, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_F32x4_S
2373 { 1605, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 648, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_F32x4
2374 { 1604, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 411, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_F16x8_S
2375 { 1603, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 648, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REPLACE_LANE_F16x8
2376 { 1602, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REM_U_I64_S
2377 { 1601, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 177, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REM_U_I64
2378 { 1600, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REM_U_I32_S
2379 { 1599, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 174, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REM_U_I32
2380 { 1598, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REM_S_I64_S
2381 { 1597, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 177, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REM_S_I64
2382 { 1596, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REM_S_I32_S
2383 { 1595, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 174, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REM_S_I32
2384 { 1594, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELAXED_SWIZZLE_S
2385 { 1593, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELAXED_SWIZZLE
2386 { 1592, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELAXED_Q15MULR_S_I16x8_S
2387 { 1591, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELAXED_Q15MULR_S_I16x8
2388 { 1590, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELAXED_DOT_S
2389 { 1589, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELAXED_DOT_BFLOAT_S
2390 { 1588, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 278, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELAXED_DOT_BFLOAT
2391 { 1587, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELAXED_DOT_ADD_S
2392 { 1586, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 278, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELAXED_DOT_ADD
2393 { 1585, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELAXED_DOT
2394 { 1584, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 647, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_TEST_FUNCREF_S
2395 { 1583, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 644, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_TEST_FUNCREF
2396 { 1582, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_NULL_FUNCREF_S
2397 { 1581, 1, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 395, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_NULL_FUNCREF
2398 { 1580, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_NULL_EXTERNREF_S
2399 { 1579, 1, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 392, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_NULL_EXTERNREF
2400 { 1578, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_NULL_EXNREF_S
2401 { 1577, 1, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 291, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_NULL_EXNREF
2402 { 1576, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_IS_NULL_FUNCREF_S
2403 { 1575, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 642, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_IS_NULL_FUNCREF
2404 { 1574, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_IS_NULL_EXTERNREF_S
2405 { 1573, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 640, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_IS_NULL_EXTERNREF
2406 { 1572, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_IS_NULL_EXNREF_S
2407 { 1571, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 638, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_IS_NULL_EXNREF
2408 { 1570, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 155, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_FUNC_S
2409 { 1569, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 636, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REF_FUNC
2410 { 1568, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Q15MULR_SAT_S_I16x8_S
2411 { 1567, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Q15MULR_SAT_S_I16x8
2412 { 1566, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // POPCNT_I8x16_S
2413 { 1565, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // POPCNT_I8x16
2414 { 1564, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // POPCNT_I64_S
2415 { 1563, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 294, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // POPCNT_I64
2416 { 1562, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // POPCNT_I32_S
2417 { 1561, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 292, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // POPCNT_I32
2418 { 1560, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PMIN_F64x2_S
2419 { 1559, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PMIN_F64x2
2420 { 1558, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PMIN_F32x4_S
2421 { 1557, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PMIN_F32x4
2422 { 1556, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PMIN_F16x8_S
2423 { 1555, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PMIN_F16x8
2424 { 1554, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PMAX_F64x2_S
2425 { 1553, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PMAX_F64x2
2426 { 1552, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PMAX_F32x4_S
2427 { 1551, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PMAX_F32x4
2428 { 1550, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PMAX_F16x8_S
2429 { 1549, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PMAX_F16x8
2430 { 1548, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_S
2431 { 1547, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_I64_S
2432 { 1546, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 177, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_I64
2433 { 1545, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_I32_S
2434 { 1544, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 174, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_I32
2435 { 1543, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR
2436 { 1542, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NOT_S
2437 { 1541, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NOT
2438 { 1540, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NOP_S
2439 { 1539, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NOP
2440 { 1538, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NMADD_F64x2_S
2441 { 1537, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 278, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NMADD_F64x2
2442 { 1536, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NMADD_F32x4_S
2443 { 1535, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 278, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NMADD_F32x4
2444 { 1534, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NMADD_F16x8_S
2445 { 1533, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 278, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NMADD_F16x8
2446 { 1532, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_I8x16_S
2447 { 1531, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_I8x16
2448 { 1530, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_I64x2_S
2449 { 1529, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_I64x2
2450 { 1528, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_I64_S
2451 { 1527, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 405, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_I64
2452 { 1526, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_I32x4_S
2453 { 1525, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_I32x4
2454 { 1524, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_I32_S
2455 { 1523, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 174, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_I32
2456 { 1522, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_I16x8_S
2457 { 1521, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_I16x8
2458 { 1520, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_F64x2_S
2459 { 1519, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_F64x2
2460 { 1518, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_F64_S
2461 { 1517, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 402, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_F64
2462 { 1516, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_F32x4_S
2463 { 1515, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_F32x4
2464 { 1514, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_F32_S
2465 { 1513, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 399, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_F32
2466 { 1512, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_F16x8_S
2467 { 1511, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NE_F16x8
2468 { 1510, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_I8x16_S
2469 { 1509, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_I8x16
2470 { 1508, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_I64x2_S
2471 { 1507, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_I64x2
2472 { 1506, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_I32x4_S
2473 { 1505, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_I32x4
2474 { 1504, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_I16x8_S
2475 { 1503, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_I16x8
2476 { 1502, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_F64x2_S
2477 { 1501, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_F64x2
2478 { 1500, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_F64_S
2479 { 1499, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 163, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_F64
2480 { 1498, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_F32x4_S
2481 { 1497, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_F32x4
2482 { 1496, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_F32_S
2483 { 1495, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_F32
2484 { 1494, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_F16x8_S
2485 { 1493, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_F16x8
2486 { 1492, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEAREST_F64x2_S
2487 { 1491, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEAREST_F64x2
2488 { 1490, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEAREST_F64_S
2489 { 1489, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 163, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEAREST_F64
2490 { 1488, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEAREST_F32x4_S
2491 { 1487, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEAREST_F32x4
2492 { 1486, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEAREST_F32_S
2493 { 1485, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEAREST_F32
2494 { 1484, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEAREST_F16x8_S
2495 { 1483, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEAREST_F16x8
2496 { 1482, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NARROW_U_I8x16_S
2497 { 1481, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NARROW_U_I8x16
2498 { 1480, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NARROW_U_I16x8_S
2499 { 1479, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NARROW_U_I16x8
2500 { 1478, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NARROW_S_I8x16_S
2501 { 1477, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NARROW_S_I8x16
2502 { 1476, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NARROW_S_I16x8_S
2503 { 1475, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NARROW_S_I16x8
2504 { 1474, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_I64x2_S
2505 { 1473, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_I64x2
2506 { 1472, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_I64_S
2507 { 1471, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 177, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_I64
2508 { 1470, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_I32x4_S
2509 { 1469, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_I32x4
2510 { 1468, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_I32_S
2511 { 1467, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 174, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_I32
2512 { 1466, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_I16x8_S
2513 { 1465, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_I16x8
2514 { 1464, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_F64x2_S
2515 { 1463, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_F64x2
2516 { 1462, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_F64_S
2517 { 1461, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 171, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_F64
2518 { 1460, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_F32x4_S
2519 { 1459, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_F32x4
2520 { 1458, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_F32_S
2521 { 1457, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 168, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_F32
2522 { 1456, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_F16x8_S
2523 { 1455, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_F16x8
2524 { 1454, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_U_I8x16_S
2525 { 1453, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_U_I8x16
2526 { 1452, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_U_I32x4_S
2527 { 1451, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_U_I32x4
2528 { 1450, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_U_I16x8_S
2529 { 1449, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_U_I16x8
2530 { 1448, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_S_I8x16_S
2531 { 1447, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_S_I8x16
2532 { 1446, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_S_I32x4_S
2533 { 1445, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_S_I32x4
2534 { 1444, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_S_I16x8_S
2535 { 1443, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_S_I16x8
2536 { 1442, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_F64x2_S
2537 { 1441, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_F64x2
2538 { 1440, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_F64_S
2539 { 1439, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 171, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_F64
2540 { 1438, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_F32x4_S
2541 { 1437, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_F32x4
2542 { 1436, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_F32_S
2543 { 1435, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 168, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_F32
2544 { 1434, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_F16x8_S
2545 { 1433, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MIN_F16x8
2546 { 1432, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 304, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMSET_A64_S
2547 { 1431, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 627, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMSET_A64
2548 { 1430, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 304, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMSET_A32_S
2549 { 1429, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 623, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMSET_A32
2550 { 1428, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 592, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_INIT_A64_S
2551 { 1427, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 631, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_INIT_A64
2552 { 1426, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 592, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_INIT_A32_S
2553 { 1425, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 587, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_INIT_A32
2554 { 1424, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 304, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_FILL_A64_S
2555 { 1423, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 627, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_FILL_A64
2556 { 1422, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 304, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_FILL_A32_S
2557 { 1421, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 623, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_FILL_A32
2558 { 1420, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 592, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_COPY_A64_S
2559 { 1419, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 594, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_COPY_A64
2560 { 1418, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 592, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_COPY_A32_S
2561 { 1417, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 587, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_COPY_A32
2562 { 1416, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_ATOMIC_WAIT64_A64_S
2563 { 1415, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 617, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_ATOMIC_WAIT64_A64
2564 { 1414, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_ATOMIC_WAIT64_A32_S
2565 { 1413, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 611, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_ATOMIC_WAIT64_A32
2566 { 1412, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_ATOMIC_WAIT32_A64_S
2567 { 1411, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 605, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_ATOMIC_WAIT32_A64
2568 { 1410, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_ATOMIC_WAIT32_A32_S
2569 { 1409, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 599, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_ATOMIC_WAIT32_A32
2570 { 1408, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_ATOMIC_NOTIFY_A64_S
2571 { 1407, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 223, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_ATOMIC_NOTIFY_A64
2572 { 1406, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_ATOMIC_NOTIFY_A32_S
2573 { 1405, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 218, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMORY_ATOMIC_NOTIFY_A32
2574 { 1404, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 592, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMCPY_A64_S
2575 { 1403, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 594, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMCPY_A64
2576 { 1402, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 592, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMCPY_A32_S
2577 { 1401, 5, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 587, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMCPY_A32
2578 { 1400, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_U_I8x16_S
2579 { 1399, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_U_I8x16
2580 { 1398, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_U_I32x4_S
2581 { 1397, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_U_I32x4
2582 { 1396, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_U_I16x8_S
2583 { 1395, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_U_I16x8
2584 { 1394, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_S_I8x16_S
2585 { 1393, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_S_I8x16
2586 { 1392, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_S_I32x4_S
2587 { 1391, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_S_I32x4
2588 { 1390, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_S_I16x8_S
2589 { 1389, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_S_I16x8
2590 { 1388, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_F64x2_S
2591 { 1387, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_F64x2
2592 { 1386, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_F64_S
2593 { 1385, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 171, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_F64
2594 { 1384, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_F32x4_S
2595 { 1383, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_F32x4
2596 { 1382, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_F32_S
2597 { 1381, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 168, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_F32
2598 { 1380, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_F16x8_S
2599 { 1379, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MAX_F16x8
2600 { 1378, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MADD_F64x2_S
2601 { 1377, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 278, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MADD_F64x2
2602 { 1376, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MADD_F32x4_S
2603 { 1375, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 278, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MADD_F32x4
2604 { 1374, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MADD_F16x8_S
2605 { 1373, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 278, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MADD_F16x8
2606 { 1372, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_U_I8x16_S
2607 { 1371, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_U_I8x16
2608 { 1370, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_U_I64_S
2609 { 1369, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 405, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_U_I64
2610 { 1368, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_U_I32x4_S
2611 { 1367, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_U_I32x4
2612 { 1366, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_U_I32_S
2613 { 1365, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 174, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_U_I32
2614 { 1364, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_U_I16x8_S
2615 { 1363, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_U_I16x8
2616 { 1362, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_S_I8x16_S
2617 { 1361, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_S_I8x16
2618 { 1360, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_S_I64x2_S
2619 { 1359, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_S_I64x2
2620 { 1358, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_S_I64_S
2621 { 1357, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 405, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_S_I64
2622 { 1356, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_S_I32x4_S
2623 { 1355, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_S_I32x4
2624 { 1354, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_S_I32_S
2625 { 1353, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 174, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_S_I32
2626 { 1352, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_S_I16x8_S
2627 { 1351, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_S_I16x8
2628 { 1350, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_F64x2_S
2629 { 1349, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_F64x2
2630 { 1348, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_F64_S
2631 { 1347, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 402, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_F64
2632 { 1346, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_F32x4_S
2633 { 1345, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_F32x4
2634 { 1344, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_F32_S
2635 { 1343, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 399, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_F32
2636 { 1342, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_F16x8_S
2637 { 1341, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LT_F16x8
2638 { 1340, 1, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 282, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOOP_S
2639 { 1339, 1, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 282, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOOP
2640 { 1338, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 532, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_V128_S
2641 { 1337, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 584, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_V128
2642 { 1336, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 532, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_I64_S
2643 { 1335, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 581, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_I64
2644 { 1334, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 532, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_I32_S
2645 { 1333, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 578, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_I32
2646 { 1332, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 532, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_FUNCREF_S
2647 { 1331, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 575, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_FUNCREF
2648 { 1330, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 532, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_F64_S
2649 { 1329, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 572, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_F64
2650 { 1328, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 532, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_F32_S
2651 { 1327, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 569, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_F32
2652 { 1326, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 532, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_EXTERNREF_S
2653 { 1325, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 566, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_EXTERNREF
2654 { 1324, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 532, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_EXNREF_S
2655 { 1323, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 563, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_TEE_EXNREF
2656 { 1322, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 532, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_V128_S
2657 { 1321, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 561, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_V128
2658 { 1320, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 532, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_I64_S
2659 { 1319, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 559, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_I64
2660 { 1318, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 532, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_I32_S
2661 { 1317, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 557, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_I32
2662 { 1316, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 532, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_FUNCREF_S
2663 { 1315, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 555, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_FUNCREF
2664 { 1314, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 532, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_F64_S
2665 { 1313, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 553, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_F64
2666 { 1312, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 532, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_F32_S
2667 { 1311, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 551, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_F32
2668 { 1310, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 532, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_EXTERNREF_S
2669 { 1309, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 549, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_EXTERNREF
2670 { 1308, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 532, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_EXNREF_S
2671 { 1307, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 547, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_SET_EXNREF
2672 { 1306, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 532, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_V128_S
2673 { 1305, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 545, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_V128
2674 { 1304, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 532, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_I64_S
2675 { 1303, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 543, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_I64
2676 { 1302, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 532, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_I32_S
2677 { 1301, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 541, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_I32
2678 { 1300, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 532, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_FUNCREF_S
2679 { 1299, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 539, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_FUNCREF
2680 { 1298, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 532, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_F64_S
2681 { 1297, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 537, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_F64
2682 { 1296, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 532, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_F32_S
2683 { 1295, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 535, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_F32
2684 { 1294, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 532, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_EXTERNREF_S
2685 { 1293, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 533, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_EXTERNREF
2686 { 1292, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 532, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_EXNREF_S
2687 { 1291, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 530, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_GET_EXNREF
2688 { 1290, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_ZERO_64_A64_S
2689 { 1289, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 492, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_ZERO_64_A64
2690 { 1288, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_ZERO_64_A32_S
2691 { 1287, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 488, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_ZERO_64_A32
2692 { 1286, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_ZERO_32_A64_S
2693 { 1285, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 492, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_ZERO_32_A64
2694 { 1284, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_ZERO_32_A32_S
2695 { 1283, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 488, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_ZERO_32_A32
2696 { 1282, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_V128_A64_S
2697 { 1281, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 492, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_V128_A64
2698 { 1280, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_V128_A32_S
2699 { 1279, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 488, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_V128_A32
2700 { 1278, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 527, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_8_A64_S
2701 { 1277, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 521, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_8_A64
2702 { 1276, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 518, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_8_A32_S
2703 { 1275, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 512, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_8_A32
2704 { 1274, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 527, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_64_A64_S
2705 { 1273, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 521, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_64_A64
2706 { 1272, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 518, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_64_A32_S
2707 { 1271, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 512, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_64_A32
2708 { 1270, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 527, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_32_A64_S
2709 { 1269, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 521, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_32_A64
2710 { 1268, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 518, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_32_A32_S
2711 { 1267, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 512, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_32_A32
2712 { 1266, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 527, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_16_A64_S
2713 { 1265, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 521, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_16_A64
2714 { 1264, 3, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 518, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_16_A32_S
2715 { 1263, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 512, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_LANE_16_A32
2716 { 1262, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_I64_A64_S
2717 { 1261, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 214, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_I64_A64
2718 { 1260, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_I64_A32_S
2719 { 1259, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 210, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_I64_A32
2720 { 1258, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_I32_A64_S
2721 { 1257, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 204, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_I32_A64
2722 { 1256, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_I32_A32_S
2723 { 1255, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 198, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_I32_A32
2724 { 1254, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_F64_A64_S
2725 { 1253, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 508, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_F64_A64
2726 { 1252, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_F64_A32_S
2727 { 1251, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 504, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_F64_A32
2728 { 1250, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_F32_A64_S
2729 { 1249, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 500, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_F32_A64
2730 { 1248, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_F32_A32_S
2731 { 1247, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 496, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_F32_A32
2732 { 1246, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_F16_F32_A64_S
2733 { 1245, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 500, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_F16_F32_A64
2734 { 1244, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_F16_F32_A32_S
2735 { 1243, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 496, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_F16_F32_A32
2736 { 1242, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_U_I64x2_A64_S
2737 { 1241, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 492, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_U_I64x2_A64
2738 { 1240, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_U_I64x2_A32_S
2739 { 1239, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 488, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_U_I64x2_A32
2740 { 1238, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_U_I32x4_A64_S
2741 { 1237, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 492, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_U_I32x4_A64
2742 { 1236, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_U_I32x4_A32_S
2743 { 1235, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 488, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_U_I32x4_A32
2744 { 1234, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_U_I16x8_A64_S
2745 { 1233, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 492, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_U_I16x8_A64
2746 { 1232, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_U_I16x8_A32_S
2747 { 1231, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 488, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_U_I16x8_A32
2748 { 1230, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_S_I64x2_A64_S
2749 { 1229, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 492, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_S_I64x2_A64
2750 { 1228, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_S_I64x2_A32_S
2751 { 1227, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 488, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_S_I64x2_A32
2752 { 1226, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_S_I32x4_A64_S
2753 { 1225, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 492, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_S_I32x4_A64
2754 { 1224, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_S_I32x4_A32_S
2755 { 1223, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 488, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_S_I32x4_A32
2756 { 1222, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_S_I16x8_A64_S
2757 { 1221, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 492, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_S_I16x8_A64
2758 { 1220, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_S_I16x8_A32_S
2759 { 1219, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 488, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_EXTEND_S_I16x8_A32
2760 { 1218, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_U_I64_A64_S
2761 { 1217, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 214, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_U_I64_A64
2762 { 1216, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_U_I64_A32_S
2763 { 1215, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 210, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_U_I64_A32
2764 { 1214, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_U_I32_A64_S
2765 { 1213, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 204, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_U_I32_A64
2766 { 1212, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_U_I32_A32_S
2767 { 1211, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 198, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_U_I32_A32
2768 { 1210, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_S_I64_A64_S
2769 { 1209, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 214, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_S_I64_A64
2770 { 1208, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_S_I64_A32_S
2771 { 1207, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 210, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_S_I64_A32
2772 { 1206, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_S_I32_A64_S
2773 { 1205, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 204, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_S_I32_A64
2774 { 1204, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_S_I32_A32_S
2775 { 1203, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 198, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_S_I32_A32
2776 { 1202, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_SPLAT_A64_S
2777 { 1201, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 492, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_SPLAT_A64
2778 { 1200, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_SPLAT_A32_S
2779 { 1199, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 488, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD8_SPLAT_A32
2780 { 1198, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD64_SPLAT_A64_S
2781 { 1197, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 492, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD64_SPLAT_A64
2782 { 1196, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD64_SPLAT_A32_S
2783 { 1195, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 488, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD64_SPLAT_A32
2784 { 1194, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD32_U_I64_A64_S
2785 { 1193, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 214, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD32_U_I64_A64
2786 { 1192, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD32_U_I64_A32_S
2787 { 1191, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 210, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD32_U_I64_A32
2788 { 1190, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD32_S_I64_A64_S
2789 { 1189, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 214, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD32_S_I64_A64
2790 { 1188, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD32_S_I64_A32_S
2791 { 1187, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 210, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD32_S_I64_A32
2792 { 1186, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD32_SPLAT_A64_S
2793 { 1185, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 492, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD32_SPLAT_A64
2794 { 1184, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD32_SPLAT_A32_S
2795 { 1183, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 488, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD32_SPLAT_A32
2796 { 1182, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_U_I64_A64_S
2797 { 1181, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 214, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_U_I64_A64
2798 { 1180, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_U_I64_A32_S
2799 { 1179, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 210, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_U_I64_A32
2800 { 1178, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_U_I32_A64_S
2801 { 1177, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 204, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_U_I32_A64
2802 { 1176, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_U_I32_A32_S
2803 { 1175, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 198, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_U_I32_A32
2804 { 1174, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_S_I64_A64_S
2805 { 1173, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 214, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_S_I64_A64
2806 { 1172, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_S_I64_A32_S
2807 { 1171, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 210, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_S_I64_A32
2808 { 1170, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_S_I32_A64_S
2809 { 1169, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 204, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_S_I32_A64
2810 { 1168, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_S_I32_A32_S
2811 { 1167, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 198, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_S_I32_A32
2812 { 1166, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_SPLAT_A64_S
2813 { 1165, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 492, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_SPLAT_A64
2814 { 1164, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_SPLAT_A32_S
2815 { 1163, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 488, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD16_SPLAT_A32
2816 { 1162, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_U_I8x16_S
2817 { 1161, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_U_I8x16
2818 { 1160, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_U_I64_S
2819 { 1159, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 405, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_U_I64
2820 { 1158, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_U_I32x4_S
2821 { 1157, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_U_I32x4
2822 { 1156, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_U_I32_S
2823 { 1155, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 174, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_U_I32
2824 { 1154, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_U_I16x8_S
2825 { 1153, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_U_I16x8
2826 { 1152, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_S_I8x16_S
2827 { 1151, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_S_I8x16
2828 { 1150, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_S_I64x2_S
2829 { 1149, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_S_I64x2
2830 { 1148, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_S_I64_S
2831 { 1147, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 405, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_S_I64
2832 { 1146, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_S_I32x4_S
2833 { 1145, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_S_I32x4
2834 { 1144, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_S_I32_S
2835 { 1143, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 174, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_S_I32
2836 { 1142, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_S_I16x8_S
2837 { 1141, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_S_I16x8
2838 { 1140, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_F64x2_S
2839 { 1139, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_F64x2
2840 { 1138, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_F64_S
2841 { 1137, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 402, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_F64
2842 { 1136, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_F32x4_S
2843 { 1135, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_F32x4
2844 { 1134, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_F32_S
2845 { 1133, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 399, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_F32
2846 { 1132, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_F16x8_S
2847 { 1131, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE_F16x8
2848 { 1130, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LANESELECT_I8x16_S
2849 { 1129, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 278, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LANESELECT_I8x16
2850 { 1128, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LANESELECT_I64x2_S
2851 { 1127, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 278, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LANESELECT_I64x2
2852 { 1126, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LANESELECT_I32x4_S
2853 { 1125, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 278, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LANESELECT_I32x4
2854 { 1124, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LANESELECT_I16x8_S
2855 { 1123, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 278, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LANESELECT_I16x8
2856 { 1122, 1, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 282, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // IF_S
2857 { 1121, 2, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 486, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // IF
2858 { 1120, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_U_SAT_F64_S
2859 { 1119, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 439, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_U_SAT_F64
2860 { 1118, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_U_SAT_F32_S
2861 { 1117, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 437, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_U_SAT_F32
2862 { 1116, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_U_F64_S
2863 { 1115, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 439, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_U_F64
2864 { 1114, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_U_F32_S
2865 { 1113, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 437, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_U_F32
2866 { 1112, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_S_SAT_F64_S
2867 { 1111, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 439, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_S_SAT_F64
2868 { 1110, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_S_SAT_F32_S
2869 { 1109, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 437, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_S_SAT_F32
2870 { 1108, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_S_F64_S
2871 { 1107, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 439, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_S_F64
2872 { 1106, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_S_F32_S
2873 { 1105, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 437, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_TRUNC_S_F32
2874 { 1104, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_SUB128_S
2875 { 1103, 6, 2, 0, 0, 0, 1, WebAssemblyOpInfoBase + 474, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_SUB128
2876 { 1102, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_REINTERPRET_F64_S
2877 { 1101, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 439, 3, 0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_REINTERPRET_F64
2878 { 1100, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_MUL_WIDE_U_S
2879 { 1099, 4, 2, 0, 0, 0, 1, WebAssemblyOpInfoBase + 482, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_MUL_WIDE_U
2880 { 1098, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_MUL_WIDE_S_S
2881 { 1097, 4, 2, 0, 0, 0, 1, WebAssemblyOpInfoBase + 482, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_MUL_WIDE_S
2882 { 1096, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_EXTEND_U_I32_S
2883 { 1095, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 480, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_EXTEND_U_I32
2884 { 1094, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_EXTEND_S_I32_S
2885 { 1093, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 480, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_EXTEND_S_I32
2886 { 1092, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_EXTEND8_S_I64_S
2887 { 1091, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 294, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_EXTEND8_S_I64
2888 { 1090, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_EXTEND32_S_I64_S
2889 { 1089, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 294, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_EXTEND32_S_I64
2890 { 1088, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_EXTEND16_S_I64_S
2891 { 1087, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 294, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_EXTEND16_S_I64
2892 { 1086, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_ADD128_S
2893 { 1085, 6, 2, 0, 0, 0, 1, WebAssemblyOpInfoBase + 474, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I64_ADD128
2894 { 1084, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_WRAP_I64_S
2895 { 1083, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 397, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_WRAP_I64
2896 { 1082, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_U_SAT_F64_S
2897 { 1081, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 435, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_U_SAT_F64
2898 { 1080, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_U_SAT_F32_S
2899 { 1079, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 433, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_U_SAT_F32
2900 { 1078, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_U_F64_S
2901 { 1077, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 435, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_U_F64
2902 { 1076, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_U_F32_S
2903 { 1075, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 433, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_U_F32
2904 { 1074, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_S_SAT_F64_S
2905 { 1073, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 435, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_S_SAT_F64
2906 { 1072, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_S_SAT_F32_S
2907 { 1071, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 433, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_S_SAT_F32
2908 { 1070, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_S_F64_S
2909 { 1069, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 435, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_S_F64
2910 { 1068, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_S_F32_S
2911 { 1067, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 433, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_TRUNC_S_F32
2912 { 1066, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_REINTERPRET_F32_S
2913 { 1065, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 433, 3, 0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_REINTERPRET_F32
2914 { 1064, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_EXTEND8_S_I32_S
2915 { 1063, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 292, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_EXTEND8_S_I32
2916 { 1062, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_EXTEND16_S_I32_S
2917 { 1061, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 292, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // I32_EXTEND16_S_I32
2918 { 1060, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_U_I8x16_S
2919 { 1059, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_U_I8x16
2920 { 1058, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_U_I64_S
2921 { 1057, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 405, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_U_I64
2922 { 1056, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_U_I32x4_S
2923 { 1055, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_U_I32x4
2924 { 1054, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_U_I32_S
2925 { 1053, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 174, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_U_I32
2926 { 1052, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_U_I16x8_S
2927 { 1051, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_U_I16x8
2928 { 1050, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_S_I8x16_S
2929 { 1049, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_S_I8x16
2930 { 1048, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_S_I64x2_S
2931 { 1047, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_S_I64x2
2932 { 1046, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_S_I64_S
2933 { 1045, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 405, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_S_I64
2934 { 1044, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_S_I32x4_S
2935 { 1043, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_S_I32x4
2936 { 1042, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_S_I32_S
2937 { 1041, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 174, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_S_I32
2938 { 1040, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_S_I16x8_S
2939 { 1039, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_S_I16x8
2940 { 1038, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_F64x2_S
2941 { 1037, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_F64x2
2942 { 1036, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_F64_S
2943 { 1035, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 402, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_F64
2944 { 1034, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_F32x4_S
2945 { 1033, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_F32x4
2946 { 1032, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_F32_S
2947 { 1031, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 399, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_F32
2948 { 1030, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_F16x8_S
2949 { 1029, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GT_F16x8
2950 { 1028, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 443, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_V128_S
2951 { 1027, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 472, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_V128
2952 { 1026, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 443, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_I64_S
2953 { 1025, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 470, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_I64
2954 { 1024, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 443, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_I32_S
2955 { 1023, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 468, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_I32
2956 { 1022, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 443, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_FUNCREF_S
2957 { 1021, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 466, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_FUNCREF
2958 { 1020, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 443, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_F64_S
2959 { 1019, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 464, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_F64
2960 { 1018, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 443, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_F32_S
2961 { 1017, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 462, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_F32
2962 { 1016, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 443, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_EXTERNREF_S
2963 { 1015, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 460, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_EXTERNREF
2964 { 1014, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 443, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_EXNREF_S
2965 { 1013, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 458, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_SET_EXNREF
2966 { 1012, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 443, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_V128_S
2967 { 1011, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 456, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_V128
2968 { 1010, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 443, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_I64_S
2969 { 1009, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 454, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_I64
2970 { 1008, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 443, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_I32_S
2971 { 1007, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 452, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_I32
2972 { 1006, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 443, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_FUNCREF_S
2973 { 1005, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 450, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_FUNCREF
2974 { 1004, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 443, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_F64_S
2975 { 1003, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 448, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_F64
2976 { 1002, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 443, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_F32_S
2977 { 1001, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 446, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_F32
2978 { 1000, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 443, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_EXTERNREF_S
2979 { 999, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 444, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_EXTERNREF
2980 { 998, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 443, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_EXNREF_S
2981 { 997, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 441, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GLOBAL_GET_EXNREF
2982 { 996, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_U_I8x16_S
2983 { 995, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_U_I8x16
2984 { 994, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_U_I64_S
2985 { 993, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 405, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_U_I64
2986 { 992, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_U_I32x4_S
2987 { 991, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_U_I32x4
2988 { 990, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_U_I32_S
2989 { 989, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 174, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_U_I32
2990 { 988, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_U_I16x8_S
2991 { 987, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_U_I16x8
2992 { 986, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_S_I8x16_S
2993 { 985, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_S_I8x16
2994 { 984, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_S_I64x2_S
2995 { 983, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_S_I64x2
2996 { 982, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_S_I64_S
2997 { 981, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 405, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_S_I64
2998 { 980, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_S_I32x4_S
2999 { 979, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_S_I32x4
3000 { 978, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_S_I32_S
3001 { 977, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 174, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_S_I32
3002 { 976, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_S_I16x8_S
3003 { 975, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_S_I16x8
3004 { 974, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_F64x2_S
3005 { 973, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_F64x2
3006 { 972, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_F64_S
3007 { 971, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 402, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_F64
3008 { 970, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_F32x4_S
3009 { 969, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_F32x4
3010 { 968, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_F32_S
3011 { 967, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 399, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_F32
3012 { 966, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_F16x8_S
3013 { 965, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GE_F16x8
3014 { 964, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_UINT_I64_F64_S
3015 { 963, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 439, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_UINT_I64_F64
3016 { 962, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_UINT_I64_F32_S
3017 { 961, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 437, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_UINT_I64_F32
3018 { 960, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_UINT_I32_F64_S
3019 { 959, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 435, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_UINT_I32_F64
3020 { 958, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_UINT_I32_F32_S
3021 { 957, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 433, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_UINT_I32_F32
3022 { 956, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_SINT_I64_F64_S
3023 { 955, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 439, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_SINT_I64_F64
3024 { 954, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_SINT_I64_F32_S
3025 { 953, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 437, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_SINT_I64_F32
3026 { 952, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_SINT_I32_F64_S
3027 { 951, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 435, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_SINT_I32_F64
3028 { 950, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_SINT_I32_F32_S
3029 { 949, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 433, 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FP_TO_SINT_I32_F32
3030 { 948, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FLOOR_F64x2_S
3031 { 947, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FLOOR_F64x2
3032 { 946, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FLOOR_F64_S
3033 { 945, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 163, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FLOOR_F64
3034 { 944, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FLOOR_F32x4_S
3035 { 943, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FLOOR_F32x4
3036 { 942, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FLOOR_F32_S
3037 { 941, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FLOOR_F32
3038 { 940, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FLOOR_F16x8_S
3039 { 939, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FLOOR_F16x8
3040 { 938, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FALLTHROUGH_RETURN_S
3041 { 937, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FALLTHROUGH_RETURN
3042 { 936, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F64_REINTERPRET_I64_S
3043 { 935, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 429, 3, 0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F64_REINTERPRET_I64
3044 { 934, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F64_PROMOTE_F32_S
3045 { 933, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 431, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F64_PROMOTE_F32
3046 { 932, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F64_CONVERT_U_I64_S
3047 { 931, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 429, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F64_CONVERT_U_I64
3048 { 930, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F64_CONVERT_U_I32_S
3049 { 929, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 427, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F64_CONVERT_U_I32
3050 { 928, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F64_CONVERT_S_I64_S
3051 { 927, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 429, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F64_CONVERT_S_I64
3052 { 926, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F64_CONVERT_S_I32_S
3053 { 925, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 427, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F64_CONVERT_S_I32
3054 { 924, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F32_REINTERPRET_I32_S
3055 { 923, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 421, 3, 0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F32_REINTERPRET_I32
3056 { 922, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F32_DEMOTE_F64_S
3057 { 921, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 425, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F32_DEMOTE_F64
3058 { 920, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F32_CONVERT_U_I64_S
3059 { 919, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 423, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F32_CONVERT_U_I64
3060 { 918, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F32_CONVERT_U_I32_S
3061 { 917, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 421, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F32_CONVERT_U_I32
3062 { 916, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F32_CONVERT_S_I64_S
3063 { 915, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 423, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F32_CONVERT_S_I64
3064 { 914, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F32_CONVERT_S_I32_S
3065 { 913, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 421, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // F32_CONVERT_S_I32
3066 { 912, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 411, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_I8x16_u_S
3067 { 911, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 415, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_I8x16_u
3068 { 910, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 411, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_I8x16_s_S
3069 { 909, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 415, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_I8x16_s
3070 { 908, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 411, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_I64x2_S
3071 { 907, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 418, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_I64x2
3072 { 906, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 411, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_I32x4_S
3073 { 905, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 415, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_I32x4
3074 { 904, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 411, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_I16x8_u_S
3075 { 903, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 415, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_I16x8_u
3076 { 902, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 411, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_I16x8_s_S
3077 { 901, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 415, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_I16x8_s
3078 { 900, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 411, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_F64x2_S
3079 { 899, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 412, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_F64x2
3080 { 898, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 411, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_F32x4_S
3081 { 897, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 408, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_F32x4
3082 { 896, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 411, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_F16x8_S
3083 { 895, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 408, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_LANE_F16x8
3084 { 894, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_LOW_U_I64x2_S
3085 { 893, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_LOW_U_I64x2
3086 { 892, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_LOW_U_I32x4_S
3087 { 891, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_LOW_U_I32x4
3088 { 890, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_LOW_U_I16x8_S
3089 { 889, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_LOW_U_I16x8
3090 { 888, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_LOW_S_I64x2_S
3091 { 887, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_LOW_S_I64x2
3092 { 886, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_LOW_S_I32x4_S
3093 { 885, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_LOW_S_I32x4
3094 { 884, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_LOW_S_I16x8_S
3095 { 883, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_LOW_S_I16x8
3096 { 882, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_HIGH_U_I64x2_S
3097 { 881, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_HIGH_U_I64x2
3098 { 880, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_HIGH_U_I32x4_S
3099 { 879, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_HIGH_U_I32x4
3100 { 878, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_HIGH_U_I16x8_S
3101 { 877, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_HIGH_U_I16x8
3102 { 876, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_HIGH_S_I64x2_S
3103 { 875, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_HIGH_S_I64x2
3104 { 874, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_HIGH_S_I32x4_S
3105 { 873, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_HIGH_S_I32x4
3106 { 872, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_HIGH_S_I16x8_S
3107 { 871, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTMUL_HIGH_S_I16x8
3108 { 870, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_I8x16_S
3109 { 869, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_I8x16
3110 { 868, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_I64x2_S
3111 { 867, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_I64x2
3112 { 866, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_I64_S
3113 { 865, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 405, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_I64
3114 { 864, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_I32x4_S
3115 { 863, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_I32x4
3116 { 862, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_I32_S
3117 { 861, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 174, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_I32
3118 { 860, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_I16x8_S
3119 { 859, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_I16x8
3120 { 858, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_F64x2_S
3121 { 857, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_F64x2
3122 { 856, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_F64_S
3123 { 855, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 402, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_F64
3124 { 854, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_F32x4_S
3125 { 853, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_F32x4
3126 { 852, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_F32_S
3127 { 851, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 399, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_F32
3128 { 850, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_F16x8_S
3129 { 849, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQ_F16x8
3130 { 848, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQZ_I64_S
3131 { 847, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 397, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQZ_I64
3132 { 846, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQZ_I32_S
3133 { 845, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 292, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EQZ_I32
3134 { 844, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_TRY_TABLE_S
3135 { 843, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_TRY_TABLE
3136 { 842, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_TRY_S
3137 { 841, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_TRY
3138 { 840, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_S
3139 { 839, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_LOOP_S
3140 { 838, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_LOOP
3141 { 837, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_IF_S
3142 { 836, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_IF
3143 { 835, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_FUNCTION_S
3144 { 834, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_FUNCTION
3145 { 833, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_BLOCK_S
3146 { 832, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END_BLOCK
3147 { 831, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // END
3148 { 830, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ELSE_S
3149 { 829, 0, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 1, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ELSE
3150 { 828, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_V128_S
3151 { 827, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 396, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_V128
3152 { 826, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_I64_S
3153 { 825, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 287, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_I64
3154 { 824, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_I32_S
3155 { 823, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 285, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_I32
3156 { 822, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_FUNCREF_S
3157 { 821, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 395, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_FUNCREF
3158 { 820, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_F64_S
3159 { 819, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 394, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_F64
3160 { 818, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_F32_S
3161 { 817, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 393, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_F32
3162 { 816, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_EXTERNREF_S
3163 { 815, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 392, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_EXTERNREF
3164 { 814, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_EXNREF_S
3165 { 813, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 291, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DROP_EXNREF
3166 { 812, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DOT_S
3167 { 811, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DOT
3168 { 810, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_U_I64_S
3169 { 809, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 177, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_U_I64
3170 { 808, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_U_I32_S
3171 { 807, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 174, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_U_I32
3172 { 806, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_S_I64_S
3173 { 805, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 177, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_S_I64
3174 { 804, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_S_I32_S
3175 { 803, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 174, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_S_I32
3176 { 802, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_F64x2_S
3177 { 801, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_F64x2
3178 { 800, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_F64_S
3179 { 799, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 171, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_F64
3180 { 798, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_F32x4_S
3181 { 797, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_F32x4
3182 { 796, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_F32_S
3183 { 795, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 168, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_F32
3184 { 794, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_F16x8_S
3185 { 793, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_F16x8
3186 { 792, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 158, 3, 0|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DELEGATE_S
3187 { 791, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 158, 3, 0|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DELEGATE
3188 { 790, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Trap)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DEBUG_UNREACHABLE_S
3189 { 789, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Trap)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DEBUG_UNREACHABLE
3190 { 788, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 304, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DATA_DROP_S
3191 { 787, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 304, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DATA_DROP
3192 { 786, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CTZ_I64_S
3193 { 785, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 294, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CTZ_I64
3194 { 784, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CTZ_I32_S
3195 { 783, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 292, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CTZ_I32
3196 { 782, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_V128_S
3197 { 781, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_V128
3198 { 780, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_I64_S
3199 { 779, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 294, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_I64
3200 { 778, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_I32_S
3201 { 777, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 292, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_I32
3202 { 776, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_FUNCREF_S
3203 { 775, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 390, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_FUNCREF
3204 { 774, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_F64_S
3205 { 773, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 163, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_F64
3206 { 772, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_F32_S
3207 { 771, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_F32
3208 { 770, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_EXTERNREF_S
3209 { 769, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 388, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_EXTERNREF
3210 { 768, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_EXNREF_S
3211 { 767, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 386, 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_EXNREF
3212 { 766, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPYSIGN_F64_S
3213 { 765, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 171, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPYSIGN_F64
3214 { 764, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPYSIGN_F32_S
3215 { 763, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 168, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPYSIGN_F32
3216 { 762, 16, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 370, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_V128_I8x16_S
3217 { 761, 17, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 353, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_V128_I8x16
3218 { 760, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 351, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_V128_I64x2_S
3219 { 759, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 348, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_V128_I64x2
3220 { 758, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 344, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_V128_I32x4_S
3221 { 757, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 339, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_V128_I32x4
3222 { 756, 8, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 331, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_V128_I16x8_S
3223 { 755, 9, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 322, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_V128_I16x8
3224 { 754, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 320, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_V128_F64x2_S
3225 { 753, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 317, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_V128_F64x2
3226 { 752, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 313, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_V128_F32x4_S
3227 { 751, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 308, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_V128_F32x4
3228 { 750, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 307, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_I64_S
3229 { 749, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 305, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_I64
3230 { 748, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 304, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_I32_S
3231 { 747, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 302, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_I32
3232 { 746, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 301, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_F64_S
3233 { 745, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 299, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_F64
3234 { 744, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 298, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_F32_S
3235 { 743, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 296, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CONST_F32
3236 { 742, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLZ_I64_S
3237 { 741, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 294, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLZ_I64
3238 { 740, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLZ_I32_S
3239 { 739, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 292, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLZ_I32
3240 { 738, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CEIL_F64x2_S
3241 { 737, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CEIL_F64x2
3242 { 736, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CEIL_F64_S
3243 { 735, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 163, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CEIL_F64
3244 { 734, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CEIL_F32x4_S
3245 { 733, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CEIL_F32x4
3246 { 732, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CEIL_F32_S
3247 { 731, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CEIL_F32
3248 { 730, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CEIL_F16x8_S
3249 { 729, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CEIL_F16x8
3250 { 728, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 290, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CATCH_S
3251 { 727, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 290, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CATCH_REF_S
3252 { 726, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 290, 3, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CATCH_REF
3253 { 725, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 290, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CATCH_LEGACY_S
3254 { 724, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 290, 3, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CATCH_LEGACY
3255 { 723, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CATCH_ALL_S
3256 { 722, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CATCH_ALL_REF_S
3257 { 721, 1, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 291, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CATCH_ALL_REF
3258 { 720, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CATCH_ALL_LEGACY_S
3259 { 719, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CATCH_ALL_LEGACY
3260 { 718, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CATCH_ALL
3261 { 717, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 290, 3, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CATCH
3262 { 716, 1, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 155, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CALL_S
3263 { 715, 2, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 288, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CALL_INDIRECT_S
3264 { 714, 2, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 288, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CALL_INDIRECT
3265 { 713, 1, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 155, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CALL
3266 { 712, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 158, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BR_UNLESS_S
3267 { 711, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 283, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BR_UNLESS
3268 { 710, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 286, 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BR_TABLE_I64_S
3269 { 709, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 287, 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BR_TABLE_I64
3270 { 708, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 286, 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BR_TABLE_I32_S
3271 { 707, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 285, 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BR_TABLE_I32
3272 { 706, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 158, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BR_S
3273 { 705, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 158, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BR_IF_S
3274 { 704, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 283, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BR_IF
3275 { 703, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 158, 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BR
3276 { 702, 1, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 282, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLOCK_S
3277 { 701, 1, 0, 0, 0, 1, 1, WebAssemblyOpInfoBase + 282, 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BLOCK
3278 { 700, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BITSELECT_S
3279 { 699, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 278, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BITSELECT
3280 { 698, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BITMASK_I8x16_S
3281 { 697, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 180, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BITMASK_I8x16
3282 { 696, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BITMASK_I64x2_S
3283 { 695, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 180, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BITMASK_I64x2
3284 { 694, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BITMASK_I32x4_S
3285 { 693, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 180, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BITMASK_I32x4
3286 { 692, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BITMASK_I16x8_S
3287 { 691, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 180, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BITMASK_I16x8
3288 { 690, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AVGR_U_I8x16_S
3289 { 689, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AVGR_U_I8x16
3290 { 688, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AVGR_U_I16x8_S
3291 { 687, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AVGR_U_I16x8
3292 { 686, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE_I64_A64_S
3293 { 685, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 274, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE_I64_A64
3294 { 684, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE_I64_A32_S
3295 { 683, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 270, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE_I64_A32
3296 { 682, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE_I32_A64_S
3297 { 681, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 266, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE_I32_A64
3298 { 680, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE_I32_A32_S
3299 { 679, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 262, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE_I32_A32
3300 { 678, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE8_I64_A64_S
3301 { 677, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 274, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE8_I64_A64
3302 { 676, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE8_I64_A32_S
3303 { 675, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 270, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE8_I64_A32
3304 { 674, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE8_I32_A64_S
3305 { 673, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 266, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE8_I32_A64
3306 { 672, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE8_I32_A32_S
3307 { 671, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 262, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE8_I32_A32
3308 { 670, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE32_I64_A64_S
3309 { 669, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 274, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE32_I64_A64
3310 { 668, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE32_I64_A32_S
3311 { 667, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 270, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE32_I64_A32
3312 { 666, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE16_I64_A64_S
3313 { 665, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 274, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE16_I64_A64
3314 { 664, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE16_I64_A32_S
3315 { 663, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 270, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE16_I64_A32
3316 { 662, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE16_I32_A64_S
3317 { 661, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 266, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE16_I32_A64
3318 { 660, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE16_I32_A32_S
3319 { 659, 4, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 262, 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_STORE16_I32_A32
3320 { 658, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XOR_I64_A64_S
3321 { 657, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XOR_I64_A64
3322 { 656, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XOR_I64_A32_S
3323 { 655, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 228, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XOR_I64_A32
3324 { 654, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XOR_I32_A64_S
3325 { 653, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 223, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XOR_I32_A64
3326 { 652, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XOR_I32_A32_S
3327 { 651, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 218, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XOR_I32_A32
3328 { 650, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XCHG_I64_A64_S
3329 { 649, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XCHG_I64_A64
3330 { 648, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XCHG_I64_A32_S
3331 { 647, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 228, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XCHG_I64_A32
3332 { 646, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XCHG_I32_A64_S
3333 { 645, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 223, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XCHG_I32_A64
3334 { 644, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XCHG_I32_A32_S
3335 { 643, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 218, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_XCHG_I32_A32
3336 { 642, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_SUB_I64_A64_S
3337 { 641, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_SUB_I64_A64
3338 { 640, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_SUB_I64_A32_S
3339 { 639, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 228, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_SUB_I64_A32
3340 { 638, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_SUB_I32_A64_S
3341 { 637, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 223, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_SUB_I32_A64
3342 { 636, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_SUB_I32_A32_S
3343 { 635, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 218, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_SUB_I32_A32
3344 { 634, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_OR_I64_A64_S
3345 { 633, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_OR_I64_A64
3346 { 632, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_OR_I64_A32_S
3347 { 631, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 228, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_OR_I64_A32
3348 { 630, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_OR_I32_A64_S
3349 { 629, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 223, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_OR_I32_A64
3350 { 628, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_OR_I32_A32_S
3351 { 627, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 218, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_OR_I32_A32
3352 { 626, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_CMPXCHG_I64_A64_S
3353 { 625, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 256, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_CMPXCHG_I64_A64
3354 { 624, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_CMPXCHG_I64_A32_S
3355 { 623, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 250, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_CMPXCHG_I64_A32
3356 { 622, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_CMPXCHG_I32_A64_S
3357 { 621, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 244, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_CMPXCHG_I32_A64
3358 { 620, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_CMPXCHG_I32_A32_S
3359 { 619, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 238, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_CMPXCHG_I32_A32
3360 { 618, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_AND_I64_A64_S
3361 { 617, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_AND_I64_A64
3362 { 616, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_AND_I64_A32_S
3363 { 615, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 228, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_AND_I64_A32
3364 { 614, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_AND_I32_A64_S
3365 { 613, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 223, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_AND_I32_A64
3366 { 612, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_AND_I32_A32_S
3367 { 611, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 218, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_AND_I32_A32
3368 { 610, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_ADD_I64_A64_S
3369 { 609, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_ADD_I64_A64
3370 { 608, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_ADD_I64_A32_S
3371 { 607, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 228, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_ADD_I64_A32
3372 { 606, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_ADD_I32_A64_S
3373 { 605, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 223, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_ADD_I32_A64
3374 { 604, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_ADD_I32_A32_S
3375 { 603, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 218, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW_ADD_I32_A32
3376 { 602, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XOR_I64_A64_S
3377 { 601, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XOR_I64_A64
3378 { 600, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XOR_I64_A32_S
3379 { 599, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 228, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XOR_I64_A32
3380 { 598, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XOR_I32_A64_S
3381 { 597, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 223, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XOR_I32_A64
3382 { 596, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XOR_I32_A32_S
3383 { 595, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 218, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XOR_I32_A32
3384 { 594, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XCHG_I64_A64_S
3385 { 593, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XCHG_I64_A64
3386 { 592, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XCHG_I64_A32_S
3387 { 591, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 228, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XCHG_I64_A32
3388 { 590, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XCHG_I32_A64_S
3389 { 589, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 223, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XCHG_I32_A64
3390 { 588, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XCHG_I32_A32_S
3391 { 587, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 218, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_XCHG_I32_A32
3392 { 586, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_SUB_I64_A64_S
3393 { 585, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_SUB_I64_A64
3394 { 584, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_SUB_I64_A32_S
3395 { 583, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 228, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_SUB_I64_A32
3396 { 582, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_SUB_I32_A64_S
3397 { 581, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 223, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_SUB_I32_A64
3398 { 580, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_SUB_I32_A32_S
3399 { 579, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 218, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_SUB_I32_A32
3400 { 578, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_OR_I64_A64_S
3401 { 577, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_OR_I64_A64
3402 { 576, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_OR_I64_A32_S
3403 { 575, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 228, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_OR_I64_A32
3404 { 574, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_OR_I32_A64_S
3405 { 573, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 223, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_OR_I32_A64
3406 { 572, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_OR_I32_A32_S
3407 { 571, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 218, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_OR_I32_A32
3408 { 570, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_CMPXCHG_I64_A64_S
3409 { 569, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 256, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_CMPXCHG_I64_A64
3410 { 568, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_CMPXCHG_I64_A32_S
3411 { 567, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 250, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_CMPXCHG_I64_A32
3412 { 566, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_CMPXCHG_I32_A64_S
3413 { 565, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 244, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_CMPXCHG_I32_A64
3414 { 564, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_CMPXCHG_I32_A32_S
3415 { 563, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 238, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_CMPXCHG_I32_A32
3416 { 562, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_AND_I64_A64_S
3417 { 561, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_AND_I64_A64
3418 { 560, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_AND_I64_A32_S
3419 { 559, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 228, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_AND_I64_A32
3420 { 558, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_AND_I32_A64_S
3421 { 557, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 223, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_AND_I32_A64
3422 { 556, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_AND_I32_A32_S
3423 { 555, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 218, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_AND_I32_A32
3424 { 554, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_ADD_I64_A64_S
3425 { 553, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_ADD_I64_A64
3426 { 552, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_ADD_I64_A32_S
3427 { 551, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 228, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_ADD_I64_A32
3428 { 550, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_ADD_I32_A64_S
3429 { 549, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 223, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_ADD_I32_A64
3430 { 548, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_ADD_I32_A32_S
3431 { 547, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 218, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW8_U_ADD_I32_A32
3432 { 546, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_XOR_I64_A64_S
3433 { 545, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_XOR_I64_A64
3434 { 544, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_XOR_I64_A32_S
3435 { 543, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 228, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_XOR_I64_A32
3436 { 542, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_XCHG_I64_A64_S
3437 { 541, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_XCHG_I64_A64
3438 { 540, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_XCHG_I64_A32_S
3439 { 539, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 228, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_XCHG_I64_A32
3440 { 538, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_SUB_I64_A64_S
3441 { 537, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_SUB_I64_A64
3442 { 536, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_SUB_I64_A32_S
3443 { 535, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 228, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_SUB_I64_A32
3444 { 534, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_OR_I64_A64_S
3445 { 533, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_OR_I64_A64
3446 { 532, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_OR_I64_A32_S
3447 { 531, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 228, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_OR_I64_A32
3448 { 530, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_CMPXCHG_I64_A64_S
3449 { 529, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 256, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_CMPXCHG_I64_A64
3450 { 528, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_CMPXCHG_I64_A32_S
3451 { 527, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 250, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_CMPXCHG_I64_A32
3452 { 526, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_AND_I64_A64_S
3453 { 525, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_AND_I64_A64
3454 { 524, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_AND_I64_A32_S
3455 { 523, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 228, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_AND_I64_A32
3456 { 522, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_ADD_I64_A64_S
3457 { 521, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_ADD_I64_A64
3458 { 520, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_ADD_I64_A32_S
3459 { 519, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 228, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW32_U_ADD_I64_A32
3460 { 518, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XOR_I64_A64_S
3461 { 517, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XOR_I64_A64
3462 { 516, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XOR_I64_A32_S
3463 { 515, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 228, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XOR_I64_A32
3464 { 514, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XOR_I32_A64_S
3465 { 513, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 223, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XOR_I32_A64
3466 { 512, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XOR_I32_A32_S
3467 { 511, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 218, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XOR_I32_A32
3468 { 510, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XCHG_I64_A64_S
3469 { 509, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XCHG_I64_A64
3470 { 508, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XCHG_I64_A32_S
3471 { 507, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 228, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XCHG_I64_A32
3472 { 506, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XCHG_I32_A64_S
3473 { 505, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 223, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XCHG_I32_A64
3474 { 504, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XCHG_I32_A32_S
3475 { 503, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 218, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_XCHG_I32_A32
3476 { 502, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_SUB_I64_A64_S
3477 { 501, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_SUB_I64_A64
3478 { 500, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_SUB_I64_A32_S
3479 { 499, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 228, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_SUB_I64_A32
3480 { 498, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_SUB_I32_A64_S
3481 { 497, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 223, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_SUB_I32_A64
3482 { 496, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_SUB_I32_A32_S
3483 { 495, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 218, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_SUB_I32_A32
3484 { 494, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_OR_I64_A64_S
3485 { 493, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_OR_I64_A64
3486 { 492, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_OR_I64_A32_S
3487 { 491, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 228, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_OR_I64_A32
3488 { 490, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_OR_I32_A64_S
3489 { 489, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 223, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_OR_I32_A64
3490 { 488, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_OR_I32_A32_S
3491 { 487, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 218, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_OR_I32_A32
3492 { 486, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_CMPXCHG_I64_A64_S
3493 { 485, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 256, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_CMPXCHG_I64_A64
3494 { 484, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_CMPXCHG_I64_A32_S
3495 { 483, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 250, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_CMPXCHG_I64_A32
3496 { 482, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_CMPXCHG_I32_A64_S
3497 { 481, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 244, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_CMPXCHG_I32_A64
3498 { 480, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_CMPXCHG_I32_A32_S
3499 { 479, 6, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 238, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_CMPXCHG_I32_A32
3500 { 478, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_AND_I64_A64_S
3501 { 477, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_AND_I64_A64
3502 { 476, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_AND_I64_A32_S
3503 { 475, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 228, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_AND_I64_A32
3504 { 474, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_AND_I32_A64_S
3505 { 473, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 223, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_AND_I32_A64
3506 { 472, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_AND_I32_A32_S
3507 { 471, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 218, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_AND_I32_A32
3508 { 470, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_ADD_I64_A64_S
3509 { 469, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 233, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_ADD_I64_A64
3510 { 468, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_ADD_I64_A32_S
3511 { 467, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 228, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_ADD_I64_A32
3512 { 466, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_ADD_I32_A64_S
3513 { 465, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 223, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_ADD_I32_A64
3514 { 464, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_ADD_I32_A32_S
3515 { 463, 5, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 218, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_RMW16_U_ADD_I32_A32
3516 { 462, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD_I64_A64_S
3517 { 461, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 214, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD_I64_A64
3518 { 460, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD_I64_A32_S
3519 { 459, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 210, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD_I64_A32
3520 { 458, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD_I32_A64_S
3521 { 457, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 204, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD_I32_A64
3522 { 456, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD_I32_A32_S
3523 { 455, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 198, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD_I32_A32
3524 { 454, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD8_U_I64_A64_S
3525 { 453, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 214, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD8_U_I64_A64
3526 { 452, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD8_U_I64_A32_S
3527 { 451, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 210, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD8_U_I64_A32
3528 { 450, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD8_U_I32_A64_S
3529 { 449, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 204, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD8_U_I32_A64
3530 { 448, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD8_U_I32_A32_S
3531 { 447, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 198, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD8_U_I32_A32
3532 { 446, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD32_U_I64_A64_S
3533 { 445, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 214, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD32_U_I64_A64
3534 { 444, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD32_U_I64_A32_S
3535 { 443, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 210, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD32_U_I64_A32
3536 { 442, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD16_U_I64_A64_S
3537 { 441, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 214, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD16_U_I64_A64
3538 { 440, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD16_U_I64_A32_S
3539 { 439, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 210, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD16_U_I64_A32
3540 { 438, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 208, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD16_U_I32_A64_S
3541 { 437, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 204, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD16_U_I32_A64
3542 { 436, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 202, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD16_U_I32_A32_S
3543 { 435, 4, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 198, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_LOAD16_U_I32_A32
3544 { 434, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_FENCE_S
3545 { 433, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ATOMIC_FENCE
3546 { 432, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v8i16_S
3547 { 431, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 196, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v8i16
3548 { 430, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v8f16_S
3549 { 429, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 196, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v8f16
3550 { 428, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v4i32_S
3551 { 427, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 196, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v4i32
3552 { 426, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v4f32_S
3553 { 425, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 196, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v4f32
3554 { 424, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v2i64_S
3555 { 423, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 196, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v2i64
3556 { 422, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v2f64_S
3557 { 421, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 196, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v2f64
3558 { 420, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v16i8_S
3559 { 419, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 196, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_v16i8
3560 { 418, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_i64_S
3561 { 417, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 194, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_i64
3562 { 416, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_i32_S
3563 { 415, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 192, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_i32
3564 { 414, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_funcref_S
3565 { 413, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 190, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_funcref
3566 { 412, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_f64_S
3567 { 411, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 188, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_f64
3568 { 410, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_f32_S
3569 { 409, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 186, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_f32
3570 { 408, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_externref_S
3571 { 407, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 184, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_externref
3572 { 406, 1, 0, 0, 0, 1, 0, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_exnref_S
3573 { 405, 2, 1, 0, 0, 1, 0, WebAssemblyOpInfoBase + 182, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARGUMENT_exnref
3574 { 404, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANYTRUE_S
3575 { 403, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 180, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANYTRUE
3576 { 402, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_S
3577 { 401, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_I64_S
3578 { 400, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 177, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_I64
3579 { 399, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_I32_S
3580 { 398, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 174, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_I32
3581 { 397, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANDNOT_S
3582 { 396, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANDNOT
3583 { 395, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND
3584 { 394, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ALLTRUE_I8x16_S
3585 { 393, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 180, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ALLTRUE_I8x16
3586 { 392, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ALLTRUE_I64x2_S
3587 { 391, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 180, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ALLTRUE_I64x2
3588 { 390, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ALLTRUE_I32x4_S
3589 { 389, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 180, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ALLTRUE_I32x4
3590 { 388, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ALLTRUE_I16x8_S
3591 { 387, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 180, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ALLTRUE_I16x8
3592 { 386, 2, 0, 0, 0, 2, 2, WebAssemblyOpInfoBase + 24, 4, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKUP_S
3593 { 385, 2, 0, 0, 0, 2, 2, WebAssemblyOpInfoBase + 24, 4, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKUP
3594 { 384, 2, 0, 0, 0, 2, 2, WebAssemblyOpInfoBase + 24, 4, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKDOWN_S
3595 { 383, 2, 0, 0, 0, 2, 2, WebAssemblyOpInfoBase + 24, 4, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKDOWN
3596 { 382, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_SAT_U_I8x16_S
3597 { 381, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_SAT_U_I8x16
3598 { 380, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_SAT_U_I16x8_S
3599 { 379, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_SAT_U_I16x8
3600 { 378, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_SAT_S_I8x16_S
3601 { 377, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_SAT_S_I8x16
3602 { 376, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_SAT_S_I16x8_S
3603 { 375, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_SAT_S_I16x8
3604 { 374, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I8x16_S
3605 { 373, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I8x16
3606 { 372, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I64x2_S
3607 { 371, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I64x2
3608 { 370, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I64_S
3609 { 369, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 177, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I64
3610 { 368, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I32x4_S
3611 { 367, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I32x4
3612 { 366, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I32_S
3613 { 365, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 174, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I32
3614 { 364, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I16x8_S
3615 { 363, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_I16x8
3616 { 362, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F64x2_S
3617 { 361, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F64x2
3618 { 360, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F64_S
3619 { 359, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 171, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F64
3620 { 358, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F32x4_S
3621 { 357, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F32x4
3622 { 356, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F32_S
3623 { 355, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 168, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F32
3624 { 354, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F16x8_S
3625 { 353, 3, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 165, 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_F16x8
3626 { 352, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_I8x16_S
3627 { 351, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_I8x16
3628 { 350, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_I64x2_S
3629 { 349, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_I64x2
3630 { 348, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_I32x4_S
3631 { 347, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_I32x4
3632 { 346, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_I16x8_S
3633 { 345, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_I16x8
3634 { 344, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_F64x2_S
3635 { 343, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_F64x2
3636 { 342, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_F64_S
3637 { 341, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 163, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_F64
3638 { 340, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_F32x4_S
3639 { 339, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_F32x4
3640 { 338, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_F32_S
3641 { 337, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 161, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_F32
3642 { 336, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_F16x8_S
3643 { 335, 2, 1, 0, 0, 0, 1, WebAssemblyOpInfoBase + 159, 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ABS_F16x8
3644 { 334, 0, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // RET_CALL_RESULTS_S
3645 { 333, 0, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // RET_CALL_RESULTS
3646 { 332, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COMPILER_FENCE_S
3647 { 331, 0, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 1, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COMPILER_FENCE
3648 { 330, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 158, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLEANUPRET_S
3649 { 329, 1, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 158, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CLEANUPRET
3650 { 328, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 156, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CATCHRET_S
3651 { 327, 2, 0, 0, 0, 0, 1, WebAssemblyOpInfoBase + 156, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CATCHRET
3652 { 326, 0, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CALL_RESULTS_S
3653 { 325, 0, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // CALL_RESULTS
3654 { 324, 1, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CALL_PARAMS_S
3655 { 323, 1, 0, 0, 0, 2, 1, WebAssemblyOpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CALL_PARAMS
3656 { 322, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 151, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBFX
3657 { 321, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 151, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SBFX
3658 { 320, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMIN
3659 { 319, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMAX
3660 { 318, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMIN
3661 { 317, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMAX
3662 { 316, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_XOR
3663 { 315, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_OR
3664 { 314, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_AND
3665 { 313, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_MUL
3666 { 312, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_ADD
3667 { 311, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMINIMUM
3668 { 310, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAXIMUM
3669 { 309, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMIN
3670 { 308, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAX
3671 { 307, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMUL
3672 { 306, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FADD
3673 { 305, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 134, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FMUL
3674 { 304, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 134, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FADD
3675 { 303, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBSANTRAP
3676 { 302, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DEBUGTRAP
3677 { 301, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRAP
3678 { 300, 3, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 61, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BZERO
3679 { 299, 4, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET
3680 { 298, 4, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMMOVE
3681 { 297, 3, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 134, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY_INLINE
3682 { 296, 4, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY
3683 { 295, 2, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 145, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_WRITE_REGISTER
3684 { 294, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_READ_REGISTER
3685 { 293, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FLDEXP
3686 { 292, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSQRT
3687 { 291, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMA
3688 { 290, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FREM
3689 { 289, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FDIV
3690 { 288, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMUL
3691 { 287, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSUB
3692 { 286, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FADD
3693 { 285, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKRESTORE
3694 { 284, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKSAVE
3695 { 283, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 72, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DYN_STACKALLOC
3696 { 282, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_JUMP_TABLE
3697 { 281, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BLOCK_ADDR
3698 { 280, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADDRSPACE_CAST
3699 { 279, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEARBYINT
3700 { 278, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRINT
3701 { 277, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFLOOR
3702 { 276, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSQRT
3703 { 275, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTANH
3704 { 274, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINH
3705 { 273, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOSH
3706 { 272, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN2
3707 { 271, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN
3708 { 270, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FASIN
3709 { 269, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FACOS
3710 { 268, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTAN
3711 { 267, 3, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINCOS
3712 { 266, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSIN
3713 { 265, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOS
3714 { 264, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCEIL
3715 { 263, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITREVERSE
3716 { 262, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BSWAP
3717 { 261, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTPOP
3718 { 260, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLS
3719 { 259, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ_ZERO_UNDEF
3720 { 258, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ
3721 { 257, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ_ZERO_UNDEF
3722 { 256, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ
3723 { 255, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 141, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECTOR_COMPRESS
3724 { 254, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STEP_VECTOR
3725 { 253, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SPLAT_VECTOR
3726 { 252, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 137, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHUFFLE_VECTOR
3727 { 251, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 134, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_VECTOR_ELT
3728 { 250, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_VECTOR_ELT
3729 { 249, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 61, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_SUBVECTOR
3730 { 248, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_SUBVECTOR
3731 { 247, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VSCALE
3732 { 246, 3, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 127, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRJT
3733 { 245, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BR
3734 { 244, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LLROUND
3735 { 243, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LROUND
3736 { 242, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABS
3737 { 241, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMAX
3738 { 240, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMIN
3739 { 239, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMAX
3740 { 238, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMIN
3741 { 237, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRMASK
3742 { 236, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTR_ADD
3743 { 235, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_ROUNDING
3744 { 234, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_ROUNDING
3745 { 233, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPMODE
3746 { 232, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPMODE
3747 { 231, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPMODE
3748 { 230, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPENV
3749 { 229, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPENV
3750 { 228, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPENV
3751 { 227, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUMNUM
3752 { 226, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUMNUM
3753 { 225, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUM
3754 { 224, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUM
3755 { 223, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM_IEEE
3756 { 222, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM_IEEE
3757 { 221, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM
3758 { 220, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM
3759 { 219, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCANONICALIZE
3760 { 218, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 101, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IS_FPCLASS
3761 { 217, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOPYSIGN
3762 { 216, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FABS
3763 { 215, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI_SAT
3764 { 214, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI_SAT
3765 { 213, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UITOFP
3766 { 212, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SITOFP
3767 { 211, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI
3768 { 210, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI
3769 { 209, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNC
3770 { 208, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXT
3771 { 207, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEG
3772 { 206, 3, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFREXP
3773 { 205, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLDEXP
3774 { 204, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG10
3775 { 203, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG2
3776 { 202, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG
3777 { 201, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP10
3778 { 200, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP2
3779 { 199, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP
3780 { 198, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOWI
3781 { 197, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOW
3782 { 196, 3, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMODF
3783 { 195, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREM
3784 { 194, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FDIV
3785 { 193, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAD
3786 { 192, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMA
3787 { 191, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMUL
3788 { 190, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSUB
3789 { 189, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FADD
3790 { 188, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIXSAT
3791 { 187, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIXSAT
3792 { 186, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIX
3793 { 185, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIX
3794 { 184, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIXSAT
3795 { 183, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIXSAT
3796 { 182, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIX
3797 { 181, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIX
3798 { 180, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSHLSAT
3799 { 179, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USHLSAT
3800 { 178, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBSAT
3801 { 177, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBSAT
3802 { 176, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDSAT
3803 { 175, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDSAT
3804 { 174, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULH
3805 { 173, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULH
3806 { 172, 4, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULO
3807 { 171, 4, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULO
3808 { 170, 5, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 118, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBE
3809 { 169, 4, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBO
3810 { 168, 5, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 118, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDE
3811 { 167, 4, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDO
3812 { 166, 5, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 118, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBE
3813 { 165, 4, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBO
3814 { 164, 5, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 118, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDE
3815 { 163, 4, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDO
3816 { 162, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SELECT
3817 { 161, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 115, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UCMP
3818 { 160, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 115, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SCMP
3819 { 159, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCMP
3820 { 158, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ICMP
3821 { 157, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTL
3822 { 156, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTR
3823 { 155, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHR
3824 { 154, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHL
3825 { 153, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASHR
3826 { 152, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LSHR
3827 { 151, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHL
3828 { 150, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXT
3829 { 149, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 43, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT_INREG
3830 { 148, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT
3831 { 147, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 101, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VAARG
3832 { 146, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VASTART
3833 { 145, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCONSTANT
3834 { 144, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT
3835 { 143, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_USAT_U
3836 { 142, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_U
3837 { 141, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_S
3838 { 140, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC
3839 { 139, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ANYEXT
3840 { 138, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
3841 { 137, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT
3842 { 136, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_W_SIDE_EFFECTS
3843 { 135, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC
3844 { 134, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INVOKE_REGION_START
3845 { 133, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRINDIRECT
3846 { 132, 2, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRCOND
3847 { 131, 4, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PREFETCH
3848 { 130, 2, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 24, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FENCE
3849 { 129, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_SAT
3850 { 128, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_COND
3851 { 127, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UDEC_WRAP
3852 { 126, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UINC_WRAP
3853 { 125, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUM
3854 { 124, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUM
3855 { 123, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMIN
3856 { 122, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAX
3857 { 121, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FSUB
3858 { 120, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FADD
3859 { 119, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMIN
3860 { 118, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMAX
3861 { 117, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MIN
3862 { 116, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MAX
3863 { 115, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XOR
3864 { 114, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_OR
3865 { 113, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_NAND
3866 { 112, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_AND
3867 { 111, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_SUB
3868 { 110, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_ADD
3869 { 109, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XCHG
3870 { 108, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG
3871 { 107, 5, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 85, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
3872 { 106, 5, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 80, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_STORE
3873 { 105, 2, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STORE
3874 { 104, 5, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 75, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_ZEXTLOAD
3875 { 103, 5, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 75, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_SEXTLOAD
3876 { 102, 5, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 75, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_LOAD
3877 { 101, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXTLOAD
3878 { 100, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXTLOAD
3879 { 99, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LOAD
3880 { 98, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READSTEADYCOUNTER
3881 { 97, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READCYCLECOUNTER
3882 { 96, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUNDEVEN
3883 { 95, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LLRINT
3884 { 94, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LRINT
3885 { 93, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUND
3886 { 92, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_TRUNC
3887 { 91, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 72, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_FPTRUNC_ROUND
3888 { 90, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_FOLD_BARRIER
3889 { 89, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREEZE
3890 { 88, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITCAST
3891 { 87, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTTOPTR
3892 { 86, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRTOINT
3893 { 85, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONCAT_VECTORS
3894 { 84, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR_TRUNC
3895 { 83, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR
3896 { 82, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MERGE_VALUES
3897 { 81, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT
3898 { 80, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UNMERGE_VALUES
3899 { 79, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 61, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT
3900 { 78, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_POOL
3901 { 77, 5, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 56, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRAUTH_GLOBAL_VALUE
3902 { 76, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GLOBAL_VALUE
3903 { 75, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRAME_INDEX
3904 { 74, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PHI
3905 { 73, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IMPLICIT_DEF
3906 { 72, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGCEIL
3907 { 71, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGFLOOR
3908 { 70, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGCEIL
3909 { 69, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGFLOOR
3910 { 68, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDU
3911 { 67, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDS
3912 { 66, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_XOR
3913 { 65, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_OR
3914 { 64, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_AND
3915 { 63, 4, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVREM
3916 { 62, 4, 2, 0, 0, 0, 0, WebAssemblyOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVREM
3917 { 61, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UREM
3918 { 60, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SREM
3919 { 59, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIV
3920 { 58, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIV
3921 { 57, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MUL
3922 { 56, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SUB
3923 { 55, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADD
3924 { 54, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 43, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ALIGN
3925 { 53, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 43, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ZEXT
3926 { 52, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 43, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_SEXT
3927 { 51, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_GLUE
3928 { 50, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 13, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_LOOP
3929 { 49, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ANCHOR
3930 { 48, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ENTRY
3931 { 47, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELOC_NONE
3932 { 46, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUMP_TABLE_DEBUG_INFO
3933 { 45, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMBARRIER
3934 { 44, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAKE_USE
3935 { 43, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ICALL_BRANCH_FUNNEL
3936 { 42, 3, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 40, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_15548
3937 { 41, 2, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 38, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_15547
3938 { 40, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_TAIL_CALL
3939 { 39, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_EXIT
3940 { 38, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_RET
3941 { 37, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_ENTER
3942 { 36, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_OP
3943 { 35, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAULTING_OP
3944 { 34, 2, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 36, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_ESCAPE
3945 { 33, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STATEPOINT
3946 { 32, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 33, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_15546
3947 { 31, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PREALLOCATED_SETUP
3948 { 30, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 32, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14301
3949 { 29, 6, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 26, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHPOINT
3950 { 28, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FENTRY_CALL
3951 { 27, 2, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 24, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STACKMAP
3952 { 26, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 22, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARITH_FENCE
3953 { 25, 4, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 18, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PSEUDO_PROBE
3954 { 24, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_END
3955 { 23, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_START
3956 { 22, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BUNDLE
3957 { 21, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 15, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_LANEMASK
3958 { 20, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 13, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY
3959 { 19, 2, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 13, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REG_SEQUENCE
3960 { 18, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_LABEL
3961 { 17, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_PHI
3962 { 16, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_INSTR_REF
3963 { 15, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE_LIST
3964 { 14, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE
3965 { 13, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_TO_REGCLASS
3966 { 12, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBREG_TO_REG
3967 { 11, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INIT_UNDEF
3968 { 10, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // IMPLICIT_DEF
3969 { 9, 4, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 5, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INSERT_SUBREG
3970 { 8, 3, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_SUBREG
3971 { 7, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KILL
3972 { 6, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANNOTATION_LABEL
3973 { 5, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GC_LABEL
3974 { 4, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EH_LABEL
3975 { 3, 1, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CFI_INSTRUCTION
3976 { 2, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM_BR
3977 { 1, 0, 0, 0, 0, 0, 0, WebAssemblyOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM
3978 { 0, 1, 1, 0, 0, 0, 0, WebAssemblyOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PHI
3979 }, {
3980 /* 0 */
3981 /* 0 */ WebAssembly::SP32, WebAssembly::SP64, WebAssembly::ARGUMENTS,
3982 /* 3 */ WebAssembly::ARGUMENTS,
3983 /* 4 */ WebAssembly::SP32, WebAssembly::SP64, WebAssembly::SP32, WebAssembly::SP64,
3984 /* 8 */ WebAssembly::VALUE_STACK, WebAssembly::VALUE_STACK,
3985 }, {
3986 0
3987 }, {
3988 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
3989 /* 1 */
3990 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3991 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3992 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3993 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3994 /* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
3995 /* 15 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
3996 /* 18 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3997 /* 22 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
3998 /* 24 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3999 /* 26 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4000 /* 32 */ { WebAssembly::wasm_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 },
4001 /* 33 */ { WebAssembly::wasm_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4002 /* 36 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4003 /* 38 */ { WebAssembly::wasm_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4004 /* 40 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { WebAssembly::wasm_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4005 /* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
4006 /* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
4007 /* 49 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
4008 /* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
4009 /* 54 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4010 /* 56 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4011 /* 61 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
4012 /* 64 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
4013 /* 66 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
4014 /* 70 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
4015 /* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4016 /* 75 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4017 /* 80 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4018 /* 85 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
4019 /* 90 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
4020 /* 94 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
4021 /* 97 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4022 /* 101 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4023 /* 104 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
4024 /* 107 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
4025 /* 111 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
4026 /* 115 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
4027 /* 118 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
4028 /* 123 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
4029 /* 127 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
4030 /* 130 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
4031 /* 134 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
4032 /* 137 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4033 /* 141 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
4034 /* 145 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
4035 /* 147 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
4036 /* 151 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
4037 /* 155 */ { -1, 0, WebAssembly::OPERAND_FUNCTION32, 0 },
4038 /* 156 */ { -1, 0, WebAssembly::OPERAND_BASIC_BLOCK, 0 }, { -1, 0, WebAssembly::OPERAND_BASIC_BLOCK, 0 },
4039 /* 158 */ { -1, 0, WebAssembly::OPERAND_BASIC_BLOCK, 0 },
4040 /* 159 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4041 /* 161 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4042 /* 163 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4043 /* 165 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4044 /* 168 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4045 /* 171 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4046 /* 174 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4047 /* 177 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4048 /* 180 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4049 /* 182 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4050 /* 184 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4051 /* 186 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4052 /* 188 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4053 /* 190 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4054 /* 192 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4055 /* 194 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4056 /* 196 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4057 /* 198 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4058 /* 202 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 },
4059 /* 204 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4060 /* 208 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 },
4061 /* 210 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4062 /* 214 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4063 /* 218 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4064 /* 223 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4065 /* 228 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4066 /* 233 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4067 /* 238 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4068 /* 244 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4069 /* 250 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4070 /* 256 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4071 /* 262 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4072 /* 266 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4073 /* 270 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4074 /* 274 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4075 /* 278 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4076 /* 282 */ { -1, 0, WebAssembly::OPERAND_SIGNATURE, 0 },
4077 /* 283 */ { -1, 0, WebAssembly::OPERAND_BASIC_BLOCK, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4078 /* 285 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4079 /* 286 */ { -1, 0, WebAssembly::OPERAND_BRLIST, 0 },
4080 /* 287 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4081 /* 288 */ { -1, 0, WebAssembly::OPERAND_TYPEINDEX, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 },
4082 /* 290 */ { -1, 0, WebAssembly::OPERAND_TAG, 0 },
4083 /* 291 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4084 /* 292 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4085 /* 294 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4086 /* 296 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 },
4087 /* 298 */ { -1, 0, WebAssembly::OPERAND_F32IMM, 0 },
4088 /* 299 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_F64IMM, 0 },
4089 /* 301 */ { -1, 0, WebAssembly::OPERAND_F64IMM, 0 },
4090 /* 302 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_I32IMM, 0 },
4091 /* 304 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 },
4092 /* 305 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_I64IMM, 0 },
4093 /* 307 */ { -1, 0, WebAssembly::OPERAND_I64IMM, 0 },
4094 /* 308 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 },
4095 /* 313 */ { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 },
4096 /* 317 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_F64IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F64IMM, 0 },
4097 /* 320 */ { -1, 0, WebAssembly::OPERAND_F64IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F64IMM, 0 },
4098 /* 322 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 },
4099 /* 331 */ { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 },
4100 /* 339 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 },
4101 /* 344 */ { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 },
4102 /* 348 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I64IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I64IMM, 0 },
4103 /* 351 */ { -1, 0, WebAssembly::OPERAND_VEC_I64IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I64IMM, 0 },
4104 /* 353 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 },
4105 /* 370 */ { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 },
4106 /* 386 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4107 /* 388 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4108 /* 390 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4109 /* 392 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4110 /* 393 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4111 /* 394 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4112 /* 395 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4113 /* 396 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4114 /* 397 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4115 /* 399 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4116 /* 402 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4117 /* 405 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4118 /* 408 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 },
4119 /* 411 */ { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 },
4120 /* 412 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 },
4121 /* 415 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 },
4122 /* 418 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 },
4123 /* 421 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4124 /* 423 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4125 /* 425 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4126 /* 427 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4127 /* 429 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4128 /* 431 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4129 /* 433 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4130 /* 435 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4131 /* 437 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4132 /* 439 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4133 /* 441 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 },
4134 /* 443 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 },
4135 /* 444 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 },
4136 /* 446 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 },
4137 /* 448 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 },
4138 /* 450 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 },
4139 /* 452 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 },
4140 /* 454 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 },
4141 /* 456 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 },
4142 /* 458 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4143 /* 460 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4144 /* 462 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4145 /* 464 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4146 /* 466 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4147 /* 468 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4148 /* 470 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4149 /* 472 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4150 /* 474 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4151 /* 480 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4152 /* 482 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4153 /* 486 */ { -1, 0, WebAssembly::OPERAND_SIGNATURE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4154 /* 488 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4155 /* 492 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4156 /* 496 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4157 /* 500 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4158 /* 504 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4159 /* 508 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4160 /* 512 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4161 /* 518 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 },
4162 /* 521 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4163 /* 527 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 },
4164 /* 530 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 },
4165 /* 532 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 },
4166 /* 533 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 },
4167 /* 535 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 },
4168 /* 537 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 },
4169 /* 539 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 },
4170 /* 541 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 },
4171 /* 543 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 },
4172 /* 545 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 },
4173 /* 547 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4174 /* 549 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4175 /* 551 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4176 /* 553 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4177 /* 555 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4178 /* 557 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4179 /* 559 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4180 /* 561 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4181 /* 563 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4182 /* 566 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4183 /* 569 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4184 /* 572 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4185 /* 575 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4186 /* 578 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4187 /* 581 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4188 /* 584 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4189 /* 587 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4190 /* 592 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_I32IMM, 0 },
4191 /* 594 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4192 /* 599 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4193 /* 605 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4194 /* 611 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4195 /* 617 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4196 /* 623 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4197 /* 627 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4198 /* 631 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4199 /* 636 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_FUNCTION32, 0 },
4200 /* 638 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4201 /* 640 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4202 /* 642 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4203 /* 644 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TYPEINDEX, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4204 /* 647 */ { -1, 0, WebAssembly::OPERAND_TYPEINDEX, 0 },
4205 /* 648 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4206 /* 652 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4207 /* 656 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4208 /* 660 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4209 /* 664 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4210 /* 668 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4211 /* 672 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4212 /* 676 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4213 /* 680 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4214 /* 684 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4215 /* 688 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4216 /* 692 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4217 /* 696 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4218 /* 699 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 },
4219 /* 718 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4220 /* 720 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4221 /* 722 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4222 /* 724 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4223 /* 726 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4224 /* 730 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4225 /* 734 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4226 /* 738 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4227 /* 742 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4228 /* 747 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4229 /* 752 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4230 /* 756 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4231 /* 760 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4232 /* 765 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 },
4233 /* 767 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4234 /* 771 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 },
4235 /* 772 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4236 /* 776 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4237 /* 780 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4238 /* 783 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4239 /* 786 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4240 /* 789 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4241 /* 793 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4242 /* 797 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4243 /* 801 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4244 /* 804 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4245 /* 807 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4246 /* 810 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 },
4247 /* 812 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4248 /* 815 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4249 /* 818 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4250 /* 821 */ { -1, 0, WebAssembly::OPERAND_SIGNATURE, 0 }, { -1, 0, WebAssembly::OPERAND_CATCH_LIST, 0 },
4251 /* 823 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4252 /* 826 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4253 }
4254};
4255
4256
4257#ifdef __GNUC__
4258#pragma GCC diagnostic push
4259#pragma GCC diagnostic ignored "-Woverlength-strings"
4260#endif
4261extern const char WebAssemblyInstrNameData[] = {
4262 /* 0 */ "G_FLOG10\000"
4263 /* 9 */ "G_FEXP10\000"
4264 /* 18 */ "LOAD_F16_F32_A32\000"
4265 /* 35 */ "STORE_F16_F32_A32\000"
4266 /* 53 */ "LOAD_F32_A32\000"
4267 /* 66 */ "STORE_F32_A32\000"
4268 /* 80 */ "ATOMIC_STORE16_I32_A32\000"
4269 /* 103 */ "ATOMIC_STORE8_I32_A32\000"
4270 /* 125 */ "ATOMIC_RMW16_U_SUB_I32_A32\000"
4271 /* 152 */ "ATOMIC_RMW8_U_SUB_I32_A32\000"
4272 /* 178 */ "ATOMIC_RMW_SUB_I32_A32\000"
4273 /* 201 */ "ATOMIC_LOAD_I32_A32\000"
4274 /* 221 */ "ATOMIC_RMW16_U_ADD_I32_A32\000"
4275 /* 248 */ "ATOMIC_RMW8_U_ADD_I32_A32\000"
4276 /* 274 */ "ATOMIC_RMW_ADD_I32_A32\000"
4277 /* 297 */ "ATOMIC_RMW16_U_AND_I32_A32\000"
4278 /* 324 */ "ATOMIC_RMW8_U_AND_I32_A32\000"
4279 /* 350 */ "ATOMIC_RMW_AND_I32_A32\000"
4280 /* 373 */ "ATOMIC_STORE_I32_A32\000"
4281 /* 394 */ "ATOMIC_RMW16_U_CMPXCHG_I32_A32\000"
4282 /* 425 */ "ATOMIC_RMW8_U_CMPXCHG_I32_A32\000"
4283 /* 455 */ "ATOMIC_RMW_CMPXCHG_I32_A32\000"
4284 /* 482 */ "ATOMIC_RMW16_U_XCHG_I32_A32\000"
4285 /* 510 */ "ATOMIC_RMW8_U_XCHG_I32_A32\000"
4286 /* 537 */ "ATOMIC_RMW_XCHG_I32_A32\000"
4287 /* 561 */ "ATOMIC_RMW16_U_XOR_I32_A32\000"
4288 /* 588 */ "ATOMIC_RMW8_U_XOR_I32_A32\000"
4289 /* 614 */ "ATOMIC_RMW_XOR_I32_A32\000"
4290 /* 637 */ "ATOMIC_RMW16_U_OR_I32_A32\000"
4291 /* 663 */ "ATOMIC_RMW8_U_OR_I32_A32\000"
4292 /* 688 */ "ATOMIC_RMW_OR_I32_A32\000"
4293 /* 710 */ "LOAD16_S_I32_A32\000"
4294 /* 727 */ "LOAD8_S_I32_A32\000"
4295 /* 743 */ "ATOMIC_LOAD16_U_I32_A32\000"
4296 /* 767 */ "ATOMIC_LOAD8_U_I32_A32\000"
4297 /* 790 */ "MEMORY_ATOMIC_WAIT32_A32\000"
4298 /* 815 */ "LOAD_LANE_32_A32\000"
4299 /* 832 */ "LOAD_ZERO_32_A32\000"
4300 /* 849 */ "STORE_LANE_I64x2_A32\000"
4301 /* 870 */ "LOAD_EXTEND_S_I64x2_A32\000"
4302 /* 894 */ "LOAD_EXTEND_U_I64x2_A32\000"
4303 /* 918 */ "LOAD_F64_A32\000"
4304 /* 931 */ "STORE_F64_A32\000"
4305 /* 945 */ "ATOMIC_STORE32_I64_A32\000"
4306 /* 968 */ "ATOMIC_STORE16_I64_A32\000"
4307 /* 991 */ "ATOMIC_STORE8_I64_A32\000"
4308 /* 1013 */ "ATOMIC_RMW32_U_SUB_I64_A32\000"
4309 /* 1040 */ "ATOMIC_RMW16_U_SUB_I64_A32\000"
4310 /* 1067 */ "ATOMIC_RMW8_U_SUB_I64_A32\000"
4311 /* 1093 */ "ATOMIC_RMW_SUB_I64_A32\000"
4312 /* 1116 */ "ATOMIC_LOAD_I64_A32\000"
4313 /* 1136 */ "ATOMIC_RMW32_U_ADD_I64_A32\000"
4314 /* 1163 */ "ATOMIC_RMW16_U_ADD_I64_A32\000"
4315 /* 1190 */ "ATOMIC_RMW8_U_ADD_I64_A32\000"
4316 /* 1216 */ "ATOMIC_RMW_ADD_I64_A32\000"
4317 /* 1239 */ "ATOMIC_RMW32_U_AND_I64_A32\000"
4318 /* 1266 */ "ATOMIC_RMW16_U_AND_I64_A32\000"
4319 /* 1293 */ "ATOMIC_RMW8_U_AND_I64_A32\000"
4320 /* 1319 */ "ATOMIC_RMW_AND_I64_A32\000"
4321 /* 1342 */ "ATOMIC_STORE_I64_A32\000"
4322 /* 1363 */ "ATOMIC_RMW32_U_CMPXCHG_I64_A32\000"
4323 /* 1394 */ "ATOMIC_RMW16_U_CMPXCHG_I64_A32\000"
4324 /* 1425 */ "ATOMIC_RMW8_U_CMPXCHG_I64_A32\000"
4325 /* 1455 */ "ATOMIC_RMW_CMPXCHG_I64_A32\000"
4326 /* 1482 */ "ATOMIC_RMW32_U_XCHG_I64_A32\000"
4327 /* 1510 */ "ATOMIC_RMW16_U_XCHG_I64_A32\000"
4328 /* 1538 */ "ATOMIC_RMW8_U_XCHG_I64_A32\000"
4329 /* 1565 */ "ATOMIC_RMW_XCHG_I64_A32\000"
4330 /* 1589 */ "ATOMIC_RMW32_U_XOR_I64_A32\000"
4331 /* 1616 */ "ATOMIC_RMW16_U_XOR_I64_A32\000"
4332 /* 1643 */ "ATOMIC_RMW8_U_XOR_I64_A32\000"
4333 /* 1669 */ "ATOMIC_RMW_XOR_I64_A32\000"
4334 /* 1692 */ "ATOMIC_RMW32_U_OR_I64_A32\000"
4335 /* 1718 */ "ATOMIC_RMW16_U_OR_I64_A32\000"
4336 /* 1744 */ "ATOMIC_RMW8_U_OR_I64_A32\000"
4337 /* 1769 */ "ATOMIC_RMW_OR_I64_A32\000"
4338 /* 1791 */ "LOAD32_S_I64_A32\000"
4339 /* 1808 */ "LOAD16_S_I64_A32\000"
4340 /* 1825 */ "LOAD8_S_I64_A32\000"
4341 /* 1841 */ "ATOMIC_LOAD32_U_I64_A32\000"
4342 /* 1865 */ "ATOMIC_LOAD16_U_I64_A32\000"
4343 /* 1889 */ "ATOMIC_LOAD8_U_I64_A32\000"
4344 /* 1912 */ "MEMORY_ATOMIC_WAIT64_A32\000"
4345 /* 1937 */ "LOAD_LANE_64_A32\000"
4346 /* 1954 */ "LOAD_ZERO_64_A32\000"
4347 /* 1971 */ "STORE_LANE_I32x4_A32\000"
4348 /* 1992 */ "LOAD_EXTEND_S_I32x4_A32\000"
4349 /* 2016 */ "LOAD_EXTEND_U_I32x4_A32\000"
4350 /* 2040 */ "LOAD_LANE_16_A32\000"
4351 /* 2057 */ "STORE_LANE_I8x16_A32\000"
4352 /* 2078 */ "LOAD_V128_A32\000"
4353 /* 2092 */ "STORE_V128_A32\000"
4354 /* 2107 */ "LOAD_LANE_8_A32\000"
4355 /* 2123 */ "STORE_LANE_I16x8_A32\000"
4356 /* 2144 */ "LOAD_EXTEND_S_I16x8_A32\000"
4357 /* 2168 */ "LOAD_EXTEND_U_I16x8_A32\000"
4358 /* 2192 */ "anonymous_14734MEMORY_SIZE_A32\000"
4359 /* 2223 */ "MEMORY_FILL_A32\000"
4360 /* 2239 */ "LOAD32_SPLAT_A32\000"
4361 /* 2256 */ "LOAD64_SPLAT_A32\000"
4362 /* 2273 */ "LOAD16_SPLAT_A32\000"
4363 /* 2290 */ "LOAD8_SPLAT_A32\000"
4364 /* 2306 */ "MEMSET_A32\000"
4365 /* 2317 */ "MEMORY_INIT_A32\000"
4366 /* 2333 */ "anonymous_14734MEMORY_GROW_A32\000"
4367 /* 2364 */ "MEMORY_ATOMIC_NOTIFY_A32\000"
4368 /* 2389 */ "MEMCPY_A32\000"
4369 /* 2400 */ "MEMORY_COPY_A32\000"
4370 /* 2416 */ "FP_TO_SINT_I32_F32\000"
4371 /* 2435 */ "FP_TO_UINT_I32_F32\000"
4372 /* 2454 */ "FP_TO_SINT_I64_F32\000"
4373 /* 2473 */ "FP_TO_UINT_I64_F32\000"
4374 /* 2492 */ "SUB_F32\000"
4375 /* 2500 */ "TRUNC_F32\000"
4376 /* 2510 */ "ADD_F32\000"
4377 /* 2518 */ "LOCAL_TEE_F32\000"
4378 /* 2532 */ "GE_F32\000"
4379 /* 2539 */ "LE_F32\000"
4380 /* 2546 */ "NE_F32\000"
4381 /* 2553 */ "F64_PROMOTE_F32\000"
4382 /* 2569 */ "NEG_F32\000"
4383 /* 2577 */ "CEIL_F32\000"
4384 /* 2586 */ "MUL_F32\000"
4385 /* 2594 */ "COPYSIGN_F32\000"
4386 /* 2607 */ "MIN_F32\000"
4387 /* 2615 */ "DROP_F32\000"
4388 /* 2624 */ "EQ_F32\000"
4389 /* 2631 */ "FLOOR_F32\000"
4390 /* 2641 */ "ABS_F32\000"
4391 /* 2649 */ "I32_TRUNC_S_F32\000"
4392 /* 2665 */ "I64_TRUNC_S_F32\000"
4393 /* 2681 */ "I32_TRUNC_S_SAT_F32\000"
4394 /* 2701 */ "I64_TRUNC_S_SAT_F32\000"
4395 /* 2721 */ "I32_TRUNC_U_SAT_F32\000"
4396 /* 2741 */ "I64_TRUNC_U_SAT_F32\000"
4397 /* 2761 */ "SELECT_F32\000"
4398 /* 2772 */ "GLOBAL_GET_F32\000"
4399 /* 2787 */ "LOCAL_GET_F32\000"
4400 /* 2801 */ "I32_REINTERPRET_F32\000"
4401 /* 2821 */ "GLOBAL_SET_F32\000"
4402 /* 2836 */ "LOCAL_SET_F32\000"
4403 /* 2850 */ "GT_F32\000"
4404 /* 2857 */ "LT_F32\000"
4405 /* 2864 */ "SQRT_F32\000"
4406 /* 2873 */ "NEAREST_F32\000"
4407 /* 2885 */ "CONST_F32\000"
4408 /* 2895 */ "I32_TRUNC_U_F32\000"
4409 /* 2911 */ "I64_TRUNC_U_F32\000"
4410 /* 2927 */ "DIV_F32\000"
4411 /* 2935 */ "MAX_F32\000"
4412 /* 2943 */ "COPY_F32\000"
4413 /* 2952 */ "SUB_I32\000"
4414 /* 2960 */ "ADD_I32\000"
4415 /* 2968 */ "AND_I32\000"
4416 /* 2976 */ "LOCAL_TEE_I32\000"
4417 /* 2990 */ "BR_TABLE_I32\000"
4418 /* 3003 */ "NE_I32\000"
4419 /* 3010 */ "SHL_I32\000"
4420 /* 3018 */ "ROTL_I32\000"
4421 /* 3027 */ "MUL_I32\000"
4422 /* 3035 */ "DROP_I32\000"
4423 /* 3044 */ "EQ_I32\000"
4424 /* 3051 */ "XOR_I32\000"
4425 /* 3059 */ "ROTR_I32\000"
4426 /* 3068 */ "I32_EXTEND16_S_I32\000"
4427 /* 3087 */ "I32_EXTEND8_S_I32\000"
4428 /* 3105 */ "I64_EXTEND_S_I32\000"
4429 /* 3122 */ "GE_S_I32\000"
4430 /* 3131 */ "LE_S_I32\000"
4431 /* 3140 */ "REM_S_I32\000"
4432 /* 3150 */ "SHR_S_I32\000"
4433 /* 3160 */ "GT_S_I32\000"
4434 /* 3169 */ "LT_S_I32\000"
4435 /* 3178 */ "F32_CONVERT_S_I32\000"
4436 /* 3196 */ "F64_CONVERT_S_I32\000"
4437 /* 3214 */ "DIV_S_I32\000"
4438 /* 3224 */ "SELECT_I32\000"
4439 /* 3235 */ "GLOBAL_GET_I32\000"
4440 /* 3250 */ "LOCAL_GET_I32\000"
4441 /* 3264 */ "F32_REINTERPRET_I32\000"
4442 /* 3284 */ "GLOBAL_SET_I32\000"
4443 /* 3299 */ "LOCAL_SET_I32\000"
4444 /* 3313 */ "POPCNT_I32\000"
4445 /* 3324 */ "CONST_I32\000"
4446 /* 3334 */ "I64_EXTEND_U_I32\000"
4447 /* 3351 */ "GE_U_I32\000"
4448 /* 3360 */ "LE_U_I32\000"
4449 /* 3369 */ "REM_U_I32\000"
4450 /* 3379 */ "SHR_U_I32\000"
4451 /* 3389 */ "GT_U_I32\000"
4452 /* 3398 */ "LT_U_I32\000"
4453 /* 3407 */ "F32_CONVERT_U_I32\000"
4454 /* 3425 */ "F64_CONVERT_U_I32\000"
4455 /* 3443 */ "DIV_U_I32\000"
4456 /* 3453 */ "COPY_I32\000"
4457 /* 3462 */ "CLZ_I32\000"
4458 /* 3470 */ "EQZ_I32\000"
4459 /* 3478 */ "CTZ_I32\000"
4460 /* 3486 */ "ARGUMENT_v4f32\000"
4461 /* 3501 */ "ARGUMENT_f32\000"
4462 /* 3514 */ "ARGUMENT_v4i32\000"
4463 /* 3529 */ "ARGUMENT_i32\000"
4464 /* 3542 */ "G_FLOG2\000"
4465 /* 3550 */ "G_FATAN2\000"
4466 /* 3559 */ "G_FEXP2\000"
4467 /* 3567 */ "CONST_V128_F64x2\000"
4468 /* 3584 */ "SUB_F64x2\000"
4469 /* 3594 */ "TRUNC_F64x2\000"
4470 /* 3606 */ "NMADD_F64x2\000"
4471 /* 3618 */ "GE_F64x2\000"
4472 /* 3627 */ "LE_F64x2\000"
4473 /* 3636 */ "REPLACE_LANE_F64x2\000"
4474 /* 3655 */ "EXTRACT_LANE_F64x2\000"
4475 /* 3674 */ "NEG_F64x2\000"
4476 /* 3684 */ "CEIL_F64x2\000"
4477 /* 3695 */ "MUL_F64x2\000"
4478 /* 3705 */ "SIMD_RELAXED_FMIN_F64x2\000"
4479 /* 3729 */ "PMIN_F64x2\000"
4480 /* 3740 */ "EQ_F64x2\000"
4481 /* 3749 */ "FLOOR_F64x2\000"
4482 /* 3761 */ "ABS_F64x2\000"
4483 /* 3771 */ "SPLAT_F64x2\000"
4484 /* 3783 */ "GT_F64x2\000"
4485 /* 3792 */ "LT_F64x2\000"
4486 /* 3801 */ "SQRT_F64x2\000"
4487 /* 3812 */ "NEAREST_F64x2\000"
4488 /* 3826 */ "DIV_F64x2\000"
4489 /* 3836 */ "SIMD_RELAXED_FMAX_F64x2\000"
4490 /* 3860 */ "PMAX_F64x2\000"
4491 /* 3871 */ "convert_low_s_F64x2\000"
4492 /* 3891 */ "convert_low_u_F64x2\000"
4493 /* 3911 */ "promote_low_F64x2\000"
4494 /* 3929 */ "CONST_V128_I64x2\000"
4495 /* 3946 */ "SUB_I64x2\000"
4496 /* 3956 */ "ADD_I64x2\000"
4497 /* 3966 */ "REPLACE_LANE_I64x2\000"
4498 /* 3985 */ "EXTRACT_LANE_I64x2\000"
4499 /* 4004 */ "ALLTRUE_I64x2\000"
4500 /* 4018 */ "NEG_I64x2\000"
4501 /* 4028 */ "BITMASK_I64x2\000"
4502 /* 4042 */ "SHL_I64x2\000"
4503 /* 4052 */ "MUL_I64x2\000"
4504 /* 4062 */ "EQ_I64x2\000"
4505 /* 4071 */ "ABS_I64x2\000"
4506 /* 4081 */ "GE_S_I64x2\000"
4507 /* 4092 */ "LE_S_I64x2\000"
4508 /* 4103 */ "EXTMUL_HIGH_S_I64x2\000"
4509 /* 4123 */ "SHR_S_I64x2\000"
4510 /* 4135 */ "GT_S_I64x2\000"
4511 /* 4146 */ "LT_S_I64x2\000"
4512 /* 4157 */ "EXTMUL_LOW_S_I64x2\000"
4513 /* 4176 */ "SPLAT_I64x2\000"
4514 /* 4188 */ "LANESELECT_I64x2\000"
4515 /* 4205 */ "EXTMUL_HIGH_U_I64x2\000"
4516 /* 4225 */ "SHR_U_I64x2\000"
4517 /* 4237 */ "EXTMUL_LOW_U_I64x2\000"
4518 /* 4256 */ "extend_high_s_I64x2\000"
4519 /* 4276 */ "extend_low_s_I64x2\000"
4520 /* 4295 */ "extend_high_u_I64x2\000"
4521 /* 4315 */ "extend_low_u_I64x2\000"
4522 /* 4334 */ "LOAD_F16_F32_A64\000"
4523 /* 4351 */ "STORE_F16_F32_A64\000"
4524 /* 4369 */ "LOAD_F32_A64\000"
4525 /* 4382 */ "STORE_F32_A64\000"
4526 /* 4396 */ "ATOMIC_STORE16_I32_A64\000"
4527 /* 4419 */ "ATOMIC_STORE8_I32_A64\000"
4528 /* 4441 */ "ATOMIC_RMW16_U_SUB_I32_A64\000"
4529 /* 4468 */ "ATOMIC_RMW8_U_SUB_I32_A64\000"
4530 /* 4494 */ "ATOMIC_RMW_SUB_I32_A64\000"
4531 /* 4517 */ "ATOMIC_LOAD_I32_A64\000"
4532 /* 4537 */ "ATOMIC_RMW16_U_ADD_I32_A64\000"
4533 /* 4564 */ "ATOMIC_RMW8_U_ADD_I32_A64\000"
4534 /* 4590 */ "ATOMIC_RMW_ADD_I32_A64\000"
4535 /* 4613 */ "ATOMIC_RMW16_U_AND_I32_A64\000"
4536 /* 4640 */ "ATOMIC_RMW8_U_AND_I32_A64\000"
4537 /* 4666 */ "ATOMIC_RMW_AND_I32_A64\000"
4538 /* 4689 */ "ATOMIC_STORE_I32_A64\000"
4539 /* 4710 */ "ATOMIC_RMW16_U_CMPXCHG_I32_A64\000"
4540 /* 4741 */ "ATOMIC_RMW8_U_CMPXCHG_I32_A64\000"
4541 /* 4771 */ "ATOMIC_RMW_CMPXCHG_I32_A64\000"
4542 /* 4798 */ "ATOMIC_RMW16_U_XCHG_I32_A64\000"
4543 /* 4826 */ "ATOMIC_RMW8_U_XCHG_I32_A64\000"
4544 /* 4853 */ "ATOMIC_RMW_XCHG_I32_A64\000"
4545 /* 4877 */ "ATOMIC_RMW16_U_XOR_I32_A64\000"
4546 /* 4904 */ "ATOMIC_RMW8_U_XOR_I32_A64\000"
4547 /* 4930 */ "ATOMIC_RMW_XOR_I32_A64\000"
4548 /* 4953 */ "ATOMIC_RMW16_U_OR_I32_A64\000"
4549 /* 4979 */ "ATOMIC_RMW8_U_OR_I32_A64\000"
4550 /* 5004 */ "ATOMIC_RMW_OR_I32_A64\000"
4551 /* 5026 */ "LOAD16_S_I32_A64\000"
4552 /* 5043 */ "LOAD8_S_I32_A64\000"
4553 /* 5059 */ "ATOMIC_LOAD16_U_I32_A64\000"
4554 /* 5083 */ "ATOMIC_LOAD8_U_I32_A64\000"
4555 /* 5106 */ "MEMORY_ATOMIC_WAIT32_A64\000"
4556 /* 5131 */ "LOAD_LANE_32_A64\000"
4557 /* 5148 */ "LOAD_ZERO_32_A64\000"
4558 /* 5165 */ "STORE_LANE_I64x2_A64\000"
4559 /* 5186 */ "LOAD_EXTEND_S_I64x2_A64\000"
4560 /* 5210 */ "LOAD_EXTEND_U_I64x2_A64\000"
4561 /* 5234 */ "LOAD_F64_A64\000"
4562 /* 5247 */ "STORE_F64_A64\000"
4563 /* 5261 */ "ATOMIC_STORE32_I64_A64\000"
4564 /* 5284 */ "ATOMIC_STORE16_I64_A64\000"
4565 /* 5307 */ "ATOMIC_STORE8_I64_A64\000"
4566 /* 5329 */ "ATOMIC_RMW32_U_SUB_I64_A64\000"
4567 /* 5356 */ "ATOMIC_RMW16_U_SUB_I64_A64\000"
4568 /* 5383 */ "ATOMIC_RMW8_U_SUB_I64_A64\000"
4569 /* 5409 */ "ATOMIC_RMW_SUB_I64_A64\000"
4570 /* 5432 */ "ATOMIC_LOAD_I64_A64\000"
4571 /* 5452 */ "ATOMIC_RMW32_U_ADD_I64_A64\000"
4572 /* 5479 */ "ATOMIC_RMW16_U_ADD_I64_A64\000"
4573 /* 5506 */ "ATOMIC_RMW8_U_ADD_I64_A64\000"
4574 /* 5532 */ "ATOMIC_RMW_ADD_I64_A64\000"
4575 /* 5555 */ "ATOMIC_RMW32_U_AND_I64_A64\000"
4576 /* 5582 */ "ATOMIC_RMW16_U_AND_I64_A64\000"
4577 /* 5609 */ "ATOMIC_RMW8_U_AND_I64_A64\000"
4578 /* 5635 */ "ATOMIC_RMW_AND_I64_A64\000"
4579 /* 5658 */ "ATOMIC_STORE_I64_A64\000"
4580 /* 5679 */ "ATOMIC_RMW32_U_CMPXCHG_I64_A64\000"
4581 /* 5710 */ "ATOMIC_RMW16_U_CMPXCHG_I64_A64\000"
4582 /* 5741 */ "ATOMIC_RMW8_U_CMPXCHG_I64_A64\000"
4583 /* 5771 */ "ATOMIC_RMW_CMPXCHG_I64_A64\000"
4584 /* 5798 */ "ATOMIC_RMW32_U_XCHG_I64_A64\000"
4585 /* 5826 */ "ATOMIC_RMW16_U_XCHG_I64_A64\000"
4586 /* 5854 */ "ATOMIC_RMW8_U_XCHG_I64_A64\000"
4587 /* 5881 */ "ATOMIC_RMW_XCHG_I64_A64\000"
4588 /* 5905 */ "ATOMIC_RMW32_U_XOR_I64_A64\000"
4589 /* 5932 */ "ATOMIC_RMW16_U_XOR_I64_A64\000"
4590 /* 5959 */ "ATOMIC_RMW8_U_XOR_I64_A64\000"
4591 /* 5985 */ "ATOMIC_RMW_XOR_I64_A64\000"
4592 /* 6008 */ "ATOMIC_RMW32_U_OR_I64_A64\000"
4593 /* 6034 */ "ATOMIC_RMW16_U_OR_I64_A64\000"
4594 /* 6060 */ "ATOMIC_RMW8_U_OR_I64_A64\000"
4595 /* 6085 */ "ATOMIC_RMW_OR_I64_A64\000"
4596 /* 6107 */ "LOAD32_S_I64_A64\000"
4597 /* 6124 */ "LOAD16_S_I64_A64\000"
4598 /* 6141 */ "LOAD8_S_I64_A64\000"
4599 /* 6157 */ "ATOMIC_LOAD32_U_I64_A64\000"
4600 /* 6181 */ "ATOMIC_LOAD16_U_I64_A64\000"
4601 /* 6205 */ "ATOMIC_LOAD8_U_I64_A64\000"
4602 /* 6228 */ "MEMORY_ATOMIC_WAIT64_A64\000"
4603 /* 6253 */ "LOAD_LANE_64_A64\000"
4604 /* 6270 */ "LOAD_ZERO_64_A64\000"
4605 /* 6287 */ "STORE_LANE_I32x4_A64\000"
4606 /* 6308 */ "LOAD_EXTEND_S_I32x4_A64\000"
4607 /* 6332 */ "LOAD_EXTEND_U_I32x4_A64\000"
4608 /* 6356 */ "LOAD_LANE_16_A64\000"
4609 /* 6373 */ "STORE_LANE_I8x16_A64\000"
4610 /* 6394 */ "LOAD_V128_A64\000"
4611 /* 6408 */ "STORE_V128_A64\000"
4612 /* 6423 */ "LOAD_LANE_8_A64\000"
4613 /* 6439 */ "STORE_LANE_I16x8_A64\000"
4614 /* 6460 */ "LOAD_EXTEND_S_I16x8_A64\000"
4615 /* 6484 */ "LOAD_EXTEND_U_I16x8_A64\000"
4616 /* 6508 */ "anonymous_14735MEMORY_SIZE_A64\000"
4617 /* 6539 */ "MEMORY_FILL_A64\000"
4618 /* 6555 */ "LOAD32_SPLAT_A64\000"
4619 /* 6572 */ "LOAD64_SPLAT_A64\000"
4620 /* 6589 */ "LOAD16_SPLAT_A64\000"
4621 /* 6606 */ "LOAD8_SPLAT_A64\000"
4622 /* 6622 */ "MEMSET_A64\000"
4623 /* 6633 */ "MEMORY_INIT_A64\000"
4624 /* 6649 */ "anonymous_14735MEMORY_GROW_A64\000"
4625 /* 6680 */ "MEMORY_ATOMIC_NOTIFY_A64\000"
4626 /* 6705 */ "MEMCPY_A64\000"
4627 /* 6716 */ "MEMORY_COPY_A64\000"
4628 /* 6732 */ "FP_TO_SINT_I32_F64\000"
4629 /* 6751 */ "FP_TO_UINT_I32_F64\000"
4630 /* 6770 */ "FP_TO_SINT_I64_F64\000"
4631 /* 6789 */ "FP_TO_UINT_I64_F64\000"
4632 /* 6808 */ "SUB_F64\000"
4633 /* 6816 */ "TRUNC_F64\000"
4634 /* 6826 */ "ADD_F64\000"
4635 /* 6834 */ "LOCAL_TEE_F64\000"
4636 /* 6848 */ "GE_F64\000"
4637 /* 6855 */ "LE_F64\000"
4638 /* 6862 */ "NE_F64\000"
4639 /* 6869 */ "F32_DEMOTE_F64\000"
4640 /* 6884 */ "NEG_F64\000"
4641 /* 6892 */ "CEIL_F64\000"
4642 /* 6901 */ "MUL_F64\000"
4643 /* 6909 */ "COPYSIGN_F64\000"
4644 /* 6922 */ "MIN_F64\000"
4645 /* 6930 */ "DROP_F64\000"
4646 /* 6939 */ "EQ_F64\000"
4647 /* 6946 */ "FLOOR_F64\000"
4648 /* 6956 */ "ABS_F64\000"
4649 /* 6964 */ "I32_TRUNC_S_F64\000"
4650 /* 6980 */ "I64_TRUNC_S_F64\000"
4651 /* 6996 */ "I32_TRUNC_S_SAT_F64\000"
4652 /* 7016 */ "I64_TRUNC_S_SAT_F64\000"
4653 /* 7036 */ "I32_TRUNC_U_SAT_F64\000"
4654 /* 7056 */ "I64_TRUNC_U_SAT_F64\000"
4655 /* 7076 */ "SELECT_F64\000"
4656 /* 7087 */ "GLOBAL_GET_F64\000"
4657 /* 7102 */ "LOCAL_GET_F64\000"
4658 /* 7116 */ "I64_REINTERPRET_F64\000"
4659 /* 7136 */ "GLOBAL_SET_F64\000"
4660 /* 7151 */ "LOCAL_SET_F64\000"
4661 /* 7165 */ "GT_F64\000"
4662 /* 7172 */ "LT_F64\000"
4663 /* 7179 */ "SQRT_F64\000"
4664 /* 7188 */ "NEAREST_F64\000"
4665 /* 7200 */ "CONST_F64\000"
4666 /* 7210 */ "I32_TRUNC_U_F64\000"
4667 /* 7226 */ "I64_TRUNC_U_F64\000"
4668 /* 7242 */ "DIV_F64\000"
4669 /* 7250 */ "MAX_F64\000"
4670 /* 7258 */ "COPY_F64\000"
4671 /* 7267 */ "SUB_I64\000"
4672 /* 7275 */ "ADD_I64\000"
4673 /* 7283 */ "AND_I64\000"
4674 /* 7291 */ "LOCAL_TEE_I64\000"
4675 /* 7305 */ "BR_TABLE_I64\000"
4676 /* 7318 */ "NE_I64\000"
4677 /* 7325 */ "SHL_I64\000"
4678 /* 7333 */ "ROTL_I64\000"
4679 /* 7342 */ "MUL_I64\000"
4680 /* 7350 */ "I32_WRAP_I64\000"
4681 /* 7363 */ "DROP_I64\000"
4682 /* 7372 */ "EQ_I64\000"
4683 /* 7379 */ "XOR_I64\000"
4684 /* 7387 */ "ROTR_I64\000"
4685 /* 7396 */ "I64_EXTEND32_S_I64\000"
4686 /* 7415 */ "I64_EXTEND16_S_I64\000"
4687 /* 7434 */ "I64_EXTEND8_S_I64\000"
4688 /* 7452 */ "GE_S_I64\000"
4689 /* 7461 */ "LE_S_I64\000"
4690 /* 7470 */ "REM_S_I64\000"
4691 /* 7480 */ "SHR_S_I64\000"
4692 /* 7490 */ "GT_S_I64\000"
4693 /* 7499 */ "LT_S_I64\000"
4694 /* 7508 */ "F32_CONVERT_S_I64\000"
4695 /* 7526 */ "F64_CONVERT_S_I64\000"
4696 /* 7544 */ "DIV_S_I64\000"
4697 /* 7554 */ "SELECT_I64\000"
4698 /* 7565 */ "GLOBAL_GET_I64\000"
4699 /* 7580 */ "LOCAL_GET_I64\000"
4700 /* 7594 */ "F64_REINTERPRET_I64\000"
4701 /* 7614 */ "GLOBAL_SET_I64\000"
4702 /* 7629 */ "LOCAL_SET_I64\000"
4703 /* 7643 */ "POPCNT_I64\000"
4704 /* 7654 */ "CONST_I64\000"
4705 /* 7664 */ "GE_U_I64\000"
4706 /* 7673 */ "LE_U_I64\000"
4707 /* 7682 */ "REM_U_I64\000"
4708 /* 7692 */ "SHR_U_I64\000"
4709 /* 7702 */ "GT_U_I64\000"
4710 /* 7711 */ "LT_U_I64\000"
4711 /* 7720 */ "F32_CONVERT_U_I64\000"
4712 /* 7738 */ "F64_CONVERT_U_I64\000"
4713 /* 7756 */ "DIV_U_I64\000"
4714 /* 7766 */ "COPY_I64\000"
4715 /* 7775 */ "CLZ_I64\000"
4716 /* 7783 */ "EQZ_I64\000"
4717 /* 7791 */ "CTZ_I64\000"
4718 /* 7799 */ "ARGUMENT_v2f64\000"
4719 /* 7814 */ "ARGUMENT_f64\000"
4720 /* 7827 */ "ARGUMENT_v2i64\000"
4721 /* 7842 */ "ARGUMENT_i64\000"
4722 /* 7855 */ "CONST_V128_F32x4\000"
4723 /* 7872 */ "SUB_F32x4\000"
4724 /* 7882 */ "TRUNC_F32x4\000"
4725 /* 7894 */ "NMADD_F32x4\000"
4726 /* 7906 */ "GE_F32x4\000"
4727 /* 7915 */ "LE_F32x4\000"
4728 /* 7924 */ "REPLACE_LANE_F32x4\000"
4729 /* 7943 */ "EXTRACT_LANE_F32x4\000"
4730 /* 7962 */ "NEG_F32x4\000"
4731 /* 7972 */ "CEIL_F32x4\000"
4732 /* 7983 */ "MUL_F32x4\000"
4733 /* 7993 */ "SIMD_RELAXED_FMIN_F32x4\000"
4734 /* 8017 */ "PMIN_F32x4\000"
4735 /* 8028 */ "EQ_F32x4\000"
4736 /* 8037 */ "FLOOR_F32x4\000"
4737 /* 8049 */ "ABS_F32x4\000"
4738 /* 8059 */ "SPLAT_F32x4\000"
4739 /* 8071 */ "GT_F32x4\000"
4740 /* 8080 */ "LT_F32x4\000"
4741 /* 8089 */ "SQRT_F32x4\000"
4742 /* 8100 */ "NEAREST_F32x4\000"
4743 /* 8114 */ "DIV_F32x4\000"
4744 /* 8124 */ "SIMD_RELAXED_FMAX_F32x4\000"
4745 /* 8148 */ "PMAX_F32x4\000"
4746 /* 8159 */ "demote_zero_F32x4\000"
4747 /* 8177 */ "sint_to_fp_F32x4\000"
4748 /* 8194 */ "uint_to_fp_F32x4\000"
4749 /* 8211 */ "CONST_V128_I32x4\000"
4750 /* 8228 */ "SUB_I32x4\000"
4751 /* 8238 */ "ADD_I32x4\000"
4752 /* 8248 */ "REPLACE_LANE_I32x4\000"
4753 /* 8267 */ "EXTRACT_LANE_I32x4\000"
4754 /* 8286 */ "ALLTRUE_I32x4\000"
4755 /* 8300 */ "NEG_I32x4\000"
4756 /* 8310 */ "BITMASK_I32x4\000"
4757 /* 8324 */ "SHL_I32x4\000"
4758 /* 8334 */ "MUL_I32x4\000"
4759 /* 8344 */ "EQ_I32x4\000"
4760 /* 8353 */ "ABS_I32x4\000"
4761 /* 8363 */ "GE_S_I32x4\000"
4762 /* 8374 */ "LE_S_I32x4\000"
4763 /* 8385 */ "EXTMUL_HIGH_S_I32x4\000"
4764 /* 8405 */ "MIN_S_I32x4\000"
4765 /* 8417 */ "SHR_S_I32x4\000"
4766 /* 8429 */ "GT_S_I32x4\000"
4767 /* 8440 */ "LT_S_I32x4\000"
4768 /* 8451 */ "EXTMUL_LOW_S_I32x4\000"
4769 /* 8470 */ "MAX_S_I32x4\000"
4770 /* 8482 */ "SPLAT_I32x4\000"
4771 /* 8494 */ "LANESELECT_I32x4\000"
4772 /* 8511 */ "GE_U_I32x4\000"
4773 /* 8522 */ "LE_U_I32x4\000"
4774 /* 8533 */ "EXTMUL_HIGH_U_I32x4\000"
4775 /* 8553 */ "MIN_U_I32x4\000"
4776 /* 8565 */ "SHR_U_I32x4\000"
4777 /* 8577 */ "GT_U_I32x4\000"
4778 /* 8588 */ "LT_U_I32x4\000"
4779 /* 8599 */ "EXTMUL_LOW_U_I32x4\000"
4780 /* 8618 */ "MAX_U_I32x4\000"
4781 /* 8630 */ "int_wasm_relaxed_trunc_signed_I32x4\000"
4782 /* 8666 */ "int_wasm_relaxed_trunc_unsigned_I32x4\000"
4783 /* 8704 */ "int_wasm_relaxed_trunc_signed_zero_I32x4\000"
4784 /* 8745 */ "int_wasm_relaxed_trunc_unsigned_zero_I32x4\000"
4785 /* 8788 */ "extadd_pairwise_s_I32x4\000"
4786 /* 8812 */ "extend_high_s_I32x4\000"
4787 /* 8832 */ "trunc_sat_zero_s_I32x4\000"
4788 /* 8855 */ "extend_low_s_I32x4\000"
4789 /* 8874 */ "fp_to_sint_I32x4\000"
4790 /* 8891 */ "fp_to_uint_I32x4\000"
4791 /* 8908 */ "extadd_pairwise_u_I32x4\000"
4792 /* 8932 */ "extend_high_u_I32x4\000"
4793 /* 8952 */ "trunc_sat_zero_u_I32x4\000"
4794 /* 8975 */ "extend_low_u_I32x4\000"
4795 /* 8994 */ "ARGUMENT_v8f16\000"
4796 /* 9009 */ "ARGUMENT_v8i16\000"
4797 /* 9024 */ "CONST_V128_I8x16\000"
4798 /* 9041 */ "SUB_I8x16\000"
4799 /* 9051 */ "ADD_I8x16\000"
4800 /* 9061 */ "REPLACE_LANE_I8x16\000"
4801 /* 9080 */ "ALLTRUE_I8x16\000"
4802 /* 9094 */ "NEG_I8x16\000"
4803 /* 9104 */ "BITMASK_I8x16\000"
4804 /* 9118 */ "SHL_I8x16\000"
4805 /* 9128 */ "EQ_I8x16\000"
4806 /* 9137 */ "ABS_I8x16\000"
4807 /* 9147 */ "GE_S_I8x16\000"
4808 /* 9158 */ "LE_S_I8x16\000"
4809 /* 9169 */ "MIN_S_I8x16\000"
4810 /* 9181 */ "SHR_S_I8x16\000"
4811 /* 9193 */ "SUB_SAT_S_I8x16\000"
4812 /* 9209 */ "ADD_SAT_S_I8x16\000"
4813 /* 9225 */ "GT_S_I8x16\000"
4814 /* 9236 */ "LT_S_I8x16\000"
4815 /* 9247 */ "NARROW_S_I8x16\000"
4816 /* 9262 */ "MAX_S_I8x16\000"
4817 /* 9274 */ "SPLAT_I8x16\000"
4818 /* 9286 */ "LANESELECT_I8x16\000"
4819 /* 9303 */ "POPCNT_I8x16\000"
4820 /* 9316 */ "GE_U_I8x16\000"
4821 /* 9327 */ "LE_U_I8x16\000"
4822 /* 9338 */ "MIN_U_I8x16\000"
4823 /* 9350 */ "AVGR_U_I8x16\000"
4824 /* 9363 */ "SHR_U_I8x16\000"
4825 /* 9375 */ "SUB_SAT_U_I8x16\000"
4826 /* 9391 */ "ADD_SAT_U_I8x16\000"
4827 /* 9407 */ "GT_U_I8x16\000"
4828 /* 9418 */ "LT_U_I8x16\000"
4829 /* 9429 */ "NARROW_U_I8x16\000"
4830 /* 9444 */ "MAX_U_I8x16\000"
4831 /* 9456 */ "I64_SUB128\000"
4832 /* 9467 */ "I64_ADD128\000"
4833 /* 9478 */ "LOCAL_TEE_V128\000"
4834 /* 9493 */ "DROP_V128\000"
4835 /* 9503 */ "SELECT_V128\000"
4836 /* 9515 */ "GLOBAL_GET_V128\000"
4837 /* 9531 */ "LOCAL_GET_V128\000"
4838 /* 9546 */ "GLOBAL_SET_V128\000"
4839 /* 9562 */ "LOCAL_SET_V128\000"
4840 /* 9577 */ "COPY_V128\000"
4841 /* 9587 */ "ARGUMENT_v16i8\000"
4842 /* 9602 */ "SUB_F16x8\000"
4843 /* 9612 */ "TRUNC_F16x8\000"
4844 /* 9624 */ "NMADD_F16x8\000"
4845 /* 9636 */ "GE_F16x8\000"
4846 /* 9645 */ "LE_F16x8\000"
4847 /* 9654 */ "REPLACE_LANE_F16x8\000"
4848 /* 9673 */ "EXTRACT_LANE_F16x8\000"
4849 /* 9692 */ "NEG_F16x8\000"
4850 /* 9702 */ "CEIL_F16x8\000"
4851 /* 9713 */ "MUL_F16x8\000"
4852 /* 9723 */ "PMIN_F16x8\000"
4853 /* 9734 */ "EQ_F16x8\000"
4854 /* 9743 */ "FLOOR_F16x8\000"
4855 /* 9755 */ "ABS_F16x8\000"
4856 /* 9765 */ "SPLAT_F16x8\000"
4857 /* 9777 */ "GT_F16x8\000"
4858 /* 9786 */ "LT_F16x8\000"
4859 /* 9795 */ "SQRT_F16x8\000"
4860 /* 9806 */ "NEAREST_F16x8\000"
4861 /* 9820 */ "DIV_F16x8\000"
4862 /* 9830 */ "PMAX_F16x8\000"
4863 /* 9841 */ "sint_to_fp_F16x8\000"
4864 /* 9858 */ "uint_to_fp_F16x8\000"
4865 /* 9875 */ "CONST_V128_I16x8\000"
4866 /* 9892 */ "SUB_I16x8\000"
4867 /* 9902 */ "ADD_I16x8\000"
4868 /* 9912 */ "REPLACE_LANE_I16x8\000"
4869 /* 9931 */ "ALLTRUE_I16x8\000"
4870 /* 9945 */ "NEG_I16x8\000"
4871 /* 9955 */ "BITMASK_I16x8\000"
4872 /* 9969 */ "SHL_I16x8\000"
4873 /* 9979 */ "MUL_I16x8\000"
4874 /* 9989 */ "EQ_I16x8\000"
4875 /* 9998 */ "ABS_I16x8\000"
4876 /* 10008 */ "GE_S_I16x8\000"
4877 /* 10019 */ "LE_S_I16x8\000"
4878 /* 10030 */ "EXTMUL_HIGH_S_I16x8\000"
4879 /* 10050 */ "MIN_S_I16x8\000"
4880 /* 10062 */ "SHR_S_I16x8\000"
4881 /* 10074 */ "RELAXED_Q15MULR_S_I16x8\000"
4882 /* 10098 */ "SUB_SAT_S_I16x8\000"
4883 /* 10114 */ "ADD_SAT_S_I16x8\000"
4884 /* 10130 */ "Q15MULR_SAT_S_I16x8\000"
4885 /* 10150 */ "GT_S_I16x8\000"
4886 /* 10161 */ "LT_S_I16x8\000"
4887 /* 10172 */ "EXTMUL_LOW_S_I16x8\000"
4888 /* 10191 */ "NARROW_S_I16x8\000"
4889 /* 10206 */ "MAX_S_I16x8\000"
4890 /* 10218 */ "SPLAT_I16x8\000"
4891 /* 10230 */ "LANESELECT_I16x8\000"
4892 /* 10247 */ "GE_U_I16x8\000"
4893 /* 10258 */ "LE_U_I16x8\000"
4894 /* 10269 */ "EXTMUL_HIGH_U_I16x8\000"
4895 /* 10289 */ "MIN_U_I16x8\000"
4896 /* 10301 */ "AVGR_U_I16x8\000"
4897 /* 10314 */ "SHR_U_I16x8\000"
4898 /* 10326 */ "SUB_SAT_U_I16x8\000"
4899 /* 10342 */ "ADD_SAT_U_I16x8\000"
4900 /* 10358 */ "GT_U_I16x8\000"
4901 /* 10369 */ "LT_U_I16x8\000"
4902 /* 10380 */ "EXTMUL_LOW_U_I16x8\000"
4903 /* 10399 */ "NARROW_U_I16x8\000"
4904 /* 10414 */ "MAX_U_I16x8\000"
4905 /* 10426 */ "extadd_pairwise_s_I16x8\000"
4906 /* 10450 */ "extend_high_s_I16x8\000"
4907 /* 10470 */ "extend_low_s_I16x8\000"
4908 /* 10489 */ "fp_to_sint_I16x8\000"
4909 /* 10506 */ "fp_to_uint_I16x8\000"
4910 /* 10523 */ "extadd_pairwise_u_I16x8\000"
4911 /* 10547 */ "extend_high_u_I16x8\000"
4912 /* 10567 */ "extend_low_u_I16x8\000"
4913 /* 10586 */ "G_FMA\000"
4914 /* 10592 */ "G_STRICT_FMA\000"
4915 /* 10605 */ "G_FSUB\000"
4916 /* 10612 */ "G_STRICT_FSUB\000"
4917 /* 10626 */ "G_ATOMICRMW_FSUB\000"
4918 /* 10643 */ "G_SUB\000"
4919 /* 10649 */ "G_ATOMICRMW_SUB\000"
4920 /* 10665 */ "G_INTRINSIC\000"
4921 /* 10677 */ "REF_FUNC\000"
4922 /* 10686 */ "G_FPTRUNC\000"
4923 /* 10696 */ "G_INTRINSIC_TRUNC\000"
4924 /* 10714 */ "G_TRUNC\000"
4925 /* 10722 */ "G_BUILD_VECTOR_TRUNC\000"
4926 /* 10743 */ "G_DYN_STACKALLOC\000"
4927 /* 10760 */ "G_FMAD\000"
4928 /* 10767 */ "G_INDEXED_SEXTLOAD\000"
4929 /* 10786 */ "G_SEXTLOAD\000"
4930 /* 10797 */ "G_INDEXED_ZEXTLOAD\000"
4931 /* 10816 */ "G_ZEXTLOAD\000"
4932 /* 10827 */ "G_INDEXED_LOAD\000"
4933 /* 10842 */ "G_LOAD\000"
4934 /* 10849 */ "G_VECREDUCE_FADD\000"
4935 /* 10866 */ "G_FADD\000"
4936 /* 10873 */ "G_VECREDUCE_SEQ_FADD\000"
4937 /* 10894 */ "G_STRICT_FADD\000"
4938 /* 10908 */ "G_ATOMICRMW_FADD\000"
4939 /* 10925 */ "G_VECREDUCE_ADD\000"
4940 /* 10941 */ "G_ADD\000"
4941 /* 10947 */ "G_PTR_ADD\000"
4942 /* 10957 */ "RELAXED_DOT_ADD\000"
4943 /* 10973 */ "G_ATOMICRMW_ADD\000"
4944 /* 10989 */ "G_ATOMICRMW_NAND\000"
4945 /* 11006 */ "G_VECREDUCE_AND\000"
4946 /* 11022 */ "G_AND\000"
4947 /* 11028 */ "G_ATOMICRMW_AND\000"
4948 /* 11044 */ "LIFETIME_END\000"
4949 /* 11057 */ "G_BRCOND\000"
4950 /* 11066 */ "G_ATOMICRMW_USUB_COND\000"
4951 /* 11088 */ "G_LLROUND\000"
4952 /* 11098 */ "G_LROUND\000"
4953 /* 11107 */ "G_INTRINSIC_ROUND\000"
4954 /* 11125 */ "G_INTRINSIC_FPTRUNC_ROUND\000"
4955 /* 11151 */ "LOAD_STACK_GUARD\000"
4956 /* 11168 */ "PSEUDO_PROBE\000"
4957 /* 11181 */ "G_SSUBE\000"
4958 /* 11189 */ "G_USUBE\000"
4959 /* 11197 */ "ATOMIC_FENCE\000"
4960 /* 11210 */ "G_FENCE\000"
4961 /* 11218 */ "ARITH_FENCE\000"
4962 /* 11230 */ "COMPILER_FENCE\000"
4963 /* 11245 */ "REG_SEQUENCE\000"
4964 /* 11258 */ "G_SADDE\000"
4965 /* 11266 */ "G_UADDE\000"
4966 /* 11274 */ "G_GET_FPMODE\000"
4967 /* 11287 */ "G_RESET_FPMODE\000"
4968 /* 11302 */ "G_SET_FPMODE\000"
4969 /* 11315 */ "G_FMINNUM_IEEE\000"
4970 /* 11330 */ "G_FMAXNUM_IEEE\000"
4971 /* 11345 */ "G_VSCALE\000"
4972 /* 11354 */ "DEBUG_UNREACHABLE\000"
4973 /* 11372 */ "G_JUMP_TABLE\000"
4974 /* 11385 */ "END_TRY_TABLE\000"
4975 /* 11399 */ "BUNDLE\000"
4976 /* 11406 */ "SHUFFLE\000"
4977 /* 11414 */ "RELAXED_SWIZZLE\000"
4978 /* 11430 */ "G_MEMCPY_INLINE\000"
4979 /* 11446 */ "RELOC_NONE\000"
4980 /* 11457 */ "LOCAL_ESCAPE\000"
4981 /* 11470 */ "G_STACKRESTORE\000"
4982 /* 11485 */ "G_INDEXED_STORE\000"
4983 /* 11501 */ "G_STORE\000"
4984 /* 11509 */ "ELSE\000"
4985 /* 11514 */ "G_BITREVERSE\000"
4986 /* 11527 */ "FAKE_USE\000"
4987 /* 11536 */ "DELEGATE\000"
4988 /* 11545 */ "DBG_VALUE\000"
4989 /* 11555 */ "G_GLOBAL_VALUE\000"
4990 /* 11570 */ "G_PTRAUTH_GLOBAL_VALUE\000"
4991 /* 11593 */ "CONVERGENCECTRL_GLUE\000"
4992 /* 11614 */ "ANYTRUE\000"
4993 /* 11622 */ "G_STACKSAVE\000"
4994 /* 11634 */ "G_MEMMOVE\000"
4995 /* 11644 */ "G_FREEZE\000"
4996 /* 11653 */ "G_FCANONICALIZE\000"
4997 /* 11669 */ "TABLE_SIZE\000"
4998 /* 11680 */ "G_FMODF\000"
4999 /* 11688 */ "G_CTLZ_ZERO_UNDEF\000"
5000 /* 11706 */ "G_CTTZ_ZERO_UNDEF\000"
5001 /* 11724 */ "INIT_UNDEF\000"
5002 /* 11735 */ "G_IMPLICIT_DEF\000"
5003 /* 11750 */ "LOCAL_TEE_FUNCREF\000"
5004 /* 11768 */ "TABLE_FILL_FUNCREF\000"
5005 /* 11787 */ "REF_NULL_FUNCREF\000"
5006 /* 11804 */ "REF_IS_NULL_FUNCREF\000"
5007 /* 11824 */ "DROP_FUNCREF\000"
5008 /* 11837 */ "SELECT_FUNCREF\000"
5009 /* 11852 */ "TABLE_GET_FUNCREF\000"
5010 /* 11870 */ "GLOBAL_GET_FUNCREF\000"
5011 /* 11889 */ "LOCAL_GET_FUNCREF\000"
5012 /* 11907 */ "TABLE_SET_FUNCREF\000"
5013 /* 11925 */ "GLOBAL_SET_FUNCREF\000"
5014 /* 11944 */ "LOCAL_SET_FUNCREF\000"
5015 /* 11962 */ "REF_TEST_FUNCREF\000"
5016 /* 11979 */ "TABLE_GROW_FUNCREF\000"
5017 /* 11998 */ "COPY_FUNCREF\000"
5018 /* 12011 */ "LOCAL_TEE_EXTERNREF\000"
5019 /* 12031 */ "TABLE_FILL_EXTERNREF\000"
5020 /* 12052 */ "REF_NULL_EXTERNREF\000"
5021 /* 12071 */ "REF_IS_NULL_EXTERNREF\000"
5022 /* 12093 */ "DROP_EXTERNREF\000"
5023 /* 12108 */ "SELECT_EXTERNREF\000"
5024 /* 12125 */ "TABLE_GET_EXTERNREF\000"
5025 /* 12145 */ "GLOBAL_GET_EXTERNREF\000"
5026 /* 12166 */ "LOCAL_GET_EXTERNREF\000"
5027 /* 12186 */ "TABLE_SET_EXTERNREF\000"
5028 /* 12206 */ "GLOBAL_SET_EXTERNREF\000"
5029 /* 12227 */ "LOCAL_SET_EXTERNREF\000"
5030 /* 12247 */ "TABLE_GROW_EXTERNREF\000"
5031 /* 12268 */ "COPY_EXTERNREF\000"
5032 /* 12283 */ "LOCAL_TEE_EXNREF\000"
5033 /* 12300 */ "TABLE_FILL_EXNREF\000"
5034 /* 12318 */ "REF_NULL_EXNREF\000"
5035 /* 12334 */ "REF_IS_NULL_EXNREF\000"
5036 /* 12353 */ "DROP_EXNREF\000"
5037 /* 12365 */ "SELECT_EXNREF\000"
5038 /* 12379 */ "TABLE_GET_EXNREF\000"
5039 /* 12396 */ "GLOBAL_GET_EXNREF\000"
5040 /* 12414 */ "LOCAL_GET_EXNREF\000"
5041 /* 12431 */ "TABLE_SET_EXNREF\000"
5042 /* 12448 */ "GLOBAL_SET_EXNREF\000"
5043 /* 12466 */ "LOCAL_SET_EXNREF\000"
5044 /* 12483 */ "TABLE_GROW_EXNREF\000"
5045 /* 12501 */ "COPY_EXNREF\000"
5046 /* 12513 */ "CATCH_REF\000"
5047 /* 12523 */ "CATCH_ALL_REF\000"
5048 /* 12537 */ "DBG_INSTR_REF\000"
5049 /* 12551 */ "THROW_REF\000"
5050 /* 12561 */ "END_IF\000"
5051 /* 12568 */ "BR_IF\000"
5052 /* 12574 */ "G_FNEG\000"
5053 /* 12581 */ "EXTRACT_SUBREG\000"
5054 /* 12596 */ "INSERT_SUBREG\000"
5055 /* 12610 */ "G_SEXT_INREG\000"
5056 /* 12623 */ "SUBREG_TO_REG\000"
5057 /* 12637 */ "G_ATOMIC_CMPXCHG\000"
5058 /* 12654 */ "G_ATOMICRMW_XCHG\000"
5059 /* 12671 */ "G_GET_ROUNDING\000"
5060 /* 12686 */ "G_SET_ROUNDING\000"
5061 /* 12701 */ "G_FLOG\000"
5062 /* 12708 */ "G_VAARG\000"
5063 /* 12716 */ "PREALLOCATED_ARG\000"
5064 /* 12733 */ "CATCH\000"
5065 /* 12739 */ "G_PREFETCH\000"
5066 /* 12750 */ "G_SMULH\000"
5067 /* 12758 */ "G_UMULH\000"
5068 /* 12766 */ "G_FTANH\000"
5069 /* 12774 */ "G_FSINH\000"
5070 /* 12782 */ "G_FCOSH\000"
5071 /* 12790 */ "DBG_PHI\000"
5072 /* 12798 */ "G_FPTOSI\000"
5073 /* 12807 */ "G_FPTOUI\000"
5074 /* 12816 */ "G_FPOWI\000"
5075 /* 12824 */ "END_BLOCK\000"
5076 /* 12834 */ "COPY_LANEMASK\000"
5077 /* 12848 */ "G_PTRMASK\000"
5078 /* 12858 */ "GC_LABEL\000"
5079 /* 12867 */ "DBG_LABEL\000"
5080 /* 12877 */ "EH_LABEL\000"
5081 /* 12886 */ "ANNOTATION_LABEL\000"
5082 /* 12903 */ "ICALL_BRANCH_FUNNEL\000"
5083 /* 12923 */ "G_FSHL\000"
5084 /* 12930 */ "G_SHL\000"
5085 /* 12936 */ "G_FCEIL\000"
5086 /* 12944 */ "G_SAVGCEIL\000"
5087 /* 12955 */ "G_UAVGCEIL\000"
5088 /* 12966 */ "PATCHABLE_TAIL_CALL\000"
5089 /* 12986 */ "RET_CALL\000"
5090 /* 12995 */ "PATCHABLE_TYPED_EVENT_CALL\000"
5091 /* 13022 */ "PATCHABLE_EVENT_CALL\000"
5092 /* 13043 */ "FENTRY_CALL\000"
5093 /* 13055 */ "CATCH_ALL\000"
5094 /* 13065 */ "KILL\000"
5095 /* 13070 */ "G_CONSTANT_POOL\000"
5096 /* 13086 */ "G_ROTL\000"
5097 /* 13093 */ "G_VECREDUCE_FMUL\000"
5098 /* 13110 */ "G_FMUL\000"
5099 /* 13117 */ "G_VECREDUCE_SEQ_FMUL\000"
5100 /* 13138 */ "G_STRICT_FMUL\000"
5101 /* 13152 */ "G_VECREDUCE_MUL\000"
5102 /* 13168 */ "G_MUL\000"
5103 /* 13174 */ "G_FREM\000"
5104 /* 13181 */ "G_STRICT_FREM\000"
5105 /* 13195 */ "G_SREM\000"
5106 /* 13202 */ "G_UREM\000"
5107 /* 13209 */ "G_SDIVREM\000"
5108 /* 13219 */ "G_UDIVREM\000"
5109 /* 13229 */ "INLINEASM\000"
5110 /* 13239 */ "G_VECREDUCE_FMINIMUM\000"
5111 /* 13260 */ "G_FMINIMUM\000"
5112 /* 13271 */ "G_ATOMICRMW_FMINIMUM\000"
5113 /* 13292 */ "G_VECREDUCE_FMAXIMUM\000"
5114 /* 13313 */ "G_FMAXIMUM\000"
5115 /* 13324 */ "G_ATOMICRMW_FMAXIMUM\000"
5116 /* 13345 */ "G_FMINIMUMNUM\000"
5117 /* 13359 */ "G_FMAXIMUMNUM\000"
5118 /* 13373 */ "G_FMINNUM\000"
5119 /* 13383 */ "G_FMAXNUM\000"
5120 /* 13393 */ "G_FATAN\000"
5121 /* 13401 */ "G_FTAN\000"
5122 /* 13408 */ "G_INTRINSIC_ROUNDEVEN\000"
5123 /* 13430 */ "G_ASSERT_ALIGN\000"
5124 /* 13445 */ "G_FCOPYSIGN\000"
5125 /* 13457 */ "G_VECREDUCE_FMIN\000"
5126 /* 13474 */ "G_ATOMICRMW_FMIN\000"
5127 /* 13491 */ "G_VECREDUCE_SMIN\000"
5128 /* 13508 */ "G_SMIN\000"
5129 /* 13515 */ "G_VECREDUCE_UMIN\000"
5130 /* 13532 */ "G_UMIN\000"
5131 /* 13539 */ "G_ATOMICRMW_UMIN\000"
5132 /* 13556 */ "G_ATOMICRMW_MIN\000"
5133 /* 13572 */ "G_FASIN\000"
5134 /* 13580 */ "G_FSIN\000"
5135 /* 13587 */ "END_FUNCTION\000"
5136 /* 13600 */ "CFI_INSTRUCTION\000"
5137 /* 13616 */ "FALLTHROUGH_RETURN\000"
5138 /* 13635 */ "ADJCALLSTACKDOWN\000"
5139 /* 13652 */ "G_SSUBO\000"
5140 /* 13660 */ "G_USUBO\000"
5141 /* 13668 */ "G_SADDO\000"
5142 /* 13676 */ "G_UADDO\000"
5143 /* 13684 */ "JUMP_TABLE_DEBUG_INFO\000"
5144 /* 13706 */ "G_SMULO\000"
5145 /* 13714 */ "G_UMULO\000"
5146 /* 13722 */ "G_BZERO\000"
5147 /* 13730 */ "STACKMAP\000"
5148 /* 13739 */ "G_DEBUGTRAP\000"
5149 /* 13751 */ "G_UBSANTRAP\000"
5150 /* 13763 */ "G_TRAP\000"
5151 /* 13770 */ "G_ATOMICRMW_UDEC_WRAP\000"
5152 /* 13792 */ "G_ATOMICRMW_UINC_WRAP\000"
5153 /* 13814 */ "G_BSWAP\000"
5154 /* 13822 */ "G_SITOFP\000"
5155 /* 13831 */ "G_UITOFP\000"
5156 /* 13840 */ "G_FCMP\000"
5157 /* 13847 */ "G_ICMP\000"
5158 /* 13854 */ "G_SCMP\000"
5159 /* 13861 */ "G_UCMP\000"
5160 /* 13868 */ "NOP\000"
5161 /* 13872 */ "END_LOOP\000"
5162 /* 13881 */ "CONVERGENCECTRL_LOOP\000"
5163 /* 13902 */ "G_CTPOP\000"
5164 /* 13910 */ "DATA_DROP\000"
5165 /* 13920 */ "PATCHABLE_OP\000"
5166 /* 13933 */ "FAULTING_OP\000"
5167 /* 13945 */ "ADJCALLSTACKUP\000"
5168 /* 13960 */ "PREALLOCATED_SETUP\000"
5169 /* 13979 */ "G_FLDEXP\000"
5170 /* 13988 */ "G_STRICT_FLDEXP\000"
5171 /* 14004 */ "G_FEXP\000"
5172 /* 14011 */ "G_FFREXP\000"
5173 /* 14020 */ "G_BR\000"
5174 /* 14025 */ "INLINEASM_BR\000"
5175 /* 14038 */ "G_BLOCK_ADDR\000"
5176 /* 14051 */ "MEMBARRIER\000"
5177 /* 14062 */ "G_CONSTANT_FOLD_BARRIER\000"
5178 /* 14086 */ "PATCHABLE_FUNCTION_ENTER\000"
5179 /* 14111 */ "G_READCYCLECOUNTER\000"
5180 /* 14130 */ "G_READSTEADYCOUNTER\000"
5181 /* 14150 */ "G_READ_REGISTER\000"
5182 /* 14166 */ "G_WRITE_REGISTER\000"
5183 /* 14183 */ "G_ASHR\000"
5184 /* 14190 */ "G_FSHR\000"
5185 /* 14197 */ "G_LSHR\000"
5186 /* 14204 */ "CONVERGENCECTRL_ANCHOR\000"
5187 /* 14227 */ "G_FFLOOR\000"
5188 /* 14236 */ "G_SAVGFLOOR\000"
5189 /* 14248 */ "G_UAVGFLOOR\000"
5190 /* 14260 */ "G_EXTRACT_SUBVECTOR\000"
5191 /* 14280 */ "G_INSERT_SUBVECTOR\000"
5192 /* 14299 */ "G_BUILD_VECTOR\000"
5193 /* 14314 */ "G_SHUFFLE_VECTOR\000"
5194 /* 14331 */ "G_STEP_VECTOR\000"
5195 /* 14345 */ "G_SPLAT_VECTOR\000"
5196 /* 14360 */ "G_VECREDUCE_XOR\000"
5197 /* 14376 */ "G_XOR\000"
5198 /* 14382 */ "G_ATOMICRMW_XOR\000"
5199 /* 14398 */ "G_VECREDUCE_OR\000"
5200 /* 14413 */ "G_OR\000"
5201 /* 14418 */ "G_ATOMICRMW_OR\000"
5202 /* 14433 */ "G_ROTR\000"
5203 /* 14440 */ "G_INTTOPTR\000"
5204 /* 14451 */ "G_FABS\000"
5205 /* 14458 */ "G_ABS\000"
5206 /* 14464 */ "G_ABDS\000"
5207 /* 14471 */ "G_UNMERGE_VALUES\000"
5208 /* 14488 */ "G_MERGE_VALUES\000"
5209 /* 14503 */ "G_CTLS\000"
5210 /* 14510 */ "CALL_PARAMS\000"
5211 /* 14522 */ "G_FACOS\000"
5212 /* 14530 */ "G_FCOS\000"
5213 /* 14537 */ "G_FSINCOS\000"
5214 /* 14547 */ "G_CONCAT_VECTORS\000"
5215 /* 14564 */ "COPY_TO_REGCLASS\000"
5216 /* 14581 */ "G_IS_FPCLASS\000"
5217 /* 14594 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000"
5218 /* 14624 */ "BR_UNLESS\000"
5219 /* 14634 */ "G_VECTOR_COMPRESS\000"
5220 /* 14652 */ "G_INTRINSIC_W_SIDE_EFFECTS\000"
5221 /* 14679 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000"
5222 /* 14717 */ "RET_CALL_RESULTS\000"
5223 /* 14734 */ "LOAD_F16_F32_A32_S\000"
5224 /* 14753 */ "STORE_F16_F32_A32_S\000"
5225 /* 14773 */ "LOAD_F32_A32_S\000"
5226 /* 14788 */ "STORE_F32_A32_S\000"
5227 /* 14804 */ "ATOMIC_STORE16_I32_A32_S\000"
5228 /* 14829 */ "ATOMIC_STORE8_I32_A32_S\000"
5229 /* 14853 */ "ATOMIC_RMW16_U_SUB_I32_A32_S\000"
5230 /* 14882 */ "ATOMIC_RMW8_U_SUB_I32_A32_S\000"
5231 /* 14910 */ "ATOMIC_RMW_SUB_I32_A32_S\000"
5232 /* 14935 */ "ATOMIC_LOAD_I32_A32_S\000"
5233 /* 14957 */ "ATOMIC_RMW16_U_ADD_I32_A32_S\000"
5234 /* 14986 */ "ATOMIC_RMW8_U_ADD_I32_A32_S\000"
5235 /* 15014 */ "ATOMIC_RMW_ADD_I32_A32_S\000"
5236 /* 15039 */ "ATOMIC_RMW16_U_AND_I32_A32_S\000"
5237 /* 15068 */ "ATOMIC_RMW8_U_AND_I32_A32_S\000"
5238 /* 15096 */ "ATOMIC_RMW_AND_I32_A32_S\000"
5239 /* 15121 */ "ATOMIC_STORE_I32_A32_S\000"
5240 /* 15144 */ "ATOMIC_RMW16_U_CMPXCHG_I32_A32_S\000"
5241 /* 15177 */ "ATOMIC_RMW8_U_CMPXCHG_I32_A32_S\000"
5242 /* 15209 */ "ATOMIC_RMW_CMPXCHG_I32_A32_S\000"
5243 /* 15238 */ "ATOMIC_RMW16_U_XCHG_I32_A32_S\000"
5244 /* 15268 */ "ATOMIC_RMW8_U_XCHG_I32_A32_S\000"
5245 /* 15297 */ "ATOMIC_RMW_XCHG_I32_A32_S\000"
5246 /* 15323 */ "ATOMIC_RMW16_U_XOR_I32_A32_S\000"
5247 /* 15352 */ "ATOMIC_RMW8_U_XOR_I32_A32_S\000"
5248 /* 15380 */ "ATOMIC_RMW_XOR_I32_A32_S\000"
5249 /* 15405 */ "ATOMIC_RMW16_U_OR_I32_A32_S\000"
5250 /* 15433 */ "ATOMIC_RMW8_U_OR_I32_A32_S\000"
5251 /* 15460 */ "ATOMIC_RMW_OR_I32_A32_S\000"
5252 /* 15484 */ "LOAD16_S_I32_A32_S\000"
5253 /* 15503 */ "LOAD8_S_I32_A32_S\000"
5254 /* 15521 */ "ATOMIC_LOAD16_U_I32_A32_S\000"
5255 /* 15547 */ "ATOMIC_LOAD8_U_I32_A32_S\000"
5256 /* 15572 */ "MEMORY_ATOMIC_WAIT32_A32_S\000"
5257 /* 15599 */ "LOAD_LANE_32_A32_S\000"
5258 /* 15618 */ "LOAD_ZERO_32_A32_S\000"
5259 /* 15637 */ "STORE_LANE_I64x2_A32_S\000"
5260 /* 15660 */ "LOAD_EXTEND_S_I64x2_A32_S\000"
5261 /* 15686 */ "LOAD_EXTEND_U_I64x2_A32_S\000"
5262 /* 15712 */ "LOAD_F64_A32_S\000"
5263 /* 15727 */ "STORE_F64_A32_S\000"
5264 /* 15743 */ "ATOMIC_STORE32_I64_A32_S\000"
5265 /* 15768 */ "ATOMIC_STORE16_I64_A32_S\000"
5266 /* 15793 */ "ATOMIC_STORE8_I64_A32_S\000"
5267 /* 15817 */ "ATOMIC_RMW32_U_SUB_I64_A32_S\000"
5268 /* 15846 */ "ATOMIC_RMW16_U_SUB_I64_A32_S\000"
5269 /* 15875 */ "ATOMIC_RMW8_U_SUB_I64_A32_S\000"
5270 /* 15903 */ "ATOMIC_RMW_SUB_I64_A32_S\000"
5271 /* 15928 */ "ATOMIC_LOAD_I64_A32_S\000"
5272 /* 15950 */ "ATOMIC_RMW32_U_ADD_I64_A32_S\000"
5273 /* 15979 */ "ATOMIC_RMW16_U_ADD_I64_A32_S\000"
5274 /* 16008 */ "ATOMIC_RMW8_U_ADD_I64_A32_S\000"
5275 /* 16036 */ "ATOMIC_RMW_ADD_I64_A32_S\000"
5276 /* 16061 */ "ATOMIC_RMW32_U_AND_I64_A32_S\000"
5277 /* 16090 */ "ATOMIC_RMW16_U_AND_I64_A32_S\000"
5278 /* 16119 */ "ATOMIC_RMW8_U_AND_I64_A32_S\000"
5279 /* 16147 */ "ATOMIC_RMW_AND_I64_A32_S\000"
5280 /* 16172 */ "ATOMIC_STORE_I64_A32_S\000"
5281 /* 16195 */ "ATOMIC_RMW32_U_CMPXCHG_I64_A32_S\000"
5282 /* 16228 */ "ATOMIC_RMW16_U_CMPXCHG_I64_A32_S\000"
5283 /* 16261 */ "ATOMIC_RMW8_U_CMPXCHG_I64_A32_S\000"
5284 /* 16293 */ "ATOMIC_RMW_CMPXCHG_I64_A32_S\000"
5285 /* 16322 */ "ATOMIC_RMW32_U_XCHG_I64_A32_S\000"
5286 /* 16352 */ "ATOMIC_RMW16_U_XCHG_I64_A32_S\000"
5287 /* 16382 */ "ATOMIC_RMW8_U_XCHG_I64_A32_S\000"
5288 /* 16411 */ "ATOMIC_RMW_XCHG_I64_A32_S\000"
5289 /* 16437 */ "ATOMIC_RMW32_U_XOR_I64_A32_S\000"
5290 /* 16466 */ "ATOMIC_RMW16_U_XOR_I64_A32_S\000"
5291 /* 16495 */ "ATOMIC_RMW8_U_XOR_I64_A32_S\000"
5292 /* 16523 */ "ATOMIC_RMW_XOR_I64_A32_S\000"
5293 /* 16548 */ "ATOMIC_RMW32_U_OR_I64_A32_S\000"
5294 /* 16576 */ "ATOMIC_RMW16_U_OR_I64_A32_S\000"
5295 /* 16604 */ "ATOMIC_RMW8_U_OR_I64_A32_S\000"
5296 /* 16631 */ "ATOMIC_RMW_OR_I64_A32_S\000"
5297 /* 16655 */ "LOAD32_S_I64_A32_S\000"
5298 /* 16674 */ "LOAD16_S_I64_A32_S\000"
5299 /* 16693 */ "LOAD8_S_I64_A32_S\000"
5300 /* 16711 */ "ATOMIC_LOAD32_U_I64_A32_S\000"
5301 /* 16737 */ "ATOMIC_LOAD16_U_I64_A32_S\000"
5302 /* 16763 */ "ATOMIC_LOAD8_U_I64_A32_S\000"
5303 /* 16788 */ "MEMORY_ATOMIC_WAIT64_A32_S\000"
5304 /* 16815 */ "LOAD_LANE_64_A32_S\000"
5305 /* 16834 */ "LOAD_ZERO_64_A32_S\000"
5306 /* 16853 */ "STORE_LANE_I32x4_A32_S\000"
5307 /* 16876 */ "LOAD_EXTEND_S_I32x4_A32_S\000"
5308 /* 16902 */ "LOAD_EXTEND_U_I32x4_A32_S\000"
5309 /* 16928 */ "LOAD_LANE_16_A32_S\000"
5310 /* 16947 */ "STORE_LANE_I8x16_A32_S\000"
5311 /* 16970 */ "LOAD_V128_A32_S\000"
5312 /* 16986 */ "STORE_V128_A32_S\000"
5313 /* 17003 */ "LOAD_LANE_8_A32_S\000"
5314 /* 17021 */ "STORE_LANE_I16x8_A32_S\000"
5315 /* 17044 */ "LOAD_EXTEND_S_I16x8_A32_S\000"
5316 /* 17070 */ "LOAD_EXTEND_U_I16x8_A32_S\000"
5317 /* 17096 */ "anonymous_14734MEMORY_SIZE_A32_S\000"
5318 /* 17129 */ "MEMORY_FILL_A32_S\000"
5319 /* 17147 */ "LOAD32_SPLAT_A32_S\000"
5320 /* 17166 */ "LOAD64_SPLAT_A32_S\000"
5321 /* 17185 */ "LOAD16_SPLAT_A32_S\000"
5322 /* 17204 */ "LOAD8_SPLAT_A32_S\000"
5323 /* 17222 */ "MEMSET_A32_S\000"
5324 /* 17235 */ "MEMORY_INIT_A32_S\000"
5325 /* 17253 */ "anonymous_14734MEMORY_GROW_A32_S\000"
5326 /* 17286 */ "MEMORY_ATOMIC_NOTIFY_A32_S\000"
5327 /* 17313 */ "MEMCPY_A32_S\000"
5328 /* 17326 */ "MEMORY_COPY_A32_S\000"
5329 /* 17344 */ "FP_TO_SINT_I32_F32_S\000"
5330 /* 17365 */ "FP_TO_UINT_I32_F32_S\000"
5331 /* 17386 */ "FP_TO_SINT_I64_F32_S\000"
5332 /* 17407 */ "FP_TO_UINT_I64_F32_S\000"
5333 /* 17428 */ "SUB_F32_S\000"
5334 /* 17438 */ "TRUNC_F32_S\000"
5335 /* 17450 */ "ADD_F32_S\000"
5336 /* 17460 */ "LOCAL_TEE_F32_S\000"
5337 /* 17476 */ "GE_F32_S\000"
5338 /* 17485 */ "LE_F32_S\000"
5339 /* 17494 */ "NE_F32_S\000"
5340 /* 17503 */ "F64_PROMOTE_F32_S\000"
5341 /* 17521 */ "NEG_F32_S\000"
5342 /* 17531 */ "CEIL_F32_S\000"
5343 /* 17542 */ "MUL_F32_S\000"
5344 /* 17552 */ "COPYSIGN_F32_S\000"
5345 /* 17567 */ "MIN_F32_S\000"
5346 /* 17577 */ "DROP_F32_S\000"
5347 /* 17588 */ "EQ_F32_S\000"
5348 /* 17597 */ "FLOOR_F32_S\000"
5349 /* 17609 */ "ABS_F32_S\000"
5350 /* 17619 */ "I32_TRUNC_S_F32_S\000"
5351 /* 17637 */ "I64_TRUNC_S_F32_S\000"
5352 /* 17655 */ "I32_TRUNC_S_SAT_F32_S\000"
5353 /* 17677 */ "I64_TRUNC_S_SAT_F32_S\000"
5354 /* 17699 */ "I32_TRUNC_U_SAT_F32_S\000"
5355 /* 17721 */ "I64_TRUNC_U_SAT_F32_S\000"
5356 /* 17743 */ "SELECT_F32_S\000"
5357 /* 17756 */ "GLOBAL_GET_F32_S\000"
5358 /* 17773 */ "LOCAL_GET_F32_S\000"
5359 /* 17789 */ "I32_REINTERPRET_F32_S\000"
5360 /* 17811 */ "GLOBAL_SET_F32_S\000"
5361 /* 17828 */ "LOCAL_SET_F32_S\000"
5362 /* 17844 */ "GT_F32_S\000"
5363 /* 17853 */ "LT_F32_S\000"
5364 /* 17862 */ "SQRT_F32_S\000"
5365 /* 17873 */ "NEAREST_F32_S\000"
5366 /* 17887 */ "CONST_F32_S\000"
5367 /* 17899 */ "I32_TRUNC_U_F32_S\000"
5368 /* 17917 */ "I64_TRUNC_U_F32_S\000"
5369 /* 17935 */ "DIV_F32_S\000"
5370 /* 17945 */ "MAX_F32_S\000"
5371 /* 17955 */ "COPY_F32_S\000"
5372 /* 17966 */ "SUB_I32_S\000"
5373 /* 17976 */ "ADD_I32_S\000"
5374 /* 17986 */ "AND_I32_S\000"
5375 /* 17996 */ "LOCAL_TEE_I32_S\000"
5376 /* 18012 */ "BR_TABLE_I32_S\000"
5377 /* 18027 */ "NE_I32_S\000"
5378 /* 18036 */ "SHL_I32_S\000"
5379 /* 18046 */ "ROTL_I32_S\000"
5380 /* 18057 */ "MUL_I32_S\000"
5381 /* 18067 */ "DROP_I32_S\000"
5382 /* 18078 */ "EQ_I32_S\000"
5383 /* 18087 */ "XOR_I32_S\000"
5384 /* 18097 */ "ROTR_I32_S\000"
5385 /* 18108 */ "I32_EXTEND16_S_I32_S\000"
5386 /* 18129 */ "I32_EXTEND8_S_I32_S\000"
5387 /* 18149 */ "I64_EXTEND_S_I32_S\000"
5388 /* 18168 */ "GE_S_I32_S\000"
5389 /* 18179 */ "LE_S_I32_S\000"
5390 /* 18190 */ "REM_S_I32_S\000"
5391 /* 18202 */ "SHR_S_I32_S\000"
5392 /* 18214 */ "GT_S_I32_S\000"
5393 /* 18225 */ "LT_S_I32_S\000"
5394 /* 18236 */ "F32_CONVERT_S_I32_S\000"
5395 /* 18256 */ "F64_CONVERT_S_I32_S\000"
5396 /* 18276 */ "DIV_S_I32_S\000"
5397 /* 18288 */ "SELECT_I32_S\000"
5398 /* 18301 */ "GLOBAL_GET_I32_S\000"
5399 /* 18318 */ "LOCAL_GET_I32_S\000"
5400 /* 18334 */ "F32_REINTERPRET_I32_S\000"
5401 /* 18356 */ "GLOBAL_SET_I32_S\000"
5402 /* 18373 */ "LOCAL_SET_I32_S\000"
5403 /* 18389 */ "POPCNT_I32_S\000"
5404 /* 18402 */ "CONST_I32_S\000"
5405 /* 18414 */ "I64_EXTEND_U_I32_S\000"
5406 /* 18433 */ "GE_U_I32_S\000"
5407 /* 18444 */ "LE_U_I32_S\000"
5408 /* 18455 */ "REM_U_I32_S\000"
5409 /* 18467 */ "SHR_U_I32_S\000"
5410 /* 18479 */ "GT_U_I32_S\000"
5411 /* 18490 */ "LT_U_I32_S\000"
5412 /* 18501 */ "F32_CONVERT_U_I32_S\000"
5413 /* 18521 */ "F64_CONVERT_U_I32_S\000"
5414 /* 18541 */ "DIV_U_I32_S\000"
5415 /* 18553 */ "COPY_I32_S\000"
5416 /* 18564 */ "CLZ_I32_S\000"
5417 /* 18574 */ "EQZ_I32_S\000"
5418 /* 18584 */ "CTZ_I32_S\000"
5419 /* 18594 */ "ARGUMENT_v4f32_S\000"
5420 /* 18611 */ "ARGUMENT_f32_S\000"
5421 /* 18626 */ "ARGUMENT_v4i32_S\000"
5422 /* 18643 */ "ARGUMENT_i32_S\000"
5423 /* 18658 */ "CONST_V128_F64x2_S\000"
5424 /* 18677 */ "SUB_F64x2_S\000"
5425 /* 18689 */ "TRUNC_F64x2_S\000"
5426 /* 18703 */ "NMADD_F64x2_S\000"
5427 /* 18717 */ "GE_F64x2_S\000"
5428 /* 18728 */ "LE_F64x2_S\000"
5429 /* 18739 */ "REPLACE_LANE_F64x2_S\000"
5430 /* 18760 */ "EXTRACT_LANE_F64x2_S\000"
5431 /* 18781 */ "NEG_F64x2_S\000"
5432 /* 18793 */ "CEIL_F64x2_S\000"
5433 /* 18806 */ "MUL_F64x2_S\000"
5434 /* 18818 */ "SIMD_RELAXED_FMIN_F64x2_S\000"
5435 /* 18844 */ "PMIN_F64x2_S\000"
5436 /* 18857 */ "EQ_F64x2_S\000"
5437 /* 18868 */ "FLOOR_F64x2_S\000"
5438 /* 18882 */ "ABS_F64x2_S\000"
5439 /* 18894 */ "SPLAT_F64x2_S\000"
5440 /* 18908 */ "GT_F64x2_S\000"
5441 /* 18919 */ "LT_F64x2_S\000"
5442 /* 18930 */ "SQRT_F64x2_S\000"
5443 /* 18943 */ "NEAREST_F64x2_S\000"
5444 /* 18959 */ "DIV_F64x2_S\000"
5445 /* 18971 */ "SIMD_RELAXED_FMAX_F64x2_S\000"
5446 /* 18997 */ "PMAX_F64x2_S\000"
5447 /* 19010 */ "convert_low_s_F64x2_S\000"
5448 /* 19032 */ "convert_low_u_F64x2_S\000"
5449 /* 19054 */ "promote_low_F64x2_S\000"
5450 /* 19074 */ "CONST_V128_I64x2_S\000"
5451 /* 19093 */ "SUB_I64x2_S\000"
5452 /* 19105 */ "ADD_I64x2_S\000"
5453 /* 19117 */ "REPLACE_LANE_I64x2_S\000"
5454 /* 19138 */ "EXTRACT_LANE_I64x2_S\000"
5455 /* 19159 */ "ALLTRUE_I64x2_S\000"
5456 /* 19175 */ "NEG_I64x2_S\000"
5457 /* 19187 */ "BITMASK_I64x2_S\000"
5458 /* 19203 */ "SHL_I64x2_S\000"
5459 /* 19215 */ "MUL_I64x2_S\000"
5460 /* 19227 */ "EQ_I64x2_S\000"
5461 /* 19238 */ "ABS_I64x2_S\000"
5462 /* 19250 */ "GE_S_I64x2_S\000"
5463 /* 19263 */ "LE_S_I64x2_S\000"
5464 /* 19276 */ "EXTMUL_HIGH_S_I64x2_S\000"
5465 /* 19298 */ "SHR_S_I64x2_S\000"
5466 /* 19312 */ "GT_S_I64x2_S\000"
5467 /* 19325 */ "LT_S_I64x2_S\000"
5468 /* 19338 */ "EXTMUL_LOW_S_I64x2_S\000"
5469 /* 19359 */ "SPLAT_I64x2_S\000"
5470 /* 19373 */ "LANESELECT_I64x2_S\000"
5471 /* 19392 */ "EXTMUL_HIGH_U_I64x2_S\000"
5472 /* 19414 */ "SHR_U_I64x2_S\000"
5473 /* 19428 */ "EXTMUL_LOW_U_I64x2_S\000"
5474 /* 19449 */ "extend_high_s_I64x2_S\000"
5475 /* 19471 */ "extend_low_s_I64x2_S\000"
5476 /* 19492 */ "extend_high_u_I64x2_S\000"
5477 /* 19514 */ "extend_low_u_I64x2_S\000"
5478 /* 19535 */ "LOAD_F16_F32_A64_S\000"
5479 /* 19554 */ "STORE_F16_F32_A64_S\000"
5480 /* 19574 */ "LOAD_F32_A64_S\000"
5481 /* 19589 */ "STORE_F32_A64_S\000"
5482 /* 19605 */ "ATOMIC_STORE16_I32_A64_S\000"
5483 /* 19630 */ "ATOMIC_STORE8_I32_A64_S\000"
5484 /* 19654 */ "ATOMIC_RMW16_U_SUB_I32_A64_S\000"
5485 /* 19683 */ "ATOMIC_RMW8_U_SUB_I32_A64_S\000"
5486 /* 19711 */ "ATOMIC_RMW_SUB_I32_A64_S\000"
5487 /* 19736 */ "ATOMIC_LOAD_I32_A64_S\000"
5488 /* 19758 */ "ATOMIC_RMW16_U_ADD_I32_A64_S\000"
5489 /* 19787 */ "ATOMIC_RMW8_U_ADD_I32_A64_S\000"
5490 /* 19815 */ "ATOMIC_RMW_ADD_I32_A64_S\000"
5491 /* 19840 */ "ATOMIC_RMW16_U_AND_I32_A64_S\000"
5492 /* 19869 */ "ATOMIC_RMW8_U_AND_I32_A64_S\000"
5493 /* 19897 */ "ATOMIC_RMW_AND_I32_A64_S\000"
5494 /* 19922 */ "ATOMIC_STORE_I32_A64_S\000"
5495 /* 19945 */ "ATOMIC_RMW16_U_CMPXCHG_I32_A64_S\000"
5496 /* 19978 */ "ATOMIC_RMW8_U_CMPXCHG_I32_A64_S\000"
5497 /* 20010 */ "ATOMIC_RMW_CMPXCHG_I32_A64_S\000"
5498 /* 20039 */ "ATOMIC_RMW16_U_XCHG_I32_A64_S\000"
5499 /* 20069 */ "ATOMIC_RMW8_U_XCHG_I32_A64_S\000"
5500 /* 20098 */ "ATOMIC_RMW_XCHG_I32_A64_S\000"
5501 /* 20124 */ "ATOMIC_RMW16_U_XOR_I32_A64_S\000"
5502 /* 20153 */ "ATOMIC_RMW8_U_XOR_I32_A64_S\000"
5503 /* 20181 */ "ATOMIC_RMW_XOR_I32_A64_S\000"
5504 /* 20206 */ "ATOMIC_RMW16_U_OR_I32_A64_S\000"
5505 /* 20234 */ "ATOMIC_RMW8_U_OR_I32_A64_S\000"
5506 /* 20261 */ "ATOMIC_RMW_OR_I32_A64_S\000"
5507 /* 20285 */ "LOAD16_S_I32_A64_S\000"
5508 /* 20304 */ "LOAD8_S_I32_A64_S\000"
5509 /* 20322 */ "ATOMIC_LOAD16_U_I32_A64_S\000"
5510 /* 20348 */ "ATOMIC_LOAD8_U_I32_A64_S\000"
5511 /* 20373 */ "MEMORY_ATOMIC_WAIT32_A64_S\000"
5512 /* 20400 */ "LOAD_LANE_32_A64_S\000"
5513 /* 20419 */ "LOAD_ZERO_32_A64_S\000"
5514 /* 20438 */ "STORE_LANE_I64x2_A64_S\000"
5515 /* 20461 */ "LOAD_EXTEND_S_I64x2_A64_S\000"
5516 /* 20487 */ "LOAD_EXTEND_U_I64x2_A64_S\000"
5517 /* 20513 */ "LOAD_F64_A64_S\000"
5518 /* 20528 */ "STORE_F64_A64_S\000"
5519 /* 20544 */ "ATOMIC_STORE32_I64_A64_S\000"
5520 /* 20569 */ "ATOMIC_STORE16_I64_A64_S\000"
5521 /* 20594 */ "ATOMIC_STORE8_I64_A64_S\000"
5522 /* 20618 */ "ATOMIC_RMW32_U_SUB_I64_A64_S\000"
5523 /* 20647 */ "ATOMIC_RMW16_U_SUB_I64_A64_S\000"
5524 /* 20676 */ "ATOMIC_RMW8_U_SUB_I64_A64_S\000"
5525 /* 20704 */ "ATOMIC_RMW_SUB_I64_A64_S\000"
5526 /* 20729 */ "ATOMIC_LOAD_I64_A64_S\000"
5527 /* 20751 */ "ATOMIC_RMW32_U_ADD_I64_A64_S\000"
5528 /* 20780 */ "ATOMIC_RMW16_U_ADD_I64_A64_S\000"
5529 /* 20809 */ "ATOMIC_RMW8_U_ADD_I64_A64_S\000"
5530 /* 20837 */ "ATOMIC_RMW_ADD_I64_A64_S\000"
5531 /* 20862 */ "ATOMIC_RMW32_U_AND_I64_A64_S\000"
5532 /* 20891 */ "ATOMIC_RMW16_U_AND_I64_A64_S\000"
5533 /* 20920 */ "ATOMIC_RMW8_U_AND_I64_A64_S\000"
5534 /* 20948 */ "ATOMIC_RMW_AND_I64_A64_S\000"
5535 /* 20973 */ "ATOMIC_STORE_I64_A64_S\000"
5536 /* 20996 */ "ATOMIC_RMW32_U_CMPXCHG_I64_A64_S\000"
5537 /* 21029 */ "ATOMIC_RMW16_U_CMPXCHG_I64_A64_S\000"
5538 /* 21062 */ "ATOMIC_RMW8_U_CMPXCHG_I64_A64_S\000"
5539 /* 21094 */ "ATOMIC_RMW_CMPXCHG_I64_A64_S\000"
5540 /* 21123 */ "ATOMIC_RMW32_U_XCHG_I64_A64_S\000"
5541 /* 21153 */ "ATOMIC_RMW16_U_XCHG_I64_A64_S\000"
5542 /* 21183 */ "ATOMIC_RMW8_U_XCHG_I64_A64_S\000"
5543 /* 21212 */ "ATOMIC_RMW_XCHG_I64_A64_S\000"
5544 /* 21238 */ "ATOMIC_RMW32_U_XOR_I64_A64_S\000"
5545 /* 21267 */ "ATOMIC_RMW16_U_XOR_I64_A64_S\000"
5546 /* 21296 */ "ATOMIC_RMW8_U_XOR_I64_A64_S\000"
5547 /* 21324 */ "ATOMIC_RMW_XOR_I64_A64_S\000"
5548 /* 21349 */ "ATOMIC_RMW32_U_OR_I64_A64_S\000"
5549 /* 21377 */ "ATOMIC_RMW16_U_OR_I64_A64_S\000"
5550 /* 21405 */ "ATOMIC_RMW8_U_OR_I64_A64_S\000"
5551 /* 21432 */ "ATOMIC_RMW_OR_I64_A64_S\000"
5552 /* 21456 */ "LOAD32_S_I64_A64_S\000"
5553 /* 21475 */ "LOAD16_S_I64_A64_S\000"
5554 /* 21494 */ "LOAD8_S_I64_A64_S\000"
5555 /* 21512 */ "ATOMIC_LOAD32_U_I64_A64_S\000"
5556 /* 21538 */ "ATOMIC_LOAD16_U_I64_A64_S\000"
5557 /* 21564 */ "ATOMIC_LOAD8_U_I64_A64_S\000"
5558 /* 21589 */ "MEMORY_ATOMIC_WAIT64_A64_S\000"
5559 /* 21616 */ "LOAD_LANE_64_A64_S\000"
5560 /* 21635 */ "LOAD_ZERO_64_A64_S\000"
5561 /* 21654 */ "STORE_LANE_I32x4_A64_S\000"
5562 /* 21677 */ "LOAD_EXTEND_S_I32x4_A64_S\000"
5563 /* 21703 */ "LOAD_EXTEND_U_I32x4_A64_S\000"
5564 /* 21729 */ "LOAD_LANE_16_A64_S\000"
5565 /* 21748 */ "STORE_LANE_I8x16_A64_S\000"
5566 /* 21771 */ "LOAD_V128_A64_S\000"
5567 /* 21787 */ "STORE_V128_A64_S\000"
5568 /* 21804 */ "LOAD_LANE_8_A64_S\000"
5569 /* 21822 */ "STORE_LANE_I16x8_A64_S\000"
5570 /* 21845 */ "LOAD_EXTEND_S_I16x8_A64_S\000"
5571 /* 21871 */ "LOAD_EXTEND_U_I16x8_A64_S\000"
5572 /* 21897 */ "anonymous_14735MEMORY_SIZE_A64_S\000"
5573 /* 21930 */ "MEMORY_FILL_A64_S\000"
5574 /* 21948 */ "LOAD32_SPLAT_A64_S\000"
5575 /* 21967 */ "LOAD64_SPLAT_A64_S\000"
5576 /* 21986 */ "LOAD16_SPLAT_A64_S\000"
5577 /* 22005 */ "LOAD8_SPLAT_A64_S\000"
5578 /* 22023 */ "MEMSET_A64_S\000"
5579 /* 22036 */ "MEMORY_INIT_A64_S\000"
5580 /* 22054 */ "anonymous_14735MEMORY_GROW_A64_S\000"
5581 /* 22087 */ "MEMORY_ATOMIC_NOTIFY_A64_S\000"
5582 /* 22114 */ "MEMCPY_A64_S\000"
5583 /* 22127 */ "MEMORY_COPY_A64_S\000"
5584 /* 22145 */ "FP_TO_SINT_I32_F64_S\000"
5585 /* 22166 */ "FP_TO_UINT_I32_F64_S\000"
5586 /* 22187 */ "FP_TO_SINT_I64_F64_S\000"
5587 /* 22208 */ "FP_TO_UINT_I64_F64_S\000"
5588 /* 22229 */ "SUB_F64_S\000"
5589 /* 22239 */ "TRUNC_F64_S\000"
5590 /* 22251 */ "ADD_F64_S\000"
5591 /* 22261 */ "LOCAL_TEE_F64_S\000"
5592 /* 22277 */ "GE_F64_S\000"
5593 /* 22286 */ "LE_F64_S\000"
5594 /* 22295 */ "NE_F64_S\000"
5595 /* 22304 */ "F32_DEMOTE_F64_S\000"
5596 /* 22321 */ "NEG_F64_S\000"
5597 /* 22331 */ "CEIL_F64_S\000"
5598 /* 22342 */ "MUL_F64_S\000"
5599 /* 22352 */ "COPYSIGN_F64_S\000"
5600 /* 22367 */ "MIN_F64_S\000"
5601 /* 22377 */ "DROP_F64_S\000"
5602 /* 22388 */ "EQ_F64_S\000"
5603 /* 22397 */ "FLOOR_F64_S\000"
5604 /* 22409 */ "ABS_F64_S\000"
5605 /* 22419 */ "I32_TRUNC_S_F64_S\000"
5606 /* 22437 */ "I64_TRUNC_S_F64_S\000"
5607 /* 22455 */ "I32_TRUNC_S_SAT_F64_S\000"
5608 /* 22477 */ "I64_TRUNC_S_SAT_F64_S\000"
5609 /* 22499 */ "I32_TRUNC_U_SAT_F64_S\000"
5610 /* 22521 */ "I64_TRUNC_U_SAT_F64_S\000"
5611 /* 22543 */ "SELECT_F64_S\000"
5612 /* 22556 */ "GLOBAL_GET_F64_S\000"
5613 /* 22573 */ "LOCAL_GET_F64_S\000"
5614 /* 22589 */ "I64_REINTERPRET_F64_S\000"
5615 /* 22611 */ "GLOBAL_SET_F64_S\000"
5616 /* 22628 */ "LOCAL_SET_F64_S\000"
5617 /* 22644 */ "GT_F64_S\000"
5618 /* 22653 */ "LT_F64_S\000"
5619 /* 22662 */ "SQRT_F64_S\000"
5620 /* 22673 */ "NEAREST_F64_S\000"
5621 /* 22687 */ "CONST_F64_S\000"
5622 /* 22699 */ "I32_TRUNC_U_F64_S\000"
5623 /* 22717 */ "I64_TRUNC_U_F64_S\000"
5624 /* 22735 */ "DIV_F64_S\000"
5625 /* 22745 */ "MAX_F64_S\000"
5626 /* 22755 */ "COPY_F64_S\000"
5627 /* 22766 */ "SUB_I64_S\000"
5628 /* 22776 */ "ADD_I64_S\000"
5629 /* 22786 */ "AND_I64_S\000"
5630 /* 22796 */ "LOCAL_TEE_I64_S\000"
5631 /* 22812 */ "BR_TABLE_I64_S\000"
5632 /* 22827 */ "NE_I64_S\000"
5633 /* 22836 */ "SHL_I64_S\000"
5634 /* 22846 */ "ROTL_I64_S\000"
5635 /* 22857 */ "MUL_I64_S\000"
5636 /* 22867 */ "I32_WRAP_I64_S\000"
5637 /* 22882 */ "DROP_I64_S\000"
5638 /* 22893 */ "EQ_I64_S\000"
5639 /* 22902 */ "XOR_I64_S\000"
5640 /* 22912 */ "ROTR_I64_S\000"
5641 /* 22923 */ "I64_EXTEND32_S_I64_S\000"
5642 /* 22944 */ "I64_EXTEND16_S_I64_S\000"
5643 /* 22965 */ "I64_EXTEND8_S_I64_S\000"
5644 /* 22985 */ "GE_S_I64_S\000"
5645 /* 22996 */ "LE_S_I64_S\000"
5646 /* 23007 */ "REM_S_I64_S\000"
5647 /* 23019 */ "SHR_S_I64_S\000"
5648 /* 23031 */ "GT_S_I64_S\000"
5649 /* 23042 */ "LT_S_I64_S\000"
5650 /* 23053 */ "F32_CONVERT_S_I64_S\000"
5651 /* 23073 */ "F64_CONVERT_S_I64_S\000"
5652 /* 23093 */ "DIV_S_I64_S\000"
5653 /* 23105 */ "SELECT_I64_S\000"
5654 /* 23118 */ "GLOBAL_GET_I64_S\000"
5655 /* 23135 */ "LOCAL_GET_I64_S\000"
5656 /* 23151 */ "F64_REINTERPRET_I64_S\000"
5657 /* 23173 */ "GLOBAL_SET_I64_S\000"
5658 /* 23190 */ "LOCAL_SET_I64_S\000"
5659 /* 23206 */ "POPCNT_I64_S\000"
5660 /* 23219 */ "CONST_I64_S\000"
5661 /* 23231 */ "GE_U_I64_S\000"
5662 /* 23242 */ "LE_U_I64_S\000"
5663 /* 23253 */ "REM_U_I64_S\000"
5664 /* 23265 */ "SHR_U_I64_S\000"
5665 /* 23277 */ "GT_U_I64_S\000"
5666 /* 23288 */ "LT_U_I64_S\000"
5667 /* 23299 */ "F32_CONVERT_U_I64_S\000"
5668 /* 23319 */ "F64_CONVERT_U_I64_S\000"
5669 /* 23339 */ "DIV_U_I64_S\000"
5670 /* 23351 */ "COPY_I64_S\000"
5671 /* 23362 */ "CLZ_I64_S\000"
5672 /* 23372 */ "EQZ_I64_S\000"
5673 /* 23382 */ "CTZ_I64_S\000"
5674 /* 23392 */ "ARGUMENT_v2f64_S\000"
5675 /* 23409 */ "ARGUMENT_f64_S\000"
5676 /* 23424 */ "ARGUMENT_v2i64_S\000"
5677 /* 23441 */ "ARGUMENT_i64_S\000"
5678 /* 23456 */ "CONST_V128_F32x4_S\000"
5679 /* 23475 */ "SUB_F32x4_S\000"
5680 /* 23487 */ "TRUNC_F32x4_S\000"
5681 /* 23501 */ "NMADD_F32x4_S\000"
5682 /* 23515 */ "GE_F32x4_S\000"
5683 /* 23526 */ "LE_F32x4_S\000"
5684 /* 23537 */ "REPLACE_LANE_F32x4_S\000"
5685 /* 23558 */ "EXTRACT_LANE_F32x4_S\000"
5686 /* 23579 */ "NEG_F32x4_S\000"
5687 /* 23591 */ "CEIL_F32x4_S\000"
5688 /* 23604 */ "MUL_F32x4_S\000"
5689 /* 23616 */ "SIMD_RELAXED_FMIN_F32x4_S\000"
5690 /* 23642 */ "PMIN_F32x4_S\000"
5691 /* 23655 */ "EQ_F32x4_S\000"
5692 /* 23666 */ "FLOOR_F32x4_S\000"
5693 /* 23680 */ "ABS_F32x4_S\000"
5694 /* 23692 */ "SPLAT_F32x4_S\000"
5695 /* 23706 */ "GT_F32x4_S\000"
5696 /* 23717 */ "LT_F32x4_S\000"
5697 /* 23728 */ "SQRT_F32x4_S\000"
5698 /* 23741 */ "NEAREST_F32x4_S\000"
5699 /* 23757 */ "DIV_F32x4_S\000"
5700 /* 23769 */ "SIMD_RELAXED_FMAX_F32x4_S\000"
5701 /* 23795 */ "PMAX_F32x4_S\000"
5702 /* 23808 */ "demote_zero_F32x4_S\000"
5703 /* 23828 */ "sint_to_fp_F32x4_S\000"
5704 /* 23847 */ "uint_to_fp_F32x4_S\000"
5705 /* 23866 */ "CONST_V128_I32x4_S\000"
5706 /* 23885 */ "SUB_I32x4_S\000"
5707 /* 23897 */ "ADD_I32x4_S\000"
5708 /* 23909 */ "REPLACE_LANE_I32x4_S\000"
5709 /* 23930 */ "EXTRACT_LANE_I32x4_S\000"
5710 /* 23951 */ "ALLTRUE_I32x4_S\000"
5711 /* 23967 */ "NEG_I32x4_S\000"
5712 /* 23979 */ "BITMASK_I32x4_S\000"
5713 /* 23995 */ "SHL_I32x4_S\000"
5714 /* 24007 */ "MUL_I32x4_S\000"
5715 /* 24019 */ "EQ_I32x4_S\000"
5716 /* 24030 */ "ABS_I32x4_S\000"
5717 /* 24042 */ "GE_S_I32x4_S\000"
5718 /* 24055 */ "LE_S_I32x4_S\000"
5719 /* 24068 */ "EXTMUL_HIGH_S_I32x4_S\000"
5720 /* 24090 */ "MIN_S_I32x4_S\000"
5721 /* 24104 */ "SHR_S_I32x4_S\000"
5722 /* 24118 */ "GT_S_I32x4_S\000"
5723 /* 24131 */ "LT_S_I32x4_S\000"
5724 /* 24144 */ "EXTMUL_LOW_S_I32x4_S\000"
5725 /* 24165 */ "MAX_S_I32x4_S\000"
5726 /* 24179 */ "SPLAT_I32x4_S\000"
5727 /* 24193 */ "LANESELECT_I32x4_S\000"
5728 /* 24212 */ "GE_U_I32x4_S\000"
5729 /* 24225 */ "LE_U_I32x4_S\000"
5730 /* 24238 */ "EXTMUL_HIGH_U_I32x4_S\000"
5731 /* 24260 */ "MIN_U_I32x4_S\000"
5732 /* 24274 */ "SHR_U_I32x4_S\000"
5733 /* 24288 */ "GT_U_I32x4_S\000"
5734 /* 24301 */ "LT_U_I32x4_S\000"
5735 /* 24314 */ "EXTMUL_LOW_U_I32x4_S\000"
5736 /* 24335 */ "MAX_U_I32x4_S\000"
5737 /* 24349 */ "int_wasm_relaxed_trunc_signed_I32x4_S\000"
5738 /* 24387 */ "int_wasm_relaxed_trunc_unsigned_I32x4_S\000"
5739 /* 24427 */ "int_wasm_relaxed_trunc_signed_zero_I32x4_S\000"
5740 /* 24470 */ "int_wasm_relaxed_trunc_unsigned_zero_I32x4_S\000"
5741 /* 24515 */ "extadd_pairwise_s_I32x4_S\000"
5742 /* 24541 */ "extend_high_s_I32x4_S\000"
5743 /* 24563 */ "trunc_sat_zero_s_I32x4_S\000"
5744 /* 24588 */ "extend_low_s_I32x4_S\000"
5745 /* 24609 */ "fp_to_sint_I32x4_S\000"
5746 /* 24628 */ "fp_to_uint_I32x4_S\000"
5747 /* 24647 */ "extadd_pairwise_u_I32x4_S\000"
5748 /* 24673 */ "extend_high_u_I32x4_S\000"
5749 /* 24695 */ "trunc_sat_zero_u_I32x4_S\000"
5750 /* 24720 */ "extend_low_u_I32x4_S\000"
5751 /* 24741 */ "ARGUMENT_v8f16_S\000"
5752 /* 24758 */ "ARGUMENT_v8i16_S\000"
5753 /* 24775 */ "CONST_V128_I8x16_S\000"
5754 /* 24794 */ "SUB_I8x16_S\000"
5755 /* 24806 */ "ADD_I8x16_S\000"
5756 /* 24818 */ "REPLACE_LANE_I8x16_S\000"
5757 /* 24839 */ "ALLTRUE_I8x16_S\000"
5758 /* 24855 */ "NEG_I8x16_S\000"
5759 /* 24867 */ "BITMASK_I8x16_S\000"
5760 /* 24883 */ "SHL_I8x16_S\000"
5761 /* 24895 */ "EQ_I8x16_S\000"
5762 /* 24906 */ "ABS_I8x16_S\000"
5763 /* 24918 */ "GE_S_I8x16_S\000"
5764 /* 24931 */ "LE_S_I8x16_S\000"
5765 /* 24944 */ "MIN_S_I8x16_S\000"
5766 /* 24958 */ "SHR_S_I8x16_S\000"
5767 /* 24972 */ "SUB_SAT_S_I8x16_S\000"
5768 /* 24990 */ "ADD_SAT_S_I8x16_S\000"
5769 /* 25008 */ "GT_S_I8x16_S\000"
5770 /* 25021 */ "LT_S_I8x16_S\000"
5771 /* 25034 */ "NARROW_S_I8x16_S\000"
5772 /* 25051 */ "MAX_S_I8x16_S\000"
5773 /* 25065 */ "SPLAT_I8x16_S\000"
5774 /* 25079 */ "LANESELECT_I8x16_S\000"
5775 /* 25098 */ "POPCNT_I8x16_S\000"
5776 /* 25113 */ "GE_U_I8x16_S\000"
5777 /* 25126 */ "LE_U_I8x16_S\000"
5778 /* 25139 */ "MIN_U_I8x16_S\000"
5779 /* 25153 */ "AVGR_U_I8x16_S\000"
5780 /* 25168 */ "SHR_U_I8x16_S\000"
5781 /* 25182 */ "SUB_SAT_U_I8x16_S\000"
5782 /* 25200 */ "ADD_SAT_U_I8x16_S\000"
5783 /* 25218 */ "GT_U_I8x16_S\000"
5784 /* 25231 */ "LT_U_I8x16_S\000"
5785 /* 25244 */ "NARROW_U_I8x16_S\000"
5786 /* 25261 */ "MAX_U_I8x16_S\000"
5787 /* 25275 */ "I64_SUB128_S\000"
5788 /* 25288 */ "I64_ADD128_S\000"
5789 /* 25301 */ "LOCAL_TEE_V128_S\000"
5790 /* 25318 */ "DROP_V128_S\000"
5791 /* 25330 */ "SELECT_V128_S\000"
5792 /* 25344 */ "GLOBAL_GET_V128_S\000"
5793 /* 25362 */ "LOCAL_GET_V128_S\000"
5794 /* 25379 */ "GLOBAL_SET_V128_S\000"
5795 /* 25397 */ "LOCAL_SET_V128_S\000"
5796 /* 25414 */ "COPY_V128_S\000"
5797 /* 25426 */ "ARGUMENT_v16i8_S\000"
5798 /* 25443 */ "SUB_F16x8_S\000"
5799 /* 25455 */ "TRUNC_F16x8_S\000"
5800 /* 25469 */ "NMADD_F16x8_S\000"
5801 /* 25483 */ "GE_F16x8_S\000"
5802 /* 25494 */ "LE_F16x8_S\000"
5803 /* 25505 */ "REPLACE_LANE_F16x8_S\000"
5804 /* 25526 */ "EXTRACT_LANE_F16x8_S\000"
5805 /* 25547 */ "NEG_F16x8_S\000"
5806 /* 25559 */ "CEIL_F16x8_S\000"
5807 /* 25572 */ "MUL_F16x8_S\000"
5808 /* 25584 */ "PMIN_F16x8_S\000"
5809 /* 25597 */ "EQ_F16x8_S\000"
5810 /* 25608 */ "FLOOR_F16x8_S\000"
5811 /* 25622 */ "ABS_F16x8_S\000"
5812 /* 25634 */ "SPLAT_F16x8_S\000"
5813 /* 25648 */ "GT_F16x8_S\000"
5814 /* 25659 */ "LT_F16x8_S\000"
5815 /* 25670 */ "SQRT_F16x8_S\000"
5816 /* 25683 */ "NEAREST_F16x8_S\000"
5817 /* 25699 */ "DIV_F16x8_S\000"
5818 /* 25711 */ "PMAX_F16x8_S\000"
5819 /* 25724 */ "sint_to_fp_F16x8_S\000"
5820 /* 25743 */ "uint_to_fp_F16x8_S\000"
5821 /* 25762 */ "CONST_V128_I16x8_S\000"
5822 /* 25781 */ "SUB_I16x8_S\000"
5823 /* 25793 */ "ADD_I16x8_S\000"
5824 /* 25805 */ "REPLACE_LANE_I16x8_S\000"
5825 /* 25826 */ "ALLTRUE_I16x8_S\000"
5826 /* 25842 */ "NEG_I16x8_S\000"
5827 /* 25854 */ "BITMASK_I16x8_S\000"
5828 /* 25870 */ "SHL_I16x8_S\000"
5829 /* 25882 */ "MUL_I16x8_S\000"
5830 /* 25894 */ "EQ_I16x8_S\000"
5831 /* 25905 */ "ABS_I16x8_S\000"
5832 /* 25917 */ "GE_S_I16x8_S\000"
5833 /* 25930 */ "LE_S_I16x8_S\000"
5834 /* 25943 */ "EXTMUL_HIGH_S_I16x8_S\000"
5835 /* 25965 */ "MIN_S_I16x8_S\000"
5836 /* 25979 */ "SHR_S_I16x8_S\000"
5837 /* 25993 */ "RELAXED_Q15MULR_S_I16x8_S\000"
5838 /* 26019 */ "SUB_SAT_S_I16x8_S\000"
5839 /* 26037 */ "ADD_SAT_S_I16x8_S\000"
5840 /* 26055 */ "Q15MULR_SAT_S_I16x8_S\000"
5841 /* 26077 */ "GT_S_I16x8_S\000"
5842 /* 26090 */ "LT_S_I16x8_S\000"
5843 /* 26103 */ "EXTMUL_LOW_S_I16x8_S\000"
5844 /* 26124 */ "NARROW_S_I16x8_S\000"
5845 /* 26141 */ "MAX_S_I16x8_S\000"
5846 /* 26155 */ "SPLAT_I16x8_S\000"
5847 /* 26169 */ "LANESELECT_I16x8_S\000"
5848 /* 26188 */ "GE_U_I16x8_S\000"
5849 /* 26201 */ "LE_U_I16x8_S\000"
5850 /* 26214 */ "EXTMUL_HIGH_U_I16x8_S\000"
5851 /* 26236 */ "MIN_U_I16x8_S\000"
5852 /* 26250 */ "AVGR_U_I16x8_S\000"
5853 /* 26265 */ "SHR_U_I16x8_S\000"
5854 /* 26279 */ "SUB_SAT_U_I16x8_S\000"
5855 /* 26297 */ "ADD_SAT_U_I16x8_S\000"
5856 /* 26315 */ "GT_U_I16x8_S\000"
5857 /* 26328 */ "LT_U_I16x8_S\000"
5858 /* 26341 */ "EXTMUL_LOW_U_I16x8_S\000"
5859 /* 26362 */ "NARROW_U_I16x8_S\000"
5860 /* 26379 */ "MAX_U_I16x8_S\000"
5861 /* 26393 */ "extadd_pairwise_s_I16x8_S\000"
5862 /* 26419 */ "extend_high_s_I16x8_S\000"
5863 /* 26441 */ "extend_low_s_I16x8_S\000"
5864 /* 26462 */ "fp_to_sint_I16x8_S\000"
5865 /* 26481 */ "fp_to_uint_I16x8_S\000"
5866 /* 26500 */ "extadd_pairwise_u_I16x8_S\000"
5867 /* 26526 */ "extend_high_u_I16x8_S\000"
5868 /* 26548 */ "extend_low_u_I16x8_S\000"
5869 /* 26569 */ "REF_FUNC_S\000"
5870 /* 26580 */ "RELAXED_DOT_ADD_S\000"
5871 /* 26598 */ "AND_S\000"
5872 /* 26604 */ "END_S\000"
5873 /* 26610 */ "ATOMIC_FENCE_S\000"
5874 /* 26625 */ "COMPILER_FENCE_S\000"
5875 /* 26642 */ "I64_MUL_WIDE_S\000"
5876 /* 26657 */ "DEBUG_UNREACHABLE_S\000"
5877 /* 26677 */ "END_TRY_TABLE_S\000"
5878 /* 26693 */ "SHUFFLE_S\000"
5879 /* 26703 */ "RELAXED_SWIZZLE_S\000"
5880 /* 26721 */ "ELSE_S\000"
5881 /* 26728 */ "DELEGATE_S\000"
5882 /* 26739 */ "ANYTRUE_S\000"
5883 /* 26749 */ "TABLE_SIZE_S\000"
5884 /* 26762 */ "LOCAL_TEE_FUNCREF_S\000"
5885 /* 26782 */ "TABLE_FILL_FUNCREF_S\000"
5886 /* 26803 */ "REF_NULL_FUNCREF_S\000"
5887 /* 26822 */ "REF_IS_NULL_FUNCREF_S\000"
5888 /* 26844 */ "DROP_FUNCREF_S\000"
5889 /* 26859 */ "SELECT_FUNCREF_S\000"
5890 /* 26876 */ "TABLE_GET_FUNCREF_S\000"
5891 /* 26896 */ "GLOBAL_GET_FUNCREF_S\000"
5892 /* 26917 */ "LOCAL_GET_FUNCREF_S\000"
5893 /* 26937 */ "TABLE_SET_FUNCREF_S\000"
5894 /* 26957 */ "GLOBAL_SET_FUNCREF_S\000"
5895 /* 26978 */ "LOCAL_SET_FUNCREF_S\000"
5896 /* 26998 */ "REF_TEST_FUNCREF_S\000"
5897 /* 27017 */ "TABLE_GROW_FUNCREF_S\000"
5898 /* 27038 */ "COPY_FUNCREF_S\000"
5899 /* 27053 */ "LOCAL_TEE_EXTERNREF_S\000"
5900 /* 27075 */ "TABLE_FILL_EXTERNREF_S\000"
5901 /* 27098 */ "REF_NULL_EXTERNREF_S\000"
5902 /* 27119 */ "REF_IS_NULL_EXTERNREF_S\000"
5903 /* 27143 */ "DROP_EXTERNREF_S\000"
5904 /* 27160 */ "SELECT_EXTERNREF_S\000"
5905 /* 27179 */ "TABLE_GET_EXTERNREF_S\000"
5906 /* 27201 */ "GLOBAL_GET_EXTERNREF_S\000"
5907 /* 27224 */ "LOCAL_GET_EXTERNREF_S\000"
5908 /* 27246 */ "TABLE_SET_EXTERNREF_S\000"
5909 /* 27268 */ "GLOBAL_SET_EXTERNREF_S\000"
5910 /* 27291 */ "LOCAL_SET_EXTERNREF_S\000"
5911 /* 27313 */ "TABLE_GROW_EXTERNREF_S\000"
5912 /* 27336 */ "COPY_EXTERNREF_S\000"
5913 /* 27353 */ "LOCAL_TEE_EXNREF_S\000"
5914 /* 27372 */ "TABLE_FILL_EXNREF_S\000"
5915 /* 27392 */ "REF_NULL_EXNREF_S\000"
5916 /* 27410 */ "REF_IS_NULL_EXNREF_S\000"
5917 /* 27431 */ "DROP_EXNREF_S\000"
5918 /* 27445 */ "SELECT_EXNREF_S\000"
5919 /* 27461 */ "TABLE_GET_EXNREF_S\000"
5920 /* 27480 */ "GLOBAL_GET_EXNREF_S\000"
5921 /* 27500 */ "LOCAL_GET_EXNREF_S\000"
5922 /* 27519 */ "TABLE_SET_EXNREF_S\000"
5923 /* 27538 */ "GLOBAL_SET_EXNREF_S\000"
5924 /* 27558 */ "LOCAL_SET_EXNREF_S\000"
5925 /* 27577 */ "TABLE_GROW_EXNREF_S\000"
5926 /* 27597 */ "COPY_EXNREF_S\000"
5927 /* 27611 */ "CATCH_REF_S\000"
5928 /* 27623 */ "CATCH_ALL_REF_S\000"
5929 /* 27639 */ "THROW_REF_S\000"
5930 /* 27651 */ "END_IF_S\000"
5931 /* 27660 */ "BR_IF_S\000"
5932 /* 27668 */ "CATCH_S\000"
5933 /* 27676 */ "END_BLOCK_S\000"
5934 /* 27688 */ "RET_CALL_S\000"
5935 /* 27699 */ "CATCH_ALL_S\000"
5936 /* 27711 */ "END_FUNCTION_S\000"
5937 /* 27726 */ "FALLTHROUGH_RETURN_S\000"
5938 /* 27747 */ "ADJCALLSTACKDOWN_S\000"
5939 /* 27766 */ "NOP_S\000"
5940 /* 27772 */ "END_LOOP_S\000"
5941 /* 27783 */ "DATA_DROP_S\000"
5942 /* 27795 */ "ADJCALLSTACKUP_S\000"
5943 /* 27812 */ "BR_S\000"
5944 /* 27817 */ "XOR_S\000"
5945 /* 27823 */ "CALL_PARAMS_S\000"
5946 /* 27837 */ "BR_UNLESS_S\000"
5947 /* 27849 */ "RET_CALL_RESULTS_S\000"
5948 /* 27868 */ "I64_MUL_WIDE_S_S\000"
5949 /* 27885 */ "RELAXED_DOT_BFLOAT_S\000"
5950 /* 27906 */ "G_TRUNC_SSAT_S\000"
5951 /* 27921 */ "BITSELECT_S\000"
5952 /* 27933 */ "RET_CALL_INDIRECT_S\000"
5953 /* 27953 */ "CATCHRET_S\000"
5954 /* 27964 */ "CLEANUPRET_S\000"
5955 /* 27977 */ "RELAXED_DOT_S\000"
5956 /* 27991 */ "ANDNOT_S\000"
5957 /* 28000 */ "I64_MUL_WIDE_U_S\000"
5958 /* 28017 */ "RETHROW_S\000"
5959 /* 28027 */ "CATCH_LEGACY_S\000"
5960 /* 28042 */ "CATCH_ALL_LEGACY_S\000"
5961 /* 28061 */ "TABLE_COPY_S\000"
5962 /* 28074 */ "END_TRY_S\000"
5963 /* 28084 */ "ARGUMENT_funcref_S\000"
5964 /* 28103 */ "ARGUMENT_externref_S\000"
5965 /* 28124 */ "ARGUMENT_exnref_S\000"
5966 /* 28142 */ "EXTRACT_LANE_I8x16_s_S\000"
5967 /* 28165 */ "EXTRACT_LANE_I16x8_s_S\000"
5968 /* 28188 */ "EXTRACT_LANE_I8x16_u_S\000"
5969 /* 28211 */ "EXTRACT_LANE_I16x8_u_S\000"
5970 /* 28234 */ "RELAXED_DOT_BFLOAT\000"
5971 /* 28253 */ "G_SSUBSAT\000"
5972 /* 28263 */ "G_USUBSAT\000"
5973 /* 28273 */ "G_SADDSAT\000"
5974 /* 28283 */ "G_UADDSAT\000"
5975 /* 28293 */ "G_SSHLSAT\000"
5976 /* 28303 */ "G_USHLSAT\000"
5977 /* 28313 */ "G_SMULFIXSAT\000"
5978 /* 28326 */ "G_UMULFIXSAT\000"
5979 /* 28339 */ "G_SDIVFIXSAT\000"
5980 /* 28352 */ "G_UDIVFIXSAT\000"
5981 /* 28365 */ "G_ATOMICRMW_USUB_SAT\000"
5982 /* 28386 */ "G_FPTOSI_SAT\000"
5983 /* 28399 */ "G_FPTOUI_SAT\000"
5984 /* 28412 */ "G_EXTRACT\000"
5985 /* 28422 */ "BITSELECT\000"
5986 /* 28432 */ "G_SELECT\000"
5987 /* 28441 */ "G_BRINDIRECT\000"
5988 /* 28454 */ "RET_CALL_INDIRECT\000"
5989 /* 28472 */ "CATCHRET\000"
5990 /* 28481 */ "CLEANUPRET\000"
5991 /* 28492 */ "PATCHABLE_RET\000"
5992 /* 28506 */ "G_MEMSET\000"
5993 /* 28515 */ "PATCHABLE_FUNCTION_EXIT\000"
5994 /* 28539 */ "G_BRJT\000"
5995 /* 28546 */ "G_EXTRACT_VECTOR_ELT\000"
5996 /* 28567 */ "G_INSERT_VECTOR_ELT\000"
5997 /* 28587 */ "G_FCONSTANT\000"
5998 /* 28599 */ "G_CONSTANT\000"
5999 /* 28610 */ "G_INTRINSIC_CONVERGENT\000"
6000 /* 28633 */ "STATEPOINT\000"
6001 /* 28644 */ "PATCHPOINT\000"
6002 /* 28655 */ "G_PTRTOINT\000"
6003 /* 28666 */ "G_FRINT\000"
6004 /* 28674 */ "G_INTRINSIC_LLRINT\000"
6005 /* 28693 */ "G_INTRINSIC_LRINT\000"
6006 /* 28711 */ "G_FNEARBYINT\000"
6007 /* 28724 */ "RELAXED_DOT\000"
6008 /* 28736 */ "ANDNOT\000"
6009 /* 28743 */ "G_VASTART\000"
6010 /* 28753 */ "LIFETIME_START\000"
6011 /* 28768 */ "G_INVOKE_REGION_START\000"
6012 /* 28790 */ "G_INSERT\000"
6013 /* 28799 */ "G_FSQRT\000"
6014 /* 28807 */ "G_STRICT_FSQRT\000"
6015 /* 28822 */ "G_BITCAST\000"
6016 /* 28832 */ "G_ADDRSPACE_CAST\000"
6017 /* 28849 */ "DBG_VALUE_LIST\000"
6018 /* 28864 */ "G_FPEXT\000"
6019 /* 28872 */ "G_SEXT\000"
6020 /* 28879 */ "G_ASSERT_SEXT\000"
6021 /* 28893 */ "G_ANYEXT\000"
6022 /* 28902 */ "G_ZEXT\000"
6023 /* 28909 */ "G_ASSERT_ZEXT\000"
6024 /* 28923 */ "G_ABDU\000"
6025 /* 28930 */ "I64_MUL_WIDE_U\000"
6026 /* 28945 */ "G_TRUNC_SSAT_U\000"
6027 /* 28960 */ "G_TRUNC_USAT_U\000"
6028 /* 28975 */ "G_FDIV\000"
6029 /* 28982 */ "G_STRICT_FDIV\000"
6030 /* 28996 */ "G_SDIV\000"
6031 /* 29003 */ "G_UDIV\000"
6032 /* 29010 */ "G_GET_FPENV\000"
6033 /* 29022 */ "G_RESET_FPENV\000"
6034 /* 29036 */ "G_SET_FPENV\000"
6035 /* 29048 */ "G_FPOW\000"
6036 /* 29055 */ "RETHROW\000"
6037 /* 29063 */ "G_VECREDUCE_FMAX\000"
6038 /* 29080 */ "G_ATOMICRMW_FMAX\000"
6039 /* 29097 */ "G_VECREDUCE_SMAX\000"
6040 /* 29114 */ "G_SMAX\000"
6041 /* 29121 */ "G_VECREDUCE_UMAX\000"
6042 /* 29138 */ "G_UMAX\000"
6043 /* 29145 */ "G_ATOMICRMW_UMAX\000"
6044 /* 29162 */ "G_ATOMICRMW_MAX\000"
6045 /* 29178 */ "G_FRAME_INDEX\000"
6046 /* 29192 */ "G_SBFX\000"
6047 /* 29199 */ "G_UBFX\000"
6048 /* 29206 */ "G_SMULFIX\000"
6049 /* 29216 */ "G_UMULFIX\000"
6050 /* 29226 */ "G_SDIVFIX\000"
6051 /* 29236 */ "G_UDIVFIX\000"
6052 /* 29246 */ "CATCH_LEGACY\000"
6053 /* 29259 */ "CATCH_ALL_LEGACY\000"
6054 /* 29276 */ "G_MEMCPY\000"
6055 /* 29285 */ "TABLE_COPY\000"
6056 /* 29296 */ "CONVERGENCECTRL_ENTRY\000"
6057 /* 29318 */ "END_TRY\000"
6058 /* 29326 */ "G_CTLZ\000"
6059 /* 29333 */ "G_CTTZ\000"
6060 /* 29340 */ "ARGUMENT_funcref\000"
6061 /* 29357 */ "ARGUMENT_externref\000"
6062 /* 29376 */ "ARGUMENT_exnref\000"
6063 /* 29392 */ "EXTRACT_LANE_I8x16_s\000"
6064 /* 29413 */ "EXTRACT_LANE_I16x8_s\000"
6065 /* 29434 */ "EXTRACT_LANE_I8x16_u\000"
6066 /* 29455 */ "EXTRACT_LANE_I16x8_u\000"
6067};
6068#ifdef __GNUC__
6069#pragma GCC diagnostic pop
6070#endif
6071
6072extern const unsigned WebAssemblyInstrNameIndices[] = {
6073 12794U, 13229U, 14025U, 13600U, 12877U, 12858U, 12886U, 13065U,
6074 12581U, 12596U, 11737U, 11724U, 12623U, 14564U, 11545U, 28849U,
6075 12537U, 12790U, 12867U, 11245U, 29291U, 12834U, 11399U, 28753U,
6076 11044U, 11168U, 11218U, 13730U, 13043U, 28644U, 11151U, 13960U,
6077 12716U, 28633U, 11457U, 13933U, 13920U, 14086U, 28492U, 28515U,
6078 12966U, 13022U, 12995U, 12903U, 11527U, 14051U, 13684U, 11446U,
6079 29296U, 14204U, 13881U, 11593U, 28879U, 28909U, 13430U, 10941U,
6080 10643U, 13168U, 28996U, 29003U, 13195U, 13202U, 13209U, 13219U,
6081 11022U, 14413U, 14376U, 14464U, 28923U, 14248U, 12955U, 14236U,
6082 12944U, 11735U, 12792U, 29178U, 11555U, 11570U, 13070U, 28412U,
6083 14471U, 28790U, 14488U, 14299U, 10722U, 14547U, 28655U, 14440U,
6084 28822U, 11644U, 14062U, 11125U, 10696U, 11107U, 28693U, 28674U,
6085 13408U, 14111U, 14130U, 10842U, 10786U, 10816U, 10827U, 10767U,
6086 10797U, 11501U, 11485U, 14594U, 12637U, 12654U, 10973U, 10649U,
6087 11028U, 10989U, 14418U, 14382U, 29162U, 13556U, 29145U, 13539U,
6088 10908U, 10626U, 29080U, 13474U, 13324U, 13271U, 13792U, 13770U,
6089 11066U, 28365U, 11210U, 12739U, 11057U, 28441U, 28768U, 10665U,
6090 14652U, 28610U, 14679U, 28893U, 10714U, 27906U, 28945U, 28960U,
6091 28599U, 28587U, 28743U, 12708U, 28872U, 12610U, 28902U, 12930U,
6092 14197U, 14183U, 12923U, 14190U, 14433U, 13086U, 13847U, 13840U,
6093 13854U, 13861U, 28432U, 13676U, 11266U, 13660U, 11189U, 13668U,
6094 11258U, 13652U, 11181U, 13714U, 13706U, 12758U, 12750U, 28283U,
6095 28273U, 28263U, 28253U, 28303U, 28293U, 29206U, 29216U, 28313U,
6096 28326U, 29226U, 29236U, 28339U, 28352U, 10866U, 10605U, 13110U,
6097 10586U, 10760U, 28975U, 13174U, 11680U, 29048U, 12816U, 14004U,
6098 3559U, 9U, 12701U, 3542U, 0U, 13979U, 14011U, 12574U,
6099 28864U, 10686U, 12798U, 12807U, 13822U, 13831U, 28386U, 28399U,
6100 14451U, 13445U, 14581U, 11653U, 13373U, 13383U, 11315U, 11330U,
6101 13260U, 13313U, 13345U, 13359U, 29010U, 29036U, 29022U, 11274U,
6102 11302U, 11287U, 12671U, 12686U, 10947U, 12848U, 13508U, 29114U,
6103 13532U, 29138U, 14458U, 11098U, 11088U, 14020U, 28539U, 11345U,
6104 14280U, 14260U, 28567U, 28546U, 14314U, 14345U, 14331U, 14634U,
6105 29333U, 11706U, 29326U, 11688U, 14503U, 13902U, 13814U, 11514U,
6106 12936U, 14530U, 13580U, 14537U, 13401U, 14522U, 13572U, 13393U,
6107 3550U, 12782U, 12774U, 12766U, 28799U, 14227U, 28666U, 28711U,
6108 28832U, 14038U, 11372U, 10743U, 11622U, 11470U, 10894U, 10612U,
6109 13138U, 28982U, 13181U, 10592U, 28807U, 13988U, 14150U, 14166U,
6110 29276U, 11430U, 11634U, 28506U, 13722U, 13763U, 13739U, 13751U,
6111 10873U, 13117U, 10849U, 13093U, 29063U, 13457U, 13292U, 13239U,
6112 10925U, 13152U, 11006U, 14398U, 14360U, 29097U, 13491U, 29121U,
6113 13515U, 29192U, 29199U, 14510U, 27823U, 14721U, 27853U, 28472U,
6114 27953U, 28481U, 27964U, 11230U, 26625U, 14717U, 27849U, 9755U,
6115 25622U, 2641U, 17609U, 8049U, 23680U, 6956U, 22409U, 3761U,
6116 18882U, 9998U, 25905U, 8353U, 24030U, 4071U, 19238U, 9137U,
6117 24906U, 9626U, 25471U, 2510U, 17450U, 7896U, 23503U, 6826U,
6118 22251U, 3608U, 18705U, 9902U, 25793U, 2960U, 17976U, 8238U,
6119 23897U, 7275U, 22776U, 3956U, 19105U, 9051U, 24806U, 10114U,
6120 26037U, 9209U, 24990U, 10342U, 26297U, 9391U, 25200U, 13635U,
6121 27747U, 13945U, 27795U, 9931U, 25826U, 8286U, 23951U, 4004U,
6122 19159U, 9080U, 24839U, 11002U, 28736U, 27991U, 2968U, 17986U,
6123 7283U, 22786U, 26598U, 11614U, 26739U, 29376U, 28124U, 29357U,
6124 28103U, 3501U, 18611U, 7814U, 23409U, 29340U, 28084U, 3529U,
6125 18643U, 7842U, 23441U, 9587U, 25426U, 7799U, 23392U, 7827U,
6126 23424U, 3486U, 18594U, 3514U, 18626U, 8994U, 24741U, 9009U,
6127 24758U, 11197U, 26610U, 743U, 15521U, 5059U, 20322U, 1865U,
6128 16737U, 6181U, 21538U, 1841U, 16711U, 6157U, 21512U, 767U,
6129 15547U, 5083U, 20348U, 1889U, 16763U, 6205U, 21564U, 201U,
6130 14935U, 4517U, 19736U, 1116U, 15928U, 5432U, 20729U, 221U,
6131 14957U, 4537U, 19758U, 1163U, 15979U, 5479U, 20780U, 297U,
6132 15039U, 4613U, 19840U, 1266U, 16090U, 5582U, 20891U, 394U,
6133 15144U, 4710U, 19945U, 1394U, 16228U, 5710U, 21029U, 637U,
6134 15405U, 4953U, 20206U, 1718U, 16576U, 6034U, 21377U, 125U,
6135 14853U, 4441U, 19654U, 1040U, 15846U, 5356U, 20647U, 482U,
6136 15238U, 4798U, 20039U, 1510U, 16352U, 5826U, 21153U, 561U,
6137 15323U, 4877U, 20124U, 1616U, 16466U, 5932U, 21267U, 1136U,
6138 15950U, 5452U, 20751U, 1239U, 16061U, 5555U, 20862U, 1363U,
6139 16195U, 5679U, 20996U, 1692U, 16548U, 6008U, 21349U, 1013U,
6140 15817U, 5329U, 20618U, 1482U, 16322U, 5798U, 21123U, 1589U,
6141 16437U, 5905U, 21238U, 248U, 14986U, 4564U, 19787U, 1190U,
6142 16008U, 5506U, 20809U, 324U, 15068U, 4640U, 19869U, 1293U,
6143 16119U, 5609U, 20920U, 425U, 15177U, 4741U, 19978U, 1425U,
6144 16261U, 5741U, 21062U, 663U, 15433U, 4979U, 20234U, 1744U,
6145 16604U, 6060U, 21405U, 152U, 14882U, 4468U, 19683U, 1067U,
6146 15875U, 5383U, 20676U, 510U, 15268U, 4826U, 20069U, 1538U,
6147 16382U, 5854U, 21183U, 588U, 15352U, 4904U, 20153U, 1643U,
6148 16495U, 5959U, 21296U, 274U, 15014U, 4590U, 19815U, 1216U,
6149 16036U, 5532U, 20837U, 350U, 15096U, 4666U, 19897U, 1319U,
6150 16147U, 5635U, 20948U, 455U, 15209U, 4771U, 20010U, 1455U,
6151 16293U, 5771U, 21094U, 688U, 15460U, 5004U, 20261U, 1769U,
6152 16631U, 6085U, 21432U, 178U, 14910U, 4494U, 19711U, 1093U,
6153 15903U, 5409U, 20704U, 537U, 15297U, 4853U, 20098U, 1565U,
6154 16411U, 5881U, 21212U, 614U, 15380U, 4930U, 20181U, 1669U,
6155 16523U, 5985U, 21324U, 80U, 14804U, 4396U, 19605U, 968U,
6156 15768U, 5284U, 20569U, 945U, 15743U, 5261U, 20544U, 103U,
6157 14829U, 4419U, 19630U, 991U, 15793U, 5307U, 20594U, 373U,
6158 15121U, 4689U, 19922U, 1342U, 16172U, 5658U, 20973U, 10301U,
6159 26250U, 9350U, 25153U, 9955U, 25854U, 8310U, 23979U, 4028U,
6160 19187U, 9104U, 24867U, 28422U, 27921U, 12828U, 27680U, 14022U,
6161 12568U, 27660U, 27812U, 2990U, 18012U, 7305U, 22812U, 14624U,
6162 27837U, 12981U, 28458U, 27937U, 27692U, 12733U, 13055U, 29259U,
6163 28042U, 12523U, 27623U, 27699U, 29246U, 28027U, 12513U, 27611U,
6164 27668U, 9702U, 25559U, 2577U, 17531U, 7972U, 23591U, 6892U,
6165 22331U, 3684U, 18793U, 3462U, 18564U, 7775U, 23362U, 2885U,
6166 17887U, 7200U, 22687U, 3324U, 18402U, 7654U, 23219U, 7855U,
6167 23456U, 3567U, 18658U, 9875U, 25762U, 8211U, 23866U, 3929U,
6168 19074U, 9024U, 24775U, 2594U, 17552U, 6909U, 22352U, 12501U,
6169 27597U, 12268U, 27336U, 2943U, 17955U, 7258U, 22755U, 11998U,
6170 27038U, 3453U, 18553U, 7766U, 23351U, 9577U, 25414U, 3478U,
6171 18584U, 7791U, 23382U, 13910U, 27783U, 11354U, 26657U, 11536U,
6172 26728U, 9820U, 25699U, 2927U, 17935U, 8114U, 23757U, 7242U,
6173 22735U, 3826U, 18959U, 3214U, 18276U, 7544U, 23093U, 3443U,
6174 18541U, 7756U, 23339U, 28732U, 27985U, 12353U, 27431U, 12093U,
6175 27143U, 2615U, 17577U, 6930U, 22377U, 11824U, 26844U, 3035U,
6176 18067U, 7363U, 22882U, 9493U, 25318U, 11509U, 26721U, 11053U,
6177 12824U, 27676U, 13587U, 27711U, 12561U, 27651U, 13872U, 27772U,
6178 26604U, 29318U, 28074U, 11385U, 26677U, 3470U, 18574U, 7783U,
6179 23372U, 9734U, 25597U, 2624U, 17588U, 8028U, 23655U, 6939U,
6180 22388U, 3740U, 18857U, 9989U, 25894U, 3044U, 18078U, 8344U,
6181 24019U, 7372U, 22893U, 4062U, 19227U, 9128U, 24895U, 10030U,
6182 25943U, 8385U, 24068U, 4103U, 19276U, 10269U, 26214U, 8533U,
6183 24238U, 4205U, 19392U, 10172U, 26103U, 8451U, 24144U, 4157U,
6184 19338U, 10380U, 26341U, 8599U, 24314U, 4237U, 19428U, 9673U,
6185 25526U, 7943U, 23558U, 3655U, 18760U, 29413U, 28165U, 29455U,
6186 28211U, 8267U, 23930U, 3985U, 19138U, 29392U, 28142U, 29434U,
6187 28188U, 3178U, 18236U, 7508U, 23053U, 3407U, 18501U, 7720U,
6188 23299U, 6869U, 22304U, 3264U, 18334U, 3196U, 18256U, 7526U,
6189 23073U, 3425U, 18521U, 7738U, 23319U, 2553U, 17503U, 7594U,
6190 23151U, 13616U, 27726U, 9743U, 25608U, 2631U, 17597U, 8037U,
6191 23666U, 6946U, 22397U, 3749U, 18868U, 2416U, 17344U, 6732U,
6192 22145U, 2454U, 17386U, 6770U, 22187U, 2435U, 17365U, 6751U,
6193 22166U, 2473U, 17407U, 6789U, 22208U, 9636U, 25483U, 2532U,
6194 17476U, 7906U, 23515U, 6848U, 22277U, 3618U, 18717U, 10008U,
6195 25917U, 3122U, 18168U, 8363U, 24042U, 7452U, 22985U, 4081U,
6196 19250U, 9147U, 24918U, 10247U, 26188U, 3351U, 18433U, 8511U,
6197 24212U, 7664U, 23231U, 9316U, 25113U, 12396U, 27480U, 12145U,
6198 27201U, 2772U, 17756U, 7087U, 22556U, 11870U, 26896U, 3235U,
6199 18301U, 7565U, 23118U, 9515U, 25344U, 12448U, 27538U, 12206U,
6200 27268U, 2821U, 17811U, 7136U, 22611U, 11925U, 26957U, 3284U,
6201 18356U, 7614U, 23173U, 9546U, 25379U, 9777U, 25648U, 2850U,
6202 17844U, 8071U, 23706U, 7165U, 22644U, 3783U, 18908U, 10150U,
6203 26077U, 3160U, 18214U, 8429U, 24118U, 7490U, 23031U, 4135U,
6204 19312U, 9225U, 25008U, 10358U, 26315U, 3389U, 18479U, 8577U,
6205 24288U, 7702U, 23277U, 9407U, 25218U, 3068U, 18108U, 3087U,
6206 18129U, 2801U, 17789U, 2649U, 17619U, 6964U, 22419U, 2681U,
6207 17655U, 6996U, 22455U, 2895U, 17899U, 7210U, 22699U, 2721U,
6208 17699U, 7036U, 22499U, 7350U, 22867U, 9467U, 25288U, 7415U,
6209 22944U, 7396U, 22923U, 7434U, 22965U, 3105U, 18149U, 3334U,
6210 18414U, 26642U, 27868U, 28930U, 28000U, 7116U, 22589U, 9456U,
6211 25275U, 2665U, 17637U, 6980U, 22437U, 2701U, 17677U, 7016U,
6212 22477U, 2911U, 17917U, 7226U, 22717U, 2741U, 17721U, 7056U,
6213 22521U, 12565U, 27655U, 10230U, 26169U, 8494U, 24193U, 4188U,
6214 19373U, 9286U, 25079U, 9645U, 25494U, 2539U, 17485U, 7915U,
6215 23526U, 6855U, 22286U, 3627U, 18728U, 10019U, 25930U, 3131U,
6216 18179U, 8374U, 24055U, 7461U, 22996U, 4092U, 19263U, 9158U,
6217 24931U, 10258U, 26201U, 3360U, 18444U, 8522U, 24225U, 7673U,
6218 23242U, 9327U, 25126U, 2273U, 17185U, 6589U, 21986U, 710U,
6219 15484U, 5026U, 20285U, 1808U, 16674U, 6124U, 21475U, 750U,
6220 15528U, 5066U, 20329U, 1872U, 16744U, 6188U, 21545U, 2239U,
6221 17147U, 6555U, 21948U, 1791U, 16655U, 6107U, 21456U, 1848U,
6222 16718U, 6164U, 21519U, 2256U, 17166U, 6572U, 21967U, 2290U,
6223 17204U, 6606U, 22005U, 727U, 15503U, 5043U, 20304U, 1825U,
6224 16693U, 6141U, 21494U, 774U, 15554U, 5090U, 20355U, 1896U,
6225 16770U, 6212U, 21571U, 2144U, 17044U, 6460U, 21845U, 1992U,
6226 16876U, 6308U, 21677U, 870U, 15660U, 5186U, 20461U, 2168U,
6227 17070U, 6484U, 21871U, 2016U, 16902U, 6332U, 21703U, 894U,
6228 15686U, 5210U, 20487U, 18U, 14734U, 4334U, 19535U, 53U,
6229 14773U, 4369U, 19574U, 918U, 15712U, 5234U, 20513U, 208U,
6230 14942U, 4524U, 19743U, 1123U, 15935U, 5439U, 20736U, 2040U,
6231 16928U, 6356U, 21729U, 815U, 15599U, 5131U, 20400U, 1937U,
6232 16815U, 6253U, 21616U, 2107U, 17003U, 6423U, 21804U, 2078U,
6233 16970U, 6394U, 21771U, 832U, 15618U, 5148U, 20419U, 1954U,
6234 16834U, 6270U, 21635U, 12414U, 27500U, 12166U, 27224U, 2787U,
6235 17773U, 7102U, 22573U, 11889U, 26917U, 3250U, 18318U, 7580U,
6236 23135U, 9531U, 25362U, 12466U, 27558U, 12227U, 27291U, 2836U,
6237 17828U, 7151U, 22628U, 11944U, 26978U, 3299U, 18373U, 7629U,
6238 23190U, 9562U, 25397U, 12283U, 27353U, 12011U, 27053U, 2518U,
6239 17460U, 6834U, 22261U, 11750U, 26762U, 2976U, 17996U, 7291U,
6240 22796U, 9478U, 25301U, 13876U, 27776U, 9786U, 25659U, 2857U,
6241 17853U, 8080U, 23717U, 7172U, 22653U, 3792U, 18919U, 10161U,
6242 26090U, 3169U, 18225U, 8440U, 24131U, 7499U, 23042U, 4146U,
6243 19325U, 9236U, 25021U, 10369U, 26328U, 3398U, 18490U, 8588U,
6244 24301U, 7711U, 23288U, 9418U, 25231U, 9625U, 25470U, 7895U,
6245 23502U, 3607U, 18704U, 9831U, 25712U, 2935U, 17945U, 8138U,
6246 23783U, 7250U, 22745U, 3850U, 18985U, 10206U, 26141U, 8470U,
6247 24165U, 9262U, 25051U, 10414U, 26379U, 8618U, 24335U, 9444U,
6248 25261U, 2389U, 17313U, 6705U, 22114U, 2364U, 17286U, 6680U,
6249 22087U, 790U, 15572U, 5106U, 20373U, 1912U, 16788U, 6228U,
6250 21589U, 2400U, 17326U, 6716U, 22127U, 2223U, 17129U, 6539U,
6251 21930U, 2317U, 17235U, 6633U, 22036U, 2306U, 17222U, 6622U,
6252 22023U, 9724U, 25585U, 2607U, 17567U, 8007U, 23630U, 6922U,
6253 22367U, 3719U, 18832U, 10050U, 25965U, 8405U, 24090U, 9169U,
6254 24944U, 10289U, 26236U, 8553U, 24260U, 9338U, 25139U, 9713U,
6255 25572U, 2586U, 17542U, 7983U, 23604U, 6901U, 22342U, 3695U,
6256 18806U, 9979U, 25882U, 3027U, 18057U, 8334U, 24007U, 7342U,
6257 22857U, 4052U, 19215U, 10191U, 26124U, 9247U, 25034U, 10399U,
6258 26362U, 9429U, 25244U, 9806U, 25683U, 2873U, 17873U, 8100U,
6259 23741U, 7188U, 22673U, 3812U, 18943U, 9692U, 25547U, 2569U,
6260 17521U, 7962U, 23579U, 6884U, 22321U, 3674U, 18781U, 9945U,
6261 25842U, 8300U, 23967U, 4018U, 19175U, 9094U, 24855U, 9664U,
6262 25515U, 2546U, 17494U, 7934U, 23547U, 6862U, 22295U, 3646U,
6263 18749U, 9922U, 25815U, 3003U, 18027U, 8258U, 23919U, 7318U,
6264 22827U, 3976U, 19127U, 9071U, 24828U, 9624U, 25469U, 7894U,
6265 23501U, 3606U, 18703U, 13868U, 27766U, 28739U, 27994U, 14224U,
6266 3052U, 18088U, 7380U, 22903U, 27818U, 9830U, 25711U, 8148U,
6267 23795U, 3860U, 18997U, 9723U, 25584U, 8017U, 23642U, 3729U,
6268 18844U, 3313U, 18389U, 7643U, 23206U, 9303U, 25098U, 10130U,
6269 26055U, 10677U, 26569U, 12334U, 27410U, 12071U, 27119U, 11804U,
6270 26822U, 12318U, 27392U, 12052U, 27098U, 11787U, 26803U, 11962U,
6271 26998U, 28724U, 10957U, 26580U, 28234U, 27885U, 27977U, 10074U,
6272 25993U, 11414U, 26703U, 3140U, 18190U, 7470U, 23007U, 3369U,
6273 18455U, 7682U, 23253U, 9654U, 25505U, 7924U, 23537U, 3636U,
6274 18739U, 9912U, 25805U, 8248U, 23909U, 3966U, 19117U, 9061U,
6275 24818U, 29055U, 28017U, 13628U, 27738U, 12986U, 28454U, 27933U,
6276 27688U, 3018U, 18046U, 7333U, 22846U, 3059U, 18097U, 7387U,
6277 22912U, 12365U, 27445U, 12108U, 27160U, 2761U, 17743U, 7076U,
6278 22543U, 11837U, 26859U, 3224U, 18288U, 7554U, 23105U, 9503U,
6279 25330U, 9969U, 25870U, 3010U, 18036U, 8324U, 23995U, 7325U,
6280 22836U, 4042U, 19203U, 9118U, 24883U, 10062U, 25979U, 3150U,
6281 18202U, 8417U, 24104U, 7480U, 23019U, 4123U, 19298U, 9181U,
6282 24958U, 10314U, 26265U, 3379U, 18467U, 8565U, 24274U, 7692U,
6283 23265U, 4225U, 19414U, 9363U, 25168U, 11406U, 26693U, 8124U,
6284 23769U, 3836U, 18971U, 7993U, 23616U, 3705U, 18818U, 9765U,
6285 25634U, 8059U, 23692U, 3771U, 18894U, 10218U, 26155U, 8482U,
6286 24179U, 4176U, 19359U, 9274U, 25065U, 9795U, 25670U, 2864U,
6287 17862U, 8089U, 23728U, 7179U, 22662U, 3801U, 18930U, 87U,
6288 14811U, 4403U, 19612U, 975U, 15775U, 5291U, 20576U, 952U,
6289 15750U, 5268U, 20551U, 110U, 14836U, 4426U, 19637U, 998U,
6290 15800U, 5314U, 20601U, 35U, 14753U, 4351U, 19554U, 66U,
6291 14788U, 4382U, 19589U, 931U, 15727U, 5247U, 20528U, 380U,
6292 15128U, 4696U, 19929U, 1349U, 16179U, 5665U, 20980U, 2123U,
6293 17021U, 6439U, 21822U, 1971U, 16853U, 6287U, 21654U, 849U,
6294 15637U, 5165U, 20438U, 2057U, 16947U, 6373U, 21748U, 2092U,
6295 16986U, 6408U, 21787U, 9602U, 25443U, 2492U, 17428U, 7872U,
6296 23475U, 6808U, 22229U, 3584U, 18677U, 9892U, 25781U, 2952U,
6297 17966U, 8228U, 23885U, 7267U, 22766U, 3946U, 19093U, 9041U,
6298 24794U, 10098U, 26019U, 9193U, 24972U, 10326U, 26279U, 9375U,
6299 25182U, 11422U, 26711U, 29285U, 28061U, 12300U, 27372U, 12031U,
6300 27075U, 11768U, 26782U, 12379U, 27461U, 12125U, 27179U, 11852U,
6301 26876U, 12483U, 27577U, 12247U, 27313U, 11979U, 27017U, 12431U,
6302 27519U, 12186U, 27246U, 11907U, 26937U, 11669U, 26749U, 12289U,
6303 27359U, 12017U, 27059U, 2524U, 17466U, 6840U, 22267U, 11756U,
6304 26768U, 2982U, 18002U, 7297U, 22802U, 9484U, 25307U, 29057U,
6305 12551U, 27639U, 28019U, 9612U, 25455U, 2500U, 17438U, 7882U,
6306 23487U, 6816U, 22239U, 3594U, 18689U, 29314U, 28078U, 11389U,
6307 26681U, 11360U, 26663U, 14372U, 3051U, 18087U, 7379U, 22902U,
6308 27817U, 2333U, 17253U, 2192U, 17096U, 6649U, 22054U, 6508U,
6309 21897U, 3871U, 19010U, 3891U, 19032U, 8159U, 23808U, 10426U,
6310 26393U, 8788U, 24515U, 10523U, 26500U, 8908U, 24647U, 10450U,
6311 26419U, 8812U, 24541U, 4256U, 19449U, 10547U, 26526U, 8932U,
6312 24673U, 4295U, 19492U, 10470U, 26441U, 8855U, 24588U, 4276U,
6313 19471U, 10567U, 26548U, 8975U, 24720U, 4315U, 19514U, 10489U,
6314 26462U, 8874U, 24609U, 10506U, 26481U, 8891U, 24628U, 8630U,
6315 24349U, 8704U, 24427U, 8666U, 24387U, 8745U, 24470U, 3911U,
6316 19054U, 9841U, 25724U, 8177U, 23828U, 8832U, 24563U, 8952U,
6317 24695U, 9858U, 25743U, 8194U, 23847U,
6318};
6319
6320extern const int16_t WebAssemblyRegClassByHwModeTables[2][1] = {
6321 { // DefaultMode
6322 WebAssembly::I32RegClassID, // wasm_ptr_rc
6323 },
6324 { // WASM64
6325 WebAssembly::I64RegClassID, // wasm_ptr_rc
6326 },
6327};
6328
6329static inline void InitWebAssemblyMCInstrInfo(MCInstrInfo *II) {
6330 II->InitMCInstrInfo(WebAssemblyDescs.Insts, WebAssemblyInstrNameIndices, WebAssemblyInstrNameData, nullptr, nullptr, 1957, &WebAssemblyRegClassByHwModeTables[0][0], 1);
6331}
6332
6333
6334} // namespace llvm
6335
6336#endif // GET_INSTRINFO_MC_DESC
6337
6338#ifdef GET_INSTRINFO_HEADER
6339#undef GET_INSTRINFO_HEADER
6340
6341namespace llvm {
6342
6343struct WebAssemblyGenInstrInfo : public TargetInstrInfo {
6344 explicit WebAssemblyGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
6345 ~WebAssemblyGenInstrInfo() override = default;
6346};
6347extern const int16_t WebAssemblyRegClassByHwModeTables[2][1];
6348
6349} // namespace llvm
6350
6351namespace llvm::WebAssembly {
6352
6353
6354} // namespace llvm::WebAssembly
6355
6356#endif // GET_INSTRINFO_HEADER
6357
6358#ifdef GET_INSTRINFO_HELPER_DECLS
6359#undef GET_INSTRINFO_HELPER_DECLS
6360
6361
6362#endif // GET_INSTRINFO_HELPER_DECLS
6363
6364#ifdef GET_INSTRINFO_HELPERS
6365#undef GET_INSTRINFO_HELPERS
6366
6367
6368#endif // GET_INSTRINFO_HELPERS
6369
6370#ifdef GET_INSTRINFO_CTOR_DTOR
6371#undef GET_INSTRINFO_CTOR_DTOR
6372
6373namespace llvm {
6374
6375extern const WebAssemblyInstrTable WebAssemblyDescs;
6376extern const unsigned WebAssemblyInstrNameIndices[];
6377extern const char WebAssemblyInstrNameData[];
6378WebAssemblyGenInstrInfo::WebAssemblyGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
6379 : TargetInstrInfo(TRI, CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode, WebAssemblyRegClassByHwModeTables[STI.getHwMode(MCSubtargetInfo::HwMode_RegInfo)]) {
6380 InitMCInstrInfo(WebAssemblyDescs.Insts, WebAssemblyInstrNameIndices, WebAssemblyInstrNameData, nullptr, nullptr, 1957, &WebAssemblyRegClassByHwModeTables[0][0], 1);
6381}
6382
6383} // namespace llvm
6384
6385#endif // GET_INSTRINFO_CTOR_DTOR
6386
6387#ifdef GET_INSTRINFO_OPERAND_ENUM
6388#undef GET_INSTRINFO_OPERAND_ENUM
6389
6390namespace llvm::WebAssembly {
6391
6392enum class OpName : uint8_t {
6393 dst = 0,
6394 p2align = 1,
6395 off = 2,
6396 addr = 3,
6397 val = 4,
6398 exp = 5,
6399 new_ = 6,
6400 idx = 7,
6401 vec = 8,
6402 count = 9,
6403 timeout = 10,
6404 NUM_OPERAND_NAMES = 11,
6405}; // enum class OpName
6406
6407LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, OpName Name);
6408LLVM_READONLY OpName getOperandIdxName(uint16_t Opcode, int16_t Idx);
6409
6410} // namespace llvm::WebAssembly
6411
6412#endif // GET_INSTRINFO_OPERAND_ENUM
6413
6414#ifdef GET_INSTRINFO_NAMED_OPS
6415#undef GET_INSTRINFO_NAMED_OPS
6416
6417namespace llvm::WebAssembly {
6418
6419LLVM_READONLY static uint8_t getInstructionIndexForOpLookup(uint16_t Opcode) {
6420 static constexpr uint8_t InstructionIndex[] = {
6421 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6422 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6423 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6424 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6425 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6426 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6427 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6428 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6429 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6430 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6431 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6432 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6433 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6434 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6435 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6436 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6437 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6438 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6439 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6440 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6441 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6442 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6443 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6444 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6445 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6446 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6447 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6448 0, 0, 0, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1,
6449 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 3,
6450 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 4,
6451 2, 4, 2, 4, 2, 4, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3,
6452 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3,
6453 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 4,
6454 2, 4, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3,
6455 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3,
6456 2, 3, 2, 4, 2, 4, 2, 4, 2, 4, 2, 3, 2, 3, 2, 3,
6457 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3,
6458 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3,
6459 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 4, 2, 4, 2, 4,
6460 2, 4, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3,
6461 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3,
6462 2, 3, 2, 5, 2, 5, 2, 5, 2, 5, 2, 5, 2, 5, 2, 5,
6463 2, 5, 2, 5, 2, 5, 2, 5, 2, 5, 2, 5, 2, 5, 2, 0,
6464 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6465 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6466 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6467 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6468 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6469 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6470 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6471 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6472 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6473 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6474 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6475 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6476 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6477 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6478 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6479 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6480 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6481 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6482 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6483 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6484 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6485 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6486 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6487 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6488 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6489 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6490 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6491 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6492 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6493 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 1, 2, 1,
6494 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1,
6495 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1,
6496 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1,
6497 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1,
6498 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1,
6499 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 6,
6500 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 1,
6501 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 0, 0, 0, 0, 0,
6502 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6503 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6504 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6505 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6506 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6507 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6508 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 8, 2, 8,
6509 2, 9, 2, 9, 2, 9, 2, 9, 2, 0, 0, 0, 0, 0, 0, 0,
6510 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6511 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6512 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6513 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6514 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6515 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6516 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6517 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6518 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6519 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6520 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6521 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6522 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6523 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6524 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6525 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6526 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6527 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6528 0, 0, 0, 0, 0, 0, 0, 5, 2, 5, 2, 5, 2, 5, 2, 5,
6529 2, 5, 2, 5, 2, 5, 2, 5, 2, 5, 2, 5, 2, 5, 2, 5,
6530 2, 5, 2, 5, 2, 5, 2, 5, 2, 5, 2, 5, 2, 5, 2, 10,
6531 7, 10, 7, 10, 7, 10, 7, 10, 7, 10, 7, 10, 7, 10, 7, 11,
6532 2, 11, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6533 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6534 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6535 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6536 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6537 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6538 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6539 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6540 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6541 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6542 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6543 0, 0, 0, 0, 0,
6544 };
6545 return InstructionIndex[Opcode];
6546}
6547LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, OpName Name) {
6548 assert(Name != OpName::NUM_OPERAND_NAMES);
6549 static constexpr int8_t OperandMap[][11] = {
6550 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
6551 {0, 1, 2, 3, -1, -1, -1, -1, -1, -1, -1, },
6552 {-1, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, },
6553 {0, 1, 2, 3, 4, -1, -1, -1, -1, -1, -1, },
6554 {0, 1, 2, 3, -1, 4, 5, -1, -1, -1, -1, },
6555 {-1, 0, 1, 2, 3, -1, -1, -1, -1, -1, -1, },
6556 {0, 1, 2, 4, -1, -1, -1, 3, 5, -1, -1, },
6557 {-1, 0, 1, -1, -1, -1, -1, 2, -1, -1, -1, },
6558 {0, 1, 2, 3, -1, -1, -1, -1, -1, 4, -1, },
6559 {0, 1, 2, 3, -1, 4, -1, -1, -1, -1, 5, },
6560 {-1, 0, 1, 3, -1, -1, -1, 2, 4, -1, -1, },
6561 {-1, 0, 1, 2, -1, -1, -1, -1, 3, -1, -1, },
6562 };
6563 unsigned InstrIdx = getInstructionIndexForOpLookup(Opcode);
6564 return OperandMap[InstrIdx][(unsigned)Name];
6565}
6566LLVM_READONLY OpName getOperandIdxName(uint16_t Opcode, int16_t Idx) {
6567 assert(Idx >= 0 && Idx < 6);
6568 static constexpr OpName OperandMap[][6] = {
6569 {OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
6570 {OpName::dst, OpName::p2align, OpName::off, OpName::addr, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
6571 {OpName::p2align, OpName::off, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
6572 {OpName::dst, OpName::p2align, OpName::off, OpName::addr, OpName::val, OpName::NUM_OPERAND_NAMES, },
6573 {OpName::dst, OpName::p2align, OpName::off, OpName::addr, OpName::exp, OpName::new_, },
6574 {OpName::p2align, OpName::off, OpName::addr, OpName::val, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
6575 {OpName::dst, OpName::p2align, OpName::off, OpName::idx, OpName::addr, OpName::vec, },
6576 {OpName::p2align, OpName::off, OpName::idx, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
6577 {OpName::dst, OpName::p2align, OpName::off, OpName::addr, OpName::count, OpName::NUM_OPERAND_NAMES, },
6578 {OpName::dst, OpName::p2align, OpName::off, OpName::addr, OpName::exp, OpName::timeout, },
6579 {OpName::p2align, OpName::off, OpName::idx, OpName::addr, OpName::vec, OpName::NUM_OPERAND_NAMES, },
6580 {OpName::p2align, OpName::off, OpName::addr, OpName::vec, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
6581 };
6582 unsigned InstrIdx = getInstructionIndexForOpLookup(Opcode);
6583 return OperandMap[InstrIdx][(unsigned)Idx];
6584}
6585
6586} // namespace llvm::WebAssembly
6587
6588#endif // GET_INSTRINFO_NAMED_OPS
6589
6590#ifdef GET_INSTRINFO_MC_HELPER_DECLS
6591#undef GET_INSTRINFO_MC_HELPER_DECLS
6592
6593namespace llvm {
6594
6595class MCInst;
6596class FeatureBitset;
6597
6598namespace WebAssembly_MC {
6599
6600void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
6601
6602} // namespace WebAssembly_MC
6603
6604} // namespace llvm
6605
6606#endif // GET_INSTRINFO_MC_HELPER_DECLS
6607
6608#ifdef GET_INSTRINFO_MC_HELPERS
6609#undef GET_INSTRINFO_MC_HELPERS
6610
6611namespace llvm::WebAssembly_MC {
6612
6613
6614} // namespace llvm::WebAssembly_MC
6615
6616#endif // GET_INSTRINFO_MC_HELPERS
6617
6618#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
6619 defined(GET_AVAILABLE_OPCODE_CHECKER)
6620#define GET_COMPUTE_FEATURES
6621#endif
6622#ifdef GET_COMPUTE_FEATURES
6623#undef GET_COMPUTE_FEATURES
6624
6625namespace llvm::WebAssembly_MC {
6626
6627// Bits for subtarget features that participate in instruction matching.
6628enum SubtargetFeatureBits : uint8_t {
6629 Feature_HasAtomicsBit = 0,
6630 Feature_HasBulkMemoryBit = 1,
6631 Feature_HasBulkMemoryOptBit = 2,
6632 Feature_HasCallIndirectOverlongBit = 3,
6633 Feature_HasExceptionHandlingBit = 4,
6634 Feature_HasExtendedConstBit = 5,
6635 Feature_HasFP16Bit = 6,
6636 Feature_HasGCBit = 7,
6637 Feature_HasMultiMemoryBit = 8,
6638 Feature_HasMultivalueBit = 9,
6639 Feature_HasMutableGlobalsBit = 10,
6640 Feature_HasNontrappingFPToIntBit = 11,
6641 Feature_NotHasNontrappingFPToIntBit = 18,
6642 Feature_HasReferenceTypesBit = 12,
6643 Feature_HasRelaxedSIMDBit = 13,
6644 Feature_HasSignExtBit = 15,
6645 Feature_HasSIMD128Bit = 14,
6646 Feature_HasTailCallBit = 16,
6647 Feature_HasWideArithmeticBit = 17,
6648};
6649
6650inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
6651 FeatureBitset Features;
6652 if (FB[WebAssembly::FeatureAtomics])
6653 Features.set(Feature_HasAtomicsBit);
6654 if (FB[WebAssembly::FeatureBulkMemory])
6655 Features.set(Feature_HasBulkMemoryBit);
6656 if (FB[WebAssembly::FeatureBulkMemoryOpt])
6657 Features.set(Feature_HasBulkMemoryOptBit);
6658 if (FB[WebAssembly::FeatureCallIndirectOverlong])
6659 Features.set(Feature_HasCallIndirectOverlongBit);
6660 if (FB[WebAssembly::FeatureExceptionHandling])
6661 Features.set(Feature_HasExceptionHandlingBit);
6662 if (FB[WebAssembly::FeatureExtendedConst])
6663 Features.set(Feature_HasExtendedConstBit);
6664 if (FB[WebAssembly::FeatureFP16])
6665 Features.set(Feature_HasFP16Bit);
6666 if (FB[WebAssembly::FeatureGC])
6667 Features.set(Feature_HasGCBit);
6668 if (FB[WebAssembly::FeatureMultiMemory])
6669 Features.set(Feature_HasMultiMemoryBit);
6670 if (FB[WebAssembly::FeatureMultivalue])
6671 Features.set(Feature_HasMultivalueBit);
6672 if (FB[WebAssembly::FeatureMutableGlobals])
6673 Features.set(Feature_HasMutableGlobalsBit);
6674 if (FB[WebAssembly::FeatureNontrappingFPToInt])
6675 Features.set(Feature_HasNontrappingFPToIntBit);
6676 if (!FB[WebAssembly::FeatureNontrappingFPToInt])
6677 Features.set(Feature_NotHasNontrappingFPToIntBit);
6678 if (FB[WebAssembly::FeatureReferenceTypes])
6679 Features.set(Feature_HasReferenceTypesBit);
6680 if (FB[WebAssembly::FeatureRelaxedSIMD])
6681 Features.set(Feature_HasRelaxedSIMDBit);
6682 if (FB[WebAssembly::FeatureSignExt])
6683 Features.set(Feature_HasSignExtBit);
6684 if (FB[WebAssembly::FeatureSIMD128] || FB[WebAssembly::FeatureRelaxedSIMD])
6685 Features.set(Feature_HasSIMD128Bit);
6686 if (FB[WebAssembly::FeatureTailCall])
6687 Features.set(Feature_HasTailCallBit);
6688 if (FB[WebAssembly::FeatureWideArithmetic])
6689 Features.set(Feature_HasWideArithmeticBit);
6690 return Features;
6691}
6692
6693inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
6694 enum : uint8_t {
6695 CEFBS_None,
6696 CEFBS_HasAtomics,
6697 CEFBS_HasBulkMemoryOpt,
6698 CEFBS_HasExceptionHandling,
6699 CEFBS_HasFP16,
6700 CEFBS_HasGC,
6701 CEFBS_HasNontrappingFPToInt,
6702 CEFBS_HasReferenceTypes,
6703 CEFBS_HasRelaxedSIMD,
6704 CEFBS_HasSIMD128,
6705 CEFBS_HasSignExt,
6706 CEFBS_HasTailCall,
6707 CEFBS_HasWideArithmetic,
6708 CEFBS_NotHasNontrappingFPToInt,
6709 CEFBS_HasReferenceTypes_HasExceptionHandling,
6710 CEFBS_HasSIMD128_HasFP16,
6711 CEFBS_HasSIMD128_HasRelaxedSIMD,
6712 };
6713
6714 static constexpr FeatureBitset FeatureBitsets[] = {
6715 {}, // CEFBS_None
6716 {Feature_HasAtomicsBit, },
6717 {Feature_HasBulkMemoryOptBit, },
6718 {Feature_HasExceptionHandlingBit, },
6719 {Feature_HasFP16Bit, },
6720 {Feature_HasGCBit, },
6721 {Feature_HasNontrappingFPToIntBit, },
6722 {Feature_HasReferenceTypesBit, },
6723 {Feature_HasRelaxedSIMDBit, },
6724 {Feature_HasSIMD128Bit, },
6725 {Feature_HasSignExtBit, },
6726 {Feature_HasTailCallBit, },
6727 {Feature_HasWideArithmeticBit, },
6728 {Feature_NotHasNontrappingFPToIntBit, },
6729 {Feature_HasReferenceTypesBit, Feature_HasExceptionHandlingBit, },
6730 {Feature_HasSIMD128Bit, Feature_HasFP16Bit, },
6731 {Feature_HasSIMD128Bit, Feature_HasRelaxedSIMDBit, },
6732 };
6733 static constexpr uint8_t RequiredFeaturesRefs[] = {
6734 CEFBS_None, // PHI
6735 CEFBS_None, // INLINEASM
6736 CEFBS_None, // INLINEASM_BR
6737 CEFBS_None, // CFI_INSTRUCTION
6738 CEFBS_None, // EH_LABEL
6739 CEFBS_None, // GC_LABEL
6740 CEFBS_None, // ANNOTATION_LABEL
6741 CEFBS_None, // KILL
6742 CEFBS_None, // EXTRACT_SUBREG
6743 CEFBS_None, // INSERT_SUBREG
6744 CEFBS_None, // IMPLICIT_DEF
6745 CEFBS_None, // INIT_UNDEF
6746 CEFBS_None, // SUBREG_TO_REG
6747 CEFBS_None, // COPY_TO_REGCLASS
6748 CEFBS_None, // DBG_VALUE
6749 CEFBS_None, // DBG_VALUE_LIST
6750 CEFBS_None, // DBG_INSTR_REF
6751 CEFBS_None, // DBG_PHI
6752 CEFBS_None, // DBG_LABEL
6753 CEFBS_None, // REG_SEQUENCE
6754 CEFBS_None, // COPY
6755 CEFBS_None, // COPY_LANEMASK
6756 CEFBS_None, // BUNDLE
6757 CEFBS_None, // LIFETIME_START
6758 CEFBS_None, // LIFETIME_END
6759 CEFBS_None, // PSEUDO_PROBE
6760 CEFBS_None, // ARITH_FENCE
6761 CEFBS_None, // STACKMAP
6762 CEFBS_None, // FENTRY_CALL
6763 CEFBS_None, // PATCHPOINT
6764 CEFBS_None, // LOAD_STACK_GUARD
6765 CEFBS_None, // PREALLOCATED_SETUP
6766 CEFBS_None, // PREALLOCATED_ARG
6767 CEFBS_None, // STATEPOINT
6768 CEFBS_None, // LOCAL_ESCAPE
6769 CEFBS_None, // FAULTING_OP
6770 CEFBS_None, // PATCHABLE_OP
6771 CEFBS_None, // PATCHABLE_FUNCTION_ENTER
6772 CEFBS_None, // PATCHABLE_RET
6773 CEFBS_None, // PATCHABLE_FUNCTION_EXIT
6774 CEFBS_None, // PATCHABLE_TAIL_CALL
6775 CEFBS_None, // PATCHABLE_EVENT_CALL
6776 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL
6777 CEFBS_None, // ICALL_BRANCH_FUNNEL
6778 CEFBS_None, // FAKE_USE
6779 CEFBS_None, // MEMBARRIER
6780 CEFBS_None, // JUMP_TABLE_DEBUG_INFO
6781 CEFBS_None, // RELOC_NONE
6782 CEFBS_None, // CONVERGENCECTRL_ENTRY
6783 CEFBS_None, // CONVERGENCECTRL_ANCHOR
6784 CEFBS_None, // CONVERGENCECTRL_LOOP
6785 CEFBS_None, // CONVERGENCECTRL_GLUE
6786 CEFBS_None, // G_ASSERT_SEXT
6787 CEFBS_None, // G_ASSERT_ZEXT
6788 CEFBS_None, // G_ASSERT_ALIGN
6789 CEFBS_None, // G_ADD
6790 CEFBS_None, // G_SUB
6791 CEFBS_None, // G_MUL
6792 CEFBS_None, // G_SDIV
6793 CEFBS_None, // G_UDIV
6794 CEFBS_None, // G_SREM
6795 CEFBS_None, // G_UREM
6796 CEFBS_None, // G_SDIVREM
6797 CEFBS_None, // G_UDIVREM
6798 CEFBS_None, // G_AND
6799 CEFBS_None, // G_OR
6800 CEFBS_None, // G_XOR
6801 CEFBS_None, // G_ABDS
6802 CEFBS_None, // G_ABDU
6803 CEFBS_None, // G_UAVGFLOOR
6804 CEFBS_None, // G_UAVGCEIL
6805 CEFBS_None, // G_SAVGFLOOR
6806 CEFBS_None, // G_SAVGCEIL
6807 CEFBS_None, // G_IMPLICIT_DEF
6808 CEFBS_None, // G_PHI
6809 CEFBS_None, // G_FRAME_INDEX
6810 CEFBS_None, // G_GLOBAL_VALUE
6811 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE
6812 CEFBS_None, // G_CONSTANT_POOL
6813 CEFBS_None, // G_EXTRACT
6814 CEFBS_None, // G_UNMERGE_VALUES
6815 CEFBS_None, // G_INSERT
6816 CEFBS_None, // G_MERGE_VALUES
6817 CEFBS_None, // G_BUILD_VECTOR
6818 CEFBS_None, // G_BUILD_VECTOR_TRUNC
6819 CEFBS_None, // G_CONCAT_VECTORS
6820 CEFBS_None, // G_PTRTOINT
6821 CEFBS_None, // G_INTTOPTR
6822 CEFBS_None, // G_BITCAST
6823 CEFBS_None, // G_FREEZE
6824 CEFBS_None, // G_CONSTANT_FOLD_BARRIER
6825 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND
6826 CEFBS_None, // G_INTRINSIC_TRUNC
6827 CEFBS_None, // G_INTRINSIC_ROUND
6828 CEFBS_None, // G_INTRINSIC_LRINT
6829 CEFBS_None, // G_INTRINSIC_LLRINT
6830 CEFBS_None, // G_INTRINSIC_ROUNDEVEN
6831 CEFBS_None, // G_READCYCLECOUNTER
6832 CEFBS_None, // G_READSTEADYCOUNTER
6833 CEFBS_None, // G_LOAD
6834 CEFBS_None, // G_SEXTLOAD
6835 CEFBS_None, // G_ZEXTLOAD
6836 CEFBS_None, // G_INDEXED_LOAD
6837 CEFBS_None, // G_INDEXED_SEXTLOAD
6838 CEFBS_None, // G_INDEXED_ZEXTLOAD
6839 CEFBS_None, // G_STORE
6840 CEFBS_None, // G_INDEXED_STORE
6841 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
6842 CEFBS_None, // G_ATOMIC_CMPXCHG
6843 CEFBS_None, // G_ATOMICRMW_XCHG
6844 CEFBS_None, // G_ATOMICRMW_ADD
6845 CEFBS_None, // G_ATOMICRMW_SUB
6846 CEFBS_None, // G_ATOMICRMW_AND
6847 CEFBS_None, // G_ATOMICRMW_NAND
6848 CEFBS_None, // G_ATOMICRMW_OR
6849 CEFBS_None, // G_ATOMICRMW_XOR
6850 CEFBS_None, // G_ATOMICRMW_MAX
6851 CEFBS_None, // G_ATOMICRMW_MIN
6852 CEFBS_None, // G_ATOMICRMW_UMAX
6853 CEFBS_None, // G_ATOMICRMW_UMIN
6854 CEFBS_None, // G_ATOMICRMW_FADD
6855 CEFBS_None, // G_ATOMICRMW_FSUB
6856 CEFBS_None, // G_ATOMICRMW_FMAX
6857 CEFBS_None, // G_ATOMICRMW_FMIN
6858 CEFBS_None, // G_ATOMICRMW_FMAXIMUM
6859 CEFBS_None, // G_ATOMICRMW_FMINIMUM
6860 CEFBS_None, // G_ATOMICRMW_UINC_WRAP
6861 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP
6862 CEFBS_None, // G_ATOMICRMW_USUB_COND
6863 CEFBS_None, // G_ATOMICRMW_USUB_SAT
6864 CEFBS_None, // G_FENCE
6865 CEFBS_None, // G_PREFETCH
6866 CEFBS_None, // G_BRCOND
6867 CEFBS_None, // G_BRINDIRECT
6868 CEFBS_None, // G_INVOKE_REGION_START
6869 CEFBS_None, // G_INTRINSIC
6870 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS
6871 CEFBS_None, // G_INTRINSIC_CONVERGENT
6872 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
6873 CEFBS_None, // G_ANYEXT
6874 CEFBS_None, // G_TRUNC
6875 CEFBS_None, // G_TRUNC_SSAT_S
6876 CEFBS_None, // G_TRUNC_SSAT_U
6877 CEFBS_None, // G_TRUNC_USAT_U
6878 CEFBS_None, // G_CONSTANT
6879 CEFBS_None, // G_FCONSTANT
6880 CEFBS_None, // G_VASTART
6881 CEFBS_None, // G_VAARG
6882 CEFBS_None, // G_SEXT
6883 CEFBS_None, // G_SEXT_INREG
6884 CEFBS_None, // G_ZEXT
6885 CEFBS_None, // G_SHL
6886 CEFBS_None, // G_LSHR
6887 CEFBS_None, // G_ASHR
6888 CEFBS_None, // G_FSHL
6889 CEFBS_None, // G_FSHR
6890 CEFBS_None, // G_ROTR
6891 CEFBS_None, // G_ROTL
6892 CEFBS_None, // G_ICMP
6893 CEFBS_None, // G_FCMP
6894 CEFBS_None, // G_SCMP
6895 CEFBS_None, // G_UCMP
6896 CEFBS_None, // G_SELECT
6897 CEFBS_None, // G_UADDO
6898 CEFBS_None, // G_UADDE
6899 CEFBS_None, // G_USUBO
6900 CEFBS_None, // G_USUBE
6901 CEFBS_None, // G_SADDO
6902 CEFBS_None, // G_SADDE
6903 CEFBS_None, // G_SSUBO
6904 CEFBS_None, // G_SSUBE
6905 CEFBS_None, // G_UMULO
6906 CEFBS_None, // G_SMULO
6907 CEFBS_None, // G_UMULH
6908 CEFBS_None, // G_SMULH
6909 CEFBS_None, // G_UADDSAT
6910 CEFBS_None, // G_SADDSAT
6911 CEFBS_None, // G_USUBSAT
6912 CEFBS_None, // G_SSUBSAT
6913 CEFBS_None, // G_USHLSAT
6914 CEFBS_None, // G_SSHLSAT
6915 CEFBS_None, // G_SMULFIX
6916 CEFBS_None, // G_UMULFIX
6917 CEFBS_None, // G_SMULFIXSAT
6918 CEFBS_None, // G_UMULFIXSAT
6919 CEFBS_None, // G_SDIVFIX
6920 CEFBS_None, // G_UDIVFIX
6921 CEFBS_None, // G_SDIVFIXSAT
6922 CEFBS_None, // G_UDIVFIXSAT
6923 CEFBS_None, // G_FADD
6924 CEFBS_None, // G_FSUB
6925 CEFBS_None, // G_FMUL
6926 CEFBS_None, // G_FMA
6927 CEFBS_None, // G_FMAD
6928 CEFBS_None, // G_FDIV
6929 CEFBS_None, // G_FREM
6930 CEFBS_None, // G_FMODF
6931 CEFBS_None, // G_FPOW
6932 CEFBS_None, // G_FPOWI
6933 CEFBS_None, // G_FEXP
6934 CEFBS_None, // G_FEXP2
6935 CEFBS_None, // G_FEXP10
6936 CEFBS_None, // G_FLOG
6937 CEFBS_None, // G_FLOG2
6938 CEFBS_None, // G_FLOG10
6939 CEFBS_None, // G_FLDEXP
6940 CEFBS_None, // G_FFREXP
6941 CEFBS_None, // G_FNEG
6942 CEFBS_None, // G_FPEXT
6943 CEFBS_None, // G_FPTRUNC
6944 CEFBS_None, // G_FPTOSI
6945 CEFBS_None, // G_FPTOUI
6946 CEFBS_None, // G_SITOFP
6947 CEFBS_None, // G_UITOFP
6948 CEFBS_None, // G_FPTOSI_SAT
6949 CEFBS_None, // G_FPTOUI_SAT
6950 CEFBS_None, // G_FABS
6951 CEFBS_None, // G_FCOPYSIGN
6952 CEFBS_None, // G_IS_FPCLASS
6953 CEFBS_None, // G_FCANONICALIZE
6954 CEFBS_None, // G_FMINNUM
6955 CEFBS_None, // G_FMAXNUM
6956 CEFBS_None, // G_FMINNUM_IEEE
6957 CEFBS_None, // G_FMAXNUM_IEEE
6958 CEFBS_None, // G_FMINIMUM
6959 CEFBS_None, // G_FMAXIMUM
6960 CEFBS_None, // G_FMINIMUMNUM
6961 CEFBS_None, // G_FMAXIMUMNUM
6962 CEFBS_None, // G_GET_FPENV
6963 CEFBS_None, // G_SET_FPENV
6964 CEFBS_None, // G_RESET_FPENV
6965 CEFBS_None, // G_GET_FPMODE
6966 CEFBS_None, // G_SET_FPMODE
6967 CEFBS_None, // G_RESET_FPMODE
6968 CEFBS_None, // G_GET_ROUNDING
6969 CEFBS_None, // G_SET_ROUNDING
6970 CEFBS_None, // G_PTR_ADD
6971 CEFBS_None, // G_PTRMASK
6972 CEFBS_None, // G_SMIN
6973 CEFBS_None, // G_SMAX
6974 CEFBS_None, // G_UMIN
6975 CEFBS_None, // G_UMAX
6976 CEFBS_None, // G_ABS
6977 CEFBS_None, // G_LROUND
6978 CEFBS_None, // G_LLROUND
6979 CEFBS_None, // G_BR
6980 CEFBS_None, // G_BRJT
6981 CEFBS_None, // G_VSCALE
6982 CEFBS_None, // G_INSERT_SUBVECTOR
6983 CEFBS_None, // G_EXTRACT_SUBVECTOR
6984 CEFBS_None, // G_INSERT_VECTOR_ELT
6985 CEFBS_None, // G_EXTRACT_VECTOR_ELT
6986 CEFBS_None, // G_SHUFFLE_VECTOR
6987 CEFBS_None, // G_SPLAT_VECTOR
6988 CEFBS_None, // G_STEP_VECTOR
6989 CEFBS_None, // G_VECTOR_COMPRESS
6990 CEFBS_None, // G_CTTZ
6991 CEFBS_None, // G_CTTZ_ZERO_UNDEF
6992 CEFBS_None, // G_CTLZ
6993 CEFBS_None, // G_CTLZ_ZERO_UNDEF
6994 CEFBS_None, // G_CTLS
6995 CEFBS_None, // G_CTPOP
6996 CEFBS_None, // G_BSWAP
6997 CEFBS_None, // G_BITREVERSE
6998 CEFBS_None, // G_FCEIL
6999 CEFBS_None, // G_FCOS
7000 CEFBS_None, // G_FSIN
7001 CEFBS_None, // G_FSINCOS
7002 CEFBS_None, // G_FTAN
7003 CEFBS_None, // G_FACOS
7004 CEFBS_None, // G_FASIN
7005 CEFBS_None, // G_FATAN
7006 CEFBS_None, // G_FATAN2
7007 CEFBS_None, // G_FCOSH
7008 CEFBS_None, // G_FSINH
7009 CEFBS_None, // G_FTANH
7010 CEFBS_None, // G_FSQRT
7011 CEFBS_None, // G_FFLOOR
7012 CEFBS_None, // G_FRINT
7013 CEFBS_None, // G_FNEARBYINT
7014 CEFBS_None, // G_ADDRSPACE_CAST
7015 CEFBS_None, // G_BLOCK_ADDR
7016 CEFBS_None, // G_JUMP_TABLE
7017 CEFBS_None, // G_DYN_STACKALLOC
7018 CEFBS_None, // G_STACKSAVE
7019 CEFBS_None, // G_STACKRESTORE
7020 CEFBS_None, // G_STRICT_FADD
7021 CEFBS_None, // G_STRICT_FSUB
7022 CEFBS_None, // G_STRICT_FMUL
7023 CEFBS_None, // G_STRICT_FDIV
7024 CEFBS_None, // G_STRICT_FREM
7025 CEFBS_None, // G_STRICT_FMA
7026 CEFBS_None, // G_STRICT_FSQRT
7027 CEFBS_None, // G_STRICT_FLDEXP
7028 CEFBS_None, // G_READ_REGISTER
7029 CEFBS_None, // G_WRITE_REGISTER
7030 CEFBS_None, // G_MEMCPY
7031 CEFBS_None, // G_MEMCPY_INLINE
7032 CEFBS_None, // G_MEMMOVE
7033 CEFBS_None, // G_MEMSET
7034 CEFBS_None, // G_BZERO
7035 CEFBS_None, // G_TRAP
7036 CEFBS_None, // G_DEBUGTRAP
7037 CEFBS_None, // G_UBSANTRAP
7038 CEFBS_None, // G_VECREDUCE_SEQ_FADD
7039 CEFBS_None, // G_VECREDUCE_SEQ_FMUL
7040 CEFBS_None, // G_VECREDUCE_FADD
7041 CEFBS_None, // G_VECREDUCE_FMUL
7042 CEFBS_None, // G_VECREDUCE_FMAX
7043 CEFBS_None, // G_VECREDUCE_FMIN
7044 CEFBS_None, // G_VECREDUCE_FMAXIMUM
7045 CEFBS_None, // G_VECREDUCE_FMINIMUM
7046 CEFBS_None, // G_VECREDUCE_ADD
7047 CEFBS_None, // G_VECREDUCE_MUL
7048 CEFBS_None, // G_VECREDUCE_AND
7049 CEFBS_None, // G_VECREDUCE_OR
7050 CEFBS_None, // G_VECREDUCE_XOR
7051 CEFBS_None, // G_VECREDUCE_SMAX
7052 CEFBS_None, // G_VECREDUCE_SMIN
7053 CEFBS_None, // G_VECREDUCE_UMAX
7054 CEFBS_None, // G_VECREDUCE_UMIN
7055 CEFBS_None, // G_SBFX
7056 CEFBS_None, // G_UBFX
7057 CEFBS_None, // CALL_PARAMS
7058 CEFBS_None, // CALL_PARAMS_S
7059 CEFBS_None, // CALL_RESULTS
7060 CEFBS_None, // CALL_RESULTS_S
7061 CEFBS_HasExceptionHandling, // CATCHRET
7062 CEFBS_HasExceptionHandling, // CATCHRET_S
7063 CEFBS_HasExceptionHandling, // CLEANUPRET
7064 CEFBS_HasExceptionHandling, // CLEANUPRET_S
7065 CEFBS_HasAtomics, // COMPILER_FENCE
7066 CEFBS_HasAtomics, // COMPILER_FENCE_S
7067 CEFBS_None, // RET_CALL_RESULTS
7068 CEFBS_None, // RET_CALL_RESULTS_S
7069 CEFBS_HasSIMD128_HasFP16, // ABS_F16x8
7070 CEFBS_HasSIMD128_HasFP16, // ABS_F16x8_S
7071 CEFBS_None, // ABS_F32
7072 CEFBS_None, // ABS_F32_S
7073 CEFBS_HasSIMD128, // ABS_F32x4
7074 CEFBS_HasSIMD128, // ABS_F32x4_S
7075 CEFBS_None, // ABS_F64
7076 CEFBS_None, // ABS_F64_S
7077 CEFBS_HasSIMD128, // ABS_F64x2
7078 CEFBS_HasSIMD128, // ABS_F64x2_S
7079 CEFBS_HasSIMD128, // ABS_I16x8
7080 CEFBS_HasSIMD128, // ABS_I16x8_S
7081 CEFBS_HasSIMD128, // ABS_I32x4
7082 CEFBS_HasSIMD128, // ABS_I32x4_S
7083 CEFBS_HasSIMD128, // ABS_I64x2
7084 CEFBS_HasSIMD128, // ABS_I64x2_S
7085 CEFBS_HasSIMD128, // ABS_I8x16
7086 CEFBS_HasSIMD128, // ABS_I8x16_S
7087 CEFBS_HasSIMD128_HasFP16, // ADD_F16x8
7088 CEFBS_HasSIMD128_HasFP16, // ADD_F16x8_S
7089 CEFBS_None, // ADD_F32
7090 CEFBS_None, // ADD_F32_S
7091 CEFBS_HasSIMD128, // ADD_F32x4
7092 CEFBS_HasSIMD128, // ADD_F32x4_S
7093 CEFBS_None, // ADD_F64
7094 CEFBS_None, // ADD_F64_S
7095 CEFBS_HasSIMD128, // ADD_F64x2
7096 CEFBS_HasSIMD128, // ADD_F64x2_S
7097 CEFBS_HasSIMD128, // ADD_I16x8
7098 CEFBS_HasSIMD128, // ADD_I16x8_S
7099 CEFBS_None, // ADD_I32
7100 CEFBS_None, // ADD_I32_S
7101 CEFBS_HasSIMD128, // ADD_I32x4
7102 CEFBS_HasSIMD128, // ADD_I32x4_S
7103 CEFBS_None, // ADD_I64
7104 CEFBS_None, // ADD_I64_S
7105 CEFBS_HasSIMD128, // ADD_I64x2
7106 CEFBS_HasSIMD128, // ADD_I64x2_S
7107 CEFBS_HasSIMD128, // ADD_I8x16
7108 CEFBS_HasSIMD128, // ADD_I8x16_S
7109 CEFBS_HasSIMD128, // ADD_SAT_S_I16x8
7110 CEFBS_HasSIMD128, // ADD_SAT_S_I16x8_S
7111 CEFBS_HasSIMD128, // ADD_SAT_S_I8x16
7112 CEFBS_HasSIMD128, // ADD_SAT_S_I8x16_S
7113 CEFBS_HasSIMD128, // ADD_SAT_U_I16x8
7114 CEFBS_HasSIMD128, // ADD_SAT_U_I16x8_S
7115 CEFBS_HasSIMD128, // ADD_SAT_U_I8x16
7116 CEFBS_HasSIMD128, // ADD_SAT_U_I8x16_S
7117 CEFBS_None, // ADJCALLSTACKDOWN
7118 CEFBS_None, // ADJCALLSTACKDOWN_S
7119 CEFBS_None, // ADJCALLSTACKUP
7120 CEFBS_None, // ADJCALLSTACKUP_S
7121 CEFBS_HasSIMD128, // ALLTRUE_I16x8
7122 CEFBS_HasSIMD128, // ALLTRUE_I16x8_S
7123 CEFBS_HasSIMD128, // ALLTRUE_I32x4
7124 CEFBS_HasSIMD128, // ALLTRUE_I32x4_S
7125 CEFBS_HasSIMD128, // ALLTRUE_I64x2
7126 CEFBS_HasSIMD128, // ALLTRUE_I64x2_S
7127 CEFBS_HasSIMD128, // ALLTRUE_I8x16
7128 CEFBS_HasSIMD128, // ALLTRUE_I8x16_S
7129 CEFBS_HasSIMD128, // AND
7130 CEFBS_HasSIMD128, // ANDNOT
7131 CEFBS_HasSIMD128, // ANDNOT_S
7132 CEFBS_None, // AND_I32
7133 CEFBS_None, // AND_I32_S
7134 CEFBS_None, // AND_I64
7135 CEFBS_None, // AND_I64_S
7136 CEFBS_HasSIMD128, // AND_S
7137 CEFBS_HasSIMD128, // ANYTRUE
7138 CEFBS_HasSIMD128, // ANYTRUE_S
7139 CEFBS_None, // ARGUMENT_exnref
7140 CEFBS_None, // ARGUMENT_exnref_S
7141 CEFBS_None, // ARGUMENT_externref
7142 CEFBS_None, // ARGUMENT_externref_S
7143 CEFBS_None, // ARGUMENT_f32
7144 CEFBS_None, // ARGUMENT_f32_S
7145 CEFBS_None, // ARGUMENT_f64
7146 CEFBS_None, // ARGUMENT_f64_S
7147 CEFBS_None, // ARGUMENT_funcref
7148 CEFBS_None, // ARGUMENT_funcref_S
7149 CEFBS_None, // ARGUMENT_i32
7150 CEFBS_None, // ARGUMENT_i32_S
7151 CEFBS_None, // ARGUMENT_i64
7152 CEFBS_None, // ARGUMENT_i64_S
7153 CEFBS_None, // ARGUMENT_v16i8
7154 CEFBS_None, // ARGUMENT_v16i8_S
7155 CEFBS_None, // ARGUMENT_v2f64
7156 CEFBS_None, // ARGUMENT_v2f64_S
7157 CEFBS_None, // ARGUMENT_v2i64
7158 CEFBS_None, // ARGUMENT_v2i64_S
7159 CEFBS_None, // ARGUMENT_v4f32
7160 CEFBS_None, // ARGUMENT_v4f32_S
7161 CEFBS_None, // ARGUMENT_v4i32
7162 CEFBS_None, // ARGUMENT_v4i32_S
7163 CEFBS_None, // ARGUMENT_v8f16
7164 CEFBS_None, // ARGUMENT_v8f16_S
7165 CEFBS_None, // ARGUMENT_v8i16
7166 CEFBS_None, // ARGUMENT_v8i16_S
7167 CEFBS_HasAtomics, // ATOMIC_FENCE
7168 CEFBS_HasAtomics, // ATOMIC_FENCE_S
7169 CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I32_A32
7170 CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I32_A32_S
7171 CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I32_A64
7172 CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I32_A64_S
7173 CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I64_A32
7174 CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I64_A32_S
7175 CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I64_A64
7176 CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I64_A64_S
7177 CEFBS_HasAtomics, // ATOMIC_LOAD32_U_I64_A32
7178 CEFBS_HasAtomics, // ATOMIC_LOAD32_U_I64_A32_S
7179 CEFBS_HasAtomics, // ATOMIC_LOAD32_U_I64_A64
7180 CEFBS_HasAtomics, // ATOMIC_LOAD32_U_I64_A64_S
7181 CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I32_A32
7182 CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I32_A32_S
7183 CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I32_A64
7184 CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I32_A64_S
7185 CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I64_A32
7186 CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I64_A32_S
7187 CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I64_A64
7188 CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I64_A64_S
7189 CEFBS_HasAtomics, // ATOMIC_LOAD_I32_A32
7190 CEFBS_HasAtomics, // ATOMIC_LOAD_I32_A32_S
7191 CEFBS_HasAtomics, // ATOMIC_LOAD_I32_A64
7192 CEFBS_HasAtomics, // ATOMIC_LOAD_I32_A64_S
7193 CEFBS_HasAtomics, // ATOMIC_LOAD_I64_A32
7194 CEFBS_HasAtomics, // ATOMIC_LOAD_I64_A32_S
7195 CEFBS_HasAtomics, // ATOMIC_LOAD_I64_A64
7196 CEFBS_HasAtomics, // ATOMIC_LOAD_I64_A64_S
7197 CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I32_A32
7198 CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I32_A32_S
7199 CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I32_A64
7200 CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I32_A64_S
7201 CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I64_A32
7202 CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I64_A32_S
7203 CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I64_A64
7204 CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I64_A64_S
7205 CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I32_A32
7206 CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I32_A32_S
7207 CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I32_A64
7208 CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I32_A64_S
7209 CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I64_A32
7210 CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I64_A32_S
7211 CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I64_A64
7212 CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I64_A64_S
7213 CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I32_A32
7214 CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I32_A32_S
7215 CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I32_A64
7216 CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I32_A64_S
7217 CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I64_A32
7218 CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I64_A32_S
7219 CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I64_A64
7220 CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I64_A64_S
7221 CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I32_A32
7222 CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I32_A32_S
7223 CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I32_A64
7224 CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I32_A64_S
7225 CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I64_A32
7226 CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I64_A32_S
7227 CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I64_A64
7228 CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I64_A64_S
7229 CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I32_A32
7230 CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I32_A32_S
7231 CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I32_A64
7232 CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I32_A64_S
7233 CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I64_A32
7234 CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I64_A32_S
7235 CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I64_A64
7236 CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I64_A64_S
7237 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I32_A32
7238 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I32_A32_S
7239 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I32_A64
7240 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I32_A64_S
7241 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I64_A32
7242 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I64_A32_S
7243 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I64_A64
7244 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I64_A64_S
7245 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I32_A32
7246 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I32_A32_S
7247 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I32_A64
7248 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I32_A64_S
7249 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I64_A32
7250 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I64_A32_S
7251 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I64_A64
7252 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I64_A64_S
7253 CEFBS_HasAtomics, // ATOMIC_RMW32_U_ADD_I64_A32
7254 CEFBS_HasAtomics, // ATOMIC_RMW32_U_ADD_I64_A32_S
7255 CEFBS_HasAtomics, // ATOMIC_RMW32_U_ADD_I64_A64
7256 CEFBS_HasAtomics, // ATOMIC_RMW32_U_ADD_I64_A64_S
7257 CEFBS_HasAtomics, // ATOMIC_RMW32_U_AND_I64_A32
7258 CEFBS_HasAtomics, // ATOMIC_RMW32_U_AND_I64_A32_S
7259 CEFBS_HasAtomics, // ATOMIC_RMW32_U_AND_I64_A64
7260 CEFBS_HasAtomics, // ATOMIC_RMW32_U_AND_I64_A64_S
7261 CEFBS_HasAtomics, // ATOMIC_RMW32_U_CMPXCHG_I64_A32
7262 CEFBS_HasAtomics, // ATOMIC_RMW32_U_CMPXCHG_I64_A32_S
7263 CEFBS_HasAtomics, // ATOMIC_RMW32_U_CMPXCHG_I64_A64
7264 CEFBS_HasAtomics, // ATOMIC_RMW32_U_CMPXCHG_I64_A64_S
7265 CEFBS_HasAtomics, // ATOMIC_RMW32_U_OR_I64_A32
7266 CEFBS_HasAtomics, // ATOMIC_RMW32_U_OR_I64_A32_S
7267 CEFBS_HasAtomics, // ATOMIC_RMW32_U_OR_I64_A64
7268 CEFBS_HasAtomics, // ATOMIC_RMW32_U_OR_I64_A64_S
7269 CEFBS_HasAtomics, // ATOMIC_RMW32_U_SUB_I64_A32
7270 CEFBS_HasAtomics, // ATOMIC_RMW32_U_SUB_I64_A32_S
7271 CEFBS_HasAtomics, // ATOMIC_RMW32_U_SUB_I64_A64
7272 CEFBS_HasAtomics, // ATOMIC_RMW32_U_SUB_I64_A64_S
7273 CEFBS_HasAtomics, // ATOMIC_RMW32_U_XCHG_I64_A32
7274 CEFBS_HasAtomics, // ATOMIC_RMW32_U_XCHG_I64_A32_S
7275 CEFBS_HasAtomics, // ATOMIC_RMW32_U_XCHG_I64_A64
7276 CEFBS_HasAtomics, // ATOMIC_RMW32_U_XCHG_I64_A64_S
7277 CEFBS_HasAtomics, // ATOMIC_RMW32_U_XOR_I64_A32
7278 CEFBS_HasAtomics, // ATOMIC_RMW32_U_XOR_I64_A32_S
7279 CEFBS_HasAtomics, // ATOMIC_RMW32_U_XOR_I64_A64
7280 CEFBS_HasAtomics, // ATOMIC_RMW32_U_XOR_I64_A64_S
7281 CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I32_A32
7282 CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I32_A32_S
7283 CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I32_A64
7284 CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I32_A64_S
7285 CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I64_A32
7286 CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I64_A32_S
7287 CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I64_A64
7288 CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I64_A64_S
7289 CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I32_A32
7290 CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I32_A32_S
7291 CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I32_A64
7292 CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I32_A64_S
7293 CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I64_A32
7294 CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I64_A32_S
7295 CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I64_A64
7296 CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I64_A64_S
7297 CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I32_A32
7298 CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I32_A32_S
7299 CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I32_A64
7300 CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I32_A64_S
7301 CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I64_A32
7302 CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I64_A32_S
7303 CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I64_A64
7304 CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I64_A64_S
7305 CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I32_A32
7306 CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I32_A32_S
7307 CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I32_A64
7308 CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I32_A64_S
7309 CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I64_A32
7310 CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I64_A32_S
7311 CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I64_A64
7312 CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I64_A64_S
7313 CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I32_A32
7314 CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I32_A32_S
7315 CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I32_A64
7316 CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I32_A64_S
7317 CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I64_A32
7318 CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I64_A32_S
7319 CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I64_A64
7320 CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I64_A64_S
7321 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I32_A32
7322 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I32_A32_S
7323 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I32_A64
7324 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I32_A64_S
7325 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I64_A32
7326 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I64_A32_S
7327 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I64_A64
7328 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I64_A64_S
7329 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I32_A32
7330 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I32_A32_S
7331 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I32_A64
7332 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I32_A64_S
7333 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I64_A32
7334 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I64_A32_S
7335 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I64_A64
7336 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I64_A64_S
7337 CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I32_A32
7338 CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I32_A32_S
7339 CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I32_A64
7340 CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I32_A64_S
7341 CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I64_A32
7342 CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I64_A32_S
7343 CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I64_A64
7344 CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I64_A64_S
7345 CEFBS_HasAtomics, // ATOMIC_RMW_AND_I32_A32
7346 CEFBS_HasAtomics, // ATOMIC_RMW_AND_I32_A32_S
7347 CEFBS_HasAtomics, // ATOMIC_RMW_AND_I32_A64
7348 CEFBS_HasAtomics, // ATOMIC_RMW_AND_I32_A64_S
7349 CEFBS_HasAtomics, // ATOMIC_RMW_AND_I64_A32
7350 CEFBS_HasAtomics, // ATOMIC_RMW_AND_I64_A32_S
7351 CEFBS_HasAtomics, // ATOMIC_RMW_AND_I64_A64
7352 CEFBS_HasAtomics, // ATOMIC_RMW_AND_I64_A64_S
7353 CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I32_A32
7354 CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I32_A32_S
7355 CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I32_A64
7356 CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I32_A64_S
7357 CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I64_A32
7358 CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I64_A32_S
7359 CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I64_A64
7360 CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I64_A64_S
7361 CEFBS_HasAtomics, // ATOMIC_RMW_OR_I32_A32
7362 CEFBS_HasAtomics, // ATOMIC_RMW_OR_I32_A32_S
7363 CEFBS_HasAtomics, // ATOMIC_RMW_OR_I32_A64
7364 CEFBS_HasAtomics, // ATOMIC_RMW_OR_I32_A64_S
7365 CEFBS_HasAtomics, // ATOMIC_RMW_OR_I64_A32
7366 CEFBS_HasAtomics, // ATOMIC_RMW_OR_I64_A32_S
7367 CEFBS_HasAtomics, // ATOMIC_RMW_OR_I64_A64
7368 CEFBS_HasAtomics, // ATOMIC_RMW_OR_I64_A64_S
7369 CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I32_A32
7370 CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I32_A32_S
7371 CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I32_A64
7372 CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I32_A64_S
7373 CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I64_A32
7374 CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I64_A32_S
7375 CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I64_A64
7376 CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I64_A64_S
7377 CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I32_A32
7378 CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I32_A32_S
7379 CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I32_A64
7380 CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I32_A64_S
7381 CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I64_A32
7382 CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I64_A32_S
7383 CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I64_A64
7384 CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I64_A64_S
7385 CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I32_A32
7386 CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I32_A32_S
7387 CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I32_A64
7388 CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I32_A64_S
7389 CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I64_A32
7390 CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I64_A32_S
7391 CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I64_A64
7392 CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I64_A64_S
7393 CEFBS_HasAtomics, // ATOMIC_STORE16_I32_A32
7394 CEFBS_HasAtomics, // ATOMIC_STORE16_I32_A32_S
7395 CEFBS_HasAtomics, // ATOMIC_STORE16_I32_A64
7396 CEFBS_HasAtomics, // ATOMIC_STORE16_I32_A64_S
7397 CEFBS_HasAtomics, // ATOMIC_STORE16_I64_A32
7398 CEFBS_HasAtomics, // ATOMIC_STORE16_I64_A32_S
7399 CEFBS_HasAtomics, // ATOMIC_STORE16_I64_A64
7400 CEFBS_HasAtomics, // ATOMIC_STORE16_I64_A64_S
7401 CEFBS_HasAtomics, // ATOMIC_STORE32_I64_A32
7402 CEFBS_HasAtomics, // ATOMIC_STORE32_I64_A32_S
7403 CEFBS_HasAtomics, // ATOMIC_STORE32_I64_A64
7404 CEFBS_HasAtomics, // ATOMIC_STORE32_I64_A64_S
7405 CEFBS_HasAtomics, // ATOMIC_STORE8_I32_A32
7406 CEFBS_HasAtomics, // ATOMIC_STORE8_I32_A32_S
7407 CEFBS_HasAtomics, // ATOMIC_STORE8_I32_A64
7408 CEFBS_HasAtomics, // ATOMIC_STORE8_I32_A64_S
7409 CEFBS_HasAtomics, // ATOMIC_STORE8_I64_A32
7410 CEFBS_HasAtomics, // ATOMIC_STORE8_I64_A32_S
7411 CEFBS_HasAtomics, // ATOMIC_STORE8_I64_A64
7412 CEFBS_HasAtomics, // ATOMIC_STORE8_I64_A64_S
7413 CEFBS_HasAtomics, // ATOMIC_STORE_I32_A32
7414 CEFBS_HasAtomics, // ATOMIC_STORE_I32_A32_S
7415 CEFBS_HasAtomics, // ATOMIC_STORE_I32_A64
7416 CEFBS_HasAtomics, // ATOMIC_STORE_I32_A64_S
7417 CEFBS_HasAtomics, // ATOMIC_STORE_I64_A32
7418 CEFBS_HasAtomics, // ATOMIC_STORE_I64_A32_S
7419 CEFBS_HasAtomics, // ATOMIC_STORE_I64_A64
7420 CEFBS_HasAtomics, // ATOMIC_STORE_I64_A64_S
7421 CEFBS_HasSIMD128, // AVGR_U_I16x8
7422 CEFBS_HasSIMD128, // AVGR_U_I16x8_S
7423 CEFBS_HasSIMD128, // AVGR_U_I8x16
7424 CEFBS_HasSIMD128, // AVGR_U_I8x16_S
7425 CEFBS_HasSIMD128, // BITMASK_I16x8
7426 CEFBS_HasSIMD128, // BITMASK_I16x8_S
7427 CEFBS_HasSIMD128, // BITMASK_I32x4
7428 CEFBS_HasSIMD128, // BITMASK_I32x4_S
7429 CEFBS_HasSIMD128, // BITMASK_I64x2
7430 CEFBS_HasSIMD128, // BITMASK_I64x2_S
7431 CEFBS_HasSIMD128, // BITMASK_I8x16
7432 CEFBS_HasSIMD128, // BITMASK_I8x16_S
7433 CEFBS_HasSIMD128, // BITSELECT
7434 CEFBS_HasSIMD128, // BITSELECT_S
7435 CEFBS_None, // BLOCK
7436 CEFBS_None, // BLOCK_S
7437 CEFBS_None, // BR
7438 CEFBS_None, // BR_IF
7439 CEFBS_None, // BR_IF_S
7440 CEFBS_None, // BR_S
7441 CEFBS_None, // BR_TABLE_I32
7442 CEFBS_None, // BR_TABLE_I32_S
7443 CEFBS_None, // BR_TABLE_I64
7444 CEFBS_None, // BR_TABLE_I64_S
7445 CEFBS_None, // BR_UNLESS
7446 CEFBS_None, // BR_UNLESS_S
7447 CEFBS_None, // CALL
7448 CEFBS_None, // CALL_INDIRECT
7449 CEFBS_None, // CALL_INDIRECT_S
7450 CEFBS_None, // CALL_S
7451 CEFBS_HasExceptionHandling, // CATCH
7452 CEFBS_HasExceptionHandling, // CATCH_ALL
7453 CEFBS_HasExceptionHandling, // CATCH_ALL_LEGACY
7454 CEFBS_HasExceptionHandling, // CATCH_ALL_LEGACY_S
7455 CEFBS_HasExceptionHandling, // CATCH_ALL_REF
7456 CEFBS_HasExceptionHandling, // CATCH_ALL_REF_S
7457 CEFBS_HasExceptionHandling, // CATCH_ALL_S
7458 CEFBS_HasExceptionHandling, // CATCH_LEGACY
7459 CEFBS_HasExceptionHandling, // CATCH_LEGACY_S
7460 CEFBS_HasExceptionHandling, // CATCH_REF
7461 CEFBS_HasExceptionHandling, // CATCH_REF_S
7462 CEFBS_HasExceptionHandling, // CATCH_S
7463 CEFBS_HasSIMD128_HasFP16, // CEIL_F16x8
7464 CEFBS_HasSIMD128_HasFP16, // CEIL_F16x8_S
7465 CEFBS_None, // CEIL_F32
7466 CEFBS_None, // CEIL_F32_S
7467 CEFBS_HasSIMD128, // CEIL_F32x4
7468 CEFBS_HasSIMD128, // CEIL_F32x4_S
7469 CEFBS_None, // CEIL_F64
7470 CEFBS_None, // CEIL_F64_S
7471 CEFBS_HasSIMD128, // CEIL_F64x2
7472 CEFBS_HasSIMD128, // CEIL_F64x2_S
7473 CEFBS_None, // CLZ_I32
7474 CEFBS_None, // CLZ_I32_S
7475 CEFBS_None, // CLZ_I64
7476 CEFBS_None, // CLZ_I64_S
7477 CEFBS_None, // CONST_F32
7478 CEFBS_None, // CONST_F32_S
7479 CEFBS_None, // CONST_F64
7480 CEFBS_None, // CONST_F64_S
7481 CEFBS_None, // CONST_I32
7482 CEFBS_None, // CONST_I32_S
7483 CEFBS_None, // CONST_I64
7484 CEFBS_None, // CONST_I64_S
7485 CEFBS_HasSIMD128, // CONST_V128_F32x4
7486 CEFBS_HasSIMD128, // CONST_V128_F32x4_S
7487 CEFBS_HasSIMD128, // CONST_V128_F64x2
7488 CEFBS_HasSIMD128, // CONST_V128_F64x2_S
7489 CEFBS_HasSIMD128, // CONST_V128_I16x8
7490 CEFBS_HasSIMD128, // CONST_V128_I16x8_S
7491 CEFBS_HasSIMD128, // CONST_V128_I32x4
7492 CEFBS_HasSIMD128, // CONST_V128_I32x4_S
7493 CEFBS_HasSIMD128, // CONST_V128_I64x2
7494 CEFBS_HasSIMD128, // CONST_V128_I64x2_S
7495 CEFBS_HasSIMD128, // CONST_V128_I8x16
7496 CEFBS_HasSIMD128, // CONST_V128_I8x16_S
7497 CEFBS_None, // COPYSIGN_F32
7498 CEFBS_None, // COPYSIGN_F32_S
7499 CEFBS_None, // COPYSIGN_F64
7500 CEFBS_None, // COPYSIGN_F64_S
7501 CEFBS_HasReferenceTypes_HasExceptionHandling, // COPY_EXNREF
7502 CEFBS_HasReferenceTypes_HasExceptionHandling, // COPY_EXNREF_S
7503 CEFBS_HasReferenceTypes, // COPY_EXTERNREF
7504 CEFBS_HasReferenceTypes, // COPY_EXTERNREF_S
7505 CEFBS_None, // COPY_F32
7506 CEFBS_None, // COPY_F32_S
7507 CEFBS_None, // COPY_F64
7508 CEFBS_None, // COPY_F64_S
7509 CEFBS_HasReferenceTypes, // COPY_FUNCREF
7510 CEFBS_HasReferenceTypes, // COPY_FUNCREF_S
7511 CEFBS_None, // COPY_I32
7512 CEFBS_None, // COPY_I32_S
7513 CEFBS_None, // COPY_I64
7514 CEFBS_None, // COPY_I64_S
7515 CEFBS_HasSIMD128, // COPY_V128
7516 CEFBS_HasSIMD128, // COPY_V128_S
7517 CEFBS_None, // CTZ_I32
7518 CEFBS_None, // CTZ_I32_S
7519 CEFBS_None, // CTZ_I64
7520 CEFBS_None, // CTZ_I64_S
7521 CEFBS_HasBulkMemoryOpt, // DATA_DROP
7522 CEFBS_HasBulkMemoryOpt, // DATA_DROP_S
7523 CEFBS_None, // DEBUG_UNREACHABLE
7524 CEFBS_None, // DEBUG_UNREACHABLE_S
7525 CEFBS_HasExceptionHandling, // DELEGATE
7526 CEFBS_HasExceptionHandling, // DELEGATE_S
7527 CEFBS_HasSIMD128_HasFP16, // DIV_F16x8
7528 CEFBS_HasSIMD128_HasFP16, // DIV_F16x8_S
7529 CEFBS_None, // DIV_F32
7530 CEFBS_None, // DIV_F32_S
7531 CEFBS_HasSIMD128, // DIV_F32x4
7532 CEFBS_HasSIMD128, // DIV_F32x4_S
7533 CEFBS_None, // DIV_F64
7534 CEFBS_None, // DIV_F64_S
7535 CEFBS_HasSIMD128, // DIV_F64x2
7536 CEFBS_HasSIMD128, // DIV_F64x2_S
7537 CEFBS_None, // DIV_S_I32
7538 CEFBS_None, // DIV_S_I32_S
7539 CEFBS_None, // DIV_S_I64
7540 CEFBS_None, // DIV_S_I64_S
7541 CEFBS_None, // DIV_U_I32
7542 CEFBS_None, // DIV_U_I32_S
7543 CEFBS_None, // DIV_U_I64
7544 CEFBS_None, // DIV_U_I64_S
7545 CEFBS_HasSIMD128, // DOT
7546 CEFBS_HasSIMD128, // DOT_S
7547 CEFBS_HasReferenceTypes_HasExceptionHandling, // DROP_EXNREF
7548 CEFBS_HasReferenceTypes_HasExceptionHandling, // DROP_EXNREF_S
7549 CEFBS_HasReferenceTypes, // DROP_EXTERNREF
7550 CEFBS_HasReferenceTypes, // DROP_EXTERNREF_S
7551 CEFBS_None, // DROP_F32
7552 CEFBS_None, // DROP_F32_S
7553 CEFBS_None, // DROP_F64
7554 CEFBS_None, // DROP_F64_S
7555 CEFBS_HasReferenceTypes, // DROP_FUNCREF
7556 CEFBS_HasReferenceTypes, // DROP_FUNCREF_S
7557 CEFBS_None, // DROP_I32
7558 CEFBS_None, // DROP_I32_S
7559 CEFBS_None, // DROP_I64
7560 CEFBS_None, // DROP_I64_S
7561 CEFBS_HasSIMD128, // DROP_V128
7562 CEFBS_HasSIMD128, // DROP_V128_S
7563 CEFBS_None, // ELSE
7564 CEFBS_None, // ELSE_S
7565 CEFBS_None, // END
7566 CEFBS_None, // END_BLOCK
7567 CEFBS_None, // END_BLOCK_S
7568 CEFBS_None, // END_FUNCTION
7569 CEFBS_None, // END_FUNCTION_S
7570 CEFBS_None, // END_IF
7571 CEFBS_None, // END_IF_S
7572 CEFBS_None, // END_LOOP
7573 CEFBS_None, // END_LOOP_S
7574 CEFBS_None, // END_S
7575 CEFBS_HasExceptionHandling, // END_TRY
7576 CEFBS_HasExceptionHandling, // END_TRY_S
7577 CEFBS_HasExceptionHandling, // END_TRY_TABLE
7578 CEFBS_HasExceptionHandling, // END_TRY_TABLE_S
7579 CEFBS_None, // EQZ_I32
7580 CEFBS_None, // EQZ_I32_S
7581 CEFBS_None, // EQZ_I64
7582 CEFBS_None, // EQZ_I64_S
7583 CEFBS_HasSIMD128_HasFP16, // EQ_F16x8
7584 CEFBS_HasSIMD128_HasFP16, // EQ_F16x8_S
7585 CEFBS_None, // EQ_F32
7586 CEFBS_None, // EQ_F32_S
7587 CEFBS_HasSIMD128, // EQ_F32x4
7588 CEFBS_HasSIMD128, // EQ_F32x4_S
7589 CEFBS_None, // EQ_F64
7590 CEFBS_None, // EQ_F64_S
7591 CEFBS_HasSIMD128, // EQ_F64x2
7592 CEFBS_HasSIMD128, // EQ_F64x2_S
7593 CEFBS_HasSIMD128, // EQ_I16x8
7594 CEFBS_HasSIMD128, // EQ_I16x8_S
7595 CEFBS_None, // EQ_I32
7596 CEFBS_None, // EQ_I32_S
7597 CEFBS_HasSIMD128, // EQ_I32x4
7598 CEFBS_HasSIMD128, // EQ_I32x4_S
7599 CEFBS_None, // EQ_I64
7600 CEFBS_None, // EQ_I64_S
7601 CEFBS_HasSIMD128, // EQ_I64x2
7602 CEFBS_HasSIMD128, // EQ_I64x2_S
7603 CEFBS_HasSIMD128, // EQ_I8x16
7604 CEFBS_HasSIMD128, // EQ_I8x16_S
7605 CEFBS_HasSIMD128, // EXTMUL_HIGH_S_I16x8
7606 CEFBS_HasSIMD128, // EXTMUL_HIGH_S_I16x8_S
7607 CEFBS_HasSIMD128, // EXTMUL_HIGH_S_I32x4
7608 CEFBS_HasSIMD128, // EXTMUL_HIGH_S_I32x4_S
7609 CEFBS_HasSIMD128, // EXTMUL_HIGH_S_I64x2
7610 CEFBS_HasSIMD128, // EXTMUL_HIGH_S_I64x2_S
7611 CEFBS_HasSIMD128, // EXTMUL_HIGH_U_I16x8
7612 CEFBS_HasSIMD128, // EXTMUL_HIGH_U_I16x8_S
7613 CEFBS_HasSIMD128, // EXTMUL_HIGH_U_I32x4
7614 CEFBS_HasSIMD128, // EXTMUL_HIGH_U_I32x4_S
7615 CEFBS_HasSIMD128, // EXTMUL_HIGH_U_I64x2
7616 CEFBS_HasSIMD128, // EXTMUL_HIGH_U_I64x2_S
7617 CEFBS_HasSIMD128, // EXTMUL_LOW_S_I16x8
7618 CEFBS_HasSIMD128, // EXTMUL_LOW_S_I16x8_S
7619 CEFBS_HasSIMD128, // EXTMUL_LOW_S_I32x4
7620 CEFBS_HasSIMD128, // EXTMUL_LOW_S_I32x4_S
7621 CEFBS_HasSIMD128, // EXTMUL_LOW_S_I64x2
7622 CEFBS_HasSIMD128, // EXTMUL_LOW_S_I64x2_S
7623 CEFBS_HasSIMD128, // EXTMUL_LOW_U_I16x8
7624 CEFBS_HasSIMD128, // EXTMUL_LOW_U_I16x8_S
7625 CEFBS_HasSIMD128, // EXTMUL_LOW_U_I32x4
7626 CEFBS_HasSIMD128, // EXTMUL_LOW_U_I32x4_S
7627 CEFBS_HasSIMD128, // EXTMUL_LOW_U_I64x2
7628 CEFBS_HasSIMD128, // EXTMUL_LOW_U_I64x2_S
7629 CEFBS_HasFP16, // EXTRACT_LANE_F16x8
7630 CEFBS_HasFP16, // EXTRACT_LANE_F16x8_S
7631 CEFBS_HasSIMD128, // EXTRACT_LANE_F32x4
7632 CEFBS_HasSIMD128, // EXTRACT_LANE_F32x4_S
7633 CEFBS_HasSIMD128, // EXTRACT_LANE_F64x2
7634 CEFBS_HasSIMD128, // EXTRACT_LANE_F64x2_S
7635 CEFBS_HasSIMD128, // EXTRACT_LANE_I16x8_s
7636 CEFBS_HasSIMD128, // EXTRACT_LANE_I16x8_s_S
7637 CEFBS_HasSIMD128, // EXTRACT_LANE_I16x8_u
7638 CEFBS_HasSIMD128, // EXTRACT_LANE_I16x8_u_S
7639 CEFBS_HasSIMD128, // EXTRACT_LANE_I32x4
7640 CEFBS_HasSIMD128, // EXTRACT_LANE_I32x4_S
7641 CEFBS_HasSIMD128, // EXTRACT_LANE_I64x2
7642 CEFBS_HasSIMD128, // EXTRACT_LANE_I64x2_S
7643 CEFBS_HasSIMD128, // EXTRACT_LANE_I8x16_s
7644 CEFBS_HasSIMD128, // EXTRACT_LANE_I8x16_s_S
7645 CEFBS_HasSIMD128, // EXTRACT_LANE_I8x16_u
7646 CEFBS_HasSIMD128, // EXTRACT_LANE_I8x16_u_S
7647 CEFBS_None, // F32_CONVERT_S_I32
7648 CEFBS_None, // F32_CONVERT_S_I32_S
7649 CEFBS_None, // F32_CONVERT_S_I64
7650 CEFBS_None, // F32_CONVERT_S_I64_S
7651 CEFBS_None, // F32_CONVERT_U_I32
7652 CEFBS_None, // F32_CONVERT_U_I32_S
7653 CEFBS_None, // F32_CONVERT_U_I64
7654 CEFBS_None, // F32_CONVERT_U_I64_S
7655 CEFBS_None, // F32_DEMOTE_F64
7656 CEFBS_None, // F32_DEMOTE_F64_S
7657 CEFBS_None, // F32_REINTERPRET_I32
7658 CEFBS_None, // F32_REINTERPRET_I32_S
7659 CEFBS_None, // F64_CONVERT_S_I32
7660 CEFBS_None, // F64_CONVERT_S_I32_S
7661 CEFBS_None, // F64_CONVERT_S_I64
7662 CEFBS_None, // F64_CONVERT_S_I64_S
7663 CEFBS_None, // F64_CONVERT_U_I32
7664 CEFBS_None, // F64_CONVERT_U_I32_S
7665 CEFBS_None, // F64_CONVERT_U_I64
7666 CEFBS_None, // F64_CONVERT_U_I64_S
7667 CEFBS_None, // F64_PROMOTE_F32
7668 CEFBS_None, // F64_PROMOTE_F32_S
7669 CEFBS_None, // F64_REINTERPRET_I64
7670 CEFBS_None, // F64_REINTERPRET_I64_S
7671 CEFBS_None, // FALLTHROUGH_RETURN
7672 CEFBS_None, // FALLTHROUGH_RETURN_S
7673 CEFBS_HasSIMD128_HasFP16, // FLOOR_F16x8
7674 CEFBS_HasSIMD128_HasFP16, // FLOOR_F16x8_S
7675 CEFBS_None, // FLOOR_F32
7676 CEFBS_None, // FLOOR_F32_S
7677 CEFBS_HasSIMD128, // FLOOR_F32x4
7678 CEFBS_HasSIMD128, // FLOOR_F32x4_S
7679 CEFBS_None, // FLOOR_F64
7680 CEFBS_None, // FLOOR_F64_S
7681 CEFBS_HasSIMD128, // FLOOR_F64x2
7682 CEFBS_HasSIMD128, // FLOOR_F64x2_S
7683 CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I32_F32
7684 CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I32_F32_S
7685 CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I32_F64
7686 CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I32_F64_S
7687 CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I64_F32
7688 CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I64_F32_S
7689 CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I64_F64
7690 CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I64_F64_S
7691 CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I32_F32
7692 CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I32_F32_S
7693 CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I32_F64
7694 CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I32_F64_S
7695 CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I64_F32
7696 CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I64_F32_S
7697 CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I64_F64
7698 CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I64_F64_S
7699 CEFBS_HasSIMD128_HasFP16, // GE_F16x8
7700 CEFBS_HasSIMD128_HasFP16, // GE_F16x8_S
7701 CEFBS_None, // GE_F32
7702 CEFBS_None, // GE_F32_S
7703 CEFBS_HasSIMD128, // GE_F32x4
7704 CEFBS_HasSIMD128, // GE_F32x4_S
7705 CEFBS_None, // GE_F64
7706 CEFBS_None, // GE_F64_S
7707 CEFBS_HasSIMD128, // GE_F64x2
7708 CEFBS_HasSIMD128, // GE_F64x2_S
7709 CEFBS_HasSIMD128, // GE_S_I16x8
7710 CEFBS_HasSIMD128, // GE_S_I16x8_S
7711 CEFBS_None, // GE_S_I32
7712 CEFBS_None, // GE_S_I32_S
7713 CEFBS_HasSIMD128, // GE_S_I32x4
7714 CEFBS_HasSIMD128, // GE_S_I32x4_S
7715 CEFBS_None, // GE_S_I64
7716 CEFBS_None, // GE_S_I64_S
7717 CEFBS_HasSIMD128, // GE_S_I64x2
7718 CEFBS_HasSIMD128, // GE_S_I64x2_S
7719 CEFBS_HasSIMD128, // GE_S_I8x16
7720 CEFBS_HasSIMD128, // GE_S_I8x16_S
7721 CEFBS_HasSIMD128, // GE_U_I16x8
7722 CEFBS_HasSIMD128, // GE_U_I16x8_S
7723 CEFBS_None, // GE_U_I32
7724 CEFBS_None, // GE_U_I32_S
7725 CEFBS_HasSIMD128, // GE_U_I32x4
7726 CEFBS_HasSIMD128, // GE_U_I32x4_S
7727 CEFBS_None, // GE_U_I64
7728 CEFBS_None, // GE_U_I64_S
7729 CEFBS_HasSIMD128, // GE_U_I8x16
7730 CEFBS_HasSIMD128, // GE_U_I8x16_S
7731 CEFBS_HasReferenceTypes_HasExceptionHandling, // GLOBAL_GET_EXNREF
7732 CEFBS_HasReferenceTypes_HasExceptionHandling, // GLOBAL_GET_EXNREF_S
7733 CEFBS_HasReferenceTypes, // GLOBAL_GET_EXTERNREF
7734 CEFBS_HasReferenceTypes, // GLOBAL_GET_EXTERNREF_S
7735 CEFBS_None, // GLOBAL_GET_F32
7736 CEFBS_None, // GLOBAL_GET_F32_S
7737 CEFBS_None, // GLOBAL_GET_F64
7738 CEFBS_None, // GLOBAL_GET_F64_S
7739 CEFBS_HasReferenceTypes, // GLOBAL_GET_FUNCREF
7740 CEFBS_HasReferenceTypes, // GLOBAL_GET_FUNCREF_S
7741 CEFBS_None, // GLOBAL_GET_I32
7742 CEFBS_None, // GLOBAL_GET_I32_S
7743 CEFBS_None, // GLOBAL_GET_I64
7744 CEFBS_None, // GLOBAL_GET_I64_S
7745 CEFBS_HasSIMD128, // GLOBAL_GET_V128
7746 CEFBS_HasSIMD128, // GLOBAL_GET_V128_S
7747 CEFBS_HasReferenceTypes_HasExceptionHandling, // GLOBAL_SET_EXNREF
7748 CEFBS_HasReferenceTypes_HasExceptionHandling, // GLOBAL_SET_EXNREF_S
7749 CEFBS_HasReferenceTypes, // GLOBAL_SET_EXTERNREF
7750 CEFBS_HasReferenceTypes, // GLOBAL_SET_EXTERNREF_S
7751 CEFBS_None, // GLOBAL_SET_F32
7752 CEFBS_None, // GLOBAL_SET_F32_S
7753 CEFBS_None, // GLOBAL_SET_F64
7754 CEFBS_None, // GLOBAL_SET_F64_S
7755 CEFBS_HasReferenceTypes, // GLOBAL_SET_FUNCREF
7756 CEFBS_HasReferenceTypes, // GLOBAL_SET_FUNCREF_S
7757 CEFBS_None, // GLOBAL_SET_I32
7758 CEFBS_None, // GLOBAL_SET_I32_S
7759 CEFBS_None, // GLOBAL_SET_I64
7760 CEFBS_None, // GLOBAL_SET_I64_S
7761 CEFBS_HasSIMD128, // GLOBAL_SET_V128
7762 CEFBS_HasSIMD128, // GLOBAL_SET_V128_S
7763 CEFBS_HasSIMD128_HasFP16, // GT_F16x8
7764 CEFBS_HasSIMD128_HasFP16, // GT_F16x8_S
7765 CEFBS_None, // GT_F32
7766 CEFBS_None, // GT_F32_S
7767 CEFBS_HasSIMD128, // GT_F32x4
7768 CEFBS_HasSIMD128, // GT_F32x4_S
7769 CEFBS_None, // GT_F64
7770 CEFBS_None, // GT_F64_S
7771 CEFBS_HasSIMD128, // GT_F64x2
7772 CEFBS_HasSIMD128, // GT_F64x2_S
7773 CEFBS_HasSIMD128, // GT_S_I16x8
7774 CEFBS_HasSIMD128, // GT_S_I16x8_S
7775 CEFBS_None, // GT_S_I32
7776 CEFBS_None, // GT_S_I32_S
7777 CEFBS_HasSIMD128, // GT_S_I32x4
7778 CEFBS_HasSIMD128, // GT_S_I32x4_S
7779 CEFBS_None, // GT_S_I64
7780 CEFBS_None, // GT_S_I64_S
7781 CEFBS_HasSIMD128, // GT_S_I64x2
7782 CEFBS_HasSIMD128, // GT_S_I64x2_S
7783 CEFBS_HasSIMD128, // GT_S_I8x16
7784 CEFBS_HasSIMD128, // GT_S_I8x16_S
7785 CEFBS_HasSIMD128, // GT_U_I16x8
7786 CEFBS_HasSIMD128, // GT_U_I16x8_S
7787 CEFBS_None, // GT_U_I32
7788 CEFBS_None, // GT_U_I32_S
7789 CEFBS_HasSIMD128, // GT_U_I32x4
7790 CEFBS_HasSIMD128, // GT_U_I32x4_S
7791 CEFBS_None, // GT_U_I64
7792 CEFBS_None, // GT_U_I64_S
7793 CEFBS_HasSIMD128, // GT_U_I8x16
7794 CEFBS_HasSIMD128, // GT_U_I8x16_S
7795 CEFBS_HasSignExt, // I32_EXTEND16_S_I32
7796 CEFBS_HasSignExt, // I32_EXTEND16_S_I32_S
7797 CEFBS_HasSignExt, // I32_EXTEND8_S_I32
7798 CEFBS_HasSignExt, // I32_EXTEND8_S_I32_S
7799 CEFBS_None, // I32_REINTERPRET_F32
7800 CEFBS_None, // I32_REINTERPRET_F32_S
7801 CEFBS_None, // I32_TRUNC_S_F32
7802 CEFBS_None, // I32_TRUNC_S_F32_S
7803 CEFBS_None, // I32_TRUNC_S_F64
7804 CEFBS_None, // I32_TRUNC_S_F64_S
7805 CEFBS_HasNontrappingFPToInt, // I32_TRUNC_S_SAT_F32
7806 CEFBS_HasNontrappingFPToInt, // I32_TRUNC_S_SAT_F32_S
7807 CEFBS_HasNontrappingFPToInt, // I32_TRUNC_S_SAT_F64
7808 CEFBS_HasNontrappingFPToInt, // I32_TRUNC_S_SAT_F64_S
7809 CEFBS_None, // I32_TRUNC_U_F32
7810 CEFBS_None, // I32_TRUNC_U_F32_S
7811 CEFBS_None, // I32_TRUNC_U_F64
7812 CEFBS_None, // I32_TRUNC_U_F64_S
7813 CEFBS_HasNontrappingFPToInt, // I32_TRUNC_U_SAT_F32
7814 CEFBS_HasNontrappingFPToInt, // I32_TRUNC_U_SAT_F32_S
7815 CEFBS_HasNontrappingFPToInt, // I32_TRUNC_U_SAT_F64
7816 CEFBS_HasNontrappingFPToInt, // I32_TRUNC_U_SAT_F64_S
7817 CEFBS_None, // I32_WRAP_I64
7818 CEFBS_None, // I32_WRAP_I64_S
7819 CEFBS_HasWideArithmetic, // I64_ADD128
7820 CEFBS_HasWideArithmetic, // I64_ADD128_S
7821 CEFBS_HasSignExt, // I64_EXTEND16_S_I64
7822 CEFBS_HasSignExt, // I64_EXTEND16_S_I64_S
7823 CEFBS_HasSignExt, // I64_EXTEND32_S_I64
7824 CEFBS_HasSignExt, // I64_EXTEND32_S_I64_S
7825 CEFBS_HasSignExt, // I64_EXTEND8_S_I64
7826 CEFBS_HasSignExt, // I64_EXTEND8_S_I64_S
7827 CEFBS_None, // I64_EXTEND_S_I32
7828 CEFBS_None, // I64_EXTEND_S_I32_S
7829 CEFBS_None, // I64_EXTEND_U_I32
7830 CEFBS_None, // I64_EXTEND_U_I32_S
7831 CEFBS_HasWideArithmetic, // I64_MUL_WIDE_S
7832 CEFBS_HasWideArithmetic, // I64_MUL_WIDE_S_S
7833 CEFBS_HasWideArithmetic, // I64_MUL_WIDE_U
7834 CEFBS_HasWideArithmetic, // I64_MUL_WIDE_U_S
7835 CEFBS_None, // I64_REINTERPRET_F64
7836 CEFBS_None, // I64_REINTERPRET_F64_S
7837 CEFBS_HasWideArithmetic, // I64_SUB128
7838 CEFBS_HasWideArithmetic, // I64_SUB128_S
7839 CEFBS_None, // I64_TRUNC_S_F32
7840 CEFBS_None, // I64_TRUNC_S_F32_S
7841 CEFBS_None, // I64_TRUNC_S_F64
7842 CEFBS_None, // I64_TRUNC_S_F64_S
7843 CEFBS_HasNontrappingFPToInt, // I64_TRUNC_S_SAT_F32
7844 CEFBS_HasNontrappingFPToInt, // I64_TRUNC_S_SAT_F32_S
7845 CEFBS_HasNontrappingFPToInt, // I64_TRUNC_S_SAT_F64
7846 CEFBS_HasNontrappingFPToInt, // I64_TRUNC_S_SAT_F64_S
7847 CEFBS_None, // I64_TRUNC_U_F32
7848 CEFBS_None, // I64_TRUNC_U_F32_S
7849 CEFBS_None, // I64_TRUNC_U_F64
7850 CEFBS_None, // I64_TRUNC_U_F64_S
7851 CEFBS_HasNontrappingFPToInt, // I64_TRUNC_U_SAT_F32
7852 CEFBS_HasNontrappingFPToInt, // I64_TRUNC_U_SAT_F32_S
7853 CEFBS_HasNontrappingFPToInt, // I64_TRUNC_U_SAT_F64
7854 CEFBS_HasNontrappingFPToInt, // I64_TRUNC_U_SAT_F64_S
7855 CEFBS_None, // IF
7856 CEFBS_None, // IF_S
7857 CEFBS_HasRelaxedSIMD, // LANESELECT_I16x8
7858 CEFBS_HasRelaxedSIMD, // LANESELECT_I16x8_S
7859 CEFBS_HasRelaxedSIMD, // LANESELECT_I32x4
7860 CEFBS_HasRelaxedSIMD, // LANESELECT_I32x4_S
7861 CEFBS_HasRelaxedSIMD, // LANESELECT_I64x2
7862 CEFBS_HasRelaxedSIMD, // LANESELECT_I64x2_S
7863 CEFBS_HasRelaxedSIMD, // LANESELECT_I8x16
7864 CEFBS_HasRelaxedSIMD, // LANESELECT_I8x16_S
7865 CEFBS_HasSIMD128_HasFP16, // LE_F16x8
7866 CEFBS_HasSIMD128_HasFP16, // LE_F16x8_S
7867 CEFBS_None, // LE_F32
7868 CEFBS_None, // LE_F32_S
7869 CEFBS_HasSIMD128, // LE_F32x4
7870 CEFBS_HasSIMD128, // LE_F32x4_S
7871 CEFBS_None, // LE_F64
7872 CEFBS_None, // LE_F64_S
7873 CEFBS_HasSIMD128, // LE_F64x2
7874 CEFBS_HasSIMD128, // LE_F64x2_S
7875 CEFBS_HasSIMD128, // LE_S_I16x8
7876 CEFBS_HasSIMD128, // LE_S_I16x8_S
7877 CEFBS_None, // LE_S_I32
7878 CEFBS_None, // LE_S_I32_S
7879 CEFBS_HasSIMD128, // LE_S_I32x4
7880 CEFBS_HasSIMD128, // LE_S_I32x4_S
7881 CEFBS_None, // LE_S_I64
7882 CEFBS_None, // LE_S_I64_S
7883 CEFBS_HasSIMD128, // LE_S_I64x2
7884 CEFBS_HasSIMD128, // LE_S_I64x2_S
7885 CEFBS_HasSIMD128, // LE_S_I8x16
7886 CEFBS_HasSIMD128, // LE_S_I8x16_S
7887 CEFBS_HasSIMD128, // LE_U_I16x8
7888 CEFBS_HasSIMD128, // LE_U_I16x8_S
7889 CEFBS_None, // LE_U_I32
7890 CEFBS_None, // LE_U_I32_S
7891 CEFBS_HasSIMD128, // LE_U_I32x4
7892 CEFBS_HasSIMD128, // LE_U_I32x4_S
7893 CEFBS_None, // LE_U_I64
7894 CEFBS_None, // LE_U_I64_S
7895 CEFBS_HasSIMD128, // LE_U_I8x16
7896 CEFBS_HasSIMD128, // LE_U_I8x16_S
7897 CEFBS_HasSIMD128, // LOAD16_SPLAT_A32
7898 CEFBS_HasSIMD128, // LOAD16_SPLAT_A32_S
7899 CEFBS_HasSIMD128, // LOAD16_SPLAT_A64
7900 CEFBS_HasSIMD128, // LOAD16_SPLAT_A64_S
7901 CEFBS_None, // LOAD16_S_I32_A32
7902 CEFBS_None, // LOAD16_S_I32_A32_S
7903 CEFBS_None, // LOAD16_S_I32_A64
7904 CEFBS_None, // LOAD16_S_I32_A64_S
7905 CEFBS_None, // LOAD16_S_I64_A32
7906 CEFBS_None, // LOAD16_S_I64_A32_S
7907 CEFBS_None, // LOAD16_S_I64_A64
7908 CEFBS_None, // LOAD16_S_I64_A64_S
7909 CEFBS_None, // LOAD16_U_I32_A32
7910 CEFBS_None, // LOAD16_U_I32_A32_S
7911 CEFBS_None, // LOAD16_U_I32_A64
7912 CEFBS_None, // LOAD16_U_I32_A64_S
7913 CEFBS_None, // LOAD16_U_I64_A32
7914 CEFBS_None, // LOAD16_U_I64_A32_S
7915 CEFBS_None, // LOAD16_U_I64_A64
7916 CEFBS_None, // LOAD16_U_I64_A64_S
7917 CEFBS_HasSIMD128, // LOAD32_SPLAT_A32
7918 CEFBS_HasSIMD128, // LOAD32_SPLAT_A32_S
7919 CEFBS_HasSIMD128, // LOAD32_SPLAT_A64
7920 CEFBS_HasSIMD128, // LOAD32_SPLAT_A64_S
7921 CEFBS_None, // LOAD32_S_I64_A32
7922 CEFBS_None, // LOAD32_S_I64_A32_S
7923 CEFBS_None, // LOAD32_S_I64_A64
7924 CEFBS_None, // LOAD32_S_I64_A64_S
7925 CEFBS_None, // LOAD32_U_I64_A32
7926 CEFBS_None, // LOAD32_U_I64_A32_S
7927 CEFBS_None, // LOAD32_U_I64_A64
7928 CEFBS_None, // LOAD32_U_I64_A64_S
7929 CEFBS_HasSIMD128, // LOAD64_SPLAT_A32
7930 CEFBS_HasSIMD128, // LOAD64_SPLAT_A32_S
7931 CEFBS_HasSIMD128, // LOAD64_SPLAT_A64
7932 CEFBS_HasSIMD128, // LOAD64_SPLAT_A64_S
7933 CEFBS_HasSIMD128, // LOAD8_SPLAT_A32
7934 CEFBS_HasSIMD128, // LOAD8_SPLAT_A32_S
7935 CEFBS_HasSIMD128, // LOAD8_SPLAT_A64
7936 CEFBS_HasSIMD128, // LOAD8_SPLAT_A64_S
7937 CEFBS_None, // LOAD8_S_I32_A32
7938 CEFBS_None, // LOAD8_S_I32_A32_S
7939 CEFBS_None, // LOAD8_S_I32_A64
7940 CEFBS_None, // LOAD8_S_I32_A64_S
7941 CEFBS_None, // LOAD8_S_I64_A32
7942 CEFBS_None, // LOAD8_S_I64_A32_S
7943 CEFBS_None, // LOAD8_S_I64_A64
7944 CEFBS_None, // LOAD8_S_I64_A64_S
7945 CEFBS_None, // LOAD8_U_I32_A32
7946 CEFBS_None, // LOAD8_U_I32_A32_S
7947 CEFBS_None, // LOAD8_U_I32_A64
7948 CEFBS_None, // LOAD8_U_I32_A64_S
7949 CEFBS_None, // LOAD8_U_I64_A32
7950 CEFBS_None, // LOAD8_U_I64_A32_S
7951 CEFBS_None, // LOAD8_U_I64_A64
7952 CEFBS_None, // LOAD8_U_I64_A64_S
7953 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I16x8_A32
7954 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I16x8_A32_S
7955 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I16x8_A64
7956 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I16x8_A64_S
7957 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I32x4_A32
7958 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I32x4_A32_S
7959 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I32x4_A64
7960 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I32x4_A64_S
7961 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I64x2_A32
7962 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I64x2_A32_S
7963 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I64x2_A64
7964 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I64x2_A64_S
7965 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I16x8_A32
7966 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I16x8_A32_S
7967 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I16x8_A64
7968 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I16x8_A64_S
7969 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I32x4_A32
7970 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I32x4_A32_S
7971 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I32x4_A64
7972 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I32x4_A64_S
7973 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I64x2_A32
7974 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I64x2_A32_S
7975 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I64x2_A64
7976 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I64x2_A64_S
7977 CEFBS_HasFP16, // LOAD_F16_F32_A32
7978 CEFBS_HasFP16, // LOAD_F16_F32_A32_S
7979 CEFBS_HasFP16, // LOAD_F16_F32_A64
7980 CEFBS_HasFP16, // LOAD_F16_F32_A64_S
7981 CEFBS_None, // LOAD_F32_A32
7982 CEFBS_None, // LOAD_F32_A32_S
7983 CEFBS_None, // LOAD_F32_A64
7984 CEFBS_None, // LOAD_F32_A64_S
7985 CEFBS_None, // LOAD_F64_A32
7986 CEFBS_None, // LOAD_F64_A32_S
7987 CEFBS_None, // LOAD_F64_A64
7988 CEFBS_None, // LOAD_F64_A64_S
7989 CEFBS_None, // LOAD_I32_A32
7990 CEFBS_None, // LOAD_I32_A32_S
7991 CEFBS_None, // LOAD_I32_A64
7992 CEFBS_None, // LOAD_I32_A64_S
7993 CEFBS_None, // LOAD_I64_A32
7994 CEFBS_None, // LOAD_I64_A32_S
7995 CEFBS_None, // LOAD_I64_A64
7996 CEFBS_None, // LOAD_I64_A64_S
7997 CEFBS_HasSIMD128, // LOAD_LANE_16_A32
7998 CEFBS_HasSIMD128, // LOAD_LANE_16_A32_S
7999 CEFBS_HasSIMD128, // LOAD_LANE_16_A64
8000 CEFBS_HasSIMD128, // LOAD_LANE_16_A64_S
8001 CEFBS_HasSIMD128, // LOAD_LANE_32_A32
8002 CEFBS_HasSIMD128, // LOAD_LANE_32_A32_S
8003 CEFBS_HasSIMD128, // LOAD_LANE_32_A64
8004 CEFBS_HasSIMD128, // LOAD_LANE_32_A64_S
8005 CEFBS_HasSIMD128, // LOAD_LANE_64_A32
8006 CEFBS_HasSIMD128, // LOAD_LANE_64_A32_S
8007 CEFBS_HasSIMD128, // LOAD_LANE_64_A64
8008 CEFBS_HasSIMD128, // LOAD_LANE_64_A64_S
8009 CEFBS_HasSIMD128, // LOAD_LANE_8_A32
8010 CEFBS_HasSIMD128, // LOAD_LANE_8_A32_S
8011 CEFBS_HasSIMD128, // LOAD_LANE_8_A64
8012 CEFBS_HasSIMD128, // LOAD_LANE_8_A64_S
8013 CEFBS_HasSIMD128, // LOAD_V128_A32
8014 CEFBS_HasSIMD128, // LOAD_V128_A32_S
8015 CEFBS_HasSIMD128, // LOAD_V128_A64
8016 CEFBS_HasSIMD128, // LOAD_V128_A64_S
8017 CEFBS_HasSIMD128, // LOAD_ZERO_32_A32
8018 CEFBS_HasSIMD128, // LOAD_ZERO_32_A32_S
8019 CEFBS_HasSIMD128, // LOAD_ZERO_32_A64
8020 CEFBS_HasSIMD128, // LOAD_ZERO_32_A64_S
8021 CEFBS_HasSIMD128, // LOAD_ZERO_64_A32
8022 CEFBS_HasSIMD128, // LOAD_ZERO_64_A32_S
8023 CEFBS_HasSIMD128, // LOAD_ZERO_64_A64
8024 CEFBS_HasSIMD128, // LOAD_ZERO_64_A64_S
8025 CEFBS_HasReferenceTypes_HasExceptionHandling, // LOCAL_GET_EXNREF
8026 CEFBS_HasReferenceTypes_HasExceptionHandling, // LOCAL_GET_EXNREF_S
8027 CEFBS_HasReferenceTypes, // LOCAL_GET_EXTERNREF
8028 CEFBS_HasReferenceTypes, // LOCAL_GET_EXTERNREF_S
8029 CEFBS_None, // LOCAL_GET_F32
8030 CEFBS_None, // LOCAL_GET_F32_S
8031 CEFBS_None, // LOCAL_GET_F64
8032 CEFBS_None, // LOCAL_GET_F64_S
8033 CEFBS_HasReferenceTypes, // LOCAL_GET_FUNCREF
8034 CEFBS_HasReferenceTypes, // LOCAL_GET_FUNCREF_S
8035 CEFBS_None, // LOCAL_GET_I32
8036 CEFBS_None, // LOCAL_GET_I32_S
8037 CEFBS_None, // LOCAL_GET_I64
8038 CEFBS_None, // LOCAL_GET_I64_S
8039 CEFBS_HasSIMD128, // LOCAL_GET_V128
8040 CEFBS_HasSIMD128, // LOCAL_GET_V128_S
8041 CEFBS_HasReferenceTypes_HasExceptionHandling, // LOCAL_SET_EXNREF
8042 CEFBS_HasReferenceTypes_HasExceptionHandling, // LOCAL_SET_EXNREF_S
8043 CEFBS_HasReferenceTypes, // LOCAL_SET_EXTERNREF
8044 CEFBS_HasReferenceTypes, // LOCAL_SET_EXTERNREF_S
8045 CEFBS_None, // LOCAL_SET_F32
8046 CEFBS_None, // LOCAL_SET_F32_S
8047 CEFBS_None, // LOCAL_SET_F64
8048 CEFBS_None, // LOCAL_SET_F64_S
8049 CEFBS_HasReferenceTypes, // LOCAL_SET_FUNCREF
8050 CEFBS_HasReferenceTypes, // LOCAL_SET_FUNCREF_S
8051 CEFBS_None, // LOCAL_SET_I32
8052 CEFBS_None, // LOCAL_SET_I32_S
8053 CEFBS_None, // LOCAL_SET_I64
8054 CEFBS_None, // LOCAL_SET_I64_S
8055 CEFBS_HasSIMD128, // LOCAL_SET_V128
8056 CEFBS_HasSIMD128, // LOCAL_SET_V128_S
8057 CEFBS_HasReferenceTypes_HasExceptionHandling, // LOCAL_TEE_EXNREF
8058 CEFBS_HasReferenceTypes_HasExceptionHandling, // LOCAL_TEE_EXNREF_S
8059 CEFBS_HasReferenceTypes, // LOCAL_TEE_EXTERNREF
8060 CEFBS_HasReferenceTypes, // LOCAL_TEE_EXTERNREF_S
8061 CEFBS_None, // LOCAL_TEE_F32
8062 CEFBS_None, // LOCAL_TEE_F32_S
8063 CEFBS_None, // LOCAL_TEE_F64
8064 CEFBS_None, // LOCAL_TEE_F64_S
8065 CEFBS_HasReferenceTypes, // LOCAL_TEE_FUNCREF
8066 CEFBS_HasReferenceTypes, // LOCAL_TEE_FUNCREF_S
8067 CEFBS_None, // LOCAL_TEE_I32
8068 CEFBS_None, // LOCAL_TEE_I32_S
8069 CEFBS_None, // LOCAL_TEE_I64
8070 CEFBS_None, // LOCAL_TEE_I64_S
8071 CEFBS_HasSIMD128, // LOCAL_TEE_V128
8072 CEFBS_HasSIMD128, // LOCAL_TEE_V128_S
8073 CEFBS_None, // LOOP
8074 CEFBS_None, // LOOP_S
8075 CEFBS_HasSIMD128_HasFP16, // LT_F16x8
8076 CEFBS_HasSIMD128_HasFP16, // LT_F16x8_S
8077 CEFBS_None, // LT_F32
8078 CEFBS_None, // LT_F32_S
8079 CEFBS_HasSIMD128, // LT_F32x4
8080 CEFBS_HasSIMD128, // LT_F32x4_S
8081 CEFBS_None, // LT_F64
8082 CEFBS_None, // LT_F64_S
8083 CEFBS_HasSIMD128, // LT_F64x2
8084 CEFBS_HasSIMD128, // LT_F64x2_S
8085 CEFBS_HasSIMD128, // LT_S_I16x8
8086 CEFBS_HasSIMD128, // LT_S_I16x8_S
8087 CEFBS_None, // LT_S_I32
8088 CEFBS_None, // LT_S_I32_S
8089 CEFBS_HasSIMD128, // LT_S_I32x4
8090 CEFBS_HasSIMD128, // LT_S_I32x4_S
8091 CEFBS_None, // LT_S_I64
8092 CEFBS_None, // LT_S_I64_S
8093 CEFBS_HasSIMD128, // LT_S_I64x2
8094 CEFBS_HasSIMD128, // LT_S_I64x2_S
8095 CEFBS_HasSIMD128, // LT_S_I8x16
8096 CEFBS_HasSIMD128, // LT_S_I8x16_S
8097 CEFBS_HasSIMD128, // LT_U_I16x8
8098 CEFBS_HasSIMD128, // LT_U_I16x8_S
8099 CEFBS_None, // LT_U_I32
8100 CEFBS_None, // LT_U_I32_S
8101 CEFBS_HasSIMD128, // LT_U_I32x4
8102 CEFBS_HasSIMD128, // LT_U_I32x4_S
8103 CEFBS_None, // LT_U_I64
8104 CEFBS_None, // LT_U_I64_S
8105 CEFBS_HasSIMD128, // LT_U_I8x16
8106 CEFBS_HasSIMD128, // LT_U_I8x16_S
8107 CEFBS_HasSIMD128_HasFP16, // MADD_F16x8
8108 CEFBS_HasSIMD128_HasFP16, // MADD_F16x8_S
8109 CEFBS_HasSIMD128_HasRelaxedSIMD, // MADD_F32x4
8110 CEFBS_HasSIMD128_HasRelaxedSIMD, // MADD_F32x4_S
8111 CEFBS_HasSIMD128_HasRelaxedSIMD, // MADD_F64x2
8112 CEFBS_HasSIMD128_HasRelaxedSIMD, // MADD_F64x2_S
8113 CEFBS_HasSIMD128_HasFP16, // MAX_F16x8
8114 CEFBS_HasSIMD128_HasFP16, // MAX_F16x8_S
8115 CEFBS_None, // MAX_F32
8116 CEFBS_None, // MAX_F32_S
8117 CEFBS_HasSIMD128, // MAX_F32x4
8118 CEFBS_HasSIMD128, // MAX_F32x4_S
8119 CEFBS_None, // MAX_F64
8120 CEFBS_None, // MAX_F64_S
8121 CEFBS_HasSIMD128, // MAX_F64x2
8122 CEFBS_HasSIMD128, // MAX_F64x2_S
8123 CEFBS_HasSIMD128, // MAX_S_I16x8
8124 CEFBS_HasSIMD128, // MAX_S_I16x8_S
8125 CEFBS_HasSIMD128, // MAX_S_I32x4
8126 CEFBS_HasSIMD128, // MAX_S_I32x4_S
8127 CEFBS_HasSIMD128, // MAX_S_I8x16
8128 CEFBS_HasSIMD128, // MAX_S_I8x16_S
8129 CEFBS_HasSIMD128, // MAX_U_I16x8
8130 CEFBS_HasSIMD128, // MAX_U_I16x8_S
8131 CEFBS_HasSIMD128, // MAX_U_I32x4
8132 CEFBS_HasSIMD128, // MAX_U_I32x4_S
8133 CEFBS_HasSIMD128, // MAX_U_I8x16
8134 CEFBS_HasSIMD128, // MAX_U_I8x16_S
8135 CEFBS_HasBulkMemoryOpt, // MEMCPY_A32
8136 CEFBS_HasBulkMemoryOpt, // MEMCPY_A32_S
8137 CEFBS_HasBulkMemoryOpt, // MEMCPY_A64
8138 CEFBS_HasBulkMemoryOpt, // MEMCPY_A64_S
8139 CEFBS_HasAtomics, // MEMORY_ATOMIC_NOTIFY_A32
8140 CEFBS_HasAtomics, // MEMORY_ATOMIC_NOTIFY_A32_S
8141 CEFBS_HasAtomics, // MEMORY_ATOMIC_NOTIFY_A64
8142 CEFBS_HasAtomics, // MEMORY_ATOMIC_NOTIFY_A64_S
8143 CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT32_A32
8144 CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT32_A32_S
8145 CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT32_A64
8146 CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT32_A64_S
8147 CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT64_A32
8148 CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT64_A32_S
8149 CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT64_A64
8150 CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT64_A64_S
8151 CEFBS_HasBulkMemoryOpt, // MEMORY_COPY_A32
8152 CEFBS_HasBulkMemoryOpt, // MEMORY_COPY_A32_S
8153 CEFBS_HasBulkMemoryOpt, // MEMORY_COPY_A64
8154 CEFBS_HasBulkMemoryOpt, // MEMORY_COPY_A64_S
8155 CEFBS_HasBulkMemoryOpt, // MEMORY_FILL_A32
8156 CEFBS_HasBulkMemoryOpt, // MEMORY_FILL_A32_S
8157 CEFBS_HasBulkMemoryOpt, // MEMORY_FILL_A64
8158 CEFBS_HasBulkMemoryOpt, // MEMORY_FILL_A64_S
8159 CEFBS_HasBulkMemoryOpt, // MEMORY_INIT_A32
8160 CEFBS_HasBulkMemoryOpt, // MEMORY_INIT_A32_S
8161 CEFBS_HasBulkMemoryOpt, // MEMORY_INIT_A64
8162 CEFBS_HasBulkMemoryOpt, // MEMORY_INIT_A64_S
8163 CEFBS_HasBulkMemoryOpt, // MEMSET_A32
8164 CEFBS_HasBulkMemoryOpt, // MEMSET_A32_S
8165 CEFBS_HasBulkMemoryOpt, // MEMSET_A64
8166 CEFBS_HasBulkMemoryOpt, // MEMSET_A64_S
8167 CEFBS_HasSIMD128_HasFP16, // MIN_F16x8
8168 CEFBS_HasSIMD128_HasFP16, // MIN_F16x8_S
8169 CEFBS_None, // MIN_F32
8170 CEFBS_None, // MIN_F32_S
8171 CEFBS_HasSIMD128, // MIN_F32x4
8172 CEFBS_HasSIMD128, // MIN_F32x4_S
8173 CEFBS_None, // MIN_F64
8174 CEFBS_None, // MIN_F64_S
8175 CEFBS_HasSIMD128, // MIN_F64x2
8176 CEFBS_HasSIMD128, // MIN_F64x2_S
8177 CEFBS_HasSIMD128, // MIN_S_I16x8
8178 CEFBS_HasSIMD128, // MIN_S_I16x8_S
8179 CEFBS_HasSIMD128, // MIN_S_I32x4
8180 CEFBS_HasSIMD128, // MIN_S_I32x4_S
8181 CEFBS_HasSIMD128, // MIN_S_I8x16
8182 CEFBS_HasSIMD128, // MIN_S_I8x16_S
8183 CEFBS_HasSIMD128, // MIN_U_I16x8
8184 CEFBS_HasSIMD128, // MIN_U_I16x8_S
8185 CEFBS_HasSIMD128, // MIN_U_I32x4
8186 CEFBS_HasSIMD128, // MIN_U_I32x4_S
8187 CEFBS_HasSIMD128, // MIN_U_I8x16
8188 CEFBS_HasSIMD128, // MIN_U_I8x16_S
8189 CEFBS_HasSIMD128_HasFP16, // MUL_F16x8
8190 CEFBS_HasSIMD128_HasFP16, // MUL_F16x8_S
8191 CEFBS_None, // MUL_F32
8192 CEFBS_None, // MUL_F32_S
8193 CEFBS_HasSIMD128, // MUL_F32x4
8194 CEFBS_HasSIMD128, // MUL_F32x4_S
8195 CEFBS_None, // MUL_F64
8196 CEFBS_None, // MUL_F64_S
8197 CEFBS_HasSIMD128, // MUL_F64x2
8198 CEFBS_HasSIMD128, // MUL_F64x2_S
8199 CEFBS_HasSIMD128, // MUL_I16x8
8200 CEFBS_HasSIMD128, // MUL_I16x8_S
8201 CEFBS_None, // MUL_I32
8202 CEFBS_None, // MUL_I32_S
8203 CEFBS_HasSIMD128, // MUL_I32x4
8204 CEFBS_HasSIMD128, // MUL_I32x4_S
8205 CEFBS_None, // MUL_I64
8206 CEFBS_None, // MUL_I64_S
8207 CEFBS_HasSIMD128, // MUL_I64x2
8208 CEFBS_HasSIMD128, // MUL_I64x2_S
8209 CEFBS_HasSIMD128, // NARROW_S_I16x8
8210 CEFBS_HasSIMD128, // NARROW_S_I16x8_S
8211 CEFBS_HasSIMD128, // NARROW_S_I8x16
8212 CEFBS_HasSIMD128, // NARROW_S_I8x16_S
8213 CEFBS_HasSIMD128, // NARROW_U_I16x8
8214 CEFBS_HasSIMD128, // NARROW_U_I16x8_S
8215 CEFBS_HasSIMD128, // NARROW_U_I8x16
8216 CEFBS_HasSIMD128, // NARROW_U_I8x16_S
8217 CEFBS_HasSIMD128_HasFP16, // NEAREST_F16x8
8218 CEFBS_HasSIMD128_HasFP16, // NEAREST_F16x8_S
8219 CEFBS_None, // NEAREST_F32
8220 CEFBS_None, // NEAREST_F32_S
8221 CEFBS_HasSIMD128, // NEAREST_F32x4
8222 CEFBS_HasSIMD128, // NEAREST_F32x4_S
8223 CEFBS_None, // NEAREST_F64
8224 CEFBS_None, // NEAREST_F64_S
8225 CEFBS_HasSIMD128, // NEAREST_F64x2
8226 CEFBS_HasSIMD128, // NEAREST_F64x2_S
8227 CEFBS_HasSIMD128_HasFP16, // NEG_F16x8
8228 CEFBS_HasSIMD128_HasFP16, // NEG_F16x8_S
8229 CEFBS_None, // NEG_F32
8230 CEFBS_None, // NEG_F32_S
8231 CEFBS_HasSIMD128, // NEG_F32x4
8232 CEFBS_HasSIMD128, // NEG_F32x4_S
8233 CEFBS_None, // NEG_F64
8234 CEFBS_None, // NEG_F64_S
8235 CEFBS_HasSIMD128, // NEG_F64x2
8236 CEFBS_HasSIMD128, // NEG_F64x2_S
8237 CEFBS_HasSIMD128, // NEG_I16x8
8238 CEFBS_HasSIMD128, // NEG_I16x8_S
8239 CEFBS_HasSIMD128, // NEG_I32x4
8240 CEFBS_HasSIMD128, // NEG_I32x4_S
8241 CEFBS_HasSIMD128, // NEG_I64x2
8242 CEFBS_HasSIMD128, // NEG_I64x2_S
8243 CEFBS_HasSIMD128, // NEG_I8x16
8244 CEFBS_HasSIMD128, // NEG_I8x16_S
8245 CEFBS_HasSIMD128_HasFP16, // NE_F16x8
8246 CEFBS_HasSIMD128_HasFP16, // NE_F16x8_S
8247 CEFBS_None, // NE_F32
8248 CEFBS_None, // NE_F32_S
8249 CEFBS_HasSIMD128, // NE_F32x4
8250 CEFBS_HasSIMD128, // NE_F32x4_S
8251 CEFBS_None, // NE_F64
8252 CEFBS_None, // NE_F64_S
8253 CEFBS_HasSIMD128, // NE_F64x2
8254 CEFBS_HasSIMD128, // NE_F64x2_S
8255 CEFBS_HasSIMD128, // NE_I16x8
8256 CEFBS_HasSIMD128, // NE_I16x8_S
8257 CEFBS_None, // NE_I32
8258 CEFBS_None, // NE_I32_S
8259 CEFBS_HasSIMD128, // NE_I32x4
8260 CEFBS_HasSIMD128, // NE_I32x4_S
8261 CEFBS_None, // NE_I64
8262 CEFBS_None, // NE_I64_S
8263 CEFBS_HasSIMD128, // NE_I64x2
8264 CEFBS_HasSIMD128, // NE_I64x2_S
8265 CEFBS_HasSIMD128, // NE_I8x16
8266 CEFBS_HasSIMD128, // NE_I8x16_S
8267 CEFBS_HasSIMD128_HasFP16, // NMADD_F16x8
8268 CEFBS_HasSIMD128_HasFP16, // NMADD_F16x8_S
8269 CEFBS_HasSIMD128_HasRelaxedSIMD, // NMADD_F32x4
8270 CEFBS_HasSIMD128_HasRelaxedSIMD, // NMADD_F32x4_S
8271 CEFBS_HasSIMD128_HasRelaxedSIMD, // NMADD_F64x2
8272 CEFBS_HasSIMD128_HasRelaxedSIMD, // NMADD_F64x2_S
8273 CEFBS_None, // NOP
8274 CEFBS_None, // NOP_S
8275 CEFBS_HasSIMD128, // NOT
8276 CEFBS_HasSIMD128, // NOT_S
8277 CEFBS_HasSIMD128, // OR
8278 CEFBS_None, // OR_I32
8279 CEFBS_None, // OR_I32_S
8280 CEFBS_None, // OR_I64
8281 CEFBS_None, // OR_I64_S
8282 CEFBS_HasSIMD128, // OR_S
8283 CEFBS_HasSIMD128_HasFP16, // PMAX_F16x8
8284 CEFBS_HasSIMD128_HasFP16, // PMAX_F16x8_S
8285 CEFBS_HasSIMD128, // PMAX_F32x4
8286 CEFBS_HasSIMD128, // PMAX_F32x4_S
8287 CEFBS_HasSIMD128, // PMAX_F64x2
8288 CEFBS_HasSIMD128, // PMAX_F64x2_S
8289 CEFBS_HasSIMD128_HasFP16, // PMIN_F16x8
8290 CEFBS_HasSIMD128_HasFP16, // PMIN_F16x8_S
8291 CEFBS_HasSIMD128, // PMIN_F32x4
8292 CEFBS_HasSIMD128, // PMIN_F32x4_S
8293 CEFBS_HasSIMD128, // PMIN_F64x2
8294 CEFBS_HasSIMD128, // PMIN_F64x2_S
8295 CEFBS_None, // POPCNT_I32
8296 CEFBS_None, // POPCNT_I32_S
8297 CEFBS_None, // POPCNT_I64
8298 CEFBS_None, // POPCNT_I64_S
8299 CEFBS_HasSIMD128, // POPCNT_I8x16
8300 CEFBS_HasSIMD128, // POPCNT_I8x16_S
8301 CEFBS_HasSIMD128, // Q15MULR_SAT_S_I16x8
8302 CEFBS_HasSIMD128, // Q15MULR_SAT_S_I16x8_S
8303 CEFBS_HasReferenceTypes, // REF_FUNC
8304 CEFBS_HasReferenceTypes, // REF_FUNC_S
8305 CEFBS_HasReferenceTypes, // REF_IS_NULL_EXNREF
8306 CEFBS_HasReferenceTypes, // REF_IS_NULL_EXNREF_S
8307 CEFBS_HasReferenceTypes, // REF_IS_NULL_EXTERNREF
8308 CEFBS_HasReferenceTypes, // REF_IS_NULL_EXTERNREF_S
8309 CEFBS_HasReferenceTypes, // REF_IS_NULL_FUNCREF
8310 CEFBS_HasReferenceTypes, // REF_IS_NULL_FUNCREF_S
8311 CEFBS_HasReferenceTypes, // REF_NULL_EXNREF
8312 CEFBS_HasReferenceTypes, // REF_NULL_EXNREF_S
8313 CEFBS_HasReferenceTypes, // REF_NULL_EXTERNREF
8314 CEFBS_HasReferenceTypes, // REF_NULL_EXTERNREF_S
8315 CEFBS_HasReferenceTypes, // REF_NULL_FUNCREF
8316 CEFBS_HasReferenceTypes, // REF_NULL_FUNCREF_S
8317 CEFBS_HasGC, // REF_TEST_FUNCREF
8318 CEFBS_HasGC, // REF_TEST_FUNCREF_S
8319 CEFBS_HasRelaxedSIMD, // RELAXED_DOT
8320 CEFBS_HasRelaxedSIMD, // RELAXED_DOT_ADD
8321 CEFBS_HasRelaxedSIMD, // RELAXED_DOT_ADD_S
8322 CEFBS_HasRelaxedSIMD, // RELAXED_DOT_BFLOAT
8323 CEFBS_HasRelaxedSIMD, // RELAXED_DOT_BFLOAT_S
8324 CEFBS_HasRelaxedSIMD, // RELAXED_DOT_S
8325 CEFBS_HasRelaxedSIMD, // RELAXED_Q15MULR_S_I16x8
8326 CEFBS_HasRelaxedSIMD, // RELAXED_Q15MULR_S_I16x8_S
8327 CEFBS_HasRelaxedSIMD, // RELAXED_SWIZZLE
8328 CEFBS_HasRelaxedSIMD, // RELAXED_SWIZZLE_S
8329 CEFBS_None, // REM_S_I32
8330 CEFBS_None, // REM_S_I32_S
8331 CEFBS_None, // REM_S_I64
8332 CEFBS_None, // REM_S_I64_S
8333 CEFBS_None, // REM_U_I32
8334 CEFBS_None, // REM_U_I32_S
8335 CEFBS_None, // REM_U_I64
8336 CEFBS_None, // REM_U_I64_S
8337 CEFBS_HasFP16, // REPLACE_LANE_F16x8
8338 CEFBS_HasFP16, // REPLACE_LANE_F16x8_S
8339 CEFBS_HasSIMD128, // REPLACE_LANE_F32x4
8340 CEFBS_HasSIMD128, // REPLACE_LANE_F32x4_S
8341 CEFBS_HasSIMD128, // REPLACE_LANE_F64x2
8342 CEFBS_HasSIMD128, // REPLACE_LANE_F64x2_S
8343 CEFBS_HasSIMD128, // REPLACE_LANE_I16x8
8344 CEFBS_HasSIMD128, // REPLACE_LANE_I16x8_S
8345 CEFBS_HasSIMD128, // REPLACE_LANE_I32x4
8346 CEFBS_HasSIMD128, // REPLACE_LANE_I32x4_S
8347 CEFBS_HasSIMD128, // REPLACE_LANE_I64x2
8348 CEFBS_HasSIMD128, // REPLACE_LANE_I64x2_S
8349 CEFBS_HasSIMD128, // REPLACE_LANE_I8x16
8350 CEFBS_HasSIMD128, // REPLACE_LANE_I8x16_S
8351 CEFBS_HasExceptionHandling, // RETHROW
8352 CEFBS_HasExceptionHandling, // RETHROW_S
8353 CEFBS_None, // RETURN
8354 CEFBS_None, // RETURN_S
8355 CEFBS_HasTailCall, // RET_CALL
8356 CEFBS_HasTailCall, // RET_CALL_INDIRECT
8357 CEFBS_HasTailCall, // RET_CALL_INDIRECT_S
8358 CEFBS_HasTailCall, // RET_CALL_S
8359 CEFBS_None, // ROTL_I32
8360 CEFBS_None, // ROTL_I32_S
8361 CEFBS_None, // ROTL_I64
8362 CEFBS_None, // ROTL_I64_S
8363 CEFBS_None, // ROTR_I32
8364 CEFBS_None, // ROTR_I32_S
8365 CEFBS_None, // ROTR_I64
8366 CEFBS_None, // ROTR_I64_S
8367 CEFBS_HasReferenceTypes, // SELECT_EXNREF
8368 CEFBS_HasReferenceTypes, // SELECT_EXNREF_S
8369 CEFBS_HasReferenceTypes, // SELECT_EXTERNREF
8370 CEFBS_HasReferenceTypes, // SELECT_EXTERNREF_S
8371 CEFBS_None, // SELECT_F32
8372 CEFBS_None, // SELECT_F32_S
8373 CEFBS_None, // SELECT_F64
8374 CEFBS_None, // SELECT_F64_S
8375 CEFBS_HasReferenceTypes, // SELECT_FUNCREF
8376 CEFBS_HasReferenceTypes, // SELECT_FUNCREF_S
8377 CEFBS_None, // SELECT_I32
8378 CEFBS_None, // SELECT_I32_S
8379 CEFBS_None, // SELECT_I64
8380 CEFBS_None, // SELECT_I64_S
8381 CEFBS_None, // SELECT_V128
8382 CEFBS_None, // SELECT_V128_S
8383 CEFBS_HasSIMD128, // SHL_I16x8
8384 CEFBS_HasSIMD128, // SHL_I16x8_S
8385 CEFBS_None, // SHL_I32
8386 CEFBS_None, // SHL_I32_S
8387 CEFBS_HasSIMD128, // SHL_I32x4
8388 CEFBS_HasSIMD128, // SHL_I32x4_S
8389 CEFBS_None, // SHL_I64
8390 CEFBS_None, // SHL_I64_S
8391 CEFBS_HasSIMD128, // SHL_I64x2
8392 CEFBS_HasSIMD128, // SHL_I64x2_S
8393 CEFBS_HasSIMD128, // SHL_I8x16
8394 CEFBS_HasSIMD128, // SHL_I8x16_S
8395 CEFBS_HasSIMD128, // SHR_S_I16x8
8396 CEFBS_HasSIMD128, // SHR_S_I16x8_S
8397 CEFBS_None, // SHR_S_I32
8398 CEFBS_None, // SHR_S_I32_S
8399 CEFBS_HasSIMD128, // SHR_S_I32x4
8400 CEFBS_HasSIMD128, // SHR_S_I32x4_S
8401 CEFBS_None, // SHR_S_I64
8402 CEFBS_None, // SHR_S_I64_S
8403 CEFBS_HasSIMD128, // SHR_S_I64x2
8404 CEFBS_HasSIMD128, // SHR_S_I64x2_S
8405 CEFBS_HasSIMD128, // SHR_S_I8x16
8406 CEFBS_HasSIMD128, // SHR_S_I8x16_S
8407 CEFBS_HasSIMD128, // SHR_U_I16x8
8408 CEFBS_HasSIMD128, // SHR_U_I16x8_S
8409 CEFBS_None, // SHR_U_I32
8410 CEFBS_None, // SHR_U_I32_S
8411 CEFBS_HasSIMD128, // SHR_U_I32x4
8412 CEFBS_HasSIMD128, // SHR_U_I32x4_S
8413 CEFBS_None, // SHR_U_I64
8414 CEFBS_None, // SHR_U_I64_S
8415 CEFBS_HasSIMD128, // SHR_U_I64x2
8416 CEFBS_HasSIMD128, // SHR_U_I64x2_S
8417 CEFBS_HasSIMD128, // SHR_U_I8x16
8418 CEFBS_HasSIMD128, // SHR_U_I8x16_S
8419 CEFBS_HasSIMD128, // SHUFFLE
8420 CEFBS_HasSIMD128, // SHUFFLE_S
8421 CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMAX_F32x4
8422 CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMAX_F32x4_S
8423 CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMAX_F64x2
8424 CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMAX_F64x2_S
8425 CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMIN_F32x4
8426 CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMIN_F32x4_S
8427 CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMIN_F64x2
8428 CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMIN_F64x2_S
8429 CEFBS_HasFP16, // SPLAT_F16x8
8430 CEFBS_HasFP16, // SPLAT_F16x8_S
8431 CEFBS_HasSIMD128, // SPLAT_F32x4
8432 CEFBS_HasSIMD128, // SPLAT_F32x4_S
8433 CEFBS_HasSIMD128, // SPLAT_F64x2
8434 CEFBS_HasSIMD128, // SPLAT_F64x2_S
8435 CEFBS_HasSIMD128, // SPLAT_I16x8
8436 CEFBS_HasSIMD128, // SPLAT_I16x8_S
8437 CEFBS_HasSIMD128, // SPLAT_I32x4
8438 CEFBS_HasSIMD128, // SPLAT_I32x4_S
8439 CEFBS_HasSIMD128, // SPLAT_I64x2
8440 CEFBS_HasSIMD128, // SPLAT_I64x2_S
8441 CEFBS_HasSIMD128, // SPLAT_I8x16
8442 CEFBS_HasSIMD128, // SPLAT_I8x16_S
8443 CEFBS_HasSIMD128_HasFP16, // SQRT_F16x8
8444 CEFBS_HasSIMD128_HasFP16, // SQRT_F16x8_S
8445 CEFBS_None, // SQRT_F32
8446 CEFBS_None, // SQRT_F32_S
8447 CEFBS_HasSIMD128, // SQRT_F32x4
8448 CEFBS_HasSIMD128, // SQRT_F32x4_S
8449 CEFBS_None, // SQRT_F64
8450 CEFBS_None, // SQRT_F64_S
8451 CEFBS_HasSIMD128, // SQRT_F64x2
8452 CEFBS_HasSIMD128, // SQRT_F64x2_S
8453 CEFBS_None, // STORE16_I32_A32
8454 CEFBS_None, // STORE16_I32_A32_S
8455 CEFBS_None, // STORE16_I32_A64
8456 CEFBS_None, // STORE16_I32_A64_S
8457 CEFBS_None, // STORE16_I64_A32
8458 CEFBS_None, // STORE16_I64_A32_S
8459 CEFBS_None, // STORE16_I64_A64
8460 CEFBS_None, // STORE16_I64_A64_S
8461 CEFBS_None, // STORE32_I64_A32
8462 CEFBS_None, // STORE32_I64_A32_S
8463 CEFBS_None, // STORE32_I64_A64
8464 CEFBS_None, // STORE32_I64_A64_S
8465 CEFBS_None, // STORE8_I32_A32
8466 CEFBS_None, // STORE8_I32_A32_S
8467 CEFBS_None, // STORE8_I32_A64
8468 CEFBS_None, // STORE8_I32_A64_S
8469 CEFBS_None, // STORE8_I64_A32
8470 CEFBS_None, // STORE8_I64_A32_S
8471 CEFBS_None, // STORE8_I64_A64
8472 CEFBS_None, // STORE8_I64_A64_S
8473 CEFBS_HasFP16, // STORE_F16_F32_A32
8474 CEFBS_HasFP16, // STORE_F16_F32_A32_S
8475 CEFBS_HasFP16, // STORE_F16_F32_A64
8476 CEFBS_HasFP16, // STORE_F16_F32_A64_S
8477 CEFBS_None, // STORE_F32_A32
8478 CEFBS_None, // STORE_F32_A32_S
8479 CEFBS_None, // STORE_F32_A64
8480 CEFBS_None, // STORE_F32_A64_S
8481 CEFBS_None, // STORE_F64_A32
8482 CEFBS_None, // STORE_F64_A32_S
8483 CEFBS_None, // STORE_F64_A64
8484 CEFBS_None, // STORE_F64_A64_S
8485 CEFBS_None, // STORE_I32_A32
8486 CEFBS_None, // STORE_I32_A32_S
8487 CEFBS_None, // STORE_I32_A64
8488 CEFBS_None, // STORE_I32_A64_S
8489 CEFBS_None, // STORE_I64_A32
8490 CEFBS_None, // STORE_I64_A32_S
8491 CEFBS_None, // STORE_I64_A64
8492 CEFBS_None, // STORE_I64_A64_S
8493 CEFBS_HasSIMD128, // STORE_LANE_I16x8_A32
8494 CEFBS_HasSIMD128, // STORE_LANE_I16x8_A32_S
8495 CEFBS_HasSIMD128, // STORE_LANE_I16x8_A64
8496 CEFBS_HasSIMD128, // STORE_LANE_I16x8_A64_S
8497 CEFBS_HasSIMD128, // STORE_LANE_I32x4_A32
8498 CEFBS_HasSIMD128, // STORE_LANE_I32x4_A32_S
8499 CEFBS_HasSIMD128, // STORE_LANE_I32x4_A64
8500 CEFBS_HasSIMD128, // STORE_LANE_I32x4_A64_S
8501 CEFBS_HasSIMD128, // STORE_LANE_I64x2_A32
8502 CEFBS_HasSIMD128, // STORE_LANE_I64x2_A32_S
8503 CEFBS_HasSIMD128, // STORE_LANE_I64x2_A64
8504 CEFBS_HasSIMD128, // STORE_LANE_I64x2_A64_S
8505 CEFBS_HasSIMD128, // STORE_LANE_I8x16_A32
8506 CEFBS_HasSIMD128, // STORE_LANE_I8x16_A32_S
8507 CEFBS_HasSIMD128, // STORE_LANE_I8x16_A64
8508 CEFBS_HasSIMD128, // STORE_LANE_I8x16_A64_S
8509 CEFBS_HasSIMD128, // STORE_V128_A32
8510 CEFBS_HasSIMD128, // STORE_V128_A32_S
8511 CEFBS_HasSIMD128, // STORE_V128_A64
8512 CEFBS_HasSIMD128, // STORE_V128_A64_S
8513 CEFBS_HasSIMD128_HasFP16, // SUB_F16x8
8514 CEFBS_HasSIMD128_HasFP16, // SUB_F16x8_S
8515 CEFBS_None, // SUB_F32
8516 CEFBS_None, // SUB_F32_S
8517 CEFBS_HasSIMD128, // SUB_F32x4
8518 CEFBS_HasSIMD128, // SUB_F32x4_S
8519 CEFBS_None, // SUB_F64
8520 CEFBS_None, // SUB_F64_S
8521 CEFBS_HasSIMD128, // SUB_F64x2
8522 CEFBS_HasSIMD128, // SUB_F64x2_S
8523 CEFBS_HasSIMD128, // SUB_I16x8
8524 CEFBS_HasSIMD128, // SUB_I16x8_S
8525 CEFBS_None, // SUB_I32
8526 CEFBS_None, // SUB_I32_S
8527 CEFBS_HasSIMD128, // SUB_I32x4
8528 CEFBS_HasSIMD128, // SUB_I32x4_S
8529 CEFBS_None, // SUB_I64
8530 CEFBS_None, // SUB_I64_S
8531 CEFBS_HasSIMD128, // SUB_I64x2
8532 CEFBS_HasSIMD128, // SUB_I64x2_S
8533 CEFBS_HasSIMD128, // SUB_I8x16
8534 CEFBS_HasSIMD128, // SUB_I8x16_S
8535 CEFBS_HasSIMD128, // SUB_SAT_S_I16x8
8536 CEFBS_HasSIMD128, // SUB_SAT_S_I16x8_S
8537 CEFBS_HasSIMD128, // SUB_SAT_S_I8x16
8538 CEFBS_HasSIMD128, // SUB_SAT_S_I8x16_S
8539 CEFBS_HasSIMD128, // SUB_SAT_U_I16x8
8540 CEFBS_HasSIMD128, // SUB_SAT_U_I16x8_S
8541 CEFBS_HasSIMD128, // SUB_SAT_U_I8x16
8542 CEFBS_HasSIMD128, // SUB_SAT_U_I8x16_S
8543 CEFBS_HasSIMD128, // SWIZZLE
8544 CEFBS_HasSIMD128, // SWIZZLE_S
8545 CEFBS_HasReferenceTypes, // TABLE_COPY
8546 CEFBS_HasReferenceTypes, // TABLE_COPY_S
8547 CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_FILL_EXNREF
8548 CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_FILL_EXNREF_S
8549 CEFBS_HasReferenceTypes, // TABLE_FILL_EXTERNREF
8550 CEFBS_HasReferenceTypes, // TABLE_FILL_EXTERNREF_S
8551 CEFBS_HasReferenceTypes, // TABLE_FILL_FUNCREF
8552 CEFBS_HasReferenceTypes, // TABLE_FILL_FUNCREF_S
8553 CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_GET_EXNREF
8554 CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_GET_EXNREF_S
8555 CEFBS_HasReferenceTypes, // TABLE_GET_EXTERNREF
8556 CEFBS_HasReferenceTypes, // TABLE_GET_EXTERNREF_S
8557 CEFBS_HasReferenceTypes, // TABLE_GET_FUNCREF
8558 CEFBS_HasReferenceTypes, // TABLE_GET_FUNCREF_S
8559 CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_GROW_EXNREF
8560 CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_GROW_EXNREF_S
8561 CEFBS_HasReferenceTypes, // TABLE_GROW_EXTERNREF
8562 CEFBS_HasReferenceTypes, // TABLE_GROW_EXTERNREF_S
8563 CEFBS_HasReferenceTypes, // TABLE_GROW_FUNCREF
8564 CEFBS_HasReferenceTypes, // TABLE_GROW_FUNCREF_S
8565 CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_SET_EXNREF
8566 CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_SET_EXNREF_S
8567 CEFBS_HasReferenceTypes, // TABLE_SET_EXTERNREF
8568 CEFBS_HasReferenceTypes, // TABLE_SET_EXTERNREF_S
8569 CEFBS_HasReferenceTypes, // TABLE_SET_FUNCREF
8570 CEFBS_HasReferenceTypes, // TABLE_SET_FUNCREF_S
8571 CEFBS_HasReferenceTypes, // TABLE_SIZE
8572 CEFBS_HasReferenceTypes, // TABLE_SIZE_S
8573 CEFBS_HasReferenceTypes_HasExceptionHandling, // TEE_EXNREF
8574 CEFBS_HasReferenceTypes_HasExceptionHandling, // TEE_EXNREF_S
8575 CEFBS_HasReferenceTypes, // TEE_EXTERNREF
8576 CEFBS_HasReferenceTypes, // TEE_EXTERNREF_S
8577 CEFBS_None, // TEE_F32
8578 CEFBS_None, // TEE_F32_S
8579 CEFBS_None, // TEE_F64
8580 CEFBS_None, // TEE_F64_S
8581 CEFBS_HasReferenceTypes, // TEE_FUNCREF
8582 CEFBS_HasReferenceTypes, // TEE_FUNCREF_S
8583 CEFBS_None, // TEE_I32
8584 CEFBS_None, // TEE_I32_S
8585 CEFBS_None, // TEE_I64
8586 CEFBS_None, // TEE_I64_S
8587 CEFBS_HasSIMD128, // TEE_V128
8588 CEFBS_HasSIMD128, // TEE_V128_S
8589 CEFBS_HasExceptionHandling, // THROW
8590 CEFBS_HasExceptionHandling, // THROW_REF
8591 CEFBS_HasExceptionHandling, // THROW_REF_S
8592 CEFBS_HasExceptionHandling, // THROW_S
8593 CEFBS_HasSIMD128_HasFP16, // TRUNC_F16x8
8594 CEFBS_HasSIMD128_HasFP16, // TRUNC_F16x8_S
8595 CEFBS_None, // TRUNC_F32
8596 CEFBS_None, // TRUNC_F32_S
8597 CEFBS_HasSIMD128, // TRUNC_F32x4
8598 CEFBS_HasSIMD128, // TRUNC_F32x4_S
8599 CEFBS_None, // TRUNC_F64
8600 CEFBS_None, // TRUNC_F64_S
8601 CEFBS_HasSIMD128, // TRUNC_F64x2
8602 CEFBS_HasSIMD128, // TRUNC_F64x2_S
8603 CEFBS_HasExceptionHandling, // TRY
8604 CEFBS_HasExceptionHandling, // TRY_S
8605 CEFBS_HasExceptionHandling, // TRY_TABLE
8606 CEFBS_HasExceptionHandling, // TRY_TABLE_S
8607 CEFBS_None, // UNREACHABLE
8608 CEFBS_None, // UNREACHABLE_S
8609 CEFBS_HasSIMD128, // XOR
8610 CEFBS_None, // XOR_I32
8611 CEFBS_None, // XOR_I32_S
8612 CEFBS_None, // XOR_I64
8613 CEFBS_None, // XOR_I64_S
8614 CEFBS_HasSIMD128, // XOR_S
8615 CEFBS_None, // anonymous_14734MEMORY_GROW_A32
8616 CEFBS_None, // anonymous_14734MEMORY_GROW_A32_S
8617 CEFBS_None, // anonymous_14734MEMORY_SIZE_A32
8618 CEFBS_None, // anonymous_14734MEMORY_SIZE_A32_S
8619 CEFBS_None, // anonymous_14735MEMORY_GROW_A64
8620 CEFBS_None, // anonymous_14735MEMORY_GROW_A64_S
8621 CEFBS_None, // anonymous_14735MEMORY_SIZE_A64
8622 CEFBS_None, // anonymous_14735MEMORY_SIZE_A64_S
8623 CEFBS_HasSIMD128, // convert_low_s_F64x2
8624 CEFBS_HasSIMD128, // convert_low_s_F64x2_S
8625 CEFBS_HasSIMD128, // convert_low_u_F64x2
8626 CEFBS_HasSIMD128, // convert_low_u_F64x2_S
8627 CEFBS_HasSIMD128, // demote_zero_F32x4
8628 CEFBS_HasSIMD128, // demote_zero_F32x4_S
8629 CEFBS_HasSIMD128, // extadd_pairwise_s_I16x8
8630 CEFBS_HasSIMD128, // extadd_pairwise_s_I16x8_S
8631 CEFBS_HasSIMD128, // extadd_pairwise_s_I32x4
8632 CEFBS_HasSIMD128, // extadd_pairwise_s_I32x4_S
8633 CEFBS_HasSIMD128, // extadd_pairwise_u_I16x8
8634 CEFBS_HasSIMD128, // extadd_pairwise_u_I16x8_S
8635 CEFBS_HasSIMD128, // extadd_pairwise_u_I32x4
8636 CEFBS_HasSIMD128, // extadd_pairwise_u_I32x4_S
8637 CEFBS_HasSIMD128, // extend_high_s_I16x8
8638 CEFBS_HasSIMD128, // extend_high_s_I16x8_S
8639 CEFBS_HasSIMD128, // extend_high_s_I32x4
8640 CEFBS_HasSIMD128, // extend_high_s_I32x4_S
8641 CEFBS_HasSIMD128, // extend_high_s_I64x2
8642 CEFBS_HasSIMD128, // extend_high_s_I64x2_S
8643 CEFBS_HasSIMD128, // extend_high_u_I16x8
8644 CEFBS_HasSIMD128, // extend_high_u_I16x8_S
8645 CEFBS_HasSIMD128, // extend_high_u_I32x4
8646 CEFBS_HasSIMD128, // extend_high_u_I32x4_S
8647 CEFBS_HasSIMD128, // extend_high_u_I64x2
8648 CEFBS_HasSIMD128, // extend_high_u_I64x2_S
8649 CEFBS_HasSIMD128, // extend_low_s_I16x8
8650 CEFBS_HasSIMD128, // extend_low_s_I16x8_S
8651 CEFBS_HasSIMD128, // extend_low_s_I32x4
8652 CEFBS_HasSIMD128, // extend_low_s_I32x4_S
8653 CEFBS_HasSIMD128, // extend_low_s_I64x2
8654 CEFBS_HasSIMD128, // extend_low_s_I64x2_S
8655 CEFBS_HasSIMD128, // extend_low_u_I16x8
8656 CEFBS_HasSIMD128, // extend_low_u_I16x8_S
8657 CEFBS_HasSIMD128, // extend_low_u_I32x4
8658 CEFBS_HasSIMD128, // extend_low_u_I32x4_S
8659 CEFBS_HasSIMD128, // extend_low_u_I64x2
8660 CEFBS_HasSIMD128, // extend_low_u_I64x2_S
8661 CEFBS_HasSIMD128_HasFP16, // fp_to_sint_I16x8
8662 CEFBS_HasSIMD128_HasFP16, // fp_to_sint_I16x8_S
8663 CEFBS_HasSIMD128, // fp_to_sint_I32x4
8664 CEFBS_HasSIMD128, // fp_to_sint_I32x4_S
8665 CEFBS_HasSIMD128_HasFP16, // fp_to_uint_I16x8
8666 CEFBS_HasSIMD128_HasFP16, // fp_to_uint_I16x8_S
8667 CEFBS_HasSIMD128, // fp_to_uint_I32x4
8668 CEFBS_HasSIMD128, // fp_to_uint_I32x4_S
8669 CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_signed_I32x4
8670 CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_signed_I32x4_S
8671 CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_signed_zero_I32x4
8672 CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_signed_zero_I32x4_S
8673 CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_unsigned_I32x4
8674 CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_unsigned_I32x4_S
8675 CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_unsigned_zero_I32x4
8676 CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_unsigned_zero_I32x4_S
8677 CEFBS_HasSIMD128, // promote_low_F64x2
8678 CEFBS_HasSIMD128, // promote_low_F64x2_S
8679 CEFBS_HasSIMD128_HasFP16, // sint_to_fp_F16x8
8680 CEFBS_HasSIMD128_HasFP16, // sint_to_fp_F16x8_S
8681 CEFBS_HasSIMD128, // sint_to_fp_F32x4
8682 CEFBS_HasSIMD128, // sint_to_fp_F32x4_S
8683 CEFBS_HasSIMD128, // trunc_sat_zero_s_I32x4
8684 CEFBS_HasSIMD128, // trunc_sat_zero_s_I32x4_S
8685 CEFBS_HasSIMD128, // trunc_sat_zero_u_I32x4
8686 CEFBS_HasSIMD128, // trunc_sat_zero_u_I32x4_S
8687 CEFBS_HasSIMD128_HasFP16, // uint_to_fp_F16x8
8688 CEFBS_HasSIMD128_HasFP16, // uint_to_fp_F16x8_S
8689 CEFBS_HasSIMD128, // uint_to_fp_F32x4
8690 CEFBS_HasSIMD128, // uint_to_fp_F32x4_S
8691 };
8692
8693 assert(Opcode < 1957);
8694 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
8695}
8696
8697
8698} // namespace llvm::WebAssembly_MC
8699
8700#endif // GET_COMPUTE_FEATURES
8701
8702#ifdef GET_AVAILABLE_OPCODE_CHECKER
8703#undef GET_AVAILABLE_OPCODE_CHECKER
8704
8705namespace llvm::WebAssembly_MC {
8706
8707bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
8708 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
8709 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
8710 FeatureBitset MissingFeatures =
8711 (AvailableFeatures & RequiredFeatures) ^
8712 RequiredFeatures;
8713 return !MissingFeatures.any();
8714}
8715
8716} // namespace llvm::WebAssembly_MC
8717
8718#endif // GET_AVAILABLE_OPCODE_CHECKER
8719
8720#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
8721#undef ENABLE_INSTR_PREDICATE_VERIFIER
8722
8723#include <sstream>
8724
8725namespace llvm::WebAssembly_MC {
8726
8727#ifndef NDEBUG
8728static const char *SubtargetFeatureNames[] = {
8729 "Feature_HasAtomics",
8730 "Feature_HasBulkMemory",
8731 "Feature_HasBulkMemoryOpt",
8732 "Feature_HasCallIndirectOverlong",
8733 "Feature_HasExceptionHandling",
8734 "Feature_HasExtendedConst",
8735 "Feature_HasFP16",
8736 "Feature_HasGC",
8737 "Feature_HasMultiMemory",
8738 "Feature_HasMultivalue",
8739 "Feature_HasMutableGlobals",
8740 "Feature_HasNontrappingFPToInt",
8741 "Feature_HasReferenceTypes",
8742 "Feature_HasRelaxedSIMD",
8743 "Feature_HasSIMD128",
8744 "Feature_HasSignExt",
8745 "Feature_HasTailCall",
8746 "Feature_HasWideArithmetic",
8747 "Feature_NotHasNontrappingFPToInt",
8748 nullptr
8749};
8750
8751#endif // NDEBUG
8752
8753void verifyInstructionPredicates(
8754 unsigned Opcode, const FeatureBitset &Features) {
8755#ifndef NDEBUG
8756 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
8757 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
8758 FeatureBitset MissingFeatures =
8759 (AvailableFeatures & RequiredFeatures) ^
8760 RequiredFeatures;
8761 if (MissingFeatures.any()) {
8762 std::ostringstream Msg;
8763 Msg << "Attempting to emit " << &WebAssemblyInstrNameData[WebAssemblyInstrNameIndices[Opcode]]
8764 << " instruction but the ";
8765 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
8766 if (MissingFeatures.test(i))
8767 Msg << SubtargetFeatureNames[i] << " ";
8768 Msg << "predicate(s) are not met";
8769 report_fatal_error(Msg.str().c_str());
8770 }
8771#endif // NDEBUG
8772}
8773
8774} // namespace llvm::WebAssembly_MC
8775
8776#endif // ENABLE_INSTR_PREDICATE_VERIFIER
8777
8778#ifdef GET_INSTRMAP_INFO
8779#undef GET_INSTRMAP_INFO
8780
8781namespace llvm::WebAssembly {
8782
8783enum IsWasm64 {
8784 IsWasm64_1
8785};
8786
8787enum StackBased {
8788 StackBased_0,
8789 StackBased_1
8790};
8791
8792// getRegisterOpcode
8793LLVM_READONLY
8794int getRegisterOpcode(uint16_t Opcode) {
8795 using namespace WebAssembly;
8796 static constexpr uint16_t Table[][2] = {
8797 { CALL_PARAMS_S, CALL_PARAMS },
8798 { CALL_RESULTS_S, CALL_RESULTS },
8799 { CATCHRET_S, CATCHRET },
8800 { CLEANUPRET_S, CLEANUPRET },
8801 { COMPILER_FENCE_S, COMPILER_FENCE },
8802 { RET_CALL_RESULTS_S, RET_CALL_RESULTS },
8803 { ABS_F16x8_S, ABS_F16x8 },
8804 { ABS_F32_S, ABS_F32 },
8805 { ABS_F32x4_S, ABS_F32x4 },
8806 { ABS_F64_S, ABS_F64 },
8807 { ABS_F64x2_S, ABS_F64x2 },
8808 { ABS_I16x8_S, ABS_I16x8 },
8809 { ABS_I32x4_S, ABS_I32x4 },
8810 { ABS_I64x2_S, ABS_I64x2 },
8811 { ABS_I8x16_S, ABS_I8x16 },
8812 { ADD_F16x8_S, ADD_F16x8 },
8813 { ADD_F32_S, ADD_F32 },
8814 { ADD_F32x4_S, ADD_F32x4 },
8815 { ADD_F64_S, ADD_F64 },
8816 { ADD_F64x2_S, ADD_F64x2 },
8817 { ADD_I16x8_S, ADD_I16x8 },
8818 { ADD_I32_S, ADD_I32 },
8819 { ADD_I32x4_S, ADD_I32x4 },
8820 { ADD_I64_S, ADD_I64 },
8821 { ADD_I64x2_S, ADD_I64x2 },
8822 { ADD_I8x16_S, ADD_I8x16 },
8823 { ADD_SAT_S_I16x8_S, ADD_SAT_S_I16x8 },
8824 { ADD_SAT_S_I8x16_S, ADD_SAT_S_I8x16 },
8825 { ADD_SAT_U_I16x8_S, ADD_SAT_U_I16x8 },
8826 { ADD_SAT_U_I8x16_S, ADD_SAT_U_I8x16 },
8827 { ADJCALLSTACKDOWN_S, ADJCALLSTACKDOWN },
8828 { ADJCALLSTACKUP_S, ADJCALLSTACKUP },
8829 { ALLTRUE_I16x8_S, ALLTRUE_I16x8 },
8830 { ALLTRUE_I32x4_S, ALLTRUE_I32x4 },
8831 { ALLTRUE_I64x2_S, ALLTRUE_I64x2 },
8832 { ALLTRUE_I8x16_S, ALLTRUE_I8x16 },
8833 { ANDNOT_S, ANDNOT },
8834 { AND_I32_S, AND_I32 },
8835 { AND_I64_S, AND_I64 },
8836 { AND_S, AND },
8837 { ANYTRUE_S, ANYTRUE },
8838 { ARGUMENT_exnref_S, ARGUMENT_exnref },
8839 { ARGUMENT_externref_S, ARGUMENT_externref },
8840 { ARGUMENT_f32_S, ARGUMENT_f32 },
8841 { ARGUMENT_f64_S, ARGUMENT_f64 },
8842 { ARGUMENT_funcref_S, ARGUMENT_funcref },
8843 { ARGUMENT_i32_S, ARGUMENT_i32 },
8844 { ARGUMENT_i64_S, ARGUMENT_i64 },
8845 { ARGUMENT_v16i8_S, ARGUMENT_v16i8 },
8846 { ARGUMENT_v2f64_S, ARGUMENT_v2f64 },
8847 { ARGUMENT_v2i64_S, ARGUMENT_v2i64 },
8848 { ARGUMENT_v4f32_S, ARGUMENT_v4f32 },
8849 { ARGUMENT_v4i32_S, ARGUMENT_v4i32 },
8850 { ARGUMENT_v8f16_S, ARGUMENT_v8f16 },
8851 { ARGUMENT_v8i16_S, ARGUMENT_v8i16 },
8852 { ATOMIC_FENCE_S, ATOMIC_FENCE },
8853 { ATOMIC_LOAD16_U_I32_A32_S, ATOMIC_LOAD16_U_I32_A32 },
8854 { ATOMIC_LOAD16_U_I32_A64_S, ATOMIC_LOAD16_U_I32_A64 },
8855 { ATOMIC_LOAD16_U_I64_A32_S, ATOMIC_LOAD16_U_I64_A32 },
8856 { ATOMIC_LOAD16_U_I64_A64_S, ATOMIC_LOAD16_U_I64_A64 },
8857 { ATOMIC_LOAD32_U_I64_A32_S, ATOMIC_LOAD32_U_I64_A32 },
8858 { ATOMIC_LOAD32_U_I64_A64_S, ATOMIC_LOAD32_U_I64_A64 },
8859 { ATOMIC_LOAD8_U_I32_A32_S, ATOMIC_LOAD8_U_I32_A32 },
8860 { ATOMIC_LOAD8_U_I32_A64_S, ATOMIC_LOAD8_U_I32_A64 },
8861 { ATOMIC_LOAD8_U_I64_A32_S, ATOMIC_LOAD8_U_I64_A32 },
8862 { ATOMIC_LOAD8_U_I64_A64_S, ATOMIC_LOAD8_U_I64_A64 },
8863 { ATOMIC_LOAD_I32_A32_S, ATOMIC_LOAD_I32_A32 },
8864 { ATOMIC_LOAD_I32_A64_S, ATOMIC_LOAD_I32_A64 },
8865 { ATOMIC_LOAD_I64_A32_S, ATOMIC_LOAD_I64_A32 },
8866 { ATOMIC_LOAD_I64_A64_S, ATOMIC_LOAD_I64_A64 },
8867 { ATOMIC_RMW16_U_ADD_I32_A32_S, ATOMIC_RMW16_U_ADD_I32_A32 },
8868 { ATOMIC_RMW16_U_ADD_I32_A64_S, ATOMIC_RMW16_U_ADD_I32_A64 },
8869 { ATOMIC_RMW16_U_ADD_I64_A32_S, ATOMIC_RMW16_U_ADD_I64_A32 },
8870 { ATOMIC_RMW16_U_ADD_I64_A64_S, ATOMIC_RMW16_U_ADD_I64_A64 },
8871 { ATOMIC_RMW16_U_AND_I32_A32_S, ATOMIC_RMW16_U_AND_I32_A32 },
8872 { ATOMIC_RMW16_U_AND_I32_A64_S, ATOMIC_RMW16_U_AND_I32_A64 },
8873 { ATOMIC_RMW16_U_AND_I64_A32_S, ATOMIC_RMW16_U_AND_I64_A32 },
8874 { ATOMIC_RMW16_U_AND_I64_A64_S, ATOMIC_RMW16_U_AND_I64_A64 },
8875 { ATOMIC_RMW16_U_CMPXCHG_I32_A32_S, ATOMIC_RMW16_U_CMPXCHG_I32_A32 },
8876 { ATOMIC_RMW16_U_CMPXCHG_I32_A64_S, ATOMIC_RMW16_U_CMPXCHG_I32_A64 },
8877 { ATOMIC_RMW16_U_CMPXCHG_I64_A32_S, ATOMIC_RMW16_U_CMPXCHG_I64_A32 },
8878 { ATOMIC_RMW16_U_CMPXCHG_I64_A64_S, ATOMIC_RMW16_U_CMPXCHG_I64_A64 },
8879 { ATOMIC_RMW16_U_OR_I32_A32_S, ATOMIC_RMW16_U_OR_I32_A32 },
8880 { ATOMIC_RMW16_U_OR_I32_A64_S, ATOMIC_RMW16_U_OR_I32_A64 },
8881 { ATOMIC_RMW16_U_OR_I64_A32_S, ATOMIC_RMW16_U_OR_I64_A32 },
8882 { ATOMIC_RMW16_U_OR_I64_A64_S, ATOMIC_RMW16_U_OR_I64_A64 },
8883 { ATOMIC_RMW16_U_SUB_I32_A32_S, ATOMIC_RMW16_U_SUB_I32_A32 },
8884 { ATOMIC_RMW16_U_SUB_I32_A64_S, ATOMIC_RMW16_U_SUB_I32_A64 },
8885 { ATOMIC_RMW16_U_SUB_I64_A32_S, ATOMIC_RMW16_U_SUB_I64_A32 },
8886 { ATOMIC_RMW16_U_SUB_I64_A64_S, ATOMIC_RMW16_U_SUB_I64_A64 },
8887 { ATOMIC_RMW16_U_XCHG_I32_A32_S, ATOMIC_RMW16_U_XCHG_I32_A32 },
8888 { ATOMIC_RMW16_U_XCHG_I32_A64_S, ATOMIC_RMW16_U_XCHG_I32_A64 },
8889 { ATOMIC_RMW16_U_XCHG_I64_A32_S, ATOMIC_RMW16_U_XCHG_I64_A32 },
8890 { ATOMIC_RMW16_U_XCHG_I64_A64_S, ATOMIC_RMW16_U_XCHG_I64_A64 },
8891 { ATOMIC_RMW16_U_XOR_I32_A32_S, ATOMIC_RMW16_U_XOR_I32_A32 },
8892 { ATOMIC_RMW16_U_XOR_I32_A64_S, ATOMIC_RMW16_U_XOR_I32_A64 },
8893 { ATOMIC_RMW16_U_XOR_I64_A32_S, ATOMIC_RMW16_U_XOR_I64_A32 },
8894 { ATOMIC_RMW16_U_XOR_I64_A64_S, ATOMIC_RMW16_U_XOR_I64_A64 },
8895 { ATOMIC_RMW32_U_ADD_I64_A32_S, ATOMIC_RMW32_U_ADD_I64_A32 },
8896 { ATOMIC_RMW32_U_ADD_I64_A64_S, ATOMIC_RMW32_U_ADD_I64_A64 },
8897 { ATOMIC_RMW32_U_AND_I64_A32_S, ATOMIC_RMW32_U_AND_I64_A32 },
8898 { ATOMIC_RMW32_U_AND_I64_A64_S, ATOMIC_RMW32_U_AND_I64_A64 },
8899 { ATOMIC_RMW32_U_CMPXCHG_I64_A32_S, ATOMIC_RMW32_U_CMPXCHG_I64_A32 },
8900 { ATOMIC_RMW32_U_CMPXCHG_I64_A64_S, ATOMIC_RMW32_U_CMPXCHG_I64_A64 },
8901 { ATOMIC_RMW32_U_OR_I64_A32_S, ATOMIC_RMW32_U_OR_I64_A32 },
8902 { ATOMIC_RMW32_U_OR_I64_A64_S, ATOMIC_RMW32_U_OR_I64_A64 },
8903 { ATOMIC_RMW32_U_SUB_I64_A32_S, ATOMIC_RMW32_U_SUB_I64_A32 },
8904 { ATOMIC_RMW32_U_SUB_I64_A64_S, ATOMIC_RMW32_U_SUB_I64_A64 },
8905 { ATOMIC_RMW32_U_XCHG_I64_A32_S, ATOMIC_RMW32_U_XCHG_I64_A32 },
8906 { ATOMIC_RMW32_U_XCHG_I64_A64_S, ATOMIC_RMW32_U_XCHG_I64_A64 },
8907 { ATOMIC_RMW32_U_XOR_I64_A32_S, ATOMIC_RMW32_U_XOR_I64_A32 },
8908 { ATOMIC_RMW32_U_XOR_I64_A64_S, ATOMIC_RMW32_U_XOR_I64_A64 },
8909 { ATOMIC_RMW8_U_ADD_I32_A32_S, ATOMIC_RMW8_U_ADD_I32_A32 },
8910 { ATOMIC_RMW8_U_ADD_I32_A64_S, ATOMIC_RMW8_U_ADD_I32_A64 },
8911 { ATOMIC_RMW8_U_ADD_I64_A32_S, ATOMIC_RMW8_U_ADD_I64_A32 },
8912 { ATOMIC_RMW8_U_ADD_I64_A64_S, ATOMIC_RMW8_U_ADD_I64_A64 },
8913 { ATOMIC_RMW8_U_AND_I32_A32_S, ATOMIC_RMW8_U_AND_I32_A32 },
8914 { ATOMIC_RMW8_U_AND_I32_A64_S, ATOMIC_RMW8_U_AND_I32_A64 },
8915 { ATOMIC_RMW8_U_AND_I64_A32_S, ATOMIC_RMW8_U_AND_I64_A32 },
8916 { ATOMIC_RMW8_U_AND_I64_A64_S, ATOMIC_RMW8_U_AND_I64_A64 },
8917 { ATOMIC_RMW8_U_CMPXCHG_I32_A32_S, ATOMIC_RMW8_U_CMPXCHG_I32_A32 },
8918 { ATOMIC_RMW8_U_CMPXCHG_I32_A64_S, ATOMIC_RMW8_U_CMPXCHG_I32_A64 },
8919 { ATOMIC_RMW8_U_CMPXCHG_I64_A32_S, ATOMIC_RMW8_U_CMPXCHG_I64_A32 },
8920 { ATOMIC_RMW8_U_CMPXCHG_I64_A64_S, ATOMIC_RMW8_U_CMPXCHG_I64_A64 },
8921 { ATOMIC_RMW8_U_OR_I32_A32_S, ATOMIC_RMW8_U_OR_I32_A32 },
8922 { ATOMIC_RMW8_U_OR_I32_A64_S, ATOMIC_RMW8_U_OR_I32_A64 },
8923 { ATOMIC_RMW8_U_OR_I64_A32_S, ATOMIC_RMW8_U_OR_I64_A32 },
8924 { ATOMIC_RMW8_U_OR_I64_A64_S, ATOMIC_RMW8_U_OR_I64_A64 },
8925 { ATOMIC_RMW8_U_SUB_I32_A32_S, ATOMIC_RMW8_U_SUB_I32_A32 },
8926 { ATOMIC_RMW8_U_SUB_I32_A64_S, ATOMIC_RMW8_U_SUB_I32_A64 },
8927 { ATOMIC_RMW8_U_SUB_I64_A32_S, ATOMIC_RMW8_U_SUB_I64_A32 },
8928 { ATOMIC_RMW8_U_SUB_I64_A64_S, ATOMIC_RMW8_U_SUB_I64_A64 },
8929 { ATOMIC_RMW8_U_XCHG_I32_A32_S, ATOMIC_RMW8_U_XCHG_I32_A32 },
8930 { ATOMIC_RMW8_U_XCHG_I32_A64_S, ATOMIC_RMW8_U_XCHG_I32_A64 },
8931 { ATOMIC_RMW8_U_XCHG_I64_A32_S, ATOMIC_RMW8_U_XCHG_I64_A32 },
8932 { ATOMIC_RMW8_U_XCHG_I64_A64_S, ATOMIC_RMW8_U_XCHG_I64_A64 },
8933 { ATOMIC_RMW8_U_XOR_I32_A32_S, ATOMIC_RMW8_U_XOR_I32_A32 },
8934 { ATOMIC_RMW8_U_XOR_I32_A64_S, ATOMIC_RMW8_U_XOR_I32_A64 },
8935 { ATOMIC_RMW8_U_XOR_I64_A32_S, ATOMIC_RMW8_U_XOR_I64_A32 },
8936 { ATOMIC_RMW8_U_XOR_I64_A64_S, ATOMIC_RMW8_U_XOR_I64_A64 },
8937 { ATOMIC_RMW_ADD_I32_A32_S, ATOMIC_RMW_ADD_I32_A32 },
8938 { ATOMIC_RMW_ADD_I32_A64_S, ATOMIC_RMW_ADD_I32_A64 },
8939 { ATOMIC_RMW_ADD_I64_A32_S, ATOMIC_RMW_ADD_I64_A32 },
8940 { ATOMIC_RMW_ADD_I64_A64_S, ATOMIC_RMW_ADD_I64_A64 },
8941 { ATOMIC_RMW_AND_I32_A32_S, ATOMIC_RMW_AND_I32_A32 },
8942 { ATOMIC_RMW_AND_I32_A64_S, ATOMIC_RMW_AND_I32_A64 },
8943 { ATOMIC_RMW_AND_I64_A32_S, ATOMIC_RMW_AND_I64_A32 },
8944 { ATOMIC_RMW_AND_I64_A64_S, ATOMIC_RMW_AND_I64_A64 },
8945 { ATOMIC_RMW_CMPXCHG_I32_A32_S, ATOMIC_RMW_CMPXCHG_I32_A32 },
8946 { ATOMIC_RMW_CMPXCHG_I32_A64_S, ATOMIC_RMW_CMPXCHG_I32_A64 },
8947 { ATOMIC_RMW_CMPXCHG_I64_A32_S, ATOMIC_RMW_CMPXCHG_I64_A32 },
8948 { ATOMIC_RMW_CMPXCHG_I64_A64_S, ATOMIC_RMW_CMPXCHG_I64_A64 },
8949 { ATOMIC_RMW_OR_I32_A32_S, ATOMIC_RMW_OR_I32_A32 },
8950 { ATOMIC_RMW_OR_I32_A64_S, ATOMIC_RMW_OR_I32_A64 },
8951 { ATOMIC_RMW_OR_I64_A32_S, ATOMIC_RMW_OR_I64_A32 },
8952 { ATOMIC_RMW_OR_I64_A64_S, ATOMIC_RMW_OR_I64_A64 },
8953 { ATOMIC_RMW_SUB_I32_A32_S, ATOMIC_RMW_SUB_I32_A32 },
8954 { ATOMIC_RMW_SUB_I32_A64_S, ATOMIC_RMW_SUB_I32_A64 },
8955 { ATOMIC_RMW_SUB_I64_A32_S, ATOMIC_RMW_SUB_I64_A32 },
8956 { ATOMIC_RMW_SUB_I64_A64_S, ATOMIC_RMW_SUB_I64_A64 },
8957 { ATOMIC_RMW_XCHG_I32_A32_S, ATOMIC_RMW_XCHG_I32_A32 },
8958 { ATOMIC_RMW_XCHG_I32_A64_S, ATOMIC_RMW_XCHG_I32_A64 },
8959 { ATOMIC_RMW_XCHG_I64_A32_S, ATOMIC_RMW_XCHG_I64_A32 },
8960 { ATOMIC_RMW_XCHG_I64_A64_S, ATOMIC_RMW_XCHG_I64_A64 },
8961 { ATOMIC_RMW_XOR_I32_A32_S, ATOMIC_RMW_XOR_I32_A32 },
8962 { ATOMIC_RMW_XOR_I32_A64_S, ATOMIC_RMW_XOR_I32_A64 },
8963 { ATOMIC_RMW_XOR_I64_A32_S, ATOMIC_RMW_XOR_I64_A32 },
8964 { ATOMIC_RMW_XOR_I64_A64_S, ATOMIC_RMW_XOR_I64_A64 },
8965 { ATOMIC_STORE16_I32_A32_S, ATOMIC_STORE16_I32_A32 },
8966 { ATOMIC_STORE16_I32_A64_S, ATOMIC_STORE16_I32_A64 },
8967 { ATOMIC_STORE16_I64_A32_S, ATOMIC_STORE16_I64_A32 },
8968 { ATOMIC_STORE16_I64_A64_S, ATOMIC_STORE16_I64_A64 },
8969 { ATOMIC_STORE32_I64_A32_S, ATOMIC_STORE32_I64_A32 },
8970 { ATOMIC_STORE32_I64_A64_S, ATOMIC_STORE32_I64_A64 },
8971 { ATOMIC_STORE8_I32_A32_S, ATOMIC_STORE8_I32_A32 },
8972 { ATOMIC_STORE8_I32_A64_S, ATOMIC_STORE8_I32_A64 },
8973 { ATOMIC_STORE8_I64_A32_S, ATOMIC_STORE8_I64_A32 },
8974 { ATOMIC_STORE8_I64_A64_S, ATOMIC_STORE8_I64_A64 },
8975 { ATOMIC_STORE_I32_A32_S, ATOMIC_STORE_I32_A32 },
8976 { ATOMIC_STORE_I32_A64_S, ATOMIC_STORE_I32_A64 },
8977 { ATOMIC_STORE_I64_A32_S, ATOMIC_STORE_I64_A32 },
8978 { ATOMIC_STORE_I64_A64_S, ATOMIC_STORE_I64_A64 },
8979 { AVGR_U_I16x8_S, AVGR_U_I16x8 },
8980 { AVGR_U_I8x16_S, AVGR_U_I8x16 },
8981 { BITMASK_I16x8_S, BITMASK_I16x8 },
8982 { BITMASK_I32x4_S, BITMASK_I32x4 },
8983 { BITMASK_I64x2_S, BITMASK_I64x2 },
8984 { BITMASK_I8x16_S, BITMASK_I8x16 },
8985 { BITSELECT_S, BITSELECT },
8986 { BLOCK_S, BLOCK },
8987 { BR_IF_S, BR_IF },
8988 { BR_S, BR },
8989 { BR_TABLE_I32_S, BR_TABLE_I32 },
8990 { BR_TABLE_I64_S, BR_TABLE_I64 },
8991 { BR_UNLESS_S, BR_UNLESS },
8992 { CALL_INDIRECT_S, CALL_INDIRECT },
8993 { CALL_S, CALL },
8994 { CATCH_ALL_LEGACY_S, CATCH_ALL_LEGACY },
8995 { CATCH_ALL_REF_S, CATCH_ALL_REF },
8996 { CATCH_ALL_S, CATCH_ALL },
8997 { CATCH_LEGACY_S, CATCH_LEGACY },
8998 { CATCH_REF_S, CATCH_REF },
8999 { CATCH_S, CATCH },
9000 { CEIL_F16x8_S, CEIL_F16x8 },
9001 { CEIL_F32_S, CEIL_F32 },
9002 { CEIL_F32x4_S, CEIL_F32x4 },
9003 { CEIL_F64_S, CEIL_F64 },
9004 { CEIL_F64x2_S, CEIL_F64x2 },
9005 { CLZ_I32_S, CLZ_I32 },
9006 { CLZ_I64_S, CLZ_I64 },
9007 { CONST_F32_S, CONST_F32 },
9008 { CONST_F64_S, CONST_F64 },
9009 { CONST_I32_S, CONST_I32 },
9010 { CONST_I64_S, CONST_I64 },
9011 { CONST_V128_F32x4_S, CONST_V128_F32x4 },
9012 { CONST_V128_F64x2_S, CONST_V128_F64x2 },
9013 { CONST_V128_I16x8_S, CONST_V128_I16x8 },
9014 { CONST_V128_I32x4_S, CONST_V128_I32x4 },
9015 { CONST_V128_I64x2_S, CONST_V128_I64x2 },
9016 { CONST_V128_I8x16_S, CONST_V128_I8x16 },
9017 { COPYSIGN_F32_S, COPYSIGN_F32 },
9018 { COPYSIGN_F64_S, COPYSIGN_F64 },
9019 { COPY_EXNREF_S, COPY_EXNREF },
9020 { COPY_EXTERNREF_S, COPY_EXTERNREF },
9021 { COPY_F32_S, COPY_F32 },
9022 { COPY_F64_S, COPY_F64 },
9023 { COPY_FUNCREF_S, COPY_FUNCREF },
9024 { COPY_I32_S, COPY_I32 },
9025 { COPY_I64_S, COPY_I64 },
9026 { COPY_V128_S, COPY_V128 },
9027 { CTZ_I32_S, CTZ_I32 },
9028 { CTZ_I64_S, CTZ_I64 },
9029 { DATA_DROP_S, DATA_DROP },
9030 { DEBUG_UNREACHABLE_S, DEBUG_UNREACHABLE },
9031 { DELEGATE_S, DELEGATE },
9032 { DIV_F16x8_S, DIV_F16x8 },
9033 { DIV_F32_S, DIV_F32 },
9034 { DIV_F32x4_S, DIV_F32x4 },
9035 { DIV_F64_S, DIV_F64 },
9036 { DIV_F64x2_S, DIV_F64x2 },
9037 { DIV_S_I32_S, DIV_S_I32 },
9038 { DIV_S_I64_S, DIV_S_I64 },
9039 { DIV_U_I32_S, DIV_U_I32 },
9040 { DIV_U_I64_S, DIV_U_I64 },
9041 { DOT_S, DOT },
9042 { DROP_EXNREF_S, DROP_EXNREF },
9043 { DROP_EXTERNREF_S, DROP_EXTERNREF },
9044 { DROP_F32_S, DROP_F32 },
9045 { DROP_F64_S, DROP_F64 },
9046 { DROP_FUNCREF_S, DROP_FUNCREF },
9047 { DROP_I32_S, DROP_I32 },
9048 { DROP_I64_S, DROP_I64 },
9049 { DROP_V128_S, DROP_V128 },
9050 { ELSE_S, ELSE },
9051 { END_BLOCK_S, END_BLOCK },
9052 { END_FUNCTION_S, END_FUNCTION },
9053 { END_IF_S, END_IF },
9054 { END_LOOP_S, END_LOOP },
9055 { END_S, END },
9056 { END_TRY_S, END_TRY },
9057 { END_TRY_TABLE_S, END_TRY_TABLE },
9058 { EQZ_I32_S, EQZ_I32 },
9059 { EQZ_I64_S, EQZ_I64 },
9060 { EQ_F16x8_S, EQ_F16x8 },
9061 { EQ_F32_S, EQ_F32 },
9062 { EQ_F32x4_S, EQ_F32x4 },
9063 { EQ_F64_S, EQ_F64 },
9064 { EQ_F64x2_S, EQ_F64x2 },
9065 { EQ_I16x8_S, EQ_I16x8 },
9066 { EQ_I32_S, EQ_I32 },
9067 { EQ_I32x4_S, EQ_I32x4 },
9068 { EQ_I64_S, EQ_I64 },
9069 { EQ_I64x2_S, EQ_I64x2 },
9070 { EQ_I8x16_S, EQ_I8x16 },
9071 { EXTMUL_HIGH_S_I16x8_S, EXTMUL_HIGH_S_I16x8 },
9072 { EXTMUL_HIGH_S_I32x4_S, EXTMUL_HIGH_S_I32x4 },
9073 { EXTMUL_HIGH_S_I64x2_S, EXTMUL_HIGH_S_I64x2 },
9074 { EXTMUL_HIGH_U_I16x8_S, EXTMUL_HIGH_U_I16x8 },
9075 { EXTMUL_HIGH_U_I32x4_S, EXTMUL_HIGH_U_I32x4 },
9076 { EXTMUL_HIGH_U_I64x2_S, EXTMUL_HIGH_U_I64x2 },
9077 { EXTMUL_LOW_S_I16x8_S, EXTMUL_LOW_S_I16x8 },
9078 { EXTMUL_LOW_S_I32x4_S, EXTMUL_LOW_S_I32x4 },
9079 { EXTMUL_LOW_S_I64x2_S, EXTMUL_LOW_S_I64x2 },
9080 { EXTMUL_LOW_U_I16x8_S, EXTMUL_LOW_U_I16x8 },
9081 { EXTMUL_LOW_U_I32x4_S, EXTMUL_LOW_U_I32x4 },
9082 { EXTMUL_LOW_U_I64x2_S, EXTMUL_LOW_U_I64x2 },
9083 { EXTRACT_LANE_F16x8_S, EXTRACT_LANE_F16x8 },
9084 { EXTRACT_LANE_F32x4_S, EXTRACT_LANE_F32x4 },
9085 { EXTRACT_LANE_F64x2_S, EXTRACT_LANE_F64x2 },
9086 { EXTRACT_LANE_I16x8_s_S, EXTRACT_LANE_I16x8_s },
9087 { EXTRACT_LANE_I16x8_u_S, EXTRACT_LANE_I16x8_u },
9088 { EXTRACT_LANE_I32x4_S, EXTRACT_LANE_I32x4 },
9089 { EXTRACT_LANE_I64x2_S, EXTRACT_LANE_I64x2 },
9090 { EXTRACT_LANE_I8x16_s_S, EXTRACT_LANE_I8x16_s },
9091 { EXTRACT_LANE_I8x16_u_S, EXTRACT_LANE_I8x16_u },
9092 { F32_CONVERT_S_I32_S, F32_CONVERT_S_I32 },
9093 { F32_CONVERT_S_I64_S, F32_CONVERT_S_I64 },
9094 { F32_CONVERT_U_I32_S, F32_CONVERT_U_I32 },
9095 { F32_CONVERT_U_I64_S, F32_CONVERT_U_I64 },
9096 { F32_DEMOTE_F64_S, F32_DEMOTE_F64 },
9097 { F32_REINTERPRET_I32_S, F32_REINTERPRET_I32 },
9098 { F64_CONVERT_S_I32_S, F64_CONVERT_S_I32 },
9099 { F64_CONVERT_S_I64_S, F64_CONVERT_S_I64 },
9100 { F64_CONVERT_U_I32_S, F64_CONVERT_U_I32 },
9101 { F64_CONVERT_U_I64_S, F64_CONVERT_U_I64 },
9102 { F64_PROMOTE_F32_S, F64_PROMOTE_F32 },
9103 { F64_REINTERPRET_I64_S, F64_REINTERPRET_I64 },
9104 { FALLTHROUGH_RETURN_S, FALLTHROUGH_RETURN },
9105 { FLOOR_F16x8_S, FLOOR_F16x8 },
9106 { FLOOR_F32_S, FLOOR_F32 },
9107 { FLOOR_F32x4_S, FLOOR_F32x4 },
9108 { FLOOR_F64_S, FLOOR_F64 },
9109 { FLOOR_F64x2_S, FLOOR_F64x2 },
9110 { FP_TO_SINT_I32_F32_S, FP_TO_SINT_I32_F32 },
9111 { FP_TO_SINT_I32_F64_S, FP_TO_SINT_I32_F64 },
9112 { FP_TO_SINT_I64_F32_S, FP_TO_SINT_I64_F32 },
9113 { FP_TO_SINT_I64_F64_S, FP_TO_SINT_I64_F64 },
9114 { FP_TO_UINT_I32_F32_S, FP_TO_UINT_I32_F32 },
9115 { FP_TO_UINT_I32_F64_S, FP_TO_UINT_I32_F64 },
9116 { FP_TO_UINT_I64_F32_S, FP_TO_UINT_I64_F32 },
9117 { FP_TO_UINT_I64_F64_S, FP_TO_UINT_I64_F64 },
9118 { GE_F16x8_S, GE_F16x8 },
9119 { GE_F32_S, GE_F32 },
9120 { GE_F32x4_S, GE_F32x4 },
9121 { GE_F64_S, GE_F64 },
9122 { GE_F64x2_S, GE_F64x2 },
9123 { GE_S_I16x8_S, GE_S_I16x8 },
9124 { GE_S_I32_S, GE_S_I32 },
9125 { GE_S_I32x4_S, GE_S_I32x4 },
9126 { GE_S_I64_S, GE_S_I64 },
9127 { GE_S_I64x2_S, GE_S_I64x2 },
9128 { GE_S_I8x16_S, GE_S_I8x16 },
9129 { GE_U_I16x8_S, GE_U_I16x8 },
9130 { GE_U_I32_S, GE_U_I32 },
9131 { GE_U_I32x4_S, GE_U_I32x4 },
9132 { GE_U_I64_S, GE_U_I64 },
9133 { GE_U_I8x16_S, GE_U_I8x16 },
9134 { GLOBAL_GET_EXNREF_S, GLOBAL_GET_EXNREF },
9135 { GLOBAL_GET_EXTERNREF_S, GLOBAL_GET_EXTERNREF },
9136 { GLOBAL_GET_F32_S, GLOBAL_GET_F32 },
9137 { GLOBAL_GET_F64_S, GLOBAL_GET_F64 },
9138 { GLOBAL_GET_FUNCREF_S, GLOBAL_GET_FUNCREF },
9139 { GLOBAL_GET_I32_S, GLOBAL_GET_I32 },
9140 { GLOBAL_GET_I64_S, GLOBAL_GET_I64 },
9141 { GLOBAL_GET_V128_S, GLOBAL_GET_V128 },
9142 { GLOBAL_SET_EXNREF_S, GLOBAL_SET_EXNREF },
9143 { GLOBAL_SET_EXTERNREF_S, GLOBAL_SET_EXTERNREF },
9144 { GLOBAL_SET_F32_S, GLOBAL_SET_F32 },
9145 { GLOBAL_SET_F64_S, GLOBAL_SET_F64 },
9146 { GLOBAL_SET_FUNCREF_S, GLOBAL_SET_FUNCREF },
9147 { GLOBAL_SET_I32_S, GLOBAL_SET_I32 },
9148 { GLOBAL_SET_I64_S, GLOBAL_SET_I64 },
9149 { GLOBAL_SET_V128_S, GLOBAL_SET_V128 },
9150 { GT_F16x8_S, GT_F16x8 },
9151 { GT_F32_S, GT_F32 },
9152 { GT_F32x4_S, GT_F32x4 },
9153 { GT_F64_S, GT_F64 },
9154 { GT_F64x2_S, GT_F64x2 },
9155 { GT_S_I16x8_S, GT_S_I16x8 },
9156 { GT_S_I32_S, GT_S_I32 },
9157 { GT_S_I32x4_S, GT_S_I32x4 },
9158 { GT_S_I64_S, GT_S_I64 },
9159 { GT_S_I64x2_S, GT_S_I64x2 },
9160 { GT_S_I8x16_S, GT_S_I8x16 },
9161 { GT_U_I16x8_S, GT_U_I16x8 },
9162 { GT_U_I32_S, GT_U_I32 },
9163 { GT_U_I32x4_S, GT_U_I32x4 },
9164 { GT_U_I64_S, GT_U_I64 },
9165 { GT_U_I8x16_S, GT_U_I8x16 },
9166 { I32_EXTEND16_S_I32_S, I32_EXTEND16_S_I32 },
9167 { I32_EXTEND8_S_I32_S, I32_EXTEND8_S_I32 },
9168 { I32_REINTERPRET_F32_S, I32_REINTERPRET_F32 },
9169 { I32_TRUNC_S_F32_S, I32_TRUNC_S_F32 },
9170 { I32_TRUNC_S_F64_S, I32_TRUNC_S_F64 },
9171 { I32_TRUNC_S_SAT_F32_S, I32_TRUNC_S_SAT_F32 },
9172 { I32_TRUNC_S_SAT_F64_S, I32_TRUNC_S_SAT_F64 },
9173 { I32_TRUNC_U_F32_S, I32_TRUNC_U_F32 },
9174 { I32_TRUNC_U_F64_S, I32_TRUNC_U_F64 },
9175 { I32_TRUNC_U_SAT_F32_S, I32_TRUNC_U_SAT_F32 },
9176 { I32_TRUNC_U_SAT_F64_S, I32_TRUNC_U_SAT_F64 },
9177 { I32_WRAP_I64_S, I32_WRAP_I64 },
9178 { I64_ADD128_S, I64_ADD128 },
9179 { I64_EXTEND16_S_I64_S, I64_EXTEND16_S_I64 },
9180 { I64_EXTEND32_S_I64_S, I64_EXTEND32_S_I64 },
9181 { I64_EXTEND8_S_I64_S, I64_EXTEND8_S_I64 },
9182 { I64_EXTEND_S_I32_S, I64_EXTEND_S_I32 },
9183 { I64_EXTEND_U_I32_S, I64_EXTEND_U_I32 },
9184 { I64_MUL_WIDE_S_S, I64_MUL_WIDE_S },
9185 { I64_MUL_WIDE_U_S, I64_MUL_WIDE_U },
9186 { I64_REINTERPRET_F64_S, I64_REINTERPRET_F64 },
9187 { I64_SUB128_S, I64_SUB128 },
9188 { I64_TRUNC_S_F32_S, I64_TRUNC_S_F32 },
9189 { I64_TRUNC_S_F64_S, I64_TRUNC_S_F64 },
9190 { I64_TRUNC_S_SAT_F32_S, I64_TRUNC_S_SAT_F32 },
9191 { I64_TRUNC_S_SAT_F64_S, I64_TRUNC_S_SAT_F64 },
9192 { I64_TRUNC_U_F32_S, I64_TRUNC_U_F32 },
9193 { I64_TRUNC_U_F64_S, I64_TRUNC_U_F64 },
9194 { I64_TRUNC_U_SAT_F32_S, I64_TRUNC_U_SAT_F32 },
9195 { I64_TRUNC_U_SAT_F64_S, I64_TRUNC_U_SAT_F64 },
9196 { IF_S, IF },
9197 { LANESELECT_I16x8_S, LANESELECT_I16x8 },
9198 { LANESELECT_I32x4_S, LANESELECT_I32x4 },
9199 { LANESELECT_I64x2_S, LANESELECT_I64x2 },
9200 { LANESELECT_I8x16_S, LANESELECT_I8x16 },
9201 { LE_F16x8_S, LE_F16x8 },
9202 { LE_F32_S, LE_F32 },
9203 { LE_F32x4_S, LE_F32x4 },
9204 { LE_F64_S, LE_F64 },
9205 { LE_F64x2_S, LE_F64x2 },
9206 { LE_S_I16x8_S, LE_S_I16x8 },
9207 { LE_S_I32_S, LE_S_I32 },
9208 { LE_S_I32x4_S, LE_S_I32x4 },
9209 { LE_S_I64_S, LE_S_I64 },
9210 { LE_S_I64x2_S, LE_S_I64x2 },
9211 { LE_S_I8x16_S, LE_S_I8x16 },
9212 { LE_U_I16x8_S, LE_U_I16x8 },
9213 { LE_U_I32_S, LE_U_I32 },
9214 { LE_U_I32x4_S, LE_U_I32x4 },
9215 { LE_U_I64_S, LE_U_I64 },
9216 { LE_U_I8x16_S, LE_U_I8x16 },
9217 { LOAD16_SPLAT_A32_S, LOAD16_SPLAT_A32 },
9218 { LOAD16_SPLAT_A64_S, LOAD16_SPLAT_A64 },
9219 { LOAD16_S_I32_A32_S, LOAD16_S_I32_A32 },
9220 { LOAD16_S_I32_A64_S, LOAD16_S_I32_A64 },
9221 { LOAD16_S_I64_A32_S, LOAD16_S_I64_A32 },
9222 { LOAD16_S_I64_A64_S, LOAD16_S_I64_A64 },
9223 { LOAD16_U_I32_A32_S, LOAD16_U_I32_A32 },
9224 { LOAD16_U_I32_A64_S, LOAD16_U_I32_A64 },
9225 { LOAD16_U_I64_A32_S, LOAD16_U_I64_A32 },
9226 { LOAD16_U_I64_A64_S, LOAD16_U_I64_A64 },
9227 { LOAD32_SPLAT_A32_S, LOAD32_SPLAT_A32 },
9228 { LOAD32_SPLAT_A64_S, LOAD32_SPLAT_A64 },
9229 { LOAD32_S_I64_A32_S, LOAD32_S_I64_A32 },
9230 { LOAD32_S_I64_A64_S, LOAD32_S_I64_A64 },
9231 { LOAD32_U_I64_A32_S, LOAD32_U_I64_A32 },
9232 { LOAD32_U_I64_A64_S, LOAD32_U_I64_A64 },
9233 { LOAD64_SPLAT_A32_S, LOAD64_SPLAT_A32 },
9234 { LOAD64_SPLAT_A64_S, LOAD64_SPLAT_A64 },
9235 { LOAD8_SPLAT_A32_S, LOAD8_SPLAT_A32 },
9236 { LOAD8_SPLAT_A64_S, LOAD8_SPLAT_A64 },
9237 { LOAD8_S_I32_A32_S, LOAD8_S_I32_A32 },
9238 { LOAD8_S_I32_A64_S, LOAD8_S_I32_A64 },
9239 { LOAD8_S_I64_A32_S, LOAD8_S_I64_A32 },
9240 { LOAD8_S_I64_A64_S, LOAD8_S_I64_A64 },
9241 { LOAD8_U_I32_A32_S, LOAD8_U_I32_A32 },
9242 { LOAD8_U_I32_A64_S, LOAD8_U_I32_A64 },
9243 { LOAD8_U_I64_A32_S, LOAD8_U_I64_A32 },
9244 { LOAD8_U_I64_A64_S, LOAD8_U_I64_A64 },
9245 { LOAD_EXTEND_S_I16x8_A32_S, LOAD_EXTEND_S_I16x8_A32 },
9246 { LOAD_EXTEND_S_I16x8_A64_S, LOAD_EXTEND_S_I16x8_A64 },
9247 { LOAD_EXTEND_S_I32x4_A32_S, LOAD_EXTEND_S_I32x4_A32 },
9248 { LOAD_EXTEND_S_I32x4_A64_S, LOAD_EXTEND_S_I32x4_A64 },
9249 { LOAD_EXTEND_S_I64x2_A32_S, LOAD_EXTEND_S_I64x2_A32 },
9250 { LOAD_EXTEND_S_I64x2_A64_S, LOAD_EXTEND_S_I64x2_A64 },
9251 { LOAD_EXTEND_U_I16x8_A32_S, LOAD_EXTEND_U_I16x8_A32 },
9252 { LOAD_EXTEND_U_I16x8_A64_S, LOAD_EXTEND_U_I16x8_A64 },
9253 { LOAD_EXTEND_U_I32x4_A32_S, LOAD_EXTEND_U_I32x4_A32 },
9254 { LOAD_EXTEND_U_I32x4_A64_S, LOAD_EXTEND_U_I32x4_A64 },
9255 { LOAD_EXTEND_U_I64x2_A32_S, LOAD_EXTEND_U_I64x2_A32 },
9256 { LOAD_EXTEND_U_I64x2_A64_S, LOAD_EXTEND_U_I64x2_A64 },
9257 { LOAD_F16_F32_A32_S, LOAD_F16_F32_A32 },
9258 { LOAD_F16_F32_A64_S, LOAD_F16_F32_A64 },
9259 { LOAD_F32_A32_S, LOAD_F32_A32 },
9260 { LOAD_F32_A64_S, LOAD_F32_A64 },
9261 { LOAD_F64_A32_S, LOAD_F64_A32 },
9262 { LOAD_F64_A64_S, LOAD_F64_A64 },
9263 { LOAD_I32_A32_S, LOAD_I32_A32 },
9264 { LOAD_I32_A64_S, LOAD_I32_A64 },
9265 { LOAD_I64_A32_S, LOAD_I64_A32 },
9266 { LOAD_I64_A64_S, LOAD_I64_A64 },
9267 { LOAD_LANE_16_A32_S, LOAD_LANE_16_A32 },
9268 { LOAD_LANE_16_A64_S, LOAD_LANE_16_A64 },
9269 { LOAD_LANE_32_A32_S, LOAD_LANE_32_A32 },
9270 { LOAD_LANE_32_A64_S, LOAD_LANE_32_A64 },
9271 { LOAD_LANE_64_A32_S, LOAD_LANE_64_A32 },
9272 { LOAD_LANE_64_A64_S, LOAD_LANE_64_A64 },
9273 { LOAD_LANE_8_A32_S, LOAD_LANE_8_A32 },
9274 { LOAD_LANE_8_A64_S, LOAD_LANE_8_A64 },
9275 { LOAD_V128_A32_S, LOAD_V128_A32 },
9276 { LOAD_V128_A64_S, LOAD_V128_A64 },
9277 { LOAD_ZERO_32_A32_S, LOAD_ZERO_32_A32 },
9278 { LOAD_ZERO_32_A64_S, LOAD_ZERO_32_A64 },
9279 { LOAD_ZERO_64_A32_S, LOAD_ZERO_64_A32 },
9280 { LOAD_ZERO_64_A64_S, LOAD_ZERO_64_A64 },
9281 { LOCAL_GET_EXNREF_S, LOCAL_GET_EXNREF },
9282 { LOCAL_GET_EXTERNREF_S, LOCAL_GET_EXTERNREF },
9283 { LOCAL_GET_F32_S, LOCAL_GET_F32 },
9284 { LOCAL_GET_F64_S, LOCAL_GET_F64 },
9285 { LOCAL_GET_FUNCREF_S, LOCAL_GET_FUNCREF },
9286 { LOCAL_GET_I32_S, LOCAL_GET_I32 },
9287 { LOCAL_GET_I64_S, LOCAL_GET_I64 },
9288 { LOCAL_GET_V128_S, LOCAL_GET_V128 },
9289 { LOCAL_SET_EXNREF_S, LOCAL_SET_EXNREF },
9290 { LOCAL_SET_EXTERNREF_S, LOCAL_SET_EXTERNREF },
9291 { LOCAL_SET_F32_S, LOCAL_SET_F32 },
9292 { LOCAL_SET_F64_S, LOCAL_SET_F64 },
9293 { LOCAL_SET_FUNCREF_S, LOCAL_SET_FUNCREF },
9294 { LOCAL_SET_I32_S, LOCAL_SET_I32 },
9295 { LOCAL_SET_I64_S, LOCAL_SET_I64 },
9296 { LOCAL_SET_V128_S, LOCAL_SET_V128 },
9297 { LOCAL_TEE_EXNREF_S, LOCAL_TEE_EXNREF },
9298 { LOCAL_TEE_EXTERNREF_S, LOCAL_TEE_EXTERNREF },
9299 { LOCAL_TEE_F32_S, LOCAL_TEE_F32 },
9300 { LOCAL_TEE_F64_S, LOCAL_TEE_F64 },
9301 { LOCAL_TEE_FUNCREF_S, LOCAL_TEE_FUNCREF },
9302 { LOCAL_TEE_I32_S, LOCAL_TEE_I32 },
9303 { LOCAL_TEE_I64_S, LOCAL_TEE_I64 },
9304 { LOCAL_TEE_V128_S, LOCAL_TEE_V128 },
9305 { LOOP_S, LOOP },
9306 { LT_F16x8_S, LT_F16x8 },
9307 { LT_F32_S, LT_F32 },
9308 { LT_F32x4_S, LT_F32x4 },
9309 { LT_F64_S, LT_F64 },
9310 { LT_F64x2_S, LT_F64x2 },
9311 { LT_S_I16x8_S, LT_S_I16x8 },
9312 { LT_S_I32_S, LT_S_I32 },
9313 { LT_S_I32x4_S, LT_S_I32x4 },
9314 { LT_S_I64_S, LT_S_I64 },
9315 { LT_S_I64x2_S, LT_S_I64x2 },
9316 { LT_S_I8x16_S, LT_S_I8x16 },
9317 { LT_U_I16x8_S, LT_U_I16x8 },
9318 { LT_U_I32_S, LT_U_I32 },
9319 { LT_U_I32x4_S, LT_U_I32x4 },
9320 { LT_U_I64_S, LT_U_I64 },
9321 { LT_U_I8x16_S, LT_U_I8x16 },
9322 { MADD_F16x8_S, MADD_F16x8 },
9323 { MADD_F32x4_S, MADD_F32x4 },
9324 { MADD_F64x2_S, MADD_F64x2 },
9325 { MAX_F16x8_S, MAX_F16x8 },
9326 { MAX_F32_S, MAX_F32 },
9327 { MAX_F32x4_S, MAX_F32x4 },
9328 { MAX_F64_S, MAX_F64 },
9329 { MAX_F64x2_S, MAX_F64x2 },
9330 { MAX_S_I16x8_S, MAX_S_I16x8 },
9331 { MAX_S_I32x4_S, MAX_S_I32x4 },
9332 { MAX_S_I8x16_S, MAX_S_I8x16 },
9333 { MAX_U_I16x8_S, MAX_U_I16x8 },
9334 { MAX_U_I32x4_S, MAX_U_I32x4 },
9335 { MAX_U_I8x16_S, MAX_U_I8x16 },
9336 { MEMCPY_A32_S, MEMCPY_A32 },
9337 { MEMCPY_A64_S, MEMCPY_A64 },
9338 { MEMORY_ATOMIC_NOTIFY_A32_S, MEMORY_ATOMIC_NOTIFY_A32 },
9339 { MEMORY_ATOMIC_NOTIFY_A64_S, MEMORY_ATOMIC_NOTIFY_A64 },
9340 { MEMORY_ATOMIC_WAIT32_A32_S, MEMORY_ATOMIC_WAIT32_A32 },
9341 { MEMORY_ATOMIC_WAIT32_A64_S, MEMORY_ATOMIC_WAIT32_A64 },
9342 { MEMORY_ATOMIC_WAIT64_A32_S, MEMORY_ATOMIC_WAIT64_A32 },
9343 { MEMORY_ATOMIC_WAIT64_A64_S, MEMORY_ATOMIC_WAIT64_A64 },
9344 { MEMORY_COPY_A32_S, MEMORY_COPY_A32 },
9345 { MEMORY_COPY_A64_S, MEMORY_COPY_A64 },
9346 { MEMORY_FILL_A32_S, MEMORY_FILL_A32 },
9347 { MEMORY_FILL_A64_S, MEMORY_FILL_A64 },
9348 { MEMORY_INIT_A32_S, MEMORY_INIT_A32 },
9349 { MEMORY_INIT_A64_S, MEMORY_INIT_A64 },
9350 { MEMSET_A32_S, MEMSET_A32 },
9351 { MEMSET_A64_S, MEMSET_A64 },
9352 { MIN_F16x8_S, MIN_F16x8 },
9353 { MIN_F32_S, MIN_F32 },
9354 { MIN_F32x4_S, MIN_F32x4 },
9355 { MIN_F64_S, MIN_F64 },
9356 { MIN_F64x2_S, MIN_F64x2 },
9357 { MIN_S_I16x8_S, MIN_S_I16x8 },
9358 { MIN_S_I32x4_S, MIN_S_I32x4 },
9359 { MIN_S_I8x16_S, MIN_S_I8x16 },
9360 { MIN_U_I16x8_S, MIN_U_I16x8 },
9361 { MIN_U_I32x4_S, MIN_U_I32x4 },
9362 { MIN_U_I8x16_S, MIN_U_I8x16 },
9363 { MUL_F16x8_S, MUL_F16x8 },
9364 { MUL_F32_S, MUL_F32 },
9365 { MUL_F32x4_S, MUL_F32x4 },
9366 { MUL_F64_S, MUL_F64 },
9367 { MUL_F64x2_S, MUL_F64x2 },
9368 { MUL_I16x8_S, MUL_I16x8 },
9369 { MUL_I32_S, MUL_I32 },
9370 { MUL_I32x4_S, MUL_I32x4 },
9371 { MUL_I64_S, MUL_I64 },
9372 { MUL_I64x2_S, MUL_I64x2 },
9373 { NARROW_S_I16x8_S, NARROW_S_I16x8 },
9374 { NARROW_S_I8x16_S, NARROW_S_I8x16 },
9375 { NARROW_U_I16x8_S, NARROW_U_I16x8 },
9376 { NARROW_U_I8x16_S, NARROW_U_I8x16 },
9377 { NEAREST_F16x8_S, NEAREST_F16x8 },
9378 { NEAREST_F32_S, NEAREST_F32 },
9379 { NEAREST_F32x4_S, NEAREST_F32x4 },
9380 { NEAREST_F64_S, NEAREST_F64 },
9381 { NEAREST_F64x2_S, NEAREST_F64x2 },
9382 { NEG_F16x8_S, NEG_F16x8 },
9383 { NEG_F32_S, NEG_F32 },
9384 { NEG_F32x4_S, NEG_F32x4 },
9385 { NEG_F64_S, NEG_F64 },
9386 { NEG_F64x2_S, NEG_F64x2 },
9387 { NEG_I16x8_S, NEG_I16x8 },
9388 { NEG_I32x4_S, NEG_I32x4 },
9389 { NEG_I64x2_S, NEG_I64x2 },
9390 { NEG_I8x16_S, NEG_I8x16 },
9391 { NE_F16x8_S, NE_F16x8 },
9392 { NE_F32_S, NE_F32 },
9393 { NE_F32x4_S, NE_F32x4 },
9394 { NE_F64_S, NE_F64 },
9395 { NE_F64x2_S, NE_F64x2 },
9396 { NE_I16x8_S, NE_I16x8 },
9397 { NE_I32_S, NE_I32 },
9398 { NE_I32x4_S, NE_I32x4 },
9399 { NE_I64_S, NE_I64 },
9400 { NE_I64x2_S, NE_I64x2 },
9401 { NE_I8x16_S, NE_I8x16 },
9402 { NMADD_F16x8_S, NMADD_F16x8 },
9403 { NMADD_F32x4_S, NMADD_F32x4 },
9404 { NMADD_F64x2_S, NMADD_F64x2 },
9405 { NOP_S, NOP },
9406 { NOT_S, NOT },
9407 { OR_I32_S, OR_I32 },
9408 { OR_I64_S, OR_I64 },
9409 { OR_S, OR },
9410 { PMAX_F16x8_S, PMAX_F16x8 },
9411 { PMAX_F32x4_S, PMAX_F32x4 },
9412 { PMAX_F64x2_S, PMAX_F64x2 },
9413 { PMIN_F16x8_S, PMIN_F16x8 },
9414 { PMIN_F32x4_S, PMIN_F32x4 },
9415 { PMIN_F64x2_S, PMIN_F64x2 },
9416 { POPCNT_I32_S, POPCNT_I32 },
9417 { POPCNT_I64_S, POPCNT_I64 },
9418 { POPCNT_I8x16_S, POPCNT_I8x16 },
9419 { Q15MULR_SAT_S_I16x8_S, Q15MULR_SAT_S_I16x8 },
9420 { REF_FUNC_S, REF_FUNC },
9421 { REF_IS_NULL_EXNREF_S, REF_IS_NULL_EXNREF },
9422 { REF_IS_NULL_EXTERNREF_S, REF_IS_NULL_EXTERNREF },
9423 { REF_IS_NULL_FUNCREF_S, REF_IS_NULL_FUNCREF },
9424 { REF_NULL_EXNREF_S, REF_NULL_EXNREF },
9425 { REF_NULL_EXTERNREF_S, REF_NULL_EXTERNREF },
9426 { REF_NULL_FUNCREF_S, REF_NULL_FUNCREF },
9427 { REF_TEST_FUNCREF_S, REF_TEST_FUNCREF },
9428 { RELAXED_DOT_ADD_S, RELAXED_DOT_ADD },
9429 { RELAXED_DOT_BFLOAT_S, RELAXED_DOT_BFLOAT },
9430 { RELAXED_DOT_S, RELAXED_DOT },
9431 { RELAXED_Q15MULR_S_I16x8_S, RELAXED_Q15MULR_S_I16x8 },
9432 { RELAXED_SWIZZLE_S, RELAXED_SWIZZLE },
9433 { REM_S_I32_S, REM_S_I32 },
9434 { REM_S_I64_S, REM_S_I64 },
9435 { REM_U_I32_S, REM_U_I32 },
9436 { REM_U_I64_S, REM_U_I64 },
9437 { REPLACE_LANE_F16x8_S, REPLACE_LANE_F16x8 },
9438 { REPLACE_LANE_F32x4_S, REPLACE_LANE_F32x4 },
9439 { REPLACE_LANE_F64x2_S, REPLACE_LANE_F64x2 },
9440 { REPLACE_LANE_I16x8_S, REPLACE_LANE_I16x8 },
9441 { REPLACE_LANE_I32x4_S, REPLACE_LANE_I32x4 },
9442 { REPLACE_LANE_I64x2_S, REPLACE_LANE_I64x2 },
9443 { REPLACE_LANE_I8x16_S, REPLACE_LANE_I8x16 },
9444 { RETHROW_S, RETHROW },
9445 { RETURN_S, RETURN },
9446 { RET_CALL_INDIRECT_S, RET_CALL_INDIRECT },
9447 { RET_CALL_S, RET_CALL },
9448 { ROTL_I32_S, ROTL_I32 },
9449 { ROTL_I64_S, ROTL_I64 },
9450 { ROTR_I32_S, ROTR_I32 },
9451 { ROTR_I64_S, ROTR_I64 },
9452 { SELECT_EXNREF_S, SELECT_EXNREF },
9453 { SELECT_EXTERNREF_S, SELECT_EXTERNREF },
9454 { SELECT_F32_S, SELECT_F32 },
9455 { SELECT_F64_S, SELECT_F64 },
9456 { SELECT_FUNCREF_S, SELECT_FUNCREF },
9457 { SELECT_I32_S, SELECT_I32 },
9458 { SELECT_I64_S, SELECT_I64 },
9459 { SELECT_V128_S, SELECT_V128 },
9460 { SHL_I16x8_S, SHL_I16x8 },
9461 { SHL_I32_S, SHL_I32 },
9462 { SHL_I32x4_S, SHL_I32x4 },
9463 { SHL_I64_S, SHL_I64 },
9464 { SHL_I64x2_S, SHL_I64x2 },
9465 { SHL_I8x16_S, SHL_I8x16 },
9466 { SHR_S_I16x8_S, SHR_S_I16x8 },
9467 { SHR_S_I32_S, SHR_S_I32 },
9468 { SHR_S_I32x4_S, SHR_S_I32x4 },
9469 { SHR_S_I64_S, SHR_S_I64 },
9470 { SHR_S_I64x2_S, SHR_S_I64x2 },
9471 { SHR_S_I8x16_S, SHR_S_I8x16 },
9472 { SHR_U_I16x8_S, SHR_U_I16x8 },
9473 { SHR_U_I32_S, SHR_U_I32 },
9474 { SHR_U_I32x4_S, SHR_U_I32x4 },
9475 { SHR_U_I64_S, SHR_U_I64 },
9476 { SHR_U_I64x2_S, SHR_U_I64x2 },
9477 { SHR_U_I8x16_S, SHR_U_I8x16 },
9478 { SHUFFLE_S, SHUFFLE },
9479 { SIMD_RELAXED_FMAX_F32x4_S, SIMD_RELAXED_FMAX_F32x4 },
9480 { SIMD_RELAXED_FMAX_F64x2_S, SIMD_RELAXED_FMAX_F64x2 },
9481 { SIMD_RELAXED_FMIN_F32x4_S, SIMD_RELAXED_FMIN_F32x4 },
9482 { SIMD_RELAXED_FMIN_F64x2_S, SIMD_RELAXED_FMIN_F64x2 },
9483 { SPLAT_F16x8_S, SPLAT_F16x8 },
9484 { SPLAT_F32x4_S, SPLAT_F32x4 },
9485 { SPLAT_F64x2_S, SPLAT_F64x2 },
9486 { SPLAT_I16x8_S, SPLAT_I16x8 },
9487 { SPLAT_I32x4_S, SPLAT_I32x4 },
9488 { SPLAT_I64x2_S, SPLAT_I64x2 },
9489 { SPLAT_I8x16_S, SPLAT_I8x16 },
9490 { SQRT_F16x8_S, SQRT_F16x8 },
9491 { SQRT_F32_S, SQRT_F32 },
9492 { SQRT_F32x4_S, SQRT_F32x4 },
9493 { SQRT_F64_S, SQRT_F64 },
9494 { SQRT_F64x2_S, SQRT_F64x2 },
9495 { STORE16_I32_A32_S, STORE16_I32_A32 },
9496 { STORE16_I32_A64_S, STORE16_I32_A64 },
9497 { STORE16_I64_A32_S, STORE16_I64_A32 },
9498 { STORE16_I64_A64_S, STORE16_I64_A64 },
9499 { STORE32_I64_A32_S, STORE32_I64_A32 },
9500 { STORE32_I64_A64_S, STORE32_I64_A64 },
9501 { STORE8_I32_A32_S, STORE8_I32_A32 },
9502 { STORE8_I32_A64_S, STORE8_I32_A64 },
9503 { STORE8_I64_A32_S, STORE8_I64_A32 },
9504 { STORE8_I64_A64_S, STORE8_I64_A64 },
9505 { STORE_F16_F32_A32_S, STORE_F16_F32_A32 },
9506 { STORE_F16_F32_A64_S, STORE_F16_F32_A64 },
9507 { STORE_F32_A32_S, STORE_F32_A32 },
9508 { STORE_F32_A64_S, STORE_F32_A64 },
9509 { STORE_F64_A32_S, STORE_F64_A32 },
9510 { STORE_F64_A64_S, STORE_F64_A64 },
9511 { STORE_I32_A32_S, STORE_I32_A32 },
9512 { STORE_I32_A64_S, STORE_I32_A64 },
9513 { STORE_I64_A32_S, STORE_I64_A32 },
9514 { STORE_I64_A64_S, STORE_I64_A64 },
9515 { STORE_LANE_I16x8_A32_S, STORE_LANE_I16x8_A32 },
9516 { STORE_LANE_I16x8_A64_S, STORE_LANE_I16x8_A64 },
9517 { STORE_LANE_I32x4_A32_S, STORE_LANE_I32x4_A32 },
9518 { STORE_LANE_I32x4_A64_S, STORE_LANE_I32x4_A64 },
9519 { STORE_LANE_I64x2_A32_S, STORE_LANE_I64x2_A32 },
9520 { STORE_LANE_I64x2_A64_S, STORE_LANE_I64x2_A64 },
9521 { STORE_LANE_I8x16_A32_S, STORE_LANE_I8x16_A32 },
9522 { STORE_LANE_I8x16_A64_S, STORE_LANE_I8x16_A64 },
9523 { STORE_V128_A32_S, STORE_V128_A32 },
9524 { STORE_V128_A64_S, STORE_V128_A64 },
9525 { SUB_F16x8_S, SUB_F16x8 },
9526 { SUB_F32_S, SUB_F32 },
9527 { SUB_F32x4_S, SUB_F32x4 },
9528 { SUB_F64_S, SUB_F64 },
9529 { SUB_F64x2_S, SUB_F64x2 },
9530 { SUB_I16x8_S, SUB_I16x8 },
9531 { SUB_I32_S, SUB_I32 },
9532 { SUB_I32x4_S, SUB_I32x4 },
9533 { SUB_I64_S, SUB_I64 },
9534 { SUB_I64x2_S, SUB_I64x2 },
9535 { SUB_I8x16_S, SUB_I8x16 },
9536 { SUB_SAT_S_I16x8_S, SUB_SAT_S_I16x8 },
9537 { SUB_SAT_S_I8x16_S, SUB_SAT_S_I8x16 },
9538 { SUB_SAT_U_I16x8_S, SUB_SAT_U_I16x8 },
9539 { SUB_SAT_U_I8x16_S, SUB_SAT_U_I8x16 },
9540 { SWIZZLE_S, SWIZZLE },
9541 { TABLE_COPY_S, TABLE_COPY },
9542 { TABLE_FILL_EXNREF_S, TABLE_FILL_EXNREF },
9543 { TABLE_FILL_EXTERNREF_S, TABLE_FILL_EXTERNREF },
9544 { TABLE_FILL_FUNCREF_S, TABLE_FILL_FUNCREF },
9545 { TABLE_GET_EXNREF_S, TABLE_GET_EXNREF },
9546 { TABLE_GET_EXTERNREF_S, TABLE_GET_EXTERNREF },
9547 { TABLE_GET_FUNCREF_S, TABLE_GET_FUNCREF },
9548 { TABLE_GROW_EXNREF_S, TABLE_GROW_EXNREF },
9549 { TABLE_GROW_EXTERNREF_S, TABLE_GROW_EXTERNREF },
9550 { TABLE_GROW_FUNCREF_S, TABLE_GROW_FUNCREF },
9551 { TABLE_SET_EXNREF_S, TABLE_SET_EXNREF },
9552 { TABLE_SET_EXTERNREF_S, TABLE_SET_EXTERNREF },
9553 { TABLE_SET_FUNCREF_S, TABLE_SET_FUNCREF },
9554 { TABLE_SIZE_S, TABLE_SIZE },
9555 { TEE_EXNREF_S, TEE_EXNREF },
9556 { TEE_EXTERNREF_S, TEE_EXTERNREF },
9557 { TEE_F32_S, TEE_F32 },
9558 { TEE_F64_S, TEE_F64 },
9559 { TEE_FUNCREF_S, TEE_FUNCREF },
9560 { TEE_I32_S, TEE_I32 },
9561 { TEE_I64_S, TEE_I64 },
9562 { TEE_V128_S, TEE_V128 },
9563 { THROW_REF_S, THROW_REF },
9564 { THROW_S, THROW },
9565 { TRUNC_F16x8_S, TRUNC_F16x8 },
9566 { TRUNC_F32_S, TRUNC_F32 },
9567 { TRUNC_F32x4_S, TRUNC_F32x4 },
9568 { TRUNC_F64_S, TRUNC_F64 },
9569 { TRUNC_F64x2_S, TRUNC_F64x2 },
9570 { TRY_S, TRY },
9571 { TRY_TABLE_S, TRY_TABLE },
9572 { UNREACHABLE_S, UNREACHABLE },
9573 { XOR_I32_S, XOR_I32 },
9574 { XOR_I64_S, XOR_I64 },
9575 { XOR_S, XOR },
9576 { anonymous_14734MEMORY_GROW_A32_S, anonymous_14734MEMORY_GROW_A32 },
9577 { anonymous_14734MEMORY_SIZE_A32_S, anonymous_14734MEMORY_SIZE_A32 },
9578 { anonymous_14735MEMORY_GROW_A64_S, anonymous_14735MEMORY_GROW_A64 },
9579 { anonymous_14735MEMORY_SIZE_A64_S, anonymous_14735MEMORY_SIZE_A64 },
9580 { convert_low_s_F64x2_S, convert_low_s_F64x2 },
9581 { convert_low_u_F64x2_S, convert_low_u_F64x2 },
9582 { demote_zero_F32x4_S, demote_zero_F32x4 },
9583 { extadd_pairwise_s_I16x8_S, extadd_pairwise_s_I16x8 },
9584 { extadd_pairwise_s_I32x4_S, extadd_pairwise_s_I32x4 },
9585 { extadd_pairwise_u_I16x8_S, extadd_pairwise_u_I16x8 },
9586 { extadd_pairwise_u_I32x4_S, extadd_pairwise_u_I32x4 },
9587 { extend_high_s_I16x8_S, extend_high_s_I16x8 },
9588 { extend_high_s_I32x4_S, extend_high_s_I32x4 },
9589 { extend_high_s_I64x2_S, extend_high_s_I64x2 },
9590 { extend_high_u_I16x8_S, extend_high_u_I16x8 },
9591 { extend_high_u_I32x4_S, extend_high_u_I32x4 },
9592 { extend_high_u_I64x2_S, extend_high_u_I64x2 },
9593 { extend_low_s_I16x8_S, extend_low_s_I16x8 },
9594 { extend_low_s_I32x4_S, extend_low_s_I32x4 },
9595 { extend_low_s_I64x2_S, extend_low_s_I64x2 },
9596 { extend_low_u_I16x8_S, extend_low_u_I16x8 },
9597 { extend_low_u_I32x4_S, extend_low_u_I32x4 },
9598 { extend_low_u_I64x2_S, extend_low_u_I64x2 },
9599 { fp_to_sint_I16x8_S, fp_to_sint_I16x8 },
9600 { fp_to_sint_I32x4_S, fp_to_sint_I32x4 },
9601 { fp_to_uint_I16x8_S, fp_to_uint_I16x8 },
9602 { fp_to_uint_I32x4_S, fp_to_uint_I32x4 },
9603 { int_wasm_relaxed_trunc_signed_I32x4_S, int_wasm_relaxed_trunc_signed_I32x4 },
9604 { int_wasm_relaxed_trunc_signed_zero_I32x4_S, int_wasm_relaxed_trunc_signed_zero_I32x4 },
9605 { int_wasm_relaxed_trunc_unsigned_I32x4_S, int_wasm_relaxed_trunc_unsigned_I32x4 },
9606 { int_wasm_relaxed_trunc_unsigned_zero_I32x4_S, int_wasm_relaxed_trunc_unsigned_zero_I32x4 },
9607 { promote_low_F64x2_S, promote_low_F64x2 },
9608 { sint_to_fp_F16x8_S, sint_to_fp_F16x8 },
9609 { sint_to_fp_F32x4_S, sint_to_fp_F32x4 },
9610 { trunc_sat_zero_s_I32x4_S, trunc_sat_zero_s_I32x4 },
9611 { trunc_sat_zero_u_I32x4_S, trunc_sat_zero_u_I32x4 },
9612 { uint_to_fp_F16x8_S, uint_to_fp_F16x8 },
9613 { uint_to_fp_F32x4_S, uint_to_fp_F32x4 },
9614 }; // End of Table
9615
9616 unsigned mid;
9617 unsigned start = 0;
9618 unsigned end = 817;
9619 while (start < end) {
9620 mid = start + (end - start) / 2;
9621 if (Opcode == Table[mid][0])
9622 break;
9623 if (Opcode < Table[mid][0])
9624 end = mid;
9625 else
9626 start = mid + 1;
9627 }
9628 if (start == end)
9629 return -1; // Instruction doesn't exist in this table.
9630
9631 return Table[mid][1];
9632}
9633
9634// getStackOpcode
9635LLVM_READONLY
9636int getStackOpcode(uint16_t Opcode) {
9637 using namespace WebAssembly;
9638 static constexpr uint16_t Table[][2] = {
9639 { CALL_PARAMS, CALL_PARAMS_S },
9640 { CALL_RESULTS, CALL_RESULTS_S },
9641 { CATCHRET, CATCHRET_S },
9642 { CLEANUPRET, CLEANUPRET_S },
9643 { COMPILER_FENCE, COMPILER_FENCE_S },
9644 { RET_CALL_RESULTS, RET_CALL_RESULTS_S },
9645 { ABS_F16x8, ABS_F16x8_S },
9646 { ABS_F32, ABS_F32_S },
9647 { ABS_F32x4, ABS_F32x4_S },
9648 { ABS_F64, ABS_F64_S },
9649 { ABS_F64x2, ABS_F64x2_S },
9650 { ABS_I16x8, ABS_I16x8_S },
9651 { ABS_I32x4, ABS_I32x4_S },
9652 { ABS_I64x2, ABS_I64x2_S },
9653 { ABS_I8x16, ABS_I8x16_S },
9654 { ADD_F16x8, ADD_F16x8_S },
9655 { ADD_F32, ADD_F32_S },
9656 { ADD_F32x4, ADD_F32x4_S },
9657 { ADD_F64, ADD_F64_S },
9658 { ADD_F64x2, ADD_F64x2_S },
9659 { ADD_I16x8, ADD_I16x8_S },
9660 { ADD_I32, ADD_I32_S },
9661 { ADD_I32x4, ADD_I32x4_S },
9662 { ADD_I64, ADD_I64_S },
9663 { ADD_I64x2, ADD_I64x2_S },
9664 { ADD_I8x16, ADD_I8x16_S },
9665 { ADD_SAT_S_I16x8, ADD_SAT_S_I16x8_S },
9666 { ADD_SAT_S_I8x16, ADD_SAT_S_I8x16_S },
9667 { ADD_SAT_U_I16x8, ADD_SAT_U_I16x8_S },
9668 { ADD_SAT_U_I8x16, ADD_SAT_U_I8x16_S },
9669 { ADJCALLSTACKDOWN, ADJCALLSTACKDOWN_S },
9670 { ADJCALLSTACKUP, ADJCALLSTACKUP_S },
9671 { ALLTRUE_I16x8, ALLTRUE_I16x8_S },
9672 { ALLTRUE_I32x4, ALLTRUE_I32x4_S },
9673 { ALLTRUE_I64x2, ALLTRUE_I64x2_S },
9674 { ALLTRUE_I8x16, ALLTRUE_I8x16_S },
9675 { AND, AND_S },
9676 { ANDNOT, ANDNOT_S },
9677 { AND_I32, AND_I32_S },
9678 { AND_I64, AND_I64_S },
9679 { ANYTRUE, ANYTRUE_S },
9680 { ARGUMENT_exnref, ARGUMENT_exnref_S },
9681 { ARGUMENT_externref, ARGUMENT_externref_S },
9682 { ARGUMENT_f32, ARGUMENT_f32_S },
9683 { ARGUMENT_f64, ARGUMENT_f64_S },
9684 { ARGUMENT_funcref, ARGUMENT_funcref_S },
9685 { ARGUMENT_i32, ARGUMENT_i32_S },
9686 { ARGUMENT_i64, ARGUMENT_i64_S },
9687 { ARGUMENT_v16i8, ARGUMENT_v16i8_S },
9688 { ARGUMENT_v2f64, ARGUMENT_v2f64_S },
9689 { ARGUMENT_v2i64, ARGUMENT_v2i64_S },
9690 { ARGUMENT_v4f32, ARGUMENT_v4f32_S },
9691 { ARGUMENT_v4i32, ARGUMENT_v4i32_S },
9692 { ARGUMENT_v8f16, ARGUMENT_v8f16_S },
9693 { ARGUMENT_v8i16, ARGUMENT_v8i16_S },
9694 { ATOMIC_FENCE, ATOMIC_FENCE_S },
9695 { ATOMIC_LOAD16_U_I32_A32, ATOMIC_LOAD16_U_I32_A32_S },
9696 { ATOMIC_LOAD16_U_I32_A64, ATOMIC_LOAD16_U_I32_A64_S },
9697 { ATOMIC_LOAD16_U_I64_A32, ATOMIC_LOAD16_U_I64_A32_S },
9698 { ATOMIC_LOAD16_U_I64_A64, ATOMIC_LOAD16_U_I64_A64_S },
9699 { ATOMIC_LOAD32_U_I64_A32, ATOMIC_LOAD32_U_I64_A32_S },
9700 { ATOMIC_LOAD32_U_I64_A64, ATOMIC_LOAD32_U_I64_A64_S },
9701 { ATOMIC_LOAD8_U_I32_A32, ATOMIC_LOAD8_U_I32_A32_S },
9702 { ATOMIC_LOAD8_U_I32_A64, ATOMIC_LOAD8_U_I32_A64_S },
9703 { ATOMIC_LOAD8_U_I64_A32, ATOMIC_LOAD8_U_I64_A32_S },
9704 { ATOMIC_LOAD8_U_I64_A64, ATOMIC_LOAD8_U_I64_A64_S },
9705 { ATOMIC_LOAD_I32_A32, ATOMIC_LOAD_I32_A32_S },
9706 { ATOMIC_LOAD_I32_A64, ATOMIC_LOAD_I32_A64_S },
9707 { ATOMIC_LOAD_I64_A32, ATOMIC_LOAD_I64_A32_S },
9708 { ATOMIC_LOAD_I64_A64, ATOMIC_LOAD_I64_A64_S },
9709 { ATOMIC_RMW16_U_ADD_I32_A32, ATOMIC_RMW16_U_ADD_I32_A32_S },
9710 { ATOMIC_RMW16_U_ADD_I32_A64, ATOMIC_RMW16_U_ADD_I32_A64_S },
9711 { ATOMIC_RMW16_U_ADD_I64_A32, ATOMIC_RMW16_U_ADD_I64_A32_S },
9712 { ATOMIC_RMW16_U_ADD_I64_A64, ATOMIC_RMW16_U_ADD_I64_A64_S },
9713 { ATOMIC_RMW16_U_AND_I32_A32, ATOMIC_RMW16_U_AND_I32_A32_S },
9714 { ATOMIC_RMW16_U_AND_I32_A64, ATOMIC_RMW16_U_AND_I32_A64_S },
9715 { ATOMIC_RMW16_U_AND_I64_A32, ATOMIC_RMW16_U_AND_I64_A32_S },
9716 { ATOMIC_RMW16_U_AND_I64_A64, ATOMIC_RMW16_U_AND_I64_A64_S },
9717 { ATOMIC_RMW16_U_CMPXCHG_I32_A32, ATOMIC_RMW16_U_CMPXCHG_I32_A32_S },
9718 { ATOMIC_RMW16_U_CMPXCHG_I32_A64, ATOMIC_RMW16_U_CMPXCHG_I32_A64_S },
9719 { ATOMIC_RMW16_U_CMPXCHG_I64_A32, ATOMIC_RMW16_U_CMPXCHG_I64_A32_S },
9720 { ATOMIC_RMW16_U_CMPXCHG_I64_A64, ATOMIC_RMW16_U_CMPXCHG_I64_A64_S },
9721 { ATOMIC_RMW16_U_OR_I32_A32, ATOMIC_RMW16_U_OR_I32_A32_S },
9722 { ATOMIC_RMW16_U_OR_I32_A64, ATOMIC_RMW16_U_OR_I32_A64_S },
9723 { ATOMIC_RMW16_U_OR_I64_A32, ATOMIC_RMW16_U_OR_I64_A32_S },
9724 { ATOMIC_RMW16_U_OR_I64_A64, ATOMIC_RMW16_U_OR_I64_A64_S },
9725 { ATOMIC_RMW16_U_SUB_I32_A32, ATOMIC_RMW16_U_SUB_I32_A32_S },
9726 { ATOMIC_RMW16_U_SUB_I32_A64, ATOMIC_RMW16_U_SUB_I32_A64_S },
9727 { ATOMIC_RMW16_U_SUB_I64_A32, ATOMIC_RMW16_U_SUB_I64_A32_S },
9728 { ATOMIC_RMW16_U_SUB_I64_A64, ATOMIC_RMW16_U_SUB_I64_A64_S },
9729 { ATOMIC_RMW16_U_XCHG_I32_A32, ATOMIC_RMW16_U_XCHG_I32_A32_S },
9730 { ATOMIC_RMW16_U_XCHG_I32_A64, ATOMIC_RMW16_U_XCHG_I32_A64_S },
9731 { ATOMIC_RMW16_U_XCHG_I64_A32, ATOMIC_RMW16_U_XCHG_I64_A32_S },
9732 { ATOMIC_RMW16_U_XCHG_I64_A64, ATOMIC_RMW16_U_XCHG_I64_A64_S },
9733 { ATOMIC_RMW16_U_XOR_I32_A32, ATOMIC_RMW16_U_XOR_I32_A32_S },
9734 { ATOMIC_RMW16_U_XOR_I32_A64, ATOMIC_RMW16_U_XOR_I32_A64_S },
9735 { ATOMIC_RMW16_U_XOR_I64_A32, ATOMIC_RMW16_U_XOR_I64_A32_S },
9736 { ATOMIC_RMW16_U_XOR_I64_A64, ATOMIC_RMW16_U_XOR_I64_A64_S },
9737 { ATOMIC_RMW32_U_ADD_I64_A32, ATOMIC_RMW32_U_ADD_I64_A32_S },
9738 { ATOMIC_RMW32_U_ADD_I64_A64, ATOMIC_RMW32_U_ADD_I64_A64_S },
9739 { ATOMIC_RMW32_U_AND_I64_A32, ATOMIC_RMW32_U_AND_I64_A32_S },
9740 { ATOMIC_RMW32_U_AND_I64_A64, ATOMIC_RMW32_U_AND_I64_A64_S },
9741 { ATOMIC_RMW32_U_CMPXCHG_I64_A32, ATOMIC_RMW32_U_CMPXCHG_I64_A32_S },
9742 { ATOMIC_RMW32_U_CMPXCHG_I64_A64, ATOMIC_RMW32_U_CMPXCHG_I64_A64_S },
9743 { ATOMIC_RMW32_U_OR_I64_A32, ATOMIC_RMW32_U_OR_I64_A32_S },
9744 { ATOMIC_RMW32_U_OR_I64_A64, ATOMIC_RMW32_U_OR_I64_A64_S },
9745 { ATOMIC_RMW32_U_SUB_I64_A32, ATOMIC_RMW32_U_SUB_I64_A32_S },
9746 { ATOMIC_RMW32_U_SUB_I64_A64, ATOMIC_RMW32_U_SUB_I64_A64_S },
9747 { ATOMIC_RMW32_U_XCHG_I64_A32, ATOMIC_RMW32_U_XCHG_I64_A32_S },
9748 { ATOMIC_RMW32_U_XCHG_I64_A64, ATOMIC_RMW32_U_XCHG_I64_A64_S },
9749 { ATOMIC_RMW32_U_XOR_I64_A32, ATOMIC_RMW32_U_XOR_I64_A32_S },
9750 { ATOMIC_RMW32_U_XOR_I64_A64, ATOMIC_RMW32_U_XOR_I64_A64_S },
9751 { ATOMIC_RMW8_U_ADD_I32_A32, ATOMIC_RMW8_U_ADD_I32_A32_S },
9752 { ATOMIC_RMW8_U_ADD_I32_A64, ATOMIC_RMW8_U_ADD_I32_A64_S },
9753 { ATOMIC_RMW8_U_ADD_I64_A32, ATOMIC_RMW8_U_ADD_I64_A32_S },
9754 { ATOMIC_RMW8_U_ADD_I64_A64, ATOMIC_RMW8_U_ADD_I64_A64_S },
9755 { ATOMIC_RMW8_U_AND_I32_A32, ATOMIC_RMW8_U_AND_I32_A32_S },
9756 { ATOMIC_RMW8_U_AND_I32_A64, ATOMIC_RMW8_U_AND_I32_A64_S },
9757 { ATOMIC_RMW8_U_AND_I64_A32, ATOMIC_RMW8_U_AND_I64_A32_S },
9758 { ATOMIC_RMW8_U_AND_I64_A64, ATOMIC_RMW8_U_AND_I64_A64_S },
9759 { ATOMIC_RMW8_U_CMPXCHG_I32_A32, ATOMIC_RMW8_U_CMPXCHG_I32_A32_S },
9760 { ATOMIC_RMW8_U_CMPXCHG_I32_A64, ATOMIC_RMW8_U_CMPXCHG_I32_A64_S },
9761 { ATOMIC_RMW8_U_CMPXCHG_I64_A32, ATOMIC_RMW8_U_CMPXCHG_I64_A32_S },
9762 { ATOMIC_RMW8_U_CMPXCHG_I64_A64, ATOMIC_RMW8_U_CMPXCHG_I64_A64_S },
9763 { ATOMIC_RMW8_U_OR_I32_A32, ATOMIC_RMW8_U_OR_I32_A32_S },
9764 { ATOMIC_RMW8_U_OR_I32_A64, ATOMIC_RMW8_U_OR_I32_A64_S },
9765 { ATOMIC_RMW8_U_OR_I64_A32, ATOMIC_RMW8_U_OR_I64_A32_S },
9766 { ATOMIC_RMW8_U_OR_I64_A64, ATOMIC_RMW8_U_OR_I64_A64_S },
9767 { ATOMIC_RMW8_U_SUB_I32_A32, ATOMIC_RMW8_U_SUB_I32_A32_S },
9768 { ATOMIC_RMW8_U_SUB_I32_A64, ATOMIC_RMW8_U_SUB_I32_A64_S },
9769 { ATOMIC_RMW8_U_SUB_I64_A32, ATOMIC_RMW8_U_SUB_I64_A32_S },
9770 { ATOMIC_RMW8_U_SUB_I64_A64, ATOMIC_RMW8_U_SUB_I64_A64_S },
9771 { ATOMIC_RMW8_U_XCHG_I32_A32, ATOMIC_RMW8_U_XCHG_I32_A32_S },
9772 { ATOMIC_RMW8_U_XCHG_I32_A64, ATOMIC_RMW8_U_XCHG_I32_A64_S },
9773 { ATOMIC_RMW8_U_XCHG_I64_A32, ATOMIC_RMW8_U_XCHG_I64_A32_S },
9774 { ATOMIC_RMW8_U_XCHG_I64_A64, ATOMIC_RMW8_U_XCHG_I64_A64_S },
9775 { ATOMIC_RMW8_U_XOR_I32_A32, ATOMIC_RMW8_U_XOR_I32_A32_S },
9776 { ATOMIC_RMW8_U_XOR_I32_A64, ATOMIC_RMW8_U_XOR_I32_A64_S },
9777 { ATOMIC_RMW8_U_XOR_I64_A32, ATOMIC_RMW8_U_XOR_I64_A32_S },
9778 { ATOMIC_RMW8_U_XOR_I64_A64, ATOMIC_RMW8_U_XOR_I64_A64_S },
9779 { ATOMIC_RMW_ADD_I32_A32, ATOMIC_RMW_ADD_I32_A32_S },
9780 { ATOMIC_RMW_ADD_I32_A64, ATOMIC_RMW_ADD_I32_A64_S },
9781 { ATOMIC_RMW_ADD_I64_A32, ATOMIC_RMW_ADD_I64_A32_S },
9782 { ATOMIC_RMW_ADD_I64_A64, ATOMIC_RMW_ADD_I64_A64_S },
9783 { ATOMIC_RMW_AND_I32_A32, ATOMIC_RMW_AND_I32_A32_S },
9784 { ATOMIC_RMW_AND_I32_A64, ATOMIC_RMW_AND_I32_A64_S },
9785 { ATOMIC_RMW_AND_I64_A32, ATOMIC_RMW_AND_I64_A32_S },
9786 { ATOMIC_RMW_AND_I64_A64, ATOMIC_RMW_AND_I64_A64_S },
9787 { ATOMIC_RMW_CMPXCHG_I32_A32, ATOMIC_RMW_CMPXCHG_I32_A32_S },
9788 { ATOMIC_RMW_CMPXCHG_I32_A64, ATOMIC_RMW_CMPXCHG_I32_A64_S },
9789 { ATOMIC_RMW_CMPXCHG_I64_A32, ATOMIC_RMW_CMPXCHG_I64_A32_S },
9790 { ATOMIC_RMW_CMPXCHG_I64_A64, ATOMIC_RMW_CMPXCHG_I64_A64_S },
9791 { ATOMIC_RMW_OR_I32_A32, ATOMIC_RMW_OR_I32_A32_S },
9792 { ATOMIC_RMW_OR_I32_A64, ATOMIC_RMW_OR_I32_A64_S },
9793 { ATOMIC_RMW_OR_I64_A32, ATOMIC_RMW_OR_I64_A32_S },
9794 { ATOMIC_RMW_OR_I64_A64, ATOMIC_RMW_OR_I64_A64_S },
9795 { ATOMIC_RMW_SUB_I32_A32, ATOMIC_RMW_SUB_I32_A32_S },
9796 { ATOMIC_RMW_SUB_I32_A64, ATOMIC_RMW_SUB_I32_A64_S },
9797 { ATOMIC_RMW_SUB_I64_A32, ATOMIC_RMW_SUB_I64_A32_S },
9798 { ATOMIC_RMW_SUB_I64_A64, ATOMIC_RMW_SUB_I64_A64_S },
9799 { ATOMIC_RMW_XCHG_I32_A32, ATOMIC_RMW_XCHG_I32_A32_S },
9800 { ATOMIC_RMW_XCHG_I32_A64, ATOMIC_RMW_XCHG_I32_A64_S },
9801 { ATOMIC_RMW_XCHG_I64_A32, ATOMIC_RMW_XCHG_I64_A32_S },
9802 { ATOMIC_RMW_XCHG_I64_A64, ATOMIC_RMW_XCHG_I64_A64_S },
9803 { ATOMIC_RMW_XOR_I32_A32, ATOMIC_RMW_XOR_I32_A32_S },
9804 { ATOMIC_RMW_XOR_I32_A64, ATOMIC_RMW_XOR_I32_A64_S },
9805 { ATOMIC_RMW_XOR_I64_A32, ATOMIC_RMW_XOR_I64_A32_S },
9806 { ATOMIC_RMW_XOR_I64_A64, ATOMIC_RMW_XOR_I64_A64_S },
9807 { ATOMIC_STORE16_I32_A32, ATOMIC_STORE16_I32_A32_S },
9808 { ATOMIC_STORE16_I32_A64, ATOMIC_STORE16_I32_A64_S },
9809 { ATOMIC_STORE16_I64_A32, ATOMIC_STORE16_I64_A32_S },
9810 { ATOMIC_STORE16_I64_A64, ATOMIC_STORE16_I64_A64_S },
9811 { ATOMIC_STORE32_I64_A32, ATOMIC_STORE32_I64_A32_S },
9812 { ATOMIC_STORE32_I64_A64, ATOMIC_STORE32_I64_A64_S },
9813 { ATOMIC_STORE8_I32_A32, ATOMIC_STORE8_I32_A32_S },
9814 { ATOMIC_STORE8_I32_A64, ATOMIC_STORE8_I32_A64_S },
9815 { ATOMIC_STORE8_I64_A32, ATOMIC_STORE8_I64_A32_S },
9816 { ATOMIC_STORE8_I64_A64, ATOMIC_STORE8_I64_A64_S },
9817 { ATOMIC_STORE_I32_A32, ATOMIC_STORE_I32_A32_S },
9818 { ATOMIC_STORE_I32_A64, ATOMIC_STORE_I32_A64_S },
9819 { ATOMIC_STORE_I64_A32, ATOMIC_STORE_I64_A32_S },
9820 { ATOMIC_STORE_I64_A64, ATOMIC_STORE_I64_A64_S },
9821 { AVGR_U_I16x8, AVGR_U_I16x8_S },
9822 { AVGR_U_I8x16, AVGR_U_I8x16_S },
9823 { BITMASK_I16x8, BITMASK_I16x8_S },
9824 { BITMASK_I32x4, BITMASK_I32x4_S },
9825 { BITMASK_I64x2, BITMASK_I64x2_S },
9826 { BITMASK_I8x16, BITMASK_I8x16_S },
9827 { BITSELECT, BITSELECT_S },
9828 { BLOCK, BLOCK_S },
9829 { BR, BR_S },
9830 { BR_IF, BR_IF_S },
9831 { BR_TABLE_I32, BR_TABLE_I32_S },
9832 { BR_TABLE_I64, BR_TABLE_I64_S },
9833 { BR_UNLESS, BR_UNLESS_S },
9834 { CALL, CALL_S },
9835 { CALL_INDIRECT, CALL_INDIRECT_S },
9836 { CATCH, CATCH_S },
9837 { CATCH_ALL, CATCH_ALL_S },
9838 { CATCH_ALL_LEGACY, CATCH_ALL_LEGACY_S },
9839 { CATCH_ALL_REF, CATCH_ALL_REF_S },
9840 { CATCH_LEGACY, CATCH_LEGACY_S },
9841 { CATCH_REF, CATCH_REF_S },
9842 { CEIL_F16x8, CEIL_F16x8_S },
9843 { CEIL_F32, CEIL_F32_S },
9844 { CEIL_F32x4, CEIL_F32x4_S },
9845 { CEIL_F64, CEIL_F64_S },
9846 { CEIL_F64x2, CEIL_F64x2_S },
9847 { CLZ_I32, CLZ_I32_S },
9848 { CLZ_I64, CLZ_I64_S },
9849 { CONST_F32, CONST_F32_S },
9850 { CONST_F64, CONST_F64_S },
9851 { CONST_I32, CONST_I32_S },
9852 { CONST_I64, CONST_I64_S },
9853 { CONST_V128_F32x4, CONST_V128_F32x4_S },
9854 { CONST_V128_F64x2, CONST_V128_F64x2_S },
9855 { CONST_V128_I16x8, CONST_V128_I16x8_S },
9856 { CONST_V128_I32x4, CONST_V128_I32x4_S },
9857 { CONST_V128_I64x2, CONST_V128_I64x2_S },
9858 { CONST_V128_I8x16, CONST_V128_I8x16_S },
9859 { COPYSIGN_F32, COPYSIGN_F32_S },
9860 { COPYSIGN_F64, COPYSIGN_F64_S },
9861 { COPY_EXNREF, COPY_EXNREF_S },
9862 { COPY_EXTERNREF, COPY_EXTERNREF_S },
9863 { COPY_F32, COPY_F32_S },
9864 { COPY_F64, COPY_F64_S },
9865 { COPY_FUNCREF, COPY_FUNCREF_S },
9866 { COPY_I32, COPY_I32_S },
9867 { COPY_I64, COPY_I64_S },
9868 { COPY_V128, COPY_V128_S },
9869 { CTZ_I32, CTZ_I32_S },
9870 { CTZ_I64, CTZ_I64_S },
9871 { DATA_DROP, DATA_DROP_S },
9872 { DEBUG_UNREACHABLE, DEBUG_UNREACHABLE_S },
9873 { DELEGATE, DELEGATE_S },
9874 { DIV_F16x8, DIV_F16x8_S },
9875 { DIV_F32, DIV_F32_S },
9876 { DIV_F32x4, DIV_F32x4_S },
9877 { DIV_F64, DIV_F64_S },
9878 { DIV_F64x2, DIV_F64x2_S },
9879 { DIV_S_I32, DIV_S_I32_S },
9880 { DIV_S_I64, DIV_S_I64_S },
9881 { DIV_U_I32, DIV_U_I32_S },
9882 { DIV_U_I64, DIV_U_I64_S },
9883 { DOT, DOT_S },
9884 { DROP_EXNREF, DROP_EXNREF_S },
9885 { DROP_EXTERNREF, DROP_EXTERNREF_S },
9886 { DROP_F32, DROP_F32_S },
9887 { DROP_F64, DROP_F64_S },
9888 { DROP_FUNCREF, DROP_FUNCREF_S },
9889 { DROP_I32, DROP_I32_S },
9890 { DROP_I64, DROP_I64_S },
9891 { DROP_V128, DROP_V128_S },
9892 { ELSE, ELSE_S },
9893 { END, END_S },
9894 { END_BLOCK, END_BLOCK_S },
9895 { END_FUNCTION, END_FUNCTION_S },
9896 { END_IF, END_IF_S },
9897 { END_LOOP, END_LOOP_S },
9898 { END_TRY, END_TRY_S },
9899 { END_TRY_TABLE, END_TRY_TABLE_S },
9900 { EQZ_I32, EQZ_I32_S },
9901 { EQZ_I64, EQZ_I64_S },
9902 { EQ_F16x8, EQ_F16x8_S },
9903 { EQ_F32, EQ_F32_S },
9904 { EQ_F32x4, EQ_F32x4_S },
9905 { EQ_F64, EQ_F64_S },
9906 { EQ_F64x2, EQ_F64x2_S },
9907 { EQ_I16x8, EQ_I16x8_S },
9908 { EQ_I32, EQ_I32_S },
9909 { EQ_I32x4, EQ_I32x4_S },
9910 { EQ_I64, EQ_I64_S },
9911 { EQ_I64x2, EQ_I64x2_S },
9912 { EQ_I8x16, EQ_I8x16_S },
9913 { EXTMUL_HIGH_S_I16x8, EXTMUL_HIGH_S_I16x8_S },
9914 { EXTMUL_HIGH_S_I32x4, EXTMUL_HIGH_S_I32x4_S },
9915 { EXTMUL_HIGH_S_I64x2, EXTMUL_HIGH_S_I64x2_S },
9916 { EXTMUL_HIGH_U_I16x8, EXTMUL_HIGH_U_I16x8_S },
9917 { EXTMUL_HIGH_U_I32x4, EXTMUL_HIGH_U_I32x4_S },
9918 { EXTMUL_HIGH_U_I64x2, EXTMUL_HIGH_U_I64x2_S },
9919 { EXTMUL_LOW_S_I16x8, EXTMUL_LOW_S_I16x8_S },
9920 { EXTMUL_LOW_S_I32x4, EXTMUL_LOW_S_I32x4_S },
9921 { EXTMUL_LOW_S_I64x2, EXTMUL_LOW_S_I64x2_S },
9922 { EXTMUL_LOW_U_I16x8, EXTMUL_LOW_U_I16x8_S },
9923 { EXTMUL_LOW_U_I32x4, EXTMUL_LOW_U_I32x4_S },
9924 { EXTMUL_LOW_U_I64x2, EXTMUL_LOW_U_I64x2_S },
9925 { EXTRACT_LANE_F16x8, EXTRACT_LANE_F16x8_S },
9926 { EXTRACT_LANE_F32x4, EXTRACT_LANE_F32x4_S },
9927 { EXTRACT_LANE_F64x2, EXTRACT_LANE_F64x2_S },
9928 { EXTRACT_LANE_I16x8_s, EXTRACT_LANE_I16x8_s_S },
9929 { EXTRACT_LANE_I16x8_u, EXTRACT_LANE_I16x8_u_S },
9930 { EXTRACT_LANE_I32x4, EXTRACT_LANE_I32x4_S },
9931 { EXTRACT_LANE_I64x2, EXTRACT_LANE_I64x2_S },
9932 { EXTRACT_LANE_I8x16_s, EXTRACT_LANE_I8x16_s_S },
9933 { EXTRACT_LANE_I8x16_u, EXTRACT_LANE_I8x16_u_S },
9934 { F32_CONVERT_S_I32, F32_CONVERT_S_I32_S },
9935 { F32_CONVERT_S_I64, F32_CONVERT_S_I64_S },
9936 { F32_CONVERT_U_I32, F32_CONVERT_U_I32_S },
9937 { F32_CONVERT_U_I64, F32_CONVERT_U_I64_S },
9938 { F32_DEMOTE_F64, F32_DEMOTE_F64_S },
9939 { F32_REINTERPRET_I32, F32_REINTERPRET_I32_S },
9940 { F64_CONVERT_S_I32, F64_CONVERT_S_I32_S },
9941 { F64_CONVERT_S_I64, F64_CONVERT_S_I64_S },
9942 { F64_CONVERT_U_I32, F64_CONVERT_U_I32_S },
9943 { F64_CONVERT_U_I64, F64_CONVERT_U_I64_S },
9944 { F64_PROMOTE_F32, F64_PROMOTE_F32_S },
9945 { F64_REINTERPRET_I64, F64_REINTERPRET_I64_S },
9946 { FALLTHROUGH_RETURN, FALLTHROUGH_RETURN_S },
9947 { FLOOR_F16x8, FLOOR_F16x8_S },
9948 { FLOOR_F32, FLOOR_F32_S },
9949 { FLOOR_F32x4, FLOOR_F32x4_S },
9950 { FLOOR_F64, FLOOR_F64_S },
9951 { FLOOR_F64x2, FLOOR_F64x2_S },
9952 { FP_TO_SINT_I32_F32, FP_TO_SINT_I32_F32_S },
9953 { FP_TO_SINT_I32_F64, FP_TO_SINT_I32_F64_S },
9954 { FP_TO_SINT_I64_F32, FP_TO_SINT_I64_F32_S },
9955 { FP_TO_SINT_I64_F64, FP_TO_SINT_I64_F64_S },
9956 { FP_TO_UINT_I32_F32, FP_TO_UINT_I32_F32_S },
9957 { FP_TO_UINT_I32_F64, FP_TO_UINT_I32_F64_S },
9958 { FP_TO_UINT_I64_F32, FP_TO_UINT_I64_F32_S },
9959 { FP_TO_UINT_I64_F64, FP_TO_UINT_I64_F64_S },
9960 { GE_F16x8, GE_F16x8_S },
9961 { GE_F32, GE_F32_S },
9962 { GE_F32x4, GE_F32x4_S },
9963 { GE_F64, GE_F64_S },
9964 { GE_F64x2, GE_F64x2_S },
9965 { GE_S_I16x8, GE_S_I16x8_S },
9966 { GE_S_I32, GE_S_I32_S },
9967 { GE_S_I32x4, GE_S_I32x4_S },
9968 { GE_S_I64, GE_S_I64_S },
9969 { GE_S_I64x2, GE_S_I64x2_S },
9970 { GE_S_I8x16, GE_S_I8x16_S },
9971 { GE_U_I16x8, GE_U_I16x8_S },
9972 { GE_U_I32, GE_U_I32_S },
9973 { GE_U_I32x4, GE_U_I32x4_S },
9974 { GE_U_I64, GE_U_I64_S },
9975 { GE_U_I8x16, GE_U_I8x16_S },
9976 { GLOBAL_GET_EXNREF, GLOBAL_GET_EXNREF_S },
9977 { GLOBAL_GET_EXTERNREF, GLOBAL_GET_EXTERNREF_S },
9978 { GLOBAL_GET_F32, GLOBAL_GET_F32_S },
9979 { GLOBAL_GET_F64, GLOBAL_GET_F64_S },
9980 { GLOBAL_GET_FUNCREF, GLOBAL_GET_FUNCREF_S },
9981 { GLOBAL_GET_I32, GLOBAL_GET_I32_S },
9982 { GLOBAL_GET_I64, GLOBAL_GET_I64_S },
9983 { GLOBAL_GET_V128, GLOBAL_GET_V128_S },
9984 { GLOBAL_SET_EXNREF, GLOBAL_SET_EXNREF_S },
9985 { GLOBAL_SET_EXTERNREF, GLOBAL_SET_EXTERNREF_S },
9986 { GLOBAL_SET_F32, GLOBAL_SET_F32_S },
9987 { GLOBAL_SET_F64, GLOBAL_SET_F64_S },
9988 { GLOBAL_SET_FUNCREF, GLOBAL_SET_FUNCREF_S },
9989 { GLOBAL_SET_I32, GLOBAL_SET_I32_S },
9990 { GLOBAL_SET_I64, GLOBAL_SET_I64_S },
9991 { GLOBAL_SET_V128, GLOBAL_SET_V128_S },
9992 { GT_F16x8, GT_F16x8_S },
9993 { GT_F32, GT_F32_S },
9994 { GT_F32x4, GT_F32x4_S },
9995 { GT_F64, GT_F64_S },
9996 { GT_F64x2, GT_F64x2_S },
9997 { GT_S_I16x8, GT_S_I16x8_S },
9998 { GT_S_I32, GT_S_I32_S },
9999 { GT_S_I32x4, GT_S_I32x4_S },
10000 { GT_S_I64, GT_S_I64_S },
10001 { GT_S_I64x2, GT_S_I64x2_S },
10002 { GT_S_I8x16, GT_S_I8x16_S },
10003 { GT_U_I16x8, GT_U_I16x8_S },
10004 { GT_U_I32, GT_U_I32_S },
10005 { GT_U_I32x4, GT_U_I32x4_S },
10006 { GT_U_I64, GT_U_I64_S },
10007 { GT_U_I8x16, GT_U_I8x16_S },
10008 { I32_EXTEND16_S_I32, I32_EXTEND16_S_I32_S },
10009 { I32_EXTEND8_S_I32, I32_EXTEND8_S_I32_S },
10010 { I32_REINTERPRET_F32, I32_REINTERPRET_F32_S },
10011 { I32_TRUNC_S_F32, I32_TRUNC_S_F32_S },
10012 { I32_TRUNC_S_F64, I32_TRUNC_S_F64_S },
10013 { I32_TRUNC_S_SAT_F32, I32_TRUNC_S_SAT_F32_S },
10014 { I32_TRUNC_S_SAT_F64, I32_TRUNC_S_SAT_F64_S },
10015 { I32_TRUNC_U_F32, I32_TRUNC_U_F32_S },
10016 { I32_TRUNC_U_F64, I32_TRUNC_U_F64_S },
10017 { I32_TRUNC_U_SAT_F32, I32_TRUNC_U_SAT_F32_S },
10018 { I32_TRUNC_U_SAT_F64, I32_TRUNC_U_SAT_F64_S },
10019 { I32_WRAP_I64, I32_WRAP_I64_S },
10020 { I64_ADD128, I64_ADD128_S },
10021 { I64_EXTEND16_S_I64, I64_EXTEND16_S_I64_S },
10022 { I64_EXTEND32_S_I64, I64_EXTEND32_S_I64_S },
10023 { I64_EXTEND8_S_I64, I64_EXTEND8_S_I64_S },
10024 { I64_EXTEND_S_I32, I64_EXTEND_S_I32_S },
10025 { I64_EXTEND_U_I32, I64_EXTEND_U_I32_S },
10026 { I64_MUL_WIDE_S, I64_MUL_WIDE_S_S },
10027 { I64_MUL_WIDE_U, I64_MUL_WIDE_U_S },
10028 { I64_REINTERPRET_F64, I64_REINTERPRET_F64_S },
10029 { I64_SUB128, I64_SUB128_S },
10030 { I64_TRUNC_S_F32, I64_TRUNC_S_F32_S },
10031 { I64_TRUNC_S_F64, I64_TRUNC_S_F64_S },
10032 { I64_TRUNC_S_SAT_F32, I64_TRUNC_S_SAT_F32_S },
10033 { I64_TRUNC_S_SAT_F64, I64_TRUNC_S_SAT_F64_S },
10034 { I64_TRUNC_U_F32, I64_TRUNC_U_F32_S },
10035 { I64_TRUNC_U_F64, I64_TRUNC_U_F64_S },
10036 { I64_TRUNC_U_SAT_F32, I64_TRUNC_U_SAT_F32_S },
10037 { I64_TRUNC_U_SAT_F64, I64_TRUNC_U_SAT_F64_S },
10038 { IF, IF_S },
10039 { LANESELECT_I16x8, LANESELECT_I16x8_S },
10040 { LANESELECT_I32x4, LANESELECT_I32x4_S },
10041 { LANESELECT_I64x2, LANESELECT_I64x2_S },
10042 { LANESELECT_I8x16, LANESELECT_I8x16_S },
10043 { LE_F16x8, LE_F16x8_S },
10044 { LE_F32, LE_F32_S },
10045 { LE_F32x4, LE_F32x4_S },
10046 { LE_F64, LE_F64_S },
10047 { LE_F64x2, LE_F64x2_S },
10048 { LE_S_I16x8, LE_S_I16x8_S },
10049 { LE_S_I32, LE_S_I32_S },
10050 { LE_S_I32x4, LE_S_I32x4_S },
10051 { LE_S_I64, LE_S_I64_S },
10052 { LE_S_I64x2, LE_S_I64x2_S },
10053 { LE_S_I8x16, LE_S_I8x16_S },
10054 { LE_U_I16x8, LE_U_I16x8_S },
10055 { LE_U_I32, LE_U_I32_S },
10056 { LE_U_I32x4, LE_U_I32x4_S },
10057 { LE_U_I64, LE_U_I64_S },
10058 { LE_U_I8x16, LE_U_I8x16_S },
10059 { LOAD16_SPLAT_A32, LOAD16_SPLAT_A32_S },
10060 { LOAD16_SPLAT_A64, LOAD16_SPLAT_A64_S },
10061 { LOAD16_S_I32_A32, LOAD16_S_I32_A32_S },
10062 { LOAD16_S_I32_A64, LOAD16_S_I32_A64_S },
10063 { LOAD16_S_I64_A32, LOAD16_S_I64_A32_S },
10064 { LOAD16_S_I64_A64, LOAD16_S_I64_A64_S },
10065 { LOAD16_U_I32_A32, LOAD16_U_I32_A32_S },
10066 { LOAD16_U_I32_A64, LOAD16_U_I32_A64_S },
10067 { LOAD16_U_I64_A32, LOAD16_U_I64_A32_S },
10068 { LOAD16_U_I64_A64, LOAD16_U_I64_A64_S },
10069 { LOAD32_SPLAT_A32, LOAD32_SPLAT_A32_S },
10070 { LOAD32_SPLAT_A64, LOAD32_SPLAT_A64_S },
10071 { LOAD32_S_I64_A32, LOAD32_S_I64_A32_S },
10072 { LOAD32_S_I64_A64, LOAD32_S_I64_A64_S },
10073 { LOAD32_U_I64_A32, LOAD32_U_I64_A32_S },
10074 { LOAD32_U_I64_A64, LOAD32_U_I64_A64_S },
10075 { LOAD64_SPLAT_A32, LOAD64_SPLAT_A32_S },
10076 { LOAD64_SPLAT_A64, LOAD64_SPLAT_A64_S },
10077 { LOAD8_SPLAT_A32, LOAD8_SPLAT_A32_S },
10078 { LOAD8_SPLAT_A64, LOAD8_SPLAT_A64_S },
10079 { LOAD8_S_I32_A32, LOAD8_S_I32_A32_S },
10080 { LOAD8_S_I32_A64, LOAD8_S_I32_A64_S },
10081 { LOAD8_S_I64_A32, LOAD8_S_I64_A32_S },
10082 { LOAD8_S_I64_A64, LOAD8_S_I64_A64_S },
10083 { LOAD8_U_I32_A32, LOAD8_U_I32_A32_S },
10084 { LOAD8_U_I32_A64, LOAD8_U_I32_A64_S },
10085 { LOAD8_U_I64_A32, LOAD8_U_I64_A32_S },
10086 { LOAD8_U_I64_A64, LOAD8_U_I64_A64_S },
10087 { LOAD_EXTEND_S_I16x8_A32, LOAD_EXTEND_S_I16x8_A32_S },
10088 { LOAD_EXTEND_S_I16x8_A64, LOAD_EXTEND_S_I16x8_A64_S },
10089 { LOAD_EXTEND_S_I32x4_A32, LOAD_EXTEND_S_I32x4_A32_S },
10090 { LOAD_EXTEND_S_I32x4_A64, LOAD_EXTEND_S_I32x4_A64_S },
10091 { LOAD_EXTEND_S_I64x2_A32, LOAD_EXTEND_S_I64x2_A32_S },
10092 { LOAD_EXTEND_S_I64x2_A64, LOAD_EXTEND_S_I64x2_A64_S },
10093 { LOAD_EXTEND_U_I16x8_A32, LOAD_EXTEND_U_I16x8_A32_S },
10094 { LOAD_EXTEND_U_I16x8_A64, LOAD_EXTEND_U_I16x8_A64_S },
10095 { LOAD_EXTEND_U_I32x4_A32, LOAD_EXTEND_U_I32x4_A32_S },
10096 { LOAD_EXTEND_U_I32x4_A64, LOAD_EXTEND_U_I32x4_A64_S },
10097 { LOAD_EXTEND_U_I64x2_A32, LOAD_EXTEND_U_I64x2_A32_S },
10098 { LOAD_EXTEND_U_I64x2_A64, LOAD_EXTEND_U_I64x2_A64_S },
10099 { LOAD_F16_F32_A32, LOAD_F16_F32_A32_S },
10100 { LOAD_F16_F32_A64, LOAD_F16_F32_A64_S },
10101 { LOAD_F32_A32, LOAD_F32_A32_S },
10102 { LOAD_F32_A64, LOAD_F32_A64_S },
10103 { LOAD_F64_A32, LOAD_F64_A32_S },
10104 { LOAD_F64_A64, LOAD_F64_A64_S },
10105 { LOAD_I32_A32, LOAD_I32_A32_S },
10106 { LOAD_I32_A64, LOAD_I32_A64_S },
10107 { LOAD_I64_A32, LOAD_I64_A32_S },
10108 { LOAD_I64_A64, LOAD_I64_A64_S },
10109 { LOAD_LANE_16_A32, LOAD_LANE_16_A32_S },
10110 { LOAD_LANE_16_A64, LOAD_LANE_16_A64_S },
10111 { LOAD_LANE_32_A32, LOAD_LANE_32_A32_S },
10112 { LOAD_LANE_32_A64, LOAD_LANE_32_A64_S },
10113 { LOAD_LANE_64_A32, LOAD_LANE_64_A32_S },
10114 { LOAD_LANE_64_A64, LOAD_LANE_64_A64_S },
10115 { LOAD_LANE_8_A32, LOAD_LANE_8_A32_S },
10116 { LOAD_LANE_8_A64, LOAD_LANE_8_A64_S },
10117 { LOAD_V128_A32, LOAD_V128_A32_S },
10118 { LOAD_V128_A64, LOAD_V128_A64_S },
10119 { LOAD_ZERO_32_A32, LOAD_ZERO_32_A32_S },
10120 { LOAD_ZERO_32_A64, LOAD_ZERO_32_A64_S },
10121 { LOAD_ZERO_64_A32, LOAD_ZERO_64_A32_S },
10122 { LOAD_ZERO_64_A64, LOAD_ZERO_64_A64_S },
10123 { LOCAL_GET_EXNREF, LOCAL_GET_EXNREF_S },
10124 { LOCAL_GET_EXTERNREF, LOCAL_GET_EXTERNREF_S },
10125 { LOCAL_GET_F32, LOCAL_GET_F32_S },
10126 { LOCAL_GET_F64, LOCAL_GET_F64_S },
10127 { LOCAL_GET_FUNCREF, LOCAL_GET_FUNCREF_S },
10128 { LOCAL_GET_I32, LOCAL_GET_I32_S },
10129 { LOCAL_GET_I64, LOCAL_GET_I64_S },
10130 { LOCAL_GET_V128, LOCAL_GET_V128_S },
10131 { LOCAL_SET_EXNREF, LOCAL_SET_EXNREF_S },
10132 { LOCAL_SET_EXTERNREF, LOCAL_SET_EXTERNREF_S },
10133 { LOCAL_SET_F32, LOCAL_SET_F32_S },
10134 { LOCAL_SET_F64, LOCAL_SET_F64_S },
10135 { LOCAL_SET_FUNCREF, LOCAL_SET_FUNCREF_S },
10136 { LOCAL_SET_I32, LOCAL_SET_I32_S },
10137 { LOCAL_SET_I64, LOCAL_SET_I64_S },
10138 { LOCAL_SET_V128, LOCAL_SET_V128_S },
10139 { LOCAL_TEE_EXNREF, LOCAL_TEE_EXNREF_S },
10140 { LOCAL_TEE_EXTERNREF, LOCAL_TEE_EXTERNREF_S },
10141 { LOCAL_TEE_F32, LOCAL_TEE_F32_S },
10142 { LOCAL_TEE_F64, LOCAL_TEE_F64_S },
10143 { LOCAL_TEE_FUNCREF, LOCAL_TEE_FUNCREF_S },
10144 { LOCAL_TEE_I32, LOCAL_TEE_I32_S },
10145 { LOCAL_TEE_I64, LOCAL_TEE_I64_S },
10146 { LOCAL_TEE_V128, LOCAL_TEE_V128_S },
10147 { LOOP, LOOP_S },
10148 { LT_F16x8, LT_F16x8_S },
10149 { LT_F32, LT_F32_S },
10150 { LT_F32x4, LT_F32x4_S },
10151 { LT_F64, LT_F64_S },
10152 { LT_F64x2, LT_F64x2_S },
10153 { LT_S_I16x8, LT_S_I16x8_S },
10154 { LT_S_I32, LT_S_I32_S },
10155 { LT_S_I32x4, LT_S_I32x4_S },
10156 { LT_S_I64, LT_S_I64_S },
10157 { LT_S_I64x2, LT_S_I64x2_S },
10158 { LT_S_I8x16, LT_S_I8x16_S },
10159 { LT_U_I16x8, LT_U_I16x8_S },
10160 { LT_U_I32, LT_U_I32_S },
10161 { LT_U_I32x4, LT_U_I32x4_S },
10162 { LT_U_I64, LT_U_I64_S },
10163 { LT_U_I8x16, LT_U_I8x16_S },
10164 { MADD_F16x8, MADD_F16x8_S },
10165 { MADD_F32x4, MADD_F32x4_S },
10166 { MADD_F64x2, MADD_F64x2_S },
10167 { MAX_F16x8, MAX_F16x8_S },
10168 { MAX_F32, MAX_F32_S },
10169 { MAX_F32x4, MAX_F32x4_S },
10170 { MAX_F64, MAX_F64_S },
10171 { MAX_F64x2, MAX_F64x2_S },
10172 { MAX_S_I16x8, MAX_S_I16x8_S },
10173 { MAX_S_I32x4, MAX_S_I32x4_S },
10174 { MAX_S_I8x16, MAX_S_I8x16_S },
10175 { MAX_U_I16x8, MAX_U_I16x8_S },
10176 { MAX_U_I32x4, MAX_U_I32x4_S },
10177 { MAX_U_I8x16, MAX_U_I8x16_S },
10178 { MEMCPY_A32, MEMCPY_A32_S },
10179 { MEMCPY_A64, MEMCPY_A64_S },
10180 { MEMORY_ATOMIC_NOTIFY_A32, MEMORY_ATOMIC_NOTIFY_A32_S },
10181 { MEMORY_ATOMIC_NOTIFY_A64, MEMORY_ATOMIC_NOTIFY_A64_S },
10182 { MEMORY_ATOMIC_WAIT32_A32, MEMORY_ATOMIC_WAIT32_A32_S },
10183 { MEMORY_ATOMIC_WAIT32_A64, MEMORY_ATOMIC_WAIT32_A64_S },
10184 { MEMORY_ATOMIC_WAIT64_A32, MEMORY_ATOMIC_WAIT64_A32_S },
10185 { MEMORY_ATOMIC_WAIT64_A64, MEMORY_ATOMIC_WAIT64_A64_S },
10186 { MEMORY_COPY_A32, MEMORY_COPY_A32_S },
10187 { MEMORY_COPY_A64, MEMORY_COPY_A64_S },
10188 { MEMORY_FILL_A32, MEMORY_FILL_A32_S },
10189 { MEMORY_FILL_A64, MEMORY_FILL_A64_S },
10190 { MEMORY_INIT_A32, MEMORY_INIT_A32_S },
10191 { MEMORY_INIT_A64, MEMORY_INIT_A64_S },
10192 { MEMSET_A32, MEMSET_A32_S },
10193 { MEMSET_A64, MEMSET_A64_S },
10194 { MIN_F16x8, MIN_F16x8_S },
10195 { MIN_F32, MIN_F32_S },
10196 { MIN_F32x4, MIN_F32x4_S },
10197 { MIN_F64, MIN_F64_S },
10198 { MIN_F64x2, MIN_F64x2_S },
10199 { MIN_S_I16x8, MIN_S_I16x8_S },
10200 { MIN_S_I32x4, MIN_S_I32x4_S },
10201 { MIN_S_I8x16, MIN_S_I8x16_S },
10202 { MIN_U_I16x8, MIN_U_I16x8_S },
10203 { MIN_U_I32x4, MIN_U_I32x4_S },
10204 { MIN_U_I8x16, MIN_U_I8x16_S },
10205 { MUL_F16x8, MUL_F16x8_S },
10206 { MUL_F32, MUL_F32_S },
10207 { MUL_F32x4, MUL_F32x4_S },
10208 { MUL_F64, MUL_F64_S },
10209 { MUL_F64x2, MUL_F64x2_S },
10210 { MUL_I16x8, MUL_I16x8_S },
10211 { MUL_I32, MUL_I32_S },
10212 { MUL_I32x4, MUL_I32x4_S },
10213 { MUL_I64, MUL_I64_S },
10214 { MUL_I64x2, MUL_I64x2_S },
10215 { NARROW_S_I16x8, NARROW_S_I16x8_S },
10216 { NARROW_S_I8x16, NARROW_S_I8x16_S },
10217 { NARROW_U_I16x8, NARROW_U_I16x8_S },
10218 { NARROW_U_I8x16, NARROW_U_I8x16_S },
10219 { NEAREST_F16x8, NEAREST_F16x8_S },
10220 { NEAREST_F32, NEAREST_F32_S },
10221 { NEAREST_F32x4, NEAREST_F32x4_S },
10222 { NEAREST_F64, NEAREST_F64_S },
10223 { NEAREST_F64x2, NEAREST_F64x2_S },
10224 { NEG_F16x8, NEG_F16x8_S },
10225 { NEG_F32, NEG_F32_S },
10226 { NEG_F32x4, NEG_F32x4_S },
10227 { NEG_F64, NEG_F64_S },
10228 { NEG_F64x2, NEG_F64x2_S },
10229 { NEG_I16x8, NEG_I16x8_S },
10230 { NEG_I32x4, NEG_I32x4_S },
10231 { NEG_I64x2, NEG_I64x2_S },
10232 { NEG_I8x16, NEG_I8x16_S },
10233 { NE_F16x8, NE_F16x8_S },
10234 { NE_F32, NE_F32_S },
10235 { NE_F32x4, NE_F32x4_S },
10236 { NE_F64, NE_F64_S },
10237 { NE_F64x2, NE_F64x2_S },
10238 { NE_I16x8, NE_I16x8_S },
10239 { NE_I32, NE_I32_S },
10240 { NE_I32x4, NE_I32x4_S },
10241 { NE_I64, NE_I64_S },
10242 { NE_I64x2, NE_I64x2_S },
10243 { NE_I8x16, NE_I8x16_S },
10244 { NMADD_F16x8, NMADD_F16x8_S },
10245 { NMADD_F32x4, NMADD_F32x4_S },
10246 { NMADD_F64x2, NMADD_F64x2_S },
10247 { NOP, NOP_S },
10248 { NOT, NOT_S },
10249 { OR, OR_S },
10250 { OR_I32, OR_I32_S },
10251 { OR_I64, OR_I64_S },
10252 { PMAX_F16x8, PMAX_F16x8_S },
10253 { PMAX_F32x4, PMAX_F32x4_S },
10254 { PMAX_F64x2, PMAX_F64x2_S },
10255 { PMIN_F16x8, PMIN_F16x8_S },
10256 { PMIN_F32x4, PMIN_F32x4_S },
10257 { PMIN_F64x2, PMIN_F64x2_S },
10258 { POPCNT_I32, POPCNT_I32_S },
10259 { POPCNT_I64, POPCNT_I64_S },
10260 { POPCNT_I8x16, POPCNT_I8x16_S },
10261 { Q15MULR_SAT_S_I16x8, Q15MULR_SAT_S_I16x8_S },
10262 { REF_FUNC, REF_FUNC_S },
10263 { REF_IS_NULL_EXNREF, REF_IS_NULL_EXNREF_S },
10264 { REF_IS_NULL_EXTERNREF, REF_IS_NULL_EXTERNREF_S },
10265 { REF_IS_NULL_FUNCREF, REF_IS_NULL_FUNCREF_S },
10266 { REF_NULL_EXNREF, REF_NULL_EXNREF_S },
10267 { REF_NULL_EXTERNREF, REF_NULL_EXTERNREF_S },
10268 { REF_NULL_FUNCREF, REF_NULL_FUNCREF_S },
10269 { REF_TEST_FUNCREF, REF_TEST_FUNCREF_S },
10270 { RELAXED_DOT, RELAXED_DOT_S },
10271 { RELAXED_DOT_ADD, RELAXED_DOT_ADD_S },
10272 { RELAXED_DOT_BFLOAT, RELAXED_DOT_BFLOAT_S },
10273 { RELAXED_Q15MULR_S_I16x8, RELAXED_Q15MULR_S_I16x8_S },
10274 { RELAXED_SWIZZLE, RELAXED_SWIZZLE_S },
10275 { REM_S_I32, REM_S_I32_S },
10276 { REM_S_I64, REM_S_I64_S },
10277 { REM_U_I32, REM_U_I32_S },
10278 { REM_U_I64, REM_U_I64_S },
10279 { REPLACE_LANE_F16x8, REPLACE_LANE_F16x8_S },
10280 { REPLACE_LANE_F32x4, REPLACE_LANE_F32x4_S },
10281 { REPLACE_LANE_F64x2, REPLACE_LANE_F64x2_S },
10282 { REPLACE_LANE_I16x8, REPLACE_LANE_I16x8_S },
10283 { REPLACE_LANE_I32x4, REPLACE_LANE_I32x4_S },
10284 { REPLACE_LANE_I64x2, REPLACE_LANE_I64x2_S },
10285 { REPLACE_LANE_I8x16, REPLACE_LANE_I8x16_S },
10286 { RETHROW, RETHROW_S },
10287 { RETURN, RETURN_S },
10288 { RET_CALL, RET_CALL_S },
10289 { RET_CALL_INDIRECT, RET_CALL_INDIRECT_S },
10290 { ROTL_I32, ROTL_I32_S },
10291 { ROTL_I64, ROTL_I64_S },
10292 { ROTR_I32, ROTR_I32_S },
10293 { ROTR_I64, ROTR_I64_S },
10294 { SELECT_EXNREF, SELECT_EXNREF_S },
10295 { SELECT_EXTERNREF, SELECT_EXTERNREF_S },
10296 { SELECT_F32, SELECT_F32_S },
10297 { SELECT_F64, SELECT_F64_S },
10298 { SELECT_FUNCREF, SELECT_FUNCREF_S },
10299 { SELECT_I32, SELECT_I32_S },
10300 { SELECT_I64, SELECT_I64_S },
10301 { SELECT_V128, SELECT_V128_S },
10302 { SHL_I16x8, SHL_I16x8_S },
10303 { SHL_I32, SHL_I32_S },
10304 { SHL_I32x4, SHL_I32x4_S },
10305 { SHL_I64, SHL_I64_S },
10306 { SHL_I64x2, SHL_I64x2_S },
10307 { SHL_I8x16, SHL_I8x16_S },
10308 { SHR_S_I16x8, SHR_S_I16x8_S },
10309 { SHR_S_I32, SHR_S_I32_S },
10310 { SHR_S_I32x4, SHR_S_I32x4_S },
10311 { SHR_S_I64, SHR_S_I64_S },
10312 { SHR_S_I64x2, SHR_S_I64x2_S },
10313 { SHR_S_I8x16, SHR_S_I8x16_S },
10314 { SHR_U_I16x8, SHR_U_I16x8_S },
10315 { SHR_U_I32, SHR_U_I32_S },
10316 { SHR_U_I32x4, SHR_U_I32x4_S },
10317 { SHR_U_I64, SHR_U_I64_S },
10318 { SHR_U_I64x2, SHR_U_I64x2_S },
10319 { SHR_U_I8x16, SHR_U_I8x16_S },
10320 { SHUFFLE, SHUFFLE_S },
10321 { SIMD_RELAXED_FMAX_F32x4, SIMD_RELAXED_FMAX_F32x4_S },
10322 { SIMD_RELAXED_FMAX_F64x2, SIMD_RELAXED_FMAX_F64x2_S },
10323 { SIMD_RELAXED_FMIN_F32x4, SIMD_RELAXED_FMIN_F32x4_S },
10324 { SIMD_RELAXED_FMIN_F64x2, SIMD_RELAXED_FMIN_F64x2_S },
10325 { SPLAT_F16x8, SPLAT_F16x8_S },
10326 { SPLAT_F32x4, SPLAT_F32x4_S },
10327 { SPLAT_F64x2, SPLAT_F64x2_S },
10328 { SPLAT_I16x8, SPLAT_I16x8_S },
10329 { SPLAT_I32x4, SPLAT_I32x4_S },
10330 { SPLAT_I64x2, SPLAT_I64x2_S },
10331 { SPLAT_I8x16, SPLAT_I8x16_S },
10332 { SQRT_F16x8, SQRT_F16x8_S },
10333 { SQRT_F32, SQRT_F32_S },
10334 { SQRT_F32x4, SQRT_F32x4_S },
10335 { SQRT_F64, SQRT_F64_S },
10336 { SQRT_F64x2, SQRT_F64x2_S },
10337 { STORE16_I32_A32, STORE16_I32_A32_S },
10338 { STORE16_I32_A64, STORE16_I32_A64_S },
10339 { STORE16_I64_A32, STORE16_I64_A32_S },
10340 { STORE16_I64_A64, STORE16_I64_A64_S },
10341 { STORE32_I64_A32, STORE32_I64_A32_S },
10342 { STORE32_I64_A64, STORE32_I64_A64_S },
10343 { STORE8_I32_A32, STORE8_I32_A32_S },
10344 { STORE8_I32_A64, STORE8_I32_A64_S },
10345 { STORE8_I64_A32, STORE8_I64_A32_S },
10346 { STORE8_I64_A64, STORE8_I64_A64_S },
10347 { STORE_F16_F32_A32, STORE_F16_F32_A32_S },
10348 { STORE_F16_F32_A64, STORE_F16_F32_A64_S },
10349 { STORE_F32_A32, STORE_F32_A32_S },
10350 { STORE_F32_A64, STORE_F32_A64_S },
10351 { STORE_F64_A32, STORE_F64_A32_S },
10352 { STORE_F64_A64, STORE_F64_A64_S },
10353 { STORE_I32_A32, STORE_I32_A32_S },
10354 { STORE_I32_A64, STORE_I32_A64_S },
10355 { STORE_I64_A32, STORE_I64_A32_S },
10356 { STORE_I64_A64, STORE_I64_A64_S },
10357 { STORE_LANE_I16x8_A32, STORE_LANE_I16x8_A32_S },
10358 { STORE_LANE_I16x8_A64, STORE_LANE_I16x8_A64_S },
10359 { STORE_LANE_I32x4_A32, STORE_LANE_I32x4_A32_S },
10360 { STORE_LANE_I32x4_A64, STORE_LANE_I32x4_A64_S },
10361 { STORE_LANE_I64x2_A32, STORE_LANE_I64x2_A32_S },
10362 { STORE_LANE_I64x2_A64, STORE_LANE_I64x2_A64_S },
10363 { STORE_LANE_I8x16_A32, STORE_LANE_I8x16_A32_S },
10364 { STORE_LANE_I8x16_A64, STORE_LANE_I8x16_A64_S },
10365 { STORE_V128_A32, STORE_V128_A32_S },
10366 { STORE_V128_A64, STORE_V128_A64_S },
10367 { SUB_F16x8, SUB_F16x8_S },
10368 { SUB_F32, SUB_F32_S },
10369 { SUB_F32x4, SUB_F32x4_S },
10370 { SUB_F64, SUB_F64_S },
10371 { SUB_F64x2, SUB_F64x2_S },
10372 { SUB_I16x8, SUB_I16x8_S },
10373 { SUB_I32, SUB_I32_S },
10374 { SUB_I32x4, SUB_I32x4_S },
10375 { SUB_I64, SUB_I64_S },
10376 { SUB_I64x2, SUB_I64x2_S },
10377 { SUB_I8x16, SUB_I8x16_S },
10378 { SUB_SAT_S_I16x8, SUB_SAT_S_I16x8_S },
10379 { SUB_SAT_S_I8x16, SUB_SAT_S_I8x16_S },
10380 { SUB_SAT_U_I16x8, SUB_SAT_U_I16x8_S },
10381 { SUB_SAT_U_I8x16, SUB_SAT_U_I8x16_S },
10382 { SWIZZLE, SWIZZLE_S },
10383 { TABLE_COPY, TABLE_COPY_S },
10384 { TABLE_FILL_EXNREF, TABLE_FILL_EXNREF_S },
10385 { TABLE_FILL_EXTERNREF, TABLE_FILL_EXTERNREF_S },
10386 { TABLE_FILL_FUNCREF, TABLE_FILL_FUNCREF_S },
10387 { TABLE_GET_EXNREF, TABLE_GET_EXNREF_S },
10388 { TABLE_GET_EXTERNREF, TABLE_GET_EXTERNREF_S },
10389 { TABLE_GET_FUNCREF, TABLE_GET_FUNCREF_S },
10390 { TABLE_GROW_EXNREF, TABLE_GROW_EXNREF_S },
10391 { TABLE_GROW_EXTERNREF, TABLE_GROW_EXTERNREF_S },
10392 { TABLE_GROW_FUNCREF, TABLE_GROW_FUNCREF_S },
10393 { TABLE_SET_EXNREF, TABLE_SET_EXNREF_S },
10394 { TABLE_SET_EXTERNREF, TABLE_SET_EXTERNREF_S },
10395 { TABLE_SET_FUNCREF, TABLE_SET_FUNCREF_S },
10396 { TABLE_SIZE, TABLE_SIZE_S },
10397 { TEE_EXNREF, TEE_EXNREF_S },
10398 { TEE_EXTERNREF, TEE_EXTERNREF_S },
10399 { TEE_F32, TEE_F32_S },
10400 { TEE_F64, TEE_F64_S },
10401 { TEE_FUNCREF, TEE_FUNCREF_S },
10402 { TEE_I32, TEE_I32_S },
10403 { TEE_I64, TEE_I64_S },
10404 { TEE_V128, TEE_V128_S },
10405 { THROW, THROW_S },
10406 { THROW_REF, THROW_REF_S },
10407 { TRUNC_F16x8, TRUNC_F16x8_S },
10408 { TRUNC_F32, TRUNC_F32_S },
10409 { TRUNC_F32x4, TRUNC_F32x4_S },
10410 { TRUNC_F64, TRUNC_F64_S },
10411 { TRUNC_F64x2, TRUNC_F64x2_S },
10412 { TRY, TRY_S },
10413 { TRY_TABLE, TRY_TABLE_S },
10414 { UNREACHABLE, UNREACHABLE_S },
10415 { XOR, XOR_S },
10416 { XOR_I32, XOR_I32_S },
10417 { XOR_I64, XOR_I64_S },
10418 { anonymous_14734MEMORY_GROW_A32, anonymous_14734MEMORY_GROW_A32_S },
10419 { anonymous_14734MEMORY_SIZE_A32, anonymous_14734MEMORY_SIZE_A32_S },
10420 { anonymous_14735MEMORY_GROW_A64, anonymous_14735MEMORY_GROW_A64_S },
10421 { anonymous_14735MEMORY_SIZE_A64, anonymous_14735MEMORY_SIZE_A64_S },
10422 { convert_low_s_F64x2, convert_low_s_F64x2_S },
10423 { convert_low_u_F64x2, convert_low_u_F64x2_S },
10424 { demote_zero_F32x4, demote_zero_F32x4_S },
10425 { extadd_pairwise_s_I16x8, extadd_pairwise_s_I16x8_S },
10426 { extadd_pairwise_s_I32x4, extadd_pairwise_s_I32x4_S },
10427 { extadd_pairwise_u_I16x8, extadd_pairwise_u_I16x8_S },
10428 { extadd_pairwise_u_I32x4, extadd_pairwise_u_I32x4_S },
10429 { extend_high_s_I16x8, extend_high_s_I16x8_S },
10430 { extend_high_s_I32x4, extend_high_s_I32x4_S },
10431 { extend_high_s_I64x2, extend_high_s_I64x2_S },
10432 { extend_high_u_I16x8, extend_high_u_I16x8_S },
10433 { extend_high_u_I32x4, extend_high_u_I32x4_S },
10434 { extend_high_u_I64x2, extend_high_u_I64x2_S },
10435 { extend_low_s_I16x8, extend_low_s_I16x8_S },
10436 { extend_low_s_I32x4, extend_low_s_I32x4_S },
10437 { extend_low_s_I64x2, extend_low_s_I64x2_S },
10438 { extend_low_u_I16x8, extend_low_u_I16x8_S },
10439 { extend_low_u_I32x4, extend_low_u_I32x4_S },
10440 { extend_low_u_I64x2, extend_low_u_I64x2_S },
10441 { fp_to_sint_I16x8, fp_to_sint_I16x8_S },
10442 { fp_to_sint_I32x4, fp_to_sint_I32x4_S },
10443 { fp_to_uint_I16x8, fp_to_uint_I16x8_S },
10444 { fp_to_uint_I32x4, fp_to_uint_I32x4_S },
10445 { int_wasm_relaxed_trunc_signed_I32x4, int_wasm_relaxed_trunc_signed_I32x4_S },
10446 { int_wasm_relaxed_trunc_signed_zero_I32x4, int_wasm_relaxed_trunc_signed_zero_I32x4_S },
10447 { int_wasm_relaxed_trunc_unsigned_I32x4, int_wasm_relaxed_trunc_unsigned_I32x4_S },
10448 { int_wasm_relaxed_trunc_unsigned_zero_I32x4, int_wasm_relaxed_trunc_unsigned_zero_I32x4_S },
10449 { promote_low_F64x2, promote_low_F64x2_S },
10450 { sint_to_fp_F16x8, sint_to_fp_F16x8_S },
10451 { sint_to_fp_F32x4, sint_to_fp_F32x4_S },
10452 { trunc_sat_zero_s_I32x4, trunc_sat_zero_s_I32x4_S },
10453 { trunc_sat_zero_u_I32x4, trunc_sat_zero_u_I32x4_S },
10454 { uint_to_fp_F16x8, uint_to_fp_F16x8_S },
10455 { uint_to_fp_F32x4, uint_to_fp_F32x4_S },
10456 }; // End of Table
10457
10458 unsigned mid;
10459 unsigned start = 0;
10460 unsigned end = 817;
10461 while (start < end) {
10462 mid = start + (end - start) / 2;
10463 if (Opcode == Table[mid][0])
10464 break;
10465 if (Opcode < Table[mid][0])
10466 end = mid;
10467 else
10468 start = mid + 1;
10469 }
10470 if (start == end)
10471 return -1; // Instruction doesn't exist in this table.
10472
10473 return Table[mid][1];
10474}
10475
10476// getWasm64Opcode
10477LLVM_READONLY
10478int getWasm64Opcode(uint16_t Opcode) {
10479 using namespace WebAssembly;
10480 static constexpr uint16_t Table[][2] = {
10481 { ATOMIC_LOAD16_U_I32_A32, ATOMIC_LOAD16_U_I32_A64 },
10482 { ATOMIC_LOAD16_U_I32_A32_S, ATOMIC_LOAD16_U_I32_A64_S },
10483 { ATOMIC_LOAD16_U_I64_A32, ATOMIC_LOAD16_U_I64_A64 },
10484 { ATOMIC_LOAD16_U_I64_A32_S, ATOMIC_LOAD16_U_I64_A64_S },
10485 { ATOMIC_LOAD32_U_I64_A32, ATOMIC_LOAD32_U_I64_A64 },
10486 { ATOMIC_LOAD32_U_I64_A32_S, ATOMIC_LOAD32_U_I64_A64_S },
10487 { ATOMIC_LOAD8_U_I32_A32, ATOMIC_LOAD8_U_I32_A64 },
10488 { ATOMIC_LOAD8_U_I32_A32_S, ATOMIC_LOAD8_U_I32_A64_S },
10489 { ATOMIC_LOAD8_U_I64_A32, ATOMIC_LOAD8_U_I64_A64 },
10490 { ATOMIC_LOAD8_U_I64_A32_S, ATOMIC_LOAD8_U_I64_A64_S },
10491 { ATOMIC_LOAD_I32_A32, ATOMIC_LOAD_I32_A64 },
10492 { ATOMIC_LOAD_I32_A32_S, ATOMIC_LOAD_I32_A64_S },
10493 { ATOMIC_LOAD_I64_A32, ATOMIC_LOAD_I64_A64 },
10494 { ATOMIC_LOAD_I64_A32_S, ATOMIC_LOAD_I64_A64_S },
10495 { ATOMIC_RMW16_U_ADD_I32_A32, ATOMIC_RMW16_U_ADD_I32_A64 },
10496 { ATOMIC_RMW16_U_ADD_I32_A32_S, ATOMIC_RMW16_U_ADD_I32_A64_S },
10497 { ATOMIC_RMW16_U_ADD_I64_A32, ATOMIC_RMW16_U_ADD_I64_A64 },
10498 { ATOMIC_RMW16_U_ADD_I64_A32_S, ATOMIC_RMW16_U_ADD_I64_A64_S },
10499 { ATOMIC_RMW16_U_AND_I32_A32, ATOMIC_RMW16_U_AND_I32_A64 },
10500 { ATOMIC_RMW16_U_AND_I32_A32_S, ATOMIC_RMW16_U_AND_I32_A64_S },
10501 { ATOMIC_RMW16_U_AND_I64_A32, ATOMIC_RMW16_U_AND_I64_A64 },
10502 { ATOMIC_RMW16_U_AND_I64_A32_S, ATOMIC_RMW16_U_AND_I64_A64_S },
10503 { ATOMIC_RMW16_U_CMPXCHG_I32_A32, ATOMIC_RMW16_U_CMPXCHG_I32_A64 },
10504 { ATOMIC_RMW16_U_CMPXCHG_I32_A32_S, ATOMIC_RMW16_U_CMPXCHG_I32_A64_S },
10505 { ATOMIC_RMW16_U_CMPXCHG_I64_A32, ATOMIC_RMW16_U_CMPXCHG_I64_A64 },
10506 { ATOMIC_RMW16_U_CMPXCHG_I64_A32_S, ATOMIC_RMW16_U_CMPXCHG_I64_A64_S },
10507 { ATOMIC_RMW16_U_OR_I32_A32, ATOMIC_RMW16_U_OR_I32_A64 },
10508 { ATOMIC_RMW16_U_OR_I32_A32_S, ATOMIC_RMW16_U_OR_I32_A64_S },
10509 { ATOMIC_RMW16_U_OR_I64_A32, ATOMIC_RMW16_U_OR_I64_A64 },
10510 { ATOMIC_RMW16_U_OR_I64_A32_S, ATOMIC_RMW16_U_OR_I64_A64_S },
10511 { ATOMIC_RMW16_U_SUB_I32_A32, ATOMIC_RMW16_U_SUB_I32_A64 },
10512 { ATOMIC_RMW16_U_SUB_I32_A32_S, ATOMIC_RMW16_U_SUB_I32_A64_S },
10513 { ATOMIC_RMW16_U_SUB_I64_A32, ATOMIC_RMW16_U_SUB_I64_A64 },
10514 { ATOMIC_RMW16_U_SUB_I64_A32_S, ATOMIC_RMW16_U_SUB_I64_A64_S },
10515 { ATOMIC_RMW16_U_XCHG_I32_A32, ATOMIC_RMW16_U_XCHG_I32_A64 },
10516 { ATOMIC_RMW16_U_XCHG_I32_A32_S, ATOMIC_RMW16_U_XCHG_I32_A64_S },
10517 { ATOMIC_RMW16_U_XCHG_I64_A32, ATOMIC_RMW16_U_XCHG_I64_A64 },
10518 { ATOMIC_RMW16_U_XCHG_I64_A32_S, ATOMIC_RMW16_U_XCHG_I64_A64_S },
10519 { ATOMIC_RMW16_U_XOR_I32_A32, ATOMIC_RMW16_U_XOR_I32_A64 },
10520 { ATOMIC_RMW16_U_XOR_I32_A32_S, ATOMIC_RMW16_U_XOR_I32_A64_S },
10521 { ATOMIC_RMW16_U_XOR_I64_A32, ATOMIC_RMW16_U_XOR_I64_A64 },
10522 { ATOMIC_RMW16_U_XOR_I64_A32_S, ATOMIC_RMW16_U_XOR_I64_A64_S },
10523 { ATOMIC_RMW32_U_ADD_I64_A32, ATOMIC_RMW32_U_ADD_I64_A64 },
10524 { ATOMIC_RMW32_U_ADD_I64_A32_S, ATOMIC_RMW32_U_ADD_I64_A64_S },
10525 { ATOMIC_RMW32_U_AND_I64_A32, ATOMIC_RMW32_U_AND_I64_A64 },
10526 { ATOMIC_RMW32_U_AND_I64_A32_S, ATOMIC_RMW32_U_AND_I64_A64_S },
10527 { ATOMIC_RMW32_U_CMPXCHG_I64_A32, ATOMIC_RMW32_U_CMPXCHG_I64_A64 },
10528 { ATOMIC_RMW32_U_CMPXCHG_I64_A32_S, ATOMIC_RMW32_U_CMPXCHG_I64_A64_S },
10529 { ATOMIC_RMW32_U_OR_I64_A32, ATOMIC_RMW32_U_OR_I64_A64 },
10530 { ATOMIC_RMW32_U_OR_I64_A32_S, ATOMIC_RMW32_U_OR_I64_A64_S },
10531 { ATOMIC_RMW32_U_SUB_I64_A32, ATOMIC_RMW32_U_SUB_I64_A64 },
10532 { ATOMIC_RMW32_U_SUB_I64_A32_S, ATOMIC_RMW32_U_SUB_I64_A64_S },
10533 { ATOMIC_RMW32_U_XCHG_I64_A32, ATOMIC_RMW32_U_XCHG_I64_A64 },
10534 { ATOMIC_RMW32_U_XCHG_I64_A32_S, ATOMIC_RMW32_U_XCHG_I64_A64_S },
10535 { ATOMIC_RMW32_U_XOR_I64_A32, ATOMIC_RMW32_U_XOR_I64_A64 },
10536 { ATOMIC_RMW32_U_XOR_I64_A32_S, ATOMIC_RMW32_U_XOR_I64_A64_S },
10537 { ATOMIC_RMW8_U_ADD_I32_A32, ATOMIC_RMW8_U_ADD_I32_A64 },
10538 { ATOMIC_RMW8_U_ADD_I32_A32_S, ATOMIC_RMW8_U_ADD_I32_A64_S },
10539 { ATOMIC_RMW8_U_ADD_I64_A32, ATOMIC_RMW8_U_ADD_I64_A64 },
10540 { ATOMIC_RMW8_U_ADD_I64_A32_S, ATOMIC_RMW8_U_ADD_I64_A64_S },
10541 { ATOMIC_RMW8_U_AND_I32_A32, ATOMIC_RMW8_U_AND_I32_A64 },
10542 { ATOMIC_RMW8_U_AND_I32_A32_S, ATOMIC_RMW8_U_AND_I32_A64_S },
10543 { ATOMIC_RMW8_U_AND_I64_A32, ATOMIC_RMW8_U_AND_I64_A64 },
10544 { ATOMIC_RMW8_U_AND_I64_A32_S, ATOMIC_RMW8_U_AND_I64_A64_S },
10545 { ATOMIC_RMW8_U_CMPXCHG_I32_A32, ATOMIC_RMW8_U_CMPXCHG_I32_A64 },
10546 { ATOMIC_RMW8_U_CMPXCHG_I32_A32_S, ATOMIC_RMW8_U_CMPXCHG_I32_A64_S },
10547 { ATOMIC_RMW8_U_CMPXCHG_I64_A32, ATOMIC_RMW8_U_CMPXCHG_I64_A64 },
10548 { ATOMIC_RMW8_U_CMPXCHG_I64_A32_S, ATOMIC_RMW8_U_CMPXCHG_I64_A64_S },
10549 { ATOMIC_RMW8_U_OR_I32_A32, ATOMIC_RMW8_U_OR_I32_A64 },
10550 { ATOMIC_RMW8_U_OR_I32_A32_S, ATOMIC_RMW8_U_OR_I32_A64_S },
10551 { ATOMIC_RMW8_U_OR_I64_A32, ATOMIC_RMW8_U_OR_I64_A64 },
10552 { ATOMIC_RMW8_U_OR_I64_A32_S, ATOMIC_RMW8_U_OR_I64_A64_S },
10553 { ATOMIC_RMW8_U_SUB_I32_A32, ATOMIC_RMW8_U_SUB_I32_A64 },
10554 { ATOMIC_RMW8_U_SUB_I32_A32_S, ATOMIC_RMW8_U_SUB_I32_A64_S },
10555 { ATOMIC_RMW8_U_SUB_I64_A32, ATOMIC_RMW8_U_SUB_I64_A64 },
10556 { ATOMIC_RMW8_U_SUB_I64_A32_S, ATOMIC_RMW8_U_SUB_I64_A64_S },
10557 { ATOMIC_RMW8_U_XCHG_I32_A32, ATOMIC_RMW8_U_XCHG_I32_A64 },
10558 { ATOMIC_RMW8_U_XCHG_I32_A32_S, ATOMIC_RMW8_U_XCHG_I32_A64_S },
10559 { ATOMIC_RMW8_U_XCHG_I64_A32, ATOMIC_RMW8_U_XCHG_I64_A64 },
10560 { ATOMIC_RMW8_U_XCHG_I64_A32_S, ATOMIC_RMW8_U_XCHG_I64_A64_S },
10561 { ATOMIC_RMW8_U_XOR_I32_A32, ATOMIC_RMW8_U_XOR_I32_A64 },
10562 { ATOMIC_RMW8_U_XOR_I32_A32_S, ATOMIC_RMW8_U_XOR_I32_A64_S },
10563 { ATOMIC_RMW8_U_XOR_I64_A32, ATOMIC_RMW8_U_XOR_I64_A64 },
10564 { ATOMIC_RMW8_U_XOR_I64_A32_S, ATOMIC_RMW8_U_XOR_I64_A64_S },
10565 { ATOMIC_RMW_ADD_I32_A32, ATOMIC_RMW_ADD_I32_A64 },
10566 { ATOMIC_RMW_ADD_I32_A32_S, ATOMIC_RMW_ADD_I32_A64_S },
10567 { ATOMIC_RMW_ADD_I64_A32, ATOMIC_RMW_ADD_I64_A64 },
10568 { ATOMIC_RMW_ADD_I64_A32_S, ATOMIC_RMW_ADD_I64_A64_S },
10569 { ATOMIC_RMW_AND_I32_A32, ATOMIC_RMW_AND_I32_A64 },
10570 { ATOMIC_RMW_AND_I32_A32_S, ATOMIC_RMW_AND_I32_A64_S },
10571 { ATOMIC_RMW_AND_I64_A32, ATOMIC_RMW_AND_I64_A64 },
10572 { ATOMIC_RMW_AND_I64_A32_S, ATOMIC_RMW_AND_I64_A64_S },
10573 { ATOMIC_RMW_CMPXCHG_I32_A32, ATOMIC_RMW_CMPXCHG_I32_A64 },
10574 { ATOMIC_RMW_CMPXCHG_I32_A32_S, ATOMIC_RMW_CMPXCHG_I32_A64_S },
10575 { ATOMIC_RMW_CMPXCHG_I64_A32, ATOMIC_RMW_CMPXCHG_I64_A64 },
10576 { ATOMIC_RMW_CMPXCHG_I64_A32_S, ATOMIC_RMW_CMPXCHG_I64_A64_S },
10577 { ATOMIC_RMW_OR_I32_A32, ATOMIC_RMW_OR_I32_A64 },
10578 { ATOMIC_RMW_OR_I32_A32_S, ATOMIC_RMW_OR_I32_A64_S },
10579 { ATOMIC_RMW_OR_I64_A32, ATOMIC_RMW_OR_I64_A64 },
10580 { ATOMIC_RMW_OR_I64_A32_S, ATOMIC_RMW_OR_I64_A64_S },
10581 { ATOMIC_RMW_SUB_I32_A32, ATOMIC_RMW_SUB_I32_A64 },
10582 { ATOMIC_RMW_SUB_I32_A32_S, ATOMIC_RMW_SUB_I32_A64_S },
10583 { ATOMIC_RMW_SUB_I64_A32, ATOMIC_RMW_SUB_I64_A64 },
10584 { ATOMIC_RMW_SUB_I64_A32_S, ATOMIC_RMW_SUB_I64_A64_S },
10585 { ATOMIC_RMW_XCHG_I32_A32, ATOMIC_RMW_XCHG_I32_A64 },
10586 { ATOMIC_RMW_XCHG_I32_A32_S, ATOMIC_RMW_XCHG_I32_A64_S },
10587 { ATOMIC_RMW_XCHG_I64_A32, ATOMIC_RMW_XCHG_I64_A64 },
10588 { ATOMIC_RMW_XCHG_I64_A32_S, ATOMIC_RMW_XCHG_I64_A64_S },
10589 { ATOMIC_RMW_XOR_I32_A32, ATOMIC_RMW_XOR_I32_A64 },
10590 { ATOMIC_RMW_XOR_I32_A32_S, ATOMIC_RMW_XOR_I32_A64_S },
10591 { ATOMIC_RMW_XOR_I64_A32, ATOMIC_RMW_XOR_I64_A64 },
10592 { ATOMIC_RMW_XOR_I64_A32_S, ATOMIC_RMW_XOR_I64_A64_S },
10593 { ATOMIC_STORE16_I32_A32, ATOMIC_STORE16_I32_A64 },
10594 { ATOMIC_STORE16_I32_A32_S, ATOMIC_STORE16_I32_A64_S },
10595 { ATOMIC_STORE16_I64_A32, ATOMIC_STORE16_I64_A64 },
10596 { ATOMIC_STORE16_I64_A32_S, ATOMIC_STORE16_I64_A64_S },
10597 { ATOMIC_STORE32_I64_A32, ATOMIC_STORE32_I64_A64 },
10598 { ATOMIC_STORE32_I64_A32_S, ATOMIC_STORE32_I64_A64_S },
10599 { ATOMIC_STORE8_I32_A32, ATOMIC_STORE8_I32_A64 },
10600 { ATOMIC_STORE8_I32_A32_S, ATOMIC_STORE8_I32_A64_S },
10601 { ATOMIC_STORE8_I64_A32, ATOMIC_STORE8_I64_A64 },
10602 { ATOMIC_STORE8_I64_A32_S, ATOMIC_STORE8_I64_A64_S },
10603 { ATOMIC_STORE_I32_A32, ATOMIC_STORE_I32_A64 },
10604 { ATOMIC_STORE_I32_A32_S, ATOMIC_STORE_I32_A64_S },
10605 { ATOMIC_STORE_I64_A32, ATOMIC_STORE_I64_A64 },
10606 { ATOMIC_STORE_I64_A32_S, ATOMIC_STORE_I64_A64_S },
10607 { LOAD16_S_I32_A32, LOAD16_S_I32_A64 },
10608 { LOAD16_S_I32_A32_S, LOAD16_S_I32_A64_S },
10609 { LOAD16_S_I64_A32, LOAD16_S_I64_A64 },
10610 { LOAD16_S_I64_A32_S, LOAD16_S_I64_A64_S },
10611 { LOAD16_U_I32_A32, LOAD16_U_I32_A64 },
10612 { LOAD16_U_I32_A32_S, LOAD16_U_I32_A64_S },
10613 { LOAD16_U_I64_A32, LOAD16_U_I64_A64 },
10614 { LOAD16_U_I64_A32_S, LOAD16_U_I64_A64_S },
10615 { LOAD32_S_I64_A32, LOAD32_S_I64_A64 },
10616 { LOAD32_S_I64_A32_S, LOAD32_S_I64_A64_S },
10617 { LOAD32_U_I64_A32, LOAD32_U_I64_A64 },
10618 { LOAD32_U_I64_A32_S, LOAD32_U_I64_A64_S },
10619 { LOAD8_S_I32_A32, LOAD8_S_I32_A64 },
10620 { LOAD8_S_I32_A32_S, LOAD8_S_I32_A64_S },
10621 { LOAD8_S_I64_A32, LOAD8_S_I64_A64 },
10622 { LOAD8_S_I64_A32_S, LOAD8_S_I64_A64_S },
10623 { LOAD8_U_I32_A32, LOAD8_U_I32_A64 },
10624 { LOAD8_U_I32_A32_S, LOAD8_U_I32_A64_S },
10625 { LOAD8_U_I64_A32, LOAD8_U_I64_A64 },
10626 { LOAD8_U_I64_A32_S, LOAD8_U_I64_A64_S },
10627 { LOAD_F16_F32_A32, LOAD_F16_F32_A64 },
10628 { LOAD_F16_F32_A32_S, LOAD_F16_F32_A64_S },
10629 { LOAD_F32_A32, LOAD_F32_A64 },
10630 { LOAD_F32_A32_S, LOAD_F32_A64_S },
10631 { LOAD_F64_A32, LOAD_F64_A64 },
10632 { LOAD_F64_A32_S, LOAD_F64_A64_S },
10633 { LOAD_I32_A32, LOAD_I32_A64 },
10634 { LOAD_I32_A32_S, LOAD_I32_A64_S },
10635 { LOAD_I64_A32, LOAD_I64_A64 },
10636 { LOAD_I64_A32_S, LOAD_I64_A64_S },
10637 { MEMORY_ATOMIC_NOTIFY_A32, MEMORY_ATOMIC_NOTIFY_A64 },
10638 { MEMORY_ATOMIC_NOTIFY_A32_S, MEMORY_ATOMIC_NOTIFY_A64_S },
10639 { MEMORY_ATOMIC_WAIT32_A32, MEMORY_ATOMIC_WAIT32_A64 },
10640 { MEMORY_ATOMIC_WAIT32_A32_S, MEMORY_ATOMIC_WAIT32_A64_S },
10641 { MEMORY_ATOMIC_WAIT64_A32, MEMORY_ATOMIC_WAIT64_A64 },
10642 { MEMORY_ATOMIC_WAIT64_A32_S, MEMORY_ATOMIC_WAIT64_A64_S },
10643 { STORE16_I32_A32, STORE16_I32_A64 },
10644 { STORE16_I32_A32_S, STORE16_I32_A64_S },
10645 { STORE16_I64_A32, STORE16_I64_A64 },
10646 { STORE16_I64_A32_S, STORE16_I64_A64_S },
10647 { STORE32_I64_A32, STORE32_I64_A64 },
10648 { STORE32_I64_A32_S, STORE32_I64_A64_S },
10649 { STORE8_I32_A32, STORE8_I32_A64 },
10650 { STORE8_I32_A32_S, STORE8_I32_A64_S },
10651 { STORE8_I64_A32, STORE8_I64_A64 },
10652 { STORE8_I64_A32_S, STORE8_I64_A64_S },
10653 { STORE_F16_F32_A32, STORE_F16_F32_A64 },
10654 { STORE_F16_F32_A32_S, STORE_F16_F32_A64_S },
10655 { STORE_F32_A32, STORE_F32_A64 },
10656 { STORE_F32_A32_S, STORE_F32_A64_S },
10657 { STORE_F64_A32, STORE_F64_A64 },
10658 { STORE_F64_A32_S, STORE_F64_A64_S },
10659 { STORE_I32_A32, STORE_I32_A64 },
10660 { STORE_I32_A32_S, STORE_I32_A64_S },
10661 { STORE_I64_A32, STORE_I64_A64 },
10662 { STORE_I64_A32_S, STORE_I64_A64_S },
10663 }; // End of Table
10664
10665 unsigned mid;
10666 unsigned start = 0;
10667 unsigned end = 182;
10668 while (start < end) {
10669 mid = start + (end - start) / 2;
10670 if (Opcode == Table[mid][0])
10671 break;
10672 if (Opcode < Table[mid][0])
10673 end = mid;
10674 else
10675 start = mid + 1;
10676 }
10677 if (start == end)
10678 return -1; // Instruction doesn't exist in this table.
10679
10680 return Table[mid][1];
10681}
10682
10683
10684} // namespace llvm::WebAssembly
10685
10686#endif // GET_INSTRMAP_INFO
10687
10688