1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Subtarget Enumeration Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_SUBTARGETINFO_ENUM
10#undef GET_SUBTARGETINFO_ENUM
11
12namespace llvm {
13
14namespace WebAssembly {
15
16enum {
17 FeatureAtomics = 0,
18 FeatureBulkMemory = 1,
19 FeatureBulkMemoryOpt = 2,
20 FeatureCallIndirectOverlong = 3,
21 FeatureExceptionHandling = 4,
22 FeatureExtendedConst = 5,
23 FeatureFP16 = 6,
24 FeatureGC = 7,
25 FeatureMultiMemory = 8,
26 FeatureMultivalue = 9,
27 FeatureMutableGlobals = 10,
28 FeatureNontrappingFPToInt = 11,
29 FeatureReferenceTypes = 12,
30 FeatureRelaxedAtomics = 13,
31 FeatureRelaxedSIMD = 14,
32 FeatureSIMD128 = 15,
33 FeatureSignExt = 16,
34 FeatureTailCall = 17,
35 FeatureWideArithmetic = 18,
36 NumSubtargetFeatures = 19
37};
38
39} // namespace WebAssembly
40
41} // namespace llvm
42
43#endif // GET_SUBTARGETINFO_ENUM
44
45#ifdef GET_SUBTARGETINFO_MACRO
46
47GET_SUBTARGETINFO_MACRO(HasAtomics, false, hasAtomics)
48GET_SUBTARGETINFO_MACRO(HasBulkMemory, false, hasBulkMemory)
49GET_SUBTARGETINFO_MACRO(HasBulkMemoryOpt, false, hasBulkMemoryOpt)
50GET_SUBTARGETINFO_MACRO(HasCallIndirectOverlong, false, hasCallIndirectOverlong)
51GET_SUBTARGETINFO_MACRO(HasExceptionHandling, false, hasExceptionHandling)
52GET_SUBTARGETINFO_MACRO(HasExtendedConst, false, hasExtendedConst)
53GET_SUBTARGETINFO_MACRO(HasFP16, false, hasFP16)
54GET_SUBTARGETINFO_MACRO(HasGC, false, hasGC)
55GET_SUBTARGETINFO_MACRO(HasMultiMemory, false, hasMultiMemory)
56GET_SUBTARGETINFO_MACRO(HasMultivalue, false, hasMultivalue)
57GET_SUBTARGETINFO_MACRO(HasMutableGlobals, false, hasMutableGlobals)
58GET_SUBTARGETINFO_MACRO(HasNontrappingFPToInt, false, hasNontrappingFPToInt)
59GET_SUBTARGETINFO_MACRO(HasReferenceTypes, false, hasReferenceTypes)
60GET_SUBTARGETINFO_MACRO(HasRelaxedAtomics, false, hasRelaxedAtomics)
61GET_SUBTARGETINFO_MACRO(HasSignExt, false, hasSignExt)
62GET_SUBTARGETINFO_MACRO(HasTailCall, false, hasTailCall)
63GET_SUBTARGETINFO_MACRO(HasWideArithmetic, false, hasWideArithmetic)
64
65#undef GET_SUBTARGETINFO_MACRO
66#endif // GET_SUBTARGETINFO_MACRO
67
68#ifdef GET_SUBTARGETINFO_MC_DESC
69#undef GET_SUBTARGETINFO_MC_DESC
70
71namespace llvm {
72
73// Sorted (by key) array of values for CPU features.
74extern const llvm::SubtargetFeatureKV WebAssemblyFeatureKV[] = {
75 { "atomics", "Enable Atomics", WebAssembly::FeatureAtomics, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
76 { "bulk-memory", "Enable bulk memory operations", WebAssembly::FeatureBulkMemory, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
77 { "bulk-memory-opt", "Enable bulk memory optimization operations", WebAssembly::FeatureBulkMemoryOpt, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
78 { "call-indirect-overlong", "Enable overlong encoding for call_indirect immediates", WebAssembly::FeatureCallIndirectOverlong, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
79 { "exception-handling", "Enable Wasm exception handling", WebAssembly::FeatureExceptionHandling, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
80 { "extended-const", "Enable extended const expressions", WebAssembly::FeatureExtendedConst, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
81 { "fp16", "Enable FP16 instructions", WebAssembly::FeatureFP16, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
82 { "gc", "Enable wasm gc", WebAssembly::FeatureGC, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
83 { "multimemory", "Enable multiple memories", WebAssembly::FeatureMultiMemory, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
84 { "multivalue", "Enable multivalue blocks, instructions, and functions", WebAssembly::FeatureMultivalue, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
85 { "mutable-globals", "Enable mutable globals", WebAssembly::FeatureMutableGlobals, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
86 { "nontrapping-fptoint", "Enable non-trapping float-to-int conversion operators", WebAssembly::FeatureNontrappingFPToInt, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
87 { "reference-types", "Enable reference types", WebAssembly::FeatureReferenceTypes, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
88 { "relaxed-atomics", "Enable relaxed-atomics proposal", WebAssembly::FeatureRelaxedAtomics, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
89 { "relaxed-simd", "Enable relaxed-simd instructions", WebAssembly::FeatureRelaxedSIMD, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
90 { "sign-ext", "Enable sign extension operators", WebAssembly::FeatureSignExt, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
91 { "simd128", "Enable 128-bit SIMD", WebAssembly::FeatureSIMD128, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
92 { "tail-call", "Enable tail call instructions", WebAssembly::FeatureTailCall, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
93 { "wide-arithmetic", "Enable wide-arithmetic instructions", WebAssembly::FeatureWideArithmetic, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
94};
95
96#ifdef DBGFIELD
97#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
98#endif
99#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
100#define DBGFIELD(x) x,
101#define DBGVAL_OR_NULLPTR(x) x
102#else
103#define DBGFIELD(x)
104#define DBGVAL_OR_NULLPTR(x) nullptr
105#endif
106
107// ===============================================================
108// Data tables for the new per-operand machine model.
109
110// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}
111extern const llvm::MCWriteProcResEntry WebAssemblyWriteProcResTable[] = {
112 { 0, 0, 0 }, // Invalid
113}; // WebAssemblyWriteProcResTable
114
115// {Cycles, WriteResourceID}
116extern const llvm::MCWriteLatencyEntry WebAssemblyWriteLatencyTable[] = {
117 { 0, 0}, // Invalid
118}; // WebAssemblyWriteLatencyTable
119
120// {UseIdx, WriteResourceID, Cycles}
121extern const llvm::MCReadAdvanceEntry WebAssemblyReadAdvanceTable[] = {
122 {0, 0, 0}, // Invalid
123}; // WebAssemblyReadAdvanceTable
124
125#ifdef __GNUC__
126#pragma GCC diagnostic push
127#pragma GCC diagnostic ignored "-Woverlength-strings"
128#endif
129static constexpr char WebAssemblySchedClassNamesStorage[] =
130 "\0"
131 "InvalidSchedClass\0"
132 ;
133#ifdef __GNUC__
134#pragma GCC diagnostic pop
135#endif
136
137static constexpr llvm::StringTable
138WebAssemblySchedClassNames = WebAssemblySchedClassNamesStorage;
139
140static const llvm::MCSchedModel NoSchedModel = {
141 MCSchedModel::DefaultIssueWidth,
142 MCSchedModel::DefaultMicroOpBufferSize,
143 MCSchedModel::DefaultLoopMicroOpBufferSize,
144 MCSchedModel::DefaultLoadLatency,
145 MCSchedModel::DefaultHighLatency,
146 MCSchedModel::DefaultMispredictPenalty,
147 false, // PostRAScheduler
148 false, // CompleteModel
149 false, // EnableIntervals
150 0, // Processor ID
151 nullptr, nullptr, 0, 0, // No instruction-level machine model.
152 DBGVAL_OR_NULLPTR(&WebAssemblySchedClassNames), // SchedClassNames
153 nullptr, // No Itinerary
154 nullptr // No extra processor descriptor
155};
156
157#undef DBGFIELD
158
159#undef DBGVAL_OR_NULLPTR
160
161// Sorted (by key) array of values for CPU subtype.
162extern const llvm::SubtargetSubTypeKV WebAssemblySubTypeKV[] = {
163 { "bleeding-edge", { { { 0x3dfffULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
164 { "generic", { { { 0x11e0eULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
165 { "lime1", { { { 0x10e2cULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
166 { "mvp", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
167};
168
169// Sorted array of names of CPU subtypes, including aliases.
170extern const llvm::StringRef WebAssemblyNames[] = {
171"bleeding-edge",
172"generic",
173"lime1",
174"mvp"};
175
176namespace WebAssembly_MC {
177
178unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
179 const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID) {
180 // Don't know how to resolve this scheduling class.
181 return 0;
182}
183
184} // namespace WebAssembly_MC
185struct WebAssemblyGenMCSubtargetInfo : public MCSubtargetInfo {
186 WebAssemblyGenMCSubtargetInfo(const Triple &TT,
187 StringRef CPU, StringRef TuneCPU, StringRef FS,
188 ArrayRef<StringRef> PN,
189 ArrayRef<SubtargetFeatureKV> PF,
190 ArrayRef<SubtargetSubTypeKV> PD,
191 const MCWriteProcResEntry *WPR,
192 const MCWriteLatencyEntry *WL,
193 const MCReadAdvanceEntry *RA, const InstrStage *IS,
194 const unsigned *OC, const unsigned *FP) :
195 MCSubtargetInfo(TT, CPU, TuneCPU, FS, PN, PF, PD,
196 WPR, WL, RA, IS, OC, FP) { }
197
198 unsigned resolveVariantSchedClass(unsigned SchedClass,
199 const MCInst *MI, const MCInstrInfo *MCII,
200 unsigned CPUID) const final {
201 return WebAssembly_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
202 }
203 unsigned getHwModeSet() const final;
204 unsigned getHwMode(enum HwModeType type = HwMode_Default) const final;
205};
206unsigned WebAssemblyGenMCSubtargetInfo::getHwModeSet() const {
207 [[maybe_unused]] const FeatureBitset &FB = getFeatureBits();
208 // Collect HwModes and store them as a bit set.
209 unsigned Modes = 0;
210 if (false) Modes |= (1 << 0);
211 return Modes;
212}
213unsigned WebAssemblyGenMCSubtargetInfo::getHwMode(enum HwModeType type) const {
214 unsigned Modes = getHwModeSet();
215
216 if (!Modes)
217 return Modes;
218
219 switch (type) {
220 case HwMode_Default:
221 return llvm::countr_zero(Modes) + 1;
222 case HwMode_ValueType:
223 // No HwMode for ValueType.
224 return 0;
225 case HwMode_RegInfo:
226 Modes &= 1;
227 if (!Modes)
228 return Modes;
229 if (!llvm::has_single_bit<unsigned>(Modes))
230 llvm_unreachable("Two or more HwModes for RegInfo were found!");
231 return llvm::countr_zero(Modes) + 1;
232 case HwMode_EncodingInfo:
233 // No HwMode for EncodingInfo.
234 return 0;
235 }
236 llvm_unreachable("unexpected HwModeType");
237 return 0; // should not get here
238}
239
240static inline MCSubtargetInfo *createWebAssemblyMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
241 return new WebAssemblyGenMCSubtargetInfo(TT, CPU, TuneCPU, FS, WebAssemblyNames, WebAssemblyFeatureKV, WebAssemblySubTypeKV,
242 WebAssemblyWriteProcResTable, WebAssemblyWriteLatencyTable, WebAssemblyReadAdvanceTable,
243 nullptr, nullptr, nullptr);
244}
245
246
247} // namespace llvm
248
249#endif // GET_SUBTARGETINFO_MC_DESC
250
251#ifdef GET_SUBTARGETINFO_TARGET_DESC
252#undef GET_SUBTARGETINFO_TARGET_DESC
253
254#include "llvm/ADT/BitmaskEnum.h"
255#include "llvm/Support/Debug.h"
256#include "llvm/Support/raw_ostream.h"
257
258// ParseSubtargetFeatures - Parses features string setting specified
259// subtarget options.
260void llvm::WebAssemblySubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
261 LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
262 LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
263 LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
264 InitMCProcessorInfo(CPU, TuneCPU, FS);
265 const FeatureBitset &Bits = getFeatureBits();
266 if (Bits[WebAssembly::FeatureAtomics]) HasAtomics = true;
267 if (Bits[WebAssembly::FeatureBulkMemory]) HasBulkMemory = true;
268 if (Bits[WebAssembly::FeatureBulkMemoryOpt]) HasBulkMemoryOpt = true;
269 if (Bits[WebAssembly::FeatureCallIndirectOverlong]) HasCallIndirectOverlong = true;
270 if (Bits[WebAssembly::FeatureExceptionHandling]) HasExceptionHandling = true;
271 if (Bits[WebAssembly::FeatureExtendedConst]) HasExtendedConst = true;
272 if (Bits[WebAssembly::FeatureFP16]) HasFP16 = true;
273 if (Bits[WebAssembly::FeatureGC]) HasGC = true;
274 if (Bits[WebAssembly::FeatureMultiMemory]) HasMultiMemory = true;
275 if (Bits[WebAssembly::FeatureMultivalue]) HasMultivalue = true;
276 if (Bits[WebAssembly::FeatureMutableGlobals]) HasMutableGlobals = true;
277 if (Bits[WebAssembly::FeatureNontrappingFPToInt]) HasNontrappingFPToInt = true;
278 if (Bits[WebAssembly::FeatureReferenceTypes]) HasReferenceTypes = true;
279 if (Bits[WebAssembly::FeatureRelaxedAtomics]) HasRelaxedAtomics = true;
280 if (Bits[WebAssembly::FeatureRelaxedSIMD] && SIMDLevel < RelaxedSIMD) SIMDLevel = RelaxedSIMD;
281 if (Bits[WebAssembly::FeatureSIMD128] && SIMDLevel < SIMD128) SIMDLevel = SIMD128;
282 if (Bits[WebAssembly::FeatureSignExt]) HasSignExt = true;
283 if (Bits[WebAssembly::FeatureTailCall]) HasTailCall = true;
284 if (Bits[WebAssembly::FeatureWideArithmetic]) HasWideArithmetic = true;
285}
286
287#endif // GET_SUBTARGETINFO_TARGET_DESC
288
289#ifdef GET_SUBTARGETINFO_HEADER
290#undef GET_SUBTARGETINFO_HEADER
291
292namespace llvm {
293
294class DFAPacketizer;
295namespace WebAssembly_MC {
296
297unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID);
298
299} // namespace WebAssembly_MC
300struct WebAssemblyGenSubtargetInfo : public TargetSubtargetInfo {
301 explicit WebAssemblyGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
302public:
303 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const final;
304 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const final;
305 DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
306 enum class WebAssemblyHwModeBits : unsigned {
307 DefaultMode = 0,
308 WASM64 = (1 << 0),
309
310 LLVM_MARK_AS_BITMASK_ENUM(/*LargestValue=*/WASM64),
311 };
312 unsigned getHwModeSet() const final;
313 unsigned getHwMode(enum HwModeType type = HwMode_Default) const final;
314};
315
316} // namespace llvm
317
318#endif // GET_SUBTARGETINFO_HEADER
319
320#ifdef GET_SUBTARGETINFO_CTOR
321#undef GET_SUBTARGETINFO_CTOR
322
323#include "llvm/CodeGen/TargetSchedule.h"
324
325namespace llvm {
326
327extern const llvm::StringRef WebAssemblyNames[];
328extern const llvm::SubtargetFeatureKV WebAssemblyFeatureKV[];
329extern const llvm::SubtargetSubTypeKV WebAssemblySubTypeKV[];
330extern const llvm::MCWriteProcResEntry WebAssemblyWriteProcResTable[];
331extern const llvm::MCWriteLatencyEntry WebAssemblyWriteLatencyTable[];
332extern const llvm::MCReadAdvanceEntry WebAssemblyReadAdvanceTable[];
333WebAssemblyGenSubtargetInfo::WebAssemblyGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
334 : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, ArrayRef(WebAssemblyNames, 4), ArrayRef(WebAssemblyFeatureKV, 19), ArrayRef(WebAssemblySubTypeKV, 4),
335 WebAssemblyWriteProcResTable, WebAssemblyWriteLatencyTable, WebAssemblyReadAdvanceTable,
336 nullptr, nullptr, nullptr) {}
337
338unsigned WebAssemblyGenSubtargetInfo
339::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
340 report_fatal_error("Expected a variant SchedClass");
341} // WebAssemblyGenSubtargetInfo::resolveSchedClass
342
343unsigned WebAssemblyGenSubtargetInfo
344::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {
345 return WebAssembly_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
346} // WebAssemblyGenSubtargetInfo::resolveVariantSchedClass
347
348unsigned WebAssemblyGenSubtargetInfo::getHwModeSet() const {
349 [[maybe_unused]] const auto *Subtarget =
350 static_cast<const WebAssemblySubtarget *>(this);
351 // Collect HwModes and store them as a bit set.
352 unsigned Modes = 0;
353 if ((Subtarget->hasAddr64())) Modes |= (1 << 0);
354 return Modes;
355}
356unsigned WebAssemblyGenSubtargetInfo::getHwMode(enum HwModeType type) const {
357 unsigned Modes = getHwModeSet();
358
359 if (!Modes)
360 return Modes;
361
362 switch (type) {
363 case HwMode_Default:
364 return llvm::countr_zero(Modes) + 1;
365 case HwMode_ValueType:
366 // No HwMode for ValueType.
367 return 0;
368 case HwMode_RegInfo:
369 Modes &= 1;
370 if (!Modes)
371 return Modes;
372 if (!llvm::has_single_bit<unsigned>(Modes))
373 llvm_unreachable("Two or more HwModes for RegInfo were found!");
374 return llvm::countr_zero(Modes) + 1;
375 case HwMode_EncodingInfo:
376 // No HwMode for EncodingInfo.
377 return 0;
378 }
379 llvm_unreachable("unexpected HwModeType");
380 return 0; // should not get here
381}
382
383} // namespace llvm
384
385#endif // GET_SUBTARGETINFO_CTOR
386
387#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
388#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
389
390
391#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
392
393#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
394#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
395
396
397#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
398
399