1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Subtarget Enumeration Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_SUBTARGETINFO_ENUM
10#undef GET_SUBTARGETINFO_ENUM
11
12namespace llvm {
13
14namespace WebAssembly {
15
16enum {
17 FeatureAtomics = 0,
18 FeatureBulkMemory = 1,
19 FeatureBulkMemoryOpt = 2,
20 FeatureCallIndirectOverlong = 3,
21 FeatureExceptionHandling = 4,
22 FeatureExtendedConst = 5,
23 FeatureFP16 = 6,
24 FeatureGC = 7,
25 FeatureMultiMemory = 8,
26 FeatureMultivalue = 9,
27 FeatureMutableGlobals = 10,
28 FeatureNontrappingFPToInt = 11,
29 FeatureReferenceTypes = 12,
30 FeatureRelaxedAtomics = 13,
31 FeatureRelaxedSIMD = 14,
32 FeatureSIMD128 = 15,
33 FeatureSignExt = 16,
34 FeatureTailCall = 17,
35 FeatureWideArithmetic = 18,
36 NumSubtargetFeatures = 19
37};
38
39} // namespace WebAssembly
40
41} // namespace llvm
42
43#endif // GET_SUBTARGETINFO_ENUM
44
45#ifdef GET_SUBTARGETINFO_MACRO
46
47GET_SUBTARGETINFO_MACRO(HasAtomics, false, hasAtomics)
48GET_SUBTARGETINFO_MACRO(HasBulkMemory, false, hasBulkMemory)
49GET_SUBTARGETINFO_MACRO(HasBulkMemoryOpt, false, hasBulkMemoryOpt)
50GET_SUBTARGETINFO_MACRO(HasCallIndirectOverlong, false, hasCallIndirectOverlong)
51GET_SUBTARGETINFO_MACRO(HasExceptionHandling, false, hasExceptionHandling)
52GET_SUBTARGETINFO_MACRO(HasExtendedConst, false, hasExtendedConst)
53GET_SUBTARGETINFO_MACRO(HasFP16, false, hasFP16)
54GET_SUBTARGETINFO_MACRO(HasGC, false, hasGC)
55GET_SUBTARGETINFO_MACRO(HasMultiMemory, false, hasMultiMemory)
56GET_SUBTARGETINFO_MACRO(HasMultivalue, false, hasMultivalue)
57GET_SUBTARGETINFO_MACRO(HasMutableGlobals, false, hasMutableGlobals)
58GET_SUBTARGETINFO_MACRO(HasNontrappingFPToInt, false, hasNontrappingFPToInt)
59GET_SUBTARGETINFO_MACRO(HasReferenceTypes, false, hasReferenceTypes)
60GET_SUBTARGETINFO_MACRO(HasRelaxedAtomics, false, hasRelaxedAtomics)
61GET_SUBTARGETINFO_MACRO(HasSignExt, false, hasSignExt)
62GET_SUBTARGETINFO_MACRO(HasTailCall, false, hasTailCall)
63GET_SUBTARGETINFO_MACRO(HasWideArithmetic, false, hasWideArithmetic)
64
65#undef GET_SUBTARGETINFO_MACRO
66#endif // GET_SUBTARGETINFO_MACRO
67
68#ifdef GET_SUBTARGETINFO_MC_DESC
69#undef GET_SUBTARGETINFO_MC_DESC
70
71namespace llvm {
72
73// Sorted (by key) array of values for CPU features.
74extern const llvm::SubtargetFeatureKVStorage< 19, 859> WebAssemblyFeatureKVStorage = {
75 {
76 { sizeof(SubtargetFeatureKV) * 19 + 1, sizeof(SubtargetFeatureKV) * 19 + 9, WebAssembly::FeatureAtomics, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
77 { sizeof(SubtargetFeatureKV) * 18 + 24, sizeof(SubtargetFeatureKV) * 18 + 36, WebAssembly::FeatureBulkMemory, { { { 0x4ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
78 { sizeof(SubtargetFeatureKV) * 17 + 66, sizeof(SubtargetFeatureKV) * 17 + 82, WebAssembly::FeatureBulkMemoryOpt, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
79 { sizeof(SubtargetFeatureKV) * 16 + 125, sizeof(SubtargetFeatureKV) * 16 + 148, WebAssembly::FeatureCallIndirectOverlong, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
80 { sizeof(SubtargetFeatureKV) * 15 + 202, sizeof(SubtargetFeatureKV) * 15 + 221, WebAssembly::FeatureExceptionHandling, { { { 0x1200ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
81 { sizeof(SubtargetFeatureKV) * 14 + 252, sizeof(SubtargetFeatureKV) * 14 + 267, WebAssembly::FeatureExtendedConst, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
82 { sizeof(SubtargetFeatureKV) * 13 + 301, sizeof(SubtargetFeatureKV) * 13 + 306, WebAssembly::FeatureFP16, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
83 { sizeof(SubtargetFeatureKV) * 12 + 331, sizeof(SubtargetFeatureKV) * 12 + 334, WebAssembly::FeatureGC, { { { 0x1000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
84 { sizeof(SubtargetFeatureKV) * 11 + 349, sizeof(SubtargetFeatureKV) * 11 + 361, WebAssembly::FeatureMultiMemory, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
85 { sizeof(SubtargetFeatureKV) * 10 + 386, sizeof(SubtargetFeatureKV) * 10 + 397, WebAssembly::FeatureMultivalue, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
86 { sizeof(SubtargetFeatureKV) * 9 + 451, sizeof(SubtargetFeatureKV) * 9 + 467, WebAssembly::FeatureMutableGlobals, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
87 { sizeof(SubtargetFeatureKV) * 8 + 490, sizeof(SubtargetFeatureKV) * 8 + 510, WebAssembly::FeatureNontrappingFPToInt, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
88 { sizeof(SubtargetFeatureKV) * 7 + 564, sizeof(SubtargetFeatureKV) * 7 + 580, WebAssembly::FeatureReferenceTypes, { { { 0x8ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
89 { sizeof(SubtargetFeatureKV) * 6 + 603, sizeof(SubtargetFeatureKV) * 6 + 619, WebAssembly::FeatureRelaxedAtomics, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
90 { sizeof(SubtargetFeatureKV) * 5 + 651, sizeof(SubtargetFeatureKV) * 5 + 664, WebAssembly::FeatureRelaxedSIMD, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
91 { sizeof(SubtargetFeatureKV) * 4 + 697, sizeof(SubtargetFeatureKV) * 4 + 706, WebAssembly::FeatureSignExt, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
92 { sizeof(SubtargetFeatureKV) * 3 + 738, sizeof(SubtargetFeatureKV) * 3 + 746, WebAssembly::FeatureSIMD128, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
93 { sizeof(SubtargetFeatureKV) * 2 + 766, sizeof(SubtargetFeatureKV) * 2 + 776, WebAssembly::FeatureTailCall, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
94 { sizeof(SubtargetFeatureKV) * 1 + 806, sizeof(SubtargetFeatureKV) * 1 + 822, WebAssembly::FeatureWideArithmetic, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
95 },
96 "\000atomics\000Enable Atomics\000bulk-memory\000Enable bulk memory oper"
97 "ations\000bulk-memory-opt\000Enable bulk memory optimization operations"
98 "\000call-indirect-overlong\000Enable overlong encoding for call_indirec"
99 "t immediates\000exception-handling\000Enable Wasm exception handling\000"
100 "extended-const\000Enable extended const expressions\000fp16\000Enable F"
101 "P16 instructions\000gc\000Enable wasm gc\000multimemory\000Enable multi"
102 "ple memories\000multivalue\000Enable multivalue blocks, instructions, a"
103 "nd functions\000mutable-globals\000Enable mutable globals\000nontrappin"
104 "g-fptoint\000Enable non-trapping float-to-int conversion operators\000r"
105 "eference-types\000Enable reference types\000relaxed-atomics\000Enable r"
106 "elaxed-atomics proposal\000relaxed-simd\000Enable relaxed-simd instruct"
107 "ions\000sign-ext\000Enable sign extension operators\000simd128\000Enabl"
108 "e 128-bit SIMD\000tail-call\000Enable tail call instructions\000wide-ar"
109 "ithmetic\000Enable wide-arithmetic instructions\000"};
110
111#ifdef DBGFIELD
112#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
113#endif
114#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
115#define DBGFIELD(x) x,
116#define DBGVAL_OR_NULLPTR(x) x
117#else
118#define DBGFIELD(x)
119#define DBGVAL_OR_NULLPTR(x) nullptr
120#endif
121
122// ===============================================================
123// Data tables for the new per-operand machine model.
124
125static_assert(0 <= UINT8_MAX, "NumWriteProcResEntries does not fit in uint8_t");
126static_assert(0 <= UINT8_MAX, "NumWriteLatencyEntries does not fit in uint8_t");
127
128// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}
129extern const llvm::MCWriteProcResEntry WebAssemblyWriteProcResTable[] = {
130 { 0, 0, 0 }, // Invalid
131}; // WebAssemblyWriteProcResTable
132
133// {Cycles, WriteResourceID}
134extern const llvm::MCWriteLatencyEntry WebAssemblyWriteLatencyTable[] = {
135 { 0, 0}, // Invalid
136}; // WebAssemblyWriteLatencyTable
137
138// {UseIdx, WriteResourceID, Cycles}
139extern const llvm::MCReadAdvanceEntry WebAssemblyReadAdvanceTable[] = {
140 {0, 0, 0}, // Invalid
141}; // WebAssemblyReadAdvanceTable
142
143#ifdef __GNUC__
144#pragma GCC diagnostic push
145#pragma GCC diagnostic ignored "-Woverlength-strings"
146#endif
147static constexpr char WebAssemblySchedClassNamesStorage[] =
148 "\0"
149 "InvalidSchedClass\0"
150 ;
151#ifdef __GNUC__
152#pragma GCC diagnostic pop
153#endif
154
155static constexpr llvm::StringTable
156WebAssemblySchedClassNames = WebAssemblySchedClassNamesStorage;
157
158extern const llvm::MCSchedModel WebAssemblySchedModels[] = {
159{ // NoSchedModel
160 MCSchedModel::DefaultIssueWidth,
161 MCSchedModel::DefaultMicroOpBufferSize,
162 MCSchedModel::DefaultLoopMicroOpBufferSize,
163 MCSchedModel::DefaultLoadLatency,
164 MCSchedModel::DefaultHighLatency,
165 MCSchedModel::DefaultMispredictPenalty,
166 false, // PostRAScheduler
167 false, // CompleteModel
168 false, // EnableIntervals
169 0, // Processor ID
170 nullptr, nullptr, 0, 0, // No instruction-level machine model.
171 DBGVAL_OR_NULLPTR(&WebAssemblySchedClassNames), // SchedClassNames
172 nullptr, // No Itinerary
173 nullptr // No extra processor descriptor
174 },
175};
176
177#undef DBGFIELD
178
179#undef DBGVAL_OR_NULLPTR
180
181// Sorted (by key) array of values for CPU subtype.
182extern const llvm::SubtargetSubTypeKVStorage< 4, 34> WebAssemblySubTypeKVStorage = {
183 {
184 { sizeof(SubtargetSubTypeKV) * 4 + 1, { { { 0x3dfffULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
185 { sizeof(SubtargetSubTypeKV) * 3 + 15, { { { 0x11e0eULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
186 { sizeof(SubtargetSubTypeKV) * 2 + 23, { { { 0x10e2cULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
187 { sizeof(SubtargetSubTypeKV) * 1 + 29, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
188 },
189 "\000bleeding-edge\000generic\000lime1\000mvp\000"};
190
191namespace WebAssembly_MC {
192
193unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
194 const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID) {
195 // Don't know how to resolve this scheduling class.
196 return 0;
197}
198
199} // namespace WebAssembly_MC
200struct WebAssemblyGenMCSubtargetInfo : public MCSubtargetInfo {
201 WebAssemblyGenMCSubtargetInfo(const Triple &TT,
202 StringRef CPU, StringRef TuneCPU, StringRef FS,
203 StringTable PN,
204 ArrayRef<SubtargetFeatureKV> PF,
205 ArrayRef<SubtargetSubTypeKV> PD,
206 const MCSchedModel *PSM,
207 const MCWriteProcResEntry *WPR,
208 const MCWriteLatencyEntry *WL,
209 const MCReadAdvanceEntry *RA, const InstrStage *IS,
210 const unsigned *OC, const unsigned *FP) :
211 MCSubtargetInfo(TT, CPU, TuneCPU, FS, PN, PF, PD, PSM,
212 WPR, WL, RA, IS, OC, FP) { }
213
214 unsigned resolveVariantSchedClass(unsigned SchedClass,
215 const MCInst *MI, const MCInstrInfo *MCII,
216 unsigned CPUID) const final {
217 return WebAssembly_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
218 }
219 unsigned getHwModeSet() const final;
220 unsigned getHwMode(enum HwModeType type = HwMode_Default) const final;
221};
222unsigned WebAssemblyGenMCSubtargetInfo::getHwModeSet() const {
223 [[maybe_unused]] const FeatureBitset &FB = getFeatureBits();
224 // Collect HwModes and store them as a bit set.
225 unsigned Modes = 0;
226 if (false) Modes |= (1 << 0);
227 return Modes;
228}
229unsigned WebAssemblyGenMCSubtargetInfo::getHwMode(enum HwModeType type) const {
230 unsigned Modes = getHwModeSet();
231
232 if (!Modes)
233 return Modes;
234
235 switch (type) {
236 case HwMode_Default:
237 return llvm::countr_zero(Modes) + 1;
238 case HwMode_ValueType:
239 // No HwMode for ValueType.
240 return 0;
241 case HwMode_RegInfo:
242 Modes &= 1;
243 if (!Modes)
244 return Modes;
245 if (!llvm::has_single_bit<unsigned>(Modes))
246 llvm_unreachable("Two or more HwModes for RegInfo were found!");
247 return llvm::countr_zero(Modes) + 1;
248 case HwMode_EncodingInfo:
249 // No HwMode for EncodingInfo.
250 return 0;
251 }
252 llvm_unreachable("unexpected HwModeType");
253 return 0; // should not get here
254}
255
256static inline MCSubtargetInfo *createWebAssemblyMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
257 return new WebAssemblyGenMCSubtargetInfo(TT, CPU, TuneCPU, FS, StringTable(WebAssemblySubTypeKVStorage.Strings), WebAssemblyFeatureKVStorage.Features, WebAssemblySubTypeKVStorage.SubTypes, WebAssemblySchedModels,
258 WebAssemblyWriteProcResTable, WebAssemblyWriteLatencyTable, WebAssemblyReadAdvanceTable,
259 nullptr, nullptr, nullptr);
260}
261
262
263} // namespace llvm
264
265#endif // GET_SUBTARGETINFO_MC_DESC
266
267#ifdef GET_SUBTARGETINFO_TARGET_DESC
268#undef GET_SUBTARGETINFO_TARGET_DESC
269
270#include "llvm/ADT/BitmaskEnum.h"
271#include "llvm/Support/Debug.h"
272#include "llvm/Support/raw_ostream.h"
273
274// ParseSubtargetFeatures - Parses features string setting specified
275// subtarget options.
276void llvm::WebAssemblySubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
277 LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
278 LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
279 LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
280 InitMCProcessorInfo(CPU, TuneCPU, FS);
281 const FeatureBitset &Bits = getFeatureBits();
282 if (Bits[WebAssembly::FeatureAtomics]) HasAtomics = true;
283 if (Bits[WebAssembly::FeatureBulkMemory]) HasBulkMemory = true;
284 if (Bits[WebAssembly::FeatureBulkMemoryOpt]) HasBulkMemoryOpt = true;
285 if (Bits[WebAssembly::FeatureCallIndirectOverlong]) HasCallIndirectOverlong = true;
286 if (Bits[WebAssembly::FeatureExceptionHandling]) HasExceptionHandling = true;
287 if (Bits[WebAssembly::FeatureExtendedConst]) HasExtendedConst = true;
288 if (Bits[WebAssembly::FeatureFP16]) HasFP16 = true;
289 if (Bits[WebAssembly::FeatureGC]) HasGC = true;
290 if (Bits[WebAssembly::FeatureMultiMemory]) HasMultiMemory = true;
291 if (Bits[WebAssembly::FeatureMultivalue]) HasMultivalue = true;
292 if (Bits[WebAssembly::FeatureMutableGlobals]) HasMutableGlobals = true;
293 if (Bits[WebAssembly::FeatureNontrappingFPToInt]) HasNontrappingFPToInt = true;
294 if (Bits[WebAssembly::FeatureReferenceTypes]) HasReferenceTypes = true;
295 if (Bits[WebAssembly::FeatureRelaxedAtomics]) HasRelaxedAtomics = true;
296 if (Bits[WebAssembly::FeatureRelaxedSIMD] && SIMDLevel < RelaxedSIMD) SIMDLevel = RelaxedSIMD;
297 if (Bits[WebAssembly::FeatureSIMD128] && SIMDLevel < SIMD128) SIMDLevel = SIMD128;
298 if (Bits[WebAssembly::FeatureSignExt]) HasSignExt = true;
299 if (Bits[WebAssembly::FeatureTailCall]) HasTailCall = true;
300 if (Bits[WebAssembly::FeatureWideArithmetic]) HasWideArithmetic = true;
301}
302
303#endif // GET_SUBTARGETINFO_TARGET_DESC
304
305#ifdef GET_SUBTARGETINFO_HEADER
306#undef GET_SUBTARGETINFO_HEADER
307
308namespace llvm {
309
310class DFAPacketizer;
311namespace WebAssembly_MC {
312
313unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID);
314
315} // namespace WebAssembly_MC
316struct WebAssemblyGenSubtargetInfo : public TargetSubtargetInfo {
317 explicit WebAssemblyGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
318public:
319 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const final;
320 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const final;
321 DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
322 enum class WebAssemblyHwModeBits : unsigned {
323 DefaultMode = 0,
324 WASM64 = (1 << 0),
325
326 LLVM_MARK_AS_BITMASK_ENUM(/*LargestValue=*/WASM64),
327 };
328 unsigned getHwModeSet() const final;
329 unsigned getHwMode(enum HwModeType type = HwMode_Default) const final;
330 const FeatureBitset &getInlineIgnoreFeatures() const override;
331 const FeatureBitset &getInlineInverseFeatures() const override;
332 const FeatureBitset &getInlineMustMatchFeatures() const override;
333};
334
335} // namespace llvm
336
337#endif // GET_SUBTARGETINFO_HEADER
338
339#ifdef GET_SUBTARGETINFO_CTOR
340#undef GET_SUBTARGETINFO_CTOR
341
342#include "llvm/CodeGen/TargetSchedule.h"
343
344namespace llvm {
345
346extern const llvm::StringRef WebAssemblyNames[];
347extern const llvm::SubtargetFeatureKVStorage<19, 859> WebAssemblyFeatureKVStorage;
348extern const llvm::SubtargetSubTypeKVStorage<4, 34> WebAssemblySubTypeKVStorage;
349extern const llvm::MCSchedModel WebAssemblySchedModels[];
350extern const llvm::MCWriteProcResEntry WebAssemblyWriteProcResTable[];
351extern const llvm::MCWriteLatencyEntry WebAssemblyWriteLatencyTable[];
352extern const llvm::MCReadAdvanceEntry WebAssemblyReadAdvanceTable[];
353WebAssemblyGenSubtargetInfo::WebAssemblyGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
354 : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, StringTable(WebAssemblySubTypeKVStorage.Strings), ArrayRef(WebAssemblyFeatureKVStorage.Features), ArrayRef(WebAssemblySubTypeKVStorage.SubTypes), WebAssemblySchedModels,
355 WebAssemblyWriteProcResTable, WebAssemblyWriteLatencyTable, WebAssemblyReadAdvanceTable,
356 nullptr, nullptr, nullptr) {}
357
358unsigned WebAssemblyGenSubtargetInfo
359::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
360 report_fatal_error("Expected a variant SchedClass");
361} // WebAssemblyGenSubtargetInfo::resolveSchedClass
362
363unsigned WebAssemblyGenSubtargetInfo
364::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {
365 return WebAssembly_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
366} // WebAssemblyGenSubtargetInfo::resolveVariantSchedClass
367
368unsigned WebAssemblyGenSubtargetInfo::getHwModeSet() const {
369 [[maybe_unused]] const auto *Subtarget =
370 static_cast<const WebAssemblySubtarget *>(this);
371 // Collect HwModes and store them as a bit set.
372 unsigned Modes = 0;
373 if ((Subtarget->hasAddr64())) Modes |= (1 << 0);
374 return Modes;
375}
376unsigned WebAssemblyGenSubtargetInfo::getHwMode(enum HwModeType type) const {
377 unsigned Modes = getHwModeSet();
378
379 if (!Modes)
380 return Modes;
381
382 switch (type) {
383 case HwMode_Default:
384 return llvm::countr_zero(Modes) + 1;
385 case HwMode_ValueType:
386 // No HwMode for ValueType.
387 return 0;
388 case HwMode_RegInfo:
389 Modes &= 1;
390 if (!Modes)
391 return Modes;
392 if (!llvm::has_single_bit<unsigned>(Modes))
393 llvm_unreachable("Two or more HwModes for RegInfo were found!");
394 return llvm::countr_zero(Modes) + 1;
395 case HwMode_EncodingInfo:
396 // No HwMode for EncodingInfo.
397 return 0;
398 }
399 llvm_unreachable("unexpected HwModeType");
400 return 0; // should not get here
401}
402const FeatureBitset &WebAssemblyGenSubtargetInfo::getInlineIgnoreFeatures() const {
403 static constexpr FeatureBitset Features = {
404 };
405 return Features;
406}
407
408const FeatureBitset &WebAssemblyGenSubtargetInfo::getInlineInverseFeatures() const {
409 static constexpr FeatureBitset Features = {
410 };
411 return Features;
412}
413
414const FeatureBitset &WebAssemblyGenSubtargetInfo::getInlineMustMatchFeatures() const {
415 static constexpr FeatureBitset Features = {
416 };
417 return Features;
418}
419
420
421} // namespace llvm
422
423#endif // GET_SUBTARGETINFO_CTOR
424
425#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
426#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
427
428
429#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
430
431#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
432#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
433
434
435#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
436
437