1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Subtarget Enumeration Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_SUBTARGETINFO_ENUM
10#undef GET_SUBTARGETINFO_ENUM
11
12namespace llvm {
13
14namespace WebAssembly {
15
16enum {
17 FeatureAtomics = 0,
18 FeatureBulkMemory = 1,
19 FeatureBulkMemoryOpt = 2,
20 FeatureCallIndirectOverlong = 3,
21 FeatureExceptionHandling = 4,
22 FeatureExtendedConst = 5,
23 FeatureFP16 = 6,
24 FeatureGC = 7,
25 FeatureMultiMemory = 8,
26 FeatureMultivalue = 9,
27 FeatureMutableGlobals = 10,
28 FeatureNontrappingFPToInt = 11,
29 FeatureReferenceTypes = 12,
30 FeatureRelaxedAtomics = 13,
31 FeatureRelaxedSIMD = 14,
32 FeatureSIMD128 = 15,
33 FeatureSignExt = 16,
34 FeatureTailCall = 17,
35 FeatureWideArithmetic = 18,
36 NumSubtargetFeatures = 19
37};
38
39} // namespace WebAssembly
40
41} // namespace llvm
42
43#endif // GET_SUBTARGETINFO_ENUM
44
45#ifdef GET_SUBTARGETINFO_MACRO
46
47GET_SUBTARGETINFO_MACRO(HasAtomics, false, hasAtomics)
48GET_SUBTARGETINFO_MACRO(HasBulkMemory, false, hasBulkMemory)
49GET_SUBTARGETINFO_MACRO(HasBulkMemoryOpt, false, hasBulkMemoryOpt)
50GET_SUBTARGETINFO_MACRO(HasCallIndirectOverlong, false, hasCallIndirectOverlong)
51GET_SUBTARGETINFO_MACRO(HasExceptionHandling, false, hasExceptionHandling)
52GET_SUBTARGETINFO_MACRO(HasExtendedConst, false, hasExtendedConst)
53GET_SUBTARGETINFO_MACRO(HasFP16, false, hasFP16)
54GET_SUBTARGETINFO_MACRO(HasGC, false, hasGC)
55GET_SUBTARGETINFO_MACRO(HasMultiMemory, false, hasMultiMemory)
56GET_SUBTARGETINFO_MACRO(HasMultivalue, false, hasMultivalue)
57GET_SUBTARGETINFO_MACRO(HasMutableGlobals, false, hasMutableGlobals)
58GET_SUBTARGETINFO_MACRO(HasNontrappingFPToInt, false, hasNontrappingFPToInt)
59GET_SUBTARGETINFO_MACRO(HasReferenceTypes, false, hasReferenceTypes)
60GET_SUBTARGETINFO_MACRO(HasRelaxedAtomics, false, hasRelaxedAtomics)
61GET_SUBTARGETINFO_MACRO(HasSignExt, false, hasSignExt)
62GET_SUBTARGETINFO_MACRO(HasTailCall, false, hasTailCall)
63GET_SUBTARGETINFO_MACRO(HasWideArithmetic, false, hasWideArithmetic)
64
65#undef GET_SUBTARGETINFO_MACRO
66#endif // GET_SUBTARGETINFO_MACRO
67
68#ifdef GET_SUBTARGETINFO_MC_DESC
69#undef GET_SUBTARGETINFO_MC_DESC
70
71namespace llvm {
72
73// Sorted (by key) array of values for CPU features.
74extern const llvm::SubtargetFeatureKVStorage< 19, 859> WebAssemblyFeatureKVStorage = {
75 {
76 { sizeof(SubtargetFeatureKV) * 19 + 1, sizeof(SubtargetFeatureKV) * 19 + 9, WebAssembly::FeatureAtomics, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
77 { sizeof(SubtargetFeatureKV) * 18 + 24, sizeof(SubtargetFeatureKV) * 18 + 36, WebAssembly::FeatureBulkMemory, { { { 0x4ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
78 { sizeof(SubtargetFeatureKV) * 17 + 66, sizeof(SubtargetFeatureKV) * 17 + 82, WebAssembly::FeatureBulkMemoryOpt, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
79 { sizeof(SubtargetFeatureKV) * 16 + 125, sizeof(SubtargetFeatureKV) * 16 + 148, WebAssembly::FeatureCallIndirectOverlong, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
80 { sizeof(SubtargetFeatureKV) * 15 + 202, sizeof(SubtargetFeatureKV) * 15 + 221, WebAssembly::FeatureExceptionHandling, { { { 0x1200ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
81 { sizeof(SubtargetFeatureKV) * 14 + 252, sizeof(SubtargetFeatureKV) * 14 + 267, WebAssembly::FeatureExtendedConst, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
82 { sizeof(SubtargetFeatureKV) * 13 + 301, sizeof(SubtargetFeatureKV) * 13 + 306, WebAssembly::FeatureFP16, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
83 { sizeof(SubtargetFeatureKV) * 12 + 331, sizeof(SubtargetFeatureKV) * 12 + 334, WebAssembly::FeatureGC, { { { 0x1000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
84 { sizeof(SubtargetFeatureKV) * 11 + 349, sizeof(SubtargetFeatureKV) * 11 + 361, WebAssembly::FeatureMultiMemory, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
85 { sizeof(SubtargetFeatureKV) * 10 + 386, sizeof(SubtargetFeatureKV) * 10 + 397, WebAssembly::FeatureMultivalue, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
86 { sizeof(SubtargetFeatureKV) * 9 + 451, sizeof(SubtargetFeatureKV) * 9 + 467, WebAssembly::FeatureMutableGlobals, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
87 { sizeof(SubtargetFeatureKV) * 8 + 490, sizeof(SubtargetFeatureKV) * 8 + 510, WebAssembly::FeatureNontrappingFPToInt, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
88 { sizeof(SubtargetFeatureKV) * 7 + 564, sizeof(SubtargetFeatureKV) * 7 + 580, WebAssembly::FeatureReferenceTypes, { { { 0x8ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
89 { sizeof(SubtargetFeatureKV) * 6 + 603, sizeof(SubtargetFeatureKV) * 6 + 619, WebAssembly::FeatureRelaxedAtomics, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
90 { sizeof(SubtargetFeatureKV) * 5 + 651, sizeof(SubtargetFeatureKV) * 5 + 664, WebAssembly::FeatureRelaxedSIMD, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
91 { sizeof(SubtargetFeatureKV) * 4 + 697, sizeof(SubtargetFeatureKV) * 4 + 706, WebAssembly::FeatureSignExt, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
92 { sizeof(SubtargetFeatureKV) * 3 + 738, sizeof(SubtargetFeatureKV) * 3 + 746, WebAssembly::FeatureSIMD128, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
93 { sizeof(SubtargetFeatureKV) * 2 + 766, sizeof(SubtargetFeatureKV) * 2 + 776, WebAssembly::FeatureTailCall, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
94 { sizeof(SubtargetFeatureKV) * 1 + 806, sizeof(SubtargetFeatureKV) * 1 + 822, WebAssembly::FeatureWideArithmetic, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
95 },
96 "\000atomics\000Enable Atomics\000bulk-memory\000Enable bulk memory oper"
97 "ations\000bulk-memory-opt\000Enable bulk memory optimization operations"
98 "\000call-indirect-overlong\000Enable overlong encoding for call_indirec"
99 "t immediates\000exception-handling\000Enable Wasm exception handling\000"
100 "extended-const\000Enable extended const expressions\000fp16\000Enable F"
101 "P16 instructions\000gc\000Enable wasm gc\000multimemory\000Enable multi"
102 "ple memories\000multivalue\000Enable multivalue blocks, instructions, a"
103 "nd functions\000mutable-globals\000Enable mutable globals\000nontrappin"
104 "g-fptoint\000Enable non-trapping float-to-int conversion operators\000r"
105 "eference-types\000Enable reference types\000relaxed-atomics\000Enable r"
106 "elaxed-atomics proposal\000relaxed-simd\000Enable relaxed-simd instruct"
107 "ions\000sign-ext\000Enable sign extension operators\000simd128\000Enabl"
108 "e 128-bit SIMD\000tail-call\000Enable tail call instructions\000wide-ar"
109 "ithmetic\000Enable wide-arithmetic instructions\000"};
110
111#ifdef DBGFIELD
112#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
113#endif
114#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
115#define DBGFIELD(x) x,
116#define DBGVAL_OR_NULLPTR(x) x
117#else
118#define DBGFIELD(x)
119#define DBGVAL_OR_NULLPTR(x) nullptr
120#endif
121
122// ===============================================================
123// Data tables for the new per-operand machine model.
124
125static_assert(0 <= UINT8_MAX, "NumWriteProcResEntries does not fit in uint8_t");
126static_assert(0 <= UINT8_MAX, "NumWriteLatencyEntries does not fit in uint8_t");
127
128// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}
129extern const llvm::MCWriteProcResEntry WebAssemblyWriteProcResTable[] = {
130 { 0, 0, 0 }, // Invalid
131}; // WebAssemblyWriteProcResTable
132
133// {Cycles, WriteResourceID}
134extern const llvm::MCWriteLatencyEntry WebAssemblyWriteLatencyTable[] = {
135 { 0, 0}, // Invalid
136}; // WebAssemblyWriteLatencyTable
137
138// {UseIdx, WriteResourceID, Cycles}
139extern const llvm::MCReadAdvanceEntry WebAssemblyReadAdvanceTable[] = {
140 {0, 0, 0}, // Invalid
141}; // WebAssemblyReadAdvanceTable
142
143#ifdef __GNUC__
144#pragma GCC diagnostic push
145#pragma GCC diagnostic ignored "-Woverlength-strings"
146#endif
147static constexpr char WebAssemblySchedClassNamesStorage[] =
148 "\0"
149 "InvalidSchedClass\0"
150 ;
151#ifdef __GNUC__
152#pragma GCC diagnostic pop
153#endif
154
155static constexpr llvm::StringTable
156WebAssemblySchedClassNames = WebAssemblySchedClassNamesStorage;
157
158extern const llvm::MCSchedModel WebAssemblySchedModels[] = {
159{ // NoSchedModel
160 MCSchedModel::DefaultIssueWidth,
161 MCSchedModel::DefaultMicroOpBufferSize,
162 MCSchedModel::DefaultLoopMicroOpBufferSize,
163 MCSchedModel::DefaultLoadLatency,
164 MCSchedModel::DefaultHighLatency,
165 MCSchedModel::DefaultMispredictPenalty,
166 false, // PostRAScheduler
167 false, // CompleteModel
168 false, // EnableIntervals
169 0, // Processor ID
170 nullptr, nullptr, 0, 0, // No instruction-level machine model.
171 DBGVAL_OR_NULLPTR(&WebAssemblySchedClassNames), // SchedClassNames
172 nullptr, // No Itinerary
173 nullptr // No extra processor descriptor
174 },
175};
176
177#undef DBGFIELD
178
179#undef DBGVAL_OR_NULLPTR
180
181static constexpr size_t WebAssemblyCPUAliasArraySize = sizeof(std::array<SubtargetSubTypeAliasKV, 0>);
182// Sorted (by key) array of values for CPU subtype.
183extern const llvm::SubtargetSubTypeKVStorage< 4, 0, 34> WebAssemblySubTypeKVStorage = {
184 {
185 { sizeof(SubtargetSubTypeKV) * 4 + WebAssemblyCPUAliasArraySize + 1, { { { 0x3dfffULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
186 { sizeof(SubtargetSubTypeKV) * 3 + WebAssemblyCPUAliasArraySize + 15, { { { 0x11e0eULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
187 { sizeof(SubtargetSubTypeKV) * 2 + WebAssemblyCPUAliasArraySize + 23, { { { 0x10e2cULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
188 { sizeof(SubtargetSubTypeKV) * 1 + WebAssemblyCPUAliasArraySize + 29, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
189 },
190 { {
191 } },
192 "\000bleeding-edge\000generic\000lime1\000mvp\000"};
193
194namespace WebAssembly_MC {
195
196unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
197 const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID) {
198 // Don't know how to resolve this scheduling class.
199 return 0;
200}
201
202} // namespace WebAssembly_MC
203struct WebAssemblyGenMCSubtargetInfo : public MCSubtargetInfo {
204 WebAssemblyGenMCSubtargetInfo(const Triple &TT,
205 StringRef CPU, StringRef TuneCPU, StringRef FS,
206 StringTable PN,
207 ArrayRef<SubtargetFeatureKV> PF,
208 ArrayRef<SubtargetSubTypeKV> PD,
209 ArrayRef<SubtargetSubTypeAliasKV> PA,
210 const MCSchedModel *PSM,
211 const MCWriteProcResEntry *WPR,
212 const MCWriteLatencyEntry *WL,
213 const MCReadAdvanceEntry *RA, const InstrStage *IS,
214 const unsigned *OC, const unsigned *FP) :
215 MCSubtargetInfo(TT, CPU, TuneCPU, FS, PN, PF, PD, PA, PSM,
216 WPR, WL, RA, IS, OC, FP) { }
217
218 unsigned resolveVariantSchedClass(unsigned SchedClass,
219 const MCInst *MI, const MCInstrInfo *MCII,
220 unsigned CPUID) const final {
221 return WebAssembly_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
222 }
223 unsigned getHwModeSet() const final;
224 unsigned getHwMode(enum HwModeType type = HwMode_Default) const final;
225};
226unsigned WebAssemblyGenMCSubtargetInfo::getHwModeSet() const {
227 [[maybe_unused]] const FeatureBitset &FB = getFeatureBits();
228 // Collect HwModes and store them as a bit set.
229 unsigned Modes = 0;
230 if (false) Modes |= (1 << 0);
231 return Modes;
232}
233unsigned WebAssemblyGenMCSubtargetInfo::getHwMode(enum HwModeType type) const {
234 unsigned Modes = getHwModeSet();
235
236 if (!Modes)
237 return Modes;
238
239 switch (type) {
240 case HwMode_Default:
241 return llvm::countr_zero(Modes) + 1;
242 case HwMode_ValueType:
243 // No HwMode for ValueType.
244 return 0;
245 case HwMode_RegInfo:
246 Modes &= 1;
247 if (!Modes)
248 return Modes;
249 if (!llvm::has_single_bit<unsigned>(Modes))
250 llvm_unreachable("Two or more HwModes for RegInfo were found!");
251 return llvm::countr_zero(Modes) + 1;
252 case HwMode_EncodingInfo:
253 // No HwMode for EncodingInfo.
254 return 0;
255 }
256 llvm_unreachable("unexpected HwModeType");
257 return 0; // should not get here
258}
259
260static inline MCSubtargetInfo *createWebAssemblyMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
261 return new WebAssemblyGenMCSubtargetInfo(TT, CPU, TuneCPU, FS, StringTable(WebAssemblySubTypeKVStorage.Strings), WebAssemblyFeatureKVStorage.Features, WebAssemblySubTypeKVStorage.SubTypes, ArrayRef(WebAssemblySubTypeKVStorage.Aliases).take_front(0), WebAssemblySchedModels,
262 WebAssemblyWriteProcResTable, WebAssemblyWriteLatencyTable, WebAssemblyReadAdvanceTable,
263 nullptr, nullptr, nullptr);
264}
265
266
267} // namespace llvm
268
269#endif // GET_SUBTARGETINFO_MC_DESC
270
271#ifdef GET_SUBTARGETINFO_TARGET_DESC
272#undef GET_SUBTARGETINFO_TARGET_DESC
273
274#include "llvm/ADT/BitmaskEnum.h"
275#include "llvm/Support/Debug.h"
276#include "llvm/Support/raw_ostream.h"
277
278// ParseSubtargetFeatures - Parses features string setting specified
279// subtarget options.
280void llvm::WebAssemblySubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
281 LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
282 LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
283 LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
284 InitMCProcessorInfo(CPU, TuneCPU, FS);
285 const FeatureBitset &Bits = getFeatureBits();
286 if (Bits[WebAssembly::FeatureAtomics]) HasAtomics = true;
287 if (Bits[WebAssembly::FeatureBulkMemory]) HasBulkMemory = true;
288 if (Bits[WebAssembly::FeatureBulkMemoryOpt]) HasBulkMemoryOpt = true;
289 if (Bits[WebAssembly::FeatureCallIndirectOverlong]) HasCallIndirectOverlong = true;
290 if (Bits[WebAssembly::FeatureExceptionHandling]) HasExceptionHandling = true;
291 if (Bits[WebAssembly::FeatureExtendedConst]) HasExtendedConst = true;
292 if (Bits[WebAssembly::FeatureFP16]) HasFP16 = true;
293 if (Bits[WebAssembly::FeatureGC]) HasGC = true;
294 if (Bits[WebAssembly::FeatureMultiMemory]) HasMultiMemory = true;
295 if (Bits[WebAssembly::FeatureMultivalue]) HasMultivalue = true;
296 if (Bits[WebAssembly::FeatureMutableGlobals]) HasMutableGlobals = true;
297 if (Bits[WebAssembly::FeatureNontrappingFPToInt]) HasNontrappingFPToInt = true;
298 if (Bits[WebAssembly::FeatureReferenceTypes]) HasReferenceTypes = true;
299 if (Bits[WebAssembly::FeatureRelaxedAtomics]) HasRelaxedAtomics = true;
300 if (Bits[WebAssembly::FeatureRelaxedSIMD] && SIMDLevel < RelaxedSIMD) SIMDLevel = RelaxedSIMD;
301 if (Bits[WebAssembly::FeatureSIMD128] && SIMDLevel < SIMD128) SIMDLevel = SIMD128;
302 if (Bits[WebAssembly::FeatureSignExt]) HasSignExt = true;
303 if (Bits[WebAssembly::FeatureTailCall]) HasTailCall = true;
304 if (Bits[WebAssembly::FeatureWideArithmetic]) HasWideArithmetic = true;
305}
306
307#endif // GET_SUBTARGETINFO_TARGET_DESC
308
309#ifdef GET_SUBTARGETINFO_HEADER
310#undef GET_SUBTARGETINFO_HEADER
311
312namespace llvm {
313
314class DFAPacketizer;
315namespace WebAssembly_MC {
316
317unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID);
318
319} // namespace WebAssembly_MC
320struct WebAssemblyGenSubtargetInfo : public TargetSubtargetInfo {
321 explicit WebAssemblyGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
322public:
323 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const final;
324 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const final;
325 DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
326 enum class WebAssemblyHwModeBits : unsigned {
327 DefaultMode = 0,
328 WASM64 = (1 << 0),
329
330 LLVM_MARK_AS_BITMASK_ENUM(/*LargestValue=*/WASM64),
331 };
332 unsigned getHwModeSet() const final;
333 unsigned getHwMode(enum HwModeType type = HwMode_Default) const final;
334 const FeatureBitset &getInlineIgnoreFeatures() const override;
335 const FeatureBitset &getInlineInverseFeatures() const override;
336 const FeatureBitset &getInlineMustMatchFeatures() const override;
337};
338
339} // namespace llvm
340
341#endif // GET_SUBTARGETINFO_HEADER
342
343#ifdef GET_SUBTARGETINFO_CTOR
344#undef GET_SUBTARGETINFO_CTOR
345
346#include "llvm/CodeGen/TargetSchedule.h"
347
348namespace llvm {
349
350extern const llvm::StringRef WebAssemblyNames[];
351extern const llvm::SubtargetFeatureKVStorage<19, 859> WebAssemblyFeatureKVStorage;
352extern const llvm::SubtargetSubTypeKVStorage<4, 0, 34> WebAssemblySubTypeKVStorage;
353extern const llvm::MCSchedModel WebAssemblySchedModels[];
354extern const llvm::MCWriteProcResEntry WebAssemblyWriteProcResTable[];
355extern const llvm::MCWriteLatencyEntry WebAssemblyWriteLatencyTable[];
356extern const llvm::MCReadAdvanceEntry WebAssemblyReadAdvanceTable[];
357WebAssemblyGenSubtargetInfo::WebAssemblyGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
358 : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, StringTable(WebAssemblySubTypeKVStorage.Strings), ArrayRef(WebAssemblyFeatureKVStorage.Features), ArrayRef(WebAssemblySubTypeKVStorage.SubTypes), ArrayRef(WebAssemblySubTypeKVStorage.Aliases).take_front(0), WebAssemblySchedModels,
359 WebAssemblyWriteProcResTable, WebAssemblyWriteLatencyTable, WebAssemblyReadAdvanceTable,
360 nullptr, nullptr, nullptr) {}
361
362unsigned WebAssemblyGenSubtargetInfo
363::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
364 report_fatal_error("Expected a variant SchedClass");
365} // WebAssemblyGenSubtargetInfo::resolveSchedClass
366
367unsigned WebAssemblyGenSubtargetInfo
368::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {
369 return WebAssembly_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
370} // WebAssemblyGenSubtargetInfo::resolveVariantSchedClass
371
372unsigned WebAssemblyGenSubtargetInfo::getHwModeSet() const {
373 [[maybe_unused]] const auto *Subtarget =
374 static_cast<const WebAssemblySubtarget *>(this);
375 // Collect HwModes and store them as a bit set.
376 unsigned Modes = 0;
377 if ((Subtarget->hasAddr64())) Modes |= (1 << 0);
378 return Modes;
379}
380unsigned WebAssemblyGenSubtargetInfo::getHwMode(enum HwModeType type) const {
381 unsigned Modes = getHwModeSet();
382
383 if (!Modes)
384 return Modes;
385
386 switch (type) {
387 case HwMode_Default:
388 return llvm::countr_zero(Modes) + 1;
389 case HwMode_ValueType:
390 // No HwMode for ValueType.
391 return 0;
392 case HwMode_RegInfo:
393 Modes &= 1;
394 if (!Modes)
395 return Modes;
396 if (!llvm::has_single_bit<unsigned>(Modes))
397 llvm_unreachable("Two or more HwModes for RegInfo were found!");
398 return llvm::countr_zero(Modes) + 1;
399 case HwMode_EncodingInfo:
400 // No HwMode for EncodingInfo.
401 return 0;
402 }
403 llvm_unreachable("unexpected HwModeType");
404 return 0; // should not get here
405}
406const FeatureBitset &WebAssemblyGenSubtargetInfo::getInlineIgnoreFeatures() const {
407 static constexpr FeatureBitset Features = {
408 };
409 return Features;
410}
411
412const FeatureBitset &WebAssemblyGenSubtargetInfo::getInlineInverseFeatures() const {
413 static constexpr FeatureBitset Features = {
414 };
415 return Features;
416}
417
418const FeatureBitset &WebAssemblyGenSubtargetInfo::getInlineMustMatchFeatures() const {
419 static constexpr FeatureBitset Features = {
420 };
421 return Features;
422}
423
424
425} // namespace llvm
426
427#endif // GET_SUBTARGETINFO_CTOR
428
429#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
430#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
431
432
433#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
434
435#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
436#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
437
438
439#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
440
441