1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Subtarget Enumeration Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_SUBTARGETINFO_ENUM
10#undef GET_SUBTARGETINFO_ENUM
11
12namespace llvm {
13
14namespace WebAssembly {
15
16enum {
17 FeatureAtomics = 0,
18 FeatureBulkMemory = 1,
19 FeatureBulkMemoryOpt = 2,
20 FeatureCallIndirectOverlong = 3,
21 FeatureExceptionHandling = 4,
22 FeatureExtendedConst = 5,
23 FeatureFP16 = 6,
24 FeatureGC = 7,
25 FeatureMultiMemory = 8,
26 FeatureMultivalue = 9,
27 FeatureMutableGlobals = 10,
28 FeatureNontrappingFPToInt = 11,
29 FeatureReferenceTypes = 12,
30 FeatureRelaxedSIMD = 13,
31 FeatureSIMD128 = 14,
32 FeatureSignExt = 15,
33 FeatureTailCall = 16,
34 FeatureWideArithmetic = 17,
35 NumSubtargetFeatures = 18
36};
37
38} // namespace WebAssembly
39
40} // namespace llvm
41
42#endif // GET_SUBTARGETINFO_ENUM
43
44#ifdef GET_SUBTARGETINFO_MACRO
45
46GET_SUBTARGETINFO_MACRO(HasAtomics, false, hasAtomics)
47GET_SUBTARGETINFO_MACRO(HasBulkMemory, false, hasBulkMemory)
48GET_SUBTARGETINFO_MACRO(HasBulkMemoryOpt, false, hasBulkMemoryOpt)
49GET_SUBTARGETINFO_MACRO(HasCallIndirectOverlong, false, hasCallIndirectOverlong)
50GET_SUBTARGETINFO_MACRO(HasExceptionHandling, false, hasExceptionHandling)
51GET_SUBTARGETINFO_MACRO(HasExtendedConst, false, hasExtendedConst)
52GET_SUBTARGETINFO_MACRO(HasFP16, false, hasFP16)
53GET_SUBTARGETINFO_MACRO(HasGC, false, hasGC)
54GET_SUBTARGETINFO_MACRO(HasMultiMemory, false, hasMultiMemory)
55GET_SUBTARGETINFO_MACRO(HasMultivalue, false, hasMultivalue)
56GET_SUBTARGETINFO_MACRO(HasMutableGlobals, false, hasMutableGlobals)
57GET_SUBTARGETINFO_MACRO(HasNontrappingFPToInt, false, hasNontrappingFPToInt)
58GET_SUBTARGETINFO_MACRO(HasReferenceTypes, false, hasReferenceTypes)
59GET_SUBTARGETINFO_MACRO(HasSignExt, false, hasSignExt)
60GET_SUBTARGETINFO_MACRO(HasTailCall, false, hasTailCall)
61GET_SUBTARGETINFO_MACRO(HasWideArithmetic, false, hasWideArithmetic)
62
63#undef GET_SUBTARGETINFO_MACRO
64#endif // GET_SUBTARGETINFO_MACRO
65
66#ifdef GET_SUBTARGETINFO_MC_DESC
67#undef GET_SUBTARGETINFO_MC_DESC
68
69namespace llvm {
70
71// Sorted (by key) array of values for CPU features.
72extern const llvm::SubtargetFeatureKV WebAssemblyFeatureKV[] = {
73 { "atomics", "Enable Atomics", WebAssembly::FeatureAtomics, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
74 { "bulk-memory", "Enable bulk memory operations", WebAssembly::FeatureBulkMemory, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
75 { "bulk-memory-opt", "Enable bulk memory optimization operations", WebAssembly::FeatureBulkMemoryOpt, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
76 { "call-indirect-overlong", "Enable overlong encoding for call_indirect immediates", WebAssembly::FeatureCallIndirectOverlong, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
77 { "exception-handling", "Enable Wasm exception handling", WebAssembly::FeatureExceptionHandling, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
78 { "extended-const", "Enable extended const expressions", WebAssembly::FeatureExtendedConst, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
79 { "fp16", "Enable FP16 instructions", WebAssembly::FeatureFP16, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
80 { "gc", "Enable wasm gc", WebAssembly::FeatureGC, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
81 { "multimemory", "Enable multiple memories", WebAssembly::FeatureMultiMemory, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
82 { "multivalue", "Enable multivalue blocks, instructions, and functions", WebAssembly::FeatureMultivalue, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
83 { "mutable-globals", "Enable mutable globals", WebAssembly::FeatureMutableGlobals, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
84 { "nontrapping-fptoint", "Enable non-trapping float-to-int conversion operators", WebAssembly::FeatureNontrappingFPToInt, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
85 { "reference-types", "Enable reference types", WebAssembly::FeatureReferenceTypes, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
86 { "relaxed-simd", "Enable relaxed-simd instructions", WebAssembly::FeatureRelaxedSIMD, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
87 { "sign-ext", "Enable sign extension operators", WebAssembly::FeatureSignExt, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
88 { "simd128", "Enable 128-bit SIMD", WebAssembly::FeatureSIMD128, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
89 { "tail-call", "Enable tail call instructions", WebAssembly::FeatureTailCall, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
90 { "wide-arithmetic", "Enable wide-arithmetic instructions", WebAssembly::FeatureWideArithmetic, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
91};
92
93#ifdef DBGFIELD
94#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
95#endif
96#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
97#define DBGFIELD(x) x,
98#define DBGVAL_OR_NULLPTR(x) x
99#else
100#define DBGFIELD(x)
101#define DBGVAL_OR_NULLPTR(x) nullptr
102#endif
103
104// ===============================================================
105// Data tables for the new per-operand machine model.
106
107// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}
108extern const llvm::MCWriteProcResEntry WebAssemblyWriteProcResTable[] = {
109 { 0, 0, 0 }, // Invalid
110}; // WebAssemblyWriteProcResTable
111
112// {Cycles, WriteResourceID}
113extern const llvm::MCWriteLatencyEntry WebAssemblyWriteLatencyTable[] = {
114 { 0, 0}, // Invalid
115}; // WebAssemblyWriteLatencyTable
116
117// {UseIdx, WriteResourceID, Cycles}
118extern const llvm::MCReadAdvanceEntry WebAssemblyReadAdvanceTable[] = {
119 {0, 0, 0}, // Invalid
120}; // WebAssemblyReadAdvanceTable
121
122#ifdef __GNUC__
123#pragma GCC diagnostic push
124#pragma GCC diagnostic ignored "-Woverlength-strings"
125#endif
126static constexpr char WebAssemblySchedClassNamesStorage[] =
127 "\0"
128 "InvalidSchedClass\0"
129 ;
130#ifdef __GNUC__
131#pragma GCC diagnostic pop
132#endif
133
134static constexpr llvm::StringTable
135WebAssemblySchedClassNames = WebAssemblySchedClassNamesStorage;
136
137static const llvm::MCSchedModel NoSchedModel = {
138 MCSchedModel::DefaultIssueWidth,
139 MCSchedModel::DefaultMicroOpBufferSize,
140 MCSchedModel::DefaultLoopMicroOpBufferSize,
141 MCSchedModel::DefaultLoadLatency,
142 MCSchedModel::DefaultHighLatency,
143 MCSchedModel::DefaultMispredictPenalty,
144 false, // PostRAScheduler
145 false, // CompleteModel
146 false, // EnableIntervals
147 0, // Processor ID
148 nullptr, nullptr, 0, 0, // No instruction-level machine model.
149 DBGVAL_OR_NULLPTR(&WebAssemblySchedClassNames), // SchedClassNames
150 nullptr, // No Itinerary
151 nullptr // No extra processor descriptor
152};
153
154#undef DBGFIELD
155
156#undef DBGVAL_OR_NULLPTR
157
158// Sorted (by key) array of values for CPU subtype.
159extern const llvm::SubtargetSubTypeKV WebAssemblySubTypeKV[] = {
160 { "bleeding-edge", { { { 0x1ffffULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
161 { "generic", { { { 0x9e0eULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
162 { "lime1", { { { 0x8e2cULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
163 { "mvp", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
164};
165
166// Sorted array of names of CPU subtypes, including aliases.
167extern const llvm::StringRef WebAssemblyNames[] = {
168"bleeding-edge",
169"generic",
170"lime1",
171"mvp"};
172
173namespace WebAssembly_MC {
174
175unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
176 const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID) {
177 // Don't know how to resolve this scheduling class.
178 return 0;
179}
180
181} // namespace WebAssembly_MC
182struct WebAssemblyGenMCSubtargetInfo : public MCSubtargetInfo {
183 WebAssemblyGenMCSubtargetInfo(const Triple &TT,
184 StringRef CPU, StringRef TuneCPU, StringRef FS,
185 ArrayRef<StringRef> PN,
186 ArrayRef<SubtargetFeatureKV> PF,
187 ArrayRef<SubtargetSubTypeKV> PD,
188 const MCWriteProcResEntry *WPR,
189 const MCWriteLatencyEntry *WL,
190 const MCReadAdvanceEntry *RA, const InstrStage *IS,
191 const unsigned *OC, const unsigned *FP) :
192 MCSubtargetInfo(TT, CPU, TuneCPU, FS, PN, PF, PD,
193 WPR, WL, RA, IS, OC, FP) { }
194
195 unsigned resolveVariantSchedClass(unsigned SchedClass,
196 const MCInst *MI, const MCInstrInfo *MCII,
197 unsigned CPUID) const final {
198 return WebAssembly_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
199 }
200 unsigned getHwModeSet() const final;
201 unsigned getHwMode(enum HwModeType type = HwMode_Default) const final;
202};
203unsigned WebAssemblyGenMCSubtargetInfo::getHwModeSet() const {
204 [[maybe_unused]] const FeatureBitset &FB = getFeatureBits();
205 // Collect HwModes and store them as a bit set.
206 unsigned Modes = 0;
207 if (false) Modes |= (1 << 0);
208 return Modes;
209}
210unsigned WebAssemblyGenMCSubtargetInfo::getHwMode(enum HwModeType type) const {
211 unsigned Modes = getHwModeSet();
212
213 if (!Modes)
214 return Modes;
215
216 switch (type) {
217 case HwMode_Default:
218 return llvm::countr_zero(Modes) + 1;
219 case HwMode_ValueType:
220 Modes &= 0;
221 if (!Modes)
222 return Modes;
223 if (!llvm::has_single_bit<unsigned>(Modes))
224 llvm_unreachable("Two or more HwModes for ValueType were found!");
225 return llvm::countr_zero(Modes) + 1;
226 case HwMode_RegInfo:
227 Modes &= 1;
228 if (!Modes)
229 return Modes;
230 if (!llvm::has_single_bit<unsigned>(Modes))
231 llvm_unreachable("Two or more HwModes for RegInfo were found!");
232 return llvm::countr_zero(Modes) + 1;
233 case HwMode_EncodingInfo:
234 Modes &= 0;
235 if (!Modes)
236 return Modes;
237 if (!llvm::has_single_bit<unsigned>(Modes))
238 llvm_unreachable("Two or more HwModes for EncodingInfo were found!");
239 return llvm::countr_zero(Modes) + 1;
240 }
241 llvm_unreachable("unexpected HwModeType");
242 return 0; // should not get here
243}
244
245static inline MCSubtargetInfo *createWebAssemblyMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
246 return new WebAssemblyGenMCSubtargetInfo(TT, CPU, TuneCPU, FS, WebAssemblyNames, WebAssemblyFeatureKV, WebAssemblySubTypeKV,
247 WebAssemblyWriteProcResTable, WebAssemblyWriteLatencyTable, WebAssemblyReadAdvanceTable,
248 nullptr, nullptr, nullptr);
249}
250
251
252} // namespace llvm
253
254#endif // GET_SUBTARGETINFO_MC_DESC
255
256#ifdef GET_SUBTARGETINFO_TARGET_DESC
257#undef GET_SUBTARGETINFO_TARGET_DESC
258
259#include "llvm/ADT/BitmaskEnum.h"
260#include "llvm/Support/Debug.h"
261#include "llvm/Support/raw_ostream.h"
262
263// ParseSubtargetFeatures - Parses features string setting specified
264// subtarget options.
265void llvm::WebAssemblySubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
266 LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
267 LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
268 LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
269 InitMCProcessorInfo(CPU, TuneCPU, FS);
270 const FeatureBitset &Bits = getFeatureBits();
271 if (Bits[WebAssembly::FeatureAtomics]) HasAtomics = true;
272 if (Bits[WebAssembly::FeatureBulkMemory]) HasBulkMemory = true;
273 if (Bits[WebAssembly::FeatureBulkMemoryOpt]) HasBulkMemoryOpt = true;
274 if (Bits[WebAssembly::FeatureCallIndirectOverlong]) HasCallIndirectOverlong = true;
275 if (Bits[WebAssembly::FeatureExceptionHandling]) HasExceptionHandling = true;
276 if (Bits[WebAssembly::FeatureExtendedConst]) HasExtendedConst = true;
277 if (Bits[WebAssembly::FeatureFP16]) HasFP16 = true;
278 if (Bits[WebAssembly::FeatureGC]) HasGC = true;
279 if (Bits[WebAssembly::FeatureMultiMemory]) HasMultiMemory = true;
280 if (Bits[WebAssembly::FeatureMultivalue]) HasMultivalue = true;
281 if (Bits[WebAssembly::FeatureMutableGlobals]) HasMutableGlobals = true;
282 if (Bits[WebAssembly::FeatureNontrappingFPToInt]) HasNontrappingFPToInt = true;
283 if (Bits[WebAssembly::FeatureReferenceTypes]) HasReferenceTypes = true;
284 if (Bits[WebAssembly::FeatureRelaxedSIMD] && SIMDLevel < RelaxedSIMD) SIMDLevel = RelaxedSIMD;
285 if (Bits[WebAssembly::FeatureSIMD128] && SIMDLevel < SIMD128) SIMDLevel = SIMD128;
286 if (Bits[WebAssembly::FeatureSignExt]) HasSignExt = true;
287 if (Bits[WebAssembly::FeatureTailCall]) HasTailCall = true;
288 if (Bits[WebAssembly::FeatureWideArithmetic]) HasWideArithmetic = true;
289}
290
291#endif // GET_SUBTARGETINFO_TARGET_DESC
292
293#ifdef GET_SUBTARGETINFO_HEADER
294#undef GET_SUBTARGETINFO_HEADER
295
296namespace llvm {
297
298class DFAPacketizer;
299namespace WebAssembly_MC {
300
301unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID);
302
303} // namespace WebAssembly_MC
304struct WebAssemblyGenSubtargetInfo : public TargetSubtargetInfo {
305 explicit WebAssemblyGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
306public:
307 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const final;
308 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const final;
309 DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
310 enum class WebAssemblyHwModeBits : unsigned {
311 DefaultMode = 0,
312 WASM64 = (1 << 0),
313
314 LLVM_MARK_AS_BITMASK_ENUM(/*LargestValue=*/WASM64),
315 };
316 unsigned getHwModeSet() const final;
317 unsigned getHwMode(enum HwModeType type = HwMode_Default) const final;
318};
319
320} // namespace llvm
321
322#endif // GET_SUBTARGETINFO_HEADER
323
324#ifdef GET_SUBTARGETINFO_CTOR
325#undef GET_SUBTARGETINFO_CTOR
326
327#include "llvm/CodeGen/TargetSchedule.h"
328
329namespace llvm {
330
331extern const llvm::StringRef WebAssemblyNames[];
332extern const llvm::SubtargetFeatureKV WebAssemblyFeatureKV[];
333extern const llvm::SubtargetSubTypeKV WebAssemblySubTypeKV[];
334extern const llvm::MCWriteProcResEntry WebAssemblyWriteProcResTable[];
335extern const llvm::MCWriteLatencyEntry WebAssemblyWriteLatencyTable[];
336extern const llvm::MCReadAdvanceEntry WebAssemblyReadAdvanceTable[];
337WebAssemblyGenSubtargetInfo::WebAssemblyGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
338 : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, ArrayRef(WebAssemblyNames, 4), ArrayRef(WebAssemblyFeatureKV, 18), ArrayRef(WebAssemblySubTypeKV, 4),
339 WebAssemblyWriteProcResTable, WebAssemblyWriteLatencyTable, WebAssemblyReadAdvanceTable,
340 nullptr, nullptr, nullptr) {}
341
342unsigned WebAssemblyGenSubtargetInfo
343::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
344 report_fatal_error("Expected a variant SchedClass");
345} // WebAssemblyGenSubtargetInfo::resolveSchedClass
346
347unsigned WebAssemblyGenSubtargetInfo
348::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {
349 return WebAssembly_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
350} // WebAssemblyGenSubtargetInfo::resolveVariantSchedClass
351
352unsigned WebAssemblyGenSubtargetInfo::getHwModeSet() const {
353 [[maybe_unused]] const auto *Subtarget =
354 static_cast<const WebAssemblySubtarget *>(this);
355 // Collect HwModes and store them as a bit set.
356 unsigned Modes = 0;
357 if ((Subtarget->hasAddr64())) Modes |= (1 << 0);
358 return Modes;
359}
360unsigned WebAssemblyGenSubtargetInfo::getHwMode(enum HwModeType type) const {
361 unsigned Modes = getHwModeSet();
362
363 if (!Modes)
364 return Modes;
365
366 switch (type) {
367 case HwMode_Default:
368 return llvm::countr_zero(Modes) + 1;
369 case HwMode_ValueType:
370 Modes &= 0;
371 if (!Modes)
372 return Modes;
373 if (!llvm::has_single_bit<unsigned>(Modes))
374 llvm_unreachable("Two or more HwModes for ValueType were found!");
375 return llvm::countr_zero(Modes) + 1;
376 case HwMode_RegInfo:
377 Modes &= 1;
378 if (!Modes)
379 return Modes;
380 if (!llvm::has_single_bit<unsigned>(Modes))
381 llvm_unreachable("Two or more HwModes for RegInfo were found!");
382 return llvm::countr_zero(Modes) + 1;
383 case HwMode_EncodingInfo:
384 Modes &= 0;
385 if (!Modes)
386 return Modes;
387 if (!llvm::has_single_bit<unsigned>(Modes))
388 llvm_unreachable("Two or more HwModes for EncodingInfo were found!");
389 return llvm::countr_zero(Modes) + 1;
390 }
391 llvm_unreachable("unexpected HwModeType");
392 return 0; // should not get here
393}
394
395} // namespace llvm
396
397#endif // GET_SUBTARGETINFO_CTOR
398
399#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
400#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
401
402
403#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
404
405#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
406#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
407
408
409#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
410
411